diff -u src.orig/radeon.h src/radeon.h --- src.orig/radeon.h 2007-09-18 04:26:45.000000000 +0100 +++ src/radeon.h 2007-09-18 04:27:11.000000000 +0100 @@ -286,7 +286,7 @@ unsigned ppll_ref_div; unsigned ppll_div_3; CARD32 htotal_cntl; - CARD32 vclk_ecp_cntl; + CARD32 vclk_cntl; /* Computed values for PLL2 */ CARD32 dot_clock_freq_2; diff -u src.orig/radeon_crtc.c src/radeon_crtc.c --- src.orig/radeon_crtc.c 2007-09-18 04:26:45.000000000 +0100 +++ src/radeon_crtc.c 2007-09-18 04:27:11.000000000 +0100 @@ -683,7 +683,7 @@ save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); save->htotal_cntl = 0; - save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & + save->vclk_cntl = (info->SavedReg.vclk_cntl & ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; } diff -u src.orig/radeon_driver.c src/radeon_driver.c --- src.orig/radeon_driver.c 2007-09-18 04:26:45.000000000 +0100 +++ src/radeon_driver.c 2007-09-18 04:27:12.000000000 +0100 @@ -4664,10 +4664,9 @@ usleep(50000); /* Let the clock to lock */ - /* OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, + OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, RADEON_VCLK_SRC_SEL_PPLLCLK, - ~(RADEON_VCLK_SRC_SEL_MASK));*/ - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl); + ~(RADEON_VCLK_SRC_SEL_MASK)); ErrorF("finished PLL1\n"); @@ -4738,10 +4737,9 @@ usleep(5000); /* Let the clock to lock */ - /*OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, + OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, - ~(RADEON_PIX2CLK_SRC_SEL_MASK));*/ - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); + ~(RADEON_PIX2CLK_SRC_SEL_MASK)); ErrorF("finished PLL2\n"); @@ -5184,7 +5182,7 @@ save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); - save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + save->vclk_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Read: 0x%08x 0x%08x 0x%08x\n",