[ 3128.576135] [drm:drm_ioctl] pid=3002, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
[ 3128.576141] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
[ 3128.576150] [drm:drm_mode_setcrtc] [CONNECTOR:47:DP-2]
[ 3128.576162] [drm:drm_atomic_state_init] Allocated atomic state ffff8800712d8008
[ 3128.576168] [drm:drm_mode_object_reference] OBJ ID: 103 (2)
[ 3128.576171] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff8800712db7e8 state to ffff8800712d8008
[ 3128.576177] [drm:drm_atomic_get_plane_state] Added [PLANE:23:primary A] ffff88007c1c8a58 state to ffff8800712d8008
[ 3128.576183] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x2160] for CRTC state ffff8800712db7e8
[ 3128.576185] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88007c1c8a58 to [CRTC:26:pipe A]
[ 3128.576188] [drm:drm_mode_object_reference] OBJ ID: 105 (2)
[ 3128.576193] [drm:drm_atomic_set_fb_for_plane] Set [FB:105] for plane state ffff88007c1c8a58
[ 3128.576195] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8800712d8008
[ 3128.576204] [drm:drm_mode_object_reference] OBJ ID: 47 (3)
[ 3128.576206] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:47] ffff880107c802e8 state to ffff8800712d8008
[ 3128.576207] [drm:drm_mode_object_reference] OBJ ID: 47 (4)
[ 3128.576212] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880107c802e8 to [CRTC:26:pipe A]
[ 3128.576216] [drm:drm_atomic_check_only] checking ffff8800712d8008
[ 3128.576219] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] mode changed
[ 3128.576220] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] enable changed
[ 3128.576222] [drm:update_connector_routing] Updating routing for [CONNECTOR:47:DP-2]
[ 3128.576224] [drm:update_connector_routing] [CONNECTOR:47:DP-2] using [ENCODER:43:DP-MST A] on [CRTC:26:pipe A]
[ 3128.576225] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
[ 3128.576227] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
[ 3128.576229] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8800712d8008
[ 3128.576231] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff8800712d8008
[ 3128.576233] [drm:connected_sink_compute_bpp] [CONNECTOR:47:DP-2] checking for sink bpp constrains
[ 3128.576234] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 30
[ 3128.576236] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[ 3128.576238] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
[ 3128.576240] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_htotal (expected 0, found 2080)
[ 3128.576241] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
[ 3128.576242] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_hblank_end (expected 0, found 2080)
[ 3128.576244] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_hsync_start (expected 0, found 1968)
[ 3128.576248] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_hsync_end (expected 0, found 2000)
[ 3128.576253] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vdisplay (expected 0, found 2160)
[ 3128.576258] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vtotal (expected 0, found 2222)
[ 3128.576263] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vblank_start (expected 0, found 2160)
[ 3128.576268] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vblank_end (expected 0, found 2222)
[ 3128.576271] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vsync_start (expected 0, found 2163)
[ 3128.576273] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_vsync_end (expected 0, found 2173)
[ 3128.576274] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PHSYNC) (expected 0, found 1)
[ 3128.576276] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NVSYNC) (expected 0, found 8)
[ 3128.576278] [drm:intel_pipe_config_compare] mismatch in base.adjusted_mode.crtc_clock (expected 0, found 277250)
[ 3128.576279] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff8800712db7e8 for pipe A
[ 3128.576281] [drm:intel_dump_pipe_config] cpu_transcoder: A
[ 3128.576282] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[ 3128.576285] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3128.576287] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 3230196, gmch_n: 8388608, link_m: 538366, link_n: 1048576, tu: 25
[ 3128.576289] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 3128.576290] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 3128.576291] [drm:intel_dump_pipe_config] requested mode:
[ 3128.576294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x2160" 60 277250 1920 1968 2000 2080 2160 2163 2173 2222 0x48 0x9
[ 3128.576295] [drm:intel_dump_pipe_config] adjusted mode:
[ 3128.576298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x2160" 60 277250 1920 1968 2000 2080 2160 2163 2173 2222 0x48 0x9
[ 3128.576300] [drm:intel_dump_crtc_timings] crtc timings: 277250 1920 1968 2000 2080 2160 2163 2173 2222, type: 0x48 flags: 0x9
[ 3128.576302] [drm:intel_dump_pipe_config] port clock: 540000
[ 3128.576303] [drm:intel_dump_pipe_config] pipe src size: 1920x2160
[ 3128.576305] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
[ 3128.576306] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 3128.576308] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 3128.576310] [drm:intel_dump_pipe_config] ips: 1
[ 3128.576311] [drm:intel_dump_pipe_config] double wide: 0
[ 3128.576312] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x0; dpll_hw_state: wrpll: 0x0 spll: 0x0
[ 3128.576313] [drm:intel_dump_pipe_config] planes on this crtc
[ 3128.576315] [drm:intel_dump_pipe_config] [PLANE:23:primary A] disabled, scaler_id = 0
[ 3128.576317] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = 0
[ 3128.576322] [drm:intel_dump_pipe_config] [PLANE:27:sprite A] disabled, scaler_id = 0
[ 3128.576329] [drm:intel_modeset_checks] New cdclk calculated to be atomic 337500, actual 337500
[ 3128.576334] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:primary A] with fb 105
[ 3128.576340] [drm:intel_plane_atomic_calc_changes] [PLANE:23:primary A] visible 0 -> 1, off 0, on 1, ms 1
[ 3128.576345] [drm:intel_reference_shared_dpll] using LCPLL 2700 for pipe A
[ 3128.576350] [drm:drm_atomic_commit] commiting ffff8800712d8008
[ 3128.577975] [drm:drm_calc_timestamping_constants] crtc 26: hwmode: htotal 2080, vtotal 2222, vdisplay 2160
[ 3128.577976] [drm:drm_calc_timestamping_constants] crtc 26: clock 277250 kHz framedur 16670009 linedur 7502
[ 3128.577978] [drm:verify_encoder_state] [ENCODER:36:DDI B]
[ 3128.577979] [drm:verify_encoder_state] [ENCODER:41:DDI C]
[ 3128.577980] [drm:verify_encoder_state] [ENCODER:43:DP-MST A]
[ 3128.577981] [drm:verify_encoder_state] [ENCODER:44:DP-MST B]
[ 3128.577982] [drm:verify_encoder_state] [ENCODER:45:DP-MST C]
[ 3128.577983] [drm:intel_connector_verify_state] [CONNECTOR:37:HDMI-A-1]
[ 3128.577985] [drm:intel_connector_verify_state] [CONNECTOR:42:DP-1]
[ 3128.577986] [drm:intel_connector_verify_state] [CONNECTOR:46:HDMI-A-2]
[ 3128.577987] [drm:intel_connector_verify_state] [CONNECTOR:51:DP-3]
[ 3128.577988] [drm:verify_single_dpll_state] WRPLL 1
[ 3128.577989] [drm:verify_single_dpll_state] WRPLL 2
[ 3128.577990] [drm:verify_single_dpll_state] SPLL
[ 3128.577991] [drm:verify_single_dpll_state] LCPLL 810
[ 3128.577992] [drm:verify_single_dpll_state] LCPLL 1350
[ 3128.577992] [drm:verify_single_dpll_state] LCPLL 2700
[ 3128.577994] [drm:intel_enable_shared_dpll] enable LCPLL 2700 (active 1, on? 0) for crtc 26
[ 3128.577995] [drm:intel_enable_shared_dpll] enabling LCPLL 2700
[ 3128.578000] [drm:intel_mst_pre_enable_dp] 0
[ 3128.579097] [drm:intel_dp_set_signal_levels] Using signal levels 01000000
[ 3128.579099] [drm:intel_dp_set_signal_levels] Using vswing level 0
[ 3128.579100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[ 3128.580767] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
[ 3128.580768] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[ 3128.580769] [drm:intel_dp_set_signal_levels] Using vswing level 0
[ 3128.580770] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
[ 3128.582507] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
[ 3128.582509] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.582509] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[ 3128.584233] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
[ 3128.584235] [drm:intel_dp_set_signal_levels] Using vswing level 2
[ 3128.584235] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[ 3128.585940] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[ 3128.585942] [drm:intel_dp_set_signal_levels] Using vswing level 0
[ 3128.585944] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
[ 3128.587710] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.587713] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.587715] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.589458] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.589460] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.589462] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.591209] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.591212] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.591213] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.592932] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.592935] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.592937] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.594691] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.594693] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.594695] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.596460] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.596464] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.596465] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.598254] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many voltage retries, give up
[ 3128.600478] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.600481] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.600482] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.602636] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.602639] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.602641] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.604803] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.604806] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.604808] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.606984] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.606988] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.606989] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.609142] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.609146] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.609147] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.611301] [drm:intel_dp_set_signal_levels] Using signal levels 06000000
[ 3128.611304] [drm:intel_dp_set_signal_levels] Using vswing level 1
[ 3128.611306] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
[ 3128.615385] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
[ 3128.615553] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for 992 25