(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00001000 (II): RENCLK_GATE_D1: 0x70000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00080018 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x00001d9c (II): DSPFW1: 0x3f8f0f0f (II): DSPFW2: 0x00000f0f (II): DSPFW3: 0x00000000 (II): ADPA: 0x40000c00 (disabled, pipe B, -hsync, -vsync) (II): LVDS: 0xc2308300 (enabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync) (II): DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000003 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PFIT_CONTROL: 0x20000000 (II): PFIT_PGM_RATIOS: 0x0f5c0ccd (II): PORT_HOTPLUG_EN: 0x00000020 (II): PORT_HOTPLUG_STAT: 0x00000400 (II): DSPACNTR: 0xd8000000 (enabled, pipe A) (II): DSPASTRIDE: 0x00001400 (5120 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00050000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0xc0000000 (enabled, active) (II): PIPEASRC: 0x03ff02ff (1024, 768) (II): FPA0: 0x00031305 (n = 3, m1 = 19, m2 = 5) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0x94020c00 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10) (II): DPLL_A_MD: 0x00000200 (II): HTOTAL_A: 0x045f03ff (1024 active, 1120 total) (II): HBLANK_A: 0x045f03ff (1024 start, 1120 end) (II): HSYNC_A: 0x043f0400 (1025 start, 1088 end) (II): VTOTAL_A: 0x032002ff (768 active, 801 total) (II): VBLANK_A: 0x032002ff (768 start, 801 end) (II): VSYNC_A: 0x031f0300 (769 start, 800 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0xd9000000 (enabled, pipe B) (II): DSPBSTRIDE: 0x00001400 (5120 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00050000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0xc0000000 (enabled, active) (II): PIPEBSRC: 0x04ff031f (1280, 800) (II): FPB0: 0x00031009 (n = 3, m1 = 16, m2 = 9) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x98020c00 (enabled, non-dvo, default clock, LVDS mode, p1 = 2, p2 = 14) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x057f04ff (1280 active, 1408 total) (II): HBLANK_B: 0x057f04ff (1280 start, 1408 end) (II): HSYNC_B: 0x05340514 (1301 start, 1333 end) (II): VTOTAL_B: 0x032f031f (800 active, 816 total) (II): VBLANK_B: 0x032f031f (800 start, 816 end) (II): VSYNC_B: 0x03270322 (803 start, 808 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0x80000000 (disabled) (II): TV_CTL: 0x800c0000 (II): TV_DAC: 0x30000000 (II): TV_CSC_Y: 0x0332012d (II): TV_CSC_Y2: 0x07d30104 (II): TV_CSC_U: 0x0733052d (II): TV_CSC_U2: 0x05c70200 (II): TV_CSC_V: 0x0340030c (II): TV_CSC_V2: 0x06d00200 (II): TV_CLR_KNOBS: 0x10606000 (II): TV_CLR_LEVEL: 0x010b00e1 (II): TV_H_CTL_1: 0x00400359 (II): TV_H_CTL_2: 0x80480022 (II): TV_H_CTL_3: 0x007c0344 (II): TV_V_CTL_1: 0x00f01415 (II): TV_V_CTL_2: 0x00060607 (II): TV_V_CTL_3: 0x80120001 (II): TV_V_CTL_4: 0x000900f0 (II): TV_V_CTL_5: 0x000a00f0 (II): TV_V_CTL_6: 0x000900f0 (II): TV_V_CTL_7: 0x000a00f0 (II): TV_SC_CTL_1: 0xc1710088 (II): TV_SC_CTL_2: 0x4e2d1dc8 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00360024 (II): TV_WIN_SIZE: 0x02640198 (II): TV_FILTER_CTL_1: 0x80000d63 (II): TV_FILTER_CTL_2: 0x0001e1e2 (II): TV_FILTER_CTL_3: 0x0000f0f1 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0xb1403000 (II): TV_H_LUMA_59: 0x0000b060 (II): TV_H_CHROMA_0: 0xb1403000 (II): TV_H_CHROMA_59: 0x0000b060 (II): SR00: 0x03 (II): SR01: 0x01 (II): SR02: 0x0f (II): SR03: 0x00 (II): SR04: 0x0e (II): SR05: 0x00 (II): SR06: 0x00 (II): SR07: 0x00 (II): MSR: 0x67 (II): CR00: 0x5f (II): CR01: 0x4f (II): CR02: 0x50 (II): CR03: 0x82 (II): CR04: 0x55 (II): CR05: 0x81 (II): CR06: 0xbf (II): CR07: 0x1f (II): CR08: 0x00 (II): CR09: 0x4f (II): CR0a: 0x0d (II): CR0b: 0x0e (II): CR0c: 0x00 (II): CR0d: 0x00 (II): CR0e: 0x06 (II): CR0f: 0x66 (II): CR10: 0x9c (II): CR11: 0x0e (II): CR12: 0x8f (II): CR13: 0x28 (II): CR14: 0x1f (II): CR15: 0x96 (II): CR16: 0xb9 (II): CR17: 0xa3 (II): CR18: 0xff (II): CR19: 0x00 (II): CR1a: 0x00 (II): CR1b: 0x00 (II): CR1c: 0x00 (II): CR1d: 0x00 (II): CR1e: 0x00 (II): CR1f: 0x00 (II): CR20: 0x00 (II): CR21: 0x00 (II): CR22: 0x00 (II): CR23: 0x00 (II): CR24: 0x00 (II): pipe A dot 107520 n 3 m1 19 m2 5 p1 2 p2 10 (II): pipe B dot 69257 n 3 m1 16 m2 9 p1 2 p2 14 (II): DumpRegsEnd