diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 8d91642..3effe3f 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -857,12 +857,12 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 	regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 	regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
-	regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0) 
-				| SetBit(7);
-	regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
-	regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
-				| SetBitField(horizEnd,4:0,4:0);
-	regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
+	regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = 0x82;//SetBitField(horizBlankEnd,4:0,4:0) 
+//				| SetBit(7);
+	regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = 0xb9;//Set8Bits(horizStart);
+	regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = 0x1c;//SetBitField(horizBlankEnd,5:5,7:7)
+//				| SetBitField(horizEnd,4:0,4:0);
+	regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = 0x36;//SetBitField(vertTotal,7:0,7:0);
 	regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 				| SetBitField(vertDisplay,8:8,1:1)
 				| SetBitField(vertStart,8:8,2:2)
@@ -887,10 +887,10 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 	regp->CRTC[0xe] = 0x00;
 	regp->CRTC[0xf] = 0x00;
-	regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
+	regp->CRTC[NV_VGA_CRTCX_VSYNCS] = 0x33;//Set8Bits(vertStart);
 	/* What is the meaning of bit5, it is empty in the vga spec. */
-	regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
-									(NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
+	regp->CRTC[NV_VGA_CRTCX_VSYNCE] = 0x24;//SetBitField(vertEnd,3:0,3:0) |
+						//			(NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
 	regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 	if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 		regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
@@ -904,8 +904,8 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	} else {
 		regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 	}
-	regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
-	regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
+	regp->CRTC[NV_VGA_CRTCX_VBLANKS] = 0x33;//Set8Bits(vertBlankStart);
+	regp->CRTC[NV_VGA_CRTCX_VBLANKE] = 0x37;//Set8Bits(vertBlankEnd);
 	/* 0x80 enables the sequencer, we don't want that */
 	if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 		regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
@@ -1053,9 +1053,9 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adju
 	/* Sometimes 0x10 is used, what is this? */
 	regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
 	/* Some kind of tmds switch for older cards */
-	if (pNv->Architecture < NV_ARCH_40) {
-		regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
-	}
+//	if (pNv->Architecture < NV_ARCH_40) {
+//		regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
+//	}
 
 	/*
 	* Initialize DAC palette.
@@ -1263,7 +1263,7 @@ nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModeP
 		regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 		regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 		/* This is what the blob does. */
-		regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
+		regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1 + 28;
 		regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 		regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 		regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
@@ -1272,7 +1272,7 @@ nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModeP
 		regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 		regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 		/* This is what the blob does. */
-		regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
+		regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1 - 10;
 		regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 		regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 		regp->fp_vert_regs[REG_DISP_VALID_START] = 0;