diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 83bf3df..75a8309 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -316,7 +316,8 @@ static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int do
 		} else
 			VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 	} else
-		VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
+		CalcVClock(dotClock, &VClk, &regp->vpll_a, pNv);
+//		VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 
 	/* Are these all the (relevant) G70 cards? */
 	if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
@@ -332,7 +333,7 @@ static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int do
 		/* See nvregisters.xml for details. */
 		regp->vpll_a = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 	else
-		regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
+//		regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 	regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 
 	/* Does register 0x580 already have a value? */
diff --git a/src/nv_hw.c b/src/nv_hw.c
index 0c1ab01..c7fe3a5 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -1034,7 +1034,7 @@ void nForceUpdateArbitrationSettings (unsigned VClk,
 /*
  * Calculate the Video Clock parameters for the PLL.
  */
-static void CalcVClock (
+void CalcVClock (
     int           clockIn,
     int          *clockOut,
     CARD32         *pllOut,
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 71eb50e..1af8f80 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -64,6 +64,7 @@ void NVCalcStateExt(NVPtr,struct _riva_hw_state *,int,int,int,int,int,int);
 void NVLoadStateExt(ScrnInfoPtr pScrn,struct _riva_hw_state *);
 void NVUnloadStateExt(NVPtr,struct _riva_hw_state *);
 void NVSetStartAddress(NVPtr,CARD32);
+void CalcVClock (int, int *, CARD32 *, NVPtr);
 
 /* in nv_shadow.c */
 void NVRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);