diff --git a/src/legacy_output.c b/src/legacy_output.c
index 4df81ab..96088cb 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -169,6 +169,25 @@ RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 
 }
 
+/* Write disp pwr mgmt registers */
+void
+RADEONRestoreDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    OUTREG(RADEON_DISP_PWR_MAN,         restore->disp_pwr_man);
+}
+
+void
+RADEONSaveDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    save->disp_pwr_man              = INREG(RADEON_DISP_PWR_MAN);
+}
+
 void
 RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
 {
@@ -763,6 +782,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 	    }
 	} else if (radeon_output->MonType == MT_LCD) {
 	    info->output_lcd1 |= (1 << o);
+	    RADEONInitDispPwrManRegisters(pScrn, save);
+	    RADEONRestoreDispPwrManRegisters(pScrn, save);
+	    tmp = INREG(RADEON_LVDS_PLL_CNTL);
+	    tmp |= RADEON_LVDS_PLL_EN;
+	    OUTREG(RADEON_LVDS_PLL_CNTL, tmp);
+	    usleep (1000);
+	    tmp = INREG(RADEON_LVDS_PLL_CNTL);
+	    tmp &= ~RADEON_LVDS_PLL_RESET;
+	    OUTREG(RADEON_LVDS_PLL_CNTL, tmp);
 	    tmp = INREG(RADEON_LVDS_GEN_CNTL);
 	    tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
 	    tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
@@ -1077,10 +1105,7 @@ RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
 
-    save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl |
-			   RADEON_LVDS_PLL_EN);
-
-    save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
+    save->lvds_pll_cntl = info->SavedReg->lvds_pll_cntl;
 
     save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
     save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
@@ -1360,6 +1385,17 @@ RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
     }
 }
 
+void
+RADEONInitDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+
+    save->disp_pwr_man = info->SavedReg->disp_pwr_man;
+
+    save->disp_pwr_man |= (RADEON_AUTO_PWRUP_EN);
+
+}
+
 static void
 RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
 			  DisplayModePtr mode, xf86OutputPtr output,
diff --git a/src/radeon.h b/src/radeon.h
index 23bd0a5..5373e4d 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -816,9 +816,12 @@ extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONInitDispPwrManRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 
 /* radeon_accel.c */
 extern Bool RADEONAccelInit(ScreenPtr pScreen);
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 16a0530..03f17bd 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4869,6 +4869,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
 
 	RADEONSaveMemMapRegisters(pScrn, save);
 	RADEONSaveCommonRegisters(pScrn, save);
+	RADEONSaveDispPwrManRegisters(pScrn, save);
 	RADEONSavePLLRegisters(pScrn, save);
 	RADEONSaveCrtcRegisters(pScrn, save);
 	RADEONSaveFPRegisters(pScrn, save);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 24af52b..b35be35 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -397,6 +397,7 @@ typedef struct {
     uint32_t          cap0_trig_cntl;
     uint32_t          cap1_trig_cntl;
     uint32_t          bus_cntl;
+    uint32_t          disp_pwr_man;
 
     uint32_t          bios_0_scratch;
     uint32_t          bios_1_scratch;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 59e2f12..708d642 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -556,6 +556,24 @@
 #       define RADEON_DAC_PDWN_R            (1 << 16)
 #       define RADEON_DAC_PDWN_G            (1 << 17)
 #       define RADEON_DAC_PDWN_B            (1 << 18)
+#define RADEON_DISP_PWR_MAN                 0x0d08
+#       define RADEON_DISP_PWR_MAN_D3_CRTC_EN      (1 << 0)
+#       define RADEON_DISP_PWR_MAN_D3_CRTC2_EN     (1 << 4)
+#       define RADEON_DISP_PWR_MAN_DPMS_ON  (0 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_STANDBY    (1 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_SUSPEND    (2 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
+#       define RADEON_DISP_D3_RST           (1 << 16)
+#       define RADEON_DISP_D3_REG_RST       (1 << 17)
+#       define RADEON_DISP_D3_GRPH_RST      (1 << 18)
+#       define RADEON_DISP_D3_SUBPIC_RST    (1 << 19)
+#       define RADEON_DISP_D3_OV0_RST       (1 << 20)
+#       define RADEON_DISP_D1D2_GRPH_RST    (1 << 21)
+#       define RADEON_DISP_D1D2_SUBPIC_RST  (1 << 22)
+#       define RADEON_DISP_D1D2_OV0_RST     (1 << 23)
+#       define RADEON_DIG_TMDS_ENABLE_RST   (1 << 24)
+#       define RADEON_TV_ENABLE_RST         (1 << 25)
+#       define RADEON_AUTO_PWRUP_EN         (1 << 26)
 #define RADEON_TV_DAC_CNTL                  0x088c
 #       define RADEON_TV_DAC_NBLANK         (1 << 0)
 #       define RADEON_TV_DAC_NHOLD          (1 << 1)