diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index b34a421..726fbcf 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -1321,6 +1321,43 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
     return FALSE;
 }
 
+static void radeon_hw_i2c_write(xf86OutputPtr output, uint32_t gpio_reg,
+				int slave, int address, int value)
+{
+    ScrnInfoPtr pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+    uint32_t gpio_line;
+
+    if (gpio_reg == RADEON_GPIO_VGA_DDC)
+	gpio_line = (0 << 3);
+    else if (gpio_reg == RADEON_GPIO_DVI_DDC)
+	gpio_line = (1 << 3);
+    else if (gpio_reg == RADEON_GPIO_DVI_DDC)
+	gpio_line = (2 << 3);
+    else if (gpio_reg == RADEON_GPIO_CRT2_DDC)
+	gpio_line = (3 << 3);
+    else {
+	ErrorF("bad gpio_reg: 0x%x\n", gpio_reg);
+	return;
+    }
+
+    ErrorF("gpio_reg: 0x%x\n", gpio_reg);
+
+    OUTREG(RADEON_DVI_I2C_CNTL_0, 0x27 | gpio_line);
+    OUTREG(RADEON_DVI_I2C_CNTL_1, 0x30020021);
+
+    OUTREG(RADEON_DVI_I2C_DATA, slave);
+    OUTREG(RADEON_DVI_I2C_DATA, address);
+    OUTREG(RADEON_DVI_I2C_DATA, value);
+
+    OUTREG(RADEON_DVI_I2C_CNTL_0, 0x8801300 | gpio_line);
+    usleep(1000);
+
+    ErrorF("gpio_reg status: 0x%x\n", INREG(RADEON_DVI_I2C_CNTL_0));
+}
+
+
 Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
 {
     ScrnInfoPtr pScrn = output->scrn;
@@ -1391,7 +1428,9 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
 				index++;
 				ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg,
 				       (unsigned)val);
-				RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
+				//RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
+				radeon_hw_i2c_write(output, radeon_output->dvo_i2c_slave_addr,
+						    radeon_output->dvo_i2c.mask_clk_reg, reg, val);
 				break;
 			    default:
 				ErrorF("unknown id %d\n", id>>13);