b-- BIOS enabled HDMI/DVI |x-- XORG running ||d-- RADEON enabled DVI |||h-- RADEON enabled HDMI |||| 0x0300: VGA_RENDER_CONTROL 0x0201000F x 0x0201000F b 0x0203000F xd 0x0201000F x h 0x0201000F xdh 0x0201000F 0x0338: D2VGA_CONTROL 0x00000401 x 0x00000400 0x00000000 b 0x00000001 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x0414: EXT2_PPLL_REF_DIV 0x00000007 x 0x00000007 0x00000002 b 0x00000004 xd 0x00000002 x h 0x00000002 xdh 0x00000002 0x041C: EXT2_PPLL_UPDATE_CNTL 0x00000000 x 0x00000000 0x00010000 b 0x00010000 xd 0x00010000 x h 0x00010000 xdh 0x00010000 0x0434: EXT2_PPLL_FB_DIV 0x01280000 x 0x01280000 0x00300030 b 0x00900030 xd 0x00300030 x h 0x00300030 xdh 0x00300030 0x0440: EXT2_PPLL_POST_DIV_SRC 0x00000000 x 0x00000000 0x00000001 b 0x00000001 xd 0x00000001 x h 0x00000001 xdh 0x00000001 0x0444: EXT2_PPLL_POST_DIV 0x00000006 x 0x00000006 0x00000004 b 0x00000009 xd 0x00000004 x h 0x00000004 xdh 0x00000004 0x044C: EXT2_PPLL_CNTL 0x05120704 x 0x05120704 0x159F8704 b 0x159EC704 xd 0x159F8704 x h 0x159F8704 xdh 0x159F8704 0x0454: P2PLL_CNTL 0x6C012003 x 0x6C012003 0x00310000 b 0x00310000 xd 0x00310000 x h 0x00310000 xdh 0x00310000 0x0460: **NOT IN .H** 0x00000000 x 0x00000000 0x00000001 b 0x00000001 xd 0x00000001 x h 0x00000000 0x00000001 xdh 0x00000001 0x046C: P2PLL_DISP_CLK_CNTL 0x00000302 x 0x00000302 0x00000002 b 0x00000002 xd 0x00000002 x h 0x00000002 xdh 0x00000002 0x0484: PCLK_CRTC2_CNTL 0x00000000 x 0x00000000 0x00010000 b 0x00010000 xd 0x00010000 x h 0x00010000 xdh 0x00010000 0x1730: **NOT IN .H** 0x00000002 x 0x00000002 0x00080002 b 0x0008000A xd 0x0008000A x h 0x00000002 0x00080002 xdh 0x0008000A 0x1738: **NOT IN .H** 0x00000002 x 0x00000002 b 0x0000018F xd 0x00000002 x h 0x00000002 xdh 0x00000002 0x173C: **NOT IN .H** 0x10001800 x 0x30001810 b 0x90001800 xd 0x30001810 x h 0x30001810 xdh 0x30001810 0x60F4: **NOT IN .H** 0x00000001 x 0x00000001 0x00010001 b 0x00010001 xd 0x00010001 x h 0x00010001 xdh 0x00010001 0x60F8: **NOT IN .H** 0x00000001 x 0x00000001 b 0x00000003 xd 0x00000003 x h 0x00000003 xdh 0x00000003 0x6520: **NOT IN .H** 0x00070000 x 0x00030000 0x00330000 b 0x00770000 xd 0x00330000 x h 0x00330000 xdh 0x00330000 0x6524: D1CUR_UPDATE 0x00000001 x 0x00000001 b 0x00000000 xd 0x00000001 x h 0x00000001 xdh 0x00000001 0x65D0: **NOT IN .H** 0x00000001 x 0x00000001 b 0x00000000 xd 0x00000001 x h 0x00000001 xdh 0x00000001 0x6800: D2CRTC_H_TOTAL 0x0000031F x 0x0000031F 0x0000086F b 0x00000697 xd 0x0000086F x h 0x0000086F xdh 0x0000086F 0x6804: D2CRTC_H_BLANK_START_END 0x00000000 x 0x00000000 0x01F00830 b 0x01680668 xd 0x01F00830 x h 0x01F00830 xdh 0x01F00830 0x6808: D2CRTC_H_SYNC_A 0x00000000 x 0x00000000 0x00C00000 b 0x00700000 xd 0x00C00000 x h 0x00C00000 xdh 0x00C00000 0x6820: D2CRTC_V_TOTAL 0x0000020C x 0x0000020C 0x000004E1 b 0x00000429 xd 0x000004E1 x h 0x000004E1 xdh 0x000004E1 0x6824: D2CRTC_V_BLANK_START_END 0x00000000 x 0x00000000 0x003104E1 b 0x00290429 xd 0x003104E1 x h 0x003104E1 xdh 0x003104E1 0x6828: D2CRTC_V_SYNC_A 0x00000000 x 0x00000000 0x00030000 b 0x00030000 xd 0x00030000 x h 0x00030000 xdh 0x00030000 0x682C: D2CRTC_V_SYNC_A_CNTL 0x00000000 x 0x00000000 b 0x00000001 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6880: D2CRTC_CONTROL 0x01000310 x 0x01000310 b 0x00010311 xd 0x00010311 x h 0x00010311 xdh 0x00010311 0x6884: D2CRTC_BLANK_CONTROL 0x00000001 x 0x00000101 b 0x00000000 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x68EC: **NOT IN .H** 0x00000000 x 0x00000000 0x00000100 b 0x00000100 xd 0x00000100 0x00000000 x h 0x00000000 xdh 0x00000100 0x6D90: D2SCL_ENABLE 0x00000000 x 0x00000000 b 0x00000001 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6D94: D2SCL_TAP_CONTROL 0x00000000 x 0x00000000 b 0x00000101 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6D9C: D2MODE_CENTER (guess) 0x00000002 x 0x00000002 b 0x00000000 xd 0x00000002 x h 0x00000002 xdh 0x00000002 0x6DA4: D2SCL_HVSCALE (guess) 0x00000000 x 0x00000000 b 0x00010001 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6DB0: D2SCL_HFILTER (guess) 0x00000000 x 0x00000000 b 0x00030100 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6DC0: D2SCL_VFILTER (guess) 0x00000000 x 0x00000000 b 0x00030100 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6DCC: D2SCL_UPDATE 0x00000100 x 0x00000100 0x00000000 b 0x00000000 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6DD4: D2SCL_DITHER (guess) 0x00000000 x 0x00000000 b 0x00001010 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6E20: **NOT IN .H** 0x00000000 x 0x00000000 b 0x02400000 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6E24: **NOT IN .H** 0x00000000 x 0x00000000 b 0x00032000 xd 0x00000000 x h 0x00000000 xdh 0x00000000 0x6E28: **NOT IN .H** 0x00000000 x 0x00000000 0x064004B0 b 0x02D00190 xd 0x064004B0 x h 0x064004B0 xdh 0x064004B0 0x7880: TMDSA_CNTL 0x00001000 x 0x00001000 0x00001001 b 0x10001001 xd 0x00001001 x h 0x00001000 0x00001001 xdh 0x00001001 0x7884: TMDSA_SOURCE_SELECT 0x00000000 x 0x00000000 0x00000001 b 0x00000001 xd 0x00000001 x h 0x00000000 0x00000001 xdh 0x00000001 0x7894: TMDSA_BIT_DEPTH_CONTROL 0x02000000 x 0x02000000 0x00000000 b 0x14000100 xd 0x00000000 x h 0x02000000 0x00000000 xdh 0x00000000 0x78DC: TMDSA_DATA_SYNCHRONIZATION_R600 0x00000000 x 0x00000000 0x00000001 b 0x00000001 xd 0x00000001 x h 0x00000000 0x00000001 xdh 0x00000001 0x7904: TMDSA_TRANSMITTER_ENABLE 0x00000000 x 0x00000000 b 0x00001F00 xd 0x0000001F x h 0x00000000 xdh 0x0000001F 0x790C: TMDSA_MACRO_CONTROL (r5x0 and r600: 3 for pll and 1 for TX) 0x0000070B x 0x0000070B 0x0001040A b 0x0001040A xd 0x0001040A x h 0x0000070B 0x0001040A xdh 0x0001040A 0x7910: TMDSA_TRANSMITTER_CONTROL 0x30000032 x 0x30000032 0x00000031 b 0x30000031 xd 0x00000031 x h 0x30000032 0x00000031 xdh 0x00000031 0x7920: TMDSA_TRANSMITTER_ADJUST (rv6x0: TX part of macro control) 0x000000AA x 0x000000AA 0x0003038B b 0x0003038B xd 0x0003038B x h 0x000000AA 0x0003038B xdh 0x0003038B