Attachment 25569 Details for Bug 21373 – Output of intel_reg_dumper

Output of intel_reg_dumper

intel_reg_dumper-output.txt (text/plain), 9.35 KB, created by aguertin+freedesktop on 2009-05-06 12:27:31 UTC

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Creator: aguertin+freedesktop

Created: 2009-05-06 12:27:31 UTC

Size: 9.35 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x6ef000ad (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep present)
>(II):               C0DRB0: 0x00000000 (0x0000)
>(II):               C0DRB1: 0x00000000 (0x0000)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x00000000 (0x0000)
>(II):               C1DRB0: 0x00000000 (0x0000)
>(II):               C1DRB1: 0x00000000 (0x0000)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x00000000 (0x0000)
>(II):              C0DRA23: 0x00000000 (0x0000)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):           PGETBL_CTL: 0x3ffe0001
>(II):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II):         CACHE_MODE_0: 0x00000000
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x0000005f
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II):                 LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000000 (power target: off)
>(II):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00000000
>(II):        PP_OFF_DELAYS: 0x00000000
>(II):           PP_DIVISOR: 0x00000000
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x01800000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II):            PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):                 FPA0: 0x0004160d (n = 4, m1 = 22, m2 = 13)
>(II):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):               DPLL_A: 0x90a00000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 4)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>(II):             HBLANK_A: 0x069704ff (1280 start, 1688 end)
>(II):              HSYNC_A: 0x059f050f (1296 start, 1440 end)
>(II):             VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>(II):             VBLANK_A: 0x042903ff (1024 start, 1066 end)
>(II):              VSYNC_A: 0x04030400 (1025 start, 1028 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0x00000000 (disabled, pipe A)
>(II):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II):             PIPEBSRC: 0x00000000 (1, 1)
>(II):            PIPEBSTAT: 0x00000000 (status:)
>(II):                 FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II):                 FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>(II):               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x00000000 (1 active, 1 total)
>(II):             HBLANK_B: 0x00000000 (1 start, 1 end)
>(II):              HSYNC_B: 0x00000000 (1 start, 1 end)
>(II):             VTOTAL_B: 0x00000000 (1 active, 1 total)
>(II):             VBLANK_B: 0x00000000 (1 start, 1 end)
>(II):              VSYNC_B: 0x00000000 (1 start, 1 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00021207
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x0000888b
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x069704ff
>(II):               TV_DAC: 0x069704ff
>(II):             TV_CSC_Y: 0x042903ff
>(II):            TV_CSC_Y2: 0x04030400
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x04ff03ff
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00200000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x069704ff
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x00000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000000
>(II):         MI_ARB_STATE: 0x00000000
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x069704ff
>(II):       DPC_AUX_CH_CTL: 0x042903ff
>(II):     DPC_AUX_CH_DATA1: 0x04030400
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x04ff03ff
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II): pipe A dot 135000 n 4 m1 22 m2 13 p1 2 p2 4
>(II): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2
>(II): DumpRegsEnd

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Attachments on bug 21373: 25092 | 25093 | 25256 | 25389 | 25569 | 25599 | 25661

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