diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
index 3f80db8..0bb23ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_calc.c
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
@@ -199,6 +199,11 @@ nv10CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
 	mclks += 2;	/* fb_cas_n_  memory request to fbio block */
 	mclks += 7;	/* sm_d_rdv   data returned from fbio block */
 
+	printk("pclk_freq: %d mclk_freq: %d nvclk_freq: %d pagemiss: %d"
+	       " width: %d video_enable: %d bpp: %d memory_type: %d\n",
+	       pclk_freq, mclk_freq, nvclk_freq, pagemiss, width,
+	       video_enable, bpp, arb->memory_type);
+
 	/* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
 	if (arb->memory_type == 0) {
 		if (arb->memory_width == 64)	/* 64 bit bus */
@@ -304,6 +309,9 @@ nv10CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
 		p1clk = m2us * pclk_freq / (1000 * 1000);
 		p2 = p1clk * bpp / 8;	/* bytes drained. */
 
+		printk("min_mclk_extra: %d cbs: %d us_pipe_min: %d us_min_mclk_extra: %d\n",
+		       min_mclk_extra, cbs, us_pipe_min, us_min_mclk_extra);
+
 		if (p2 < m1 && m1 > 0) {
 			fifo->valid = false;
 			found = 0;
@@ -325,7 +333,10 @@ nv10CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
 
 		/* This correction works around a slight snow effect
 		 * when the TV and VGA outputs are enabled simultaneously. */
-		min_clwm = 1024 - cbs + 128 * pclk_freq / 100000;
+		min_clwm = 1024 - cbs + 64 * crtc_drain_rate / 100000;
+		printk("clwm: %d min_clwm: %d m1: %d min_m1: %d p2: %d\n",
+		       clwm, min_clwm, m1, min_clwm + cbs - 1024, p2);
+
 		if (clwm < min_clwm)
 			clwm = min_clwm;