diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index e1334e2..c69f1ef 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -207,7 +207,7 @@ int rs600_gart_enable(struct radeon_device *rdev)
 		WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 			  S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 			  S_00016C_SYSTEM_ACCESS_MODE_MASK(
-				  V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
+				  V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
 			  S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 				  V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 			  S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
@@ -231,8 +231,8 @@ int rs600_gart_enable(struct radeon_device *rdev)
 	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
 	/* System context maps to VRAM space */
-	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
-	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
+	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
+	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
 
 	/* enable page tables */
 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);