Attachment 106551 Details for Bug 84089 – Fix

[patch] Fix

0001-R600-SI-Fix-config-value-for-number-of-gprs.patch (text/plain), 2.26 KB, created by Tom Stellard on 2014-09-19 14:01:29 UTC

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Creator: Tom Stellard

Created: 2014-09-19 14:01:29 UTC

Size: 2.26 KB

patch

obsolete

>From 445509221e5078c1e3092ea179699dd72d1518bc Mon Sep 17 00:00:00 2001
>From: Tom Stellard <thomas.stellard@amd.com>
>Date: Fri, 19 Sep 2014 08:55:46 -0400
>Subject: [PATCH] R600/SI: Fix config value for number of gprs
>
>In r217636, the value stored in KernelInfo.Num[VS]GPRSs was changed from
>the highest GPR index used to the number of gprs in order to be
>consistent with the name of the variable.
>
>The code writing the config values still assumed that the value in this
>variable was the highest GPR index used, which caused the compiler to
>over report the number of GPRs being used.
>
>https://bugs.freedesktop.org/show_bug.cgi?id=84089
>---
> lib/Target/R600/AMDGPUAsmPrinter.cpp | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
>diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp
>index 2755af2..b736afc 100644
>--- a/lib/Target/R600/AMDGPUAsmPrinter.cpp
>+++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp
>@@ -389,12 +389,15 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
>     RoundUpToAlignment(KernelInfo.ScratchSize * STM.getWavefrontSize(),
>                        1 << ScratchAlignShift) >> ScratchAlignShift;
> 
>+  unsigned VGPRBlocks = (KernelInfo.NumVGPR - 1) / 4;
>+  unsigned SGPRBlocks = (KernelInfo.NumSGPR - 1) / 8;
>+
>   if (MFI->getShaderType() == ShaderType::COMPUTE) {
>     OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
> 
>     const uint32_t ComputePGMRSrc1 =
>-      S_00B848_VGPRS(KernelInfo.NumVGPR / 4) |
>-      S_00B848_SGPRS(KernelInfo.NumSGPR / 8) |
>+      S_00B848_VGPRS(VGPRBlocks) |
>+      S_00B848_SGPRS(SGPRBlocks) |
>       S_00B848_PRIORITY(KernelInfo.Priority) |
>       S_00B848_FLOAT_MODE(KernelInfo.FloatMode) |
>       S_00B848_PRIV(KernelInfo.Priv) |
>@@ -418,8 +421,8 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
>     // 0" comment but I don't see a corresponding field in the register spec.
>   } else {
>     OutStreamer.EmitIntValue(RsrcReg, 4);
>-    OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
>-                             S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
>+    OutStreamer.EmitIntValue(S_00B028_VGPRS(VGPRBlocks) |
>+                             S_00B028_SGPRS(SGPRBlocks), 4);
>   }
> 
>   if (MFI->getShaderType() == ShaderType::PIXEL) {
>-- 
>1.8.5.5
>

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