Attachment 127253 Details for Bug 97450 – This is combined Paulo patchset that applies to 4.8.1

[patch] This is combined Paulo patchset that applies to 4.8.1

skl_uncondition_memory_bandwitdth_WA_n_adjusted_mode_in_SAGV_check.patch (text/plain), 4.43 KB, created by yann on 2016-10-12 17:19:30 UTC

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Creator: yann

Created: 2016-10-12 17:19:30 UTC

Size: 4.43 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 2d24813..4c5edf3 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2877,6 +2877,21 @@ skl_wm_plane_id(const struct intel_plane *plane)
> }
>
> /*
>+ * FIXME: We still don't have the proper code detect if we need to apply the WA,
>+ * so assume we'll always need it in order to avoid underruns.
>+ */
>+static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
>+{
>+       struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+
>+       if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
>+           IS_KABYLAKE(dev_priv))
>+               return true;
>+
>+       return false;
>+}
>+
>+/*
>  * SAGV dynamically adjusts the system agent voltage and clock frequencies
>  * depending on power and performance requirements. The display engine access
>  * to system memory is blocked during the adjustment time. Because of the
>@@ -2979,9 +2994,10 @@ bool skl_can_enable_sagv(struct drm_atomic_state *state)
>        struct drm_device *dev = state->dev;
>        struct drm_i915_private *dev_priv = to_i915(dev);
>        struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>-       struct drm_crtc *crtc;
>+       struct intel_crtc *crtc;
>+       struct intel_plane *plane;
>        enum pipe pipe;
>-       int level, plane;
>+       int level, id, latency;
>
>        /*
>         * SKL workaround: bspec recommends we disable the SAGV when we have
>@@ -2996,27 +3012,36 @@ bool skl_can_enable_sagv(struct drm_atomic_state *state)
>
>        /* Since we're now guaranteed to only have one active CRTC... */
>        pipe = ffs(intel_state->active_crtcs) - 1;
>-       crtc = dev_priv->pipe_to_crtc_mapping[pipe];
>+       crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>
>-       if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
>+       if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>                return false;
>
>-       for_each_plane(dev_priv, pipe, plane) {
>+       for_each_intel_plane_on_crtc(dev, crtc, plane) {
>+               id = skl_wm_plane_id(plane);
>+
>                /* Skip this plane if it's not enabled */
>-               if (intel_state->wm_results.plane[pipe][plane][0] == 0)
>+               if (intel_state->wm_results.plane[pipe][id][0] == 0)
>                        continue;
>
>                /* Find the highest enabled wm level for this plane */
>                for (level = ilk_wm_max_level(dev);
>-                    intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
>+                    intel_state->wm_results.plane[pipe][id][level] == 0; --level)
>                     { }
>
>+               latency = dev_priv->wm.skl_latency[level];
>+
>+               if (skl_needs_memory_bw_wa(intel_state) &&
>+                   plane->base.state->fb->modifier[0] ==
>+                   I915_FORMAT_MOD_X_TILED)
>+                       latency += 15;
>+
>                /*
>                 * If any of the planes on this pipe don't enable wm levels
>                 * that incur memory latencies higher then 30Âµs we can't enable
>                 * the SAGV
>                 */
>-               if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
>+               if (latency < SKL_SAGV_BLOCK_TIME)
>                        return false;
>        }
>
>@@ -3546,12 +3571,18 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>        uint8_t cpp;
>        uint32_t width = 0, height = 0;
>        uint32_t plane_pixel_rate;
>+       struct intel_atomic_state *state =
>+               to_intel_atomic_state(cstate->base.state);
>+       bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
>
>        if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
>                *enabled = false;
>                return 0;
>        }
>
>+       if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
>+               latency += 15;
>+
>        width = drm_rect_width(&intel_pstate->src) >> 16;
>        height = drm_rect_height(&intel_pstate->src) >> 16;
>
>@@ -3593,6 +3624,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>                        }
>                }
>                y_tile_minimum = plane_blocks_per_line * min_scanlines;
>+                if (apply_memory_bw_wa)
>+                       y_tile_minimum *= 2;
>+
>                selected_result = max(method2, y_tile_minimum);
>        } else {
>                if ((ddb_allocation / plane_blocks_per_line) >= 1)

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