Attachment 4636 Details for Bug 5766 – Limit pixel clock to model memory bandwidth limits

[patch] Limit pixel clock to model memory bandwidth limits

rn50-pixelclock-limit.diff (text/plain), 1.82 KB, created by Michel Dänzer on 2006-02-17 05:40:11 UTC

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Creator: Michel Dänzer

Created: 2006-02-17 05:40:11 UTC

Size: 1.82 KB

patch

obsolete

>Index: src/radeon_driver.c
>===================================================================
>RCS file: /cvs/xorg/driver/xf86-video-ati/src/radeon_driver.c,v
>retrieving revision 1.85
>diff -p -u -r1.85 radeon_driver.c
>--- src/radeon_driver.c	19 Jan 2006 14:20:37 -0000	1.85
>+++ src/radeon_driver.c	16 Feb 2006 18:30:29 -0000
>@@ -1721,6 +1721,15 @@ static void RADEONGetClockInfo(ScrnInfoP
>         info->mclk = 200.00;
>     }
> 
>+    if (info->ChipFamily == CHIP_FAMILY_RV100 && !info->HasCRTC2) {
>+        /* Avoid RN50 corruption due to memory bandwidth starvation.
>+         * 18 is an empirical value based on the databook and Windows driver.
>+        */
>+        pll->max_pll_freq = min(pll->max_pll_freq,
>+                               18 * info->mclk * 100 / pScrn->bitsPerPixel *
>+                               info->RamWidth / 16);
>+    }
>+
>     xf86DrvMsg (pScrn->scrnIndex, X_INFO,
> 		"PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n",
> 		pll->reference_freq,
>@@ -2358,6 +2367,10 @@ static void RADEONGetVRamType(ScrnInfoPt
> 	       (info->ChipFamily == CHIP_FAMILY_RS200)){
> 	if (tmp & RV100_HALF_MODE) info->RamWidth = 32;
> 	else info->RamWidth = 64;
>+       if (!info->HasCRTC2) {
>+           info->RamWidth /= 4;
>+           info->IsDDR = TRUE;
>+       }
>     } else {
> 	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128;
> 	else info->RamWidth = 64;
>@@ -2424,10 +2437,11 @@ static Bool RADEONPreInitConfig(ScrnInfo
> 	info->ChipFamily = CHIP_FAMILY_RV100;
> 	break;
> 
>-    case PCI_CHIP_RV100_QY:
>-    case PCI_CHIP_RV100_QZ:
>     case PCI_CHIP_RN50_515E:  /* RN50 is based on the RV100 but 3D isn't guaranteed to work.  YMMV. */
>     case PCI_CHIP_RN50_5969:
>+        info->HasCRTC2 = FALSE;
>+    case PCI_CHIP_RV100_QY:
>+    case PCI_CHIP_RV100_QZ:
> 	info->ChipFamily = CHIP_FAMILY_RV100;
> 
> 	/* DELL triple-head configuration. */

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