Attachment 48892 Details for Bug 38800 – Add missing register access guards

[patch] Add missing register access guards

fdo38800-evergreen.diff (text/plain), 9.48 KB, created by Michel Dänzer on 2011-07-08 05:18:32 UTC

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Creator: Michel Dänzer

Created: 2011-07-08 05:18:32 UTC

Size: 9.48 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
>index 296e6ec..4a591e3 100644
>--- a/drivers/gpu/drm/radeon/evergreen.c
>+++ b/drivers/gpu/drm/radeon/evergreen.c
>@@ -2466,10 +2466,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
> 
> 	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
> 	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
>-	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
>-	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
>-	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
>-	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
>+	if (!(rdev->flags & RADEON_IS_IGP)) {
>+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
>+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
>+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
>+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
>+	}
> 
> 	WREG32(DC_HPD1_INT_CONTROL, hpd1);
> 	WREG32(DC_HPD2_INT_CONTROL, hpd2);
>@@ -2493,23 +2495,11 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
> 	rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
> 	rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
> 	rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
>-	rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
>-	rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
>-	rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
>-	rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
> 
> 	if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
> 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> 	if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
> 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>-	if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
>-		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>-	if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
>-		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>-	if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
>-		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>-	if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
>-		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
> 
> 	if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
> 		WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
>@@ -2521,25 +2511,41 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
> 	if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
> 		WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
> 
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
>-		WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
>-		WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
>-
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
>-		WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
>-		WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
>-
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
>-		WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
>-		WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
>-
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
>-		WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
>-	if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
>-		WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
>+	if (!(rdev->flags & RADEON_IS_IGP)) {
>+		rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
>+		rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
>+		rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
>+		rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
>+
>+		if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
>+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>+		if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
>+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>+		if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
>+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>+		if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
>+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
>+
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
>+			WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
>+			WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
>+
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
>+			WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
>+			WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
>+
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
>+			WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
>+			WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
>+
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
>+			WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
>+		if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
>+			WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
>+	}
> 
> 	if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
> 		tmp = RREG32(DC_HPD1_INT_CONTROL);
>diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
>index 0671934..8aaa345 100644
>--- a/drivers/gpu/drm/radeon/radeon_display.c
>+++ b/drivers/gpu/drm/radeon/radeon_display.c
>@@ -279,8 +279,8 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
> 
> 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
> 	work = radeon_crtc->unpin_work;
>-	if (work == NULL ||
>-	    !radeon_fence_signaled(work->fence)) {
>+	if (work == NULL || 
>+	    (work->fence && !radeon_fence_signaled(work->fence))) {
> 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
> 		return;
> 	}
>@@ -346,7 +346,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
> 	struct radeon_framebuffer *new_radeon_fb;
> 	struct drm_gem_object *obj;
> 	struct radeon_bo *rbo;
>-	struct radeon_fence *fence;
> 	struct radeon_unpin_work *work;
> 	unsigned long flags;
> 	u32 tiling_flags, pitch_pixels;
>@@ -357,22 +356,19 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
> 	if (work == NULL)
> 		return -ENOMEM;
> 
>-	r = radeon_fence_create(rdev, &fence);
>-	if (unlikely(r != 0)) {
>-		kfree(work);
>-		DRM_ERROR("flip queue: failed to create fence.\n");
>-		return -ENOMEM;
>-	}
> 	work->event = event;
> 	work->rdev = rdev;
> 	work->crtc_id = radeon_crtc->crtc_id;
>-	work->fence = radeon_fence_ref(fence);
> 	old_radeon_fb = to_radeon_framebuffer(crtc->fb);
> 	new_radeon_fb = to_radeon_framebuffer(fb);
> 	/* schedule unpin of the old buffer */
> 	obj = old_radeon_fb->obj;
> 	rbo = gem_to_radeon_bo(obj);
> 	work->old_rbo = rbo;
>+	obj = new_radeon_fb->obj;
>+	rbo = gem_to_radeon_bo(obj);
>+	if (rbo->tbo.sync_obj)
>+		work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
> 	INIT_WORK(&work->work, radeon_unpin_work_func);
> 
> 	/* We borrow the event spin lock for protecting unpin_work */
>@@ -380,7 +376,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
> 	if (radeon_crtc->unpin_work) {
> 		spin_unlock_irqrestore(&dev->event_lock, flags);
> 		kfree(work);
>-		radeon_fence_unref(&fence);
> 
> 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
> 		return -EBUSY;
>@@ -390,9 +385,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
> 	spin_unlock_irqrestore(&dev->event_lock, flags);
> 
> 	/* pin the new buffer */
>-	obj = new_radeon_fb->obj;
>-	rbo = gem_to_radeon_bo(obj);
>-
> 	DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
> 			 work->old_rbo, rbo);
> 
>@@ -467,8 +459,6 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
> 		goto pflip_cleanup2;
> 	}
> 
>-	/* emit the fence */
>-	radeon_fence_emit(rdev, fence);
> 	/* set the proper interrupt */
> 	radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
> 	/* fire the ring */
>@@ -498,7 +488,6 @@ pflip_cleanup:
> 	spin_lock_irqsave(&dev->event_lock, flags);
> 	radeon_crtc->unpin_work = NULL;
> 	spin_unlock_irqrestore(&dev->event_lock, flags);
>-	radeon_fence_unref(&fence);
> 	kfree(work);
> 
> 	return r;

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Attachments on bug 38800: 48588 | 48589 | 48590 | 48657 | 48768 | 48883 | 48888 | 48892 | 48897 | 48898

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