Attachment 60032 Details for Bug 48740 – intel_reg_dumper output using DVI -> HDMI cable (works)

intel_reg_dumper output using DVI -> HDMI cable (works)

reg_dumper_dvi.txt (text/plain), 11.65 KB, created by Dmitry Nezhevenko on 2012-04-15 12:46:16 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Dmitry Nezhevenko

Created: 2012-04-15 12:46:16 UTC

Size: 11.65 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000008
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0x082b3019
>                FDI_PLL_BIOS_1: 0x00000000
>                FDI_PLL_BIOS_2: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_0: 0x0807012b
>       DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>              FDI_PLL_FREQ_CTL: 0x00053687
>                     PIPEACONF: 0xc0000000 (enabled, active, 8bpc)
>                      HTOTAL_A: 0x06ff054f (1360 active, 1792 total)
>                      HBLANK_A: 0x06ff054f (1360 start, 1792 end)
>                       HSYNC_A: 0x05ff058f (1424 start, 1536 end)
>                      VTOTAL_A: 0x031a02ff (768 active, 795 total)
>                      VBLANK_A: 0x031a02ff (768 start, 795 end)
>                       VSYNC_A: 0x03080302 (771 start, 777 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x054f02ff (1360, 768)
>                 PIPEA_DATA_M1: 0x7e1f4fa0 (TU 64, val 0x1f4fa0 2052000)
>                 PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x00014dfc (val 0x14dfc 85500)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004400 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00001600 (88)
>                      DSPASURF: 0x0043f000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
>                      HTOTAL_B: 0x031f027f (640 active, 800 total)
>                      HBLANK_B: 0x03170287 (648 start, 792 end)
>                       HSYNC_B: 0x02ef028f (656 start, 752 end)
>                      VTOTAL_B: 0x020c01df (480 active, 525 total)
>                      VBLANK_B: 0x020401e7 (488 start, 517 end)
>                       VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      DSPBCNTR: 0x00000000 (disabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00000000 (0)
>                      DSPBSURF: 0x00000000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x027f01df (640, 480)
>                 PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007e80 (vscale 0.988281)
>                     PFA_CTL_3: 0x00003f40 (vscale initial phase 0.494141)
>                     PFA_CTL_4: 0x00007d58 (hscale 0.979248)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00000000 (vscale 0.000000)
>                     PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
>                     PFB_CTL_4: 0x00000000 (hscale 0.000000)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00000400 (cpu source disable, ssc_source disable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x00000000
>            PCH_SSC4_AUX_PARMS: 0x00000000
>                  PCH_DPLL_SEL: 0x00000000 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0xc4080008 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 4, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00021307 (n = 2, m1 = 19, m2 = 7)
>                      PCH_FPA1: 0x00021307 (n = 2, m1 = 19, m2 = 7)
>                      PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                      PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                TRANS_HTOTAL_A: 0x06ff054f (1360 active, 1792 total)
>                TRANS_HBLANK_A: 0x06ff054f (1360 start, 1792 end)
>                 TRANS_HSYNC_A: 0x05ff058f (1424 start, 1536 end)
>                TRANS_VTOTAL_A: 0x031a02ff (768 active, 795 total)
>                TRANS_VBLANK_A: 0x031a02ff (768 start, 795 end)
>                 TRANS_VSYNC_A: 0x03080302 (771 start, 777 end)
>            TRANS_VSYNCSHIFT_A: 0x00000000
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x031f027f (640 active, 800 total)
>                TRANS_HBLANK_B: 0x03170287 (648 start, 792 end)
>                 TRANS_HSYNC_B: 0x02ef028f (656 start, 752 end)
>                TRANS_VTOTAL_B: 0x020c01df (480 active, 525 total)
>                TRANS_VBLANK_B: 0x020401e7 (488 start, 517 end)
>                 TRANS_VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>            TRANS_VSYNCSHIFT_B: 0x00000000
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000044 (69 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>            TRANS_VSYNCSHIFT_C: 0x00000000
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00ffffff (val 0xffffff 16777215)
>                    TRANSACONF: 0xc0000000 (enable, active)
>                    TRANSBCONF: 0x00000000 (disable, inactive)
>                    TRANSCCONF: 0x00000000 (disable, inactive)
>                   FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0x00044000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0xb0002050 (enable, train pattern not train, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                   FDI_RXC_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk)
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000000 (FDI Delay 0)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x00000000
>               FDI_RXC_TUSIZE2: 0x00000000
>                 FDI_PLL_CTL_1: 0x33505248
>                 FDI_PLL_CTL_2: 0x00000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000000ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000000ff
>                      PCH_ADPA: 0x00f40018 (disabled, transcoder A, +hsync, +vsync)
>                         HDMIB: 0x80000adc (enabled pipe A 8bpc TMDS HDMI audio enabled +vsync +hsync detected)
>                         HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                         HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                      PCH_LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x0000001c
>                      PCH_DP_C: 0x0000001c
>                      PCH_DP_D: 0x0000001c
>                TRANS_DP_CTL_A: 0x00000000 (disabled, pipe B, 18 bit, 1 channel)
>                TRANS_DP_CTL_B: 0x00000000 (disabled, pipe B, 18 bit, 1 channel)
>                TRANS_DP_CTL_C: 0x00000000 (disabled, pipe B, 18 bit, 1 channel)
>              BLC_PWM_CPU_CTL2: 0x00000000
>               BLC_PWM_CPU_CTL: 0x00000000
>              BLC_PWM_PCH_CTL1: 0x00000000
>              BLC_PWM_PCH_CTL2: 0x00000000
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186904
>                      PORT_DBG: 0x00000000 (HW DRRS off)
>            RC6_RESIDENCY_TIME: 0xffffffff
>           RC6p_RESIDENCY_TIME: 0xffffffff
>          RC6pp_RESIDENCY_TIME: 0xffffffff

Actions: View

Attachments on bug 48740: 60028 | 60029 | 60030 | 60031 | 60032 | 66231 | 66232 | 66233

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.