Attachment 8521 Details for Bug 5766 – This patch can limit max pixel clock within ES1000's capacity, also it resolves video corruption problem

[patch] This patch can limit max pixel clock within ES1000's capacity, also it resolves video corruption problem

rn50_pixel_clock_limit.patch (text/plain), 2.50 KB, created by LisaWu on 2007-01-28 06:36:02 UTC

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Creator: LisaWu

Created: 2007-01-28 06:36:02 UTC

Size: 2.50 KB

patch

obsolete

>--- src/radeon_driver.c	2007-01-26 17:06:48.000000000 +0800
>+++ src/radeon_driver.c.new	2007-01-26 17:06:08.000000000 +0800
>@@ -1068,18 +1068,6 @@ static void RADEONGetClockInfo(ScrnInfoP
>         info->mclk = 200.00;
>     }
> 
>-    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
>-        /* Avoid RN50 corruption due to memory bandwidth starvation.
>-         * 18 is an empirical value based on the databook and Windows driver.
>-         *
>-	 * Empirical value changed to 24 to raise pixel clock limit and
>-	 * allow higher resolution modes on capable monitors
>-	 */
>-        pll->max_pll_freq = min(pll->max_pll_freq,
>-                               24 * info->mclk * 100 / pScrn->bitsPerPixel *
>-                               info->RamWidth / 16);
>-    }
>-
>     xf86DrvMsg (pScrn->scrnIndex, X_INFO,
> 		"PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n",
> 		pll->reference_freq,
>@@ -2117,6 +2105,11 @@ static Bool RADEONPreInitModes(ScrnInfoP
>     clockRanges->interlaceAllowed  = (info->DisplayType == MT_CRT);
>     clockRanges->doubleScanAllowed = (info->DisplayType == MT_CRT);
> 
>+    if (info->ChipFamily == CHIP_FAMILY_RV100) {
>+	if(!pRADEONEnt->HasCRTC2)
>+	clockRanges->maxClock =
>+	    min(clockRanges->maxClock, (440000 / ((pScrn->bitsPerPixel+7)/8)));
>+    }
>     /* We'll use our own mode validation routine for DFP/LCD, since
>      * xf86ValidateModes does not work correctly with the DFP/LCD modes
>      * 'stretched' from their native mode.
>--- src/radeon_modes.c	2007-01-26 17:07:48.000000000 +0800
>+++ src/radeon_modes.c.new	2007-01-26 17:06:23.000000000 +0800
>@@ -625,6 +625,7 @@ int RADEONValidateFPModes(ScrnInfoPtr pS
> int RADEONValidateMergeModes(ScrnInfoPtr pScrn1)
> {
>     RADEONInfoPtr   info             = RADEONPTR(pScrn1);
>+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn1);
>     ClockRangePtr   clockRanges;
>     int             modesFound;
>     ScrnInfoPtr pScrn = info->CRT2pScrn;
>@@ -669,7 +670,11 @@ int RADEONValidateMergeModes(ScrnInfoPtr
>     clockRanges->clockIndex        = -1;
>     clockRanges->interlaceAllowed  = (info->MergeType == MT_CRT);
>     clockRanges->doubleScanAllowed = (info->MergeType == MT_CRT);
>-
>+     if (info->ChipFamily == CHIP_FAMILY_RV100 ) {
>+	if(!pRADEONEnt->HasCRTC2)
>+	clockRanges->maxClock =
>+	    min(clockRanges->maxClock, (440000 / ((pScrn->bitsPerPixel+7)/8)));
>+    }
>     /* We'll use our own mode validation routine for DFP/LCD, since
>      * xf86ValidateModes does not work correctly with the DFP/LCD modes
>      * 'stretched' from their native mode.

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Attachments on bug 5766: 4636 | 8521

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