Index: radeon.h
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v
retrieving revision 1.19
diff -u -r1.19 radeon.h
--- radeon.h	24 Mar 2005 06:45:51 -0000	1.19
+++ radeon.h	29 Mar 2005 01:57:15 -0000
@@ -667,6 +667,8 @@
 extern void        RADEONEngineRestore(ScrnInfoPtr pScrn);
 
 extern unsigned    RADEONINPLL(ScrnInfoPtr pScrn, int addr);
+extern void        RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+
 extern void        RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
 extern void        RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
 
@@ -684,6 +686,9 @@
 extern void        RADEONResetVideo(ScrnInfoPtr pScrn);
 extern void        R300CGWorkaround(ScrnInfoPtr pScrn);
 
+extern void        RADEONPllErrataAfterIndex(RADEONInfoPtr info);
+extern void        RADEONPllErrataAfterData(RADEONInfoPtr info);
+
 #ifdef XF86DRI
 extern void        RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
 extern Bool        RADEONDRIScreenInit(ScreenPtr pScreen);
Index: radeon_driver.c
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v
retrieving revision 1.46
diff -u -r1.46 radeon_driver.c
--- radeon_driver.c	24 Mar 2005 06:45:51 -0000	1.46
+++ radeon_driver.c	29 Mar 2005 01:57:17 -0000
@@ -712,6 +712,48 @@
     return TRUE;
 }
 
+void RADEONPllErrataAfterIndex(RADEONInfoPtr info)
+{
+    unsigned char *RADEONMMIO = info->MMIO;
+	
+    if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
+	return;
+
+    /* This workaround is necessary on rv200 and RS200 or PLL
+     * reads may return garbage (among others...)
+     */
+    (void)INREG(RADEON_CLOCK_CNTL_DATA);
+    (void)INREG(RADEON_CRTC_GEN_CNTL);
+}
+
+void RADEONPllErrataAfterData(RADEONInfoPtr info)
+{
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    /* This workarounds is necessary on RV100, RS100 and RS200 chips
+     * or the chip could hang on a subsequent access
+     */
+    if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) {
+	/* we can't deal with posted writes here ... */
+	usleep(5000);
+    }
+
+    /* This function is required to workaround a hardware bug in some (all?)
+     * revisions of the R300.  This workaround should be called after every
+     * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
+     * may not be correct.
+     */
+    if (info->ChipErrata & CHIP_ERRATA_R300_CG) {
+	CARD32         save, tmp;
+
+	save = INREG(RADEON_CLOCK_CNTL_INDEX);
+	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
+	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
+	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
+	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
+    }
+}
+
 /* Read PLL register */
 unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr)
 {
@@ -728,7 +770,7 @@
 }
 
 /* Write PLL information */
-unsigned RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data)
+void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
@@ -5727,9 +5769,6 @@
 
 static void RADEONPLLWriteUpdate(ScrnInfoPtr pScrn)
 {
-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-
     while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 
     OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
@@ -5753,9 +5792,6 @@
 
 static void RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn)
 {
-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-
     while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 
     OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
@@ -5869,9 +5905,6 @@
 static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
 				       RADEONSavePtr restore)
 {
-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-
     OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
 	    RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 	    ~(RADEON_PIX2CLK_SRC_SEL_MASK));
Index: radeon_macros.h
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v
retrieving revision 1.4
diff -u -r1.4 radeon_macros.h
--- radeon_macros.h	24 Mar 2005 06:45:51 -0000	1.4
+++ radeon_macros.h	29 Mar 2005 01:57:17 -0000
@@ -133,46 +133,4 @@
     }									\
 } while (0)
 
-static void RADEONPllErrataAfterIndex(RADEONInfoPtr info)
-{
-    unsigned char *RADEONMMIO = info->MMIO;
-	
-    if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
-	return;
-
-    /* This workaround is necessary on rv200 and RS200 or PLL
-     * reads may return garbage (among others...)
-     */
-    (void)INREG(RADEON_CLOCK_CNTL_DATA);
-    (void)INREG(RADEON_CRTC_GEN_CNTL);
-}
-
-static void RADEONPllErrataAfterData(RADEONInfoPtr info)
-{
-    unsigned char *RADEONMMIO = info->MMIO;
-
-    /* This workarounds is necessary on RV100, RS100 and RS200 chips
-     * or the chip could hang on a subsequent access
-     */
-    if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) {
-	/* we can't deal with posted writes here ... */
-	usleep(5000);
-    }
-
-    /* This function is required to workaround a hardware bug in some (all?)
-     * revisions of the R300.  This workaround should be called after every
-     * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
-     * may not be correct.
-     */
-    if (info->ChipErrata & CHIP_ERRATA_R300_CG) {
-	CARD32         save, tmp;
-
-	save = INREG(RADEON_CLOCK_CNTL_INDEX);
-	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
-	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
-	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
-	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
-    }
-}
-
 #endif