* compute_memory_pool_new()
--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }

===== SHADER #1 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 12 dw ===== 3 gprs ===== 0 stack =========================================
0000  00000002 80800400 VTX 2 @4
 0004  7c000000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0008  7c000000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }

===== SHADER #2 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }

===== SHADER #3 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }

===== SHADER #4 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }

===== SHADER #5 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

[SLG] Reading configuration file: scenes/luxball/luxball.cfg
[SLG] Configuration: 
[SLG]   image.width = 640
[SLG]   image.height = 480
[SLG]   batch.halttime = 0
[SLG]   scene.file = scenes/luxball/luxball.scn
[SLG]   scene.fieldofview = 45
[SLG]   opencl.cpu.use = 0
[SLG]   opencl.gpu.use = 1
[SLG]   opencl.platform.index = 0
[SLG]   opencl.gpu.workgroup.size = 64
[SLG]   screen.refresh.interval = 100
[SLG]   film.gamma = 2.2
[SLG]   path.maxdepth = 16
[SLG]   path.russianroulette.depth = 5
[SLG]   light.maxdepth = 16
[SLG]   light.russianroulette.depth = 5
[SLG]   accelerator.imagestorage.enable = 0
[SDL] Reading scene: scenes/luxball/luxball.scn
[SDL] Camera position: Point[0.5, -1.4, 1.7]
[SDL] Camera target: Point[0, 0, 0.4]
[SDL] Camera horizontal stereo disabled
[SDL] Material definition: shell
[SDL] Material definition: whitematte
[SDL] Material definition: luxtext
[SDL] Material definition: blacktext
[SDL] Material definition: whitelight
[SDL] The l1 object is a light source with 2 triangles
[SDL] The l2 object is a light source with 2 triangles
[SDL] PLY object count: 7
* compute_memory_pool_new()
--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }

===== SHADER #1 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 12 dw ===== 3 gprs ===== 0 stack =========================================
0000  00000002 80800400 VTX 2 @4
 0004  7c000000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0008  7c000000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }

===== SHADER #2 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }

===== SHADER #3 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }

===== SHADER #4 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }

===== SHADER #5 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }

===== SHADER #6 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 12 dw ===== 3 gprs ===== 0 stack =========================================
0000  00000002 80800400 VTX 2 @4
 0004  7c000000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0008  7c000000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }

===== SHADER #7 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }

===== SHADER #8 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }

===== SHADER #9 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }

===== SHADER #10 =================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

[LuxRays] OpenCL Platform 0: Mesa
[LuxRays] Device 0 name: NativeThread
[LuxRays] Device 0 type: NATIVE_THREAD
[LuxRays] Device 0 compute units: 1
[LuxRays] Device 0 preferred float vector width: 4
[LuxRays] Device 0 max allocable memory: 0MBytes
[LuxRays] Device 0 max allocable memory block size: 0MBytes
[LuxRays] Device 1 name: AMD CEDAR
[LuxRays] Device 1 type: OPENCL_GPU
[LuxRays] Device 1 compute units: 2
[LuxRays] Device 1 preferred float vector width: 4
[LuxRays] Device 1 max allocable memory: 192MBytes
[LuxRays] Device 1 max allocable memory block size: 48MBytes
[LuxRays] Preprocessing DataSet
[LuxRays] Total vertex count: 223380
[LuxRays] Total triangle count: 260794
[LuxRays] Preprocessing DataSet done
[LuxRays] Creating 1 intersection device(s)
[LuxRays] Allocating intersection device 0: AMD CEDAR (Type = OPENCL_GPU)
[SLG] OpenCL Devices used:
[SLG] [AMD CEDARIntersect]
[SLG]   Device OpenCL version: OpenCL 1.1 MESA 10.3.0-devel
[LuxRays] Adding DataSet accelerator: QBVH
[LuxRays] Total vertex count: 223380
[LuxRays] Total triangle count: 260794
[LuxRays] Building QBVH, primitives: 260794, initial nodes: 21734
[LuxRays] QBVH completed with 43467/43468 nodes
[LuxRays] Total QBVH memory usage: 4754Kbytes
[LuxRays] Total QBVH QuadTriangle count: 87103
[LuxRays] Max. QBVH Depth: 25
[SLG] Configuring 1 CPU render threads
[LuxRays] [OpenCL device::AMD CEDARIntersect] QBVH max. stack size: 32
[LuxRays] [OpenCL device::AMD CEDARIntersect] Disable forced for QBVH scene storage inside image
[LuxRays] [OpenCL device::AMD CEDARIntersect] QBVH buffer size: 4754Kbytes
[LuxRays] [OpenCL device::AMD CEDARIntersect] QuadTriangle buffer size: 14970Kbytes
--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }

===== SHADER #6 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 12 dw ===== 3 gprs ===== 0 stack =========================================
0000  00000002 80800400 VTX 2 @4
 0004  7c000000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0008  7c000000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }

===== SHADER #7 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 93564001 00080000 VFETCH              R1.x001, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:13 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_UINT, }

===== SHADER #8 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 97561001 00080000 VFETCH              R1.xy01, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:29 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32_UINT, }

===== SHADER #9 ==================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 9bd51001 00080000 VFETCH              R1.xyz1, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:47 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_UINT, }

===== SHADER #10 =================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 988d1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:34 NUM:1 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

[SLG] [PathOCLRenderEngine] OpenCL task count: 65536
[SLG] [PathOCLRenderEngine] OpenCL max. page memory size: 49152Kbytes
[SLG] [PathOCLRenderThread::CompiledScene] Compile Geometry
[SLG] [PathOCLRenderThread::CompiledScene] Scene geometry compilation time: 5ms
[SLG] [PathOCLRenderThread::CompiledScene] Compile Materials
[SLG] [PathOCLRenderThread::CompiledScene] Compile Textures
[SLG] [PathOCLRenderThread::CompiledScene] Textures compilation time: 0ms
[SLG] [PathOCLRenderThread::CompiledScene] Material compilation time: 0ms
[SLG] [PathOCLRenderThread::CompiledScene] Compile Triangle AreaLights
[SLG] [PathOCLRenderThread::CompiledScene] Triangle area lights compilation time: 0ms
[SLG] [PathOCLRenderThread::CompiledScene] Compile InfiniteLight
[SLG] [PathOCLRenderThread::CompiledScene] Infinitelight compilation time: 0ms
[SLG] [PathOCLRenderThread::CompiledScene] Compile SunLight
[SLG] [PathOCLRenderThread::CompiledScene] Compile SkyLight
[SLG] [PathOCLRenderThread::CompiledScene] Compile ImageMaps
[SLG] [PathOCLRenderThread::CompiledScene] Image maps page count: 0
[SLG] [PathOCLRenderThread::CompiledScene] Texture maps compilation time: 0ms
[SLG] Starting 1 PathOCL render threads
[SLG] [PathOCLRenderThread::0] FrameBuffer buffer size: 4835Kbytes
[SLG] [PathOCLRenderThread::0] Camera buffer size: 528bytes
[SLG] [PathOCLRenderThread::0] Normals buffer size: 2617Kbytes
[SLG] [PathOCLRenderThread::0] UVs buffer size: 318Kbytes
[SLG] [PathOCLRenderThread::0] Colors buffer size: 553Kbytes
[SLG] [PathOCLRenderThread::0] Vertices buffer size: 2617Kbytes
[SLG] [PathOCLRenderThread::0] Triangles buffer size: 3056Kbytes
[SLG] [PathOCLRenderThread::0] Mesh description buffer size: 1064bytes
[SLG] [PathOCLRenderThread::0] Textures buffer size: 2412bytes
[SLG] [PathOCLRenderThread::0] Materials buffer size: 240bytes
[SLG] [PathOCLRenderThread::0] Mesh material index buffer size: 28bytes
[SLG] [PathOCLRenderThread::0] Triangle AreaLights buffer size: 272bytes
[SLG] [PathOCLRenderThread::0] Triangle AreaLights offsets buffer size: 28bytes
[SLG] [PathOCLRenderThread::0] Ray buffer size: 3072Kbytes
[SLG] [PathOCLRenderThread::0] RayHit buffer size: 1280Kbytes
[SLG] [PathOCLRenderThread::0] GPUTask Stats buffer size: 256Kbytes
[SLG] [PathOCLRenderThread::0] Size of a GPUTask: 336bytes
[SLG] [PathOCLRenderThread::0] GPUTask buffer size: 21504Kbytes
[SLG] [PathOCLRenderThread::0] Sample dimensions: 147
[SLG] [PathOCLRenderThread::0] Size of a SampleData: 8bytes
[SLG] [PathOCLRenderThread::0] SampleData buffer size: 512Kbytes
[SLG] [PathOCLRenderThread::0] Defined symbols:  -D LUXRAYS_OPENCL_KERNEL -D SLG_OPENCL_KERNEL -D PARAM_TASK_COUNT=65536 -D PARAM_IMAGE_WIDTH=640 -D PARAM_IMAGE_HEIGHT=480 -D PARAM_RAY_EPSILON_MIN=1.000000e-09f -D PARAM_RAY_EPSILON_MAX=1.000000e-01f -D PARAM_MAX_PATH_DEPTH=16 -D PARAM_RR_DEPTH=5 -D PARAM_RR_CAP=5.000000e-01f -D PARAM_ACCEL_QBVH -D PARAM_HAS_NORMALS_BUFFER -D PARAM_HAS_UVS_BUFFER -D PARAM_HAS_COLS_BUFFER -D PARAM_ENABLE_TEX_CONST_FLOAT -D PARAM_ENABLE_TEX_CONST_FLOAT3 -D PARAM_ENABLE_MAT_MATTE -D PARAM_ENABLE_MAT_GLASS -D PARAM_HAS_PASSTHROUGH -D PARAM_DIRECT_LIGHT_SAMPLING -D PARAM_DL_LIGHT_COUNT=4 -D PARAM_IMAGE_FILTER_TYPE=0 -D PARAM_SAMPLER_TYPE=0 -D PARAM_DEVICE_INDEX=0 -D PARAM_DEVICE_COUNT=1 -D PARAM_TONEMAP_LINEAR_SCALE=1.000000e+00f -D PARAM_GAMMA=2.200000e+00f
[SLG] [PathOCLRenderThread::0] Compiling kernels 
[SLG] [PathOCLRenderThread::0] Kernels not cached
[SLG] [PathOCLRenderThread::0] Compiling Init Kernel
[SLG] [PathOCLRenderThread::0] Compiling InitFrameBuffer Kernel
[SLG] [PathOCLRenderThread::0] Compiling AdvancePaths Kernel
[SLG] [PathOCLRenderThread::0] Kernels compilation time: 295ms
*** r600_compute_global_buffer_create
width = 4951104 array_size = 0
* compute_memory_alloc() size_in_dw = 1237776 (4951104 bytes)
  + Adding item 0x436e4a0 id = 0 size = 1237776 (4951104 bytes)
*** evergreen_create_compute_state
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 1
* compute_memory_finalize_pending()
* compute_memory_grow_pool() new_size_in_dw = 1238016 (4952064 bytes)
* compute_memory_pool_init() initial_size_in_dw = 1238016
* compute_memory_prealloc_chunk() size_in_dw = 1237776
  + Found space for Item 0x436e4a0 id = 0 start_in_dw = 0 (0 bytes) size_in_dw = 1237776 (4951104 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 0
bind rat: 0 
*** evergreen_launch_grid: pc = 1
; ModuleID = 'radeon'
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"

%struct.Pixel.58 = type { %struct.Spectrum.43, float }
%struct.Spectrum.43 = type { float, float, float }

; Function Attrs: nounwind
define void @InitFrameBuffer(%struct.Pixel.58 addrspace(1)* nocapture %frameBuffer) #0 {
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i8.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %1 = mul i32 %x.i8.i, %x.i.i
  %x.i1.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %2 = add i32 %x.i1.i, %1
  %3 = icmp ugt i32 %2, 309443
  br i1 %3, label %7, label %4

; <label>:4                                       ; preds = %0
  %5 = getelementptr inbounds %struct.Pixel.58 addrspace(1)* %frameBuffer, i32 %2, i32 0, i32 0
  %6 = bitcast float addrspace(1)* %5 to <4 x float> addrspace(1)*
  store <4 x float> zeroinitializer, <4 x float> addrspace(1)* %6, align 4, !tbaa !14
  br label %7

; <label>:7                                       ; preds = %4, %0
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.x() #1

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.x() #1

attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }

!opencl.kernels = !{!0, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11}
!llvm.ident = !{!12, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13}

!0 = metadata !{null, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 64, i32 1, i32 1}
!2 = metadata !{void (%struct.Pixel.58 addrspace(1)*)* @InitFrameBuffer, metadata !1}
!3 = metadata !{null, metadata !1}
!4 = metadata !{null, metadata !1}
!5 = metadata !{null, metadata !1}
!6 = metadata !{null, metadata !1}
!7 = metadata !{null, metadata !1}
!8 = metadata !{null, metadata !1}
!9 = metadata !{null, metadata !1}
!10 = metadata !{null, metadata !1}
!11 = metadata !{null}
!12 = metadata !{metadata !"clang version 3.5.0 (trunk 212264) (llvm/trunk 212275)"}
!13 = metadata !{metadata !"clang version 3.5.0 (trunk 212142) (llvm/trunk 212143)"}
!14 = metadata !{metadata !15, metadata !15, i64 0}
!15 = metadata !{metadata !"float", metadata !16, i64 0}
!16 = metadata !{metadata !"omnipotent char", metadata !17, i64 0}
!17 = metadata !{metadata !"Simple C/C++ TBAA"}

Shader Disassembly:

	ALU_PUSH_BEFORE 4, @6, KC0[CB0:0-32], KC1[]                            ; 80000006 A4100000
	JUMP @5 POP:1                                                          ; 00000005 82800001
	ALU 9, @11, KC0[CB0:0-32], KC1[]                                       ; 8000000B A0240000
	MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 0                           ; 0000A020 95C0F000
	POP @5 POP:1                                                           ; 00000005 83800001
	CF_END                                                                 ; 00000000 80200000
	ALU clause starting at 6:                                              ; 
	  MULLO_INT             * T0.Y, KC0[1].Z, T1.X,                        ; 80002881 20004790
	  ADD_INT               * T0.W, T0.X, PS,                              ; 801FE000 60001A10
	  SETGT_UINT            * T1.W, PV.W, literal.x,                       ; 801FACFE 60201F10
	309443(4.336220e-40), 0(0.000000e+00)                                  ; 0004B8C3 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,   ; 801F0CFE 00002104
	ALU clause starting at 11:                                             ; 
	  MOV                     T1.X, 0.0,                                   ; 000000F8 00200C90
	  MOV                     T1.Y, 0.0,                                   ; 000000F8 20200C90
	  MOV                     T1.Z, 0.0,                                   ; 000000F8 40200C90
	  MOV                     T1.W, 0.0,                                   ; 000000F8 60200C90
	  MOV                   * T2.W, KC0[2].Y,                              ; 80000482 60400C90
	  LSHL                  * T0.W, T0.W, literal.x,                       ; 801FAC00 60000B90
	4(5.605194e-45), 0(0.000000e+00)                                       ; 00000004 00000000
	  ADD_INT               * T0.W, T2.W, PV.W,                            ; 819FCC02 60001A10
	  LSHR                  * T0.X, PV.W, literal.x,                       ; 801FACFE 00000B10
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000

bytecode 42 dw -- 3 gprs -- 1 nstack -------------
shader 0 -- E
--------------------------------------
input 0 : 4836
input 1 : 1
input 2 : 1
input 3 : 309504
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 0
Using 2 pipes, 2 wavefronts per thread block, allocating 0 dwords lds.
*** evergreen_set_global_binding first = 0 n = 1
*** evergreen_set_compute_resources: start = 0 count = 0
*** r600_compute_global_buffer_create
width = 22020096 array_size = 0
* compute_memory_alloc() size_in_dw = 5505024 (22020096 bytes)
  + Adding item 0x328d810 id = 1 size = 5505024 (22020096 bytes)
*** r600_compute_global_buffer_create
width = 524289 array_size = 0
* compute_memory_alloc() size_in_dw = 131073 (524292 bytes)
  + Adding item 0x3212270 id = 2 size = 131073 (524292 bytes)
*** r600_compute_global_buffer_create
width = 262144 array_size = 0
* compute_memory_alloc() size_in_dw = 65536 (262144 bytes)
  + Adding item 0x3503560 id = 3 size = 65536 (262144 bytes)
*** r600_compute_global_buffer_create
width = 3145728 array_size = 0
* compute_memory_alloc() size_in_dw = 786432 (3145728 bytes)
  + Adding item 0x39b91d0 id = 4 size = 786432 (3145728 bytes)
*** r600_compute_global_buffer_create
width = 528 array_size = 0
* compute_memory_alloc() size_in_dw = 132 (528 bytes)
  + Adding item 0x3520460 id = 5 size = 132 (528 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 528, height = 1, depth = 1)
Buffer id = 5 offset = 0 (box.x)
*** evergreen_create_compute_state
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 5
* compute_memory_finalize_pending()
  + list: offset = 0 id = 0 size = 1237776 (4951104 bytes)
* compute_memory_grow_pool() new_size_in_dw = 7728128 (30912512 bytes)
  Aligned size = 7728128 (30912512 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 4952064
* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 30912512
* compute_memory_prealloc_chunk() size_in_dw = 5505024
  + Found space for Item 0x328d810 id = 1 start_in_dw = 1238016 (4952064 bytes) size_in_dw = 5505024 (22020096 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 1238016
* compute_memory_prealloc_chunk() size_in_dw = 131073
  + Found space for Item 0x3212270 id = 2 start_in_dw = 6743040 (26972160 bytes) size_in_dw = 131073 (524292 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 6743040
* compute_memory_prealloc_chunk() size_in_dw = 65536
  + Found space for Item 0x3503560 id = 3 start_in_dw = 6875136 (27500544 bytes) size_in_dw = 65536 (262144 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 6875136
* compute_memory_prealloc_chunk() size_in_dw = 786432
  + Found space for Item 0x39b91d0 id = 4 start_in_dw = 6940672 (27762688 bytes) size_in_dw = 786432 (3145728 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 6940672
* compute_memory_prealloc_chunk() size_in_dw = 132
  + Found space for Item 0x3520460 id = 5 start_in_dw = 7727104 (30908416 bytes) size_in_dw = 132 (528 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 7727104
bind rat: 0 
*** evergreen_launch_grid: pc = 0
; ModuleID = 'radeon'
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"

%struct.GPUTask.32 = type { %struct.Seed.6, %struct.RandomSample.25, %struct.PathStateBase.29, %struct.PathStateDirectLight.30, %struct.PathStateDirectLightPassThrough.31 }
%struct.Seed.6 = type { i32, i32, i32 }
%struct.RandomSample.25 = type { %struct.Spectrum.9 }
%struct.Spectrum.9 = type { float, float, float }
%struct.PathStateBase.29 = type { i32, i32, %struct.Spectrum.9, %struct.BSDF.26 }
%struct.BSDF.26 = type { %struct.HitPoint.14, i32, i32, %struct.Frame.4 }
%struct.HitPoint.14 = type { %struct.Vector.1, %struct.Point.0, %struct.UV.8, %struct.Normal.13, %struct.Normal.13, float }
%struct.Vector.1 = type { float, float, float }
%struct.Point.0 = type { float, float, float }
%struct.UV.8 = type { float, float }
%struct.Normal.13 = type { float, float, float }
%struct.Frame.4 = type { %struct.Vector.1, %struct.Vector.1, %struct.Vector.1 }
%struct.PathStateDirectLight.30 = type { %struct.Spectrum.9, float, i32, %struct.HitPoint.14 }
%struct.PathStateDirectLightPassThrough.31 = type { float, %struct.BSDF.26 }
%struct.GPUTaskStats.33 = type { i32 }
%struct.Ray.2 = type { %struct.Point.0, %struct.Vector.1, float, float, float, [3 x float] }
%struct.Camera.22 = type { [2 x %struct.Transform.5], [2 x %struct.Transform.5], float, float, float, float }
%struct.Transform.5 = type { %struct.Matrix4x4.3, %struct.Matrix4x4.3 }
%struct.Matrix4x4.3 = type { [4 x [4 x float]] }

; Function Attrs: nounwind readnone
declare float @llvm.fabs.f32(float) #0

; Function Attrs: nounwind readnone
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare float @llvm.sqrt.f32(float) #0

; Function Attrs: nounwind
define void @Init(i32 %seedBase, %struct.GPUTask.32 addrspace(1)* nocapture %tasks, float addrspace(1)* nocapture %samplesData, %struct.GPUTaskStats.33 addrspace(1)* nocapture %taskStats, %struct.Ray.2 addrspace(1)* nocapture %rays, %struct.Camera.22 addrspace(1)* readonly %camera) #1 {
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #0
  %x.i8.i = tail call i32 @llvm.r600.read.local.size.x() #0
  %1 = mul i32 %x.i8.i, %x.i.i
  %x.i1.i = tail call i32 @llvm.r600.read.tidig.x() #0
  %2 = add i32 %x.i1.i, %1
  %3 = icmp ugt i32 %2, 65535
  br i1 %3, label %291, label %4

; <label>:4                                       ; preds = %0
  %5 = add i32 %2, %seedBase
  %6 = icmp eq i32 %5, 0
  %7 = add i32 %5, 16777215
  %8 = select i1 %6, i32 %7, i32 %5
  %9 = mul i32 %8, 69069
  %10 = icmp eq i32 %9, 0
  %11 = zext i1 %10 to i32
  %.x.i2.i = add i32 %11, %9
  %12 = mul i32 %.x.i2.i, 69069
  %13 = icmp ult i32 %12, 7
  %14 = select i1 %13, i32 7, i32 0
  %.x.i1.i = add i32 %14, %12
  %15 = mul i32 %.x.i1.i, 69069
  %16 = icmp ult i32 %15, 15
  %17 = select i1 %16, i32 15, i32 0
  %.x.i.i = add i32 %17, %15
  %18 = shl i32 %2, 1
  %19 = getelementptr inbounds float addrspace(1)* %samplesData, i32 %18
  %20 = shl i32 %.x.i2.i, 12
  %21 = and i32 %20, -8192
  %22 = shl i32 %.x.i2.i, 13
  %23 = xor i32 %22, %.x.i2.i
  %24 = lshr i32 %23, 19
  %25 = or i32 %24, %21
  %26 = shl i32 %.x.i1.i, 4
  %27 = and i32 %26, -128
  %28 = shl i32 %.x.i1.i, 2
  %29 = xor i32 %28, %.x.i1.i
  %30 = lshr i32 %29, 25
  %31 = or i32 %30, %27
  %32 = shl i32 %.x.i.i, 17
  %33 = and i32 %32, -2097152
  %34 = shl i32 %.x.i.i, 3
  %35 = xor i32 %34, %.x.i.i
  %36 = lshr i32 %35, 11
  %37 = or i32 %36, %33
  %38 = xor i32 %31, %25
  %39 = xor i32 %38, %37
  %40 = zext i32 %39 to i64
  %41 = and i64 %40, 16777215
  %42 = uitofp i64 %41 to float
  %43 = fmul float %42, 0x3E70000000000000
  store float %43, float addrspace(1)* %19, align 4, !tbaa !14
  %44 = shl i32 %25, 12
  %45 = and i32 %44, -8192
  %46 = shl i32 %25, 13
  %47 = xor i32 %46, %20
  %48 = lshr i32 %47, 19
  %49 = or i32 %48, %45
  %50 = shl i32 %31, 4
  %51 = and i32 %50, -128
  %52 = shl i32 %.x.i1.i, 6
  %53 = xor i32 %52, %26
  %54 = lshr i32 %53, 25
  %55 = or i32 %51, %54
  %56 = shl i32 %36, 17
  %57 = and i32 %56, -2097152
  %58 = shl i32 %37, 3
  %59 = xor i32 %58, %37
  %60 = lshr i32 %59, 11
  %61 = or i32 %60, %57
  %62 = xor i32 %55, %49
  %63 = xor i32 %62, %61
  %64 = zext i32 %63 to i64
  %65 = and i64 %64, 16777215
  %66 = uitofp i64 %65 to float
  %67 = fmul float %66, 0x3E70000000000000
  %.sum1 = or i32 %18, 1
  %68 = getelementptr inbounds float addrspace(1)* %samplesData, i32 %.sum1
  store float %67, float addrspace(1)* %68, align 4, !tbaa !14
  %69 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 1, i32 0, i32 0
  store float 0.000000e+00, float addrspace(1)* %69, align 4, !tbaa !14
  %70 = getelementptr inbounds float addrspace(1)* %69, i32 1
  store float 0.000000e+00, float addrspace(1)* %70, align 4, !tbaa !14
  %71 = getelementptr inbounds float addrspace(1)* %69, i32 2
  store float 0.000000e+00, float addrspace(1)* %71, align 4, !tbaa !14
  %72 = load float addrspace(1)* %19, align 4, !tbaa !14
  %73 = load float addrspace(1)* %68, align 4, !tbaa !14
  %74 = shl i32 %49, 12
  %75 = and i32 %74, -8192
  %76 = shl i32 %49, 13
  %77 = xor i32 %76, %44
  %78 = lshr i32 %77, 19
  %79 = or i32 %78, %75
  %80 = shl i32 %55, 4
  %81 = and i32 %80, -128
  %82 = shl i32 %.x.i1.i, 10
  %83 = xor i32 %50, %82
  %84 = lshr i32 %83, 25
  %85 = or i32 %81, %84
  %86 = shl i32 %60, 17
  %87 = and i32 %86, -2097152
  %88 = shl i32 %61, 3
  %89 = xor i32 %88, %61
  %90 = lshr i32 %89, 11
  %91 = or i32 %90, %87
  %92 = xor i32 %85, %79
  %93 = xor i32 %92, %91
  %94 = zext i32 %93 to i64
  %95 = and i64 %94, 16777215
  %96 = uitofp i64 %95 to float
  %97 = fmul float %96, 0x3E70000000000000
  %98 = fmul float %72, 6.400000e+02
  %99 = fcmp olt float %98, 6.390000e+02
  %100 = select i1 %99, float %98, float 6.390000e+02
  %101 = fsub float 1.000000e+00, %73
  %102 = fmul float %101, 4.800000e+02
  %103 = fcmp olt float %102, 4.790000e+02
  %104 = select i1 %103, float %102, float 4.790000e+02
  %105 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 0
  %106 = load float addrspace(1)* %105, align 4, !tbaa !14
  %107 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 1
  %108 = load float addrspace(1)* %107, align 4, !tbaa !14
  %109 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 2
  %110 = load float addrspace(1)* %109, align 4, !tbaa !14
  %111 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 3
  %112 = load float addrspace(1)* %111, align 4, !tbaa !14
  %113 = fmul float %108, %104
  %114 = tail call float @llvm.fmuladd.f32(float %106, float %100, float %113) #2
  %115 = tail call float @llvm.fmuladd.f32(float %110, float 0.000000e+00, float %114) #2
  %116 = tail call float @llvm.fmuladd.f32(float %112, float 1.000000e+00, float %115) #2
  %117 = fdiv float 1.000000e+00, %116, !fpmath !18
  %118 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0
  %119 = load float addrspace(1)* %118, align 4, !tbaa !14
  %120 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1
  %121 = load float addrspace(1)* %120, align 4, !tbaa !14
  %122 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2
  %123 = load float addrspace(1)* %122, align 4, !tbaa !14
  %124 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3
  %125 = load float addrspace(1)* %124, align 4, !tbaa !14
  %126 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0
  %127 = load float addrspace(1)* %126, align 4, !tbaa !14
  %128 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1
  %129 = load float addrspace(1)* %128, align 4, !tbaa !14
  %130 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 2
  %131 = load float addrspace(1)* %130, align 4, !tbaa !14
  %132 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 3
  %133 = load float addrspace(1)* %132, align 4, !tbaa !14
  %134 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0
  %135 = load float addrspace(1)* %134, align 4, !tbaa !14
  %136 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 1
  %137 = load float addrspace(1)* %136, align 4, !tbaa !14
  %138 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 2
  %139 = load float addrspace(1)* %138, align 4, !tbaa !14
  %140 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 3
  %141 = load float addrspace(1)* %140, align 4, !tbaa !14
  %142 = fmul float %104, %121
  %143 = tail call float @llvm.fmuladd.f32(float %119, float %100, float %142) #2
  %144 = tail call float @llvm.fmuladd.f32(float %123, float 0.000000e+00, float %143) #2
  %145 = tail call float @llvm.fmuladd.f32(float %125, float 1.000000e+00, float %144) #2
  %146 = fmul float %117, %145
  %147 = insertelement <3 x float> undef, float %146, i32 0
  %148 = fmul float %104, %129
  %149 = tail call float @llvm.fmuladd.f32(float %127, float %100, float %148) #2
  %150 = tail call float @llvm.fmuladd.f32(float %131, float 0.000000e+00, float %149) #2
  %151 = tail call float @llvm.fmuladd.f32(float %133, float 1.000000e+00, float %150) #2
  %152 = fmul float %117, %151
  %153 = insertelement <3 x float> %147, float %152, i32 1
  %154 = fmul float %104, %137
  %155 = tail call float @llvm.fmuladd.f32(float %135, float %100, float %154) #2
  %156 = tail call float @llvm.fmuladd.f32(float %139, float 0.000000e+00, float %155) #2
  %157 = tail call float @llvm.fmuladd.f32(float %141, float 1.000000e+00, float %156) #2
  %158 = fmul float %117, %157
  %159 = insertelement <3 x float> %153, float %158, i32 2
  %160 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 5
  %161 = load float addrspace(1)* %160, align 4, !tbaa !19
  %162 = fmul float %152, %152
  %163 = tail call float @llvm.fmuladd.f32(float %146, float %146, float %162) #2
  %164 = tail call float @llvm.fmuladd.f32(float %158, float %158, float %163) #2
  %165 = tail call float @llvm.sqrt.f32(float %164) #3
  %166 = insertelement <3 x float> undef, float %165, i32 0
  %167 = shufflevector <3 x float> %166, <3 x float> undef, <3 x i32> zeroinitializer
  %168 = fdiv <3 x float> %159, %167, !fpmath !18
  %169 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 4
  %170 = load float addrspace(1)* %169, align 4, !tbaa !21
  %171 = fsub float %170, %161
  %172 = extractelement <3 x float> %168, i32 2
  %173 = fdiv float %171, %172, !fpmath !18
  %174 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 0
  %175 = load float addrspace(1)* %174, align 4, !tbaa !14
  %176 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 1
  %177 = load float addrspace(1)* %176, align 4, !tbaa !14
  %178 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 2
  %179 = load float addrspace(1)* %178, align 4, !tbaa !14
  %180 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 3
  %181 = load float addrspace(1)* %180, align 4, !tbaa !14
  %182 = fmul float %152, %177
  %183 = tail call float @llvm.fmuladd.f32(float %175, float %146, float %182) #2
  %184 = tail call float @llvm.fmuladd.f32(float %179, float %158, float %183) #2
  %185 = tail call float @llvm.fmuladd.f32(float %181, float 1.000000e+00, float %184) #2
  %186 = fdiv float 1.000000e+00, %185, !fpmath !18
  %187 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0
  %188 = load float addrspace(1)* %187, align 4, !tbaa !14
  %189 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1
  %190 = load float addrspace(1)* %189, align 4, !tbaa !14
  %191 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 2
  %192 = load float addrspace(1)* %191, align 4, !tbaa !14
  %193 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 3
  %194 = load float addrspace(1)* %193, align 4, !tbaa !14
  %195 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 0
  %196 = load float addrspace(1)* %195, align 4, !tbaa !14
  %197 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 1
  %198 = load float addrspace(1)* %197, align 4, !tbaa !14
  %199 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 2
  %200 = load float addrspace(1)* %199, align 4, !tbaa !14
  %201 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 3
  %202 = load float addrspace(1)* %201, align 4, !tbaa !14
  %203 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 0
  %204 = load float addrspace(1)* %203, align 4, !tbaa !14
  %205 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 1
  %206 = load float addrspace(1)* %205, align 4, !tbaa !14
  %207 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 2
  %208 = load float addrspace(1)* %207, align 4, !tbaa !14
  %209 = getelementptr inbounds %struct.Camera.22 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 3
  %210 = load float addrspace(1)* %209, align 4, !tbaa !14
  %211 = fmul float %152, %190
  %212 = tail call float @llvm.fmuladd.f32(float %188, float %146, float %211) #2
  %213 = tail call float @llvm.fmuladd.f32(float %192, float %158, float %212) #2
  %214 = tail call float @llvm.fmuladd.f32(float %194, float 1.000000e+00, float %213) #2
  %215 = fmul float %186, %214
  %216 = fmul float %152, %198
  %217 = tail call float @llvm.fmuladd.f32(float %196, float %146, float %216) #2
  %218 = tail call float @llvm.fmuladd.f32(float %200, float %158, float %217) #2
  %219 = tail call float @llvm.fmuladd.f32(float %202, float 1.000000e+00, float %218) #2
  %220 = fmul float %186, %219
  %221 = fmul float %152, %206
  %222 = tail call float @llvm.fmuladd.f32(float %204, float %146, float %221) #2
  %223 = tail call float @llvm.fmuladd.f32(float %208, float %158, float %222) #2
  %224 = tail call float @llvm.fmuladd.f32(float %210, float 1.000000e+00, float %223) #2
  %225 = fmul float %186, %224
  %226 = extractelement <3 x float> %168, i32 0
  %227 = extractelement <3 x float> %168, i32 1
  %228 = fmul float %227, %190
  %229 = tail call float @llvm.fmuladd.f32(float %188, float %226, float %228) #2
  %230 = tail call float @llvm.fmuladd.f32(float %192, float %172, float %229) #2
  %231 = fmul float %227, %198
  %232 = tail call float @llvm.fmuladd.f32(float %196, float %226, float %231) #2
  %233 = tail call float @llvm.fmuladd.f32(float %200, float %172, float %232) #2
  %234 = fmul float %227, %206
  %235 = tail call float @llvm.fmuladd.f32(float %204, float %226, float %234) #2
  %236 = tail call float @llvm.fmuladd.f32(float %208, float %172, float %235) #2
  %237 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2, i32 0, i32 0
  store float %215, float addrspace(1)* %237, align 4, !tbaa !14
  %238 = getelementptr inbounds float addrspace(1)* %237, i32 1
  store float %220, float addrspace(1)* %238, align 4, !tbaa !14
  %239 = getelementptr inbounds float addrspace(1)* %237, i32 2
  store float %225, float addrspace(1)* %239, align 4, !tbaa !14
  %240 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  store float %230, float addrspace(1)* %240, align 4, !tbaa !14
  %241 = getelementptr inbounds float addrspace(1)* %240, i32 1
  store float %233, float addrspace(1)* %241, align 4, !tbaa !14
  %242 = getelementptr inbounds float addrspace(1)* %240, i32 2
  store float %236, float addrspace(1)* %242, align 4, !tbaa !14
  %243 = bitcast float %215 to i32
  %244 = add i32 %243, 128
  %245 = bitcast i32 %244 to float
  %246 = fsub float %245, %215
  %247 = tail call float @llvm.fabs.f32(float %246) #2
  %248 = fcmp ogt float %247, 0x3FB99999A0000000
  br i1 %248, label %MachineEpsilon_E.exit.i.i.i, label %249

; <label>:249                                     ; preds = %4
  %250 = fcmp olt float %247, 0x3E112E0BE0000000
  %251 = select i1 %250, float 0x3E112E0BE0000000, float %247
  br label %MachineEpsilon_E.exit.i.i.i

MachineEpsilon_E.exit.i.i.i:                      ; preds = %249, %4
  %252 = phi float [ %251, %249 ], [ 0x3FB99999A0000000, %4 ]
  %253 = bitcast float %220 to i32
  %254 = add i32 %253, 128
  %255 = bitcast i32 %254 to float
  %256 = fsub float %255, %220
  %257 = tail call float @llvm.fabs.f32(float %256) #2
  %258 = fcmp ogt float %257, 0x3FB99999A0000000
  br i1 %258, label %MachineEpsilon_E.exit2.i.i.i, label %259

; <label>:259                                     ; preds = %MachineEpsilon_E.exit.i.i.i
  %260 = fcmp olt float %257, 0x3E112E0BE0000000
  %261 = select i1 %260, float 0x3E112E0BE0000000, float %257
  br label %MachineEpsilon_E.exit2.i.i.i

MachineEpsilon_E.exit2.i.i.i:                     ; preds = %259, %MachineEpsilon_E.exit.i.i.i
  %262 = phi float [ %261, %259 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit.i.i.i ]
  %263 = bitcast float %225 to i32
  %264 = add i32 %263, 128
  %265 = bitcast i32 %264 to float
  %266 = fsub float %265, %225
  %267 = tail call float @llvm.fabs.f32(float %266) #2
  %268 = fcmp ogt float %267, 0x3FB99999A0000000
  br i1 %268, label %Camera_GenerateRay.exit, label %269

; <label>:269                                     ; preds = %MachineEpsilon_E.exit2.i.i.i
  %270 = fcmp olt float %267, 0x3E112E0BE0000000
  %271 = select i1 %270, float 0x3E112E0BE0000000, float %267
  br label %Camera_GenerateRay.exit

Camera_GenerateRay.exit:                          ; preds = %MachineEpsilon_E.exit2.i.i.i, %269
  %272 = phi float [ %271, %269 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit2.i.i.i ]
  %273 = fcmp olt float %262, %272
  %274 = select i1 %273, float %272, float %262
  %275 = fcmp olt float %252, %274
  %276 = select i1 %275, float %274, float %252
  %277 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2, i32 2
  store float %276, float addrspace(1)* %277, align 4, !tbaa !22
  %278 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2, i32 3
  store float %173, float addrspace(1)* %278, align 4, !tbaa !25
  %279 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 2, i32 0
  store i32 0, i32 addrspace(1)* %279, align 4, !tbaa !26
  %280 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 2, i32 1
  store i32 1, i32 addrspace(1)* %280, align 4, !tbaa !38
  %281 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 2, i32 2, i32 0
  store float 1.000000e+00, float addrspace(1)* %281, align 4, !tbaa !14
  %282 = getelementptr inbounds float addrspace(1)* %281, i32 1
  store float 1.000000e+00, float addrspace(1)* %282, align 4, !tbaa !14
  %283 = getelementptr inbounds float addrspace(1)* %281, i32 2
  store float 1.000000e+00, float addrspace(1)* %283, align 4, !tbaa !14
  %284 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 3, i32 1
  store float 1.000000e+00, float addrspace(1)* %284, align 4, !tbaa !39
  %285 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 3, i32 2
  store i32 1, i32 addrspace(1)* %285, align 4, !tbaa !40
  %286 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 5
  store float %97, float addrspace(1)* %286, align 4, !tbaa !41
  %287 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 0, i32 0
  store i32 %79, i32 addrspace(1)* %287, align 4, !tbaa !42
  %288 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 0, i32 1
  store i32 %85, i32 addrspace(1)* %288, align 4, !tbaa !43
  %289 = getelementptr inbounds %struct.GPUTask.32 addrspace(1)* %tasks, i32 %2, i32 0, i32 2
  store i32 %91, i32 addrspace(1)* %289, align 4, !tbaa !44
  %290 = getelementptr inbounds %struct.GPUTaskStats.33 addrspace(1)* %taskStats, i32 %2, i32 0
  store i32 0, i32 addrspace(1)* %290, align 4, !tbaa !45
  br label %291

; <label>:291                                     ; preds = %Camera_GenerateRay.exit, %0
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.x() #0

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
attributes #3 = { nobuiltin nounwind }

!opencl.kernels = !{!0, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11}
!llvm.ident = !{!12, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13}

!0 = metadata !{void (i32, %struct.GPUTask.32 addrspace(1)*, float addrspace(1)*, %struct.GPUTaskStats.33 addrspace(1)*, %struct.Ray.2 addrspace(1)*, %struct.Camera.22 addrspace(1)*)* @Init, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 64, i32 1, i32 1}
!2 = metadata !{null, metadata !1}
!3 = metadata !{null, metadata !1}
!4 = metadata !{null, metadata !1}
!5 = metadata !{null, metadata !1}
!6 = metadata !{null, metadata !1}
!7 = metadata !{null, metadata !1}
!8 = metadata !{null, metadata !1}
!9 = metadata !{null, metadata !1}
!10 = metadata !{null, metadata !1}
!11 = metadata !{null}
!12 = metadata !{metadata !"clang version 3.5.0 (trunk 212264) (llvm/trunk 212275)"}
!13 = metadata !{metadata !"clang version 3.5.0 (trunk 212142) (llvm/trunk 212143)"}
!14 = metadata !{metadata !15, metadata !15, i64 0}
!15 = metadata !{metadata !"float", metadata !16, i64 0}
!16 = metadata !{metadata !"omnipotent char", metadata !17, i64 0}
!17 = metadata !{metadata !"Simple C/C++ TBAA"}
!18 = metadata !{float 2.500000e+00}
!19 = metadata !{metadata !20, metadata !15, i64 524}
!20 = metadata !{metadata !"", metadata !16, i64 0, metadata !16, i64 256, metadata !15, i64 512, metadata !15, i64 516, metadata !15, i64 520, metadata !15, i64 524}
!21 = metadata !{metadata !20, metadata !15, i64 520}
!22 = metadata !{metadata !23, metadata !15, i64 24}
!23 = metadata !{metadata !"", metadata !24, i64 0, metadata !24, i64 12, metadata !15, i64 24, metadata !15, i64 28, metadata !15, i64 32, metadata !16, i64 36}
!24 = metadata !{metadata !"", metadata !15, i64 0, metadata !15, i64 4, metadata !15, i64 8}
!25 = metadata !{metadata !23, metadata !15, i64 28}
!26 = metadata !{metadata !27, metadata !16, i64 24}
!27 = metadata !{metadata !"", metadata !28, i64 0, metadata !30, i64 12, metadata !31, i64 24, metadata !36, i64 148, metadata !37, i64 228}
!28 = metadata !{metadata !"", metadata !29, i64 0, metadata !29, i64 4, metadata !29, i64 8}
!29 = metadata !{metadata !"int", metadata !16, i64 0}
!30 = metadata !{metadata !"", metadata !24, i64 0}
!31 = metadata !{metadata !"", metadata !16, i64 0, metadata !29, i64 4, metadata !24, i64 8, metadata !32, i64 20}
!32 = metadata !{metadata !"", metadata !33, i64 0, metadata !29, i64 60, metadata !29, i64 64, metadata !35, i64 68}
!33 = metadata !{metadata !"", metadata !24, i64 0, metadata !24, i64 12, metadata !34, i64 24, metadata !24, i64 32, metadata !24, i64 44, metadata !15, i64 56}
!34 = metadata !{metadata !"", metadata !15, i64 0, metadata !15, i64 4}
!35 = metadata !{metadata !"", metadata !24, i64 0, metadata !24, i64 12, metadata !24, i64 24}
!36 = metadata !{metadata !"", metadata !24, i64 0, metadata !15, i64 12, metadata !29, i64 16, metadata !33, i64 20}
!37 = metadata !{metadata !"", metadata !15, i64 0, metadata !32, i64 4}
!38 = metadata !{metadata !27, metadata !29, i64 28}
!39 = metadata !{metadata !27, metadata !15, i64 160}
!40 = metadata !{metadata !27, metadata !29, i64 164}
!41 = metadata !{metadata !27, metadata !15, i64 100}
!42 = metadata !{metadata !27, metadata !29, i64 0}
!43 = metadata !{metadata !27, metadata !29, i64 4}
!44 = metadata !{metadata !27, metadata !29, i64 8}
!45 = metadata !{metadata !46, metadata !29, i64 0}
!46 = metadata !{metadata !"", metadata !29, i64 0}

Shader Disassembly:

	ALU_PUSH_BEFORE 4, @0x72, KC0[CB0:0-32], KC1[]                         ; 80000072 A4100000
	JUMP @40 POP:1                                                         ; 00000028 82800001
	ALU 0x65, @0x77, KC0[CB0:0-32], KC1[]                                  ; 80000077 A1940000
	ALU 10, @0xdd, KC0[CB0:0-32], KC1[]                                    ; 800000DD A0280000
	MEM_RAT_CACHELESS STORE_RAW T10.X, T12.X, 0                            ; 06052020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T7.X, 0                              ; 0382A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T1.XY, T3.X, 0                             ; 0180A020 95C03000
	MEM_RAT_CACHELESS STORE_RAW T0.X, T4.X, 0                              ; 02002020 95C01000
	ALU 16, @0xe8, KC0[CB0:0-32], KC1[]                                    ; 800000E8 A0400000
	TEX 6 @42                                                              ; 0000002A 80401800
	ALU 16, @0xf9, KC0[], KC1[]                                            ; 000000F9 A0400000
	TEX 8 @56                                                              ; 00000038 80402000
	ALU 13, @0x10a, KC0[], KC1[]                                           ; 0000010A A0340000
	TEX 8 @0x4a                                                            ; 0000004A 80402000
	ALU 37, @0x118, KC0[CB0:0-32], KC1[]                                   ; 80000118 A0940000
	TEX 10 @0x5c                                                           ; 0000005C 80402800
	ALU 39, @0x13e, KC0[], KC1[]                                           ; 0000013E A09C0000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T16.X, 0                            ; 08072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T7.X, T13.X, 0                             ; 0683A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T6.X, T1.X, 0                              ; 00832020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T10.X, T12.X, 0                            ; 06052020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T22.X, 0                            ; 0B07A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T3.X, T11.X, 0                             ; 0581A020 95C01000
	ALU 0x42, @0x166, KC0[CB0:0-32], KC1[]                                 ; 80000166 A1080000
	ALU 49, @0x1a9, KC0[], KC1[]                                           ; 000001A9 A0C40000
	MEM_RAT_CACHELESS STORE_RAW T21.X, T22.X, 0                            ; 0B0AA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T20.X, 0                             ; 0A02A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T0.X, T19.X, 0                             ; 09802020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T17.X, 0                            ; 08892020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T15.X, 0                            ; 07882020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T14.X, 0                            ; 07082020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T13.X, 0                            ; 06882020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T12.X, 0                            ; 06082020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T11.X, 0                            ; 05892020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T4.X, T10.X, 0                             ; 05022020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T2.X, T9.X, 0                              ; 04812020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T1.X, T8.X, 0                              ; 0400A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T3.X, T7.X, 0                              ; 0381A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T0.X, T6.X, 0                              ; 03002020 95C01000
	POP @40 POP:1                                                          ; 00000028 83800001
	CF_END                                                                 ; 00000000 80200000
	PAD                                                                    ; 00000000 00000000
	Fetch clause starting at 42:                                           ; 
	VTX_READ_32 T22.X, T22.X, 48                                           ; 10160140 135FF016 00080030 00000000
	VTX_READ_32 T21.X, T21.X, 4                                            ; 10150140 135FF015 00080004 00000000
	VTX_READ_32 T20.X, T20.X, 16                                           ; 10140140 135FF014 00080010 00000000
	VTX_READ_32 T19.X, T19.X, 20                                           ; 10130140 135FF013 00080014 00000000
	VTX_READ_32 T18.X, T18.X, 52                                           ; 10120140 135FF012 00080034 00000000
	VTX_READ_32 T11.X, T11.X, 0                                            ; 100B0140 135FF00B 00080000 00000000
	VTX_READ_32 T6.X, T6.X, 0                                              ; 10060140 135FF006 00080000 00000000
	Fetch clause starting at 56:                                           ; 
	VTX_READ_32 T18.X, T18.X, 32                                           ; 10120140 135FF012 00080020 00000000
	VTX_READ_32 T11.X, T11.X, 12                                           ; 100B0140 135FF00B 0008000C 00000000
	VTX_READ_32 T23.X, T23.X, 8                                            ; 10170140 135FF017 00080008 00000000
	VTX_READ_32 T6.X, T6.X, 28                                             ; 10060140 135FF006 0008001C 00000000
	VTX_READ_32 T17.X, T17.X, 36                                           ; 10110140 135FF011 00080024 00000000
	VTX_READ_32 T16.X, T16.X, 24                                           ; 10100140 135FF010 00080018 00000000
	VTX_READ_32 T15.X, T15.X, 0                                            ; 100F0140 135FF00F 00080000 00000000
	VTX_READ_32 T14.X, T14.X, 60                                           ; 100E0140 135FF00E 0008003C 00000000
	VTX_READ_32 T5.X, T5.X, 56                                             ; 10050140 135FF005 00080038 00000000
	Fetch clause starting at 0x4a:                                         ; 
	VTX_READ_32 T6.X, T6.X, 0x134                                          ; 10060140 135FF006 00080134 00000000
	VTX_READ_32 T14.X, T14.X, 0x118                                        ; 100E0140 135FF00E 00080118 00000000
	VTX_READ_32 T19.X, T19.X, 0x110                                        ; 10130140 135FF013 00080110 00000000
	VTX_READ_32 T13.X, T13.X, 0x114                                        ; 100D0140 135FF00D 00080114 00000000
	VTX_READ_32 T12.X, T12.X, 0x128                                        ; 100C0140 135FF00C 00080128 00000000
	VTX_READ_32 T10.X, T10.X, 0x120                                        ; 100A0140 135FF00A 00080120 00000000
	VTX_READ_32 T7.X, T7.X, 0x124                                          ; 10070140 135FF007 00080124 00000000
	VTX_READ_32 T4.X, T4.X, 44                                             ; 10040140 135FF004 0008002C 00000000
	VTX_READ_32 T3.X, T3.X, 40                                             ; 10030140 135FF003 00080028 00000000
	Fetch clause starting at 0x5c:                                         ; 
	VTX_READ_32 T5.X, T5.X, 0x208                                          ; 10050140 135FF005 00080208 00000000
	VTX_READ_32 T4.X, T4.X, 0x20c                                          ; 10040140 135FF004 0008020C 00000000
	VTX_READ_32 T24.X, T24.X, 0x10c                                        ; 10180140 135FF018 0008010C 00000000
	VTX_READ_32 T23.X, T23.X, 0x11c                                        ; 10170140 135FF017 0008011C 00000000
	VTX_READ_32 T1.X, T1.X, 0x12c                                          ; 10010140 135FF001 0008012C 00000000
	VTX_READ_32 T20.X, T20.X, 0x13c                                        ; 10140140 135FF014 0008013C 00000000
	VTX_READ_32 T16.X, T16.X, 0x108                                        ; 10100140 135FF010 00080108 00000000
	VTX_READ_32 T18.X, T18.X, 0x100                                        ; 10120140 135FF012 00080100 00000000
	VTX_READ_32 T21.X, T21.X, 0x138                                        ; 10150140 135FF015 00080138 00000000
	VTX_READ_32 T22.X, T22.X, 0x130                                        ; 10160140 135FF016 00080130 00000000
	VTX_READ_32 T17.X, T17.X, 0x104                                        ; 10110140 135FF011 00080104 00000000
	ALU clause starting at 0x72:                                           ; 
	  MULLO_INT             * T0.Y, KC0[1].Z, T1.X,                        ; 80002881 20004790
	  ADD_INT               * T0.W, T0.X, PS,                              ; 801FE000 60001A10
	  SETGT_UINT            * T1.W, PV.W, literal.x,                       ; 801FACFE 60201F10
	65535(9.183409e-41), 0(0.000000e+00)                                   ; 0000FFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,   ; 801F0CFE 00002104
	ALU clause starting at 0x77:                                           ; 
	  MOV                     T1.X, 0.0,                                   ; 000000F8 00200C90
	  MOV                     T1.Y, 0.0,                                   ; 000000F8 20200C90
	  MOV                   * T1.W, KC0[2].Y,                              ; 80000482 60200C90
	  ADD_INT               * T1.W, T0.W, PV.W,                            ; 819FCC00 60201A10
	  ADD_INT               * T2.W, PV.W, literal.x,                       ; 801FACFE 60401A10
	16777215(2.350989e-38), 0(0.000000e+00)                                ; 00FFFFFF 00000000
	  CNDE_INT              * T1.W, T1.W, PV.W, T1.W,                      ; 819FCC01 60238C01
	  MULLO_INT             * T0.X, PV.W, literal.x,                       ; 801FACFE 00004790
	69069(9.678628e-41), 0(0.000000e+00)                                   ; 00010DCD 00000000
	  SETE_INT              * T1.W, PS, 0.0,                               ; 801F00FF 60201D10
	  AND_INT               * T1.W, PV.W, 1,                               ; 801F4CFE 60201810
	  ADD_INT               * T1.W, PV.W, T0.X,                            ; 80000CFE 60201A10
	  MULLO_INT             * T0.X, PV.W, literal.x,                       ; 801FACFE 00004790
	69069(9.678628e-41), 0(0.000000e+00)                                   ; 00010DCD 00000000
	  SETGT_UINT            * T2.W, PS, literal.x,                         ; 801FA0FF 60401F10
	6(8.407791e-45), 0(0.000000e+00)                                       ; 00000006 00000000
	  CNDE_INT              * T2.W, PV.W, literal.x, 0.0,                  ; 801FACFE 604380F8
	7(9.809089e-45), 0(0.000000e+00)                                       ; 00000007 00000000
	  ADD_INT               * T2.W, PV.W, T0.X,                            ; 80000CFE 60401A10
	  MULLO_INT             * T0.X, PV.W, literal.x,                       ; 801FACFE 00004790
	69069(9.678628e-41), 0(0.000000e+00)                                   ; 00010DCD 00000000
	  SETGT_UINT              T3.W, PS, literal.x,                         ; 001FA0FF 60601F10
	  LSHL                  * T4.W, T2.W, literal.y,                       ; 809FAC02 60800B90
	14(1.961818e-44), 2(2.802597e-45)                                      ; 0000000E 00000002
	  CNDE_INT              * T3.W, PV.W, literal.x, 0.0,                  ; 801FACFE 606380F8
	15(2.101948e-44), 0(0.000000e+00)                                      ; 0000000F 00000000
	  ADD_INT                 T0.Z, PV.W, T0.X,                            ; 00000CFE 40001A10
	  LSHL                    T3.W, T1.W, literal.x,                       ; 001FAC01 60600B90
	  XOR_INT               * T4.W, T4.W, T2.W,                            ; 81804C04 60801910
	13(1.821688e-44), 0(0.000000e+00)                                      ; 0000000D 00000000
	  LSHR                    T0.X, PS, literal.x,                         ; 001FA0FF 00000B10
	  LSHL                    T0.Y, T1.W, literal.y,                       ; 009FAC01 20000B90
	  XOR_INT                 T1.Z, PV.W, T1.W,                            ; 01802CFE 40201910
	  LSHL                    T1.W, PV.Z, literal.z,                       ; 011FA8FE 60200B90
	  LSHL                  * T3.W, T2.W, literal.w,                       ; 819FAC02 60600B90
	25(3.503246e-44), 12(1.681558e-44)                                     ; 00000019 0000000C
	3(4.203895e-45), 4(5.605194e-45)                                       ; 00000003 00000004
	  AND_INT                 T2.X, PS, literal.x,                         ; 001FA0FF 00401810
	  LSHL                    T2.Y, T0.Z, literal.y,                       ; 009FA800 20400B90
	  XOR_INT                 T0.Z, PV.W, T0.Z,                            ; 01000CFE 40001910
	  LSHR                    T1.W, PV.Z, literal.z,                       ; 011FA8FE 60200B10
	  AND_INT               * T4.W, PV.Y, literal.w,                       ; 819FA4FE 60801810
	-128(-nan), 17(2.382207e-44)                                           ; FFFFFF80 00000011
	19(2.662467e-44), -8192(-nan)                                          ; 00000013 FFFFE000
	  OR_INT                  T3.X, PV.W, PS,                              ; 001FECFE 00601890
	  LSHR                    T3.Y, PV.Z, literal.x,                       ; 001FA8FE 20600B10
	  AND_INT                 T1.Z, PV.Y, literal.y,                       ; 009FA4FE 40201810
	  OR_INT                  T1.W, T0.X, PV.X,                            ; 001FC000 60201890
	  LSHL                  * T4.W, T2.W, literal.z,                       ; 811FAC02 60800B90
	11(1.541428e-44), -2097152(-nan)                                       ; 0000000B FFE00000
	6(8.407791e-45), 0(0.000000e+00)                                       ; 00000006 00000000
	  XOR_INT                 T2.Y, PS, T3.W,                              ; 018060FF 20401910
	  LSHL                    T2.Z, PV.W, literal.x,                       ; 001FACFE 40400B90
	  OR_INT                  T3.W, PV.Y, PV.Z,                            ; 011FC4FE 60601890
	  LSHL                  * T4.W, PV.X, literal.y,                       ; 809FA0FE 60800B90
	4(5.605194e-45), 13(1.821688e-44)                                      ; 00000004 0000000D
	  LSHL                    T2.X, T3.X, literal.x,                       ; 001FA003 00400B90
	  XOR_INT                 T0.Y, PS, T0.Y,                              ; 008000FF 20001910
	  LSHL                    T1.Z, PV.W, literal.y,                       ; 009FACFE 40200B90
	  AND_INT                 T4.W, PV.Z, literal.z,                       ; 011FA8FE 60801810
	  LSHR                  * T5.W, PV.Y, literal.w,                       ; 819FA4FE 60A00B10
	12(1.681558e-44), 3(4.203895e-45)                                      ; 0000000C 00000003
	-128(-nan), 25(3.503246e-44)                                           ; FFFFFF80 00000019
	  OR_INT                  T8.X, PV.W, PS,                              ; 001FECFE 01001890
	  LSHL                    T2.Y, T0.Z, literal.x,                       ; 001FA800 20400B90
	  XOR_INT                 T3.Z, PV.Z, T3.W,                            ; 018068FE 40601910
	  LSHR                    T4.W, PV.Y, literal.y,                       ; 009FA4FE 60800B10
	  AND_INT               * T5.W, PV.X, literal.z,                       ; 811FA0FE 60A01810
	6(8.407791e-45), 19(2.662467e-44)                                      ; 00000006 00000013
	-8192(-nan), 0(0.000000e+00)                                           ; FFFFE000 00000000
	  OR_INT                  T9.X, PV.W, PS,                              ; 001FECFE 01201890
	  LSHR                    T0.Y, PV.Z, literal.x,                       ; 001FA8FE 20000B10
	  AND_INT                 T1.Z, PV.Y, literal.y,                       ; 009FA4FE 40201810
	  MOV                     T4.W, KC0[2].Z,                              ; 00000882 60800C90
	  MULLO_INT             * T0.X, T0.W, literal.z,                       ; 811FAC00 00004790
	11(1.541428e-44), -2097152(-nan)                                       ; 0000000B FFE00000
	336(4.708363e-43), 0(0.000000e+00)                                     ; 00000150 00000000
	  ADD_INT                 T0.Z, PV.W, PS,                              ; 001FECFE 40001A10
	  OR_INT                  T4.W, PV.Y, PV.Z,                            ; 011FC4FE 60801890
	  XOR_INT               * T5.W, T8.X, PV.X,                            ; 801FC008 60A01910
	  XOR_INT                 T5.W, PS, PV.W,                              ; 019FC0FF 60A01910
	  ADD_INT               * T6.W, PV.Z, literal.x,                       ; 801FA8FE 60C01A10
	20(2.802597e-44), 0(0.000000e+00)                                      ; 00000014 00000000
	  LSHR                    T4.X, PS, literal.x,                         ; 001FA0FF 00800B10
	  AND_INT                 T5.W, PV.W, literal.y,                       ; 009FACFE 60A01810
	  MOV                   * T0.X, literal.z,                             ; 800008FD 00000C90
	2(2.802597e-45), 16777215(2.350989e-38)                                ; 00000002 00FFFFFF
	0(0.000000e+00), 0(0.000000e+00)                                       ; 00000000 00000000
	  XOR_INT                 T1.Z, T1.W, T3.X,                            ; 00006C01 40201910
	  ADD_INT                 T1.W, T0.Z, literal.x,                       ; 001FA800 60201A10
	  UINT_TO_FLT           * T0.Y, PV.W,                                  ; 80000CFE 20004E10
	12(1.681558e-44), 0(0.000000e+00)                                      ; 0000000C 00000000
	  LSHR                    T3.X, PV.W, literal.x,                       ; 001FACFE 00600B10
	  LSHL                    T4.Z, T0.W, literal.y,                       ; 009FAC00 40800B90
	  XOR_INT                 T1.W, PV.Z, T3.W,                            ; 018068FE 60201910
	  ADD                   * T3.W, PS, 0.0,                               ; 801F00FF 60600010
	2(2.802597e-45), 3(4.203895e-45)                                       ; 00000002 00000003
	  MUL_IEEE                T5.X, PS, literal.x,                         ; 001FA0FF 00A00110
	  AND_INT                 T1.Z, PV.W, literal.y,                       ; 009FACFE 40201810
	  OR_INT                * T1.W, PV.Z, literal.z,                       ; 811FA8FE 60201890
	864026624(5.960464e-08), 16777215(2.350989e-38)                        ; 33800000 00FFFFFF
	4(5.605194e-45), 0(0.000000e+00)                                       ; 00000004 00000000
	ALU clause starting at 0xdd:                                           ; 
	  MOV                   * T3.W, KC0[2].W,                              ; 80000C82 60600C90
	  ADD_INT                 T6.X, PV.W, T1.W,                            ; 01802CFE 00C01A10
	  UINT_TO_FLT           * T0.Y, T1.Z,                                  ; 80000801 20004E10
	  LSHR                    T7.X, PV.X, literal.x,                       ; 001FA0FE 00E00B10
	  ADD                   * T1.W, PS, 0.0,                               ; 801F00FF 60200010
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MUL_IEEE                T10.X, PV.W, literal.x,                      ; 001FACFE 01400110
	  ADD_INT               * T11.X, T3.W, T4.Z,                           ; 81008C03 01601A10
	864026624(5.960464e-08), 0(0.000000e+00)                               ; 33800000 00000000
	  LSHR                  * T12.X, PS, literal.x,                        ; 801FA0FF 01800B10
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	ALU clause starting at 0xe8:                                           ; 
	  MOV                   * T1.X, KC0[3].Z,                              ; 80000883 00200C90
	  MOV                     T3.X, PV.X,                                  ; 000000FE 00600C90
	  MOV                   * T4.X, PV.X,                                  ; 800000FE 00800C90
	  MOV                     T7.X, T1.X,                                  ; 00000001 00E00C90
	  MOV                   * T10.X, T1.X,                                 ; 80000001 01400C90
	  MOV                     T12.X, T1.X,                                 ; 00000001 01800C90
	  MOV                   * T13.X, T1.X,                                 ; 80000001 01A00C90
	  MOV                     T5.X, T1.X,                                  ; 00000001 00A00C90
	  MOV                   * T14.X, T1.X,                                 ; 80000001 01C00C90
	  MOV                     T15.X, T1.X,                                 ; 00000001 01E00C90
	  MOV                   * T16.X, T1.X,                                 ; 80000001 02000C90
	  MOV                     T17.X, T1.X,                                 ; 00000001 02200C90
	  MOV                   * T18.X, T1.X,                                 ; 80000001 02400C90
	  MOV                     T19.X, T1.X,                                 ; 00000001 02600C90
	  MOV                   * T20.X, T1.X,                                 ; 80000001 02800C90
	  MOV                     T21.X, T1.X,                                 ; 00000001 02A00C90
	  MOV                   * T22.X, T1.X,                                 ; 80000001 02C00C90
	ALU clause starting at 0xf9:                                           ; 
	  ADD                   * T1.W, -T6.X, 1.0,                            ; 801F3006 60200010
	  MOV                     T6.X, T1.X,                                  ; 00000001 00C00C90
	  MUL_IEEE                T1.W, PV.W, literal.x,                       ; 001FACFE 60200110
	  MOV                   * T23.X, T1.X,                                 ; 80000001 02E00C90
	1139802112(4.800000e+02), 0(0.000000e+00)                              ; 43F00000 00000000
	  MUL_IEEE                T3.W, T11.X, literal.x,                      ; 001FA00B 60600110
	  MIN                   * T1.W, PV.W, literal.y,                       ; 809FACFE 60200210
	1142947840(6.400000e+02), 1139769344(4.790000e+02)                     ; 44200000 43EF8000
	  MOV                     T11.X, T1.X,                                 ; 00000001 01600C90
	  MUL_IEEE                T1.Z, T18.X, PS,  BS:VEC_120/SCL_212         ; 001FE012 40280110
	  MUL_IEEE                T5.W, PS, T19.X,  BS:VEC_021/SCL_122         ; 000260FF 60A40110
	  MIN                   * T3.W, PV.W, literal.x,                       ; 801FACFE 60600210
	1142931456(6.390000e+02), 0(0.000000e+00)                              ; 441FC000 00000000
	  MOV                     T18.X, T1.X,                                 ; 00000001 02400C90
	  MULADD_IEEE             T4.Z, T20.X, PS, PV.W, BS:VEC_120/SCL_212    ; 001FE014 408B0CFE
	  MUL_IEEE              * T5.W, T1.W, T21.X,  BS:VEC_021/SCL_122       ; 8002AC01 60A40110
	  MULADD_IEEE           * T6.W, T22.X, T3.W, T1.Z,                     ; 81806016 60C30801
	ALU clause starting at 0x10a:                                          ; 
	  MULADD_IEEE           * T6.W, T5.X, 0.0, T6.W,                       ; 801F0005 60C30C06
	  MOV                     T19.X, T1.X,                                 ; 00000001 02600C90
	  ADD                     T1.Z, T14.X, PV.W,  BS:VEC_120/SCL_212       ; 019FC00E 40280010
	  MULADD_IEEE           * T5.W, T15.X, T3.W, T5.W, BS:VEC_201          ; 8180600F 60B30C05
	  MULADD_IEEE           * T6.W, T16.X, 0.0, T4.Z,                      ; 801F0010 60C30804
	  MOV                     T14.X, T1.X,                                 ; 00000001 01C00C90
	  MUL_IEEE                T0.Y, T1.W, T17.X,                           ; 00022C01 20000110
	  ADD                   * T4.Z, T6.X, PV.W,  BS:VEC_201                ; 819FC006 40900010
	  MULADD_IEEE             T1.W, T23.X, 0.0, T5.W,                      ; 001F0017 60230C05
	  RECIP_IEEE            * T1.Y, T1.Z,                                  ; 80000801 20204310
	  MOV                     T6.X, T1.X,                                  ; 00000001 00C00C90
	  ADD                     T1.Z, T11.X, PV.W,  BS:VEC_120/SCL_212       ; 019FC00B 40280010
	  MUL_IEEE                T5.W, PS, T4.Z,                              ; 010080FF 60A00110
	  MULADD_IEEE           * T1.W, T18.X, T3.W, T0.Y,                     ; 81806012 60230400
	ALU clause starting at 0x118:                                          ; 
	  MULADD_IEEE           * T1.W, T3.X, 0.0, T1.W,                       ; 801F0003 60230C01
	  ADD                     T4.Z, T4.X, PV.W,                            ; 019FC004 40800010
	  MUL_IEEE                T1.W, T5.W, T5.W,                            ; 0180AC05 60200110
	  MUL_IEEE              * T3.W, T1.Y, T1.Z,                            ; 81002401 60600110
	  MULADD_IEEE             T1.W, PS, PS, PV.W,                          ; 001FE0FF 60230CFE
	  MUL_IEEE              * T6.W, T1.Y, PV.Z,                            ; 811FC401 60C00110
	  MULADD_IEEE           * T1.W, PS, PS, PV.W,                          ; 801FE0FF 60230CFE
	  RECIPSQRT_CLAMPED     * T0.Y, PV.W,                                  ; 80000CFE 20004390
	  MUL NON-IEEE          * T1.W, T1.W, PS,                              ; 801FEC01 60200090
	  RECIP_IEEE            * T0.Y, PV.W,                                  ; 80000CFE 20004310
	  MUL_IEEE              * T7.W, T5.W, PS,                              ; 801FEC05 60E00110
	  MUL_IEEE                T1.Y, PV.W, T7.X,                            ; 0000ECFE 20200110
	  MUL_IEEE                T4.Z, T3.W, T0.Y,                            ; 00800C03 40800110
	  MOV                     T1.W, KC0[3].Y,                              ; 00000483 60200C90
	  MULLO_INT             * T1.Z, T0.W, literal.x,                       ; 801FAC00 40204790
	48(6.726233e-44), 0(0.000000e+00)                                      ; 00000030 00000000
	  ADD_INT                 T1.Z, PV.W, PS,                              ; 001FECFE 40201A10
	  MULADD_IEEE             T8.W, T10.X, PV.Z, PV.Y,                     ; 011FC00A 610304FE
	  MUL_IEEE              * T1.W, T6.W, T0.Y,                            ; 80800C06 60200110
	  MULADD_IEEE             T3.X, T12.X, PS, PV.W,                       ; 001FE00C 00630CFE
	  MUL_IEEE                T8.W, T7.W, T13.X,                           ; 0001AC07 61000110
	  ADD_INT               * T9.W, PV.Z, literal.x,                       ; 801FA8FE 61201A10
	20(2.802597e-44), 0(0.000000e+00)                                      ; 00000014 00000000
	  LSHR                    T11.X, PS, literal.x,                        ; 001FA0FF 01600B10
	  MULADD_IEEE           * T8.W, T19.X, T4.Z, PV.W,                     ; 81008013 61030CFE
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MULADD_IEEE             T15.X, T14.X, T1.W, PV.W,                    ; 0180200E 01E30CFE
	  MOV                   * T16.X, T1.X,                                 ; 80000001 02000C90
	  MOV                     T17.X, T1.X,                                 ; 00000001 02200C90
	  MOV                   * T18.X, T1.X,                                 ; 80000001 02400C90
	  MOV                     T20.X, T1.X,                                 ; 00000001 02800C90
	  MOV                   * T21.X, T1.X,                                 ; 80000001 02A00C90
	  MOV                     T22.X, T1.X,                                 ; 00000001 02C00C90
	  MOV                   * T23.X, T1.X,                                 ; 80000001 02E00C90
	  MOV                     T24.X, T1.X,                                 ; 00000001 03000C90
	  MOV                   * T4.X, T1.X,                                  ; 80000001 00800C90
	  MOV                     T5.X, T1.X,                                  ; 00000001 00A00C90
	  MUL_IEEE              * T8.W, T5.W, T6.X,                            ; 8000CC05 61000110
	ALU clause starting at 0x13e:                                          ; 
	  MUL_IEEE                T0.Y, T7.W, T17.X,                           ; 00022C07 20000110
	  MULADD_IEEE           * T5.Z, T22.X, T3.W, T8.W,                     ; 81806016 40A30C08
	  MUL_IEEE                T7.W, T5.W, T7.X,                            ; 0000EC05 60E00110
	  ADD_INT               * T8.W, T1.Z, literal.x,                       ; 801FA801 61001A10
	16(2.242078e-44), 0(0.000000e+00)                                      ; 00000010 00000000
	  LSHR                    T22.X, PS, literal.x,                        ; 001FA0FF 02C00B10
	  MULADD_IEEE             T6.Z, T10.X, T3.W, PV.W,                     ; 0180600A 40C30CFE
	  MULADD_IEEE             T7.W, T21.X, T6.W, T5.Z, BS:VEC_120/SCL_212  ; 0180C015 60EB0805
	  MULADD_IEEE           * T8.W, T18.X, T4.Z, T0.Y,                     ; 81008012 61030400
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MULADD_IEEE             T10.X, T16.X, T1.W, PS,                      ; 01802010 014300FF
	  ADD                     T0.Y, T20.X, PV.W,  BS:VEC_120/SCL_212       ; 019FC014 20080010
	  MULADD_IEEE           * T4.Z, T12.X, T6.W, PV.Z, BS:VEC_201          ; 8180C00C 409308FE
	  MUL_IEEE                T7.W, T5.W, T13.X,                           ; 0001AC05 60E00110
	  ADD_INT               * T8.W, T1.Z, literal.x,                       ; 801FA801 61001A10
	12(1.681558e-44), 0(0.000000e+00)                                      ; 0000000C 00000000
	  LSHR                    T12.X, PS, literal.x,                        ; 001FA0FF 01800B10
	  MULADD_IEEE             T5.Z, T19.X, T3.W, PV.W,                     ; 01806013 40A30CFE
	  ADD                     T7.W, T1.X, T4.Z,  BS:VEC_120/SCL_212        ; 01008001 60E80010
	  RECIP_IEEE            * T0.Y, T0.Y,                                  ; 80000400 20004310
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MUL_IEEE                T6.X, PS, PV.W,                              ; 019FC0FF 00C00110
	  MULADD_IEEE             T4.Z, T14.X, T6.W, PV.Z,                     ; 0180C00E 408308FE
	  MUL_IEEE                T5.W, T5.W, T17.X,                           ; 00022C05 60A00110
	  ADD_INT               * T7.W, T1.Z, literal.x,                       ; 801FA801 60E01A10
	8(1.121039e-44), 0(0.000000e+00)                                       ; 00000008 00000000
	  LSHR                    T1.X, PS, literal.x,                         ; 001FA0FF 00200B10
	  MULADD_IEEE             T3.W, T18.X, T3.W, PV.W,                     ; 01806012 60630CFE
	  ADD                   * T5.W, T23.X, PV.Z,                           ; 811FC017 60A00010
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MUL_IEEE                T7.X, T0.Y, PS,                              ; 001FE400 00E00110
	  MULADD_IEEE             T3.W, T16.X, T6.W, PV.W,                     ; 0180C010 60630CFE
	  ADD_INT               * T5.W, T1.Z, literal.x,                       ; 801FA801 60A01A10
	4(5.605194e-45), 0(0.000000e+00)                                       ; 00000004 00000000
	  LSHR                    T13.X, PS, literal.x,                        ; 001FA0FF 01A00B10
	  ADD                   * T3.W, T24.X, PV.W,                           ; 819FC018 60600010
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MUL_IEEE                T14.X, T0.Y, PV.W,                           ; 019FC400 01C00110
	  LSHR                  * T16.X, T1.Z, literal.x,                      ; 801FA801 02000B10
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	ALU clause starting at 0x166:                                          ; 
	  LSHL                  * T2.W, T2.W, literal.x,                       ; 801FAC02 60400B90
	10(1.401298e-44), 0(0.000000e+00)                                      ; 0000000A 00000000
	  XOR_INT                 T2.Z, T2.Z, PV.W,                            ; 019FC802 40401910
	  LSHL                    T2.W, T8.X, literal.x,                       ; 001FA008 60400B90
	  LSHL                  * T3.W, T9.X, literal.y,                       ; 809FA009 60600B90
	4(5.605194e-45), 13(1.821688e-44)                                      ; 00000004 0000000D
	  LSHL                    T3.X, T9.X, literal.x,                       ; 001FA009 00600B90
	  XOR_INT                 T0.Y, PS, T2.X,                              ; 000040FF 20001910
	  LSHL                    T4.Z, T4.W, literal.y,                       ; 009FAC04 40800B90
	  AND_INT                 T2.W, PV.W, literal.z,                       ; 011FACFE 60401810
	  LSHR                  * T3.W, PV.Z, literal.w,                       ; 819FA8FE 60600B10
	12(1.681558e-44), 3(4.203895e-45)                                      ; 0000000C 00000003
	-128(-nan), 25(3.503246e-44)                                           ; FFFFFF80 00000019
	  OR_INT                  T1.X, PV.W, PS,                              ; 001FECFE 00201890
	  LSHL                    T1.Y, T3.Z, literal.x,                       ; 001FA803 20200B90
	  XOR_INT                 T2.Z, PV.Z, T4.W,                            ; 018088FE 40401910
	  LSHR                    T2.W, PV.Y, literal.y,                       ; 009FA4FE 60400B10
	  AND_INT               * T3.W, PV.X, literal.z,                       ; 811FA0FE 60601810
	6(8.407791e-45), 19(2.662467e-44)                                      ; 00000006 00000013
	-8192(-nan), 0(0.000000e+00)                                           ; FFFFE000 00000000
	  OR_INT                  T2.X, PV.W, PS,                              ; 001FECFE 00401890
	  LSHR                    T2.W, PV.Z, literal.x,                       ; 001FA8FE 60400B10
	  AND_INT               * T3.W, PV.Y, literal.y,                       ; 809FA4FE 60601810
	11(1.541428e-44), -2097152(-nan)                                       ; 0000000B FFE00000
	  OR_INT                  T3.X, PV.W, PS,                              ; 001FECFE 00601890
	  XOR_INT                 T2.W, T1.X, PV.X,                            ; 001FC001 60401910
	  ADD_INT               * T3.W, T14.X, literal.x,                      ; 801FA00E 60601A10
	128(1.793662e-43), 0(0.000000e+00)                                     ; 00000080 00000000
	  XOR_INT               * T2.W, PV.W, PV.X,                            ; 801FCCFE 60401910
	  AND_INT                 T2.Z, PV.W, literal.x,                       ; 001FACFE 40401810
	  ADD                     T4.W, T3.W, -T14.X,                          ; 0201CC03 60800010
	  MOV                   * T2.W, literal.y,                             ; 800004FD 60400C90
	16777215(2.350989e-38), 1036831949(1.000000e-01)                       ; 00FFFFFF 3DCCCCCD
	  MOV                     T3.W, PS,                                    ; 000000FF 60600C90
	  SETGT_DX10            * T5.W, |PV.W|, literal.x,                     ; 801FACFE 60A00691
	1036831949(1.000000e-01), 0(0.000000e+00)                              ; 3DCCCCCD 00000000
	  UINT_TO_FLT           * T0.Y, T2.Z,                                  ; 80000802 20004E10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), T5.W, 0.0,       ; 801F0C05 00002288
	  MOV                   * T3.W, |T4.W|, Pred_sel_zero                  ; C0000C04 60600C91
	  MAX                   * T3.W, T3.W, literal.x, Pred_sel_zero         ; C01FAC03 60600190
	814313567(1.000000e-09), 0(0.000000e+00)                               ; 3089705F 00000000
	  ADD_INT               * T4.W, T7.X, literal.x,                       ; 801FA007 60801A10
	128(1.793662e-43), 0(0.000000e+00)                                     ; 00000080 00000000
	  ADD                     T5.W, PV.W, -T7.X,                           ; 0200ECFE 60A00010
	  MOV                   * T4.W, T2.W,                                  ; 80000C02 60800C90
	  ADD                     T1.Y, T5.X, -T4.X,                           ; 02008005 20200010
	  ADD                     T2.Z, T0.Y, 0.0,                             ; 001F0400 40400010
	  SETGT_DX10              T6.W, |PV.W|, literal.x,                     ; 001FACFE 60C00691
	  RECIP_IEEE            * T0.Y, T1.W,                                  ; 80000C01 20004310
	1036831949(1.000000e-01), 0(0.000000e+00)                              ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,       ; 801F0CFE 00002288
	  MOV                   * T1.W, |T5.W|, Pred_sel_zero                  ; C0000C05 60200C91
	  MAX                   * T4.W, T1.W, literal.x, Pred_sel_zero         ; C01FAC01 60800190
	814313567(1.000000e-09), 0(0.000000e+00)                               ; 3089705F 00000000
	  ADD_INT               * T1.W, T6.X, literal.x,                       ; 801FA006 60201A10
	128(1.793662e-43), 0(0.000000e+00)                                     ; 00000080 00000000
	  MUL_IEEE                T5.X, T1.Y, T0.Y,                            ; 00800401 00A00110
	  ADD                     T5.W, PV.W, -T6.X,                           ; 0200CCFE 60A00010
	  MUL_IEEE              * T4.X, T2.Z, literal.x,                       ; 801FA802 00800110
	864026624(5.960464e-08), 0(0.000000e+00)                               ; 33800000 00000000
	  MOV                     T1.W, KC0[3].X,                              ; 00000083 60200C90
	  SETGT_DX10            * T6.W, |PV.W|, literal.x,                     ; 801FACFE 60C00691
	1036831949(1.000000e-01), 0(0.000000e+00)                              ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,         ; 801F00FF 00002288
	  MOV                   * T2.W, |T5.W|, Pred_sel_zero                  ; C0000C05 60400C91
	  MAX                   * T2.W, T2.W, literal.x, Pred_sel_zero         ; C01FAC02 60400190
	814313567(1.000000e-09), 0(0.000000e+00)                               ; 3089705F 00000000
	ALU clause starting at 0x1a9:                                          ; 
	  LSHL                  * T0.W, T0.W, literal.x,                       ; 801FAC00 60000B90
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  ADD_INT               * T0.W, T1.W, PV.W,                            ; 819FCC01 60001A10
	  LSHR                    T6.X, PV.W, literal.x,                       ; 001FACFE 00C00B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 8(1.121039e-44)                                       ; 00000002 00000008
	  LSHR                    T7.X, PV.W, literal.x,                       ; 001FACFE 00E00B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 4(5.605194e-45)                                       ; 00000002 00000004
	  LSHR                    T8.X, PV.W, literal.x,                       ; 001FACFE 01000B10
	  LSHR                  * T9.X, T0.Z, literal.x,                       ; 801FA800 01200B10
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  ADD_INT               * T0.W, T0.Z, literal.x,                       ; 801FA800 60001A10
	100(1.401298e-43), 0(0.000000e+00)                                     ; 00000064 00000000
	  LSHR                    T10.X, PV.W, literal.x,                      ; 001FACFE 01400B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 164(2.298129e-43)                                     ; 00000002 000000A4
	  LSHR                    T11.X, PV.W, literal.x,                      ; 001FACFE 01600B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 160(2.242078e-43)                                     ; 00000002 000000A0
	  LSHR                    T12.X, PV.W, literal.x,                      ; 001FACFE 01800B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 40(5.605194e-44)                                      ; 00000002 00000028
	  LSHR                    T13.X, PV.W, literal.x,                      ; 001FACFE 01A00B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 36(5.044674e-44)                                      ; 00000002 00000024
	  LSHR                    T14.X, PV.W, literal.x,                      ; 001FACFE 01C00B10
	  ADD_INT               * T0.W, T0.Z, literal.y,                       ; 809FA800 60001A10
	2(2.802597e-45), 32(4.484155e-44)                                      ; 00000002 00000020
	  LSHR                    T15.X, PV.W, literal.x,                      ; 001FACFE 01E00B10
	  MOV                   * T16.X, literal.y,                            ; 800004FD 02000C90
	2(2.802597e-45), 1065353216(1.000000e+00)                              ; 00000002 3F800000
	  ADD_INT               * T0.W, T0.Z, literal.x,                       ; 801FA800 60001A10
	28(3.923636e-44), 0(0.000000e+00)                                      ; 0000001C 00000000
	  LSHR                    T17.X, PV.W, literal.x,                      ; 001FACFE 02200B10
	  MOV                   * T18.X, literal.y,                            ; 800004FD 02400C90
	2(2.802597e-45), 1(1.401298e-45)                                       ; 00000002 00000001
	  ADD_INT               * T0.W, T0.Z, literal.x,                       ; 801FA800 60001A10
	24(3.363116e-44), 0(0.000000e+00)                                      ; 00000018 00000000
	  LSHR                    T19.X, PV.W, literal.x,                      ; 001FACFE 02600B10
	  ADD_INT               * T0.W, T1.Z, literal.y,                       ; 809FA801 60001A10
	2(2.802597e-45), 28(3.923636e-44)                                      ; 00000002 0000001C
	  LSHR                    T20.X, PV.W, literal.x,                      ; 001FACFE 02800B10
	  MAX                   * T0.W, T4.W, T2.W,                            ; 81804C04 60000190
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000
	  MAX                     T21.X, T3.W, PV.W,                           ; 019FCC03 02A00190
	  ADD_INT               * T0.W, T1.Z, literal.x,                       ; 801FA801 60001A10
	24(3.363116e-44), 0(0.000000e+00)                                      ; 00000018 00000000
	  LSHR                  * T22.X, PV.W, literal.x,                      ; 801FACFE 02C00B10
	2(2.802597e-45), 0(0.000000e+00)                                       ; 00000002 00000000

bytecode 950 dw -- 25 gprs -- 1 nstack -------------
shader 1 -- E
--------------------------------------
input 0 : 1024
input 1 : 1
input 2 : 1
input 3 : 65536
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 3892465422
input 10 : 4952064
input 11 : 26972160
input 12 : 27500544
input 13 : 27762688
input 14 : 30908416
Using 2 pipes, 2 wavefronts per thread block, allocating 0 dwords lds.
*** evergreen_set_global_binding first = 0 n = 5
*** evergreen_set_compute_resources: start = 0 count = 0
* r600_compute_global_transfer_map()
level = 0, usage = 1, box(x = 0, y = 0, z = 0 width = 4951104, height = 1, depth = 1)
Buffer id = 0 offset = 0 (box.x)
* r600_compute_global_transfer_map()
level = 0, usage = 1, box(x = 0, y = 0, z = 0 width = 262144, height = 1, depth = 1)
Buffer id = 3 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 1310720 array_size = 0
* compute_memory_alloc() size_in_dw = 327680 (1310720 bytes)
  + Adding item 0x7f4354006880 id = 6 size = 327680 (1310720 bytes)
*** r600_compute_global_buffer_create
width = 4868304 array_size = 0
* compute_memory_alloc() size_in_dw = 1217076 (4868304 bytes)
  + Adding item 0x7f4354006a20 id = 7 size = 1217076 (4868304 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 4868304, height = 1, depth = 1)
Buffer id = 7 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 15330128 array_size = 0
* compute_memory_alloc() size_in_dw = 3832532 (15330128 bytes)
  + Adding item 0x7f4354006d60 id = 8 size = 3832532 (15330128 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 15330128, height = 1, depth = 1)
Buffer id = 8 offset = 0 (box.x)
*** evergreen_create_compute_state
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 4
* compute_memory_finalize_pending()
  + list: offset = 1238016 id = 1 size = 5505024 (22020096 bytes)
  + list: offset = 6743040 id = 2 size = 131073 (524292 bytes)
  + list: offset = 6940672 id = 4 size = 786432 (3145728 bytes)
  + list: offset = 7727104 id = 5 size = 132 (528 bytes)
* compute_memory_grow_pool() new_size_in_dw = 11802624 (47210496 bytes)
  Aligned size = 11802624 (47210496 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 30912512
* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 47210496
* compute_memory_prealloc_chunk() size_in_dw = 327680
  + Found space for Item 0x7f4354006880 id = 6 start_in_dw = 0 (0 bytes) size_in_dw = 327680 (1310720 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 0
* compute_memory_prealloc_chunk() size_in_dw = 1217076
  + Found space for Item 0x7f4354006a20 id = 7 start_in_dw = 7728128 (30912512 bytes) size_in_dw = 1217076 (4868304 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 7728128
* compute_memory_prealloc_chunk() size_in_dw = 3832532
* compute_memory_grow_pool() new_size_in_dw = 11804672 (47218688 bytes)
  Aligned size = 11804672 (47218688 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 47210496
--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
   {src_offset = 32, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }

===== SHADER #11 =================================== FETCH/CEDAR/EVERGREEN =====
===== 16 dw ===== 4 gprs ===== 0 stack =========================================
0000  00000002 80800800 VTX 3 @4
 0004  7c000000 88cd1001 00080000 VFETCH              R1.xyzw, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0008  7c000000 88cd1002 00080010 VFETCH              R2.xyzw, R0.x + 16b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
 0012  7c000000 88cd1003 00080020 VFETCH              R3.xyzw, R0.x + 32b ,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:35 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END

===== SHADER #12 ====================================== VS/CEDAR/EVERGREEN =====
===== 24 dw ===== 5 gprs ===== 1 stack =========================================
0000  00000000 84c00000 CALL_FS @0
0002  00000004 a01c0000 ALU 8 @8
 0008  00000001 00600c90     1      x: MOV                R3.x,  R1.x
 0010  00000401 20600c90            y: MOV                R3.y,  R1.y
 0012  00000801 40600c90            z: MOV                R3.z,  R1.z
 0014  80000c01 60600c90            w: MOV                R3.w,  R1.w
 0016  00000002 00800c90     2      x: MOV                R4.x,  R2.x
 0018  00000402 20800c90            y: MOV                R4.y,  R2.y
 0020  00000802 40800c90            z: MOV                R4.z,  R2.z
 0022  80000c02 60800c90            w: MOV                R4.w,  R2.w
0004  c001a03c 95000688 EXPORT_DONE        POS   60    R3.xyzw
0006  c0024000 95200688 EXPORT_DONE        PARAM 0     R4.xyzw  EOP
===== SHADER_END ===============================================================


===== SHADER #12 OPT ================================== VS/CEDAR/EVERGREEN =====
===== 6 dw ===== 3 gprs ===== 1 stack ==========================================
0000  00000000 84c00000 CALL_FS @0
0002  c0014000 95000688 EXPORT_DONE        PARAM 0     R2.xyzw
0004  c000a03c 95200688 EXPORT_DONE        POS   60    R1.xyzw  EOP
===== SHADER_END ===============================================================

--------------------------------------------------------------
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: TEX TEMP[0], IN[0].xyyy, SAMP[0], 2D
  1: MOV OUT[0], TEMP[0]
  2: END

===== SHADER #13 ====================================== PS/CEDAR/EVERGREEN =====
===== 36 dw ===== 5 gprs ===== 0 stack =========================================
0000  00000004 a01c0000 ALU 8 @8
 0008  00380400 00146b80     1      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
 0010  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
 0012  00380400 40546b90            z: INTERP_ZW          R2.z,  R0.y, Param0.x         VEC_210
 0014  80380000 60546b90            w: INTERP_ZW          R2.w,  R0.x, Param0.x         VEC_210
 0016  00380400 00546b10     2      x: INTERP_XY          R2.x,  R0.y, Param0.x         VEC_210
 0018  00380000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param0.x         VEC_210
 0020  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
 0022  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
0002  0000000c 80400000 TEX 1 @24
 0024  00021110 f00d1004 fc800000 SAMPLE              R4.xyzw, R2.xy__,   RID:17, SID:0 CT:NNNN
0004  0000000e a00c0000 ALU 4 @28
 0028  00000004 00600c90     3      x: MOV                R3.x,  R4.x
 0030  00000404 20600c90            y: MOV                R3.y,  R4.y
 0032  00000804 40600c90            z: MOV                R3.z,  R4.z
 0034  80000c04 60600c90            w: MOV                R3.w,  R4.w
0006  c0018000 95200688 EXPORT_DONE        PIXEL 0     R3.xyzw  EOP
===== SHADER_END ===============================================================


===== SHADER #13 OPT ================================== PS/CEDAR/EVERGREEN =====
===== 20 dw ===== 1 gprs ===== 0 stack =========================================
0000  00000003 a00c0000 ALU 4 @6
 0006  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
 0008  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
 0010  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
 0012  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
0002  00000008 80400000 TEX 1 @16
 0016  00001110 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:17, SID:0 CT:NNNN
0004  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
===== SHADER_END ===============================================================

--------------------------------------------------------------
Vertex elements state:
   {src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }

===== SHADER #14 =================================== FETCH/CEDAR/EVERGREEN =====
===== 8 dw ===== 2 gprs ===== 0 stack ==========================================
0000  00000002 80800000 VTX 1 @4
 0004  7c000000 87961001 00080000 VFETCH              R1.xy01, R0.x,   RID:0  VERTEX MFC:31 UCF:0 FMT(DTA:30 NUM:0 COMP:0 MODE:1)
0002  00000000 85000000 RET @0
===== SHADER_END ===============================================================

--------------------------------------------------------------
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: END

===== SHADER #15 ====================================== VS/CEDAR/EVERGREEN =====
===== 40 dw ===== 4 gprs ===== 1 stack =========================================
0000  00000000 84c00000 CALL_FS @0
0002  40000004 a03c0000 ALU 16 @8 KC0[CB0:0-15]
 0008  00100001 00600090     1      x: MUL                R3.x,  R1.x, KC0[0].x
 0010  00900001 20600090            y: MUL                R3.y,  R1.x, KC0[0].y
 0012  01100001 40600090            z: MUL                R3.z,  R1.x, KC0[0].z
 0014  81900001 60600090            w: MUL                R3.w,  R1.x, KC0[0].w
 0016  00102401 006280fe     2      x: MULADD             R3.x,  R1.y, KC0[1].x, PV.x
 0018  00902401 206284fe            y: MULADD             R3.y,  R1.y, KC0[1].y, PV.y
 0020  01102401 406288fe            z: MULADD             R3.z,  R1.y, KC0[1].z, PV.z
 0022  81902401 60628cfe            w: MULADD             R3.w,  R1.y, KC0[1].w, PV.w
 0024  00104801 006280fe     3      x: MULADD             R3.x,  R1.z, KC0[2].x, PV.x
 0026  00904801 206284fe            y: MULADD             R3.y,  R1.z, KC0[2].y, PV.y
 0028  01104801 406288fe            z: MULADD             R3.z,  R1.z, KC0[2].z, PV.z
 0030  81904801 60628cfe            w: MULADD             R3.w,  R1.z, KC0[2].w, PV.w
 0032  00106c01 004280fe     4      x: MULADD             R2.x,  R1.w, KC0[3].x, PV.x
 0034  00906c01 204284fe            y: MULADD             R2.y,  R1.w, KC0[3].y, PV.y
 0036  01106c01 404288fe            z: MULADD             R2.z,  R1.w, KC0[3].z, PV.z
 0038  81906c01 60428cfe            w: MULADD             R2.w,  R1.w, KC0[3].w, PV.w
0004  c001203c 95000688 EXPORT_DONE        POS   60    R2.xyzw
0006  c0004000 95200fff EXPORT_DONE        PARAM 0     R0.____  EOP
===== SHADER_END ===============================================================


===== SHADER #15 OPT ================================== VS/CEDAR/EVERGREEN =====
===== 40 dw ===== 2 gprs ===== 1 stack =========================================
0000  00000000 84c00000 CALL_FS @0
0002  40000004 a03c0000 ALU 16 @8 KC0[CB0:0-15]
 0008  01900001 0f800090     1      x: MUL                T0.x,  R1.x, KC0[0].w
 0010  81100001 2f800090            y: MUL                T0.y,  R1.x, KC0[0].z
 0012  01902401 0f82807c     2      x: MULADD             T0.x,  R1.y, KC0[1].w, T0.x
 0014  01102401 2f82847c            y: MULADD             T0.y,  R1.y, KC0[1].z, T0.y
 0016  00900001 4f800090            z: MUL                T0.z,  R1.x, KC0[0].y
 0018  80100001 6f800090            w: MUL                T0.w,  R1.x, KC0[0].x
 0020  01904801 0fa2807c     3      x: MULADD             T1.x,  R1.z, KC0[2].w, T0.x
 0022  00902401 4f82887c            z: MULADD             T0.z,  R1.y, KC0[1].y, T0.z
 0024  80102401 6f828c7c            w: MULADD             T0.w,  R1.y, KC0[1].x, T0.w
 0026  00904801 0f82887c     4      x: MULADD             T0.x,  R1.z, KC0[2].y, T0.z
 0028  00104801 2f828c7c            y: MULADD             T0.y,  R1.z, KC0[2].x, T0.w
 0030  81104801 2fa6847c            t: MULADD             T1.y,  R1.z, KC0[2].z, T0.y   SCL_122
 0032  00106c01 0002847c     5      x: MULADD             R0.x,  R1.w, KC0[3].x, T0.y
 0034  00906c01 2002807c            y: MULADD             R0.y,  R1.w, KC0[3].y, T0.x
 0036  01106c01 4006847d            z: MULADD             R0.z,  R1.w, KC0[3].z, T1.y   VEC_021
 0038  81906c01 6006807d            w: MULADD             R0.w,  R1.w, KC0[3].w, T1.x   VEC_021
0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
0006  c0004000 95200fff EXPORT_DONE        PARAM 0     R0.____  EOP
===== SHADER_END ===============================================================

--------------------------------------------------------------
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
DCL CONST[0..3]
  0: MOV OUT[0], CONST[3]
  1: END

===== SHADER #16 ====================================== PS/CEDAR/EVERGREEN =====
===== 12 dw ===== 2 gprs ===== 0 stack =========================================
0000  40000002 a00c0000 ALU 4 @4 KC0[CB0:0-15]
 0004  00000083 00200c90     1      x: MOV                R1.x,  KC0[3].x
 0006  00000483 20200c90            y: MOV                R1.y,  KC0[3].y
 0008  00000883 40200c90            z: MOV                R1.z,  KC0[3].z
 0010  80000c83 60200c90            w: MOV                R1.w,  KC0[3].w
0002  c0008000 95200688 EXPORT_DONE        PIXEL 0     R1.xyzw  EOP
===== SHADER_END ===============================================================


===== SHADER #16 OPT ================================== PS/CEDAR/EVERGREEN =====
===== 12 dw ===== 1 gprs ===== 0 stack =========================================
0000  40000002 a00c0000 ALU 4 @4 KC0[CB0:0-15]
 0004  00000083 00000c90     1      x: MOV                R0.x,  KC0[3].x
 0006  00000483 20000c90            y: MOV                R0.y,  KC0[3].y
 0008  00000883 40000c90            z: MOV                R0.z,  KC0[3].z
 0010  80000c83 60000c90            w: MOV                R0.w,  KC0[3].w
0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
===== SHADER_END ===============================================================* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 47218688


* compute_memory_prealloc_chunk() size_in_dw = 3832532
* compute_memory_grow_pool() new_size_in_dw = 13722624 (54890496 bytes)
  Aligned size = 13722624 (54890496 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 47218688
--------------------------------------------------------------
VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: MOV OUT[2], IN[2]
  3: END

===== SHADER #17 ====================================== VS/CEDAR/EVERGREEN =====
===== 32 dw ===== 7 gprs ===== 1 stack =========================================
0000  00000000 84c00000 CALL_FS @0
0002  00000004 a02c0000 ALU 12 @8
 0008  00000001 00800c90     1      x: MOV                R4.x,  R1.x
 0010  00000401 20800c90            y: MOV                R4.y,  R1.y
 0012  00000801 40800c90            z: MOV                R4.z,  R1.z
 0014  80000c01 60800c90            w: MOV                R4.w,  R1.w
 0016  00000002 00a00c90     2      x: MOV                R5.x,  R2.x
 0018  00000402 20a00c90            y: MOV                R5.y,  R2.y
 0020  00000802 40a00c90            z: MOV                R5.z,  R2.z
 0022  80000c02 60a00c90            w: MOV                R5.w,  R2.w
 0024  00000003 00c00c90     3      x: MOV                R6.x,  R3.x
 0026  00000403 20c00c90            y: MOV                R6.y,  R3.y
 0028  00000803 40c00c90            z: MOV                R6.z,  R3.z
 0030  80000c03 60c00c90            w: MOV                R6.w,  R3.w
0004  c002203c 95000688 EXPORT_DONE        POS   60    R4.xyzw
0006  c002c000 95210688 EXPORT_DONE        PARAM 0-1   R5-6.xyzw  EOP
===== SHADER_END ===============================================================


===== SHADER #17 OPT ================================== VS/CEDAR/EVERGREEN =====
===== 8 dw ===== 4 gprs ===== 1 stack ==========================================
0000  00000000 84c00000 CALL_FS @0
0002  c001c001 94c00688 EXPORT             PARAM 1     R3.xyzw
0004  c0014000 95000688 EXPORT_DONE        PARAM 0     R2.xyzw
0006  c000a03c 95200688 EXPORT_DONE        POS   60    R1.xyzw  EOP
===== SHADER_END ===============================================================

--------------------------------------------------------------
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..3]
DCL TEMP[0], LOCAL
  0: TEX TEMP[0], IN[0].xyyy, SAMP[0], 2D
  1: KILL_IF -TEMP[0]
  2: MOV OUT[0], CONST[3]
  3: END

===== SHADER #18 ====================================== PS/CEDAR/EVERGREEN =====
===== 48 dw ===== 5 gprs ===== 0 stack =========================================
0000  00000005 a01c0000 ALU 8 @10
 0010  00380400 00146b80     1      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
 0012  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
 0014  00380400 40546b90            z: INTERP_ZW          R2.z,  R0.y, Param0.x         VEC_210
 0016  80380000 60546b90            w: INTERP_ZW          R2.w,  R0.x, Param0.x         VEC_210
 0018  00380400 00546b10     2      x: INTERP_XY          R2.x,  R0.y, Param0.x         VEC_210
 0020  00380000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param0.x         VEC_210
 0022  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
 0024  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
0002  0000000e 80400000 TEX 1 @28
 0028  00021110 f00d1004 fc800000 SAMPLE              R4.xyzw, R2.xy__,   RID:17, SID:0 CT:NNNN
0004  00000010 a00c0000 ALU 4 @32
 0032  020080f8 00001680     3      x: KILLGT             __.x,  0, -R4.x
 0034  028080f8 20001680            y: KILLGT             __.y,  0, -R4.y
 0036  030080f8 40001680            z: KILLGT             __.z,  0, -R4.z
 0038  838080f8 60001680            w: KILLGT             __.w,  0, -R4.w
0006  40000014 a00c0000 ALU 4 @40 KC0[CB0:0-15]
 0040  00000083 00600c90     4      x: MOV                R3.x,  KC0[3].x
 0042  00000483 20600c90            y: MOV                R3.y,  KC0[3].y
 0044  00000883 40600c90            z: MOV                R3.z,  KC0[3].z
 0046  80000c83 60600c90            w: MOV                R3.w,  KC0[3].w
0008  c0018000 95200688 EXPORT_DONE        PIXEL 0     R3.xyzw  EOP
===== SHADER_END ===============================================================


===== SHADER #18 OPT ================================== PS/CEDAR/EVERGREEN =====
===== 36 dw ===== 1 gprs ===== 0 stack =========================================
0000  00000004 a00c0000 ALU 4 @8
 0008  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
 0010  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
0002  00000008 80400000 TEX 1 @16
 0016  00001110 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:17, SID:0 CT:NNNN
0004  4000000a a01c0000 ALU 8 @20 KC0[CB0:0-15]
 0020  028000f8 00001680     2      x: KILLGT             __.x,  0, -R0.y
 0022  030000f8 20001680            y: KILLGT             __.y,  0, -R0.z
 0024  838000f8 40001680            z: KILLGT             __.z,  0, -R0.w
 0026  020000f8 00001680     3      x: KILLGT             __.x,  0, -R0.x
 0028  00000483 20000c90            y: MOV                R0.y,  KC0[3].y
 0030  00000883 40000c90            z: MOV                R0.z,  KC0[3].z
 0032  00000c83 60000c90            w: MOV                R0.w,  KC0[3].w
 0034  80000083 00000c90            t: MOV                R0.x,  KC0[3].x
0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
===== SHADER_END ===============================================================

* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 54890496
* compute_memory_prealloc_chunk() size_in_dw = 3832532
  + Found space for Item 0x7f4354006d60 id = 8 start_in_dw = 8945664 (35782656 bytes) size_in_dw = 3832532 (15330128 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 8945664
bind rat: 0 
*** evergreen_launch_grid: pc = 0
; ModuleID = 'radeon'
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"

%struct.Ray.2 = type { %struct.Point.0, %struct.Vector.1, float, float, float, [3 x float] }
%struct.Point.0 = type { float, float, float }
%struct.Vector.1 = type { float, float, float }
%struct.RayHit.4 = type { float, float, float, i32, i32 }
%struct.QBVHNode.5 = type { [2 x [3 x <4 x float>]], <4 x i32> }
%struct.QuadTiangle.6 = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x i32>, <4 x i32> }

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

; Function Attrs: nounwind
define void @Intersect(%struct.Ray.2 addrspace(1)* nocapture readonly %rays, %struct.RayHit.4 addrspace(1)* nocapture %rayHits, %struct.QBVHNode.5 addrspace(1)* nocapture readonly %nodes, %struct.QuadTiangle.6 addrspace(1)* nocapture readonly %quadTris, i32 %rayCount, i32 addrspace(3)* nocapture %nodeStacks) #1 {
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #0
  %x.i8.i = tail call i32 @llvm.r600.read.local.size.x() #0
  %1 = mul i32 %x.i8.i, %x.i.i
  %x.i1.i = tail call i32 @llvm.r600.read.tidig.x() #0
  %2 = add i32 %x.i1.i, %1
  %3 = icmp ult i32 %2, %rayCount
  br i1 %3, label %4, label %271

; <label>:4                                       ; preds = %0
  %5 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2
  %6 = bitcast %struct.Ray.2 addrspace(1)* %5 to <4 x float> addrspace(1)*
  %7 = getelementptr inbounds %struct.Ray.2 addrspace(1)* %rays, i32 %2, i32 1, i32 1
  %8 = bitcast float addrspace(1)* %7 to <4 x float> addrspace(1)*
  %9 = load <4 x float> addrspace(1)* %6, align 16, !tbaa !4
  %10 = load <4 x float> addrspace(1)* %8, align 16, !tbaa !4
  %11 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
  %12 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
  %13 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
  %14 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
  %15 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> zeroinitializer
  %16 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
  %17 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
  %18 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
  %19 = extractelement <4 x float> %9, i32 3
  %20 = fdiv float 1.000000e+00, %19, !fpmath !7
  %21 = insertelement <4 x float> undef, float %20, i32 0
  %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer
  %23 = extractelement <4 x float> %10, i32 0
  %24 = fdiv float 1.000000e+00, %23, !fpmath !7
  %25 = insertelement <4 x float> undef, float %24, i32 0
  %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> zeroinitializer
  %27 = extractelement <4 x float> %10, i32 1
  %28 = fdiv float 1.000000e+00, %27, !fpmath !7
  %29 = insertelement <4 x float> undef, float %28, i32 0
  %30 = shufflevector <4 x float> %29, <4 x float> undef, <4 x i32> zeroinitializer
  %31 = bitcast float %19 to i32
  %.lobit.i6 = lshr i32 %31, 31
  %32 = bitcast float %23 to i32
  %.lobit.i5 = lshr i32 %32, 31
  %33 = bitcast float %27 to i32
  %.lobit.i = lshr i32 %33, 31
  %34 = xor i32 %.lobit.i6, 1
  %35 = xor i32 %.lobit.i5, 1
  %36 = xor i32 %.lobit.i, 1
  %37 = shl i32 %x.i1.i, 5
  %38 = getelementptr inbounds i32 addrspace(3)* %nodeStacks, i32 %37
  store i32 0, i32 addrspace(3)* %38, align 4, !tbaa !8
  %39 = or i32 %37, 1
  br label %.lr.ph

.loopexit.loopexit:                               ; preds = %QuadTriangle_Intersect.exit
  %.lcssa62 = phi float [ %264, %QuadTriangle_Intersect.exit ]
  %.lcssa61 = phi float [ %263, %QuadTriangle_Intersect.exit ]
  %.lcssa60 = phi float [ %262, %QuadTriangle_Intersect.exit ]
  %.lcssa59 = phi i32 [ %261, %QuadTriangle_Intersect.exit ]
  %.lcssa58 = phi i32 [ %260, %QuadTriangle_Intersect.exit ]
  %.lcssa57 = phi <4 x float> [ %259, %QuadTriangle_Intersect.exit ]
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.loopexit, %107
  %.lcssa21 = phi float [ %.ph1446, %107 ], [ %.lcssa62, %.loopexit.loopexit ]
  %.lcssa20 = phi float [ %.ph1345, %107 ], [ %.lcssa61, %.loopexit.loopexit ]
  %.lcssa19 = phi float [ %.ph1244, %107 ], [ %.lcssa60, %.loopexit.loopexit ]
  %.lcssa18 = phi i32 [ %.ph1143, %107 ], [ %.lcssa59, %.loopexit.loopexit ]
  %.lcssa17 = phi i32 [ %.ph1042, %107 ], [ %.lcssa58, %.loopexit.loopexit ]
  %.lcssa16 = phi <4 x float> [ %.ph41, %107 ], [ %.lcssa57, %.loopexit.loopexit ]
  %40 = icmp sgt i32 %todoNode.022.lcssa, 0
  br i1 %40, label %.lr.ph, label %.outer._crit_edge.loopexit52

.lr.ph:                                           ; preds = %.loopexit, %4
  %todoNode.0.ph47 = phi i32 [ 0, %4 ], [ %.lcssa55, %.loopexit ]
  %.ph1446 = phi float [ undef, %4 ], [ %.lcssa21, %.loopexit ]
  %.ph1345 = phi float [ undef, %4 ], [ %.lcssa20, %.loopexit ]
  %.ph1244 = phi float [ undef, %4 ], [ %.lcssa19, %.loopexit ]
  %.ph1143 = phi i32 [ -1, %4 ], [ %.lcssa18, %.loopexit ]
  %.ph1042 = phi i32 [ -1, %4 ], [ %.lcssa17, %.loopexit ]
  %.ph41 = phi <4 x float> [ %18, %4 ], [ %.lcssa16, %.loopexit ]
  br label %41

; <label>:41                                      ; preds = %46, %.lr.ph
  %todoNode.022 = phi i32 [ %todoNode.0.ph47, %.lr.ph ], [ %105, %46 ]
  %.sum = add i32 %todoNode.022, %37
  %42 = getelementptr inbounds i32 addrspace(3)* %nodeStacks, i32 %.sum
  %43 = load i32 addrspace(3)* %42, align 4, !tbaa !8
  %44 = add nsw i32 %todoNode.022, -1
  %45 = icmp slt i32 %43, 0
  br i1 %45, label %107, label %46

; <label>:46                                      ; preds = %41
  %47 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %.lobit.i6, i32 0
  %48 = load <4 x float> addrspace(1)* %47, align 16, !tbaa !4
  %49 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %34, i32 0
  %50 = load <4 x float> addrspace(1)* %49, align 16, !tbaa !4
  %51 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %.lobit.i5, i32 1
  %52 = load <4 x float> addrspace(1)* %51, align 16, !tbaa !4
  %53 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %35, i32 1
  %54 = load <4 x float> addrspace(1)* %53, align 16, !tbaa !4
  %55 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %.lobit.i, i32 2
  %56 = load <4 x float> addrspace(1)* %55, align 16, !tbaa !4
  %57 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 0, i32 %36, i32 2
  %58 = load <4 x float> addrspace(1)* %57, align 16, !tbaa !4
  %59 = fsub <4 x float> %48, %11
  %60 = fmul <4 x float> %22, %59
  %61 = fcmp olt <4 x float> %17, %60
  %.v.i.i = select <4 x i1> %61, <4 x float> %60, <4 x float> %17
  %62 = fsub <4 x float> %50, %11
  %63 = fmul <4 x float> %22, %62
  %64 = fcmp olt <4 x float> %63, %.ph41
  %.v.i5.i = select <4 x i1> %64, <4 x float> %63, <4 x float> %.ph41
  %65 = fsub <4 x float> %52, %12
  %66 = fmul <4 x float> %26, %65
  %67 = fcmp olt <4 x float> %.v.i.i, %66
  %.v.i4.i = select <4 x i1> %67, <4 x float> %66, <4 x float> %.v.i.i
  %68 = fsub <4 x float> %54, %12
  %69 = fmul <4 x float> %26, %68
  %70 = fcmp olt <4 x float> %69, %.v.i5.i
  %.v.i3.i = select <4 x i1> %70, <4 x float> %69, <4 x float> %.v.i5.i
  %71 = fsub <4 x float> %56, %13
  %72 = fmul <4 x float> %30, %71
  %73 = fcmp olt <4 x float> %.v.i4.i, %72
  %.v.i2.i = select <4 x i1> %73, <4 x float> %72, <4 x float> %.v.i4.i
  %74 = fsub <4 x float> %58, %13
  %75 = fmul <4 x float> %30, %74
  %76 = fcmp olt <4 x float> %75, %.v.i3.i
  %.v.i1.i = select <4 x i1> %76, <4 x float> %75, <4 x float> %.v.i3.i
  %77 = fcmp oge <4 x float> %.v.i1.i, %.v.i2.i
  %78 = sext <4 x i1> %77 to <4 x i32>
  %79 = getelementptr inbounds %struct.QBVHNode.5 addrspace(1)* %nodes, i32 %43, i32 1
  %80 = load <4 x i32> addrspace(1)* %79, align 16, !tbaa !10
  %81 = extractelement <4 x i32> %80, i32 3
  store i32 %81, i32 addrspace(3)* %42, align 4, !tbaa !8
  %82 = extractelement <4 x i32> %78, i32 3
  %83 = icmp ne i32 %81, -1
  %not. = icmp ne i32 %82, 0
  %. = and i1 %83, %not.
  %84 = zext i1 %. to i32
  %85 = add nsw i32 %84, %44
  %86 = extractelement <4 x i32> %80, i32 2
  %.sum1 = add i32 %84, %.sum
  %87 = getelementptr inbounds i32 addrspace(3)* %nodeStacks, i32 %.sum1
  store i32 %86, i32 addrspace(3)* %87, align 4, !tbaa !8
  %88 = extractelement <4 x i32> %78, i32 2
  %89 = icmp ne i32 %86, -1
  %not.7 = icmp ne i32 %88, 0
  %90 = and i1 %89, %not.7
  %91 = zext i1 %90 to i32
  %92 = add nsw i32 %85, %91
  %93 = extractelement <4 x i32> %80, i32 1
  %.sum2 = add i32 %92, %39
  %94 = getelementptr inbounds i32 addrspace(3)* %nodeStacks, i32 %.sum2
  store i32 %93, i32 addrspace(3)* %94, align 4, !tbaa !8
  %95 = extractelement <4 x i32> %78, i32 1
  %96 = icmp ne i32 %93, -1
  %not.8 = icmp ne i32 %95, 0
  %.4 = and i1 %96, %not.8
  %97 = zext i1 %.4 to i32
  %98 = add nsw i32 %92, %97
  %99 = extractelement <4 x i32> %80, i32 0
  %.sum3 = add i32 %98, %39
  %100 = getelementptr inbounds i32 addrspace(3)* %nodeStacks, i32 %.sum3
  store i32 %99, i32 addrspace(3)* %100, align 4, !tbaa !8
  %101 = extractelement <4 x i32> %78, i32 0
  %102 = icmp ne i32 %99, -1
  %not.9 = icmp ne i32 %101, 0
  %103 = and i1 %102, %not.9
  %104 = zext i1 %103 to i32
  %105 = add nsw i32 %98, %104
  %106 = icmp sgt i32 %105, -1
  br i1 %106, label %41, label %.outer._crit_edge.loopexit

; <label>:107                                     ; preds = %41
  %.lcssa55 = phi i32 [ %44, %41 ]
  %.lcssa = phi i32 [ %43, %41 ]
  %todoNode.022.lcssa = phi i32 [ %todoNode.022, %41 ]
  %108 = lshr i32 %.lcssa, 27
  %109 = and i32 %108, 15
  %110 = and i32 %.lcssa, 134217727
  %111 = add nuw nsw i32 %110, 1
  %112 = add nuw nsw i32 %111, %109
  %113 = icmp ult i32 %110, %112
  br i1 %113, label %.lr.ph34.preheader, label %.loopexit

.lr.ph34.preheader:                               ; preds = %107
  br label %.lr.ph34

.lr.ph34:                                         ; preds = %.lr.ph34.preheader, %QuadTriangle_Intersect.exit
  %primNumber.032 = phi i32 [ %265, %QuadTriangle_Intersect.exit ], [ %110, %.lr.ph34.preheader ]
  %114 = phi float [ %264, %QuadTriangle_Intersect.exit ], [ %.ph1446, %.lr.ph34.preheader ]
  %115 = phi float [ %263, %QuadTriangle_Intersect.exit ], [ %.ph1345, %.lr.ph34.preheader ]
  %116 = phi float [ %262, %QuadTriangle_Intersect.exit ], [ %.ph1244, %.lr.ph34.preheader ]
  %117 = phi i32 [ %261, %QuadTriangle_Intersect.exit ], [ %.ph1143, %.lr.ph34.preheader ]
  %118 = phi i32 [ %260, %QuadTriangle_Intersect.exit ], [ %.ph1042, %.lr.ph34.preheader ]
  %119 = phi <4 x float> [ %259, %QuadTriangle_Intersect.exit ], [ %.ph41, %.lr.ph34.preheader ]
  %120 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 0
  %121 = load <4 x float> addrspace(1)* %120, align 16, !tbaa !12
  %122 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 1
  %123 = load <4 x float> addrspace(1)* %122, align 16, !tbaa !14
  %124 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 2
  %125 = load <4 x float> addrspace(1)* %124, align 16, !tbaa !15
  %126 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 3
  %127 = load <4 x float> addrspace(1)* %126, align 16, !tbaa !16
  %128 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 4
  %129 = load <4 x float> addrspace(1)* %128, align 16, !tbaa !17
  %130 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 5
  %131 = load <4 x float> addrspace(1)* %130, align 16, !tbaa !18
  %132 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 6
  %133 = load <4 x float> addrspace(1)* %132, align 16, !tbaa !19
  %134 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 7
  %135 = load <4 x float> addrspace(1)* %134, align 16, !tbaa !20
  %136 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 8
  %137 = load <4 x float> addrspace(1)* %136, align 16, !tbaa !21
  %138 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 9
  %139 = load <4 x i32> addrspace(1)* %138, align 16, !tbaa !22
  %140 = getelementptr inbounds %struct.QuadTiangle.6 addrspace(1)* %quadTris, i32 %primNumber.032, i32 10
  %141 = load <4 x i32> addrspace(1)* %140, align 16, !tbaa !23
  %142 = fmul <4 x float> %16, %135
  %143 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %142
  %144 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %137, <4 x float> %143) #2
  %145 = fmul <4 x float> %14, %137
  %146 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %145
  %147 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %16, <4 x float> %133, <4 x float> %146) #2
  %148 = fmul <4 x float> %15, %133
  %149 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %148
  %150 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %14, <4 x float> %135, <4 x float> %149) #2
  %151 = fmul <4 x float> %129, %147
  %152 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %144, <4 x float> %127, <4 x float> %151) #2
  %153 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %150, <4 x float> %131, <4 x float> %152) #2
  %154 = fsub <4 x float> %11, %121
  %155 = fsub <4 x float> %12, %123
  %156 = fsub <4 x float> %13, %125
  %157 = fmul <4 x float> %155, %147
  %158 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %154, <4 x float> %144, <4 x float> %157) #2
  %159 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %156, <4 x float> %150, <4 x float> %158) #2
  %160 = fdiv <4 x float> %159, %153, !fpmath !7
  %161 = fmul <4 x float> %156, %129
  %162 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %161
  %163 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %155, <4 x float> %131, <4 x float> %162) #2
  %164 = fmul <4 x float> %154, %131
  %165 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %164
  %166 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %156, <4 x float> %127, <4 x float> %165) #2
  %167 = fmul <4 x float> %155, %127
  %168 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %167
  %169 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %154, <4 x float> %129, <4 x float> %168) #2
  %170 = fmul <4 x float> %15, %166
  %171 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %14, <4 x float> %163, <4 x float> %170) #2
  %172 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %16, <4 x float> %169, <4 x float> %171) #2
  %173 = fdiv <4 x float> %172, %153, !fpmath !7
  %174 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %160
  %175 = fsub <4 x float> %174, %173
  %176 = fmul <4 x float> %135, %166
  %177 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %133, <4 x float> %163, <4 x float> %176) #2
  %178 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %137, <4 x float> %169, <4 x float> %177) #2
  %179 = fdiv <4 x float> %178, %153, !fpmath !7
  %180 = extractelement <4 x float> %119, i32 0
  %181 = fcmp une <4 x float> %153, zeroinitializer
  %182 = zext <4 x i1> %181 to <4 x i32>
  %183 = icmp ne <4 x i32> %182, zeroinitializer
  %184 = sext <4 x i1> %183 to <4 x i32>
  %185 = fcmp oge <4 x float> %175, zeroinitializer
  %186 = zext <4 x i1> %185 to <4 x i32>
  %187 = icmp ne <4 x i32> %186, zeroinitializer
  %188 = select <4 x i1> %187, <4 x i32> %184, <4 x i32> zeroinitializer
  %189 = fcmp oge <4 x float> %160, zeroinitializer
  %190 = zext <4 x i1> %189 to <4 x i32>
  %191 = icmp ne <4 x i32> %190, zeroinitializer
  %192 = select <4 x i1> %191, <4 x i32> %188, <4 x i32> zeroinitializer
  %193 = fcmp oge <4 x float> %173, zeroinitializer
  %194 = zext <4 x i1> %193 to <4 x i32>
  %195 = icmp ne <4 x i32> %194, zeroinitializer
  %196 = select <4 x i1> %195, <4 x i32> %192, <4 x i32> zeroinitializer
  %197 = fcmp ogt <4 x float> %179, %17
  %198 = zext <4 x i1> %197 to <4 x i32>
  %199 = icmp ne <4 x i32> %198, zeroinitializer
  %200 = select <4 x i1> %199, <4 x i32> %196, <4 x i32> zeroinitializer
  %201 = extractelement <4 x i32> %200, i32 0
  %202 = icmp eq i32 %201, 0
  %.pre.i = extractelement <4 x float> %179, i32 0
  br i1 %202, label %._crit_edge4.i, label %203

; <label>:203                                     ; preds = %.lr.ph34
  %204 = fcmp olt float %.pre.i, %180
  br label %._crit_edge4.i

._crit_edge4.i:                                   ; preds = %203, %.lr.ph34
  %205 = phi i1 [ %204, %203 ], [ false, %.lr.ph34 ]
  %206 = select i1 %205, float %.pre.i, float %180
  %207 = extractelement <4 x float> %160, i32 0
  %..i = select i1 %205, float %207, float 0.000000e+00
  %208 = extractelement <4 x float> %173, i32 0
  %209 = select i1 %205, float %208, float 0.000000e+00
  %210 = extractelement <4 x i32> %139, i32 0
  %.1.i = select i1 %205, i32 %210, i32 -1
  %211 = extractelement <4 x i32> %141, i32 0
  %212 = select i1 %205, i32 %211, i32 -1
  %213 = extractelement <4 x i32> %200, i32 1
  %214 = icmp eq i32 %213, 0
  %.pre5.i = extractelement <4 x float> %179, i32 1
  br i1 %214, label %._crit_edge3.i, label %215

; <label>:215                                     ; preds = %._crit_edge4.i
  %216 = fcmp olt float %.pre5.i, %206
  br label %._crit_edge3.i

._crit_edge3.i:                                   ; preds = %215, %._crit_edge4.i
  %217 = phi i1 [ %216, %215 ], [ false, %._crit_edge4.i ]
  %218 = select i1 %217, float %.pre5.i, float %206
  %219 = extractelement <4 x float> %160, i32 1
  %220 = select i1 %217, float %219, float %..i
  %221 = extractelement <4 x float> %173, i32 1
  %222 = select i1 %217, float %221, float %209
  %223 = extractelement <4 x i32> %139, i32 1
  %224 = select i1 %217, i32 %223, i32 %.1.i
  %225 = extractelement <4 x i32> %141, i32 1
  %226 = select i1 %217, i32 %225, i32 %212
  %227 = extractelement <4 x i32> %200, i32 2
  %228 = icmp eq i32 %227, 0
  %.pre7.i = extractelement <4 x float> %179, i32 2
  br i1 %228, label %._crit_edge2.i, label %229

; <label>:229                                     ; preds = %._crit_edge3.i
  %230 = fcmp olt float %.pre7.i, %218
  br label %._crit_edge2.i

._crit_edge2.i:                                   ; preds = %229, %._crit_edge3.i
  %231 = phi i1 [ %230, %229 ], [ false, %._crit_edge3.i ]
  %232 = select i1 %231, float %.pre7.i, float %218
  %233 = extractelement <4 x float> %160, i32 2
  %234 = select i1 %231, float %233, float %220
  %235 = extractelement <4 x float> %173, i32 2
  %236 = select i1 %231, float %235, float %222
  %237 = extractelement <4 x i32> %139, i32 2
  %238 = select i1 %231, i32 %237, i32 %224
  %239 = extractelement <4 x i32> %141, i32 2
  %240 = select i1 %231, i32 %239, i32 %226
  %241 = extractelement <4 x i32> %200, i32 3
  %242 = icmp eq i32 %241, 0
  %.pre9.i = extractelement <4 x float> %179, i32 3
  br i1 %242, label %._crit_edge.i, label %243

; <label>:243                                     ; preds = %._crit_edge2.i
  %244 = fcmp olt float %.pre9.i, %232
  br label %._crit_edge.i

._crit_edge.i:                                    ; preds = %243, %._crit_edge2.i
  %245 = phi i1 [ %244, %243 ], [ false, %._crit_edge2.i ]
  %246 = select i1 %245, float %.pre9.i, float %232
  %247 = extractelement <4 x i32> %139, i32 3
  %248 = select i1 %245, i32 %247, i32 %238
  %249 = icmp eq i32 %248, -1
  br i1 %249, label %QuadTriangle_Intersect.exit, label %250

; <label>:250                                     ; preds = %._crit_edge.i
  %251 = extractelement <4 x i32> %141, i32 3
  %252 = extractelement <4 x float> %173, i32 3
  %253 = extractelement <4 x float> %160, i32 3
  %254 = select i1 %245, i32 %251, i32 %240
  %255 = select i1 %245, float %252, float %236
  %256 = select i1 %245, float %253, float %234
  %257 = insertelement <4 x float> undef, float %246, i32 0
  %258 = shufflevector <4 x float> %257, <4 x float> undef, <4 x i32> zeroinitializer
  br label %QuadTriangle_Intersect.exit

QuadTriangle_Intersect.exit:                      ; preds = %250, %._crit_edge.i
  %259 = phi <4 x float> [ %119, %._crit_edge.i ], [ %258, %250 ]
  %260 = phi i32 [ %118, %._crit_edge.i ], [ %254, %250 ]
  %261 = phi i32 [ %117, %._crit_edge.i ], [ %248, %250 ]
  %262 = phi float [ %116, %._crit_edge.i ], [ %255, %250 ]
  %263 = phi float [ %115, %._crit_edge.i ], [ %256, %250 ]
  %264 = phi float [ %114, %._crit_edge.i ], [ %246, %250 ]
  %265 = add i32 %primNumber.032, 1
  %exitcond = icmp eq i32 %265, %112
  br i1 %exitcond, label %.loopexit.loopexit, label %.lr.ph34

.outer._crit_edge.loopexit:                       ; preds = %46
  %.ph1042.lcssa = phi i32 [ %.ph1042, %46 ]
  %.ph1143.lcssa = phi i32 [ %.ph1143, %46 ]
  %.ph1244.lcssa = phi float [ %.ph1244, %46 ]
  %.ph1345.lcssa = phi float [ %.ph1345, %46 ]
  %.ph1446.lcssa = phi float [ %.ph1446, %46 ]
  br label %.outer._crit_edge

.outer._crit_edge.loopexit52:                     ; preds = %.loopexit
  %.lcssa17.lcssa = phi i32 [ %.lcssa17, %.loopexit ]
  %.lcssa18.lcssa = phi i32 [ %.lcssa18, %.loopexit ]
  %.lcssa19.lcssa = phi float [ %.lcssa19, %.loopexit ]
  %.lcssa20.lcssa = phi float [ %.lcssa20, %.loopexit ]
  %.lcssa21.lcssa = phi float [ %.lcssa21, %.loopexit ]
  br label %.outer._crit_edge

.outer._crit_edge:                                ; preds = %.outer._crit_edge.loopexit52, %.outer._crit_edge.loopexit
  %.ph14.lcssa = phi float [ %.ph1446.lcssa, %.outer._crit_edge.loopexit ], [ %.lcssa21.lcssa, %.outer._crit_edge.loopexit52 ]
  %.ph13.lcssa = phi float [ %.ph1345.lcssa, %.outer._crit_edge.loopexit ], [ %.lcssa20.lcssa, %.outer._crit_edge.loopexit52 ]
  %.ph12.lcssa = phi float [ %.ph1244.lcssa, %.outer._crit_edge.loopexit ], [ %.lcssa19.lcssa, %.outer._crit_edge.loopexit52 ]
  %.ph11.lcssa = phi i32 [ %.ph1143.lcssa, %.outer._crit_edge.loopexit ], [ %.lcssa18.lcssa, %.outer._crit_edge.loopexit52 ]
  %.ph10.lcssa = phi i32 [ %.ph1042.lcssa, %.outer._crit_edge.loopexit ], [ %.lcssa17.lcssa, %.outer._crit_edge.loopexit52 ]
  %266 = getelementptr inbounds %struct.RayHit.4 addrspace(1)* %rayHits, i32 %2, i32 0
  store float %.ph14.lcssa, float addrspace(1)* %266, align 4, !tbaa !24
  %267 = getelementptr inbounds %struct.RayHit.4 addrspace(1)* %rayHits, i32 %2, i32 1
  store float %.ph13.lcssa, float addrspace(1)* %267, align 4, !tbaa !27
  %268 = getelementptr inbounds %struct.RayHit.4 addrspace(1)* %rayHits, i32 %2, i32 2
  store float %.ph12.lcssa, float addrspace(1)* %268, align 4, !tbaa !28
  %269 = getelementptr inbounds %struct.RayHit.4 addrspace(1)* %rayHits, i32 %2, i32 3
  store i32 %.ph11.lcssa, i32 addrspace(1)* %269, align 4, !tbaa !29
  %270 = getelementptr inbounds %struct.RayHit.4 addrspace(1)* %rayHits, i32 %2, i32 4
  store i32 %.ph10.lcssa, i32 addrspace(1)* %270, align 4, !tbaa !30
  br label %271

; <label>:271                                     ; preds = %.outer._crit_edge, %0
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.x() #0

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }

!opencl.kernels = !{!0}
!llvm.ident = !{!2, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3, !3}

!0 = metadata !{void (%struct.Ray.2 addrspace(1)*, %struct.RayHit.4 addrspace(1)*, %struct.QBVHNode.5 addrspace(1)*, %struct.QuadTiangle.6 addrspace(1)*, i32, i32 addrspace(3)*)* @Intersect, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 64, i32 1, i32 1}
!2 = metadata !{metadata !"clang version 3.5.0 (trunk 212264) (llvm/trunk 212275)"}
!3 = metadata !{metadata !"clang version 3.5.0 (trunk 212142) (llvm/trunk 212143)"}
!4 = metadata !{metadata !5, metadata !5, i64 0}
!5 = metadata !{metadata !"omnipotent char", metadata !6, i64 0}
!6 = metadata !{metadata !"Simple C/C++ TBAA"}
!7 = metadata !{float 2.500000e+00}
!8 = metadata !{metadata !9, metadata !9, i64 0}
!9 = metadata !{metadata !"int", metadata !5, i64 0}
!10 = metadata !{metadata !11, metadata !5, i64 96}
!11 = metadata !{metadata !"", metadata !5, i64 0, metadata !5, i64 96}
!12 = metadata !{metadata !13, metadata !5, i64 0}
!13 = metadata !{metadata !"", metadata !5, i64 0, metadata !5, i64 16, metadata !5, i64 32, metadata !5, i64 48, metadata !5, i64 64, metadata !5, i64 80, metadata !5, i64 96, metadata !5, i64 112, metadata !5, i64 128, metadata !5, i64 144, metadata !5, i64 160}
!14 = metadata !{metadata !13, metadata !5, i64 16}
!15 = metadata !{metadata !13, metadata !5, i64 32}
!16 = metadata !{metadata !13, metadata !5, i64 48}
!17 = metadata !{metadata !13, metadata !5, i64 64}
!18 = metadata !{metadata !13, metadata !5, i64 80}
!19 = metadata !{metadata !13, metadata !5, i64 96}
!20 = metadata !{metadata !13, metadata !5, i64 112}
!21 = metadata !{metadata !13, metadata !5, i64 128}
!22 = metadata !{metadata !13, metadata !5, i64 144}
!23 = metadata !{metadata !13, metadata !5, i64 160}
!24 = metadata !{metadata !25, metadata !26, i64 0}
!25 = metadata !{metadata !"", metadata !26, i64 0, metadata !26, i64 4, metadata !26, i64 8, metadata !9, i64 12, metadata !9, i64 16}
!26 = metadata !{metadata !"float", metadata !5, i64 0}
!27 = metadata !{metadata !25, metadata !26, i64 4}
!28 = metadata !{metadata !25, metadata !26, i64 8}
!29 = metadata !{metadata !25, metadata !9, i64 12}
!30 = metadata !{metadata !25, metadata !9, i64 16}

Shader Disassembly:

	ALU_PUSH_BEFORE 3, @0x5c, KC0[CB0:0-32], KC1[]                                        ; 8000005C A40C0000
	JUMP @51 POP:1                                                                        ; 00000033 82800001
	ALU 3, @0x60, KC0[CB0:0-32], KC1[]                                                    ; 80000060 A00C0000
	TEX 1 @52                                                                             ; 00000034 80400400
	ALU 0x43, @0x64, KC0[CB0:0-32], KC1[]                                                 ; 80000064 A10C0000
	LOOP_START_DX10 @44                                                                   ; 0000002C 81800000
	ALU 0, @0xa8, KC0[], KC1[]                                                            ; 000000A8 A0000000
	LOOP_START_DX10 @39                                                                   ; 00000027 81800000
	ALU_PUSH_BEFORE 13, @0xa9, KC0[], KC1[]                                               ; 000000A9 A4340000
	JUMP @27 POP:1                                                                        ; 0000001B 82800001
	ALU_PUSH_BEFORE 17, @0xb7, KC0[], KC1[]                                               ; 000000B7 A4440000
	JUMP @26 POP:1                                                                        ; 0000001A 82800001
	ALU 14, @0xc9, KC0[], KC1[]                                                           ; 000000C9 A0380000
	LOOP_START_DX10 @25                                                                   ; 00000019 81800000
	ALU 7, @0xd8, KC0[], KC1[]                                                            ; 000000D8 A01C0000
	TEX 8 @56                                                                             ; 00000038 80402000
	ALU 0x61, @0xe0, KC0[], KC1[]                                                         ; 000000E0 A1840000
	TEX 1 @0x4a                                                                           ; 0000004A 80400400
	ALU 0x71, @0x142, KC0[], KC1[]                                                        ; 00000142 A1C40000
	PUSH @20 POP:1                                                                        ; 00000014 82C00001
	ALU 56, @0x1b4, KC0[], KC1[]                                                          ; 000001B4 A0E00000
	JUMP @24 POP:1                                                                        ; 00000018 82800001
	LOOP_BREAK @24                                                                        ; 00000018 82400000
	POP @24 POP:1                                                                         ; 00000018 83800001
	END_LOOP @14                                                                          ; 0000000E 81400000
	POP @26 POP:1                                                                         ; 0000001A 83800001
	ALU_POP_AFTER 3, @0x1ed, KC0[], KC1[]                                                 ; 000001ED A80C0000
	ALU_PUSH_BEFORE 6, @0x1f1, KC0[], KC1[]                                               ; 000001F1 A4180000
	JUMP @34 POP:1                                                                        ; 00000022 82800001
	ALU 12, @0x1f8, KC0[], KC1[]                                                          ; 000001F8 A0300000
	TEX 4 @0x4e                                                                           ; 0000004E 80401000
	ALU 26, @0x205, KC0[], KC1[]                                                          ; 00000205 A0680000
	TEX 1 @0x58                                                                           ; 00000058 80400400
	ALU_POP_AFTER 0x71, @0x220, KC0[], KC1[]                                              ; 00000220 A9C40000
	ALU_PUSH_BEFORE 1, @0x292, KC0[], KC1[]                                               ; 00000292 A4040000
	JUMP @38 POP:1                                                                        ; 00000026 82800001
	LOOP_BREAK @38                                                                        ; 00000026 82400000
	POP @38 POP:1                                                                         ; 00000026 83800001
	END_LOOP @8                                                                           ; 00000008 81400000
	ALU_PUSH_BEFORE 11, @0x294, KC0[], KC1[]                                              ; 00000294 A42C0000
	JUMP @43 POP:1                                                                        ; 0000002B 82800001
	LOOP_BREAK @43                                                                        ; 0000002B 82400000
	POP @43 POP:1                                                                         ; 0000002B 83800001
	END_LOOP @6                                                                           ; 00000006 81400000
	ALU 16, @0x2a0, KC0[], KC1[]                                                          ; 000002A0 A0400000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T4.X, 0                                            ; 0206A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T3.X, 0                                            ; 0187A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T2.X, 0                                            ; 01082020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T1.X, 0                                            ; 00892020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T21.X, T0.X, 0                                            ; 000AA020 95C01000
	POP @51 POP:1                                                                         ; 00000033 83800001
	CF_END                                                                                ; 00000000 80200000
	Fetch clause starting at 52:                                                          ; 
	VTX_READ_128 T20.XYZW, T1.X, 16                                                       ; 40010140 188D1014 00080010 00000000
	VTX_READ_128 T1.XYZW, T1.X, 0                                                         ; 40010140 188D1001 00080000 00000000
	Fetch clause starting at 56:                                                          ; 
	VTX_READ_128 T33.XYZW, T13.X, 48                                                      ; 400D0140 188D1021 00080030 00000000
	VTX_READ_128 T28.XYZW, T13.X, 16                                                      ; 400D0140 188D101C 00080010 00000000
	VTX_READ_128 T29.XYZW, T13.X, 32                                                      ; 400D0140 188D101D 00080020 00000000
	VTX_READ_128 T30.XYZW, T22.X, 0                                                       ; 40160140 188D101E 00080000 00000000
	VTX_READ_128 T31.XYZW, T21.X, 0                                                       ; 40150140 188D101F 00080000 00000000
	VTX_READ_128 T32.XYZW, T18.X, 0                                                       ; 40120140 188D1020 00080000 00000000
	VTX_READ_128 T34.XYZW, T16.X, 0                                                       ; 40100140 188D1022 00080000 00000000
	VTX_READ_128 T35.XYZW, T13.X, 0                                                       ; 400D0140 188D1023 00080000 00000000
	VTX_READ_128 T36.XYZW, T15.X, 0                                                       ; 400F0140 188D1024 00080000 00000000
	Fetch clause starting at 0x4a:                                                        ; 
	VTX_READ_128 T28.XYZW, T13.X, 0x50                                                    ; 400D0140 188D101C 00080050 00000000
	VTX_READ_128 T32.XYZW, T13.X, 64                                                      ; 400D0140 188D1020 00080040 00000000
	Fetch clause starting at 0x4e:                                                        ; 
	VTX_READ_128 T25.XYZW, T21.X, 32                                                      ; 40150140 188D1019 00080020 00000000
	VTX_READ_128 T26.XYZW, T18.X, 16                                                      ; 40120140 188D101A 00080010 00000000
	VTX_READ_128 T28.XYZW, T16.X, 16                                                      ; 40100140 188D101C 00080010 00000000
	VTX_READ_128 T29.XYZW, T15.X, 0                                                       ; 400F0140 188D101D 00080000 00000000
	VTX_READ_128 T30.XYZW, T13.X, 0                                                       ; 400D0140 188D101E 00080000 00000000
	Fetch clause starting at 0x58:                                                        ; 
	VTX_READ_128 T33.XYZW, T12.X, 0x60                                                    ; 400C0140 188D1021 00080060 00000000
	VTX_READ_128 T34.XYZW, T16.X, 32                                                      ; 40100140 188D1022 00080020 00000000
	ALU clause starting at 0x5c:                                                          ; 
	  MULLO_INT             * T0.Y, KC0[1].Z, T1.X,                                       ; 80002881 20004790
	  ADD_INT               * T0.W, T0.X, PS,                                             ; 801FE000 60001A10
	  SETGE_UINT            * T1.W, PV.W, KC0[3].Y,                                       ; 80906CFE 60201F90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002104
	ALU clause starting at 0x60:                                                          ; 
	  MOV                     T1.W, KC0[2].Y,                                             ; 00000482 60200C90
	  MULLO_INT             * T0.Y, T0.W, literal.x,                                      ; 801FAC00 20004790
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  ADD_INT               * T1.X, PV.W, PS,                                             ; 801FECFE 00201A10
	ALU clause starting at 0x64:                                                          ; 
	  MOV                     T2.X, T1.X,                                                 ; 00000001 00400C90
	  MOV                   * T3.X, T1.Z,                                                 ; 80000801 00600C90
	  MOV                   * T2.Y, T1.X,                                                 ; 80000001 20400C90
	  MOV                     T4.X, T1.Y,                                                 ; 00000401 00800C90
	  MOV                     T3.Y, T1.Z,                                                 ; 00000801 20600C90
	  MOV                     T2.Z, T1.X,                                                 ; 00000001 40400C90
	  MOV                   * T4.Y, T1.Y,                                                 ; 80000401 20800C90
	  MOV                     T3.Z, T1.Z,                                                 ; 00000801 40600C90
	  MOV                   * T4.Z, T1.Y,                                                 ; 80000401 40800C90
	  MOV                     T3.W, T1.Z,                                                 ; 00000801 60600C90
	  MOV                   * T4.W, T1.Y,                                                 ; 80000401 60800C90
	  MOV                   * T2.W, T1.X,                                                 ; 80000001 60400C90
	  MOV                     T1.X, T1.W,                                                 ; 00000C01 00200C90
	  MOV                   * T5.X, T20.X,                                                ; 80000014 00A00C90
	  MOV                     T1.Y, T1.W,                                                 ; 00000C01 20200C90
	  MOV                     T7.W, KC0[3].X,                                             ; 00000083 60E00C90
	  MOV                   * T12.W, literal.x,                                           ; 800000FD 61800C90
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  MOV                     T6.X, T20.Z,                                                ; 00000814 00C00C90
	  MOV                     T5.Y, T20.X,                                                ; 00000014 20A00C90
	  MOV                     T1.Z, T1.W,                                                 ; 00000C01 40200C90
	  MOV                   * T0.Y, PS,                                                   ; 800000FF 20000C90
	  ADD_INT               * T7.W, T7.W, literal.x,                                      ; 801FAC07 60E01A10
	80(1.121039e-43), 0(0.000000e+00)                                                     ; 00000050 00000000
	  LSHR                    T7.X, T20.Y, literal.x,                                     ; 001FA414 00E00B10
	  MOV                     T6.Y, T20.Z,                                                ; 00000814 20C00C90
	  MOV                     T5.Z, T20.X,                                                ; 00000014 40A00C90
	  LSHL                    T8.W, T0.X, literal.y,  BS:VEC_120/SCL_212                  ; 009FA000 61080B90
	  RECIP_IEEE            * T9.X, T1.W,                                                 ; 80000C01 01204310
	31(4.344025e-44), 5(7.006492e-45)                                                     ; 0000001F 00000005
	  OR_INT                  T8.X, PV.W, 1,                                              ; 001F4CFE 01001890
	  MOV                     T9.Y, PS,                                                   ; 000000FF 21200C90
	  MOV                     T6.Z, T20.Z,                                                ; 00000814 40C00C90
	  XOR_INT                 T10.W, PV.X, 1,                                             ; 001F40FE 61401910
	  RECIP_IEEE            * T11.X, T20.Y,                                               ; 80000414 01604310
	  LSHR                    T10.X, T1.W, literal.x,                                     ; 001FAC01 01400B10
	  MOV                     T11.Y, PS,                                                  ; 000000FF 21600C90
	  MOV                     T9.Z, T9.X,                                                 ; 00000009 41200C90
	  LSHR                    T13.W, T20.X, literal.x,  BS:VEC_120/SCL_212                ; 001FA014 61A80B10
	  RECIP_IEEE            * T14.X, T20.X,                                               ; 80000014 01C04310
	31(4.344025e-44), 0(0.000000e+00)                                                     ; 0000001F 00000000
	  MOV                     T19.X, T20.W,                                               ; 00000C14 02600C90
	  MOV                     T14.Y, PS,                                                  ; 000000FF 21C00C90
	  MOV                     T11.Z, T11.X,                                               ; 0000000B 41600C90
	  XOR_INT                 T15.W, PV.W, 1,                                             ; 001F4CFE 61E01910
	  XOR_INT               * T16.W, PV.X, 1,                                             ; 801F40FE 62001910
	  MOV                     T17.X, T20.Y,                                               ; 00000414 02200C90
	  MOV                     T19.Y, T20.W,                                               ; 00000C14 22600C90
	  MOV                     T14.Z, T14.X,                                               ; 0000000E 41C00C90
	  MOV                     T18.W, KC0[3].Z,                                            ; 00000883 62400C90
	  MOV                   * T11.W, T11.X,                                               ; 8000000B 61600C90
	  LSHL                    T0.X, T0.X, literal.x,                                      ; 001FA000 00000B90
	  MOV                     T17.Y, T20.Y,                                               ; 00000414 22200C90
	  MOV                     T19.Z, T20.W,                                               ; 00000C14 42600C90
	  MOV                     T14.W, T14.X,  BS:VEC_120/SCL_212                           ; 0000000E 61C80C90
	  MOV                   * T9.W, T9.X,                                                 ; 80000009 61200C90
	7(9.809089e-45), 0(0.000000e+00)                                                      ; 00000007 00000000
	  ADD_INT                 T0.X, T18.W, PV.X,                                          ; 001FCC12 00001A10
	  MOV                     T13.Y, literal.x,                                           ; 000000FD 21A00C90
	  MOV                     T17.Z, T20.Y,                                               ; 00000414 42200C90
	  MOV                     T19.W, T20.W,  BS:VEC_120/SCL_212                           ; 00000C14 62680C90
	  MOV                   * T6.W, T20.Z,                                                ; 80000814 60C00C90
	0(0.000000e+00), 0(0.000000e+00)                                                      ; 00000000 00000000
	  LDS_WRITE             * T0.X, T13.Y,                                                ; 8081A000 01A22000
	  MOV                     T7.Y, KC0[2].Z,                                             ; 00000882 20E00C90
	  MOV                     T0.Z, KC0[2].W,                                             ; 00000C82 40000C90
	  MOV                     T17.W, T20.Y,                                               ; 00000414 62200C90
	  MOV                   * T5.W, T20.X,                                                ; 80000014 60A00C90
	ALU clause starting at 0xa8:                                                          ; 
	  MOV                   * T25.W, T13.Y,                                               ; 8000040D 63200C90
	ALU clause starting at 0xa9:                                                          ; 
	  ADD_INT               * T24.W, T25.W, T8.W,                                         ; 81810C19 63001A10
	  LSHL                  * T23.W, PV.W, literal.x,                                     ; 801FACFE 62E00B90
	2(2.802597e-45), 0(0.000000e+00)                                                      ; 00000002 00000000
	  ADD_INT               * T23.W, T18.W, PV.W,                                         ; 819FCC12 62E01A10
	  LDS_READ_RET          * OQAP, T23.W                                                 ; 80000C17 06422000
	  MOV                     T12.X, OQAP,                                                ; 000000DD 01800C90
	  MOV                   * T26.W, literal.x,                                           ; 800000FD 63400C90
	1(1.401298e-45), 0(0.000000e+00)                                                      ; 00000001 00000000
	  ADD_INT                 T12.Y, T25.W, literal.x,                                    ; 001FAC19 21801A10
	  SETGT_INT               T12.Z, 0.0, PV.X,                                           ; 001FC0F8 41801D90
	  MOV                     T28.W, PV.W,                                                ; 00000CFE 63800C90
	  MOV                   * T27.W, PV.W,                                                ; 80000CFE 63600C90
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.Z, 0.0,                  ; 801F08FE 00002284
	ALU clause starting at 0xb7:                                                          ; 
	  LSHR                  * T20.W, T12.X, literal.x,                                    ; 801FA00C 62800B10
	27(3.783506e-44), 0(0.000000e+00)                                                     ; 0000001B 00000000
	  AND_INT                 T27.W, PV.W, literal.x,                                     ; 001FACFE 63601810
	  AND_INT               * T28.W, T12.X, literal.y,                                    ; 809FA00C 63801810
	15(2.101948e-44), 134217727(3.851860e-34)                                             ; 0000000F 07FFFFFF
	  MOV                     T8.Z, T8.Y,                                                 ; 00000408 41000C90
	  ADD_INT                 T20.W, PS, PV.W,                                            ; 019FC0FF 62801A10
	  MOV                   * T10.Z, T7.Z,                                                ; 80000807 41400C90
	  MOV                   * T21.W, T0.X,                                                ; 80000000 62A00C90
	  MOV                     T10.Y, T12.W,                                               ; 00000C0C 21400C90
	  MOV                     T22.W, T0.Y,                                                ; 00000400 62C00C90
	  ADD_INT               * T20.W, T20.W, 1,                                            ; 801F4C14 62801A10
	  SETGE_UINT            * T29.W, T28.W, PS,                                           ; 801FEC1C 63A01F90
	  MOV                     T20.X, T19.X,                                               ; 00000013 02800C90
	  MOV                     T20.Y, T19.Y,                                               ; 00000413 22800C90
	  MOV                     T20.Z, T19.Z,                                               ; 00000813 42800C90
	  MOV                     T20.W, T19.W,                                               ; 00000C13 62800C90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002104
	ALU clause starting at 0xc9:                                                          ; 
	  MULLO_INT             * T8.Z, T28.W, literal.x,                                     ; 801FAC1C 41004790
	11(1.541428e-44), 0(0.000000e+00)                                                     ; 0000000B 00000000
	  MOV                     T22.W, T0.Y,                                                ; 00000400 62C00C90
	  LSHL                  * T20.W, PS, literal.x,                                       ; 801FA0FF 62800B90
	4(5.605194e-45), 0(0.000000e+00)                                                      ; 00000004 00000000
	  ADD_INT                 T13.X, T7.W, PS,                                            ; 001FEC07 01A01A10
	  MOV                     T10.Y, T12.W,  BS:VEC_120/SCL_212                           ; 00000C0C 21480C90
	  MOV                   * T21.W, T0.X,                                                ; 80000000 62A00C90
	  MOV                     T10.Z, T7.Z,                                                ; 00000807 41400C90
	  MOV                   * T8.Z, T8.Y,                                                 ; 80000408 41000C90
	  ADD_INT               * T27.W, T27.W, 1,                                            ; 801F4C1B 63601A10
	  MOV                     T20.X, T19.X,                                               ; 00000013 02800C90
	  MOV                     T20.Y, T19.Y,                                               ; 00000413 22800C90
	  MOV                     T20.Z, T19.Z,                                               ; 00000813 42800C90
	  MOV                   * T20.W, T19.W,                                               ; 80000C13 62800C90
	ALU clause starting at 0xd8:                                                          ; 
	  ADD_INT                 T15.X, T13.X, literal.x,                                    ; 001FA00D 01E01A10
	  ADD_INT               * T16.X, T13.X, literal.y,                                    ; 809FA00D 02001A10
	-80(-nan), -48(-nan)                                                                  ; FFFFFFB0 FFFFFFD0
	  ADD_INT                 T18.X, T13.X, literal.x,                                    ; 001FA00D 02401A10
	  ADD_INT               * T21.X, T13.X, literal.y,                                    ; 809FA00D 02A01A10
	-16(-nan), -64(-nan)                                                                  ; FFFFFFF0 FFFFFFC0
	  ADD_INT               * T22.X, T13.X, literal.x,                                    ; 801FA00D 02C01A10
	-32(-nan), 0(0.000000e+00)                                                            ; FFFFFFE0 00000000
	ALU clause starting at 0xe0:                                                          ; 
	  ADD                   * T37.W, T2.X, -T36.X,                                        ; 82048002 64A00010
	  MUL_IEEE                T38.W, PV.W, T35.X,  BS:VEC_102/SCL_221                     ; 00046CFE 64CC0110
	  ADD                   * T39.W, T3.X, -T34.X,                                        ; 82044003 64E00010
	  MUL_IEEE                T12.Z, PS, T32.X,                                           ; 000400FF 41800110
	  ADD                   * T40.W, T4.X, -T31.X,  BS:VEC_021/SCL_122                    ; 8203E004 65040010
	  MULADD_IEEE           * T38.W, T39.W, T30.X, -T38.W,                                ; 8003CC27 64C31C26
	  MUL_IEEE                T13.Z, T5.X, PV.W,                                          ; 019FC005 41A00110
	  MUL_IEEE                T38.W, T29.X, PV.W,  BS:VEC_201                             ; 019FC01D 64D00110
	  MULADD_IEEE           * T41.W, T40.W, T35.X, -T12.Z,                                ; 80046C28 6523180C
	  MULADD_IEEE             T13.Y, T28.X, PS, PV.W,                                     ; 001FE01C 21A30CFE
	  MULADD_IEEE             T12.Z, T1.X, PS, PV.Z, BS:VEC_201                           ; 001FE001 419308FE
	  ADD                     T38.W, T3.W, -T34.W,                                        ; 03844C03 64C00010
	  MUL_IEEE              * T41.W, T40.W, T30.X,                                        ; 8003CC28 65200110
	  MULADD_IEEE             T15.X, T37.W, T32.X, -PS,                                   ; 00040C25 01E310FF
	  MUL_IEEE              * T15.Y, PV.W, T32.W,                                         ; 81840CFE 21E00110
	  ADD                     T13.Z, T4.W, -T31.W,                                        ; 0383EC04 41A00010
	  ADD                     T41.W, T2.Z, -T36.Z,                                        ; 03048802 65200010
	  ADD                   * T42.W, T3.Y, -T34.Y,                                        ; 82844403 65400010
	  MUL_IEEE                T16.X, PS, T32.Y,                                           ; 008400FF 02000110
	  ADD                   * T16.Y, T4.Y, -T31.Y,  BS:VEC_021/SCL_122                    ; 8283E404 22040010
	  ADD                     T15.Z, T2.Y, -T36.Y,                                        ; 02848402 41E00010
	  MUL_IEEE                T43.W, T41.W, T35.Z,  BS:VEC_102/SCL_221                    ; 01046C29 656C0110
	  ADD                   * T34.W, T3.Z, -T34.Z,                                        ; 83044803 64400010
	  ADD                     T18.X, T2.W, -T36.W,                                        ; 03848C02 02400010
	  MUL_IEEE                T18.Y, PS, T32.Z,                                           ; 010400FF 22400110
	  MULADD_IEEE           * T16.Z, PS, T30.Z, -PV.W, BS:VEC_021/SCL_122                 ; 8103C0FF 42071CFE
	  ADD                     T31.W, T4.Z, -T31.Z,                                        ; 0303E804 63E00010
	  MUL_IEEE              * T36.W, T15.Z, T35.Y,                                        ; 8084680F 64800110
	  MULADD_IEEE             T21.X, T42.W, T30.Y, -PS,                                   ; 0083CC2A 02A310FF
	  MUL_IEEE                T21.Y, PV.W, T30.Z,                                         ; 0103CCFE 22A00110
	  MUL_IEEE              * T18.Z, T29.Z, T16.Z,  BS:VEC_021/SCL_122                    ; 8102081D 42440110
	  MULADD_IEEE             T36.W, T31.W, T35.Z, -T18.Y,                                ; 01046C1F 64831412
	  MUL_IEEE              * T43.W, T18.X, T35.W,                                        ; 81846012 65600110
	  MULADD_IEEE             T22.X, T38.W, T30.W, -PS,                                   ; 0183CC26 02C310FF
	  MULADD_IEEE             T18.Y, T28.Z, PV.W, T18.Z,                                  ; 019FC81C 22430812
	  MULADD_IEEE             T18.Z, T41.W, T32.Z, -T21.Y, BS:VEC_210                     ; 01040C29 42571415
	  MUL_IEEE              * T43.W, T29.Y, T21.X,  BS:VEC_120/SCL_212                    ; 8002A41D 65680110
	  MULADD_IEEE           * T44.W, T16.Y, T35.Y, -T16.X,                                ; 80846410 65831010
	  MULADD_IEEE             T16.X, T28.Y, PV.W, T43.W, BS:VEC_120/SCL_212               ; 019FC41C 020B0C2B
	  MULADD_IEEE             T18.Y, T33.Z, T18.Z, T18.Y,                                 ; 01024821 22430412
	  MUL_IEEE                T21.Z, T1.X, T33.X,  BS:VEC_021/SCL_122                     ; 00042001 42A40110
	  MUL_IEEE                T43.W, T29.W, T22.X,  BS:VEC_210                            ; 0002CC1D 65740110
	  MULADD_IEEE           * T45.W, T13.Z, T35.W, -T15.Y,                                ; 8184680D 65A3140F
	  MUL_IEEE                T23.X, T1.Y, T33.Y,                                         ; 00842401 02E00110
	  MULADD_IEEE           * T15.Y, T28.W, PS, PV.W,                                     ; 801FEC1C 21E30CFE
	  MUL_IEEE                T22.Z, T16.Y, T30.Y,                                        ; 0083C410 42C00110
	  MUL_IEEE                T43.W, T17.X, T29.X,  BS:VEC_201                            ; 0003A011 65700110
	  MULADD_IEEE           * T46.W, T17.X, T28.X, -T21.Z,                                ; 80038011 65C31815
	  MUL_IEEE                T21.X, T5.Y, T21.X,                                         ; 0002A405 02A00110
	  MUL_IEEE              * T21.Y, T5.X, T28.X,  BS:VEC_021/SCL_122                     ; 80038005 22A40110
	  MUL_IEEE                T21.Z, T32.X, T46.W,  BS:VEC_021/SCL_122                    ; 0185C020 42A40110
	  MULADD_IEEE             T43.W, T5.X, T33.X, -T43.W, BS:VEC_120/SCL_212              ; 00042005 656B1C2B
	  MUL_IEEE              * T47.W, T13.Z, T30.W,                                        ; 8183C80D 65E00110
	  MULADD_IEEE             T24.X, T18.X, T32.W, -PS,                                   ; 01840012 030310FF
	  MULADD_IEEE           * T22.Y, PV.W, T30.X, PV.Z,                                   ; 8003CCFE 22C308FE
	  MULADD_IEEE             T21.Z, T1.X, T29.X, -T21.Y,                                 ; 0003A001 42A31415
	  MULADD_IEEE             T44.W, T1.Y, T44.W, T21.X,                                  ; 01858401 65830015
	  MULADD_IEEE           * T47.W, T15.Z, T32.Y, -T22.Z,                                ; 8084080F 65E31816
	  MULADD_IEEE             T21.X, T17.Y, PS, PV.W,                                     ; 001FE411 02A30CFE
	  MULADD_IEEE             T21.Y, PV.Z, T35.X, T22.Y,                                  ; 000468FE 22A30416
	  MULADD_IEEE           * T22.Z, T33.W, T24.X, T15.Y, BS:VEC_021/SCL_122              ; 80030C21 42C7040F
	  MUL_IEEE                T44.W, T17.Y, T29.Y,  BS:VEC_201                            ; 0083A411 65900110
	  MULADD_IEEE           * T48.W, T17.Y, T28.Y, -T23.X,                                ; 80838411 66031017
	  MUL_IEEE                T23.X, T5.Z, T16.Z,                                         ; 01020805 02E00110
	  MUL_IEEE                T15.Y, T5.Y, T28.Y,                                         ; 00838405 21E00110
	  MUL_IEEE              * T16.Z, T32.Y, PS,  BS:VEC_201                               ; 801FE420 42100110
	  MULADD_IEEE             T44.W, T5.Y, T33.Y, -T44.W, BS:VEC_021/SCL_122              ; 00842405 65871C2C
	  MUL_IEEE              * T49.W, T5.W, T22.X,                                         ; 8002CC05 66200110
	  MUL_IEEE                T22.X, T1.Z, T33.Z,                                         ; 01042801 02C00110
	  MULADD_IEEE             T22.Y, T1.W, T45.W, PS,                                     ; 0185AC01 22C300FF
	  MULADD_IEEE           * T16.Z, PV.W, T30.Y, T16.Z,                                  ; 8083CCFE 42030810
	  MULADD_IEEE             T45.W, T1.Y, T29.Y, -T15.Y,                                 ; 0083A401 65A3140F
	  MULADD_IEEE           * T36.W, T1.Z, T36.W, T23.X,                                  ; 81848801 64830017
	  MULADD_IEEE             T23.X, T17.Z, T18.Z, PS,                                    ; 01024811 02E300FF
	  MULADD_IEEE             T15.Y, PV.W, T35.Y, T16.Z,                                  ; 00846CFE 21E30810
	  MULADD_IEEE             T16.Z, T17.W, T24.X, T22.Y,                                 ; 00030C11 42030416
	  MUL_IEEE              * T36.W, T1.W, T33.W,  BS:VEC_120/SCL_212                     ; 81842C01 64880110
	  MULADD_IEEE           * T49.W, T17.Z, T28.Z, -T22.X,                                ; 81038811 66231016
	  MUL_IEEE                T22.X, T5.Z, T28.Z,                                         ; 01038805 02C00110
	  MUL_IEEE                T22.Y, T32.Z, PV.W,  BS:VEC_201                             ; 019FC820 22D00110
	  MUL_IEEE              * T18.Z, T17.W, T29.W,                                        ; 8183AC11 42400110
	  MULADD_IEEE             T36.W, T17.W, T28.W, -T36.W,                                ; 01838C11 64831C24
	  MUL_IEEE              * T50.W, T17.Z, T29.Z,                                        ; 8103A811 66400110
	  MULADD_IEEE             T24.X, T5.Z, T33.Z, -PS,                                    ; 01042805 030310FF
	  MUL_IEEE                T23.Y, T5.W, T28.W,                                         ; 01838C05 22E00110
	  MUL_IEEE                T13.Z, T13.Z, PV.W,  BS:VEC_201                             ; 019FC80D 41B00110
	  MUL_IEEE              * T28.W, T32.W, PV.W,  BS:VEC_201                             ; 819FCC20 63900110
	  MULADD_IEEE           * T32.W, T5.W, T33.W, -T18.Z,                                 ; 81842C05 64031812
	  MULADD_IEEE             T25.X, PV.W, T30.W, T28.W,                                  ; 0183CCFE 03230C1C
	  MULADD_IEEE           * T24.Y, T18.X, PV.W, T13.Z,                                  ; 819FC012 2303080D
	  MULADD_IEEE             T13.Z, T1.W, T29.W, -T23.Y,                                 ; 0183AC01 41A31417
	  MULADD_IEEE             T28.W, T24.X, T30.Z, T22.Y, BS:VEC_201                      ; 0103C018 63930416
	  MULADD_IEEE           * T29.W, T1.Z, T29.Z, -T22.X,                                 ; 8103A801 63A31016
	  MULADD_IEEE             T18.X, PS, T35.Z, PV.W,                                     ; 010460FF 02430CFE
	  MULADD_IEEE             T22.Y, T38.W, PV.Z, T24.Y,                                  ; 011FCC26 22C30418
	  MUL_IEEE                T18.Z, T16.Y, T48.W,                                        ; 01860410 42400110
	  MULADD_IEEE           * T35.W, PV.Z, T35.W, T25.X, BS:VEC_021/SCL_122               ; 818468FE 64670019
	  MUL_IEEE              * T30.W, T31.W, T49.W,                                        ; 81862C1F 63C00110
	ALU clause starting at 0x142:                                                         ; 
	  MULADD_IEEE             T30.W, T41.W, T24.X, T30.W, BS:VEC_021/SCL_122              ; 00030C29 63C70C1E
	  RECIP_IEEE            * T13.Z, T35.W,                                               ; 80000C23 41A04310
	  MULADD_IEEE           * T22.X, T34.W, T29.W, PV.W,                                  ; 8183AC22 02C30CFE
	  MUL_IEEE                T16.Y, T40.W, T46.W,                                        ; 0185CC28 22000110
	  MULADD_IEEE             T15.Z, T15.Z, T44.W, T18.Z, BS:VEC_021/SCL_122              ; 0185880F 41E70812
	  MUL_IEEE                T29.W, T22.Y, T13.Z,  BS:VEC_021/SCL_122                    ; 0101A416 63A40110
	  RECIP_IEEE            * T18.Z, T18.X,                                               ; 80000012 42404310
	  MULADD_IEEE           * T24.X, T42.W, T45.W, PV.Z,                                  ; 8185AC2A 030308FE
	  MULADD_IEEE             T16.Y, T37.W, T43.W, T16.Y, BS:VEC_021/SCL_122              ; 01856C25 22070410
	  MUL_IEEE                T29.Z, T22.X, T18.Z,                                        ; 01024016 43A00110
	  MUL_IEEE                T30.W, T16.Z, T13.Z,  BS:VEC_021/SCL_122                    ; 0101A810 63C40110
	  RECIP_IEEE            * T15.Z, T15.Y,                                               ; 8000040F 41E04310
	  MULADD_IEEE             T22.X, T39.W, T21.Z, PV.Y,                                  ; 0102AC27 02C304FE
	  MUL_IEEE                T29.Y, T24.X, PS,                                           ; 001FE018 23A00110
	  MUL_IEEE              * T30.Z, T23.X, T18.Z,  BS:VEC_120/SCL_212                    ; 81024017 43C80110
	  MUL_IEEE                T31.W, T22.Z, T13.Z,                                        ; 0101A816 63E00110
	  RECIP_IEEE            * T13.Z, T21.Y,                                               ; 80000415 41A04310
	  MUL_IEEE                T29.X, T22.X, PS,                                           ; 001FE016 03A00110
	  MUL_IEEE                T30.Y, T21.X, T15.Z,  BS:VEC_120/SCL_212                    ; 0101E015 23C80110
	  MUL_IEEE                T31.Z, T18.Y, T18.Z,                                        ; 01024412 43E00110
	  MULADD_IEEE           * T34.W, T33.Y, T47.W, T16.X, BS:VEC_102/SCL_221              ; 8185E421 644F0010
	  MULADD_IEEE           * T36.W, T17.X, T15.X, T12.Z,                                 ; 8001E011 6483080C
	  MUL_IEEE                T30.X, PV.W, T13.Z,                                         ; 0101ACFE 03C00110
	  MUL_IEEE                T31.Y, T34.W, T15.Z,  BS:VEC_021/SCL_122                    ; 0101EC22 23E40110
	  ADD                     T34.W, -T29.Y, 1.0,  BS:VEC_120/SCL_212                     ; 001F341D 64480010
	  MULADD_IEEE           * T33.W, T33.X, T15.X, T13.Y,                                 ; 8001E021 6423040D
	  MUL_IEEE                T31.X, PS, T13.Z,                                           ; 0101A0FF 03E00110
	  ADD                   * T33.W, PV.W, -T30.Y,                                        ; 8283CCFE 64200010
	  SETGE_DX10              T13.Y, PV.W, 0.0,                                           ; 001F0CFE 21A00710
	  SETNE_DX10              T12.Z, T15.Y, 0.0,                                          ; 001F040F 41800790
	  SETGE_DX10              T33.W, T29.Y, 0.0,  BS:VEC_120/SCL_212                      ; 001F041D 64280710
	  SETGT_DX10            * T34.W, PV.X, T6.X,                                          ; 8000C0FE 64400690
	  AND_INT                 T15.Y, PS, 1,                                               ; 001F40FF 21E01810
	  AND_INT                 T13.Z, PV.W, 1,                                             ; 001F4CFE 41A01810
	  AND_INT                 T33.W, PV.Z, 1,                                             ; 001F48FE 64201810
	  AND_INT               * T34.W, PV.Y, 1,                                             ; 801F44FE 64401810
	  SETNE_INT               T15.X, PS, 0.0,                                             ; 001F00FF 01E01E90
	  SETNE_INT               T13.Y, PV.W, 0.0,                                           ; 001F0CFE 21A01E90
	  SETGE_DX10              T12.Z, T30.Y, 0.0,                                          ; 001F041E 41800710
	  ADD                     T33.W, -T29.Z, 1.0,                                         ; 001F381D 64200010
	  SETGT_DX10            * T34.W, T31.Y, T6.Y,                                         ; 8080C41F 64400690
	  AND_INT                 T16.X, PS, 1,                                               ; 001F40FF 02001810
	  ADD                     T16.Y, PV.W, -T30.Z,                                        ; 0303CCFE 22000010
	  AND_INT                 T12.Z, PV.Z, 1,                                             ; 001F48FE 41801810
	  CNDE_INT                T33.W, PV.X, 0.0, PV.Y,                                     ; 001F00FE 642384FE
	  SETNE_INT             * T34.W, T13.Z, 0.0,                                          ; 801F080D 64401E90
	  CNDE_INT                T15.X, PS, 0.0, PV.W,                                       ; 001F00FF 01E38CFE
	  SETNE_INT               T13.Y, PV.Z, 0.0,                                           ; 001F08FE 21A01E90
	  ADD                     T12.Z, -T29.W, 1.0,                                         ; 001F3C1D 41800010
	  SETGE_DX10              T33.W, PV.Y, 0.0,                                           ; 001F04FE 64200710
	  SETNE_DX10            * T34.W, T18.X, 0.0,                                          ; 801F0012 64400790
	  SETGT_DX10              T18.X, T31.W, T6.W,                                         ; 0180CC1F 02400690
	  AND_INT                 T16.Y, PS, 1,                                               ; 001F40FF 22001810
	  AND_INT                 T13.Z, PV.W, 1,                                             ; 001F4CFE 41A01810
	  ADD                     T33.W, PV.Z, -T30.W,  BS:VEC_021/SCL_122                    ; 0383C8FE 64240010
	  SETGE_DX10            * T34.W, T30.Z, 0.0,                                          ; 801F081E 64400710
	  AND_INT                 T21.X, PS, 1,                                               ; 001F40FF 02A01810
	  SETGE_DX10              T18.Y, PV.W, 0.0,                                           ; 001F0CFE 22400710
	  SETNE_DX10              T12.Z, T35.W, 0.0,                                          ; 001F0C23 41800790
	  SETNE_INT               T33.W, PV.Z, 0.0,                                           ; 001F08FE 64201E90
	  SETNE_INT             * T34.W, PV.Y, 0.0,                                           ; 801F04FE 64401E90
	  CNDE_INT                T22.X, PV.W, 0.0, PS,                                       ; 001F0CFE 02C380FF
	  SETGE_DX10              T16.Y, T29.Z, 0.0,                                          ; 001F081D 22000710
	  AND_INT                 T12.Z, PV.Z, 1,                                             ; 001F48FE 41801810
	  AND_INT                 T33.W, PV.Y, 1,                                             ; 001F44FE 64201810
	  SETGE_DX10            * T34.W, T29.W, 0.0,                                          ; 801F0C1D 64400710
	  AND_INT                 T23.X, PS, 1,                                               ; 001F40FF 02E01810
	  SETNE_INT               T18.Y, PV.W, 0.0,                                           ; 001F0CFE 22401E90
	  SETNE_INT               T12.Z, PV.Z, 0.0,                                           ; 001F08FE 41801E90
	  SETGE_DX10              T33.W, T30.W, 0.0,                                          ; 001F0C1E 64200710
	  AND_INT               * T34.W, PV.Y, 1,                                             ; 801F44FE 64401810
	  SETNE_INT               T24.X, PS, 0.0,                                             ; 001F00FF 03001E90
	  AND_INT                 T16.Y, PV.W, 1,                                             ; 001F4CFE 22001810
	  CNDE_INT                T12.Z, PV.Y, 0.0, PV.Z,                                     ; 001F04FE 418388FE
	  SETNE_INT               T33.W, PV.X, 0.0,                                           ; 001F00FE 64201E90
	  ADD                   * T34.W, -T29.X, 1.0,                                         ; 801F301D 64400010
	  ADD                     T23.X, PS, -T30.X,                                          ; 0203C0FF 02E00010
	  CNDE_INT                T18.Y, PV.W, 0.0, PV.Z,                                     ; 001F0CFE 224388FE
	  SETNE_INT               T12.Z, PV.Y, 0.0,                                           ; 001F04FE 41801E90
	  CNDE_INT                T33.W, PV.X, 0.0, T22.X, BS:VEC_120/SCL_212                 ; 001F00FE 642B8016
	  SETNE_INT             * T34.W, T21.X, 0.0,                                          ; 801F0015 64401E90
	  CNDE_INT                T21.X, PS, 0.0, PV.W,                                       ; 001F00FF 02A38CFE
	  CNDE_INT                T16.Y, PV.Z, 0.0, PV.Y,                                     ; 001F08FE 220384FE
	  SETGE_DX10              T12.Z, PV.X, 0.0,                                           ; 001F00FE 41800710
	  SETNE_DX10              T33.W, T21.Y, 0.0,                                          ; 001F0415 64200790
	  AND_INT               * T34.W, T18.X, 1,                                            ; 801F4012 64401810
	  SETNE_INT               T18.X, PS, 0.0,                                             ; 001F00FF 02401E90
	  SETGT_DX10              T18.Y, T31.Z, T6.Z,                                         ; 0100C81F 22400690
	  AND_INT                 T13.Z, PV.W, 1,                                             ; 001F4CFE 41A01810
	  AND_INT                 T33.W, PV.Z, 1,                                             ; 001F48FE 64201810
	  SETGE_DX10            * T34.W, T29.X, 0.0,                                          ; 801F001D 64400710
	  AND_INT                 T22.X, PS, 1,                                               ; 001F40FF 02C01810
	  SETNE_INT               T21.Y, PV.W, 0.0,                                           ; 001F0CFE 22A01E90
	  SETNE_INT               T12.Z, PV.Z, 0.0,                                           ; 001F08FE 41801E90
	  SETGE_DX10              T33.W, T30.X, 0.0,                                          ; 001F001E 64200710
	  AND_INT               * T34.W, PV.Y, 1,                                             ; 801F44FE 64401810
	  SETNE_INT               T23.X, PS, 0.0,                                             ; 001F00FF 02E01E90
	  AND_INT                 T18.Y, PV.W, 1,                                             ; 001F4CFE 22401810
	  CNDE_INT                T12.Z, PV.Y, 0.0, PV.Z,                                     ; 001F04FE 418388FE
	  SETNE_INT               T33.W, PV.X, 0.0,                                           ; 001F00FE 64201E90
	  CNDE_INT              * T35.W, T18.X, 0.0, T16.Y, BS:VEC_021/SCL_122                ; 801F0012 64678410
	  CNDE_INT                T18.X, PV.W, 0.0, PV.Z,                                     ; 001F0CFE 024388FE
	  SETNE_INT               T16.Y, PV.Y, 0.0,                                           ; 001F04FE 22001E90
	  CNDE_INT                T35.Z, PV.X, 0.0, T21.X, BS:VEC_021/SCL_122                 ; 001F00FE 44678015
	  CNDE_INT                T33.W, T13.Y, 0.0, T15.X, BS:VEC_120/SCL_212                ; 001F040D 642B800F
	  SETNE_INT             * T34.W, T16.X, 0.0,                                          ; 801F0010 64401E90
	  CNDE_INT                T35.Y, PS, 0.0, PV.W,                                       ; 001F00FF 24638CFE
	  CNDE_INT                T33.W, PV.Y, 0.0, PV.X,                                     ; 001F04FE 642380FE
	  SETNE_INT             * T34.W, T15.Y, 0.0,                                          ; 801F040F 64401E90
	  CNDE_INT                T35.X, PS, 0.0, PV.W,                                       ; 001F00FF 04638CFE
	  MOV                   * T37.W, literal.x,                                           ; 800000FD 64A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                      ; 00000000 00000000
	  MOV                     T12.Z, PV.W,                                                ; 00000CFE 41800C90
	  SETE_INT              * T33.W, PV.X, 0.0,                                           ; 801F00FE 64201D10
	ALU clause starting at 0x1b4:                                                         ; 
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), T33.W, 0.0,                     ; 801F0C21 00002288
	  SETGT_DX10            * T12.Z, T20.X, T31.X, Pred_sel_zero                          ; C003E014 41800690
	  AND_INT               * T33.W, T12.Z, 1,                                            ; 801F480C 64201810
	  MOV                     T13.Y, T37.W,                                               ; 00000C25 21A00C90
	  CNDE_INT                T13.Z, PV.W, literal.x, T32.X,                              ; 001FACFE 41A38020
	  CNDE_INT                T36.W, PV.W, T20.X, T31.X, BS:VEC_201                       ; 00028CFE 6493801F
	  SETE_INT              * T34.W, T35.Y, 0.0,                                          ; 801F0423 64401D10
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                        ; 801F00FF 00002288
	  SETGT_DX10            * T13.Y, T36.W, T31.Y, Pred_sel_zero                          ; C083EC24 21A00690
	  AND_INT               * T34.W, T13.Y, 1,                                            ; 801F440D 64401810
	  MOV                     T13.Y, T37.W,                                               ; 00000C25 21A00C90
	  CNDE_INT                T13.Z, PV.W, T13.Z, T32.Y,                                  ; 0101ACFE 41A38420
	  CNDE_INT                T38.W, PV.W, T36.W, T31.Y, BS:VEC_021/SCL_122               ; 01848CFE 64C7841F
	  SETE_INT              * T36.W, T35.Z, 0.0,                                          ; 801F0823 64801D10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                        ; 801F00FF 00002288
	  SETGT_DX10            * T13.Y, T38.W, T31.Z, Pred_sel_zero                          ; C103EC26 21A00690
	  AND_INT               * T36.W, T13.Y, 1,                                            ; 801F440D 64801810
	  CNDE_INT                T13.Z, PV.W, T13.Z, T32.Z,                                  ; 0101ACFE 41A38820
	  CNDE_INT                T38.W, PV.W, T38.W, T31.Z, BS:VEC_210                       ; 0184CCFE 64D7881F
	  SETE_INT              * T35.W, T35.W, 0.0,                                          ; 801F0C23 64601D10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                        ; 801F00FF 00002288
	  SETGT_DX10            * T37.W, T38.W, T31.W, Pred_sel_zero                          ; C183EC26 64A00690
	  AND_INT               * T35.W, T37.W, 1,                                            ; 801F4C25 64601810
	  CNDE_INT              * T32.W, PV.W, T13.Z, T32.W,                                  ; 8101ACFE 64038C20
	  SETE_INT              * T37.W, PV.W, literal.x,                                     ; 801FACFE 64A01D10
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                      ; 801F0CFE 00002288
	  LSHL                  * T21.W, T12.Z, literal.x, Pred_sel_zero                      ; C01FA80C 62A00B90
	31(4.344025e-44), 0(0.000000e+00)                                                     ; 0000001F 00000000
	  CNDE_INT              * T20.X, T35.W, T38.W, T31.W, Pred_sel_zero                   ; C184CC23 02838C1F
	  ASHR                  * T21.W, T21.W, literal.x, Pred_sel_zero                      ; C01FAC15 62A00A90
	31(4.344025e-44), 0(0.000000e+00)                                                     ; 0000001F 00000000
	  MOV                     T20.Y, T20.X, Pred_sel_zero                                 ; 40000014 22800C90
	  CNDE_INT                T8.Z, T33.W, literal.x, T28.X, Pred_sel_zero                ; 401FAC21 4103801C
	  AND_INT               * T22.W, T21.W, T30.X, Pred_sel_zero BS:VEC_210               ; C003CC15 62D41810
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  AND_INT               * T21.W, T21.W, T29.X, Pred_sel_zero                          ; C003AC15 62A01810
	  CNDE_INT                T10.Y, T34.W, T21.W, T29.Y, Pred_sel_zeroBS:VEC_201         ; 4182AC22 2153841D
	  MOV                     T20.Z, T20.X, Pred_sel_zero                                 ; 40000014 42800C90
	  CNDE_INT                T21.W, T34.W, T22.W, T30.Y, Pred_sel_zeroBS:VEC_210         ; 4182CC22 62B7841E
	  CNDE_INT              * T22.W, T34.W, T8.Z, T28.Y, Pred_sel_zeroBS:VEC_120/SCL_212  ; C1010C22 62CB841C
	  CNDE_INT                T13.Y, T36.W, T22.W, T28.Z, Pred_sel_zero                   ; 4182CC24 21A3881C
	  CNDE_INT              * T12.Z, T36.W, T21.W, T30.Z, Pred_sel_zeroBS:VEC_021/SCL_122 ; C182AC24 4187881E
	  CNDE_INT                T21.W, T36.W, T10.Y, T29.Z, Pred_sel_zero                   ; 40814C24 62A3881D
	  MOV                   * T20.W, T20.X, Pred_sel_zero                                 ; C0000014 62800C90
	  MOV                   * T8.Z, T20.X, Pred_sel_zero                                  ; C0000014 41000C90
	  MOV                   * T10.Y, T32.W, Pred_sel_zero                                 ; C0000C20 21400C90
	  CNDE_INT              * T10.Z, T35.W, T21.W, T29.W, Pred_sel_zero                   ; C182AC23 41438C1D
	  CNDE_INT                T21.W, T35.W, T12.Z, T30.W, Pred_sel_zeroBS:VEC_201         ; 41018C23 62B38C1E
	  CNDE_INT              * T22.W, T35.W, T13.Y, T28.W, Pred_sel_zero                   ; C081AC23 62C38C1C
	  ADD_INT               * T27.W, T27.W, literal.x,                                    ; 801FAC1B 63601A10
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  ADD_INT                 T13.X, T13.X, literal.x,                                    ; 001FA00D 01A01A10
	  SETE_INT              * T28.W, PV.W, 0.0,                                           ; 801F0CFE 63801D10
	176(2.466285e-43), 0(0.000000e+00)                                                    ; 000000B0 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002284
	ALU clause starting at 0x1ed:                                                         ; 
	  MOV                     T13.Y, T12.Y,                                               ; 0000040C 21A00C90
	  MOV                     T28.W, literal.x,                                           ; 000000FD 63800C90
	  SETGT_INT             * T27.W, 1, T25.W,                                            ; 818320FA 63601D90
	0(0.000000e+00), 0(0.000000e+00)                                                      ; 00000000 00000000
	ALU clause starting at 0x1f1:                                                         ; 
	  MOV                     T13.X, T8.Z,                                                ; 00000808 01A00C90
	  MOV                   * T15.X, T10.Z,                                               ; 8000080A 01E00C90
	  MOV                     T16.X, T21.W,                                               ; 00000C15 02000C90
	  MOV                   * T18.X, T10.Y,                                               ; 8000040A 02400C90
	  MOV                     T21.X, T22.W,                                               ; 00000C16 02A00C90
	  BFE_INT               * T25.W, T28.W, 0.0, 1, BS:VEC_120/SCL_212                    ; 801F0C1C 6328A0FA
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002284
	ALU clause starting at 0x1f8:                                                         ; 
	  MULLO_INT             * T12.X, T12.X, literal.x,                                    ; 801FA00C 01804790
	112(1.569454e-43), 0(0.000000e+00)                                                    ; 00000070 00000000
	  ADD_INT               * T12.X, T0.Z, PS,                                            ; 801FE800 01801A10
	  MULADD_UINT24         * T13.X, T16.W, literal.x, PV.X,                              ; 801FAC10 01A200FE
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  MULADD_UINT24         * T15.X, T10.X, literal.x, T12.X,                             ; 801FA00A 01E2000C
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  MULADD_UINT24         * T16.X, T15.W, literal.x, T12.X,                             ; 801FAC0F 0202000C
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  MULADD_UINT24         * T18.X, T13.W, literal.x, T12.X,                             ; 801FAC0D 0242000C
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  MULADD_UINT24         * T21.X, T10.W, literal.x, T12.X,                             ; 801FAC0A 02A2000C
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	ALU clause starting at 0x205:                                                         ; 
	  ADD                   * T31.W, T30.Z, -T2.Z,                                        ; 8300481E 63E00010
	  MUL_IEEE                T31.W, T9.Z, PV.W,                                          ; 019FC809 63E00110
	  ADD                   * T32.W, T29.Z, -T2.Z,                                        ; 8300481D 64000010
	  MUL_IEEE                T12.Z, T9.Z, PS,                                            ; 001FE809 41800110
	  ADD                   * T32.W, T28.Z, -T4.Z,  BS:VEC_120/SCL_212                    ; 8300881C 64080010
	  SETGT_DX10            * T33.W, T19.Z, T31.W,                                        ; 8183E813 64200690
	  CNDE_INT                T13.X, PV.W, T19.Z, T31.W,                                  ; 01026CFE 01A38C1F
	  MUL_IEEE              * T15.Y, T14.Z, T32.W,                                        ; 8184080E 21E00110
	  ADD                     T13.Z, T30.W, -T2.W,                                        ; 03804C1E 41A00010
	  ADD                   * T31.W, T26.Z, -T4.Z,                                        ; 8300881A 63E00010
	  SETGT_DX10            * T32.W, T12.Z, T6.Z,                                         ; 8100C80C 64000690
	  CNDE_INT                T15.X, PV.W, T6.Z, T12.Z,                                   ; 0100CCFE 01E3880C
	  MUL_IEEE              * T16.Y, T14.Z, T31.W,                                        ; 8183E80E 22000110
	  MUL_IEEE                T12.Z, T9.W, T13.Z,                                         ; 0101AC09 41800110
	  ADD                     T31.W, T25.Z, -T3.Z,  BS:VEC_021/SCL_122                    ; 03006819 63E40010
	  SETGT_DX10            * T32.W, T13.X, T15.Y,                                        ; 8081E00D 64000690
	  CNDE_INT                T13.X, PS, T13.X, T15.Y, BS:VEC_021/SCL_122                 ; 0001A0FF 01A7840F
	  MUL_IEEE                T15.Y, T11.Z, PV.W,                                         ; 019FC80B 21E00110
	  ADD                     T13.Z, T28.W, -T4.W,                                        ; 03808C1C 41A00010
	  SETGT_DX10              T31.W, T19.W, PV.Z,  BS:VEC_201                             ; 011FCC13 63F00690
	  SETGT_DX10            * T32.W, T16.Y, T15.X,                                        ; 8001E410 64000690
	  MULADD_UINT24           T16.X, T7.X, literal.x, T12.X,                              ; 001FA007 0202000C
	  CNDE_INT                T16.Y, PS, T15.X, T16.Y,                                    ; 0001E0FF 22038410
	  CNDE_INT                T12.Z, PV.W, T19.W, T12.Z,                                  ; 01826CFE 4183880C
	  MUL_IEEE              * T31.W, T14.W, PV.Z,                                         ; 811FCC0E 63E00110
	48(6.726233e-44), 0(0.000000e+00)                                                     ; 00000030 00000000
	  ADD                   * T32.W, T29.W, -T2.W,                                        ; 83804C1D 64000010
	ALU clause starting at 0x220:                                                         ; 
	  ADD                   * T35.W, T34.Z, -T3.Z,                                        ; 83006822 64600010
	  MUL_IEEE                T12.X, T11.Z, PV.W,                                         ; 019FC80B 01800110
	  MUL_IEEE                T18.Y, T9.W, T32.W,                                         ; 01840C09 22400110
	  ADD                   * T13.Z, T30.Y, -T2.Y,                                        ; 8280441E 41A00010
	  ADD                     T32.W, T25.W, -T3.W,  BS:VEC_021/SCL_122                    ; 03806C19 64040010
	  SETGT_DX10            * T35.W, T12.Z, T31.W,                                        ; 8183E80C 64600690
	  CNDE_INT                T15.X, PS, T12.Z, T31.W,                                    ; 010180FF 01E38C1F
	  MUL_IEEE                T21.Y, T11.W, PV.W,                                         ; 019FCC0B 22A00110
	  MUL_IEEE              * T12.Z, T9.Y, T13.Z,  BS:VEC_021/SCL_122                     ; 8101A409 41840110
	  ADD                     T31.W, T26.W, -T4.W,  BS:VEC_021/SCL_122                    ; 03808C1A 63E40010
	  SETGT_DX10            * T32.W, T18.Y, T6.W,                                         ; 8180C412 64000690
	  CNDE_INT                T16.X, PS, T6.W, T18.Y,                                     ; 0180C0FF 02038412
	  MUL_IEEE                T18.Y, T14.W, PV.W,                                         ; 019FCC0E 22400110
	  ADD                   * T13.Z, T29.Y, -T2.Y,                                        ; 8280441D 41A00010
	  ADD                     T31.W, T28.Y, -T4.Y,                                        ; 0280841C 63E00010
	  SETGT_DX10            * T32.W, T19.Y, T12.Z,                                        ; 81018413 64000690
	  CNDE_INT                T18.X, PS, T19.Y, T12.Z,                                    ; 008260FF 0243880C
	  MUL_IEEE                T22.Y, T14.Y, PV.W,                                         ; 019FC40E 22C00110
	  MUL_IEEE                T12.Z, T9.Y, T13.Z,  BS:VEC_201                             ; 0101A409 41900110
	  ADD                   * T31.W, T34.W, -T3.W,                                        ; 83806C22 63E00010
	  SETGT_DX10            * T32.W, T18.Y, T16.X,                                        ; 80020412 64000690
	  CNDE_INT                T16.X, PV.W, T16.X, T18.Y,                                  ; 00020CFE 02038412
	  MUL_IEEE                T18.Y, T11.W, T31.W,                                        ; 0183EC0B 22400110
	  ADD                   * T13.Z, T26.Y, -T4.Y,                                        ; 8280841A 41A00010
	  SETGT_DX10              T31.W, T12.Z, T6.Y,  BS:VEC_021/SCL_122                     ; 0080C80C 63E40690
	  SETGT_DX10            * T32.W, T18.X, T22.Y,                                        ; 8082C012 64000690
	  CNDE_INT                T18.X, PS, T18.X, T22.Y,                                    ; 000240FF 02438416
	  CNDE_INT                T22.Y, PV.W, T6.Y, T12.Z,                                   ; 0080CCFE 22C3880C
	  MUL_IEEE              * T12.Z, T14.Y, T13.Z,                                        ; 8101A40E 41800110
	  SETGT_DX10              T31.W, T18.Y, T16.X,                                        ; 00020412 63E00690
	  SETGT_DX10            * T32.W, T15.X, T21.Y,                                        ; 8082A00F 64000690
	  CNDE_INT                T15.X, PS, T15.X, T21.Y,                                    ; 0001E0FF 01E38415
	  CNDE_INT              * T18.Y, PV.W, T16.X, T18.Y, BS:VEC_021/SCL_122               ; 80020CFE 22478412
	  ADD                     T13.Z, T34.Y, -T3.Y,                                        ; 02806422 41A00010
	  SETGT_DX10            * T31.W, T12.Z, T22.Y,  BS:VEC_021/SCL_122                    ; 8082C80C 63E40690
	  ADD                   * T32.W, T25.Y, -T3.Y,                                        ; 82806419 64000010
	  MUL_IEEE                T16.X, T11.Y, PV.W,                                         ; 019FC40B 02000110
	  CNDE_INT                T21.Y, T31.W, T22.Y, T12.Z,                                 ; 0082CC1F 22A3880C
	  MUL_IEEE                T12.Z, T11.Y, T13.Z,                                        ; 0101A40B 41800110
	  SETGE_DX10              T31.W, T15.X, T18.Y,  BS:VEC_021/SCL_122                    ; 0082400F 63E40710
	  SETNE_INT             * T32.W, T33.W, literal.x,                                    ; 801FAC21 64001E90
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  AND_INT                 T15.X, PS, PV.W,                                            ; 019FC0FF 01E01810
	  SETGT_DX10              T18.Y, PV.Z, PV.Y,                                          ; 009FC8FE 22400690
	  SETGT_DX10              T13.Z, T18.X, PV.X,                                         ; 001FC012 41A00690
	  SETGT_DX10              T31.W, T12.X, T16.Y,  BS:VEC_120/SCL_212                    ; 0082000C 63E80690
	  SETGT_DX10            * T32.W, T13.X, T15.Y,                                        ; 8081E00D 64000690
	  CNDE_INT                T13.X, PS, T13.X, T15.Y,                                    ; 0001A0FF 01A3840F
	  CNDE_INT              * T15.Y, PV.W, T16.Y, T12.X,                                  ; 80820CFE 21E3800C
	  ADD                   * T15.Z, T30.X, -T2.X,                                        ; 8200401E 41E00010
	  CNDE_INT                T30.W, T13.Z, T18.X, T16.X, BS:VEC_120/SCL_212              ; 0002480D 63CB8010
	  CNDE_INT              * T31.W, T18.Y, T21.Y, T12.Z,                                 ; 8082A412 63E3880C
	  SETGE_DX10              T12.X, PV.W, PS,                                            ; 001FECFE 01800710
	  MUL_IEEE                T16.Y, T9.X, T15.Z,                                         ; 0101E009 22000110
	  SETGE_DX10              T12.Z, T13.X, T15.Y,  BS:VEC_120/SCL_212                    ; 0081E00D 41880710
	  SETNE_INT               T30.W, T33.Z, literal.x,                                    ; 001FA821 63C01E90
	  AND_INT               * T31.W, T15.X, 1,                                            ; 801F400F 63E01810
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  SETNE_INT               T13.X, T33.Y, literal.x,                                    ; 001FA421 01A01E90
	  ADD_INT                 T12.Y, PS, T12.Y,                                           ; 008180FF 21801A10
	  AND_INT                 T12.Z, PV.W, PV.Z,                                          ; 011FCCFE 41801810
	  ADD                     T28.W, T28.X, -T4.X,                                        ; 0200801C 63800010
	  SETGT_DX10            * T30.W, T19.X, PV.Y,                                         ; 809FC013 63C00690
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  CNDE_INT                T15.Y, PS, T19.X, T16.Y, BS:VEC_021/SCL_122                 ; 000260FF 21E78410
	  MUL_IEEE                T13.Z, T14.X, PV.W,                                         ; 019FC00E 41A00110
	  SUB_INT                 T28.W, PV.Y, PV.Z,                                          ; 011FC4FE 63801A90
	  AND_INT               * T30.W, PV.X, T12.X,                                         ; 800180FE 63C01810
	  SUB_INT                 T12.Z, PV.W, PS,                                            ; 001FECFE 41801A90
	  ADD                     T29.W, T29.X, -T2.X,                                        ; 0200401D 63A00010
	  SETGT_DX10            * T30.W, PV.Y, PV.Z,                                          ; 811FC4FE 63C00690
	  CNDE_INT                T12.Y, PS, T15.Y, T13.Z,                                    ; 0081E0FF 2183880D
	  MUL_IEEE                T13.Z, T9.X, PV.W,                                          ; 019FC009 41A00110
	  ADD_INT                 T24.W, T31.W, T24.W,                                        ; 01830C1F 63001A10
	  ADD_INT               * T29.W, PV.Z, T8.X,                                          ; 800108FE 63A01A10
	  LSHL                    T12.X, PS, literal.x,                                       ; 001FA0FF 01800B90
	  LSHL                    T15.Y, PV.W, literal.x,                                     ; 001FACFE 21E00B90
	  ADD                     T15.Z, T26.X, -T4.X,                                        ; 0200801A 41E00010
	  SETGT_DX10            * T24.W, PV.Z, T6.X,  BS:VEC_021/SCL_122                      ; 8000C8FE 63040690
	2(2.802597e-45), 0(0.000000e+00)                                                      ; 00000002 00000000
	  ADD_INT               * T26.W, T28.W, T8.X,                                         ; 80010C1C 63401A10
	  LDS_WRITE             * T23.W, T33.W,                                               ; 81842C17 01A22000
	  LSHL                    T16.Y, T26.W, literal.x,                                    ; 001FAC1A 22000B90
	  CNDE_INT                T13.Z, T24.W, T6.X, T13.Z, BS:VEC_120/SCL_212               ; 0000CC18 41AB880D
	  MUL_IEEE                T23.W, T14.X, T15.Z,                                        ; 0101E00E 62E00110
	  ADD_INT               * T24.W, T18.W, T15.Y,                                        ; 8081EC12 63001A10
	2(2.802597e-45), 0(0.000000e+00)                                                      ; 00000002 00000000
	  LDS_WRITE             * T24.W, T33.Z,                                               ; 81042C18 01A22000
	  ADD                     T15.Y, T34.X, -T3.X,                                        ; 02006022 21E00010
	  SETGT_DX10              T15.Z, T23.W, T13.Z,                                        ; 0101AC17 41E00690
	  ADD                     T24.W, T25.X, -T3.X,  BS:VEC_210                            ; 02006019 63140010
	  ADD_INT               * T25.W, T18.W, T16.Y,                                        ; 80820C12 63201A10
	  LDS_WRITE             * T25.W, T33.Y,                                               ; 80842C19 01A22000
	  MUL_IEEE                T16.Y, T11.X, T24.W,                                        ; 0183000B 22000110
	  CNDE_INT                T13.Z, T15.Z, T13.Z, T23.W, BS:VEC_120/SCL_212              ; 0101A80F 41AB8C17
	  MUL_IEEE                T23.W, T11.X, T15.Y,                                        ; 0081E00B 62E00110
	  ADD_INT               * T24.W, T18.W, T12.X,                                        ; 80018C12 63001A10
	  LDS_WRITE             * T24.W, T33.X,                                               ; 80042C18 01A22000
	  SETGT_DX10              T24.W, T23.W, T13.Z,                                        ; 0101AC17 63000690
	  SETGT_DX10            * T25.W, T12.Y, T16.Y,                                        ; 8082040C 63200690
	  MOV                     T13.X, T8.Y,                                                ; 00000408 01A00C90
	  CNDE_INT                T25.W, PS, T12.Y, T16.Y,                                    ; 008180FF 63238410
	  CNDE_INT              * T23.W, PV.W, T13.Z, T23.W,                                  ; 8101ACFE 62E38C17
	  MOV                     T15.X, T7.Z,                                                ; 00000807 01E00C90
	  SETGE_DX10              T23.W, PV.W, PS,                                            ; 001FECFE 62E00710
	  SETNE_INT             * T24.W, T33.X, literal.x,                                    ; 801FA021 63001E90
	-1(-nan), 0(0.000000e+00)                                                             ; FFFFFFFF 00000000
	  MOV                     T16.X, T0.X,                                                ; 00000000 02000C90
	  AND_INT                 T23.W, PS, PV.W,                                            ; 019FC0FF 62E01810
	  MOV                   * T18.X, T12.W,                                               ; 80000C0C 02400C90
	  SUB_INT               * T25.W, T12.Z, PV.W,                                         ; 819FC80C 63201A90
	  MOV                     T21.X, T0.Y,                                                ; 00000400 02A00C90
	  LSHR                  * T26.W, PV.W, literal.x,                                     ; 801FACFE 63400B10
	31(4.344025e-44), 0(0.000000e+00)                                                     ; 0000001F 00000000
	ALU clause starting at 0x292:                                                         ; 
	  SETNE_INT             * T23.W, T26.W, 1,                                            ; 801F4C1A 62E01E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002104
	ALU clause starting at 0x294:                                                         ; 
	  AND_INT               * T12.W, T27.W, 1,                                            ; 801F4C1B 61801810
	  MOV                   * T0.Y, T22.W,                                                ; 80000C16 20000C90
	  MOV                     T0.X, T21.W,                                                ; 00000C15 00000C90
	  MOV                   * T7.Z, T10.Z,                                                ; 8000080A 40E00C90
	  MOV                     T8.Y, T8.Z,                                                 ; 00000808 21000C90
	  SETE_INT                T21.W, T12.W, 0.0,                                          ; 001F0C0C 62A01D10
	  MOV                   * T12.W, T10.Y,                                               ; 8000040A 61800C90
	  MOV                     T19.X, T20.X,                                               ; 00000014 02600C90
	  MOV                     T19.Y, T20.Y,                                               ; 00000414 22600C90
	  MOV                     T19.Z, T20.Z,                                               ; 00000814 42600C90
	  MOV                     T19.W, T20.W,                                               ; 00000C14 62600C90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002104
	ALU clause starting at 0x2a0:                                                         ; 
	  MULLO_INT             * T0.X, T0.W, literal.x,                                      ; 801FAC00 00004790
	20(2.802597e-44), 0(0.000000e+00)                                                     ; 00000014 00000000
	  ADD_INT               * T0.W, T7.Y, PS,                                             ; 801FE407 60001A10
	  ADD_INT               * T1.W, PV.W, literal.x,                                      ; 801FACFE 60201A10
	16(2.242078e-44), 0(0.000000e+00)                                                     ; 00000010 00000000
	  LSHR                    T0.X, PV.W, literal.x,                                      ; 001FACFE 00000B10
	  ADD_INT               * T1.W, T0.W, literal.y,                                      ; 809FAC00 60201A10
	2(2.802597e-45), 12(1.681558e-44)                                                     ; 00000002 0000000C
	  LSHR                    T1.X, PV.W, literal.x,                                      ; 001FACFE 00200B10
	  ADD_INT               * T1.W, T0.W, literal.y,                                      ; 809FAC00 60201A10
	2(2.802597e-45), 8(1.121039e-44)                                                      ; 00000002 00000008
	  LSHR                    T2.X, PV.W, literal.x,                                      ; 001FACFE 00400B10
	  ADD_INT               * T1.W, T0.W, literal.y,                                      ; 809FAC00 60201A10
	2(2.802597e-45), 4(5.605194e-45)                                                      ; 00000002 00000004
	  LSHR                    T3.X, PV.W, literal.x,                                      ; 001FACFE 00600B10
	  LSHR                  * T4.X, T0.W, literal.x,                                      ; 801FAC00 00800B10
	2(2.802597e-45), 0(0.000000e+00)                                                      ; 00000002 00000000

bytecode 1378 dw -- 51 gprs -- 5 nstack -------------
shader 2 -- E
--------------------------------------
input 0 : 1024
input 1 : 1
input 2 : 1
input 3 : 65536
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 27762688
input 10 : 0
input 11 : 30912512
input 12 : 35782656
input 13 : 65536
input 14 : 0
Using 2 pipes, 2 wavefronts per thread block, allocating 2048 dwords lds.
*** evergreen_set_global_binding first = 0 n = 4
*** evergreen_set_compute_resources: start = 0 count = 0
*** r600_compute_global_buffer_create
width = 240 array_size = 0
* compute_memory_alloc() size_in_dw = 60 (240 bytes)
  + Adding item 0x7f4354034490 id = 9 size = 60 (240 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 240, height = 1, depth = 1)
Buffer id = 9 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 2412 array_size = 0
* compute_memory_alloc() size_in_dw = 603 (2412 bytes)
  + Adding item 0x7f43540c0210 id = 10 size = 603 (2412 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 2412, height = 1, depth = 1)
Buffer id = 10 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 28 array_size = 0
* compute_memory_alloc() size_in_dw = 7 (28 bytes)
  + Adding item 0x7f43540bff30 id = 11 size = 7 (28 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 28, height = 1, depth = 1)
Buffer id = 11 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 1064 array_size = 0
* compute_memory_alloc() size_in_dw = 266 (1064 bytes)
  + Adding item 0x7f4354015280 id = 12 size = 266 (1064 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 1064, height = 1, depth = 1)
Buffer id = 12 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 2680560 array_size = 0
* compute_memory_alloc() size_in_dw = 670140 (2680560 bytes)
  + Adding item 0x7f43540bfe90 id = 13 size = 670140 (2680560 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 2680560, height = 1, depth = 1)
Buffer id = 13 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 2680560 array_size = 0
* compute_memory_alloc() size_in_dw = 670140 (2680560 bytes)
  + Adding item 0x7f43540708f0 id = 14 size = 670140 (2680560 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 2680560, height = 1, depth = 1)
Buffer id = 14 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 326008 array_size = 0
* compute_memory_alloc() size_in_dw = 81502 (326008 bytes)
  + Adding item 0x7f43540a0510 id = 15 size = 81502 (326008 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 326008, height = 1, depth = 1)
Buffer id = 15 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 566772 array_size = 0
* compute_memory_alloc() size_in_dw = 141693 (566772 bytes)
  + Adding item 0x7f43540496b0 id = 16 size = 141693 (566772 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 566772, height = 1, depth = 1)
Buffer id = 16 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 3129528 array_size = 0
* compute_memory_alloc() size_in_dw = 782382 (3129528 bytes)
  + Adding item 0x7f435409d1d0 id = 17 size = 782382 (3129528 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 3129528, height = 1, depth = 1)
Buffer id = 17 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 272 array_size = 0
* compute_memory_alloc() size_in_dw = 68 (272 bytes)
  + Adding item 0x7f435409cdd0 id = 18 size = 68 (272 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 272, height = 1, depth = 1)
Buffer id = 18 offset = 0 (box.x)
*** r600_compute_global_buffer_create
width = 28 array_size = 0
* compute_memory_alloc() size_in_dw = 7 (28 bytes)
  + Adding item 0x7f4354035060 id = 19 size = 7 (28 bytes)
* r600_compute_global_transfer_map()
level = 0, usage = 4098, box(x = 0, y = 0, z = 0 width = 28, height = 1, depth = 1)
Buffer id = 19 offset = 0 (box.x)
*** evergreen_create_compute_state
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 18
* compute_memory_finalize_pending()
  + list: offset = 0 id = 6 size = 327680 (1310720 bytes)
  + list: offset = 1238016 id = 1 size = 5505024 (22020096 bytes)
  + list: offset = 6743040 id = 2 size = 131073 (524292 bytes)
  + list: offset = 6940672 id = 4 size = 786432 (3145728 bytes)
  + list: offset = 7727104 id = 5 size = 132 (528 bytes)
  + list: offset = 7728128 id = 7 size = 1217076 (4868304 bytes)
  + list: offset = 8945664 id = 8 size = 3832532 (15330128 bytes)
* compute_memory_grow_pool() new_size_in_dw = 15461376 (61845504 bytes)
  Aligned size = 15461376 (61845504 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 54890496
timeout on cs lockup likely happen at cs 0x00000005 dw 0x000001fb
timeout on cs lockup likely happen at cs 0x00000012 dw 0x00000494
timeout on cs lockup likely happen at cs 0x00000012 dw 0x00000494
timeout on cs lockup likely happen at cs 0x00000012 dw 0x00000494
* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 61845504
* compute_memory_prealloc_chunk() size_in_dw = 1237776
  + Found space for Item 0x436e4a0 id = 0 start_in_dw = 12778496 (51113984 bytes) size_in_dw = 1237776 (4951104 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 12778496
* compute_memory_prealloc_chunk() size_in_dw = 65536
  + Found space for Item 0x3503560 id = 3 start_in_dw = 327680 (1310720 bytes) size_in_dw = 65536 (262144 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 327680
* compute_memory_prealloc_chunk() size_in_dw = 60
  + Found space for Item 0x7f4354034490 id = 9 start_in_dw = 393216 (1572864 bytes) size_in_dw = 60 (240 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 393216
* compute_memory_prealloc_chunk() size_in_dw = 603
  + Found space for Item 0x7f43540c0210 id = 10 start_in_dw = 394240 (1576960 bytes) size_in_dw = 603 (2412 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 394240
* compute_memory_prealloc_chunk() size_in_dw = 7
  + Found space for Item 0x7f43540bff30 id = 11 start_in_dw = 395264 (1581056 bytes) size_in_dw = 7 (28 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 395264
* compute_memory_prealloc_chunk() size_in_dw = 266
  + Found space for Item 0x7f4354015280 id = 12 start_in_dw = 396288 (1585152 bytes) size_in_dw = 266 (1064 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 396288
* compute_memory_prealloc_chunk() size_in_dw = 670140
  + Found space for Item 0x7f43540bfe90 id = 13 start_in_dw = 397312 (1589248 bytes) size_in_dw = 670140 (2680560 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 397312
* compute_memory_prealloc_chunk() size_in_dw = 670140
  + Found space for Item 0x7f43540708f0 id = 14 start_in_dw = 14016512 (56066048 bytes) size_in_dw = 670140 (2680560 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 14016512
* compute_memory_prealloc_chunk() size_in_dw = 81502
  + Found space for Item 0x7f43540a0510 id = 15 start_in_dw = 1068032 (4272128 bytes) size_in_dw = 81502 (326008 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 1068032
* compute_memory_prealloc_chunk() size_in_dw = 141693
  + Found space for Item 0x7f43540496b0 id = 16 start_in_dw = 14687232 (58748928 bytes) size_in_dw = 141693 (566772 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 14687232
* compute_memory_prealloc_chunk() size_in_dw = 782382
* compute_memory_grow_pool() new_size_in_dw = 15854592 (63418368 bytes)
  Aligned size = 15854592 (63418368 bytes)
* compute_memory_shadow() device_to_host = 1
* compute_memory_transfer() device_to_host = 1, offset_in_chunk = 0, size = 61845504
* compute_memory_shadow() device_to_host = 0
* compute_memory_transfer() device_to_host = 0, offset_in_chunk = 0, size = 63418368
* compute_memory_prealloc_chunk() size_in_dw = 782382
  + Found space for Item 0x7f435409d1d0 id = 17 start_in_dw = 14829568 (59318272 bytes) size_in_dw = 782382 (3129528 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 14829568
* compute_memory_prealloc_chunk() size_in_dw = 68
  + Found space for Item 0x7f435409cdd0 id = 18 start_in_dw = 1149952 (4599808 bytes) size_in_dw = 68 (272 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 1149952
* compute_memory_prealloc_chunk() size_in_dw = 7
  + Found space for Item 0x7f4354035060 id = 19 start_in_dw = 1150976 (4603904 bytes) size_in_dw = 7 (28 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 1150976
bind rat: 0 
*** evergreen_launch_grid: pc = 2
; ModuleID = 'radeon'
target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"

%struct.GPUTask.100 = type { %struct.Seed.74, %struct.RandomSample.93, %struct.PathStateBase.97, %struct.PathStateDirectLight.98, %struct.PathStateDirectLightPassThrough.99 }
%struct.Seed.74 = type { i32, i32, i32 }
%struct.RandomSample.93 = type { %struct.Spectrum.77 }
%struct.Spectrum.77 = type { float, float, float }
%struct.PathStateBase.97 = type { i32, i32, %struct.Spectrum.77, %struct.BSDF.94 }
%struct.BSDF.94 = type { %struct.HitPoint.82, i32, i32, %struct.Frame.72 }
%struct.HitPoint.82 = type { %struct.Vector.69, %struct.Point.68, %struct.UV.76, %struct.Normal.81, %struct.Normal.81, float }
%struct.Vector.69 = type { float, float, float }
%struct.Point.68 = type { float, float, float }
%struct.UV.76 = type { float, float }
%struct.Normal.81 = type { float, float, float }
%struct.Frame.72 = type { %struct.Vector.69, %struct.Vector.69, %struct.Vector.69 }
%struct.PathStateDirectLight.98 = type { %struct.Spectrum.77, float, i32, %struct.HitPoint.82 }
%struct.PathStateDirectLightPassThrough.99 = type { float, %struct.BSDF.94 }
%struct.GPUTaskStats.101 = type { i32 }
%struct.Ray.70 = type { %struct.Point.68, %struct.Vector.69, float, float, float, [3 x float] }
%struct.RayHit.96 = type { float, float, float, i32, i32 }
%struct.Pixel.92 = type { %struct.Spectrum.77, float }
%struct.Material.89 = type { i32, i32, i32, i32, %union.anon.1.88 }
%union.anon.1.88 = type { %struct.Glossy2Param.87 }
%struct.Glossy2Param.87 = type { i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.Texture.86 = type { i32, %union.anon.0.85 }
%union.anon.0.85 = type { %struct.BandTexParam.84 }
%struct.BandTexParam.84 = type { i32, i32, [16 x float], [16 x %struct.Spectrum.77] }
%struct.Mesh.95 = type { i32, i32, i32, i32, i32, i32, %struct.Transform.73 }
%struct.Transform.73 = type { %struct.Matrix4x4.71, %struct.Matrix4x4.71 }
%struct.Matrix4x4.71 = type { [4 x [4 x float]] }
%struct.Triangle.75 = type { [3 x i32] }
%struct.Camera.90 = type { [2 x %struct.Transform.73], [2 x %struct.Transform.73], float, float, float, float }
%struct.TriangleLight.91 = type { %struct.Vector.69, %struct.Vector.69, %struct.Vector.69, %struct.UV.76, %struct.UV.76, %struct.UV.76, float, i32 }

; Function Attrs: nounwind readnone
declare float @llvm.fabs.f32(float) #0

; Function Attrs: nounwind readnone
declare float @llvm.floor.f32(float) #0

; Function Attrs: nounwind readnone
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare float @llvm.sqrt.f32(float) #0

; Function Attrs: nounwind readnone
declare float @llvm.cos.f32(float) #0

; Function Attrs: nounwind readnone
declare float @llvm.sin.f32(float) #0

; Function Attrs: nounwind readnone
declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) #0

; Function Attrs: nounwind readnone
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

; Function Attrs: nounwind
define void @AdvancePaths(%struct.GPUTask.100 addrspace(1)* %tasks, %struct.GPUTaskStats.101 addrspace(1)* nocapture %taskStats, float addrspace(1)* nocapture %samplesData, %struct.Ray.70 addrspace(1)* nocapture %rays, %struct.RayHit.96 addrspace(1)* nocapture readonly %rayHits, %struct.Pixel.92 addrspace(1)* nocapture %frameBuffer, %struct.Material.89 addrspace(1)* nocapture readonly %mats, %struct.Texture.86 addrspace(1)* nocapture readonly %texs, i32 addrspace(1)* nocapture readonly %meshMats, %struct.Mesh.95 addrspace(1)* nocapture readonly %meshDescs, %struct.Point.68 addrspace(1)* nocapture readonly %vertices, %struct.Vector.69 addrspace(1)* nocapture readonly %vertNormals, %struct.UV.76 addrspace(1)* nocapture readonly %vertUVs, %struct.Spectrum.77 addrspace(1)* nocapture readnone %vertCols, %struct.Triangle.75 addrspace(1)* nocapture readonly %triangles, %struct.Camera.90 addrspace(1)* readonly %camera, %struct.TriangleLight.91 addrspace(1)* nocapture readonly %triLightDefs, i32 addrspace(1)* nocapture readonly %meshTriLightDefsOffset) #1 {
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #0
  %x.i8.i = tail call i32 @llvm.r600.read.local.size.x() #0
  %1 = mul i32 %x.i8.i, %x.i.i
  %x.i1.i = tail call i32 @llvm.r600.read.tidig.x() #0
  %2 = add i32 %x.i1.i, %1
  %3 = icmp ugt i32 %2, 65535
  br i1 %3, label %2254, label %4

; <label>:4                                       ; preds = %0
  %5 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 0
  %6 = load i32 addrspace(1)* %5, align 4, !tbaa !14
  %7 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 1
  %8 = load i32 addrspace(1)* %7, align 4, !tbaa !30
  %9 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3
  %10 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 1
  %11 = shl i32 %2, 1
  %12 = getelementptr inbounds float addrspace(1)* %samplesData, i32 %11
  %13 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 0, i32 0
  %14 = load i32 addrspace(1)* %13, align 4, !tbaa !31
  %15 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 0, i32 1
  %16 = load i32 addrspace(1)* %15, align 4, !tbaa !32
  %17 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 0, i32 2
  %18 = load i32 addrspace(1)* %17, align 4, !tbaa !33
  %19 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2
  %20 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2
  %21 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 3
  %22 = load i32 addrspace(1)* %21, align 4, !tbaa !34
  %23 = icmp eq i32 %22, -1
  %.not = icmp ne i32 %6, 0
  %brmerge = or i1 %.not, %23
  br i1 %brmerge, label %459, label %24

; <label>:24                                      ; preds = %4
  %25 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %19, i32 0, i32 0, i32 0
  %26 = load float addrspace(1)* %25, align 4, !tbaa !36
  %27 = insertelement <3 x float> undef, float %26, i32 0
  %28 = getelementptr inbounds float addrspace(1)* %25, i32 1
  %29 = load float addrspace(1)* %28, align 4, !tbaa !36
  %30 = insertelement <3 x float> %27, float %29, i32 1
  %31 = getelementptr inbounds float addrspace(1)* %25, i32 2
  %32 = load float addrspace(1)* %31, align 4, !tbaa !36
  %33 = insertelement <3 x float> %30, float %32, i32 2
  %34 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  %35 = load float addrspace(1)* %34, align 4, !tbaa !36
  %36 = insertelement <3 x float> undef, float %35, i32 0
  %37 = getelementptr inbounds float addrspace(1)* %34, i32 1
  %38 = load float addrspace(1)* %37, align 4, !tbaa !36
  %39 = insertelement <3 x float> %36, float %38, i32 1
  %40 = getelementptr inbounds float addrspace(1)* %34, i32 2
  %41 = load float addrspace(1)* %40, align 4, !tbaa !36
  %42 = insertelement <3 x float> %39, float %41, i32 2
  %43 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %20, i32 0, i32 0
  %44 = load float addrspace(1)* %43, align 4, !tbaa !37
  %45 = insertelement <3 x float> undef, float %44, i32 0
  %46 = shufflevector <3 x float> %45, <3 x float> undef, <3 x i32> zeroinitializer
  %47 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %46, <3 x float> %42, <3 x float> %33) #2
  %48 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 1, i32 0
  %49 = extractelement <3 x float> %47, i32 0
  store float %49, float addrspace(1)* %48, align 4, !tbaa !36
  %50 = extractelement <3 x float> %47, i32 1
  %51 = getelementptr inbounds float addrspace(1)* %48, i32 1
  store float %50, float addrspace(1)* %51, align 4, !tbaa !36
  %52 = extractelement <3 x float> %47, i32 2
  %53 = getelementptr inbounds float addrspace(1)* %48, i32 2
  store float %52, float addrspace(1)* %53, align 4, !tbaa !36
  %54 = fsub <3 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %42
  %55 = getelementptr inbounds %struct.BSDF.94 addrspace(1)* %9, i32 0, i32 0, i32 0, i32 0
  %56 = extractelement <3 x float> %54, i32 0
  store float %56, float addrspace(1)* %55, align 4, !tbaa !36
  %57 = extractelement <3 x float> %54, i32 1
  %58 = getelementptr inbounds float addrspace(1)* %55, i32 1
  store float %57, float addrspace(1)* %58, align 4, !tbaa !36
  %59 = extractelement <3 x float> %54, i32 2
  %60 = getelementptr inbounds float addrspace(1)* %55, i32 2
  store float %59, float addrspace(1)* %60, align 4, !tbaa !36
  %61 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 4
  %62 = load i32 addrspace(1)* %61, align 4, !tbaa !38
  %63 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 0
  %64 = load i32 addrspace(1)* %63, align 4, !tbaa !39
  %65 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 5
  %66 = load i32 addrspace(1)* %65, align 4, !tbaa !43
  %67 = getelementptr inbounds i32 addrspace(1)* %meshMats, i32 %22
  %68 = load i32 addrspace(1)* %67, align 4, !tbaa !44
  %69 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 1
  store i32 %68, i32 addrspace(1)* %69, align 4, !tbaa !45
  %70 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 1
  %71 = load float addrspace(1)* %70, align 4, !tbaa !46
  %72 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 2
  %73 = load float addrspace(1)* %72, align 4, !tbaa !47
  %.sum.i = add i32 %66, %62
  %74 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i, i32 0, i32 0
  %75 = load i32 addrspace(1)* %74, align 4, !tbaa !44
  %.sum1.i = add i32 %75, %64
  %76 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum1.i, i32 0
  %77 = load float addrspace(1)* %76, align 4, !tbaa !36
  %78 = insertelement <3 x float> undef, float %77, i32 0
  %79 = getelementptr inbounds float addrspace(1)* %76, i32 1
  %80 = load float addrspace(1)* %79, align 4, !tbaa !36
  %81 = insertelement <3 x float> %78, float %80, i32 1
  %82 = getelementptr inbounds float addrspace(1)* %76, i32 2
  %83 = load float addrspace(1)* %82, align 4, !tbaa !36
  %84 = insertelement <3 x float> %81, float %83, i32 2
  %85 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i, i32 0, i32 1
  %86 = load i32 addrspace(1)* %85, align 4, !tbaa !44
  %.sum3.i = add i32 %86, %64
  %87 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum3.i, i32 0
  %88 = load float addrspace(1)* %87, align 4, !tbaa !36
  %89 = insertelement <3 x float> undef, float %88, i32 0
  %90 = getelementptr inbounds float addrspace(1)* %87, i32 1
  %91 = load float addrspace(1)* %90, align 4, !tbaa !36
  %92 = insertelement <3 x float> %89, float %91, i32 1
  %93 = getelementptr inbounds float addrspace(1)* %87, i32 2
  %94 = load float addrspace(1)* %93, align 4, !tbaa !36
  %95 = insertelement <3 x float> %92, float %94, i32 2
  %96 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i, i32 0, i32 2
  %97 = load i32 addrspace(1)* %96, align 4, !tbaa !44
  %.sum5.i = add i32 %97, %64
  %98 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum5.i, i32 0
  %99 = load float addrspace(1)* %98, align 4, !tbaa !36
  %100 = insertelement <3 x float> undef, float %99, i32 0
  %101 = getelementptr inbounds float addrspace(1)* %98, i32 1
  %102 = load float addrspace(1)* %101, align 4, !tbaa !36
  %103 = insertelement <3 x float> %100, float %102, i32 1
  %104 = getelementptr inbounds float addrspace(1)* %98, i32 2
  %105 = load float addrspace(1)* %104, align 4, !tbaa !36
  %106 = insertelement <3 x float> %103, float %105, i32 2
  %107 = fsub <3 x float> %95, %84
  %108 = fsub <3 x float> %106, %84
  %109 = extractelement <3 x float> %107, i32 1
  %110 = extractelement <3 x float> %108, i32 2
  %111 = extractelement <3 x float> %107, i32 2
  %112 = extractelement <3 x float> %108, i32 1
  %113 = fmul float %111, %112
  %114 = fsub float -0.000000e+00, %113
  %115 = tail call float @llvm.fmuladd.f32(float %109, float %110, float %114) #2
  %116 = insertelement <3 x float> undef, float %115, i32 0
  %117 = extractelement <3 x float> %108, i32 0
  %118 = extractelement <3 x float> %107, i32 0
  %119 = fmul float %118, %110
  %120 = fsub float -0.000000e+00, %119
  %121 = tail call float @llvm.fmuladd.f32(float %111, float %117, float %120) #2
  %122 = insertelement <3 x float> %116, float %121, i32 1
  %123 = fmul float %109, %117
  %124 = fsub float -0.000000e+00, %123
  %125 = tail call float @llvm.fmuladd.f32(float %118, float %112, float %124) #2
  %126 = insertelement <3 x float> %122, float %125, i32 2
  %127 = fmul float %121, %121
  %128 = tail call float @llvm.fmuladd.f32(float %115, float %115, float %127) #2
  %129 = tail call float @llvm.fmuladd.f32(float %125, float %125, float %128) #2
  %130 = tail call float @llvm.sqrt.f32(float %129) #3
  %131 = insertelement <3 x float> undef, float %130, i32 0
  %132 = shufflevector <3 x float> %131, <3 x float> undef, <3 x i32> zeroinitializer
  %133 = fdiv <3 x float> %126, %132, !fpmath !48
  %134 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 0
  %135 = load float addrspace(1)* %134, align 4, !tbaa !36
  %136 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 0
  %137 = load float addrspace(1)* %136, align 4, !tbaa !36
  %138 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 0
  %139 = load float addrspace(1)* %138, align 4, !tbaa !36
  %140 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 1
  %141 = load float addrspace(1)* %140, align 4, !tbaa !36
  %142 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 1
  %143 = load float addrspace(1)* %142, align 4, !tbaa !36
  %144 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 1
  %145 = load float addrspace(1)* %144, align 4, !tbaa !36
  %146 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 2
  %147 = load float addrspace(1)* %146, align 4, !tbaa !36
  %148 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 2
  %149 = load float addrspace(1)* %148, align 4, !tbaa !36
  %150 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 2
  %151 = load float addrspace(1)* %150, align 4, !tbaa !36
  %152 = extractelement <3 x float> %133, i32 0
  %153 = extractelement <3 x float> %133, i32 1
  %154 = fmul float %153, %137
  %155 = tail call float @llvm.fmuladd.f32(float %135, float %152, float %154) #2
  %156 = extractelement <3 x float> %133, i32 2
  %157 = tail call float @llvm.fmuladd.f32(float %139, float %156, float %155) #2
  %158 = insertelement <3 x float> undef, float %157, i32 0
  %159 = fmul float %153, %143
  %160 = tail call float @llvm.fmuladd.f32(float %141, float %152, float %159) #2
  %161 = tail call float @llvm.fmuladd.f32(float %145, float %156, float %160) #2
  %162 = insertelement <3 x float> %158, float %161, i32 1
  %163 = fmul float %153, %149
  %164 = tail call float @llvm.fmuladd.f32(float %147, float %152, float %163) #2
  %165 = tail call float @llvm.fmuladd.f32(float %151, float %156, float %164) #2
  %166 = insertelement <3 x float> %162, float %165, i32 2
  %167 = fmul float %161, %161
  %168 = tail call float @llvm.fmuladd.f32(float %157, float %157, float %167) #2
  %169 = tail call float @llvm.fmuladd.f32(float %165, float %165, float %168) #2
  %170 = tail call float @llvm.sqrt.f32(float %169) #3
  %171 = insertelement <3 x float> undef, float %170, i32 0
  %172 = shufflevector <3 x float> %171, <3 x float> undef, <3 x i32> zeroinitializer
  %173 = fdiv <3 x float> %166, %172, !fpmath !48
  %174 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 3, i32 0
  %175 = extractelement <3 x float> %173, i32 0
  store float %175, float addrspace(1)* %174, align 4, !tbaa !36
  %176 = extractelement <3 x float> %173, i32 1
  %177 = getelementptr inbounds float addrspace(1)* %174, i32 1
  store float %176, float addrspace(1)* %177, align 4, !tbaa !36
  %178 = extractelement <3 x float> %173, i32 2
  %179 = getelementptr inbounds float addrspace(1)* %174, i32 2
  store float %178, float addrspace(1)* %179, align 4, !tbaa !36
  %180 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 1
  %181 = load i32 addrspace(1)* %180, align 4, !tbaa !49
  %182 = icmp eq i32 %181, -1
  br i1 %182, label %265, label %183

; <label>:183                                     ; preds = %24
  %184 = load i32 addrspace(1)* %74, align 4, !tbaa !44
  %.sum6.i = add i32 %184, %181
  %185 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum6.i, i32 0
  %186 = load float addrspace(1)* %185, align 4, !tbaa !36
  %187 = insertelement <3 x float> undef, float %186, i32 0
  %188 = getelementptr inbounds float addrspace(1)* %185, i32 1
  %189 = load float addrspace(1)* %188, align 4, !tbaa !36
  %190 = insertelement <3 x float> %187, float %189, i32 1
  %191 = getelementptr inbounds float addrspace(1)* %185, i32 2
  %192 = load float addrspace(1)* %191, align 4, !tbaa !36
  %193 = insertelement <3 x float> %190, float %192, i32 2
  %194 = load i32 addrspace(1)* %85, align 4, !tbaa !44
  %.sum7.i = add i32 %194, %181
  %195 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum7.i, i32 0
  %196 = load float addrspace(1)* %195, align 4, !tbaa !36
  %197 = insertelement <3 x float> undef, float %196, i32 0
  %198 = getelementptr inbounds float addrspace(1)* %195, i32 1
  %199 = load float addrspace(1)* %198, align 4, !tbaa !36
  %200 = insertelement <3 x float> %197, float %199, i32 1
  %201 = getelementptr inbounds float addrspace(1)* %195, i32 2
  %202 = load float addrspace(1)* %201, align 4, !tbaa !36
  %203 = insertelement <3 x float> %200, float %202, i32 2
  %.sum8.i = add i32 %181, %97
  %204 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum8.i, i32 0
  %205 = load float addrspace(1)* %204, align 4, !tbaa !36
  %206 = insertelement <3 x float> undef, float %205, i32 0
  %207 = getelementptr inbounds float addrspace(1)* %204, i32 1
  %208 = load float addrspace(1)* %207, align 4, !tbaa !36
  %209 = insertelement <3 x float> %206, float %208, i32 1
  %210 = getelementptr inbounds float addrspace(1)* %204, i32 2
  %211 = load float addrspace(1)* %210, align 4, !tbaa !36
  %212 = insertelement <3 x float> %209, float %211, i32 2
  %213 = fsub float 1.000000e+00, %71
  %214 = fsub float %213, %73
  %215 = insertelement <3 x float> undef, float %214, i32 0
  %216 = shufflevector <3 x float> %215, <3 x float> undef, <3 x i32> zeroinitializer
  %217 = insertelement <3 x float> undef, float %71, i32 0
  %218 = shufflevector <3 x float> %217, <3 x float> undef, <3 x i32> zeroinitializer
  %219 = fmul <3 x float> %218, %203
  %220 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %216, <3 x float> %193, <3 x float> %219) #2
  %221 = insertelement <3 x float> undef, float %73, i32 0
  %222 = shufflevector <3 x float> %221, <3 x float> undef, <3 x i32> zeroinitializer
  %223 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %222, <3 x float> %212, <3 x float> %220) #2
  %224 = extractelement <3 x float> %223, i32 0
  %225 = extractelement <3 x float> %223, i32 1
  %226 = fmul float %225, %225
  %227 = tail call float @llvm.fmuladd.f32(float %224, float %224, float %226) #2
  %228 = extractelement <3 x float> %223, i32 2
  %229 = tail call float @llvm.fmuladd.f32(float %228, float %228, float %227) #2
  %230 = tail call float @llvm.sqrt.f32(float %229) #3
  %231 = insertelement <3 x float> undef, float %230, i32 0
  %232 = shufflevector <3 x float> %231, <3 x float> undef, <3 x i32> zeroinitializer
  %233 = fdiv <3 x float> %223, %232, !fpmath !48
  %234 = load float addrspace(1)* %134, align 4, !tbaa !36
  %235 = load float addrspace(1)* %136, align 4, !tbaa !36
  %236 = load float addrspace(1)* %138, align 4, !tbaa !36
  %237 = load float addrspace(1)* %140, align 4, !tbaa !36
  %238 = load float addrspace(1)* %142, align 4, !tbaa !36
  %239 = load float addrspace(1)* %144, align 4, !tbaa !36
  %240 = load float addrspace(1)* %146, align 4, !tbaa !36
  %241 = load float addrspace(1)* %148, align 4, !tbaa !36
  %242 = load float addrspace(1)* %150, align 4, !tbaa !36
  %243 = extractelement <3 x float> %233, i32 0
  %244 = extractelement <3 x float> %233, i32 1
  %245 = fmul float %244, %235
  %246 = tail call float @llvm.fmuladd.f32(float %234, float %243, float %245) #2
  %247 = extractelement <3 x float> %233, i32 2
  %248 = tail call float @llvm.fmuladd.f32(float %236, float %247, float %246) #2
  %249 = insertelement <3 x float> undef, float %248, i32 0
  %250 = fmul float %244, %238
  %251 = tail call float @llvm.fmuladd.f32(float %237, float %243, float %250) #2
  %252 = tail call float @llvm.fmuladd.f32(float %239, float %247, float %251) #2
  %253 = insertelement <3 x float> %249, float %252, i32 1
  %254 = fmul float %244, %241
  %255 = tail call float @llvm.fmuladd.f32(float %240, float %243, float %254) #2
  %256 = tail call float @llvm.fmuladd.f32(float %242, float %247, float %255) #2
  %257 = insertelement <3 x float> %253, float %256, i32 2
  %258 = fmul float %252, %252
  %259 = tail call float @llvm.fmuladd.f32(float %248, float %248, float %258) #2
  %260 = tail call float @llvm.fmuladd.f32(float %256, float %256, float %259) #2
  %261 = tail call float @llvm.sqrt.f32(float %260) #3
  %262 = insertelement <3 x float> undef, float %261, i32 0
  %263 = shufflevector <3 x float> %262, <3 x float> undef, <3 x i32> zeroinitializer
  %264 = fdiv <3 x float> %257, %263, !fpmath !48
  br label %265

; <label>:265                                     ; preds = %183, %24
  %.sink.i = phi <3 x float> [ %264, %183 ], [ %173, %24 ]
  %266 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 2
  %267 = load i32 addrspace(1)* %266, align 4, !tbaa !50
  %268 = icmp eq i32 %267, -1
  br i1 %268, label %301, label %269

; <label>:269                                     ; preds = %265
  %270 = load i32 addrspace(1)* %74, align 4, !tbaa !44
  %.sum9.i = add i32 %270, %267
  %271 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum9.i, i32 0
  %272 = load float addrspace(1)* %271, align 4, !tbaa !36
  %273 = insertelement <2 x float> undef, float %272, i32 0
  %274 = getelementptr inbounds float addrspace(1)* %271, i32 1
  %275 = load float addrspace(1)* %274, align 4, !tbaa !36
  %276 = insertelement <2 x float> %273, float %275, i32 1
  %277 = load i32 addrspace(1)* %85, align 4, !tbaa !44
  %.sum10.i = add i32 %277, %267
  %278 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum10.i, i32 0
  %279 = load float addrspace(1)* %278, align 4, !tbaa !36
  %280 = insertelement <2 x float> undef, float %279, i32 0
  %281 = getelementptr inbounds float addrspace(1)* %278, i32 1
  %282 = load float addrspace(1)* %281, align 4, !tbaa !36
  %283 = insertelement <2 x float> %280, float %282, i32 1
  %.sum11.i = add i32 %267, %97
  %284 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum11.i, i32 0
  %285 = load float addrspace(1)* %284, align 4, !tbaa !36
  %286 = insertelement <2 x float> undef, float %285, i32 0
  %287 = getelementptr inbounds float addrspace(1)* %284, i32 1
  %288 = load float addrspace(1)* %287, align 4, !tbaa !36
  %289 = insertelement <2 x float> %286, float %288, i32 1
  %290 = fsub float 1.000000e+00, %71
  %291 = fsub float %290, %73
  %292 = insertelement <2 x float> undef, float %291, i32 0
  %293 = shufflevector <2 x float> %292, <2 x float> undef, <2 x i32> zeroinitializer
  %294 = insertelement <2 x float> undef, float %71, i32 0
  %295 = shufflevector <2 x float> %294, <2 x float> undef, <2 x i32> zeroinitializer
  %296 = fmul <2 x float> %295, %283
  %297 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %293, <2 x float> %276, <2 x float> %296) #2
  %298 = insertelement <2 x float> undef, float %73, i32 0
  %299 = shufflevector <2 x float> %298, <2 x float> undef, <2 x i32> zeroinitializer
  %300 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %299, <2 x float> %289, <2 x float> %297) #2
  br label %301

; <label>:301                                     ; preds = %269, %265
  %hitPointUV.0.i = phi <2 x float> [ %300, %269 ], [ zeroinitializer, %265 ]
  %302 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 2, i32 0
  %303 = extractelement <2 x float> %hitPointUV.0.i, i32 0
  store float %303, float addrspace(1)* %302, align 4, !tbaa !36
  %304 = extractelement <2 x float> %hitPointUV.0.i, i32 1
  %305 = getelementptr inbounds float addrspace(1)* %302, i32 1
  store float %304, float addrspace(1)* %305, align 4, !tbaa !36
  %306 = getelementptr inbounds i32 addrspace(1)* %meshTriLightDefsOffset, i32 %22
  %307 = load i32 addrspace(1)* %306, align 4, !tbaa !44
  %308 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 2
  store i32 %307, i32 addrspace(1)* %308, align 4, !tbaa !51
  %309 = extractelement <3 x float> %.sink.i, i32 0
  %310 = tail call float @llvm.fabs.f32(float %309) #2
  %311 = extractelement <3 x float> %.sink.i, i32 1
  %312 = tail call float @llvm.fabs.f32(float %311) #2
  %313 = fcmp ogt float %310, %312
  %314 = extractelement <3 x float> %.sink.i, i32 2
  %315 = fmul float %314, %314
  br i1 %313, label %316, label %327

; <label>:316                                     ; preds = %301
  %317 = tail call float @llvm.fmuladd.f32(float %309, float %309, float %315) #2
  %318 = tail call float @llvm.sqrt.f32(float %317) #2
  %319 = fdiv float 1.000000e+00, %318, !fpmath !48
  %320 = fmul float %314, %319
  %321 = fsub float -0.000000e+00, %320
  %322 = insertelement <3 x float> undef, float %321, i32 0
  %323 = insertelement <3 x float> %322, float 0.000000e+00, i32 1
  %324 = shufflevector <3 x float> %323, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %325 = fmul float %309, %319
  %326 = insertelement <3 x float> %323, float %325, i32 2
  br label %BSDF_Init.exit

; <label>:327                                     ; preds = %301
  %328 = tail call float @llvm.fmuladd.f32(float %311, float %311, float %315) #2
  %329 = tail call float @llvm.sqrt.f32(float %328) #2
  %330 = fdiv float 1.000000e+00, %329, !fpmath !48
  %331 = fmul float %314, %330
  %332 = insertelement <3 x float> <float 0.000000e+00, float undef, float undef>, float %331, i32 1
  %333 = fmul float %311, %330
  %334 = fsub float -0.000000e+00, %333
  %335 = insertelement <3 x float> %332, float %334, i32 2
  br label %BSDF_Init.exit

BSDF_Init.exit:                                   ; preds = %316, %327
  %336 = phi <4 x float> [ undef, %327 ], [ %324, %316 ]
  %storemerge.i.i.i = phi <3 x float> [ %335, %327 ], [ %326, %316 ]
  %337 = shufflevector <3 x float> %storemerge.i.i.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %338 = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> %337, <4 x float> %336
  %339 = extractelement <4 x float> %338, i32 2
  %340 = extractelement <4 x float> %338, i32 1
  %341 = fmul float %314, %340
  %342 = fsub float -0.000000e+00, %341
  %343 = tail call float @llvm.fmuladd.f32(float %311, float %339, float %342) #2
  %344 = extractelement <4 x float> %338, i32 0
  %345 = fmul float %309, %339
  %346 = fsub float -0.000000e+00, %345
  %347 = tail call float @llvm.fmuladd.f32(float %314, float %344, float %346) #2
  %348 = fmul float %311, %344
  %349 = fsub float -0.000000e+00, %348
  %350 = tail call float @llvm.fmuladd.f32(float %309, float %340, float %349) #2
  %351 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 0, i32 0
  store float %344, float addrspace(1)* %351, align 4, !tbaa !36
  %352 = getelementptr inbounds float addrspace(1)* %351, i32 1
  store float %340, float addrspace(1)* %352, align 4, !tbaa !36
  %353 = getelementptr inbounds float addrspace(1)* %351, i32 2
  store float %339, float addrspace(1)* %353, align 4, !tbaa !36
  %354 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 1, i32 0
  store float %343, float addrspace(1)* %354, align 4, !tbaa !36
  %355 = getelementptr inbounds float addrspace(1)* %354, i32 1
  store float %347, float addrspace(1)* %355, align 4, !tbaa !36
  %356 = getelementptr inbounds float addrspace(1)* %354, i32 2
  store float %350, float addrspace(1)* %356, align 4, !tbaa !36
  %357 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 2, i32 0
  store float %309, float addrspace(1)* %357, align 4, !tbaa !36
  %358 = getelementptr inbounds float addrspace(1)* %357, i32 1
  store float %311, float addrspace(1)* %358, align 4, !tbaa !36
  %359 = getelementptr inbounds float addrspace(1)* %357, i32 2
  store float %314, float addrspace(1)* %359, align 4, !tbaa !36
  %360 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 4, i32 0
  store float %309, float addrspace(1)* %360, align 4, !tbaa !36
  %361 = getelementptr inbounds float addrspace(1)* %360, i32 1
  store float %311, float addrspace(1)* %361, align 4, !tbaa !36
  %362 = getelementptr inbounds float addrspace(1)* %360, i32 2
  store float %314, float addrspace(1)* %362, align 4, !tbaa !36
  %363 = icmp eq i32 %307, -1
  br i1 %363, label %.thread16, label %364

; <label>:364                                     ; preds = %BSDF_Init.exit
  %365 = load float addrspace(1)* %55, align 4, !tbaa !36
  %366 = load float addrspace(1)* %58, align 4, !tbaa !36
  %367 = load float addrspace(1)* %60, align 4, !tbaa !36
  %368 = fmul float %366, %176
  %369 = tail call float @llvm.fmuladd.f32(float %175, float %365, float %368) #2
  %370 = tail call float @llvm.fmuladd.f32(float %178, float %367, float %369) #2
  %371 = fcmp ugt float %370, 0.000000e+00
  br i1 %371, label %372, label %BSDF_GetEmittedRadiance.exit

; <label>:372                                     ; preds = %364
  %373 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %307, i32 6
  %374 = load float addrspace(1)* %373, align 4, !tbaa !52
  %375 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %307, i32 7
  %376 = load i32 addrspace(1)* %375, align 4, !tbaa !54
  %377 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %376, i32 1
  %378 = load i32 addrspace(1)* %377, align 4, !tbaa !55
  %379 = icmp eq i32 %378, -1
  br i1 %379, label %BSDF_GetEmittedRadiance.exit, label %380

; <label>:380                                     ; preds = %372
  %381 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %378, i32 0
  %382 = load i32 addrspace(1)* %381, align 4, !tbaa !57
  switch i32 %382, label %Texture_GetSpectrumValue.exit.i.i.i.i [
    i32 0, label %383
    i32 1, label %389
  ]

; <label>:383                                     ; preds = %380
  %384 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %378, i32 1
  %385 = bitcast %union.anon.0.85 addrspace(1)* %384 to float addrspace(1)*
  %386 = load float addrspace(1)* %385, align 4, !tbaa !59
  %387 = insertelement <3 x float> undef, float %386, i32 0
  %388 = shufflevector <3 x float> %387, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %Texture_GetSpectrumValue.exit.i.i.i.i

; <label>:389                                     ; preds = %380
  %390 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %378, i32 1
  %391 = bitcast %union.anon.0.85 addrspace(1)* %390 to float addrspace(1)*
  %392 = load float addrspace(1)* %391, align 4, !tbaa !36
  %393 = insertelement <4 x float> undef, float %392, i32 0
  %394 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %378, i32 1, i32 0, i32 1
  %395 = bitcast i32 addrspace(1)* %394 to float addrspace(1)*
  %396 = load float addrspace(1)* %395, align 4, !tbaa !36
  %397 = insertelement <4 x float> %393, float %396, i32 1
  %398 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %378, i32 1, i32 0, i32 2, i32 0
  %399 = load float addrspace(1)* %398, align 4, !tbaa !36
  %400 = insertelement <4 x float> %397, float %399, i32 2
  br label %Texture_GetSpectrumValue.exit.i.i.i.i

Texture_GetSpectrumValue.exit.i.i.i.i:            ; preds = %389, %383, %380
  %401 = phi <4 x float> [ %388, %383 ], [ %400, %389 ], [ undef, %380 ]
  %402 = shufflevector <4 x float> %401, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  br label %BSDF_GetEmittedRadiance.exit

BSDF_GetEmittedRadiance.exit:                     ; preds = %Texture_GetSpectrumValue.exit.i.i.i.i, %372, %364
  %403 = phi float [ undef, %364 ], [ %374, %Texture_GetSpectrumValue.exit.i.i.i.i ], [ %374, %372 ]
  %.0.i12 = phi <3 x float> [ zeroinitializer, %364 ], [ %402, %Texture_GetSpectrumValue.exit.i.i.i.i ], [ zeroinitializer, %372 ]
  %404 = fcmp oeq <3 x float> %.0.i12, zeroinitializer
  %405 = sext <3 x i1> %404 to <3 x i32>
  %406 = extractelement <3 x i32> %405, i32 0
  %407 = extractelement <3 x i32> %405, i32 1
  %408 = and i32 %406, %407
  %409 = extractelement <3 x i32> %405, i32 2
  %410 = and i32 %408, %409
  %411 = icmp slt i32 %410, 0
  br i1 %411, label %.thread16, label %412

; <label>:412                                     ; preds = %BSDF_GetEmittedRadiance.exit
  %413 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 2
  %414 = load i32 addrspace(1)* %413, align 4, !tbaa !61
  %415 = icmp eq i32 %414, 0
  br i1 %415, label %416, label %432

; <label>:416                                     ; preds = %412
  %417 = load float addrspace(1)* %43, align 4, !tbaa !37
  %418 = fmul float %366, %311
  %419 = tail call float @llvm.fmuladd.f32(float %365, float %309, float %418) #2
  %420 = tail call float @llvm.fmuladd.f32(float %367, float %314, float %419) #2
  %421 = tail call float @llvm.fabs.f32(float %420)
  %422 = fmul float %403, %417
  %423 = fmul float %417, %422
  %424 = fdiv float %423, %421, !fpmath !48
  %425 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 1
  %426 = load float addrspace(1)* %425, align 4, !tbaa !62
  %427 = fmul float %424, 2.500000e-01
  %428 = fmul float %426, %426
  %429 = fmul float %427, %427
  %430 = tail call float @llvm.fmuladd.f32(float %426, float %426, float %429) #2
  %431 = fdiv float %428, %430, !fpmath !48
  br label %432

; <label>:432                                     ; preds = %416, %412
  %weight.0 = phi float [ 1.000000e+00, %412 ], [ %431, %416 ]
  %433 = getelementptr inbounds %struct.RandomSample.93 addrspace(1)* %10, i32 0, i32 0, i32 0
  %434 = load float addrspace(1)* %433, align 4, !tbaa !36
  %435 = insertelement <3 x float> undef, float %434, i32 0
  %436 = getelementptr inbounds float addrspace(1)* %433, i32 1
  %437 = load float addrspace(1)* %436, align 4, !tbaa !36
  %438 = insertelement <3 x float> %435, float %437, i32 1
  %439 = getelementptr inbounds float addrspace(1)* %433, i32 2
  %440 = load float addrspace(1)* %439, align 4, !tbaa !36
  %441 = insertelement <3 x float> %438, float %440, i32 2
  %442 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 2, i32 0
  %443 = load float addrspace(1)* %442, align 4, !tbaa !36
  %444 = insertelement <3 x float> undef, float %443, i32 0
  %445 = getelementptr inbounds float addrspace(1)* %442, i32 1
  %446 = load float addrspace(1)* %445, align 4, !tbaa !36
  %447 = insertelement <3 x float> %444, float %446, i32 1
  %448 = getelementptr inbounds float addrspace(1)* %442, i32 2
  %449 = load float addrspace(1)* %448, align 4, !tbaa !36
  %450 = insertelement <3 x float> %447, float %449, i32 2
  %451 = insertelement <3 x float> undef, float %weight.0, i32 0
  %452 = shufflevector <3 x float> %451, <3 x float> undef, <3 x i32> zeroinitializer
  %453 = fmul <3 x float> %452, %450
  %454 = fmul <3 x float> %.0.i12, %453
  %455 = fadd <3 x float> %441, %454
  %456 = extractelement <3 x float> %455, i32 0
  store float %456, float addrspace(1)* %433, align 4, !tbaa !36
  %457 = extractelement <3 x float> %455, i32 1
  store float %457, float addrspace(1)* %436, align 4, !tbaa !36
  %458 = extractelement <3 x float> %455, i32 2
  store float %458, float addrspace(1)* %439, align 4, !tbaa !36
  br label %.thread16

; <label>:459                                     ; preds = %4
  %.mux = select i1 %.not, i32 %6, i32 4
  switch i32 %.mux, label %.thread24 [
    i32 2, label %460
    i32 1, label %..thread16_crit_edge
    i32 3, label %.thread18
    i32 4, label %.thread22
  ]

..thread16_crit_edge:                             ; preds = %459
  %.pre = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 1
  br label %.thread16

; <label>:460                                     ; preds = %459
  br i1 %23, label %461, label %484

; <label>:461                                     ; preds = %460
  %462 = getelementptr inbounds %struct.RandomSample.93 addrspace(1)* %10, i32 0, i32 0, i32 0
  %463 = load float addrspace(1)* %462, align 4, !tbaa !36
  %464 = insertelement <3 x float> undef, float %463, i32 0
  %465 = getelementptr inbounds float addrspace(1)* %462, i32 1
  %466 = load float addrspace(1)* %465, align 4, !tbaa !36
  %467 = insertelement <3 x float> %464, float %466, i32 1
  %468 = getelementptr inbounds float addrspace(1)* %462, i32 2
  %469 = load float addrspace(1)* %468, align 4, !tbaa !36
  %470 = insertelement <3 x float> %467, float %469, i32 2
  %471 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 0, i32 0
  %472 = load float addrspace(1)* %471, align 4, !tbaa !36
  %473 = insertelement <3 x float> undef, float %472, i32 0
  %474 = getelementptr inbounds float addrspace(1)* %471, i32 1
  %475 = load float addrspace(1)* %474, align 4, !tbaa !36
  %476 = insertelement <3 x float> %473, float %475, i32 1
  %477 = getelementptr inbounds float addrspace(1)* %471, i32 2
  %478 = load float addrspace(1)* %477, align 4, !tbaa !36
  %479 = insertelement <3 x float> %476, float %478, i32 2
  %480 = fadd <3 x float> %470, %479
  %481 = extractelement <3 x float> %480, i32 0
  store float %481, float addrspace(1)* %462, align 4, !tbaa !36
  %482 = extractelement <3 x float> %480, i32 1
  store float %482, float addrspace(1)* %465, align 4, !tbaa !36
  %483 = extractelement <3 x float> %480, i32 2
  store float %483, float addrspace(1)* %468, align 4, !tbaa !36
  br label %.thread18

; <label>:484                                     ; preds = %460
  %485 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 0
  %486 = load float addrspace(1)* %485, align 4, !tbaa !63
  %487 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 5
  store float %486, float addrspace(1)* %487, align 4, !tbaa !64
  %488 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %19, i32 0, i32 0, i32 0
  %489 = load float addrspace(1)* %488, align 4, !tbaa !36
  %490 = insertelement <3 x float> undef, float %489, i32 0
  %491 = getelementptr inbounds float addrspace(1)* %488, i32 1
  %492 = load float addrspace(1)* %491, align 4, !tbaa !36
  %493 = insertelement <3 x float> %490, float %492, i32 1
  %494 = getelementptr inbounds float addrspace(1)* %488, i32 2
  %495 = load float addrspace(1)* %494, align 4, !tbaa !36
  %496 = insertelement <3 x float> %493, float %495, i32 2
  %497 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  %498 = load float addrspace(1)* %497, align 4, !tbaa !36
  %499 = insertelement <3 x float> undef, float %498, i32 0
  %500 = getelementptr inbounds float addrspace(1)* %497, i32 1
  %501 = load float addrspace(1)* %500, align 4, !tbaa !36
  %502 = insertelement <3 x float> %499, float %501, i32 1
  %503 = getelementptr inbounds float addrspace(1)* %497, i32 2
  %504 = load float addrspace(1)* %503, align 4, !tbaa !36
  %505 = insertelement <3 x float> %502, float %504, i32 2
  %506 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %20, i32 0, i32 0
  %507 = load float addrspace(1)* %506, align 4, !tbaa !37
  %508 = insertelement <3 x float> undef, float %507, i32 0
  %509 = shufflevector <3 x float> %508, <3 x float> undef, <3 x i32> zeroinitializer
  %510 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %509, <3 x float> %505, <3 x float> %496) #2
  %511 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 1, i32 0
  %512 = extractelement <3 x float> %510, i32 0
  store float %512, float addrspace(1)* %511, align 4, !tbaa !36
  %513 = extractelement <3 x float> %510, i32 1
  %514 = getelementptr inbounds float addrspace(1)* %511, i32 1
  store float %513, float addrspace(1)* %514, align 4, !tbaa !36
  %515 = extractelement <3 x float> %510, i32 2
  %516 = getelementptr inbounds float addrspace(1)* %511, i32 2
  store float %515, float addrspace(1)* %516, align 4, !tbaa !36
  %517 = fsub <3 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %505
  %518 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 0, i32 0
  %519 = extractelement <3 x float> %517, i32 0
  store float %519, float addrspace(1)* %518, align 4, !tbaa !36
  %520 = extractelement <3 x float> %517, i32 1
  %521 = getelementptr inbounds float addrspace(1)* %518, i32 1
  store float %520, float addrspace(1)* %521, align 4, !tbaa !36
  %522 = extractelement <3 x float> %517, i32 2
  %523 = getelementptr inbounds float addrspace(1)* %518, i32 2
  store float %522, float addrspace(1)* %523, align 4, !tbaa !36
  %524 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 4
  %525 = load i32 addrspace(1)* %524, align 4, !tbaa !38
  %526 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 0
  %527 = load i32 addrspace(1)* %526, align 4, !tbaa !39
  %528 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 5
  %529 = load i32 addrspace(1)* %528, align 4, !tbaa !43
  %530 = getelementptr inbounds i32 addrspace(1)* %meshMats, i32 %22
  %531 = load i32 addrspace(1)* %530, align 4, !tbaa !44
  %532 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 1
  store i32 %531, i32 addrspace(1)* %532, align 4, !tbaa !45
  %533 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 1
  %534 = load float addrspace(1)* %533, align 4, !tbaa !46
  %535 = getelementptr inbounds %struct.RayHit.96 addrspace(1)* %rayHits, i32 %2, i32 2
  %536 = load float addrspace(1)* %535, align 4, !tbaa !47
  %.sum.i5 = add i32 %529, %525
  %537 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i5, i32 0, i32 0
  %538 = load i32 addrspace(1)* %537, align 4, !tbaa !44
  %.sum1.i6 = add i32 %538, %527
  %539 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum1.i6, i32 0
  %540 = load float addrspace(1)* %539, align 4, !tbaa !36
  %541 = insertelement <3 x float> undef, float %540, i32 0
  %542 = getelementptr inbounds float addrspace(1)* %539, i32 1
  %543 = load float addrspace(1)* %542, align 4, !tbaa !36
  %544 = insertelement <3 x float> %541, float %543, i32 1
  %545 = getelementptr inbounds float addrspace(1)* %539, i32 2
  %546 = load float addrspace(1)* %545, align 4, !tbaa !36
  %547 = insertelement <3 x float> %544, float %546, i32 2
  %548 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i5, i32 0, i32 1
  %549 = load i32 addrspace(1)* %548, align 4, !tbaa !44
  %.sum3.i7 = add i32 %549, %527
  %550 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum3.i7, i32 0
  %551 = load float addrspace(1)* %550, align 4, !tbaa !36
  %552 = insertelement <3 x float> undef, float %551, i32 0
  %553 = getelementptr inbounds float addrspace(1)* %550, i32 1
  %554 = load float addrspace(1)* %553, align 4, !tbaa !36
  %555 = insertelement <3 x float> %552, float %554, i32 1
  %556 = getelementptr inbounds float addrspace(1)* %550, i32 2
  %557 = load float addrspace(1)* %556, align 4, !tbaa !36
  %558 = insertelement <3 x float> %555, float %557, i32 2
  %559 = getelementptr inbounds %struct.Triangle.75 addrspace(1)* %triangles, i32 %.sum.i5, i32 0, i32 2
  %560 = load i32 addrspace(1)* %559, align 4, !tbaa !44
  %.sum5.i8 = add i32 %560, %527
  %561 = getelementptr inbounds %struct.Point.68 addrspace(1)* %vertices, i32 %.sum5.i8, i32 0
  %562 = load float addrspace(1)* %561, align 4, !tbaa !36
  %563 = insertelement <3 x float> undef, float %562, i32 0
  %564 = getelementptr inbounds float addrspace(1)* %561, i32 1
  %565 = load float addrspace(1)* %564, align 4, !tbaa !36
  %566 = insertelement <3 x float> %563, float %565, i32 1
  %567 = getelementptr inbounds float addrspace(1)* %561, i32 2
  %568 = load float addrspace(1)* %567, align 4, !tbaa !36
  %569 = insertelement <3 x float> %566, float %568, i32 2
  %570 = fsub <3 x float> %558, %547
  %571 = fsub <3 x float> %569, %547
  %572 = extractelement <3 x float> %570, i32 1
  %573 = extractelement <3 x float> %571, i32 2
  %574 = extractelement <3 x float> %570, i32 2
  %575 = extractelement <3 x float> %571, i32 1
  %576 = fmul float %574, %575
  %577 = fsub float -0.000000e+00, %576
  %578 = tail call float @llvm.fmuladd.f32(float %572, float %573, float %577) #2
  %579 = insertelement <3 x float> undef, float %578, i32 0
  %580 = extractelement <3 x float> %571, i32 0
  %581 = extractelement <3 x float> %570, i32 0
  %582 = fmul float %581, %573
  %583 = fsub float -0.000000e+00, %582
  %584 = tail call float @llvm.fmuladd.f32(float %574, float %580, float %583) #2
  %585 = insertelement <3 x float> %579, float %584, i32 1
  %586 = fmul float %572, %580
  %587 = fsub float -0.000000e+00, %586
  %588 = tail call float @llvm.fmuladd.f32(float %581, float %575, float %587) #2
  %589 = insertelement <3 x float> %585, float %588, i32 2
  %590 = fmul float %584, %584
  %591 = tail call float @llvm.fmuladd.f32(float %578, float %578, float %590) #2
  %592 = tail call float @llvm.fmuladd.f32(float %588, float %588, float %591) #2
  %593 = tail call float @llvm.sqrt.f32(float %592) #3
  %594 = insertelement <3 x float> undef, float %593, i32 0
  %595 = shufflevector <3 x float> %594, <3 x float> undef, <3 x i32> zeroinitializer
  %596 = fdiv <3 x float> %589, %595, !fpmath !48
  %597 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 0
  %598 = load float addrspace(1)* %597, align 4, !tbaa !36
  %599 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 0
  %600 = load float addrspace(1)* %599, align 4, !tbaa !36
  %601 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 0
  %602 = load float addrspace(1)* %601, align 4, !tbaa !36
  %603 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 1
  %604 = load float addrspace(1)* %603, align 4, !tbaa !36
  %605 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 1
  %606 = load float addrspace(1)* %605, align 4, !tbaa !36
  %607 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 1
  %608 = load float addrspace(1)* %607, align 4, !tbaa !36
  %609 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 0, i32 2
  %610 = load float addrspace(1)* %609, align 4, !tbaa !36
  %611 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 1, i32 2
  %612 = load float addrspace(1)* %611, align 4, !tbaa !36
  %613 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 6, i32 1, i32 0, i32 2, i32 2
  %614 = load float addrspace(1)* %613, align 4, !tbaa !36
  %615 = extractelement <3 x float> %596, i32 0
  %616 = extractelement <3 x float> %596, i32 1
  %617 = fmul float %616, %600
  %618 = tail call float @llvm.fmuladd.f32(float %598, float %615, float %617) #2
  %619 = extractelement <3 x float> %596, i32 2
  %620 = tail call float @llvm.fmuladd.f32(float %602, float %619, float %618) #2
  %621 = insertelement <3 x float> undef, float %620, i32 0
  %622 = fmul float %616, %606
  %623 = tail call float @llvm.fmuladd.f32(float %604, float %615, float %622) #2
  %624 = tail call float @llvm.fmuladd.f32(float %608, float %619, float %623) #2
  %625 = insertelement <3 x float> %621, float %624, i32 1
  %626 = fmul float %616, %612
  %627 = tail call float @llvm.fmuladd.f32(float %610, float %615, float %626) #2
  %628 = tail call float @llvm.fmuladd.f32(float %614, float %619, float %627) #2
  %629 = insertelement <3 x float> %625, float %628, i32 2
  %630 = fmul float %624, %624
  %631 = tail call float @llvm.fmuladd.f32(float %620, float %620, float %630) #2
  %632 = tail call float @llvm.fmuladd.f32(float %628, float %628, float %631) #2
  %633 = tail call float @llvm.sqrt.f32(float %632) #3
  %634 = insertelement <3 x float> undef, float %633, i32 0
  %635 = shufflevector <3 x float> %634, <3 x float> undef, <3 x i32> zeroinitializer
  %636 = fdiv <3 x float> %629, %635, !fpmath !48
  %637 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 3, i32 0
  %638 = extractelement <3 x float> %636, i32 0
  store float %638, float addrspace(1)* %637, align 4, !tbaa !36
  %639 = extractelement <3 x float> %636, i32 1
  %640 = getelementptr inbounds float addrspace(1)* %637, i32 1
  store float %639, float addrspace(1)* %640, align 4, !tbaa !36
  %641 = extractelement <3 x float> %636, i32 2
  %642 = getelementptr inbounds float addrspace(1)* %637, i32 2
  store float %641, float addrspace(1)* %642, align 4, !tbaa !36
  %643 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 1
  %644 = load i32 addrspace(1)* %643, align 4, !tbaa !49
  %645 = icmp eq i32 %644, -1
  br i1 %645, label %728, label %646

; <label>:646                                     ; preds = %484
  %647 = load i32 addrspace(1)* %537, align 4, !tbaa !44
  %.sum6.i9 = add i32 %647, %644
  %648 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum6.i9, i32 0
  %649 = load float addrspace(1)* %648, align 4, !tbaa !36
  %650 = insertelement <3 x float> undef, float %649, i32 0
  %651 = getelementptr inbounds float addrspace(1)* %648, i32 1
  %652 = load float addrspace(1)* %651, align 4, !tbaa !36
  %653 = insertelement <3 x float> %650, float %652, i32 1
  %654 = getelementptr inbounds float addrspace(1)* %648, i32 2
  %655 = load float addrspace(1)* %654, align 4, !tbaa !36
  %656 = insertelement <3 x float> %653, float %655, i32 2
  %657 = load i32 addrspace(1)* %548, align 4, !tbaa !44
  %.sum7.i10 = add i32 %657, %644
  %658 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum7.i10, i32 0
  %659 = load float addrspace(1)* %658, align 4, !tbaa !36
  %660 = insertelement <3 x float> undef, float %659, i32 0
  %661 = getelementptr inbounds float addrspace(1)* %658, i32 1
  %662 = load float addrspace(1)* %661, align 4, !tbaa !36
  %663 = insertelement <3 x float> %660, float %662, i32 1
  %664 = getelementptr inbounds float addrspace(1)* %658, i32 2
  %665 = load float addrspace(1)* %664, align 4, !tbaa !36
  %666 = insertelement <3 x float> %663, float %665, i32 2
  %.sum8.i11 = add i32 %644, %560
  %667 = getelementptr inbounds %struct.Vector.69 addrspace(1)* %vertNormals, i32 %.sum8.i11, i32 0
  %668 = load float addrspace(1)* %667, align 4, !tbaa !36
  %669 = insertelement <3 x float> undef, float %668, i32 0
  %670 = getelementptr inbounds float addrspace(1)* %667, i32 1
  %671 = load float addrspace(1)* %670, align 4, !tbaa !36
  %672 = insertelement <3 x float> %669, float %671, i32 1
  %673 = getelementptr inbounds float addrspace(1)* %667, i32 2
  %674 = load float addrspace(1)* %673, align 4, !tbaa !36
  %675 = insertelement <3 x float> %672, float %674, i32 2
  %676 = fsub float 1.000000e+00, %534
  %677 = fsub float %676, %536
  %678 = insertelement <3 x float> undef, float %677, i32 0
  %679 = shufflevector <3 x float> %678, <3 x float> undef, <3 x i32> zeroinitializer
  %680 = insertelement <3 x float> undef, float %534, i32 0
  %681 = shufflevector <3 x float> %680, <3 x float> undef, <3 x i32> zeroinitializer
  %682 = fmul <3 x float> %681, %666
  %683 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %679, <3 x float> %656, <3 x float> %682) #2
  %684 = insertelement <3 x float> undef, float %536, i32 0
  %685 = shufflevector <3 x float> %684, <3 x float> undef, <3 x i32> zeroinitializer
  %686 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %685, <3 x float> %675, <3 x float> %683) #2
  %687 = extractelement <3 x float> %686, i32 0
  %688 = extractelement <3 x float> %686, i32 1
  %689 = fmul float %688, %688
  %690 = tail call float @llvm.fmuladd.f32(float %687, float %687, float %689) #2
  %691 = extractelement <3 x float> %686, i32 2
  %692 = tail call float @llvm.fmuladd.f32(float %691, float %691, float %690) #2
  %693 = tail call float @llvm.sqrt.f32(float %692) #3
  %694 = insertelement <3 x float> undef, float %693, i32 0
  %695 = shufflevector <3 x float> %694, <3 x float> undef, <3 x i32> zeroinitializer
  %696 = fdiv <3 x float> %686, %695, !fpmath !48
  %697 = load float addrspace(1)* %597, align 4, !tbaa !36
  %698 = load float addrspace(1)* %599, align 4, !tbaa !36
  %699 = load float addrspace(1)* %601, align 4, !tbaa !36
  %700 = load float addrspace(1)* %603, align 4, !tbaa !36
  %701 = load float addrspace(1)* %605, align 4, !tbaa !36
  %702 = load float addrspace(1)* %607, align 4, !tbaa !36
  %703 = load float addrspace(1)* %609, align 4, !tbaa !36
  %704 = load float addrspace(1)* %611, align 4, !tbaa !36
  %705 = load float addrspace(1)* %613, align 4, !tbaa !36
  %706 = extractelement <3 x float> %696, i32 0
  %707 = extractelement <3 x float> %696, i32 1
  %708 = fmul float %707, %698
  %709 = tail call float @llvm.fmuladd.f32(float %697, float %706, float %708) #2
  %710 = extractelement <3 x float> %696, i32 2
  %711 = tail call float @llvm.fmuladd.f32(float %699, float %710, float %709) #2
  %712 = insertelement <3 x float> undef, float %711, i32 0
  %713 = fmul float %707, %701
  %714 = tail call float @llvm.fmuladd.f32(float %700, float %706, float %713) #2
  %715 = tail call float @llvm.fmuladd.f32(float %702, float %710, float %714) #2
  %716 = insertelement <3 x float> %712, float %715, i32 1
  %717 = fmul float %707, %704
  %718 = tail call float @llvm.fmuladd.f32(float %703, float %706, float %717) #2
  %719 = tail call float @llvm.fmuladd.f32(float %705, float %710, float %718) #2
  %720 = insertelement <3 x float> %716, float %719, i32 2
  %721 = fmul float %715, %715
  %722 = tail call float @llvm.fmuladd.f32(float %711, float %711, float %721) #2
  %723 = tail call float @llvm.fmuladd.f32(float %719, float %719, float %722) #2
  %724 = tail call float @llvm.sqrt.f32(float %723) #3
  %725 = insertelement <3 x float> undef, float %724, i32 0
  %726 = shufflevector <3 x float> %725, <3 x float> undef, <3 x i32> zeroinitializer
  %727 = fdiv <3 x float> %720, %726, !fpmath !48
  br label %728

; <label>:728                                     ; preds = %646, %484
  %.sink.i12 = phi <3 x float> [ %727, %646 ], [ %636, %484 ]
  %729 = getelementptr inbounds %struct.Mesh.95 addrspace(1)* %meshDescs, i32 %22, i32 2
  %730 = load i32 addrspace(1)* %729, align 4, !tbaa !50
  %731 = icmp eq i32 %730, -1
  br i1 %731, label %764, label %732

; <label>:732                                     ; preds = %728
  %733 = load i32 addrspace(1)* %537, align 4, !tbaa !44
  %.sum9.i13 = add i32 %733, %730
  %734 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum9.i13, i32 0
  %735 = load float addrspace(1)* %734, align 4, !tbaa !36
  %736 = insertelement <2 x float> undef, float %735, i32 0
  %737 = getelementptr inbounds float addrspace(1)* %734, i32 1
  %738 = load float addrspace(1)* %737, align 4, !tbaa !36
  %739 = insertelement <2 x float> %736, float %738, i32 1
  %740 = load i32 addrspace(1)* %548, align 4, !tbaa !44
  %.sum10.i14 = add i32 %740, %730
  %741 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum10.i14, i32 0
  %742 = load float addrspace(1)* %741, align 4, !tbaa !36
  %743 = insertelement <2 x float> undef, float %742, i32 0
  %744 = getelementptr inbounds float addrspace(1)* %741, i32 1
  %745 = load float addrspace(1)* %744, align 4, !tbaa !36
  %746 = insertelement <2 x float> %743, float %745, i32 1
  %.sum11.i15 = add i32 %730, %560
  %747 = getelementptr inbounds %struct.UV.76 addrspace(1)* %vertUVs, i32 %.sum11.i15, i32 0
  %748 = load float addrspace(1)* %747, align 4, !tbaa !36
  %749 = insertelement <2 x float> undef, float %748, i32 0
  %750 = getelementptr inbounds float addrspace(1)* %747, i32 1
  %751 = load float addrspace(1)* %750, align 4, !tbaa !36
  %752 = insertelement <2 x float> %749, float %751, i32 1
  %753 = fsub float 1.000000e+00, %534
  %754 = fsub float %753, %536
  %755 = insertelement <2 x float> undef, float %754, i32 0
  %756 = shufflevector <2 x float> %755, <2 x float> undef, <2 x i32> zeroinitializer
  %757 = insertelement <2 x float> undef, float %534, i32 0
  %758 = shufflevector <2 x float> %757, <2 x float> undef, <2 x i32> zeroinitializer
  %759 = fmul <2 x float> %758, %746
  %760 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %756, <2 x float> %739, <2 x float> %759) #2
  %761 = insertelement <2 x float> undef, float %536, i32 0
  %762 = shufflevector <2 x float> %761, <2 x float> undef, <2 x i32> zeroinitializer
  %763 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %762, <2 x float> %752, <2 x float> %760) #2
  br label %764

; <label>:764                                     ; preds = %732, %728
  %hitPointUV.0.i16 = phi <2 x float> [ %763, %732 ], [ zeroinitializer, %728 ]
  %765 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 2, i32 0
  %766 = extractelement <2 x float> %hitPointUV.0.i16, i32 0
  store float %766, float addrspace(1)* %765, align 4, !tbaa !36
  %767 = extractelement <2 x float> %hitPointUV.0.i16, i32 1
  %768 = getelementptr inbounds float addrspace(1)* %765, i32 1
  store float %767, float addrspace(1)* %768, align 4, !tbaa !36
  %769 = getelementptr inbounds i32 addrspace(1)* %meshTriLightDefsOffset, i32 %22
  %770 = load i32 addrspace(1)* %769, align 4, !tbaa !44
  %771 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 2
  store i32 %770, i32 addrspace(1)* %771, align 4, !tbaa !51
  %772 = extractelement <3 x float> %.sink.i12, i32 0
  %773 = tail call float @llvm.fabs.f32(float %772) #2
  %774 = extractelement <3 x float> %.sink.i12, i32 1
  %775 = tail call float @llvm.fabs.f32(float %774) #2
  %776 = fcmp ogt float %773, %775
  %777 = extractelement <3 x float> %.sink.i12, i32 2
  %778 = fmul float %777, %777
  br i1 %776, label %779, label %790

; <label>:779                                     ; preds = %764
  %780 = tail call float @llvm.fmuladd.f32(float %772, float %772, float %778) #2
  %781 = tail call float @llvm.sqrt.f32(float %780) #2
  %782 = fdiv float 1.000000e+00, %781, !fpmath !48
  %783 = fmul float %777, %782
  %784 = fsub float -0.000000e+00, %783
  %785 = insertelement <3 x float> undef, float %784, i32 0
  %786 = insertelement <3 x float> %785, float 0.000000e+00, i32 1
  %787 = shufflevector <3 x float> %786, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %788 = fmul float %772, %782
  %789 = insertelement <3 x float> %786, float %788, i32 2
  br label %BSDF_Init.exit18

; <label>:790                                     ; preds = %764
  %791 = tail call float @llvm.fmuladd.f32(float %774, float %774, float %778) #2
  %792 = tail call float @llvm.sqrt.f32(float %791) #2
  %793 = fdiv float 1.000000e+00, %792, !fpmath !48
  %794 = fmul float %777, %793
  %795 = insertelement <3 x float> <float 0.000000e+00, float undef, float undef>, float %794, i32 1
  %796 = fmul float %774, %793
  %797 = fsub float -0.000000e+00, %796
  %798 = insertelement <3 x float> %795, float %797, i32 2
  br label %BSDF_Init.exit18

BSDF_Init.exit18:                                 ; preds = %779, %790
  %799 = phi <4 x float> [ undef, %790 ], [ %787, %779 ]
  %storemerge.i.i.i17 = phi <3 x float> [ %798, %790 ], [ %789, %779 ]
  %800 = shufflevector <3 x float> %storemerge.i.i.i17, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %801 = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> %800, <4 x float> %799
  %802 = extractelement <4 x float> %801, i32 2
  %803 = extractelement <4 x float> %801, i32 1
  %804 = fmul float %777, %803
  %805 = fsub float -0.000000e+00, %804
  %806 = tail call float @llvm.fmuladd.f32(float %774, float %802, float %805) #2
  %807 = extractelement <4 x float> %801, i32 0
  %808 = fmul float %772, %802
  %809 = fsub float -0.000000e+00, %808
  %810 = tail call float @llvm.fmuladd.f32(float %777, float %807, float %809) #2
  %811 = fmul float %774, %807
  %812 = fsub float -0.000000e+00, %811
  %813 = tail call float @llvm.fmuladd.f32(float %772, float %803, float %812) #2
  %814 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 3, i32 0, i32 0
  store float %807, float addrspace(1)* %814, align 4, !tbaa !36
  %815 = getelementptr inbounds float addrspace(1)* %814, i32 1
  store float %803, float addrspace(1)* %815, align 4, !tbaa !36
  %816 = getelementptr inbounds float addrspace(1)* %814, i32 2
  store float %802, float addrspace(1)* %816, align 4, !tbaa !36
  %817 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 3, i32 1, i32 0
  store float %806, float addrspace(1)* %817, align 4, !tbaa !36
  %818 = getelementptr inbounds float addrspace(1)* %817, i32 1
  store float %810, float addrspace(1)* %818, align 4, !tbaa !36
  %819 = getelementptr inbounds float addrspace(1)* %817, i32 2
  store float %813, float addrspace(1)* %819, align 4, !tbaa !36
  %820 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 3, i32 2, i32 0
  store float %772, float addrspace(1)* %820, align 4, !tbaa !36
  %821 = getelementptr inbounds float addrspace(1)* %820, i32 1
  store float %774, float addrspace(1)* %821, align 4, !tbaa !36
  %822 = getelementptr inbounds float addrspace(1)* %820, i32 2
  store float %777, float addrspace(1)* %822, align 4, !tbaa !36
  %823 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 1, i32 0, i32 4, i32 0
  store float %772, float addrspace(1)* %823, align 4, !tbaa !36
  %824 = getelementptr inbounds float addrspace(1)* %823, i32 1
  store float %774, float addrspace(1)* %824, align 4, !tbaa !36
  %825 = getelementptr inbounds float addrspace(1)* %823, i32 2
  store float %777, float addrspace(1)* %825, align 4, !tbaa !36
  br label %.thread18

.thread16:                                        ; preds = %..thread16_crit_edge, %432, %BSDF_GetEmittedRadiance.exit, %BSDF_Init.exit
  %.pre-phi = phi i32 addrspace(1)* [ %.pre, %..thread16_crit_edge ], [ %69, %432 ], [ %69, %BSDF_GetEmittedRadiance.exit ], [ %69, %BSDF_Init.exit ]
  %826 = load i32 addrspace(1)* %.pre-phi, align 4, !tbaa !45
  %827 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %826, i32 0
  %828 = load i32 addrspace(1)* %827, align 4, !tbaa !65
  %not.cond.i.i.i = icmp eq i32 %828, 0
  br i1 %not.cond.i.i.i, label %829, label %.thread18

; <label>:829                                     ; preds = %.thread16
  %830 = shl i32 %14, 12
  %831 = and i32 %830, -8192
  %832 = shl i32 %14, 13
  %833 = xor i32 %832, %14
  %834 = lshr i32 %833, 19
  %835 = or i32 %834, %831
  %836 = shl i32 %16, 4
  %837 = and i32 %836, -128
  %838 = shl i32 %16, 2
  %839 = xor i32 %838, %16
  %840 = lshr i32 %839, 25
  %841 = or i32 %840, %837
  %842 = shl i32 %18, 17
  %843 = and i32 %842, -2097152
  %844 = shl i32 %18, 3
  %845 = xor i32 %844, %18
  %846 = lshr i32 %845, 11
  %847 = or i32 %846, %843
  %848 = xor i32 %841, %835
  %849 = xor i32 %848, %847
  %850 = zext i32 %849 to i64
  %851 = and i64 %850, 16777215
  %852 = uitofp i64 %851 to float
  %853 = fmul float %852, 0x3E70000000000000
  %854 = fmul float %853, 4.000000e+00
  %855 = tail call float @llvm.floor.f32(float %854)
  %856 = fptoui float %855 to i32
  %857 = icmp ult i32 %856, 3
  %858 = select i1 %857, i32 %856, i32 3
  %859 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 1, i32 0
  %860 = load float addrspace(1)* %859, align 4, !tbaa !36
  %861 = insertelement <3 x float> undef, float %860, i32 0
  %862 = getelementptr inbounds float addrspace(1)* %859, i32 1
  %863 = load float addrspace(1)* %862, align 4, !tbaa !36
  %864 = insertelement <3 x float> %861, float %863, i32 1
  %865 = getelementptr inbounds float addrspace(1)* %859, i32 2
  %866 = load float addrspace(1)* %865, align 4, !tbaa !36
  %867 = insertelement <3 x float> %864, float %866, i32 2
  %868 = shl i32 %835, 12
  %869 = and i32 %868, -8192
  %870 = shl i32 %835, 13
  %871 = xor i32 %870, %830
  %872 = lshr i32 %871, 19
  %873 = or i32 %872, %869
  %874 = shl i32 %841, 4
  %875 = and i32 %874, -128
  %876 = shl i32 %16, 6
  %877 = xor i32 %876, %836
  %878 = lshr i32 %877, 25
  %879 = or i32 %875, %878
  %880 = shl i32 %846, 17
  %881 = and i32 %880, -2097152
  %882 = shl i32 %847, 3
  %883 = xor i32 %882, %847
  %884 = lshr i32 %883, 11
  %885 = or i32 %884, %881
  %886 = xor i32 %879, %873
  %887 = xor i32 %886, %885
  %888 = zext i32 %887 to i64
  %889 = and i64 %888, 16777215
  %890 = uitofp i64 %889 to float
  %891 = fmul float %890, 0x3E70000000000000
  %892 = shl i32 %873, 12
  %893 = and i32 %892, -8192
  %894 = shl i32 %873, 13
  %895 = xor i32 %894, %868
  %896 = lshr i32 %895, 19
  %897 = or i32 %896, %893
  %898 = shl i32 %879, 4
  %899 = and i32 %898, -128
  %900 = shl i32 %16, 10
  %901 = xor i32 %874, %900
  %902 = lshr i32 %901, 25
  %903 = or i32 %899, %902
  %904 = shl i32 %884, 17
  %905 = and i32 %904, -2097152
  %906 = shl i32 %885, 3
  %907 = xor i32 %906, %885
  %908 = lshr i32 %907, 11
  %909 = or i32 %908, %905
  %910 = xor i32 %897, %903
  %911 = xor i32 %910, %909
  %912 = zext i32 %911 to i64
  %913 = and i64 %912, 16777215
  %914 = uitofp i64 %913 to float
  %915 = fmul float %914, 0x3E70000000000000
  %916 = shl i32 %897, 12
  %917 = and i32 %916, -8192
  %918 = shl i32 %897, 13
  %919 = xor i32 %918, %892
  %920 = lshr i32 %919, 19
  %921 = or i32 %920, %917
  %922 = shl i32 %903, 4
  %923 = and i32 %922, -128
  %924 = shl i32 %16, 14
  %925 = xor i32 %898, %924
  %926 = lshr i32 %925, 25
  %927 = or i32 %923, %926
  %928 = shl i32 %908, 17
  %929 = and i32 %928, -2097152
  %930 = shl i32 %909, 3
  %931 = xor i32 %930, %909
  %932 = lshr i32 %931, 11
  %933 = or i32 %932, %929
  %934 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 0, i32 0
  %935 = load float addrspace(1)* %934, align 4, !tbaa !36
  %936 = insertelement <3 x float> undef, float %935, i32 0
  %937 = getelementptr inbounds float addrspace(1)* %934, i32 1
  %938 = load float addrspace(1)* %937, align 4, !tbaa !36
  %939 = insertelement <3 x float> %936, float %938, i32 1
  %940 = getelementptr inbounds float addrspace(1)* %934, i32 2
  %941 = load float addrspace(1)* %940, align 4, !tbaa !36
  %942 = insertelement <3 x float> %939, float %941, i32 2
  %943 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 1, i32 0
  %944 = load float addrspace(1)* %943, align 4, !tbaa !36
  %945 = insertelement <3 x float> undef, float %944, i32 0
  %946 = getelementptr inbounds float addrspace(1)* %943, i32 1
  %947 = load float addrspace(1)* %946, align 4, !tbaa !36
  %948 = insertelement <3 x float> %945, float %947, i32 1
  %949 = getelementptr inbounds float addrspace(1)* %943, i32 2
  %950 = load float addrspace(1)* %949, align 4, !tbaa !36
  %951 = insertelement <3 x float> %948, float %950, i32 2
  %952 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 2, i32 0
  %953 = load float addrspace(1)* %952, align 4, !tbaa !36
  %954 = insertelement <3 x float> undef, float %953, i32 0
  %955 = getelementptr inbounds float addrspace(1)* %952, i32 1
  %956 = load float addrspace(1)* %955, align 4, !tbaa !36
  %957 = insertelement <3 x float> %954, float %956, i32 1
  %958 = getelementptr inbounds float addrspace(1)* %952, i32 2
  %959 = load float addrspace(1)* %958, align 4, !tbaa !36
  %960 = insertelement <3 x float> %957, float %959, i32 2
  %961 = tail call float @llvm.sqrt.f32(float %891) #2
  %962 = fsub float 1.000000e+00, %961
  %963 = fmul float %915, %961
  %964 = fsub float 1.000000e+00, %962
  %965 = fsub float %964, %963
  %966 = insertelement <3 x float> undef, float %965, i32 0
  %967 = shufflevector <3 x float> %966, <3 x float> undef, <3 x i32> zeroinitializer
  %968 = insertelement <3 x float> undef, float %962, i32 0
  %969 = shufflevector <3 x float> %968, <3 x float> undef, <3 x i32> zeroinitializer
  %970 = fmul <3 x float> %951, %969
  %971 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %967, <3 x float> %942, <3 x float> %970) #2
  %972 = insertelement <3 x float> undef, float %963, i32 0
  %973 = shufflevector <3 x float> %972, <3 x float> undef, <3 x i32> zeroinitializer
  %974 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %973, <3 x float> %960, <3 x float> %971) #2
  %975 = fsub <3 x float> %951, %942
  %976 = fsub <3 x float> %960, %942
  %977 = extractelement <3 x float> %975, i32 1
  %978 = extractelement <3 x float> %976, i32 2
  %979 = extractelement <3 x float> %975, i32 2
  %980 = extractelement <3 x float> %976, i32 1
  %981 = fmul float %979, %980
  %982 = fsub float -0.000000e+00, %981
  %983 = tail call float @llvm.fmuladd.f32(float %977, float %978, float %982) #2
  %984 = insertelement <3 x float> undef, float %983, i32 0
  %985 = extractelement <3 x float> %976, i32 0
  %986 = extractelement <3 x float> %975, i32 0
  %987 = fmul float %986, %978
  %988 = fsub float -0.000000e+00, %987
  %989 = tail call float @llvm.fmuladd.f32(float %979, float %985, float %988) #2
  %990 = insertelement <3 x float> %984, float %989, i32 1
  %991 = fmul float %977, %985
  %992 = fsub float -0.000000e+00, %991
  %993 = tail call float @llvm.fmuladd.f32(float %986, float %980, float %992) #2
  %994 = insertelement <3 x float> %990, float %993, i32 2
  %995 = fmul float %989, %989
  %996 = tail call float @llvm.fmuladd.f32(float %983, float %983, float %995) #2
  %997 = tail call float @llvm.fmuladd.f32(float %993, float %993, float %996) #2
  %998 = tail call float @llvm.sqrt.f32(float %997) #3
  %999 = insertelement <3 x float> undef, float %998, i32 0
  %1000 = shufflevector <3 x float> %999, <3 x float> undef, <3 x i32> zeroinitializer
  %1001 = fdiv <3 x float> %994, %1000, !fpmath !48
  %1002 = fsub <3 x float> %974, %867
  %1003 = extractelement <3 x float> %1002, i32 0
  %1004 = extractelement <3 x float> %1002, i32 1
  %1005 = fmul float %1004, %1004
  %1006 = tail call float @llvm.fmuladd.f32(float %1003, float %1003, float %1005) #2
  %1007 = extractelement <3 x float> %1002, i32 2
  %1008 = tail call float @llvm.fmuladd.f32(float %1007, float %1007, float %1006) #2
  %1009 = tail call float @llvm.sqrt.f32(float %1008) #2
  %1010 = insertelement <3 x float> undef, float %1009, i32 0
  %1011 = shufflevector <3 x float> %1010, <3 x float> undef, <3 x i32> zeroinitializer
  %1012 = fdiv <3 x float> %1002, %1011, !fpmath !48
  %1013 = fsub <3 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %1012
  %1014 = extractelement <3 x float> %1001, i32 0
  %1015 = extractelement <3 x float> %1013, i32 0
  %1016 = extractelement <3 x float> %1001, i32 1
  %1017 = extractelement <3 x float> %1013, i32 1
  %1018 = fmul float %1016, %1017
  %1019 = tail call float @llvm.fmuladd.f32(float %1014, float %1015, float %1018) #2
  %1020 = extractelement <3 x float> %1001, i32 2
  %1021 = extractelement <3 x float> %1013, i32 2
  %1022 = tail call float @llvm.fmuladd.f32(float %1020, float %1021, float %1019) #2
  %1023 = fcmp olt float %1022, 0x3F1A36E2E0000000
  br i1 %1023, label %TriangleLight_Illuminate.exit, label %1024

; <label>:1024                                    ; preds = %829
  %1025 = xor i32 %921, %927
  %1026 = xor i32 %1025, %933
  %1027 = zext i32 %1026 to i64
  %1028 = and i64 %1027, 16777215
  %1029 = uitofp i64 %1028 to float
  %1030 = fmul float %1029, 0x3E70000000000000
  %1031 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 6
  %1032 = load float addrspace(1)* %1031, align 4, !tbaa !52
  %1033 = fmul float %1008, %1032
  %1034 = fdiv float %1033, %1022, !fpmath !48
  %1035 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 3, i32 0
  %1036 = load float addrspace(1)* %1035, align 4, !tbaa !36
  %1037 = insertelement <2 x float> undef, float %1036, i32 0
  %1038 = getelementptr inbounds float addrspace(1)* %1035, i32 1
  %1039 = load float addrspace(1)* %1038, align 4, !tbaa !36
  %1040 = insertelement <2 x float> %1037, float %1039, i32 1
  %1041 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 4, i32 0
  %1042 = load float addrspace(1)* %1041, align 4, !tbaa !36
  %1043 = insertelement <2 x float> undef, float %1042, i32 0
  %1044 = getelementptr inbounds float addrspace(1)* %1041, i32 1
  %1045 = load float addrspace(1)* %1044, align 4, !tbaa !36
  %1046 = insertelement <2 x float> %1043, float %1045, i32 1
  %1047 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 5, i32 0
  %1048 = load float addrspace(1)* %1047, align 4, !tbaa !36
  %1049 = insertelement <2 x float> undef, float %1048, i32 0
  %1050 = getelementptr inbounds float addrspace(1)* %1047, i32 1
  %1051 = load float addrspace(1)* %1050, align 4, !tbaa !36
  %1052 = insertelement <2 x float> %1049, float %1051, i32 1
  %1053 = insertelement <2 x float> undef, float %965, i32 0
  %1054 = shufflevector <2 x float> %1053, <2 x float> undef, <2 x i32> zeroinitializer
  %1055 = insertelement <2 x float> undef, float %962, i32 0
  %1056 = shufflevector <2 x float> %1055, <2 x float> undef, <2 x i32> zeroinitializer
  %1057 = fmul <2 x float> %1056, %1046
  %1058 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %1054, <2 x float> %1040, <2 x float> %1057) #2
  %1059 = insertelement <2 x float> undef, float %963, i32 0
  %1060 = shufflevector <2 x float> %1059, <2 x float> undef, <2 x i32> zeroinitializer
  %1061 = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %1060, <2 x float> %1052, <2 x float> %1058) #2
  %1062 = fsub <3 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %1001
  %1063 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 0, i32 0
  %1064 = extractelement <3 x float> %1062, i32 0
  store float %1064, float addrspace(1)* %1063, align 4, !tbaa !36
  %1065 = extractelement <3 x float> %1062, i32 1
  %1066 = getelementptr inbounds float addrspace(1)* %1063, i32 1
  store float %1065, float addrspace(1)* %1066, align 4, !tbaa !36
  %1067 = extractelement <3 x float> %1062, i32 2
  %1068 = getelementptr inbounds float addrspace(1)* %1063, i32 2
  store float %1067, float addrspace(1)* %1068, align 4, !tbaa !36
  %1069 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 1, i32 0
  %1070 = extractelement <3 x float> %974, i32 0
  store float %1070, float addrspace(1)* %1069, align 4, !tbaa !36
  %1071 = extractelement <3 x float> %974, i32 1
  %1072 = getelementptr inbounds float addrspace(1)* %1069, i32 1
  store float %1071, float addrspace(1)* %1072, align 4, !tbaa !36
  %1073 = extractelement <3 x float> %974, i32 2
  %1074 = getelementptr inbounds float addrspace(1)* %1069, i32 2
  store float %1073, float addrspace(1)* %1074, align 4, !tbaa !36
  %1075 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 2, i32 0
  %1076 = extractelement <2 x float> %1061, i32 0
  store float %1076, float addrspace(1)* %1075, align 4, !tbaa !36
  %1077 = extractelement <2 x float> %1061, i32 1
  %1078 = getelementptr inbounds float addrspace(1)* %1075, i32 1
  store float %1077, float addrspace(1)* %1078, align 4, !tbaa !36
  %1079 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 3, i32 0
  store float %1014, float addrspace(1)* %1079, align 4, !tbaa !36
  %1080 = getelementptr inbounds float addrspace(1)* %1079, i32 1
  store float %1016, float addrspace(1)* %1080, align 4, !tbaa !36
  %1081 = getelementptr inbounds float addrspace(1)* %1079, i32 2
  store float %1020, float addrspace(1)* %1081, align 4, !tbaa !36
  %1082 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 4, i32 0
  store float %1014, float addrspace(1)* %1082, align 4, !tbaa !36
  %1083 = getelementptr inbounds float addrspace(1)* %1082, i32 1
  store float %1016, float addrspace(1)* %1083, align 4, !tbaa !36
  %1084 = getelementptr inbounds float addrspace(1)* %1082, i32 2
  store float %1020, float addrspace(1)* %1084, align 4, !tbaa !36
  %1085 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 3, i32 5
  store float %1030, float addrspace(1)* %1085, align 4, !tbaa !66
  %1086 = getelementptr inbounds %struct.TriangleLight.91 addrspace(1)* %triLightDefs, i32 %858, i32 7
  %1087 = load i32 addrspace(1)* %1086, align 4, !tbaa !54
  %1088 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1087, i32 1
  %1089 = load i32 addrspace(1)* %1088, align 4, !tbaa !55
  %1090 = icmp eq i32 %1089, -1
  br i1 %1090, label %TriangleLight_Illuminate.exit, label %1091

; <label>:1091                                    ; preds = %1024
  %1092 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1089, i32 0
  %1093 = load i32 addrspace(1)* %1092, align 4, !tbaa !57
  switch i32 %1093, label %Texture_GetSpectrumValue.exit.i.i.i [
    i32 0, label %1094
    i32 1, label %1100
  ]

; <label>:1094                                    ; preds = %1091
  %1095 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1089, i32 1
  %1096 = bitcast %union.anon.0.85 addrspace(1)* %1095 to float addrspace(1)*
  %1097 = load float addrspace(1)* %1096, align 4, !tbaa !59
  %1098 = insertelement <3 x float> undef, float %1097, i32 0
  %1099 = shufflevector <3 x float> %1098, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %Texture_GetSpectrumValue.exit.i.i.i

; <label>:1100                                    ; preds = %1091
  %1101 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1089, i32 1
  %1102 = bitcast %union.anon.0.85 addrspace(1)* %1101 to float addrspace(1)*
  %1103 = load float addrspace(1)* %1102, align 4, !tbaa !36
  %1104 = insertelement <4 x float> undef, float %1103, i32 0
  %1105 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1089, i32 1, i32 0, i32 1
  %1106 = bitcast i32 addrspace(1)* %1105 to float addrspace(1)*
  %1107 = load float addrspace(1)* %1106, align 4, !tbaa !36
  %1108 = insertelement <4 x float> %1104, float %1107, i32 1
  %1109 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1089, i32 1, i32 0, i32 2, i32 0
  %1110 = load float addrspace(1)* %1109, align 4, !tbaa !36
  %1111 = insertelement <4 x float> %1108, float %1110, i32 2
  br label %Texture_GetSpectrumValue.exit.i.i.i

Texture_GetSpectrumValue.exit.i.i.i:              ; preds = %1100, %1094, %1091
  %1112 = phi <4 x float> [ %1099, %1094 ], [ %1111, %1100 ], [ undef, %1091 ]
  %1113 = shufflevector <4 x float> %1112, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  br label %TriangleLight_Illuminate.exit

TriangleLight_Illuminate.exit:                    ; preds = %829, %1024, %Texture_GetSpectrumValue.exit.i.i.i
  %1114 = phi float [ undef, %829 ], [ %1034, %Texture_GetSpectrumValue.exit.i.i.i ], [ %1034, %1024 ]
  %.0.i4 = phi <3 x float> [ zeroinitializer, %829 ], [ %1113, %Texture_GetSpectrumValue.exit.i.i.i ], [ zeroinitializer, %1024 ]
  %1115 = fcmp oeq <3 x float> %.0.i4, zeroinitializer
  %1116 = sext <3 x i1> %1115 to <3 x i32>
  %1117 = extractelement <3 x i32> %1116, i32 0
  %1118 = extractelement <3 x i32> %1116, i32 1
  %1119 = and i32 %1117, %1118
  %1120 = extractelement <3 x i32> %1116, i32 2
  %1121 = and i32 %1119, %1120
  %1122 = icmp slt i32 %1121, 0
  br i1 %1122, label %.thread18, label %1123

; <label>:1123                                    ; preds = %TriangleLight_Illuminate.exit
  %1124 = getelementptr inbounds %struct.BSDF.94 addrspace(1)* %9, i32 0, i32 0, i32 0, i32 0
  %1125 = load float addrspace(1)* %1124, align 4, !tbaa !36
  %1126 = getelementptr inbounds float addrspace(1)* %1124, i32 1
  %1127 = load float addrspace(1)* %1126, align 4, !tbaa !36
  %1128 = getelementptr inbounds float addrspace(1)* %1124, i32 2
  %1129 = load float addrspace(1)* %1128, align 4, !tbaa !36
  %1130 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 3, i32 0
  %1131 = load float addrspace(1)* %1130, align 4, !tbaa !36
  %1132 = getelementptr inbounds float addrspace(1)* %1130, i32 1
  %1133 = load float addrspace(1)* %1132, align 4, !tbaa !36
  %1134 = getelementptr inbounds float addrspace(1)* %1130, i32 2
  %1135 = load float addrspace(1)* %1134, align 4, !tbaa !36
  %1136 = extractelement <3 x float> %1012, i32 0
  %1137 = extractelement <3 x float> %1012, i32 1
  %1138 = fmul float %1137, %1133
  %1139 = tail call float @llvm.fmuladd.f32(float %1136, float %1131, float %1138) #2
  %1140 = extractelement <3 x float> %1012, i32 2
  %1141 = tail call float @llvm.fmuladd.f32(float %1140, float %1135, float %1139) #2
  %1142 = tail call float @llvm.fabs.f32(float %1141) #2
  %1143 = fmul float %1127, %1133
  %1144 = tail call float @llvm.fmuladd.f32(float %1125, float %1131, float %1143) #2
  %1145 = tail call float @llvm.fmuladd.f32(float %1129, float %1135, float %1144) #2
  %1146 = tail call float @llvm.fabs.f32(float %1145) #2
  %1147 = fcmp olt float %1142, 0x3F1A36E2E0000000
  %1148 = fcmp olt float %1146, 0x3F1A36E2E0000000
  %or.cond.i = or i1 %1147, %1148
  br i1 %or.cond.i, label %BSDF_Evaluate.exit, label %1149

; <label>:1149                                    ; preds = %1123
  %1150 = load i32 addrspace(1)* %.pre-phi, align 4, !tbaa !45
  %1151 = fmul float %1141, %1145
  %1152 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1150, i32 0
  %1153 = load i32 addrspace(1)* %1152, align 4, !tbaa !65
  switch i32 %1153, label %Material_GetEventTypes.exit.i [
    i32 0, label %Material_GetEventTypes.exit.thread.i
    i32 2, label %BSDF_Evaluate.exit
  ]

Material_GetEventTypes.exit.i:                    ; preds = %1149
  %1154 = fcmp ueq float %1151, 0.000000e+00
  %cond.i.i.i = icmp eq i32 %1153, 0
  %or.cond23 = and i1 %1154, %cond.i.i.i
  br i1 %or.cond23, label %Material_GetEventTypes.exit.thread.thread.i.thread, label %BSDF_Evaluate.exit

Material_GetEventTypes.exit.thread.i:             ; preds = %1149
  %.old.i = fcmp olt float %1151, 0.000000e+00
  br i1 %.old.i, label %BSDF_Evaluate.exit, label %Material_GetEventTypes.exit.thread.thread.i.thread

Material_GetEventTypes.exit.thread.thread.i.thread: ; preds = %Material_GetEventTypes.exit.i, %Material_GetEventTypes.exit.thread.i
  %1155 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 2, i32 0
  %1156 = getelementptr inbounds float addrspace(1)* %1155, i32 1
  %1157 = load float addrspace(1)* %1156, align 4, !tbaa !36
  %1158 = fmul float %1137, %1157
  %1159 = getelementptr inbounds float addrspace(1)* %1155, i32 2
  %1160 = load float addrspace(1)* %1155, align 4, !tbaa !36
  %1161 = tail call float @llvm.fmuladd.f32(float %1136, float %1160, float %1158) #2
  %1162 = load float addrspace(1)* %1159, align 4, !tbaa !36
  %1163 = tail call float @llvm.fmuladd.f32(float %1140, float %1162, float %1161) #2
  %1164 = fmul float %1163, 0x3FD45F3060000000
  %1165 = tail call float @llvm.fabs.f32(float %1164) #2
  %1166 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1150, i32 4, i32 0, i32 0
  %1167 = load i32 addrspace(1)* %1166, align 4, !tbaa !67
  %1168 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1167, i32 0
  %1169 = load i32 addrspace(1)* %1168, align 4, !tbaa !57
  switch i32 %1169, label %MatteMaterial_Evaluate.exit.i.i.i [
    i32 0, label %1170
    i32 1, label %1176
  ]

; <label>:1170                                    ; preds = %Material_GetEventTypes.exit.thread.thread.i.thread
  %1171 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1167, i32 1
  %1172 = bitcast %union.anon.0.85 addrspace(1)* %1171 to float addrspace(1)*
  %1173 = load float addrspace(1)* %1172, align 4, !tbaa !59
  %1174 = insertelement <3 x float> undef, float %1173, i32 0
  %1175 = shufflevector <3 x float> %1174, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %MatteMaterial_Evaluate.exit.i.i.i

; <label>:1176                                    ; preds = %Material_GetEventTypes.exit.thread.thread.i.thread
  %1177 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1167, i32 1
  %1178 = bitcast %union.anon.0.85 addrspace(1)* %1177 to float addrspace(1)*
  %1179 = load float addrspace(1)* %1178, align 4, !tbaa !36
  %1180 = insertelement <4 x float> undef, float %1179, i32 0
  %1181 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1167, i32 1, i32 0, i32 1
  %1182 = bitcast i32 addrspace(1)* %1181 to float addrspace(1)*
  %1183 = load float addrspace(1)* %1182, align 4, !tbaa !36
  %1184 = insertelement <4 x float> %1180, float %1183, i32 1
  %1185 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1167, i32 1, i32 0, i32 2, i32 0
  %1186 = load float addrspace(1)* %1185, align 4, !tbaa !36
  %1187 = insertelement <4 x float> %1184, float %1186, i32 2
  br label %MatteMaterial_Evaluate.exit.i.i.i

MatteMaterial_Evaluate.exit.i.i.i:                ; preds = %1176, %1170, %Material_GetEventTypes.exit.thread.thread.i.thread
  %1188 = phi <4 x float> [ %1175, %1170 ], [ %1187, %1176 ], [ undef, %Material_GetEventTypes.exit.thread.thread.i.thread ]
  %1189 = shufflevector <4 x float> %1188, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  %1190 = fcmp ogt <3 x float> %1189, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %1191 = fcmp olt <3 x float> %1189, zeroinitializer
  %.op.i.i.i.i = fmul <3 x float> %1189, <float 0x3FD45F3060000000, float 0x3FD45F3060000000, float 0x3FD45F3060000000>
  %.v.i.i.op.i.i.i.i = select <3 x i1> %1191, <3 x float> zeroinitializer, <3 x float> %.op.i.i.i.i
  %1192 = select <3 x i1> %1190, <3 x float> <float 0x3FD45F3060000000, float 0x3FD45F3060000000, float 0x3FD45F3060000000>, <3 x float> %.v.i.i.op.i.i.i.i
  br label %BSDF_Evaluate.exit

BSDF_Evaluate.exit:                               ; preds = %1149, %1123, %Material_GetEventTypes.exit.i, %Material_GetEventTypes.exit.thread.i, %MatteMaterial_Evaluate.exit.i.i.i
  %1193 = phi float [ undef, %1123 ], [ undef, %Material_GetEventTypes.exit.thread.i ], [ undef, %Material_GetEventTypes.exit.i ], [ %1165, %MatteMaterial_Evaluate.exit.i.i.i ], [ undef, %1149 ]
  %.0.i3 = phi <3 x float> [ zeroinitializer, %1123 ], [ zeroinitializer, %Material_GetEventTypes.exit.thread.i ], [ zeroinitializer, %Material_GetEventTypes.exit.i ], [ %1192, %MatteMaterial_Evaluate.exit.i.i.i ], [ zeroinitializer, %1149 ]
  %1194 = fcmp oeq <3 x float> %.0.i3, zeroinitializer
  %1195 = sext <3 x i1> %1194 to <3 x i32>
  %1196 = extractelement <3 x i32> %1195, i32 0
  %1197 = extractelement <3 x i32> %1195, i32 1
  %1198 = and i32 %1196, %1197
  %1199 = extractelement <3 x i32> %1195, i32 2
  %1200 = and i32 %1198, %1199
  %1201 = icmp slt i32 %1200, 0
  br i1 %1201, label %.thread18, label %1202

; <label>:1202                                    ; preds = %BSDF_Evaluate.exit
  %1203 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 2, i32 0
  %1204 = load float addrspace(1)* %1203, align 4, !tbaa !36
  %1205 = insertelement <3 x float> undef, float %1204, i32 0
  %1206 = getelementptr inbounds float addrspace(1)* %1203, i32 1
  %1207 = load float addrspace(1)* %1206, align 4, !tbaa !36
  %1208 = insertelement <3 x float> %1205, float %1207, i32 1
  %1209 = getelementptr inbounds float addrspace(1)* %1203, i32 2
  %1210 = load float addrspace(1)* %1209, align 4, !tbaa !36
  %1211 = insertelement <3 x float> %1208, float %1210, i32 2
  %1212 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 4, i32 0
  %1213 = load float addrspace(1)* %1212, align 4, !tbaa !36
  %1214 = getelementptr inbounds float addrspace(1)* %1212, i32 1
  %1215 = load float addrspace(1)* %1214, align 4, !tbaa !36
  %1216 = getelementptr inbounds float addrspace(1)* %1212, i32 2
  %1217 = load float addrspace(1)* %1216, align 4, !tbaa !36
  %1218 = fmul float %1137, %1215
  %1219 = tail call float @llvm.fmuladd.f32(float %1136, float %1213, float %1218) #2
  %1220 = tail call float @llvm.fmuladd.f32(float %1140, float %1217, float %1219) #2
  %1221 = tail call float @llvm.fabs.f32(float %1220)
  %1222 = fmul float %1114, 2.500000e-01
  %1223 = fdiv float %1221, %1222, !fpmath !48
  %1224 = icmp ugt i32 %8, 4
  br i1 %1224, label %1225, label %RussianRouletteProb.exit10

; <label>:1225                                    ; preds = %1202
  %1226 = extractelement <3 x float> %.0.i3, i32 0
  %1227 = extractelement <3 x float> %.0.i3, i32 1
  %1228 = extractelement <3 x float> %.0.i3, i32 2
  %1229 = fcmp olt float %1227, %1228
  %1230 = select i1 %1229, float %1228, float %1227
  %1231 = fcmp olt float %1226, %1230
  %1232 = select i1 %1231, float %1230, float %1226
  %1233 = fcmp ogt float %1232, 1.000000e+00
  br i1 %1233, label %RussianRouletteProb.exit10, label %1234

; <label>:1234                                    ; preds = %1225
  %1235 = fcmp olt float %1232, 5.000000e-01
  %1236 = select i1 %1235, float 5.000000e-01, float %1232
  br label %RussianRouletteProb.exit10

RussianRouletteProb.exit10:                       ; preds = %1234, %1225, %1202
  %1237 = phi float [ 1.000000e+00, %1202 ], [ %1236, %1234 ], [ 1.000000e+00, %1225 ]
  %1238 = fmul float %1193, %1237
  %1239 = fmul float %1222, %1222
  %1240 = fmul float %1238, %1238
  %1241 = tail call float @llvm.fmuladd.f32(float %1222, float %1222, float %1240) #2
  %1242 = fdiv float %1239, %1241, !fpmath !48
  %1243 = fmul float %1223, %1242
  %1244 = insertelement <3 x float> undef, float %1243, i32 0
  %1245 = shufflevector <3 x float> %1244, <3 x float> undef, <3 x i32> zeroinitializer
  %1246 = fmul <3 x float> %1211, %1245
  %1247 = fmul <3 x float> %.0.i3, %1246
  %1248 = fmul <3 x float> %.0.i4, %1247
  %1249 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 0, i32 0
  %1250 = extractelement <3 x float> %1248, i32 0
  store float %1250, float addrspace(1)* %1249, align 4, !tbaa !36
  %1251 = extractelement <3 x float> %1248, i32 1
  %1252 = getelementptr inbounds float addrspace(1)* %1249, i32 1
  store float %1251, float addrspace(1)* %1252, align 4, !tbaa !36
  %1253 = extractelement <3 x float> %1248, i32 2
  %1254 = getelementptr inbounds float addrspace(1)* %1249, i32 2
  store float %1253, float addrspace(1)* %1254, align 4, !tbaa !36
  %1255 = shl i32 %921, 12
  %1256 = and i32 %1255, -8192
  %1257 = shl i32 %921, 13
  %1258 = xor i32 %1257, %916
  %1259 = lshr i32 %1258, 19
  %1260 = or i32 %1259, %1256
  %1261 = shl i32 %927, 4
  %1262 = and i32 %1261, -128
  %1263 = shl i32 %16, 18
  %1264 = xor i32 %922, %1263
  %1265 = lshr i32 %1264, 25
  %1266 = or i32 %1262, %1265
  %1267 = shl i32 %932, 17
  %1268 = and i32 %1267, -2097152
  %1269 = shl i32 %933, 3
  %1270 = xor i32 %1269, %933
  %1271 = lshr i32 %1270, 11
  %1272 = or i32 %1271, %1268
  %1273 = xor i32 %1260, %1266
  %1274 = xor i32 %1273, %1272
  %1275 = zext i32 %1274 to i64
  %1276 = and i64 %1275, 16777215
  %1277 = uitofp i64 %1276 to float
  %1278 = fmul float %1277, 0x3E70000000000000
  %1279 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 4, i32 0
  store float %1278, float addrspace(1)* %1279, align 4, !tbaa !63
  %1280 = load float addrspace(1)* %859, align 4, !tbaa !36
  %1281 = load float addrspace(1)* %862, align 4, !tbaa !36
  %1282 = load float addrspace(1)* %865, align 4, !tbaa !36
  %1283 = bitcast float %1280 to i32
  %1284 = add i32 %1283, 128
  %1285 = bitcast i32 %1284 to float
  %1286 = fsub float %1285, %1280
  %1287 = tail call float @llvm.fabs.f32(float %1286) #2
  %1288 = fcmp ogt float %1287, 0x3FB99999A0000000
  br i1 %1288, label %MachineEpsilon_E.exit.i, label %1289

; <label>:1289                                    ; preds = %RussianRouletteProb.exit10
  %1290 = fcmp olt float %1287, 0x3E112E0BE0000000
  %1291 = select i1 %1290, float 0x3E112E0BE0000000, float %1287
  br label %MachineEpsilon_E.exit.i

MachineEpsilon_E.exit.i:                          ; preds = %1289, %RussianRouletteProb.exit10
  %1292 = phi float [ %1291, %1289 ], [ 0x3FB99999A0000000, %RussianRouletteProb.exit10 ]
  %1293 = bitcast float %1281 to i32
  %1294 = add i32 %1293, 128
  %1295 = bitcast i32 %1294 to float
  %1296 = fsub float %1295, %1281
  %1297 = tail call float @llvm.fabs.f32(float %1296) #2
  %1298 = fcmp ogt float %1297, 0x3FB99999A0000000
  br i1 %1298, label %MachineEpsilon_E.exit2.i, label %1299

; <label>:1299                                    ; preds = %MachineEpsilon_E.exit.i
  %1300 = fcmp olt float %1297, 0x3E112E0BE0000000
  %1301 = select i1 %1300, float 0x3E112E0BE0000000, float %1297
  br label %MachineEpsilon_E.exit2.i

MachineEpsilon_E.exit2.i:                         ; preds = %1299, %MachineEpsilon_E.exit.i
  %1302 = phi float [ %1301, %1299 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit.i ]
  %1303 = bitcast float %1282 to i32
  %1304 = add i32 %1303, 128
  %1305 = bitcast i32 %1304 to float
  %1306 = fsub float %1305, %1282
  %1307 = tail call float @llvm.fabs.f32(float %1306) #2
  %1308 = fcmp ogt float %1307, 0x3FB99999A0000000
  br i1 %1308, label %MachineEpsilon_E_Float3.exit, label %1309

; <label>:1309                                    ; preds = %MachineEpsilon_E.exit2.i
  %1310 = fcmp olt float %1307, 0x3E112E0BE0000000
  %1311 = select i1 %1310, float 0x3E112E0BE0000000, float %1307
  br label %MachineEpsilon_E_Float3.exit

MachineEpsilon_E_Float3.exit:                     ; preds = %1309, %MachineEpsilon_E.exit2.i
  %1312 = phi float [ %1311, %1309 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit2.i ]
  %1313 = fcmp olt float %1302, %1312
  %1314 = select i1 %1313, float %1312, float %1302
  %1315 = fcmp olt float %1292, %1314
  %1316 = select i1 %1315, float %1314, float %1292
  %1317 = bitcast float %1009 to i32
  %1318 = add i32 %1317, 128
  %1319 = bitcast i32 %1318 to float
  %1320 = fsub float %1319, %1009
  %1321 = tail call float @llvm.fabs.f32(float %1320) #2
  %1322 = fcmp ogt float %1321, 0x3FB99999A0000000
  br i1 %1322, label %.thread19, label %1323

; <label>:1323                                    ; preds = %MachineEpsilon_E_Float3.exit
  %1324 = fcmp olt float %1321, 0x3E112E0BE0000000
  %1325 = select i1 %1324, float 0x3E112E0BE0000000, float %1321
  br label %.thread19

.thread19:                                        ; preds = %1323, %MachineEpsilon_E_Float3.exit
  %1326 = phi float [ %1325, %1323 ], [ 0x3FB99999A0000000, %MachineEpsilon_E_Float3.exit ]
  %1327 = fcmp olt float %1316, %1326
  %1328 = select i1 %1327, float %1326, float %1316
  %1329 = fsub float %1009, %1328
  %1330 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %19, i32 0, i32 0, i32 0
  store float %1280, float addrspace(1)* %1330, align 4, !tbaa !36
  %1331 = getelementptr inbounds float addrspace(1)* %1330, i32 1
  store float %1281, float addrspace(1)* %1331, align 4, !tbaa !36
  %1332 = getelementptr inbounds float addrspace(1)* %1330, i32 2
  store float %1282, float addrspace(1)* %1332, align 4, !tbaa !36
  %1333 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  store float %1136, float addrspace(1)* %1333, align 4, !tbaa !36
  %1334 = getelementptr inbounds float addrspace(1)* %1333, i32 1
  store float %1137, float addrspace(1)* %1334, align 4, !tbaa !36
  %1335 = getelementptr inbounds float addrspace(1)* %1333, i32 2
  store float %1140, float addrspace(1)* %1335, align 4, !tbaa !36
  %1336 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 2
  store float %1328, float addrspace(1)* %1336, align 4, !tbaa !69
  %1337 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 3
  store float %1329, float addrspace(1)* %1337, align 4, !tbaa !71
  br label %.thread24

.thread18:                                        ; preds = %BSDF_Evaluate.exit, %TriangleLight_Illuminate.exit, %.thread16, %BSDF_Init.exit18, %461, %459
  %1338 = phi i32 [ %933, %BSDF_Evaluate.exit ], [ %933, %TriangleLight_Illuminate.exit ], [ %18, %.thread16 ], [ %18, %BSDF_Init.exit18 ], [ %18, %461 ], [ %18, %459 ]
  %1339 = phi i32 [ %927, %BSDF_Evaluate.exit ], [ %927, %TriangleLight_Illuminate.exit ], [ %16, %.thread16 ], [ %16, %BSDF_Init.exit18 ], [ %16, %461 ], [ %16, %459 ]
  %1340 = phi i32 [ %921, %BSDF_Evaluate.exit ], [ %921, %TriangleLight_Illuminate.exit ], [ %14, %.thread16 ], [ %14, %BSDF_Init.exit18 ], [ %14, %461 ], [ %14, %459 ]
  %1341 = icmp ult i32 %8, 16
  br i1 %1341, label %1342, label %.thread22

; <label>:1342                                    ; preds = %.thread18
  %1343 = shl i32 %1340, 12
  %1344 = and i32 %1343, -8192
  %1345 = shl i32 %1340, 13
  %1346 = xor i32 %1345, %1340
  %1347 = lshr i32 %1346, 19
  %1348 = or i32 %1347, %1344
  %1349 = shl i32 %1339, 4
  %1350 = and i32 %1349, -128
  %1351 = shl i32 %1339, 2
  %1352 = xor i32 %1351, %1339
  %1353 = lshr i32 %1352, 25
  %1354 = or i32 %1353, %1350
  %1355 = shl i32 %1338, 17
  %1356 = and i32 %1355, -2097152
  %1357 = shl i32 %1338, 3
  %1358 = xor i32 %1357, %1338
  %1359 = lshr i32 %1358, 11
  %1360 = or i32 %1359, %1356
  %1361 = xor i32 %1354, %1360
  %1362 = xor i32 %1361, %1348
  %1363 = zext i32 %1362 to i64
  %1364 = and i64 %1363, 16777215
  %1365 = uitofp i64 %1364 to float
  %1366 = fmul float %1365, 0x3E70000000000000
  %1367 = shl i32 %1348, 12
  %1368 = and i32 %1367, -8192
  %1369 = shl i32 %1348, 13
  %1370 = xor i32 %1369, %1343
  %1371 = lshr i32 %1370, 19
  %1372 = or i32 %1371, %1368
  %1373 = shl i32 %1354, 4
  %1374 = and i32 %1373, -128
  %1375 = shl i32 %1339, 6
  %1376 = xor i32 %1375, %1349
  %1377 = lshr i32 %1376, 25
  %1378 = or i32 %1374, %1377
  %1379 = shl i32 %1359, 17
  %1380 = and i32 %1379, -2097152
  %1381 = shl i32 %1360, 3
  %1382 = xor i32 %1381, %1360
  %1383 = lshr i32 %1382, 11
  %1384 = or i32 %1383, %1380
  %1385 = xor i32 %1384, %1378
  %1386 = xor i32 %1385, %1372
  %1387 = zext i32 %1386 to i64
  %1388 = and i64 %1387, 16777215
  %1389 = uitofp i64 %1388 to float
  %1390 = fmul float %1389, 0x3E70000000000000
  %1391 = getelementptr inbounds %struct.BSDF.94 addrspace(1)* %9, i32 0, i32 0, i32 0, i32 0
  %1392 = load float addrspace(1)* %1391, align 4, !tbaa !36
  %1393 = getelementptr inbounds float addrspace(1)* %1391, i32 1
  %1394 = load float addrspace(1)* %1393, align 4, !tbaa !36
  %1395 = getelementptr inbounds float addrspace(1)* %1391, i32 2
  %1396 = load float addrspace(1)* %1395, align 4, !tbaa !36
  %1397 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 0, i32 0
  %1398 = load float addrspace(1)* %1397, align 4, !tbaa !36
  %1399 = getelementptr inbounds float addrspace(1)* %1397, i32 1
  %1400 = load float addrspace(1)* %1399, align 4, !tbaa !36
  %1401 = getelementptr inbounds float addrspace(1)* %1397, i32 2
  %1402 = load float addrspace(1)* %1401, align 4, !tbaa !36
  %1403 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 1, i32 0
  %1404 = load float addrspace(1)* %1403, align 4, !tbaa !36
  %1405 = getelementptr inbounds float addrspace(1)* %1403, i32 1
  %1406 = load float addrspace(1)* %1405, align 4, !tbaa !36
  %1407 = getelementptr inbounds float addrspace(1)* %1403, i32 2
  %1408 = load float addrspace(1)* %1407, align 4, !tbaa !36
  %1409 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 3, i32 2, i32 0
  %1410 = load float addrspace(1)* %1409, align 4, !tbaa !36
  %1411 = getelementptr inbounds float addrspace(1)* %1409, i32 1
  %1412 = load float addrspace(1)* %1411, align 4, !tbaa !36
  %1413 = getelementptr inbounds float addrspace(1)* %1409, i32 2
  %1414 = load float addrspace(1)* %1413, align 4, !tbaa !36
  %1415 = fmul float %1394, %1400
  %1416 = tail call float @llvm.fmuladd.f32(float %1392, float %1398, float %1415) #2
  %1417 = tail call float @llvm.fmuladd.f32(float %1396, float %1402, float %1416) #2
  %1418 = fmul float %1394, %1406
  %1419 = tail call float @llvm.fmuladd.f32(float %1392, float %1404, float %1418) #2
  %1420 = tail call float @llvm.fmuladd.f32(float %1396, float %1408, float %1419) #2
  %1421 = fmul float %1394, %1412
  %1422 = tail call float @llvm.fmuladd.f32(float %1392, float %1410, float %1421) #2
  %1423 = tail call float @llvm.fmuladd.f32(float %1396, float %1414, float %1422) #2
  %1424 = insertelement <3 x float> undef, float %1423, i32 2
  %1425 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 1
  %1426 = load i32 addrspace(1)* %1425, align 4, !tbaa !45
  %1427 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 5
  %1428 = load float addrspace(1)* %1427, align 4, !tbaa !64
  %1429 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 0
  %1430 = load i32 addrspace(1)* %1429, align 4, !tbaa !65
  switch i32 %1430, label %Material_SampleNoMix.exit [
    i32 0, label %1431
    i32 2, label %1517
  ]

; <label>:1431                                    ; preds = %1342
  %1432 = tail call float @llvm.fabs.f32(float %1423) #2
  %1433 = fcmp olt float %1432, 0x3F1A36E2E0000000
  br i1 %1433, label %Material_SampleNoMix.exit, label %1434

; <label>:1434                                    ; preds = %1431
  %1435 = bitcast float %1423 to i32
  %1436 = icmp slt i32 %1435, 0
  %1437 = select i1 %1436, float -1.000000e+00, float 1.000000e+00
  %1438 = insertelement <3 x float> undef, float %1437, i32 0
  %1439 = shufflevector <3 x float> %1438, <3 x float> undef, <3 x i32> zeroinitializer
  %1440 = tail call float @llvm.fmuladd.f32(float 2.000000e+00, float %1366, float -1.000000e+00) #2
  %1441 = tail call float @llvm.fmuladd.f32(float 2.000000e+00, float %1390, float -1.000000e+00) #2
  %1442 = fcmp oeq float %1440, 0.000000e+00
  %1443 = fcmp oeq float %1441, 0.000000e+00
  %or.cond.i.i.i.i = and i1 %1442, %1443
  br i1 %or.cond.i.i.i.i, label %CosineSampleHemisphereWithPdf.exit.i.i, label %1444

; <label>:1444                                    ; preds = %1434
  %1445 = fsub float -0.000000e+00, %1441
  %1446 = fcmp ult float %1440, %1445
  br i1 %1446, label %1457, label %1447

; <label>:1447                                    ; preds = %1444
  %1448 = fcmp ogt float %1440, %1441
  br i1 %1448, label %1449, label %1454

; <label>:1449                                    ; preds = %1447
  %1450 = fcmp ogt float %1441, 0.000000e+00
  %1451 = fdiv float %1441, %1440, !fpmath !48
  br i1 %1450, label %1466, label %1452

; <label>:1452                                    ; preds = %1449
  %1453 = fadd float %1451, 8.000000e+00
  br label %1466

; <label>:1454                                    ; preds = %1447
  %1455 = fdiv float %1440, %1441, !fpmath !48
  %1456 = fsub float 2.000000e+00, %1455
  br label %1466

; <label>:1457                                    ; preds = %1444
  %1458 = fcmp ugt float %1440, %1441
  br i1 %1458, label %1463, label %1459

; <label>:1459                                    ; preds = %1457
  %1460 = fsub float -0.000000e+00, %1440
  %1461 = fdiv float %1441, %1460, !fpmath !48
  %1462 = fsub float 4.000000e+00, %1461
  br label %1466

; <label>:1463                                    ; preds = %1457
  %1464 = fdiv float %1440, %1445, !fpmath !48
  %1465 = fadd float %1464, 6.000000e+00
  br label %1466

; <label>:1466                                    ; preds = %1463, %1459, %1454, %1452, %1449
  %theta.0.i.i.i.i = phi float [ %1453, %1452 ], [ %1456, %1454 ], [ %1462, %1459 ], [ %1465, %1463 ], [ %1451, %1449 ]
  %r.0.i.i.i.i = phi float [ %1440, %1452 ], [ %1441, %1454 ], [ %1460, %1459 ], [ %1445, %1463 ], [ %1440, %1449 ]
  %1467 = fmul float %theta.0.i.i.i.i, 0x3FE921FB60000000
  %1468 = tail call float @llvm.cos.f32(float %1467) #2
  %1469 = fmul float %r.0.i.i.i.i, %1468
  %1470 = tail call float @llvm.sin.f32(float %1467) #2
  %1471 = fmul float %r.0.i.i.i.i, %1470
  br label %CosineSampleHemisphereWithPdf.exit.i.i

CosineSampleHemisphereWithPdf.exit.i.i:           ; preds = %1466, %1434
  %1472 = phi float [ %1469, %1466 ], [ 0.000000e+00, %1434 ]
  %storemerge.i.i.i.i = phi float [ %1471, %1466 ], [ 0.000000e+00, %1434 ]
  %1473 = fsub float -0.000000e+00, %1472
  %1474 = tail call float @llvm.fmuladd.f32(float %1473, float %1472, float 1.000000e+00) #2
  %1475 = fsub float -0.000000e+00, %storemerge.i.i.i.i
  %1476 = tail call float @llvm.fmuladd.f32(float %1475, float %storemerge.i.i.i.i, float %1474) #2
  %1477 = fcmp ogt float %1476, 0.000000e+00
  %1478 = select i1 %1477, float %1476, float 0.000000e+00
  %1479 = tail call float @llvm.sqrt.f32(float %1478) #2
  %1480 = fmul float %1479, 0x3FD45F3060000000
  %1481 = insertelement <3 x float> undef, float %1472, i32 0
  %1482 = insertelement <3 x float> %1481, float %storemerge.i.i.i.i, i32 1
  %1483 = insertelement <3 x float> %1482, float %1479, i32 2
  %1484 = fmul <3 x float> %1439, %1483
  %1485 = shufflevector <3 x float> %1484, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %1486 = extractelement <3 x float> %1484, i32 2
  %1487 = tail call float @llvm.fabs.f32(float %1486) #2
  %1488 = fcmp olt float %1487, 0x3F1A36E2E0000000
  br i1 %1488, label %Material_SampleNoMix.exit, label %1489

; <label>:1489                                    ; preds = %CosineSampleHemisphereWithPdf.exit.i.i
  %1490 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 4, i32 0, i32 0
  %1491 = load i32 addrspace(1)* %1490, align 4, !tbaa !67
  %1492 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1491, i32 0
  %1493 = load i32 addrspace(1)* %1492, align 4, !tbaa !57
  switch i32 %1493, label %Texture_GetSpectrumValue.exit.i.i [
    i32 0, label %1494
    i32 1, label %1500
  ]

; <label>:1494                                    ; preds = %1489
  %1495 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1491, i32 1
  %1496 = bitcast %union.anon.0.85 addrspace(1)* %1495 to float addrspace(1)*
  %1497 = load float addrspace(1)* %1496, align 4, !tbaa !59
  %1498 = insertelement <3 x float> undef, float %1497, i32 0
  %1499 = shufflevector <3 x float> %1498, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %Texture_GetSpectrumValue.exit.i.i

; <label>:1500                                    ; preds = %1489
  %1501 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1491, i32 1
  %1502 = bitcast %union.anon.0.85 addrspace(1)* %1501 to float addrspace(1)*
  %1503 = load float addrspace(1)* %1502, align 4, !tbaa !36
  %1504 = insertelement <4 x float> undef, float %1503, i32 0
  %1505 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1491, i32 1, i32 0, i32 1
  %1506 = bitcast i32 addrspace(1)* %1505 to float addrspace(1)*
  %1507 = load float addrspace(1)* %1506, align 4, !tbaa !36
  %1508 = insertelement <4 x float> %1504, float %1507, i32 1
  %1509 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1491, i32 1, i32 0, i32 2, i32 0
  %1510 = load float addrspace(1)* %1509, align 4, !tbaa !36
  %1511 = insertelement <4 x float> %1508, float %1510, i32 2
  br label %Texture_GetSpectrumValue.exit.i.i

Texture_GetSpectrumValue.exit.i.i:                ; preds = %1500, %1494, %1489
  %1512 = phi <4 x float> [ %1499, %1494 ], [ %1511, %1500 ], [ undef, %1489 ]
  %1513 = shufflevector <4 x float> %1512, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  %1514 = fcmp ogt <3 x float> %1513, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %1515 = fcmp olt <3 x float> %1513, zeroinitializer
  %.op.i.i1 = fmul <3 x float> %1513, <float 0x3FD45F3060000000, float 0x3FD45F3060000000, float 0x3FD45F3060000000>
  %.v.i.i.op.i.i = select <3 x i1> %1515, <3 x float> zeroinitializer, <3 x float> %.op.i.i1
  %1516 = select <3 x i1> %1514, <3 x float> <float 0x3FD45F3060000000, float 0x3FD45F3060000000, float 0x3FD45F3060000000>, <3 x float> %.v.i.i.op.i.i
  br label %Material_SampleNoMix.exit

; <label>:1517                                    ; preds = %1342
  %1518 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 4, i32 0, i32 1
  %1519 = load i32 addrspace(1)* %1518, align 4, !tbaa !72
  %1520 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1519, i32 0
  %1521 = load i32 addrspace(1)* %1520, align 4, !tbaa !57
  switch i32 %1521, label %Texture_GetSpectrumValue.exit.i1.i [
    i32 0, label %1522
    i32 1, label %1528
  ]

; <label>:1522                                    ; preds = %1517
  %1523 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1519, i32 1
  %1524 = bitcast %union.anon.0.85 addrspace(1)* %1523 to float addrspace(1)*
  %1525 = load float addrspace(1)* %1524, align 4, !tbaa !59
  %1526 = insertelement <3 x float> undef, float %1525, i32 0
  %1527 = shufflevector <3 x float> %1526, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %Texture_GetSpectrumValue.exit.i1.i

; <label>:1528                                    ; preds = %1517
  %1529 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1519, i32 1
  %1530 = bitcast %union.anon.0.85 addrspace(1)* %1529 to float addrspace(1)*
  %1531 = load float addrspace(1)* %1530, align 4, !tbaa !36
  %1532 = insertelement <4 x float> undef, float %1531, i32 0
  %1533 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1519, i32 1, i32 0, i32 1
  %1534 = bitcast i32 addrspace(1)* %1533 to float addrspace(1)*
  %1535 = load float addrspace(1)* %1534, align 4, !tbaa !36
  %1536 = insertelement <4 x float> %1532, float %1535, i32 1
  %1537 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1519, i32 1, i32 0, i32 2, i32 0
  %1538 = load float addrspace(1)* %1537, align 4, !tbaa !36
  %1539 = insertelement <4 x float> %1536, float %1538, i32 2
  br label %Texture_GetSpectrumValue.exit.i1.i

Texture_GetSpectrumValue.exit.i1.i:               ; preds = %1528, %1522, %1517
  %1540 = phi <4 x float> [ %1527, %1522 ], [ %1539, %1528 ], [ undef, %1517 ]
  %1541 = shufflevector <4 x float> %1540, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  %1542 = fcmp ogt <3 x float> %1541, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %1543 = fcmp olt <3 x float> %1541, zeroinitializer
  %.v.i.i10.i.i = select <3 x i1> %1543, <3 x float> zeroinitializer, <3 x float> %1541
  %.v3.i.i11.i.i = select <3 x i1> %1542, <3 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <3 x float> %.v.i.i10.i.i
  %1544 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 4, i32 0, i32 0
  %1545 = load i32 addrspace(1)* %1544, align 4, !tbaa !74
  %1546 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1545, i32 0
  %1547 = load i32 addrspace(1)* %1546, align 4, !tbaa !57
  switch i32 %1547, label %Texture_GetSpectrumValue.exit9.i.i [
    i32 0, label %1548
    i32 1, label %1554
  ]

; <label>:1548                                    ; preds = %Texture_GetSpectrumValue.exit.i1.i
  %1549 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1545, i32 1
  %1550 = bitcast %union.anon.0.85 addrspace(1)* %1549 to float addrspace(1)*
  %1551 = load float addrspace(1)* %1550, align 4, !tbaa !59
  %1552 = insertelement <3 x float> undef, float %1551, i32 0
  %1553 = shufflevector <3 x float> %1552, <3 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
  br label %Texture_GetSpectrumValue.exit9.i.i

; <label>:1554                                    ; preds = %Texture_GetSpectrumValue.exit.i1.i
  %1555 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1545, i32 1
  %1556 = bitcast %union.anon.0.85 addrspace(1)* %1555 to float addrspace(1)*
  %1557 = load float addrspace(1)* %1556, align 4, !tbaa !36
  %1558 = insertelement <4 x float> undef, float %1557, i32 0
  %1559 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1545, i32 1, i32 0, i32 1
  %1560 = bitcast i32 addrspace(1)* %1559 to float addrspace(1)*
  %1561 = load float addrspace(1)* %1560, align 4, !tbaa !36
  %1562 = insertelement <4 x float> %1558, float %1561, i32 1
  %1563 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1545, i32 1, i32 0, i32 2, i32 0
  %1564 = load float addrspace(1)* %1563, align 4, !tbaa !36
  %1565 = insertelement <4 x float> %1562, float %1564, i32 2
  br label %Texture_GetSpectrumValue.exit9.i.i

Texture_GetSpectrumValue.exit9.i.i:               ; preds = %1554, %1548, %Texture_GetSpectrumValue.exit.i1.i
  %1566 = phi <4 x float> [ %1553, %1548 ], [ %1565, %1554 ], [ undef, %Texture_GetSpectrumValue.exit.i1.i ]
  %1567 = shufflevector <4 x float> %1566, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  %1568 = fcmp ogt <3 x float> %1567, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %1569 = fcmp olt <3 x float> %1567, zeroinitializer
  %.v.i.i.i.i = select <3 x i1> %1569, <3 x float> zeroinitializer, <3 x float> %1567
  %.v3.i.i.i.i = select <3 x i1> %1568, <3 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <3 x float> %.v.i.i.i.i
  %1570 = fcmp oeq <3 x float> %.v3.i.i11.i.i, zeroinitializer
  %1571 = sext <3 x i1> %1570 to <3 x i32>
  %1572 = extractelement <3 x i32> %1571, i32 0
  %1573 = extractelement <3 x i32> %1571, i32 1
  %1574 = and i32 %1572, %1573
  %1575 = extractelement <3 x i32> %1571, i32 2
  %1576 = and i32 %1574, %1575
  %1577 = icmp slt i32 %1576, 0
  %1578 = fcmp oeq <3 x float> %.v3.i.i.i.i, zeroinitializer
  %1579 = sext <3 x i1> %1578 to <3 x i32>
  %1580 = extractelement <3 x i32> %1579, i32 0
  %1581 = extractelement <3 x i32> %1579, i32 1
  %1582 = and i32 %1580, %1581
  %1583 = extractelement <3 x i32> %1579, i32 2
  %1584 = and i32 %1582, %1583
  %1585 = icmp slt i32 %1584, 0
  %1586 = and i32 %1584, %1576
  %brmerge.i.i = icmp sgt i32 %1586, -1
  br i1 %brmerge.i.i, label %1587, label %Material_SampleNoMix.exit

; <label>:1587                                    ; preds = %Texture_GetSpectrumValue.exit9.i.i
  %1588 = fcmp ogt float %1423, 0.000000e+00
  %1589 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 4, i32 0, i32 2
  %1590 = load i32 addrspace(1)* %1589, align 4, !tbaa !75
  %1591 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1590, i32 0
  %1592 = load i32 addrspace(1)* %1591, align 4, !tbaa !57
  switch i32 %1592, label %Texture_GetFloatValue.exit8.i.i [
    i32 0, label %1593
    i32 1, label %1597
  ]

; <label>:1593                                    ; preds = %1587
  %1594 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1590, i32 1
  %1595 = bitcast %union.anon.0.85 addrspace(1)* %1594 to float addrspace(1)*
  %1596 = load float addrspace(1)* %1595, align 4, !tbaa !59
  br label %Texture_GetFloatValue.exit8.i.i

; <label>:1597                                    ; preds = %1587
  %1598 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1590, i32 1
  %1599 = bitcast %union.anon.0.85 addrspace(1)* %1598 to float addrspace(1)*
  %1600 = load float addrspace(1)* %1599, align 4, !tbaa !36
  %1601 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1590, i32 1, i32 0, i32 1
  %1602 = bitcast i32 addrspace(1)* %1601 to float addrspace(1)*
  %1603 = load float addrspace(1)* %1602, align 4, !tbaa !36
  %1604 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1590, i32 1, i32 0, i32 2, i32 0
  %1605 = load float addrspace(1)* %1604, align 4, !tbaa !36
  %1606 = fmul float %1603, 0x3FE6E29740000000
  %1607 = tail call float @llvm.fmuladd.f32(float 0x3FCB38CDA0000000, float %1600, float %1606) #2
  %1608 = tail call float @llvm.fmuladd.f32(float 0x3FB279AAE0000000, float %1605, float %1607) #2
  br label %Texture_GetFloatValue.exit8.i.i

Texture_GetFloatValue.exit8.i.i:                  ; preds = %1597, %1593, %1587
  %1609 = phi float [ undef, %1587 ], [ %1596, %1593 ], [ %1608, %1597 ]
  %1610 = getelementptr inbounds %struct.Material.89 addrspace(1)* %mats, i32 %1426, i32 4, i32 0, i32 3
  %1611 = load i32 addrspace(1)* %1610, align 4, !tbaa !76
  %1612 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1611, i32 0
  %1613 = load i32 addrspace(1)* %1612, align 4, !tbaa !57
  switch i32 %1613, label %Texture_GetFloatValue.exit.i.i [
    i32 0, label %1614
    i32 1, label %1618
  ]

; <label>:1614                                    ; preds = %Texture_GetFloatValue.exit8.i.i
  %1615 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1611, i32 1
  %1616 = bitcast %union.anon.0.85 addrspace(1)* %1615 to float addrspace(1)*
  %1617 = load float addrspace(1)* %1616, align 4, !tbaa !59
  br label %Texture_GetFloatValue.exit.i.i

; <label>:1618                                    ; preds = %Texture_GetFloatValue.exit8.i.i
  %1619 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1611, i32 1
  %1620 = bitcast %union.anon.0.85 addrspace(1)* %1619 to float addrspace(1)*
  %1621 = load float addrspace(1)* %1620, align 4, !tbaa !36
  %1622 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1611, i32 1, i32 0, i32 1
  %1623 = bitcast i32 addrspace(1)* %1622 to float addrspace(1)*
  %1624 = load float addrspace(1)* %1623, align 4, !tbaa !36
  %1625 = getelementptr inbounds %struct.Texture.86 addrspace(1)* %texs, i32 %1611, i32 1, i32 0, i32 2, i32 0
  %1626 = load float addrspace(1)* %1625, align 4, !tbaa !36
  %1627 = fmul float %1624, 0x3FE6E29740000000
  %1628 = tail call float @llvm.fmuladd.f32(float 0x3FCB38CDA0000000, float %1621, float %1627) #2
  %1629 = tail call float @llvm.fmuladd.f32(float 0x3FB279AAE0000000, float %1626, float %1628) #2
  br label %Texture_GetFloatValue.exit.i.i

Texture_GetFloatValue.exit.i.i:                   ; preds = %1618, %1614, %Texture_GetFloatValue.exit8.i.i
  %1630 = phi float [ undef, %Texture_GetFloatValue.exit8.i.i ], [ %1617, %1614 ], [ %1629, %1618 ]
  %1631 = fdiv float %1630, %1609, !fpmath !48
  br i1 %1588, label %1632, label %1634

; <label>:1632                                    ; preds = %Texture_GetFloatValue.exit.i.i
  %1633 = fdiv float %1609, %1630, !fpmath !48
  br label %1634

; <label>:1634                                    ; preds = %1632, %Texture_GetFloatValue.exit.i.i
  %1635 = phi float [ %1633, %1632 ], [ %1631, %Texture_GetFloatValue.exit.i.i ]
  br i1 %1585, label %1638, label %1636

; <label>:1636                                    ; preds = %1634
  %1637 = select i1 %1577, float 0.000000e+00, float 5.000000e-01
  br label %1638

; <label>:1638                                    ; preds = %1636, %1634
  %1639 = phi float [ %1637, %1636 ], [ 1.000000e+00, %1634 ]
  %1640 = fcmp ogt float %1639, %1428
  br i1 %1640, label %1641, label %1705

; <label>:1641                                    ; preds = %1638
  %1642 = fsub float -0.000000e+00, %1423
  %1643 = tail call float @llvm.fmuladd.f32(float %1642, float %1423, float 1.000000e+00) #2
  %1644 = fcmp ogt float %1643, 0.000000e+00
  %1645 = select i1 %1644, float %1643, float 0.000000e+00
  %1646 = fmul float %1635, %1635
  %1647 = fmul float %1646, %1645
  %1648 = fcmp ult float %1647, 1.000000e+00
  br i1 %1648, label %1649, label %Material_SampleNoMix.exit

; <label>:1649                                    ; preds = %1641
  %1650 = fsub float 1.000000e+00, %1647
  %1651 = fcmp ogt float %1650, 0.000000e+00
  %1652 = select i1 %1651, float %1650, float 0.000000e+00
  %1653 = tail call float @llvm.sqrt.f32(float %1652) #2
  %1654 = select i1 %1588, float -1.000000e+00, float 1.000000e+00
  %1655 = fmul float %1654, %1653
  %1656 = fsub float -0.000000e+00, %1635
  %1657 = fmul float %1417, %1656
  %1658 = insertelement <4 x float> undef, float %1657, i32 0
  %1659 = fmul float %1420, %1656
  %1660 = insertelement <4 x float> %1658, float %1659, i32 1
  %1661 = insertelement <4 x float> %1660, float %1655, i32 2
  %1662 = tail call float @llvm.fabs.f32(float %1655) #2
  %1663 = fcmp ogt float %1655, 0.000000e+00
  %1664 = fmul float %1631, %1631
  br i1 %1663, label %1665, label %1667

; <label>:1665                                    ; preds = %1649
  %1666 = fdiv float 1.000000e+00, %1664, !fpmath !48
  br label %1667

; <label>:1667                                    ; preds = %1665, %1649
  %1668 = phi float [ %1666, %1665 ], [ %1664, %1649 ]
  %1669 = fsub float -0.000000e+00, %1655
  %1670 = tail call float @llvm.fmuladd.f32(float %1669, float %1655, float 1.000000e+00) #2
  %1671 = fcmp ogt float %1670, 0.000000e+00
  %1672 = select i1 %1671, float %1670, float 0.000000e+00
  %1673 = fmul float %1668, %1672
  %1674 = fcmp ult float %1673, 1.000000e+00
  br i1 %1674, label %1675, label %FresnelCauchy_Evaluate.exit7.i.i

; <label>:1675                                    ; preds = %1667
  %1676 = fsub float 1.000000e+00, %1673
  %1677 = fcmp ogt float %1676, 0.000000e+00
  %1678 = select i1 %1677, float %1676, float 0.000000e+00
  %1679 = tail call float @llvm.sqrt.f32(float %1678) #2
  %1680 = insertelement <3 x float> undef, float %1679, i32 0
  br i1 %1663, label %1683, label %1681

; <label>:1681                                    ; preds = %1675
  %1682 = fdiv float 1.000000e+00, %1631, !fpmath !48
  br label %1683

; <label>:1683                                    ; preds = %1681, %1675
  %1684 = phi float [ %1682, %1681 ], [ %1631, %1675 ]
  %1685 = insertelement <3 x float> undef, float %1684, i32 0
  %1686 = insertelement <3 x float> undef, float %1662, i32 0
  %1687 = fmul <3 x float> %1686, %1685
  %1688 = fsub <3 x float> %1680, %1687
  %1689 = fadd <3 x float> %1680, %1687
  %1690 = fdiv <3 x float> %1688, %1689
  %1691 = shufflevector <3 x float> %1690, <3 x float> undef, <3 x i32> zeroinitializer
  %1692 = fmul <3 x float> %1680, %1685
  %1693 = fsub <3 x float> %1686, %1692
  %1694 = fadd <3 x float> %1686, %1692
  %1695 = fdiv <3 x float> %1693, %1694
  %1696 = fmul <3 x float> %1695, %1695
  %1697 = shufflevector <3 x float> %1696, <3 x float> undef, <3 x i32> zeroinitializer
  %1698 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %1691, <3 x float> %1691, <3 x float> %1697) #2
  %1699 = fmul <3 x float> %1698, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  br label %FresnelCauchy_Evaluate.exit7.i.i

FresnelCauchy_Evaluate.exit7.i.i:                 ; preds = %1683, %1667
  %.0.i6.i.i = phi <3 x float> [ %1699, %1683 ], [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %1667 ]
  %1700 = fsub <3 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %.0.i6.i.i
  %1701 = insertelement <3 x float> undef, float %1646, i32 0
  %1702 = shufflevector <3 x float> %1701, <3 x float> undef, <3 x i32> zeroinitializer
  %1703 = fmul <3 x float> %1702, %1700
  %1704 = fmul <3 x float> %.v3.i.i11.i.i, %1703
  br label %1751

; <label>:1705                                    ; preds = %1638
  %1706 = fsub float -0.000000e+00, %1417
  %1707 = insertelement <3 x float> undef, float %1706, i32 0
  %1708 = fsub float -0.000000e+00, %1420
  %1709 = insertelement <3 x float> %1707, float %1708, i32 1
  %1710 = shufflevector <3 x float> %1709, <3 x float> %1424, <3 x i32> <i32 0, i32 1, i32 5>
  %1711 = shufflevector <3 x float> %1710, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  %1712 = tail call float @llvm.fabs.f32(float %1423) #2
  %1713 = fsub float 1.000000e+00, %1639
  %1714 = fmul float %1631, %1631
  br i1 %1588, label %1715, label %1717

; <label>:1715                                    ; preds = %1705
  %1716 = fdiv float 1.000000e+00, %1714, !fpmath !48
  br label %1717

; <label>:1717                                    ; preds = %1715, %1705
  %1718 = phi float [ %1716, %1715 ], [ %1714, %1705 ]
  %1719 = fsub float -0.000000e+00, %1423
  %1720 = tail call float @llvm.fmuladd.f32(float %1719, float %1423, float 1.000000e+00) #2
  %1721 = fcmp ogt float %1720, 0.000000e+00
  %1722 = select i1 %1721, float %1720, float 0.000000e+00
  %1723 = fmul float %1718, %1722
  %1724 = fcmp ult float %1723, 1.000000e+00
  br i1 %1724, label %1725, label %FresnelCauchy_Evaluate.exit.i.i

; <label>:1725                                    ; preds = %1717
  %1726 = fsub float 1.000000e+00, %1723
  %1727 = fcmp ogt float %1726, 0.000000e+00
  %1728 = select i1 %1727, float %1726, float 0.000000e+00
  %1729 = tail call float @llvm.sqrt.f32(float %1728) #2
  %1730 = insertelement <3 x float> undef, float %1729, i32 0
  br i1 %1588, label %1733, label %1731

; <label>:1731                                    ; preds = %1725
  %1732 = fdiv float 1.000000e+00, %1631, !fpmath !48
  br label %1733

; <label>:1733                                    ; preds = %1731, %1725
  %1734 = phi float [ %1732, %1731 ], [ %1631, %1725 ]
  %1735 = insertelement <3 x float> undef, float %1734, i32 0
  %1736 = insertelement <3 x float> undef, float %1712, i32 0
  %1737 = fmul <3 x float> %1736, %1735
  %1738 = fsub <3 x float> %1730, %1737
  %1739 = fadd <3 x float> %1730, %1737
  %1740 = fdiv <3 x float> %1738, %1739
  %1741 = shufflevector <3 x float> %1740, <3 x float> undef, <3 x i32> zeroinitializer
  %1742 = fmul <3 x float> %1730, %1735
  %1743 = fsub <3 x float> %1736, %1742
  %1744 = fadd <3 x float> %1736, %1742
  %1745 = fdiv <3 x float> %1743, %1744
  %1746 = fmul <3 x float> %1745, %1745
  %1747 = shufflevector <3 x float> %1746, <3 x float> undef, <3 x i32> zeroinitializer
  %1748 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %1741, <3 x float> %1741, <3 x float> %1747) #2
  %1749 = fmul <3 x float> %1748, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  br label %FresnelCauchy_Evaluate.exit.i.i

FresnelCauchy_Evaluate.exit.i.i:                  ; preds = %1733, %1717
  %.0.i.i.i = phi <3 x float> [ %1749, %1733 ], [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %1717 ]
  %1750 = fmul <3 x float> %.v3.i.i.i.i, %.0.i.i.i
  br label %1751

; <label>:1751                                    ; preds = %FresnelCauchy_Evaluate.exit.i.i, %FresnelCauchy_Evaluate.exit7.i.i
  %1752 = phi <4 x float> [ %1661, %FresnelCauchy_Evaluate.exit7.i.i ], [ %1711, %FresnelCauchy_Evaluate.exit.i.i ]
  %1753 = phi float [ %1639, %FresnelCauchy_Evaluate.exit7.i.i ], [ %1713, %FresnelCauchy_Evaluate.exit.i.i ]
  %1754 = phi float [ %1662, %FresnelCauchy_Evaluate.exit7.i.i ], [ %1712, %FresnelCauchy_Evaluate.exit.i.i ]
  %1755 = phi i32 [ 5, %FresnelCauchy_Evaluate.exit7.i.i ], [ 3, %FresnelCauchy_Evaluate.exit.i.i ]
  %.sink.i.i = phi <3 x float> [ %1704, %FresnelCauchy_Evaluate.exit7.i.i ], [ %1750, %FresnelCauchy_Evaluate.exit.i.i ]
  %1756 = insertelement <3 x float> undef, float %1754, i32 0
  %1757 = shufflevector <3 x float> %1756, <3 x float> undef, <3 x i32> zeroinitializer
  %1758 = fdiv <3 x float> %.sink.i.i, %1757, !fpmath !48
  br label %Material_SampleNoMix.exit

Material_SampleNoMix.exit:                        ; preds = %Texture_GetSpectrumValue.exit9.i.i, %1641, %1751, %1342, %1431, %CosineSampleHemisphereWithPdf.exit.i.i, %Texture_GetSpectrumValue.exit.i.i
  %1759 = phi <4 x float> [ undef, %1342 ], [ %1485, %Texture_GetSpectrumValue.exit.i.i ], [ undef, %1431 ], [ %1485, %CosineSampleHemisphereWithPdf.exit.i.i ], [ %1752, %1751 ], [ undef, %Texture_GetSpectrumValue.exit9.i.i ], [ undef, %1641 ]
  %1760 = phi float [ undef, %1342 ], [ %1480, %Texture_GetSpectrumValue.exit.i.i ], [ undef, %1431 ], [ %1480, %CosineSampleHemisphereWithPdf.exit.i.i ], [ %1753, %1751 ], [ undef, %Texture_GetSpectrumValue.exit9.i.i ], [ undef, %1641 ]
  %1761 = phi float [ undef, %1342 ], [ %1487, %Texture_GetSpectrumValue.exit.i.i ], [ undef, %1431 ], [ %1487, %CosineSampleHemisphereWithPdf.exit.i.i ], [ %1754, %1751 ], [ undef, %Texture_GetSpectrumValue.exit9.i.i ], [ undef, %1641 ]
  %1762 = phi i32 [ 0, %1342 ], [ 2, %Texture_GetSpectrumValue.exit.i.i ], [ 0, %1431 ], [ 0, %CosineSampleHemisphereWithPdf.exit.i.i ], [ %1755, %1751 ], [ 0, %Texture_GetSpectrumValue.exit9.i.i ], [ 0, %1641 ]
  %.0.i2 = phi <3 x float> [ zeroinitializer, %1342 ], [ %1516, %Texture_GetSpectrumValue.exit.i.i ], [ zeroinitializer, %1431 ], [ zeroinitializer, %CosineSampleHemisphereWithPdf.exit.i.i ], [ %1758, %1751 ], [ zeroinitializer, %Texture_GetSpectrumValue.exit9.i.i ], [ zeroinitializer, %1641 ]
  %1763 = fcmp oeq <3 x float> %.0.i2, zeroinitializer
  %1764 = sext <3 x i1> %1763 to <3 x i32>
  %1765 = extractelement <3 x i32> %1764, i32 0
  %1766 = extractelement <3 x i32> %1764, i32 1
  %1767 = and i32 %1765, %1766
  %1768 = extractelement <3 x i32> %1764, i32 2
  %1769 = and i32 %1767, %1768
  %1770 = icmp slt i32 %1769, 0
  br i1 %1770, label %BSDF_Sample.exit, label %1771

; <label>:1771                                    ; preds = %Material_SampleNoMix.exit
  %1772 = insertelement <3 x float> undef, float %1398, i32 0
  %1773 = insertelement <3 x float> %1772, float %1400, i32 1
  %1774 = insertelement <3 x float> %1773, float %1402, i32 2
  %1775 = insertelement <3 x float> undef, float %1404, i32 0
  %1776 = insertelement <3 x float> %1775, float %1406, i32 1
  %1777 = insertelement <3 x float> %1776, float %1408, i32 2
  %1778 = insertelement <3 x float> undef, float %1410, i32 0
  %1779 = insertelement <3 x float> %1778, float %1412, i32 1
  %1780 = insertelement <3 x float> %1779, float %1414, i32 2
  %1781 = shufflevector <4 x float> %1759, <4 x float> undef, <3 x i32> zeroinitializer
  %1782 = shufflevector <4 x float> %1759, <4 x float> undef, <3 x i32> <i32 1, i32 1, i32 1>
  %1783 = fmul <3 x float> %1782, %1777
  %1784 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %1774, <3 x float> %1781, <3 x float> %1783) #2
  %1785 = shufflevector <4 x float> %1759, <4 x float> undef, <3 x i32> <i32 2, i32 2, i32 2>
  %1786 = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %1780, <3 x float> %1785, <3 x float> %1784) #2
  %1787 = shufflevector <3 x float> %1786, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
  br label %BSDF_Sample.exit

BSDF_Sample.exit:                                 ; preds = %1771, %Material_SampleNoMix.exit
  %1788 = phi <4 x float> [ %1787, %1771 ], [ undef, %Material_SampleNoMix.exit ]
  %.0.i = phi <3 x float> [ %.0.i2, %1771 ], [ zeroinitializer, %Material_SampleNoMix.exit ]
  %1789 = extractelement <3 x float> %.0.i, i32 0
  %1790 = extractelement <3 x float> %.0.i, i32 1
  %1791 = extractelement <3 x float> %.0.i, i32 2
  %1792 = fcmp olt float %1790, %1791
  %1793 = select i1 %1792, float %1791, float %1790
  %1794 = fcmp olt float %1789, %1793
  %1795 = select i1 %1794, float %1793, float %1789
  %1796 = fcmp ogt float %1795, 1.000000e+00
  br i1 %1796, label %RussianRouletteProb.exit, label %1797

; <label>:1797                                    ; preds = %BSDF_Sample.exit
  %1798 = fcmp olt float %1795, 5.000000e-01
  %1799 = select i1 %1798, float 5.000000e-01, float %1795
  br label %RussianRouletteProb.exit

RussianRouletteProb.exit:                         ; preds = %1797, %BSDF_Sample.exit
  %1800 = phi float [ %1799, %1797 ], [ 1.000000e+00, %BSDF_Sample.exit ]
  %1801 = icmp ugt i32 %8, 4
  %1802 = and i32 %1762, 1
  %1803 = icmp eq i32 %1802, 0
  %or.cond = and i1 %1801, %1803
  br i1 %or.cond, label %1804, label %.thread20

; <label>:1804                                    ; preds = %RussianRouletteProb.exit
  %1805 = shl i32 %1372, 12
  %1806 = and i32 %1805, -8192
  %1807 = shl i32 %1372, 13
  %1808 = xor i32 %1807, %1367
  %1809 = lshr i32 %1808, 19
  %1810 = or i32 %1809, %1806
  %1811 = shl i32 %1378, 4
  %1812 = and i32 %1811, -128
  %1813 = shl i32 %1339, 10
  %1814 = xor i32 %1373, %1813
  %1815 = lshr i32 %1814, 25
  %1816 = or i32 %1812, %1815
  %1817 = shl i32 %1383, 17
  %1818 = and i32 %1817, -2097152
  %1819 = shl i32 %1384, 3
  %1820 = xor i32 %1819, %1384
  %1821 = lshr i32 %1820, 11
  %1822 = or i32 %1821, %1818
  %1823 = xor i32 %1822, %1816
  %1824 = xor i32 %1823, %1810
  %1825 = zext i32 %1824 to i64
  %1826 = and i64 %1825, 16777215
  %1827 = uitofp i64 %1826 to float
  %1828 = fmul float %1827, 0x3E70000000000000
  %1829 = fcmp olt float %1828, %1800
  br label %.thread20

.thread20:                                        ; preds = %1804, %RussianRouletteProb.exit
  %1830 = phi i32 [ %1822, %1804 ], [ %1384, %RussianRouletteProb.exit ]
  %1831 = phi i32 [ %1816, %1804 ], [ %1378, %RussianRouletteProb.exit ]
  %1832 = phi i32 [ %1810, %1804 ], [ %1372, %RussianRouletteProb.exit ]
  %1833 = phi i1 [ true, %1804 ], [ false, %RussianRouletteProb.exit ]
  %1834 = phi i1 [ %1829, %1804 ], [ true, %RussianRouletteProb.exit ]
  %1835 = fcmp oeq <3 x float> %.0.i, zeroinitializer
  %1836 = sext <3 x i1> %1835 to <3 x i32>
  %1837 = extractelement <3 x i32> %1836, i32 0
  %1838 = extractelement <3 x i32> %1836, i32 1
  %1839 = and i32 %1837, %1838
  %1840 = extractelement <3 x i32> %1836, i32 2
  %1841 = and i32 %1839, %1840
  %not. = icmp sgt i32 %1841, -1
  %. = and i1 %1834, %not.
  br i1 %., label %1842, label %.thread22

; <label>:1842                                    ; preds = %.thread20
  br i1 %1833, label %1843, label %._crit_edge

; <label>:1843                                    ; preds = %1842
  %1844 = fmul float %1760, %1800
  br label %._crit_edge

._crit_edge:                                      ; preds = %1843, %1842
  %1845 = phi float [ %1844, %1843 ], [ %1760, %1842 ]
  %1846 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 2, i32 0
  %1847 = load float addrspace(1)* %1846, align 4, !tbaa !36
  %1848 = insertelement <3 x float> undef, float %1847, i32 0
  %1849 = getelementptr inbounds float addrspace(1)* %1846, i32 1
  %1850 = load float addrspace(1)* %1849, align 4, !tbaa !36
  %1851 = insertelement <3 x float> %1848, float %1850, i32 1
  %1852 = getelementptr inbounds float addrspace(1)* %1846, i32 2
  %1853 = load float addrspace(1)* %1852, align 4, !tbaa !36
  %1854 = insertelement <3 x float> %1851, float %1853, i32 2
  %1855 = fdiv float %1761, %1845, !fpmath !48
  %1856 = insertelement <3 x float> undef, float %1855, i32 0
  %1857 = shufflevector <3 x float> %1856, <3 x float> undef, <3 x i32> zeroinitializer
  %1858 = fmul <3 x float> %.0.i, %1857
  %1859 = fmul <3 x float> %1854, %1858
  %1860 = extractelement <3 x float> %1859, i32 0
  store float %1860, float addrspace(1)* %1846, align 4, !tbaa !36
  %1861 = extractelement <3 x float> %1859, i32 1
  store float %1861, float addrspace(1)* %1849, align 4, !tbaa !36
  %1862 = extractelement <3 x float> %1859, i32 2
  store float %1862, float addrspace(1)* %1852, align 4, !tbaa !36
  %1863 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 1, i32 0
  %1864 = load float addrspace(1)* %1863, align 4, !tbaa !36
  %1865 = getelementptr inbounds float addrspace(1)* %1863, i32 1
  %1866 = load float addrspace(1)* %1865, align 4, !tbaa !36
  %1867 = getelementptr inbounds float addrspace(1)* %1863, i32 2
  %1868 = load float addrspace(1)* %1867, align 4, !tbaa !36
  %1869 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %19, i32 0, i32 0, i32 0
  store float %1864, float addrspace(1)* %1869, align 4, !tbaa !36
  %1870 = getelementptr inbounds float addrspace(1)* %1869, i32 1
  store float %1866, float addrspace(1)* %1870, align 4, !tbaa !36
  %1871 = getelementptr inbounds float addrspace(1)* %1869, i32 2
  store float %1868, float addrspace(1)* %1871, align 4, !tbaa !36
  %1872 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  %1873 = extractelement <4 x float> %1788, i32 0
  store float %1873, float addrspace(1)* %1872, align 4, !tbaa !36
  %1874 = extractelement <4 x float> %1788, i32 1
  %1875 = getelementptr inbounds float addrspace(1)* %1872, i32 1
  store float %1874, float addrspace(1)* %1875, align 4, !tbaa !36
  %1876 = extractelement <4 x float> %1788, i32 2
  %1877 = getelementptr inbounds float addrspace(1)* %1872, i32 2
  store float %1876, float addrspace(1)* %1877, align 4, !tbaa !36
  %1878 = bitcast float %1864 to i32
  %1879 = add i32 %1878, 128
  %1880 = bitcast i32 %1879 to float
  %1881 = fsub float %1880, %1864
  %1882 = tail call float @llvm.fabs.f32(float %1881) #2
  %1883 = fcmp ogt float %1882, 0x3FB99999A0000000
  br i1 %1883, label %MachineEpsilon_E.exit.i.i, label %1884

; <label>:1884                                    ; preds = %._crit_edge
  %1885 = fcmp olt float %1882, 0x3E112E0BE0000000
  %1886 = select i1 %1885, float 0x3E112E0BE0000000, float %1882
  br label %MachineEpsilon_E.exit.i.i

MachineEpsilon_E.exit.i.i:                        ; preds = %1884, %._crit_edge
  %1887 = phi float [ %1886, %1884 ], [ 0x3FB99999A0000000, %._crit_edge ]
  %1888 = bitcast float %1866 to i32
  %1889 = add i32 %1888, 128
  %1890 = bitcast i32 %1889 to float
  %1891 = fsub float %1890, %1866
  %1892 = tail call float @llvm.fabs.f32(float %1891) #2
  %1893 = fcmp ogt float %1892, 0x3FB99999A0000000
  br i1 %1893, label %MachineEpsilon_E.exit2.i.i, label %1894

; <label>:1894                                    ; preds = %MachineEpsilon_E.exit.i.i
  %1895 = fcmp olt float %1892, 0x3E112E0BE0000000
  %1896 = select i1 %1895, float 0x3E112E0BE0000000, float %1892
  br label %MachineEpsilon_E.exit2.i.i

MachineEpsilon_E.exit2.i.i:                       ; preds = %1894, %MachineEpsilon_E.exit.i.i
  %1897 = phi float [ %1896, %1894 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit.i.i ]
  %1898 = bitcast float %1868 to i32
  %1899 = add i32 %1898, 128
  %1900 = bitcast i32 %1899 to float
  %1901 = fsub float %1900, %1868
  %1902 = tail call float @llvm.fabs.f32(float %1901) #2
  %1903 = fcmp ogt float %1902, 0x3FB99999A0000000
  br i1 %1903, label %Ray_Init2.exit, label %1904

; <label>:1904                                    ; preds = %MachineEpsilon_E.exit2.i.i
  %1905 = fcmp olt float %1902, 0x3E112E0BE0000000
  %1906 = select i1 %1905, float 0x3E112E0BE0000000, float %1902
  br label %Ray_Init2.exit

Ray_Init2.exit:                                   ; preds = %1904, %MachineEpsilon_E.exit2.i.i
  %1907 = phi float [ %1906, %1904 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit2.i.i ]
  %1908 = fcmp olt float %1897, %1907
  %1909 = select i1 %1908, float %1907, float %1897
  %1910 = fcmp olt float %1887, %1909
  %1911 = select i1 %1910, float %1909, float %1887
  %1912 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 2
  store float %1911, float addrspace(1)* %1912, align 4, !tbaa !69
  %1913 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 3
  store float 0x7FF0000000000000, float addrspace(1)* %1913, align 4, !tbaa !71
  %1914 = add i32 %8, 1
  store i32 %1914, i32 addrspace(1)* %7, align 4, !tbaa !30
  %1915 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 1
  store float %1845, float addrspace(1)* %1915, align 4, !tbaa !62
  %1916 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 2
  store i32 %1802, i32 addrspace(1)* %1916, align 4, !tbaa !61
  %1917 = shl i32 %1832, 12
  %1918 = and i32 %1917, -8192
  %1919 = shl i32 %1832, 13
  %1920 = xor i32 %1919, %1832
  %1921 = lshr i32 %1920, 19
  %1922 = or i32 %1921, %1918
  %1923 = shl i32 %1831, 4
  %1924 = and i32 %1923, -128
  %1925 = shl i32 %1831, 2
  %1926 = xor i32 %1925, %1831
  %1927 = lshr i32 %1926, 25
  %1928 = or i32 %1927, %1924
  %1929 = shl i32 %1830, 17
  %1930 = and i32 %1929, -2097152
  %1931 = shl i32 %1830, 3
  %1932 = xor i32 %1931, %1830
  %1933 = lshr i32 %1932, 11
  %1934 = or i32 %1933, %1930
  %1935 = xor i32 %1928, %1934
  %1936 = xor i32 %1935, %1922
  %1937 = zext i32 %1936 to i64
  %1938 = and i64 %1937, 16777215
  %1939 = uitofp i64 %1938 to float
  %1940 = fmul float %1939, 0x3E70000000000000
  store float %1940, float addrspace(1)* %1427, align 4, !tbaa !77
  br label %.thread24

.thread22:                                        ; preds = %.thread20, %.thread18, %459
  %1941 = phi i32 [ %1830, %.thread20 ], [ %1338, %.thread18 ], [ %18, %459 ]
  %1942 = phi i32 [ %1831, %.thread20 ], [ %1339, %.thread18 ], [ %16, %459 ]
  %1943 = phi i32 [ %1832, %.thread20 ], [ %1340, %.thread18 ], [ %14, %459 ]
  %1944 = load float addrspace(1)* %12, align 4, !tbaa !36
  %.sum19 = or i32 %11, 1
  %1945 = getelementptr inbounds float addrspace(1)* %samplesData, i32 %.sum19
  %1946 = load float addrspace(1)* %1945, align 4, !tbaa !36
  %1947 = getelementptr inbounds %struct.RandomSample.93 addrspace(1)* %10, i32 0, i32 0, i32 0
  %1948 = load float addrspace(1)* %1947, align 4, !tbaa !36
  %1949 = insertelement <4 x float> undef, float %1948, i32 0
  %1950 = getelementptr inbounds float addrspace(1)* %1947, i32 1
  %1951 = load float addrspace(1)* %1950, align 4, !tbaa !36
  %1952 = insertelement <4 x float> %1949, float %1951, i32 1
  %1953 = getelementptr inbounds float addrspace(1)* %1947, i32 2
  %1954 = load float addrspace(1)* %1953, align 4, !tbaa !36
  %1955 = insertelement <4 x float> %1952, float %1954, i32 2
  %1956 = tail call float @llvm.fmuladd.f32(float 6.400000e+02, float %1944, float 5.000000e-01) #2
  %1957 = tail call float @llvm.floor.f32(float %1956) #2
  %1958 = fptoui float %1957 to i32
  %1959 = icmp ult i32 %1958, 639
  %1960 = tail call float @llvm.fmuladd.f32(float 4.800000e+02, float %1946, float 5.000000e-01) #2
  %1961 = tail call float @llvm.floor.f32(float %1960) #2
  %1962 = fptoui float %1961 to i32
  %1963 = icmp ult i32 %1962, 479
  %.op.i.i = mul i32 %1962, 642
  %1964 = select i1 %1963, i32 %.op.i.i, i32 307518
  %.op1.i.i = add i32 %1958, 643
  %1965 = select i1 %1959, i32 %.op1.i.i, i32 1282
  %1966 = add i32 %1964, %1965
  %1967 = getelementptr inbounds %struct.Pixel.92 addrspace(1)* %frameBuffer, i32 %1966
  %1968 = insertelement <4 x float> %1955, float 1.000000e+00, i32 3
  %1969 = getelementptr inbounds %struct.Pixel.92 addrspace(1)* %1967, i32 0, i32 0, i32 0
  %1970 = load float addrspace(1)* %1969, align 4, !tbaa !36
  %1971 = insertelement <4 x float> undef, float %1970, i32 0
  %1972 = getelementptr inbounds float addrspace(1)* %1969, i32 1
  %1973 = load float addrspace(1)* %1972, align 4, !tbaa !36
  %1974 = insertelement <4 x float> %1971, float %1973, i32 1
  %1975 = getelementptr inbounds float addrspace(1)* %1969, i32 2
  %1976 = load float addrspace(1)* %1975, align 4, !tbaa !36
  %1977 = insertelement <4 x float> %1974, float %1976, i32 2
  %1978 = getelementptr inbounds float addrspace(1)* %1969, i32 3
  %1979 = load float addrspace(1)* %1978, align 4, !tbaa !36
  %1980 = insertelement <4 x float> %1977, float %1979, i32 3
  %1981 = fadd <4 x float> %1968, %1980
  %1982 = bitcast %struct.Pixel.92 addrspace(1)* %1967 to <4 x float> addrspace(1)*
  store <4 x float> %1981, <4 x float> addrspace(1)* %1982, align 4, !tbaa !36
  %1983 = shl i32 %1943, 12
  %1984 = and i32 %1983, -8192
  %1985 = shl i32 %1943, 13
  %1986 = xor i32 %1985, %1943
  %1987 = lshr i32 %1986, 19
  %1988 = or i32 %1987, %1984
  %1989 = shl i32 %1942, 4
  %1990 = and i32 %1989, -128
  %1991 = shl i32 %1942, 2
  %1992 = xor i32 %1991, %1942
  %1993 = lshr i32 %1992, 25
  %1994 = or i32 %1993, %1990
  %1995 = shl i32 %1941, 17
  %1996 = and i32 %1995, -2097152
  %1997 = shl i32 %1941, 3
  %1998 = xor i32 %1997, %1941
  %1999 = lshr i32 %1998, 11
  %2000 = or i32 %1999, %1996
  %2001 = xor i32 %1994, %2000
  %2002 = xor i32 %2001, %1988
  %2003 = zext i32 %2002 to i64
  %2004 = and i64 %2003, 16777215
  %2005 = uitofp i64 %2004 to float
  %2006 = fmul float %2005, 0x3E70000000000000
  store float %2006, float addrspace(1)* %12, align 4, !tbaa !36
  %2007 = shl i32 %1988, 12
  %2008 = and i32 %2007, -8192
  %2009 = shl i32 %1988, 13
  %2010 = xor i32 %2009, %1983
  %2011 = lshr i32 %2010, 19
  %2012 = or i32 %2011, %2008
  %2013 = shl i32 %1994, 4
  %2014 = and i32 %2013, -128
  %2015 = shl i32 %1942, 6
  %2016 = xor i32 %2015, %1989
  %2017 = lshr i32 %2016, 25
  %2018 = or i32 %2014, %2017
  %2019 = shl i32 %1999, 17
  %2020 = and i32 %2019, -2097152
  %2021 = shl i32 %2000, 3
  %2022 = xor i32 %2021, %2000
  %2023 = lshr i32 %2022, 11
  %2024 = or i32 %2023, %2020
  %2025 = xor i32 %2024, %2018
  %2026 = xor i32 %2025, %2012
  %2027 = zext i32 %2026 to i64
  %2028 = and i64 %2027, 16777215
  %2029 = uitofp i64 %2028 to float
  %2030 = fmul float %2029, 0x3E70000000000000
  store float %2030, float addrspace(1)* %1945, align 4, !tbaa !36
  store float 0.000000e+00, float addrspace(1)* %1947, align 4, !tbaa !36
  store float 0.000000e+00, float addrspace(1)* %1950, align 4, !tbaa !36
  store float 0.000000e+00, float addrspace(1)* %1953, align 4, !tbaa !36
  %2031 = getelementptr inbounds %struct.GPUTaskStats.101 addrspace(1)* %taskStats, i32 %2, i32 0
  %2032 = load i32 addrspace(1)* %2031, align 4, !tbaa !67
  %2033 = add i32 %2032, 1
  store i32 %2033, i32 addrspace(1)* %2031, align 4, !tbaa !67
  %2034 = load float addrspace(1)* %12, align 4, !tbaa !36
  %2035 = load float addrspace(1)* %1945, align 4, !tbaa !36
  %2036 = shl i32 %2012, 12
  %2037 = and i32 %2036, -8192
  %2038 = shl i32 %2012, 13
  %2039 = xor i32 %2038, %2007
  %2040 = lshr i32 %2039, 19
  %2041 = or i32 %2040, %2037
  %2042 = shl i32 %2018, 4
  %2043 = and i32 %2042, -128
  %2044 = shl i32 %1942, 10
  %2045 = xor i32 %2013, %2044
  %2046 = lshr i32 %2045, 25
  %2047 = or i32 %2043, %2046
  %2048 = shl i32 %2023, 17
  %2049 = and i32 %2048, -2097152
  %2050 = shl i32 %2024, 3
  %2051 = xor i32 %2050, %2024
  %2052 = lshr i32 %2051, 11
  %2053 = or i32 %2052, %2049
  %2054 = xor i32 %2053, %2047
  %2055 = xor i32 %2054, %2041
  %2056 = zext i32 %2055 to i64
  %2057 = and i64 %2056, 16777215
  %2058 = uitofp i64 %2057 to float
  %2059 = fmul float %2058, 0x3E70000000000000
  %2060 = fmul float %2034, 6.400000e+02
  %2061 = fcmp olt float %2060, 6.390000e+02
  %2062 = select i1 %2061, float %2060, float 6.390000e+02
  %2063 = fsub float 1.000000e+00, %2035
  %2064 = fmul float %2063, 4.800000e+02
  %2065 = fcmp olt float %2064, 4.790000e+02
  %2066 = select i1 %2065, float %2064, float 4.790000e+02
  %2067 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 0
  %2068 = load float addrspace(1)* %2067, align 4, !tbaa !36
  %2069 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 1
  %2070 = load float addrspace(1)* %2069, align 4, !tbaa !36
  %2071 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 2
  %2072 = load float addrspace(1)* %2071, align 4, !tbaa !36
  %2073 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3, i32 3
  %2074 = load float addrspace(1)* %2073, align 4, !tbaa !36
  %2075 = fmul float %2070, %2066
  %2076 = tail call float @llvm.fmuladd.f32(float %2068, float %2062, float %2075) #2
  %2077 = tail call float @llvm.fmuladd.f32(float %2072, float 0.000000e+00, float %2076) #2
  %2078 = tail call float @llvm.fmuladd.f32(float %2074, float 1.000000e+00, float %2077) #2
  %2079 = fdiv float 1.000000e+00, %2078, !fpmath !48
  %2080 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0
  %2081 = load float addrspace(1)* %2080, align 4, !tbaa !36
  %2082 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1
  %2083 = load float addrspace(1)* %2082, align 4, !tbaa !36
  %2084 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2
  %2085 = load float addrspace(1)* %2084, align 4, !tbaa !36
  %2086 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 3
  %2087 = load float addrspace(1)* %2086, align 4, !tbaa !36
  %2088 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0
  %2089 = load float addrspace(1)* %2088, align 4, !tbaa !36
  %2090 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1
  %2091 = load float addrspace(1)* %2090, align 4, !tbaa !36
  %2092 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 2
  %2093 = load float addrspace(1)* %2092, align 4, !tbaa !36
  %2094 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 3
  %2095 = load float addrspace(1)* %2094, align 4, !tbaa !36
  %2096 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0
  %2097 = load float addrspace(1)* %2096, align 4, !tbaa !36
  %2098 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 1
  %2099 = load float addrspace(1)* %2098, align 4, !tbaa !36
  %2100 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 2
  %2101 = load float addrspace(1)* %2100, align 4, !tbaa !36
  %2102 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 3
  %2103 = load float addrspace(1)* %2102, align 4, !tbaa !36
  %2104 = fmul float %2066, %2083
  %2105 = tail call float @llvm.fmuladd.f32(float %2081, float %2062, float %2104) #2
  %2106 = tail call float @llvm.fmuladd.f32(float %2085, float 0.000000e+00, float %2105) #2
  %2107 = tail call float @llvm.fmuladd.f32(float %2087, float 1.000000e+00, float %2106) #2
  %2108 = fmul float %2079, %2107
  %2109 = insertelement <3 x float> undef, float %2108, i32 0
  %2110 = fmul float %2066, %2091
  %2111 = tail call float @llvm.fmuladd.f32(float %2089, float %2062, float %2110) #2
  %2112 = tail call float @llvm.fmuladd.f32(float %2093, float 0.000000e+00, float %2111) #2
  %2113 = tail call float @llvm.fmuladd.f32(float %2095, float 1.000000e+00, float %2112) #2
  %2114 = fmul float %2079, %2113
  %2115 = insertelement <3 x float> %2109, float %2114, i32 1
  %2116 = fmul float %2066, %2099
  %2117 = tail call float @llvm.fmuladd.f32(float %2097, float %2062, float %2116) #2
  %2118 = tail call float @llvm.fmuladd.f32(float %2101, float 0.000000e+00, float %2117) #2
  %2119 = tail call float @llvm.fmuladd.f32(float %2103, float 1.000000e+00, float %2118) #2
  %2120 = fmul float %2079, %2119
  %2121 = insertelement <3 x float> %2115, float %2120, i32 2
  %2122 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 5
  %2123 = load float addrspace(1)* %2122, align 4, !tbaa !78
  %2124 = fmul float %2114, %2114
  %2125 = tail call float @llvm.fmuladd.f32(float %2108, float %2108, float %2124) #2
  %2126 = tail call float @llvm.fmuladd.f32(float %2120, float %2120, float %2125) #2
  %2127 = tail call float @llvm.sqrt.f32(float %2126) #3
  %2128 = insertelement <3 x float> undef, float %2127, i32 0
  %2129 = shufflevector <3 x float> %2128, <3 x float> undef, <3 x i32> zeroinitializer
  %2130 = fdiv <3 x float> %2121, %2129, !fpmath !48
  %2131 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 4
  %2132 = load float addrspace(1)* %2131, align 4, !tbaa !80
  %2133 = fsub float %2132, %2123
  %2134 = extractelement <3 x float> %2130, i32 2
  %2135 = fdiv float %2133, %2134, !fpmath !48
  %2136 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 0
  %2137 = load float addrspace(1)* %2136, align 4, !tbaa !36
  %2138 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 1
  %2139 = load float addrspace(1)* %2138, align 4, !tbaa !36
  %2140 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 2
  %2141 = load float addrspace(1)* %2140, align 4, !tbaa !36
  %2142 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3, i32 3
  %2143 = load float addrspace(1)* %2142, align 4, !tbaa !36
  %2144 = fmul float %2114, %2139
  %2145 = tail call float @llvm.fmuladd.f32(float %2137, float %2108, float %2144) #2
  %2146 = tail call float @llvm.fmuladd.f32(float %2141, float %2120, float %2145) #2
  %2147 = tail call float @llvm.fmuladd.f32(float %2143, float 1.000000e+00, float %2146) #2
  %2148 = fdiv float 1.000000e+00, %2147, !fpmath !48
  %2149 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0
  %2150 = load float addrspace(1)* %2149, align 4, !tbaa !36
  %2151 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1
  %2152 = load float addrspace(1)* %2151, align 4, !tbaa !36
  %2153 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 2
  %2154 = load float addrspace(1)* %2153, align 4, !tbaa !36
  %2155 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 3
  %2156 = load float addrspace(1)* %2155, align 4, !tbaa !36
  %2157 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 0
  %2158 = load float addrspace(1)* %2157, align 4, !tbaa !36
  %2159 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 1
  %2160 = load float addrspace(1)* %2159, align 4, !tbaa !36
  %2161 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 2
  %2162 = load float addrspace(1)* %2161, align 4, !tbaa !36
  %2163 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 1, i32 3
  %2164 = load float addrspace(1)* %2163, align 4, !tbaa !36
  %2165 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 0
  %2166 = load float addrspace(1)* %2165, align 4, !tbaa !36
  %2167 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 1
  %2168 = load float addrspace(1)* %2167, align 4, !tbaa !36
  %2169 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 2
  %2170 = load float addrspace(1)* %2169, align 4, !tbaa !36
  %2171 = getelementptr inbounds %struct.Camera.90 addrspace(1)* %camera, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2, i32 3
  %2172 = load float addrspace(1)* %2171, align 4, !tbaa !36
  %2173 = fmul float %2114, %2152
  %2174 = tail call float @llvm.fmuladd.f32(float %2150, float %2108, float %2173) #2
  %2175 = tail call float @llvm.fmuladd.f32(float %2154, float %2120, float %2174) #2
  %2176 = tail call float @llvm.fmuladd.f32(float %2156, float 1.000000e+00, float %2175) #2
  %2177 = fmul float %2148, %2176
  %2178 = fmul float %2114, %2160
  %2179 = tail call float @llvm.fmuladd.f32(float %2158, float %2108, float %2178) #2
  %2180 = tail call float @llvm.fmuladd.f32(float %2162, float %2120, float %2179) #2
  %2181 = tail call float @llvm.fmuladd.f32(float %2164, float 1.000000e+00, float %2180) #2
  %2182 = fmul float %2148, %2181
  %2183 = fmul float %2114, %2168
  %2184 = tail call float @llvm.fmuladd.f32(float %2166, float %2108, float %2183) #2
  %2185 = tail call float @llvm.fmuladd.f32(float %2170, float %2120, float %2184) #2
  %2186 = tail call float @llvm.fmuladd.f32(float %2172, float 1.000000e+00, float %2185) #2
  %2187 = fmul float %2148, %2186
  %2188 = extractelement <3 x float> %2130, i32 0
  %2189 = extractelement <3 x float> %2130, i32 1
  %2190 = fmul float %2189, %2152
  %2191 = tail call float @llvm.fmuladd.f32(float %2150, float %2188, float %2190) #2
  %2192 = tail call float @llvm.fmuladd.f32(float %2154, float %2134, float %2191) #2
  %2193 = fmul float %2189, %2160
  %2194 = tail call float @llvm.fmuladd.f32(float %2158, float %2188, float %2193) #2
  %2195 = tail call float @llvm.fmuladd.f32(float %2162, float %2134, float %2194) #2
  %2196 = fmul float %2189, %2168
  %2197 = tail call float @llvm.fmuladd.f32(float %2166, float %2188, float %2196) #2
  %2198 = tail call float @llvm.fmuladd.f32(float %2170, float %2134, float %2197) #2
  %2199 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %19, i32 0, i32 0, i32 0
  store float %2177, float addrspace(1)* %2199, align 4, !tbaa !36
  %2200 = getelementptr inbounds float addrspace(1)* %2199, i32 1
  store float %2182, float addrspace(1)* %2200, align 4, !tbaa !36
  %2201 = getelementptr inbounds float addrspace(1)* %2199, i32 2
  store float %2187, float addrspace(1)* %2201, align 4, !tbaa !36
  %2202 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 1, i32 0
  store float %2192, float addrspace(1)* %2202, align 4, !tbaa !36
  %2203 = getelementptr inbounds float addrspace(1)* %2202, i32 1
  store float %2195, float addrspace(1)* %2203, align 4, !tbaa !36
  %2204 = getelementptr inbounds float addrspace(1)* %2202, i32 2
  store float %2198, float addrspace(1)* %2204, align 4, !tbaa !36
  %2205 = bitcast float %2177 to i32
  %2206 = add i32 %2205, 128
  %2207 = bitcast i32 %2206 to float
  %2208 = fsub float %2207, %2177
  %2209 = tail call float @llvm.fabs.f32(float %2208) #2
  %2210 = fcmp ogt float %2209, 0x3FB99999A0000000
  br i1 %2210, label %MachineEpsilon_E.exit.i.i.i, label %2211

; <label>:2211                                    ; preds = %.thread22
  %2212 = fcmp olt float %2209, 0x3E112E0BE0000000
  %2213 = select i1 %2212, float 0x3E112E0BE0000000, float %2209
  br label %MachineEpsilon_E.exit.i.i.i

MachineEpsilon_E.exit.i.i.i:                      ; preds = %2211, %.thread22
  %2214 = phi float [ %2213, %2211 ], [ 0x3FB99999A0000000, %.thread22 ]
  %2215 = bitcast float %2182 to i32
  %2216 = add i32 %2215, 128
  %2217 = bitcast i32 %2216 to float
  %2218 = fsub float %2217, %2182
  %2219 = tail call float @llvm.fabs.f32(float %2218) #2
  %2220 = fcmp ogt float %2219, 0x3FB99999A0000000
  br i1 %2220, label %MachineEpsilon_E.exit2.i.i.i, label %2221

; <label>:2221                                    ; preds = %MachineEpsilon_E.exit.i.i.i
  %2222 = fcmp olt float %2219, 0x3E112E0BE0000000
  %2223 = select i1 %2222, float 0x3E112E0BE0000000, float %2219
  br label %MachineEpsilon_E.exit2.i.i.i

MachineEpsilon_E.exit2.i.i.i:                     ; preds = %2221, %MachineEpsilon_E.exit.i.i.i
  %2224 = phi float [ %2223, %2221 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit.i.i.i ]
  %2225 = bitcast float %2187 to i32
  %2226 = add i32 %2225, 128
  %2227 = bitcast i32 %2226 to float
  %2228 = fsub float %2227, %2187
  %2229 = tail call float @llvm.fabs.f32(float %2228) #2
  %2230 = fcmp ogt float %2229, 0x3FB99999A0000000
  br i1 %2230, label %Camera_GenerateRay.exit, label %2231

; <label>:2231                                    ; preds = %MachineEpsilon_E.exit2.i.i.i
  %2232 = fcmp olt float %2229, 0x3E112E0BE0000000
  %2233 = select i1 %2232, float 0x3E112E0BE0000000, float %2229
  br label %Camera_GenerateRay.exit

Camera_GenerateRay.exit:                          ; preds = %MachineEpsilon_E.exit2.i.i.i, %2231
  %2234 = phi float [ %2233, %2231 ], [ 0x3FB99999A0000000, %MachineEpsilon_E.exit2.i.i.i ]
  %2235 = fcmp olt float %2224, %2234
  %2236 = select i1 %2235, float %2234, float %2224
  %2237 = fcmp olt float %2214, %2236
  %2238 = select i1 %2237, float %2236, float %2214
  %2239 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 2
  store float %2238, float addrspace(1)* %2239, align 4, !tbaa !69
  %2240 = getelementptr inbounds %struct.Ray.70 addrspace(1)* %rays, i32 %2, i32 3
  store float %2135, float addrspace(1)* %2240, align 4, !tbaa !71
  store i32 0, i32 addrspace(1)* %5, align 4, !tbaa !14
  store i32 1, i32 addrspace(1)* %7, align 4, !tbaa !30
  %2241 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 2, i32 0
  store float 1.000000e+00, float addrspace(1)* %2241, align 4, !tbaa !36
  %2242 = getelementptr inbounds float addrspace(1)* %2241, i32 1
  store float 1.000000e+00, float addrspace(1)* %2242, align 4, !tbaa !36
  %2243 = getelementptr inbounds float addrspace(1)* %2241, i32 2
  store float 1.000000e+00, float addrspace(1)* %2243, align 4, !tbaa !36
  %2244 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 1
  store float 1.000000e+00, float addrspace(1)* %2244, align 4, !tbaa !62
  %2245 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 3, i32 2
  store i32 1, i32 addrspace(1)* %2245, align 4, !tbaa !61
  %2246 = getelementptr inbounds %struct.GPUTask.100 addrspace(1)* %tasks, i32 %2, i32 2, i32 3, i32 0, i32 5
  store float %2059, float addrspace(1)* %2246, align 4, !tbaa !77
  br label %2250

.thread24:                                        ; preds = %Ray_Init2.exit, %.thread19, %459
  %2247 = phi i32 [ %1272, %.thread19 ], [ %1934, %Ray_Init2.exit ], [ %18, %459 ]
  %2248 = phi i32 [ %1266, %.thread19 ], [ %1928, %Ray_Init2.exit ], [ %16, %459 ]
  %2249 = phi i32 [ %1260, %.thread19 ], [ %1922, %Ray_Init2.exit ], [ %14, %459 ]
  %pathState.325 = phi i32 [ 2, %.thread19 ], [ 0, %Ray_Init2.exit ], [ %6, %459 ]
  store i32 %pathState.325, i32 addrspace(1)* %5, align 4, !tbaa !14
  br label %2250

; <label>:2250                                    ; preds = %.thread24, %Camera_GenerateRay.exit
  %2251 = phi i32 [ %2247, %.thread24 ], [ %2053, %Camera_GenerateRay.exit ]
  %2252 = phi i32 [ %2248, %.thread24 ], [ %2047, %Camera_GenerateRay.exit ]
  %2253 = phi i32 [ %2249, %.thread24 ], [ %2041, %Camera_GenerateRay.exit ]
  store i32 %2253, i32 addrspace(1)* %13, align 4, !tbaa !31
  store i32 %2252, i32 addrspace(1)* %15, align 4, !tbaa !32
  store i32 %2251, i32 addrspace(1)* %17, align 4, !tbaa !33
  br label %2254

; <label>:2254                                    ; preds = %2250, %0
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tgid.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.local.size.x() #0

; Function Attrs: nounwind readnone
declare i32 @llvm.r600.read.tidig.x() #0

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
attributes #3 = { nobuiltin nounwind }

!opencl.kernels = !{!0, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11}
!llvm.ident = !{!12, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13, !13}

!0 = metadata !{null, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 64, i32 1, i32 1}
!2 = metadata !{null, metadata !1}
!3 = metadata !{void (%struct.GPUTask.100 addrspace(1)*, %struct.GPUTaskStats.101 addrspace(1)*, float addrspace(1)*, %struct.Ray.70 addrspace(1)*, %struct.RayHit.96 addrspace(1)*, %struct.Pixel.92 addrspace(1)*, %struct.Material.89 addrspace(1)*, %struct.Texture.86 addrspace(1)*, i32 addrspace(1)*, %struct.Mesh.95 addrspace(1)*, %struct.Point.68 addrspace(1)*, %struct.Vector.69 addrspace(1)*, %struct.UV.76 addrspace(1)*, %struct.Spectrum.77 addrspace(1)*, %struct.Triangle.75 addrspace(1)*, %struct.Camera.90 addrspace(1)*, %struct.TriangleLight.91 addrspace(1)*, i32 addrspace(1)*)* @AdvancePaths, metadata !1}
!4 = metadata !{null, metadata !1}
!5 = metadata !{null, metadata !1}
!6 = metadata !{null, metadata !1}
!7 = metadata !{null, metadata !1}
!8 = metadata !{null, metadata !1}
!9 = metadata !{null, metadata !1}
!10 = metadata !{null, metadata !1}
!11 = metadata !{null}
!12 = metadata !{metadata !"clang version 3.5.0 (trunk 212264) (llvm/trunk 212275)"}
!13 = metadata !{metadata !"clang version 3.5.0 (trunk 212142) (llvm/trunk 212143)"}
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!48 = metadata !{float 2.500000e+00}
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!80 = metadata !{metadata !79, metadata !22, i64 520}

Shader Disassembly:

	ALU_PUSH_BEFORE 4, @0x4fc, KC0[CB0:0-32], KC1[]                                   ; 800004FC A4100000
	JUMP @0x286 POP:1                                                                 ; 00000286 82800001
	ALU 13, @0x501, KC0[CB0:0-32], KC1[]                                              ; 80000501 A0340000
	TEX 5 @0x288                                                                      ; 00000288 80401400
	ALU_PUSH_BEFORE 27, @0x50f, KC0[CB0:0-32], KC1[]                                  ; 8000050F A46C0000
	JUMP @0x85 POP:1                                                                  ; 00000085 82800001
	ALU 6, @0x52b, KC0[], KC1[]                                                       ; 0000052B A0180000
	TEX 6 @0x294                                                                      ; 00000294 80401800
	ALU 27, @0x532, KC0[], KC1[]                                                      ; 00000532 A06C0000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T16.X, 0                                       ; 08072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T17.X, 0                                       ; 0886A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T10.X, T15.X, 0                                       ; 07852020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T24.X, 0                                       ; 0C0BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T21.X, T22.X, 0                                       ; 0B0AA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T20.X, 0                                       ; 0A09A020 95C01000
	ALU 8, @0x54e, KC0[], KC1[]                                                       ; 0000054E A0200000
	TEX 3 @0x2a2                                                                      ; 000002A2 80400C00
	ALU 3, @0x557, KC0[], KC1[]                                                       ; 00000557 A00C0000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T18.X, 0                                       ; 09082020 95C01000
	ALU 6, @0x55b, KC0[], KC1[]                                                       ; 0000055B A0180000
	TEX 2 @0x2aa                                                                      ; 000002AA 80400800
	ALU 16, @0x562, KC0[], KC1[]                                                      ; 00000562 A0400000
	TEX 4 @0x2b0                                                                      ; 000002B0 80401000
	ALU 8, @0x573, KC0[], KC1[]                                                       ; 00000573 A0200000
	TEX 7 @0x2ba                                                                      ; 000002BA 80401C00
	ALU 27, @0x57c, KC0[], KC1[]                                                      ; 0000057C A06C0000
	TEX 6 @0x2ca                                                                      ; 000002CA 80401800
	ALU 26, @0x598, KC0[], KC1[]                                                      ; 00000598 A0680000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T23.X, 0                                       ; 0B882020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T22.X, 0                                       ; 0B072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T13.X, 0                                       ; 0687A020 95C01000
	ALU 0, @0x5b3, KC0[], KC1[]                                                       ; 000005B3 A0000000
	TEX 0 @0x2d8                                                                      ; 000002D8 80400000
	ALU_PUSH_BEFORE 7, @0x5b4, KC0[], KC1[]                                           ; 000005B4 A41C0000
	JUMP @44 POP:1                                                                    ; 0000002C 82800001
	ALU 1, @0x5bc, KC0[], KC1[]                                                       ; 000005BC A0040000
	TEX 1 @0x2da                                                                      ; 000002DA 80400400
	ALU 11, @0x5be, KC0[], KC1[]                                                      ; 000005BE A02C0000
	TEX 3 @0x2de                                                                      ; 000002DE 80400C00
	ALU 15, @0x5ca, KC0[], KC1[]                                                      ; 000005CA A03C0000
	TEX 6 @0x2e6                                                                      ; 000002E6 80401800
	ALU 26, @0x5da, KC0[], KC1[]                                                      ; 000005DA A0680000
	TEX 6 @0x2f4                                                                      ; 000002F4 80401800
	ALU_POP_AFTER 15, @0x5f5, KC0[], KC1[]                                            ; 000005F5 A83C0000
	TEX 0 @0x302                                                                      ; 00000302 80400000
	ALU_PUSH_BEFORE 4, @0x605, KC0[], KC1[]                                           ; 00000605 A4100000
	JUMP @53 POP:1                                                                    ; 00000035 82800001
	TEX 1 @0x304                                                                      ; 00000304 80400400
	ALU 14, @0x60a, KC0[], KC1[]                                                      ; 0000060A A0380000
	TEX 2 @0x308                                                                      ; 00000308 80400800
	ALU 4, @0x619, KC0[], KC1[]                                                       ; 00000619 A0100000
	TEX 2 @0x30e                                                                      ; 0000030E 80400800
	ALU_POP_AFTER 2, @0x61e, KC0[], KC1[]                                             ; 0000061E A8080000
	ALU 8, @0x621, KC0[], KC1[]                                                       ; 00000621 A0200000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T19.X, 0                                       ; 098BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T17.X, 0                                       ; 08892020 95C01000
	ALU 0, @0x62a, KC0[], KC1[]                                                       ; 0000062A A0000000
	TEX 0 @0x314                                                                      ; 00000314 80400000
	ALU 3, @0x62b, KC0[], KC1[]                                                       ; 0000062B A00C0000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T17.X, 0                                       ; 088BA020 95C01000
	ALU 20, @0x62f, KC0[], KC1[]                                                      ; 0000062F A0500000
	ALU 57, @0x644, KC0[], KC1[]                                                      ; 00000644 A0E40000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T37.X, 0                                       ; 1289A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T27.X, T36.X, 0                                       ; 120DA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T29.X, T35.X, 0                                       ; 118EA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T33.X, T34.X, 0                                       ; 1110A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T31.X, T32.X, 0                                       ; 100FA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T28.X, T30.X, 0                                       ; 0F0E2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T26.X, 0                                       ; 0D06A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T25.X, 0                                       ; 0C88A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T24.X, 0                                       ; 0C092020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T22.X, 0                                       ; 0B06A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T21.X, 0                                       ; 0A88A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T20.X, 0                                       ; 0A092020 95C01000
	ALU_PUSH_BEFORE 2, @0x67e, KC0[], KC1[]                                           ; 0000067E A4080000
	JUMP @0x84 POP:1                                                                  ; 00000084 82800001
	ALU 5, @0x681, KC0[], KC1[]                                                       ; 00000681 A0140000
	TEX 2 @0x316                                                                      ; 00000316 80400800
	PUSH @0x4f POP:1                                                                  ; 0000004F 82C00001
	ALU 4, @0x687, KC0[], KC1[]                                                       ; 00000687 A0100000
	JUMP @0x6f POP:1                                                                  ; 0000006F 82800001
	ALU 3, @0x68c, KC0[], KC1[]                                                       ; 0000068C A00C0000
	TEX 0 @0x31c                                                                      ; 0000031C 80400000
	ALU 2, @0x690, KC0[], KC1[]                                                       ; 00000690 A0080000
	TEX 1 @0x31e                                                                      ; 0000031E 80400400
	PUSH @0x56 POP:1                                                                  ; 00000056 82C00001
	ALU 5, @0x693, KC0[], KC1[]                                                       ; 00000693 A0140000
	JUMP @0x6e POP:1                                                                  ; 0000006E 82800001
	ALU 3, @0x699, KC0[], KC1[]                                                       ; 00000699 A00C0000
	TEX 0 @0x322                                                                      ; 00000322 80400000
	PUSH @0x5b POP:1                                                                  ; 0000005B 82C00001
	ALU 6, @0x69d, KC0[], KC1[]                                                       ; 0000069D A0180000
	JUMP @0x64 POP:1                                                                  ; 00000064 82800001
	PUSH @0x5e POP:1                                                                  ; 0000005E 82C00001
	ALU 3, @0x6a4, KC0[], KC1[]                                                       ; 000006A4 A00C0000
	JUMP @0x63 POP:1                                                                  ; 00000063 82800001
	ALU 2, @0x6a8, KC0[], KC1[]                                                       ; 000006A8 A0080000
	TEX 2 @0x324                                                                      ; 00000324 80400800
	ALU_POP_AFTER 3, @0x6ab, KC0[], KC1[]                                             ; 000006AB A80C0000
	ALU_POP_AFTER 1, @0x6af, KC0[], KC1[]                                             ; 000006AF A8040000
	PUSH @0x65 POP:1                                                                  ; 00000065 82C00001
	ALU 7, @0x6b1, KC0[], KC1[]                                                       ; 000006B1 A01C0000
	JUMP @0x68 POP:1                                                                  ; 00000068 82800001
	ALU_POP_AFTER 1, @0x6b9, KC0[], KC1[]                                             ; 000006B9 A8040000
	PUSH @0x69 POP:1                                                                  ; 00000069 82C00001
	ALU 1, @0x6bb, KC0[], KC1[]                                                       ; 000006BB A0040000
	JUMP @0x6d POP:1                                                                  ; 0000006D 82800001
	TEX 0 @0x32a                                                                      ; 0000032A 80400000
	ALU_POP_AFTER 5, @0x6bd, KC0[], KC1[]                                             ; 000006BD A8140000
	POP @0x6e POP:1                                                                   ; 0000006E 83800001
	POP @0x6f POP:1                                                                   ; 0000006F 83800001
	PUSH @0x70 POP:1                                                                  ; 00000070 82C00001
	ALU 6, @0x6c3, KC0[], KC1[]                                                       ; 000006C3 A0180000
	JUMP @0x83 POP:1                                                                  ; 00000083 82800001
	ALU 0, @0x6ca, KC0[], KC1[]                                                       ; 000006CA A0000000
	TEX 0 @0x32c                                                                      ; 0000032C 80400000
	PUSH @0x75 POP:1                                                                  ; 00000075 82C00001
	ALU 3, @0x6cb, KC0[], KC1[]                                                       ; 000006CB A00C0000
	JUMP @0x7a POP:1                                                                  ; 0000007A 82800001
	ALU 1, @0x6cf, KC0[], KC1[]                                                       ; 000006CF A0040000
	TEX 1 @0x32e                                                                      ; 0000032E 80400400
	ALU_POP_AFTER 13, @0x6d1, KC0[], KC1[]                                            ; 000006D1 A8340000
	ALU 0, @0x6df, KC0[], KC1[]                                                       ; 000006DF A0000000
	TEX 0 @0x332                                                                      ; 00000332 80400000
	ALU 5, @0x6e0, KC0[], KC1[]                                                       ; 000006E0 A0140000
	TEX 4 @0x334                                                                      ; 00000334 80401000
	ALU 14, @0x6e6, KC0[], KC1[]                                                      ; 000006E6 A0380000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T18.X, 0                                       ; 0908A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T16.X, 0                                       ; 0807A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T14.X, 0                                       ; 0706A020 95C01000
	POP @0x83 POP:1                                                                   ; 00000083 83800001
	POP @0x84 POP:1                                                                   ; 00000084 83800001
	ALU_POP_AFTER 2, @0x6f5, KC0[], KC1[]                                             ; 000006F5 A8080000
	ALU_PUSH_BEFORE 3, @0x6f8, KC0[], KC1[]                                           ; 000006F8 A40C0000
	JUMP @0xed POP:1                                                                  ; 000000ED 82800001
	ALU_PUSH_BEFORE 9, @0x6fc, KC0[], KC1[]                                           ; 000006FC A4240000
	JUMP @0x8a POP:1                                                                  ; 0000008A 82800001
	ALU_POP_AFTER 15, @0x706, KC0[], KC1[]                                            ; 00000706 A83C0000
	ALU_PUSH_BEFORE 2, @0x716, KC0[], KC1[]                                           ; 00000716 A4080000
	JUMP @0xeb POP:1                                                                  ; 000000EB 82800001
	PUSH @0x8d POP:1                                                                  ; 0000008D 82C00001
	ALU 3, @0x719, KC0[], KC1[]                                                       ; 00000719 A00C0000
	JUMP @0xea POP:1                                                                  ; 000000EA 82800001
	PUSH @0x90 POP:1                                                                  ; 00000090 82C00001
	ALU 3, @0x71d, KC0[], KC1[]                                                       ; 0000071D A00C0000
	JUMP @0xdd POP:1                                                                  ; 000000DD 82800001
	ALU 0, @0x721, KC0[], KC1[]                                                       ; 00000721 A0000000
	TEX 0 @0x33e                                                                      ; 0000033E 80400000
	ALU 3, @0x722, KC0[], KC1[]                                                       ; 00000722 A00C0000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T14.X, 0                                       ; 0706A020 95C01000
	ALU 6, @0x726, KC0[], KC1[]                                                       ; 00000726 A0180000
	TEX 6 @0x340                                                                      ; 00000340 80401800
	ALU 29, @0x72d, KC0[], KC1[]                                                      ; 0000072D A0740000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T17.X, 0                                       ; 0887A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T18.X, 0                                       ; 09072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T16.X, 0                                       ; 0806A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T24.X, T25.X, 0                                       ; 0C8C2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T23.X, 0                                       ; 0B8B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T20.X, T21.X, 0                                       ; 0A8A2020 95C01000
	ALU 8, @0x74b, KC0[], KC1[]                                                       ; 0000074B A0200000
	TEX 3 @0x34e                                                                      ; 0000034E 80400C00
	ALU 3, @0x754, KC0[], KC1[]                                                       ; 00000754 A00C0000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T17.X, 0                                       ; 08862020 95C01000
	ALU 6, @0x758, KC0[], KC1[]                                                       ; 00000758 A0180000
	TEX 2 @0x356                                                                      ; 00000356 80400800
	ALU 20, @0x75f, KC0[], KC1[]                                                      ; 0000075F A0500000
	TEX 4 @0x35c                                                                      ; 0000035C 80401000
	ALU 4, @0x774, KC0[], KC1[]                                                       ; 00000774 A0100000
	TEX 7 @0x366                                                                      ; 00000366 80401C00
	ALU 26, @0x779, KC0[], KC1[]                                                      ; 00000779 A0680000
	TEX 6 @0x376                                                                      ; 00000376 80401800
	ALU 26, @0x794, KC0[], KC1[]                                                      ; 00000794 A0680000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T21.X, 0                                       ; 0A87A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T18.X, 0                                       ; 0909A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T20.X, T17.X, 0                                       ; 088A2020 95C01000
	ALU 0, @0x7af, KC0[], KC1[]                                                       ; 000007AF A0000000
	TEX 0 @0x384                                                                      ; 00000384 80400000
	PUSH @0xb2 POP:1                                                                  ; 000000B2 82C00001
	ALU 3, @0x7b0, KC0[], KC1[]                                                       ; 000007B0 A00C0000
	JUMP @0xbd POP:1                                                                  ; 000000BD 82800001
	ALU 1, @0x7b4, KC0[], KC1[]                                                       ; 000007B4 A0040000
	TEX 1 @0x386                                                                      ; 00000386 80400400
	ALU 11, @0x7b6, KC0[], KC1[]                                                      ; 000007B6 A02C0000
	TEX 3 @0x38a                                                                      ; 0000038A 80400C00
	ALU 15, @0x7c2, KC0[], KC1[]                                                      ; 000007C2 A03C0000
	TEX 6 @0x392                                                                      ; 00000392 80401800
	ALU 26, @0x7d2, KC0[], KC1[]                                                      ; 000007D2 A0680000
	TEX 6 @0x3a0                                                                      ; 000003A0 80401800
	ALU_POP_AFTER 15, @0x7ed, KC0[], KC1[]                                            ; 000007ED A83C0000
	TEX 0 @0x3ae                                                                      ; 000003AE 80400000
	PUSH @0xbf POP:1                                                                  ; 000000BF 82C00001
	ALU 4, @0x7fd, KC0[], KC1[]                                                       ; 000007FD A0100000
	JUMP @0xc7 POP:1                                                                  ; 000000C7 82800001
	TEX 1 @0x3b0                                                                      ; 000003B0 80400400
	ALU 14, @0x802, KC0[], KC1[]                                                      ; 00000802 A0380000
	TEX 2 @0x3b4                                                                      ; 000003B4 80400800
	ALU 4, @0x811, KC0[], KC1[]                                                       ; 00000811 A0100000
	TEX 2 @0x3ba                                                                      ; 000003BA 80400800
	ALU_POP_AFTER 2, @0x816, KC0[], KC1[]                                             ; 00000816 A8080000
	ALU 8, @0x819, KC0[], KC1[]                                                       ; 00000819 A0200000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T13.X, 0                                       ; 06892020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T11.X, 0                                       ; 05862020 95C01000
	ALU 0, @0x822, KC0[], KC1[]                                                       ; 00000822 A0000000
	TEX 0 @0x3c0                                                                      ; 000003C0 80400000
	ALU 3, @0x823, KC0[], KC1[]                                                       ; 00000823 A00C0000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T12.X, 0                                       ; 0605A020 95C01000
	ALU 20, @0x827, KC0[], KC1[]                                                      ; 00000827 A0500000
	ALU 58, @0x83c, KC0[], KC1[]                                                      ; 0000083C A0E80000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T31.X, 0                                       ; 0F86A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T21.X, T30.X, 0                                       ; 0F0AA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T29.X, 0                                       ; 0E8BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T27.X, T28.X, 0                                       ; 0E0DA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T25.X, T26.X, 0                                       ; 0D0CA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T24.X, 0                                       ; 0C0B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T20.X, 0                                       ; 0A07A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T19.X, 0                                       ; 0985A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T18.X, 0                                       ; 09062020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T17.X, 0                                       ; 0887A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T16.X, 0                                       ; 0805A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T14.X, 0                                       ; 07062020 95C01000
	POP @0xdd POP:1                                                                   ; 000000DD 83800001
	PUSH @0xde POP:1                                                                  ; 000000DE 82C00001
	ALU 1, @0x877, KC0[], KC1[]                                                       ; 00000877 A0040000
	JUMP @0xe9 POP:1                                                                  ; 000000E9 82800001
	ALU 1, @0x879, KC0[], KC1[]                                                       ; 00000879 A0040000
	TEX 1 @0x3c2                                                                      ; 000003C2 80400400
	ALU 8, @0x87b, KC0[], KC1[]                                                       ; 0000087B A0200000
	TEX 3 @0x3c6                                                                      ; 000003C6 80400C00
	ALU 7, @0x884, KC0[], KC1[]                                                       ; 00000884 A01C0000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T16.X, 0                                       ; 0807A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T14.X, 0                                       ; 0706A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T12.X, 0                                       ; 0605A020 95C01000
	POP @0xe9 POP:1                                                                   ; 000000E9 83800001
	ALU_POP_AFTER 2, @0x88c, KC0[], KC1[]                                             ; 0000088C A8080000
	ALU_POP_AFTER 6, @0x88f, KC0[], KC1[]                                             ; 0000088F A8180000
	ALU 9, @0x896, KC0[], KC1[]                                                       ; 00000896 A0240000
	ALU_POP_AFTER 4, @0x8a0, KC0[], KC1[]                                             ; 000008A0 A8100000
	ALU_PUSH_BEFORE 1, @0x8a5, KC0[], KC1[]                                           ; 000008A5 A4040000
	JUMP @0x172 POP:1                                                                 ; 00000172 82800001
	ALU 0, @0x8a7, KC0[], KC1[]                                                       ; 000008A7 A0000000
	TEX 0 @0x3ce                                                                      ; 000003CE 80400000
	ALU 2, @0x8a8, KC0[], KC1[]                                                       ; 000008A8 A0080000
	TEX 0 @0x3d0                                                                      ; 000003D0 80400000
	ALU_PUSH_BEFORE 3, @0x8ab, KC0[], KC1[]                                           ; 000008AB A40C0000
	JUMP @0x171 POP:1                                                                 ; 00000171 82800001
	ALU 0x64, @0x8af, KC0[], KC1[]                                                    ; 000008AF A1900000
	TEX 11 @0x3d2                                                                     ; 000003D2 80402C00
	ALU 0x6a, @0x914, KC0[], KC1[]                                                    ; 00000914 A1A80000
	PUSH @0xf9 POP:1                                                                  ; 000000F9 82C00001
	ALU 0, @0x97f, KC0[], KC1[]                                                       ; 0000097F A0000000
	JUMP @0x12a POP:1                                                                 ; 0000012A 82800001
	ALU 6, @0x980, KC0[], KC1[]                                                       ; 00000980 A0180000
	TEX 6 @0x3ea                                                                      ; 000003EA 80401800
	ALU 0x45, @0x987, KC0[], KC1[]                                                    ; 00000987 A1140000
	MEM_RAT_CACHELESS STORE_RAW T41.X, T40.X, 0                                       ; 1414A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T39.X, T38.X, 0                                       ; 1313A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T37.X, T36.X, 0                                       ; 1212A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T35.X, 0                                       ; 1187A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T34.X, T33.X, 0                                       ; 10912020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T32.X, T23.X, 0                                       ; 0B902020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T21.X, T22.X, 0                                       ; 0B0AA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T20.X, 0                                       ; 0A09A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T12.X, 0                                       ; 06092020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T31.X, 0                                       ; 0F882020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T30.X, 0                                       ; 0F08A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T18.X, T29.X, 0                                       ; 0E892020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T28.X, 0                                       ; 0E082020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T27.X, 0                                       ; 0D88A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T25.X, T26.X, 0                                       ; 0D0CA020 95C01000
	TEX 0 @0x3f8                                                                      ; 000003F8 80400000
	ALU 2, @0x9cd, KC0[], KC1[]                                                       ; 000009CD A0080000
	TEX 0 @0x3fa                                                                      ; 000003FA 80400000
	PUSH @0x111 POP:1                                                                 ; 00000111 82C00001
	ALU 8, @0x9d0, KC0[], KC1[]                                                       ; 000009D0 A0200000
	JUMP @0x129 POP:1                                                                 ; 00000129 82800001
	ALU 3, @0x9d9, KC0[], KC1[]                                                       ; 000009D9 A00C0000
	TEX 0 @0x3fc                                                                      ; 000003FC 80400000
	PUSH @0x116 POP:1                                                                 ; 00000116 82C00001
	ALU 6, @0x9dd, KC0[], KC1[]                                                       ; 000009DD A0180000
	JUMP @0x11f POP:1                                                                 ; 0000011F 82800001
	PUSH @0x119 POP:1                                                                 ; 00000119 82C00001
	ALU 3, @0x9e4, KC0[], KC1[]                                                       ; 000009E4 A00C0000
	JUMP @0x11e POP:1                                                                 ; 0000011E 82800001
	ALU 2, @0x9e8, KC0[], KC1[]                                                       ; 000009E8 A0080000
	TEX 2 @0x3fe                                                                      ; 000003FE 80400800
	ALU_POP_AFTER 3, @0x9eb, KC0[], KC1[]                                             ; 000009EB A80C0000
	ALU_POP_AFTER 1, @0x9ef, KC0[], KC1[]                                             ; 000009EF A8040000
	PUSH @0x120 POP:1                                                                 ; 00000120 82C00001
	ALU 7, @0x9f1, KC0[], KC1[]                                                       ; 000009F1 A01C0000
	JUMP @0x123 POP:1                                                                 ; 00000123 82800001
	ALU_POP_AFTER 1, @0x9f9, KC0[], KC1[]                                             ; 000009F9 A8040000
	PUSH @0x124 POP:1                                                                 ; 00000124 82C00001
	ALU 1, @0x9fb, KC0[], KC1[]                                                       ; 000009FB A0040000
	JUMP @0x128 POP:1                                                                 ; 00000128 82800001
	TEX 0 @0x404                                                                      ; 00000404 80400000
	ALU_POP_AFTER 5, @0x9fd, KC0[], KC1[]                                             ; 000009FD A8140000
	POP @0x129 POP:1                                                                  ; 00000129 83800001
	POP @0x12a POP:1                                                                  ; 0000012A 83800001
	PUSH @0x12b POP:1                                                                 ; 0000012B 82C00001
	ALU 8, @0xa03, KC0[], KC1[]                                                       ; 00000A03 A0200000
	JUMP @0x170 POP:1                                                                 ; 00000170 82800001
	ALU 5, @0xa0c, KC0[], KC1[]                                                       ; 00000A0C A0140000
	TEX 5 @0x406                                                                      ; 00000406 80401400
	PUSH @0x130 POP:1                                                                 ; 00000130 82C00001
	ALU 21, @0xa12, KC0[], KC1[]                                                      ; 00000A12 A0540000
	JUMP @0x153 POP:1                                                                 ; 00000153 82800001
	TEX 0 @0x412                                                                      ; 00000412 80400000
	ALU 3, @0xa28, KC0[], KC1[]                                                       ; 00000A28 A00C0000
	TEX 0 @0x414                                                                      ; 00000414 80400000
	ALU 14, @0xa2c, KC0[], KC1[]                                                      ; 00000A2C A0380000
	PUSH @0x137 POP:1                                                                 ; 00000137 82C00001
	ALU 29, @0xa3b, KC0[], KC1[]                                                      ; 00000A3B A0740000
	JUMP @0x152 POP:1                                                                 ; 00000152 82800001
	ALU 0, @0xa59, KC0[], KC1[]                                                       ; 00000A59 A0000000
	TEX 1 @0x416                                                                      ; 00000416 80400400
	ALU 5, @0xa5a, KC0[], KC1[]                                                       ; 00000A5A A0140000
	TEX 2 @0x41a                                                                      ; 0000041A 80400800
	PUSH @0x13e POP:1                                                                 ; 0000013E 82C00001
	ALU 11, @0xa60, KC0[], KC1[]                                                      ; 00000A60 A02C0000
	JUMP @0x147 POP:1                                                                 ; 00000147 82800001
	PUSH @0x141 POP:1                                                                 ; 00000141 82C00001
	ALU 3, @0xa6c, KC0[], KC1[]                                                       ; 00000A6C A00C0000
	JUMP @0x146 POP:1                                                                 ; 00000146 82800001
	ALU 4, @0xa70, KC0[], KC1[]                                                       ; 00000A70 A0100000
	TEX 2 @0x420                                                                      ; 00000420 80400800
	ALU_POP_AFTER 3, @0xa75, KC0[], KC1[]                                             ; 00000A75 A80C0000
	ALU_POP_AFTER 1, @0xa79, KC0[], KC1[]                                             ; 00000A79 A8040000
	PUSH @0x148 POP:1                                                                 ; 00000148 82C00001
	ALU 7, @0xa7b, KC0[], KC1[]                                                       ; 00000A7B A01C0000
	JUMP @0x14b POP:1                                                                 ; 0000014B 82800001
	ALU_POP_AFTER 1, @0xa83, KC0[], KC1[]                                             ; 00000A83 A8040000
	PUSH @0x14c POP:1                                                                 ; 0000014C 82C00001
	ALU 1, @0xa85, KC0[], KC1[]                                                       ; 00000A85 A0040000
	JUMP @0x151 POP:1                                                                 ; 00000151 82800001
	ALU 2, @0xa87, KC0[], KC1[]                                                       ; 00000A87 A0080000
	TEX 0 @0x426                                                                      ; 00000426 80400000
	ALU_POP_AFTER 1, @0xa8a, KC0[], KC1[]                                             ; 00000A8A A8040000
	ALU_POP_AFTER 24, @0xa8c, KC0[], KC1[]                                            ; 00000A8C A8600000
	POP @0x153 POP:1                                                                  ; 00000153 83800001
	PUSH @0x154 POP:1                                                                 ; 00000154 82C00001
	ALU 10, @0xaa5, KC0[], KC1[]                                                      ; 00000AA5 A0280000
	JUMP @0x16f POP:1                                                                 ; 0000016F 82800001
	ALU 4, @0xab0, KC0[], KC1[]                                                       ; 00000AB0 A0100000
	TEX 2 @0x428                                                                      ; 00000428 80400800
	ALU 5, @0xab5, KC0[], KC1[]                                                       ; 00000AB5 A0140000
	TEX 2 @0x42e                                                                      ; 0000042E 80400800
	PUSH @0x15b POP:1                                                                 ; 0000015B 82C00001
	ALU 0, @0xabb, KC0[], KC1[]                                                       ; 00000ABB A0000000
	JUMP @0x15e POP:1                                                                 ; 0000015E 82800001
	ALU_POP_AFTER 6, @0xabc, KC0[], KC1[]                                             ; 00000ABC A8180000
	ALU 0x45, @0xac3, KC0[], KC1[]                                                    ; 00000AC3 A1140000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T16.X, 0                                       ; 08062020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T17.X, 0                                       ; 0889A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T18.X, 0                                       ; 0906A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T7.X, 0                                         ; 0382A020 95C01000
	ALU 1, @0xb09, KC0[], KC1[]                                                       ; 00000B09 A0040000
	TEX 2 @0x434                                                                      ; 00000434 80400800
	ALU 0x48, @0xb0b, KC0[], KC1[]                                                    ; 00000B0B A1200000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T24.X, 0                                       ; 0C062020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T7.X, T23.X, 0                                        ; 0B83A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T10.X, T22.X, 0                                       ; 0B052020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T21.X, 0                                       ; 0A85A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T20.X, 0                                       ; 0A072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T19.X, 0                                       ; 0987A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T18.X, 0                                       ; 0906A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T16.X, T17.X, 0                                       ; 08882020 95C01000
	POP @0x16f POP:1                                                                  ; 0000016F 83800001
	POP @0x170 POP:1                                                                  ; 00000170 83800001
	ALU_POP_AFTER 0, @0xb54, KC0[], KC1[]                                             ; 00000B54 A8000000
	POP @0x172 POP:1                                                                  ; 00000172 83800001
	ALU_PUSH_BEFORE 3, @0xb55, KC0[], KC1[]                                           ; 00000B55 A40C0000
	JUMP @0x238 POP:1                                                                 ; 00000238 82800001
	ALU_PUSH_BEFORE 3, @0xb59, KC0[], KC1[]                                           ; 00000B59 A40C0000
	JUMP @0x237 POP:1                                                                 ; 00000237 82800001
	ALU 0x4a, @0xb5d, KC0[], KC1[]                                                    ; 00000B5D A1280000
	TEX 3 @0x43a                                                                      ; 0000043A 80400C00
	ALU 2, @0xba8, KC0[], KC1[]                                                       ; 00000BA8 A0080000
	TEX 4 @0x442                                                                      ; 00000442 80401000
	ALU 6, @0xbab, KC0[], KC1[]                                                       ; 00000BAB A0180000
	TEX 5 @0x44c                                                                      ; 0000044C 80401400
	PUSH @0x17d POP:1                                                                 ; 0000017D 82C00001
	ALU 19, @0xbb2, KC0[], KC1[]                                                      ; 00000BB2 A04C0000
	JUMP @0x1fb POP:1                                                                 ; 000001FB 82800001
	PUSH @0x180 POP:1                                                                 ; 00000180 82C00001
	ALU 3, @0xbc6, KC0[], KC1[]                                                       ; 00000BC6 A00C0000
	JUMP @0x1fa POP:1                                                                 ; 000001FA 82800001
	ALU 3, @0xbca, KC0[], KC1[]                                                       ; 00000BCA A00C0000
	TEX 0 @0x458                                                                      ; 00000458 80400000
	ALU 2, @0xbce, KC0[], KC1[]                                                       ; 00000BCE A0080000
	TEX 0 @0x45a                                                                      ; 0000045A 80400000
	PUSH @0x187 POP:1                                                                 ; 00000187 82C00001
	ALU 6, @0xbd1, KC0[], KC1[]                                                       ; 00000BD1 A0180000
	JUMP @0x190 POP:1                                                                 ; 00000190 82800001
	PUSH @0x18a POP:1                                                                 ; 0000018A 82C00001
	ALU 3, @0xbd8, KC0[], KC1[]                                                       ; 00000BD8 A00C0000
	JUMP @0x18f POP:1                                                                 ; 0000018F 82800001
	ALU 4, @0xbdc, KC0[], KC1[]                                                       ; 00000BDC A0100000
	TEX 2 @0x45c                                                                      ; 0000045C 80400800
	ALU_POP_AFTER 3, @0xbe1, KC0[], KC1[]                                             ; 00000BE1 A80C0000
	ALU_POP_AFTER 1, @0xbe5, KC0[], KC1[]                                             ; 00000BE5 A8040000
	PUSH @0x191 POP:1                                                                 ; 00000191 82C00001
	ALU 7, @0xbe7, KC0[], KC1[]                                                       ; 00000BE7 A01C0000
	JUMP @0x194 POP:1                                                                 ; 00000194 82800001
	ALU_POP_AFTER 1, @0xbef, KC0[], KC1[]                                             ; 00000BEF A8040000
	PUSH @0x195 POP:1                                                                 ; 00000195 82C00001
	ALU 1, @0xbf1, KC0[], KC1[]                                                       ; 00000BF1 A0040000
	JUMP @0x19a POP:1                                                                 ; 0000019A 82800001
	ALU 2, @0xbf3, KC0[], KC1[]                                                       ; 00000BF3 A0080000
	TEX 0 @0x462                                                                      ; 00000462 80400000
	ALU_POP_AFTER 1, @0xbf6, KC0[], KC1[]                                             ; 00000BF6 A8040000
	ALU 0, @0xbf8, KC0[], KC1[]                                                       ; 00000BF8 A0000000
	TEX 0 @0x464                                                                      ; 00000464 80400000
	ALU 2, @0xbf9, KC0[], KC1[]                                                       ; 00000BF9 A0080000
	TEX 0 @0x466                                                                      ; 00000466 80400000
	PUSH @0x19f POP:1                                                                 ; 0000019F 82C00001
	ALU 24, @0xbfc, KC0[], KC1[]                                                      ; 00000BFC A0600000
	JUMP @0x1a8 POP:1                                                                 ; 000001A8 82800001
	PUSH @0x1a2 POP:1                                                                 ; 000001A2 82C00001
	ALU 3, @0xc15, KC0[], KC1[]                                                       ; 00000C15 A00C0000
	JUMP @0x1a7 POP:1                                                                 ; 000001A7 82800001
	ALU 4, @0xc19, KC0[], KC1[]                                                       ; 00000C19 A0100000
	TEX 2 @0x468                                                                      ; 00000468 80400800
	ALU_POP_AFTER 3, @0xc1e, KC0[], KC1[]                                             ; 00000C1E A80C0000
	ALU_POP_AFTER 1, @0xc22, KC0[], KC1[]                                             ; 00000C22 A8040000
	PUSH @0x1a9 POP:1                                                                 ; 000001A9 82C00001
	ALU 7, @0xc24, KC0[], KC1[]                                                       ; 00000C24 A01C0000
	JUMP @0x1ac POP:1                                                                 ; 000001AC 82800001
	ALU_POP_AFTER 1, @0xc2c, KC0[], KC1[]                                             ; 00000C2C A8040000
	PUSH @0x1ad POP:1                                                                 ; 000001AD 82C00001
	ALU 1, @0xc2e, KC0[], KC1[]                                                       ; 00000C2E A0040000
	JUMP @0x1b2 POP:1                                                                 ; 000001B2 82800001
	ALU 2, @0xc30, KC0[], KC1[]                                                       ; 00000C30 A0080000
	TEX 0 @0x46e                                                                      ; 0000046E 80400000
	ALU_POP_AFTER 1, @0xc33, KC0[], KC1[]                                             ; 00000C33 A8040000
	PUSH @0x1b3 POP:1                                                                 ; 000001B3 82C00001
	ALU 37, @0xc35, KC0[], KC1[]                                                      ; 00000C35 A0940000
	JUMP @0x1f9 POP:1                                                                 ; 000001F9 82800001
	ALU 0, @0xc5b, KC0[], KC1[]                                                       ; 00000C5B A0000000
	TEX 0 @0x470                                                                      ; 00000470 80400000
	ALU 2, @0xc5c, KC0[], KC1[]                                                       ; 00000C5C A0080000
	TEX 0 @0x472                                                                      ; 00000472 80400000
	PUSH @0x1ba POP:1                                                                 ; 000001BA 82C00001
	ALU 6, @0xc5f, KC0[], KC1[]                                                       ; 00000C5F A0180000
	JUMP @0x1c3 POP:1                                                                 ; 000001C3 82800001
	PUSH @0x1bd POP:1                                                                 ; 000001BD 82C00001
	ALU 3, @0xc66, KC0[], KC1[]                                                       ; 00000C66 A00C0000
	JUMP @0x1c2 POP:1                                                                 ; 000001C2 82800001
	ALU 4, @0xc6a, KC0[], KC1[]                                                       ; 00000C6A A0100000
	TEX 2 @0x474                                                                      ; 00000474 80400800
	ALU_POP_AFTER 6, @0xc6f, KC0[], KC1[]                                             ; 00000C6F A8180000
	ALU_POP_AFTER 1, @0xc76, KC0[], KC1[]                                             ; 00000C76 A8040000
	PUSH @0x1c4 POP:1                                                                 ; 000001C4 82C00001
	ALU 7, @0xc78, KC0[], KC1[]                                                       ; 00000C78 A01C0000
	JUMP @0x1c7 POP:1                                                                 ; 000001C7 82800001
	ALU_POP_AFTER 1, @0xc80, KC0[], KC1[]                                             ; 00000C80 A8040000
	PUSH @0x1c8 POP:1                                                                 ; 000001C8 82C00001
	ALU 1, @0xc82, KC0[], KC1[]                                                       ; 00000C82 A0040000
	JUMP @0x1cd POP:1                                                                 ; 000001CD 82800001
	ALU 2, @0xc84, KC0[], KC1[]                                                       ; 00000C84 A0080000
	TEX 0 @0x47a                                                                      ; 0000047A 80400000
	POP @0x1cd POP:1                                                                  ; 000001CD 83800001
	TEX 0 @0x47c                                                                      ; 0000047C 80400000
	ALU 2, @0xc87, KC0[], KC1[]                                                       ; 00000C87 A0080000
	TEX 0 @0x47e                                                                      ; 0000047E 80400000
	PUSH @0x1d1 POP:1                                                                 ; 000001D1 82C00001
	ALU 6, @0xc8a, KC0[], KC1[]                                                       ; 00000C8A A0180000
	JUMP @0x1da POP:1                                                                 ; 000001DA 82800001
	PUSH @0x1d4 POP:1                                                                 ; 000001D4 82C00001
	ALU 3, @0xc91, KC0[], KC1[]                                                       ; 00000C91 A00C0000
	JUMP @0x1d9 POP:1                                                                 ; 000001D9 82800001
	ALU 4, @0xc95, KC0[], KC1[]                                                       ; 00000C95 A0100000
	TEX 2 @0x480                                                                      ; 00000480 80400800
	ALU_POP_AFTER 6, @0xc9a, KC0[], KC1[]                                             ; 00000C9A A8180000
	ALU_POP_AFTER 1, @0xca1, KC0[], KC1[]                                             ; 00000CA1 A8040000
	PUSH @0x1db POP:1                                                                 ; 000001DB 82C00001
	ALU 7, @0xca3, KC0[], KC1[]                                                       ; 00000CA3 A01C0000
	JUMP @0x1de POP:1                                                                 ; 000001DE 82800001
	ALU_POP_AFTER 1, @0xcab, KC0[], KC1[]                                             ; 00000CAB A8040000
	PUSH @0x1df POP:1                                                                 ; 000001DF 82C00001
	ALU 1, @0xcad, KC0[], KC1[]                                                       ; 00000CAD A0040000
	JUMP @0x1e4 POP:1                                                                 ; 000001E4 82800001
	ALU 2, @0xcaf, KC0[], KC1[]                                                       ; 00000CAF A0080000
	TEX 0 @0x486                                                                      ; 00000486 80400000
	POP @0x1e4 POP:1                                                                  ; 000001E4 83800001
	PUSH @0x1e5 POP:1                                                                 ; 000001E5 82C00001
	ALU 23, @0xcb2, KC0[], KC1[]                                                      ; 00000CB2 A05C0000
	JUMP @0x1ec POP:1                                                                 ; 000001EC 82800001
	PUSH @0x1e8 POP:1                                                                 ; 000001E8 82C00001
	ALU 14, @0xcca, KC0[], KC1[]                                                      ; 00000CCA A0380000
	JUMP @0x1eb POP:1                                                                 ; 000001EB 82800001
	ALU_POP_AFTER 24, @0xcd9, KC0[], KC1[]                                            ; 00000CD9 A8600000
	ALU_POP_AFTER 9, @0xcf2, KC0[], KC1[]                                             ; 00000CF2 A8240000
	PUSH @0x1ed POP:1                                                                 ; 000001ED 82C00001
	ALU 1, @0xcfc, KC0[], KC1[]                                                       ; 00000CFC A0040000
	JUMP @0x1f8 POP:1                                                                 ; 000001F8 82800001
	PUSH @0x1f0 POP:1                                                                 ; 000001F0 82C00001
	ALU 8, @0xcfe, KC0[], KC1[]                                                       ; 00000CFE A0200000
	JUMP @0x1f7 POP:1                                                                 ; 000001F7 82800001
	PUSH @0x1f3 POP:1                                                                 ; 000001F3 82C00001
	ALU 24, @0xd07, KC0[], KC1[]                                                      ; 00000D07 A0600000
	JUMP @0x1f6 POP:1                                                                 ; 000001F6 82800001
	ALU_POP_AFTER 23, @0xd20, KC0[], KC1[]                                            ; 00000D20 A85C0000
	ALU_POP_AFTER 14, @0xd38, KC0[], KC1[]                                            ; 00000D38 A8380000
	ALU_POP_AFTER 4, @0xd47, KC0[], KC1[]                                             ; 00000D47 A8100000
	ALU_POP_AFTER 6, @0xd4c, KC0[], KC1[]                                             ; 00000D4C A8180000
	POP @0x1fa POP:1                                                                  ; 000001FA 83800001
	ALU_POP_AFTER 1, @0xd53, KC0[], KC1[]                                             ; 00000D53 A8040000
	PUSH @0x1fc POP:1                                                                 ; 000001FC 82C00001
	ALU 7, @0xd55, KC0[], KC1[]                                                       ; 00000D55 A01C0000
	JUMP @0x1ff POP:1                                                                 ; 000001FF 82800001
	ALU_POP_AFTER 5, @0xd5d, KC0[], KC1[]                                             ; 00000D5D A8140000
	PUSH @0x200 POP:1                                                                 ; 00000200 82C00001
	ALU 1, @0xd63, KC0[], KC1[]                                                       ; 00000D63 A0040000
	JUMP @0x235 POP:1                                                                 ; 00000235 82800001
	PUSH @0x203 POP:1                                                                 ; 00000203 82C00001
	ALU 6, @0xd65, KC0[], KC1[]                                                       ; 00000D65 A0180000
	JUMP @0x234 POP:1                                                                 ; 00000234 82800001
	PUSH @0x206 POP:1                                                                 ; 00000206 82C00001
	ALU 19, @0xd6c, KC0[], KC1[]                                                      ; 00000D6C A04C0000
	JUMP @0x217 POP:1                                                                 ; 00000217 82800001
	PUSH @0x209 POP:1                                                                 ; 00000209 82C00001
	ALU 7, @0xd80, KC0[], KC1[]                                                       ; 00000D80 A01C0000
	JUMP @0x211 POP:1                                                                 ; 00000211 82800001
	ALU 12, @0xd88, KC0[], KC1[]                                                      ; 00000D88 A0300000
	PUSH @0x20d POP:1                                                                 ; 0000020D 82C00001
	ALU 2, @0xd95, KC0[], KC1[]                                                       ; 00000D95 A0080000
	JUMP @0x210 POP:1                                                                 ; 00000210 82800001
	ALU_POP_AFTER 6, @0xd98, KC0[], KC1[]                                             ; 00000D98 A8180000
	ALU_POP_AFTER 1, @0xd9f, KC0[], KC1[]                                             ; 00000D9F A8040000
	PUSH @0x212 POP:1                                                                 ; 00000212 82C00001
	ALU 1, @0xda1, KC0[], KC1[]                                                       ; 00000DA1 A0040000
	JUMP @0x216 POP:1                                                                 ; 00000216 82800001
	ALU 12, @0xda3, KC0[], KC1[]                                                      ; 00000DA3 A0300000
	ALU_POP_AFTER 6, @0xdb0, KC0[], KC1[]                                             ; 00000DB0 A8180000
	ALU_POP_AFTER 10, @0xdb7, KC0[], KC1[]                                            ; 00000DB7 A8280000
	PUSH @0x218 POP:1                                                                 ; 00000218 82C00001
	ALU 20, @0xdc2, KC0[], KC1[]                                                      ; 00000DC2 A0500000
	JUMP @0x233 POP:1                                                                 ; 00000233 82800001
	ALU 2, @0xdd7, KC0[], KC1[]                                                       ; 00000DD7 A0080000
	TEX 0 @0x488                                                                      ; 00000488 80400000
	ALU 2, @0xdda, KC0[], KC1[]                                                       ; 00000DDA A0080000
	TEX 0 @0x48a                                                                      ; 0000048A 80400000
	PUSH @0x21f POP:1                                                                 ; 0000021F 82C00001
	ALU 6, @0xddd, KC0[], KC1[]                                                       ; 00000DDD A0180000
	JUMP @0x228 POP:1                                                                 ; 00000228 82800001
	PUSH @0x222 POP:1                                                                 ; 00000222 82C00001
	ALU 3, @0xde4, KC0[], KC1[]                                                       ; 00000DE4 A00C0000
	JUMP @0x227 POP:1                                                                 ; 00000227 82800001
	ALU 4, @0xde8, KC0[], KC1[]                                                       ; 00000DE8 A0100000
	TEX 2 @0x48c                                                                      ; 0000048C 80400800
	ALU_POP_AFTER 3, @0xded, KC0[], KC1[]                                             ; 00000DED A80C0000
	ALU_POP_AFTER 1, @0xdf1, KC0[], KC1[]                                             ; 00000DF1 A8040000
	PUSH @0x229 POP:1                                                                 ; 00000229 82C00001
	ALU 7, @0xdf3, KC0[], KC1[]                                                       ; 00000DF3 A01C0000
	JUMP @0x22c POP:1                                                                 ; 0000022C 82800001
	ALU_POP_AFTER 1, @0xdfb, KC0[], KC1[]                                             ; 00000DFB A8040000
	PUSH @0x22d POP:1                                                                 ; 0000022D 82C00001
	ALU 1, @0xdfd, KC0[], KC1[]                                                       ; 00000DFD A0040000
	JUMP @0x232 POP:1                                                                 ; 00000232 82800001
	ALU 2, @0xdff, KC0[], KC1[]                                                       ; 00000DFF A0080000
	TEX 0 @0x492                                                                      ; 00000492 80400000
	ALU_POP_AFTER 1, @0xe02, KC0[], KC1[]                                             ; 00000E02 A8040000
	ALU_POP_AFTER 25, @0xe04, KC0[], KC1[]                                            ; 00000E04 A8640000
	POP @0x234 POP:1                                                                  ; 00000234 83800001
	POP @0x235 POP:1                                                                  ; 00000235 83800001
	ALU 25, @0xe1e, KC0[], KC1[]                                                      ; 00000E1E A0640000
	ALU_POP_AFTER 64, @0xe38, KC0[], KC1[]                                            ; 00000E38 A9000000
	ALU_POP_AFTER 2, @0xe79, KC0[], KC1[]                                             ; 00000E79 A8080000
	ALU_PUSH_BEFORE 4, @0xe7c, KC0[], KC1[]                                           ; 00000E7C A4100000
	JUMP @0x263 POP:1                                                                 ; 00000263 82800001
	ALU 14, @0xe81, KC0[CB0:0-32], KC1[]                                              ; 80000E81 A0380000
	TEX 1 @0x494                                                                      ; 00000494 80400400
	ALU 0x63, @0xe90, KC0[CB0:0-32], KC1[]                                            ; 80000E90 A18C0000
	TEX 6 @0x498                                                                      ; 00000498 80401800
	ALU 8, @0xef4, KC0[], KC1[]                                                       ; 00000EF4 A0200000
	MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T22.X, 0                                    ; 0B082020 95C0F000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T6.X, 0                                        ; 030BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T15.X, 0                                       ; 07872020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T7.XY, T13.X, 0                                       ; 0683A020 95C03000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T9.X, 0                                        ; 0485A020 95C01000
	ALU 4, @0xefd, KC0[CB0:0-32], KC1[]                                               ; 80000EFD A0100000
	TEX 0 @0x4a6                                                                      ; 000004A6 80400000
	ALU 2, @0xf02, KC0[], KC1[]                                                       ; 00000F02 A0080000
	MEM_RAT_CACHELESS STORE_RAW T7.X, T6.X, 0                                         ; 0303A020 95C01000
	ALU 16, @0xf05, KC0[CB0:0-32], KC1[]                                              ; 80000F05 A0400000
	TEX 6 @0x4a8                                                                      ; 000004A8 80401800
	ALU 16, @0xf16, KC0[], KC1[]                                                      ; 00000F16 A0400000
	TEX 8 @0x4b6                                                                      ; 000004B6 80402000
	ALU 13, @0xf27, KC0[], KC1[]                                                      ; 00000F27 A0340000
	TEX 8 @0x4c8                                                                      ; 000004C8 80402000
	ALU 33, @0xf35, KC0[], KC1[]                                                      ; 00000F35 A0840000
	TEX 10 @0x4da                                                                     ; 000004DA 80402800
	ALU 39, @0xf57, KC0[], KC1[]                                                      ; 00000F57 A09C0000
	MEM_RAT_CACHELESS STORE_RAW T17.X, T18.X, 0                                       ; 0908A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T16.X, 0                                       ; 08072020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T7.X, 0                                        ; 0386A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T28.X, T15.X, 0                                       ; 078E2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T8.X, 0                                        ; 040BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T9.X, T22.X, 0                                        ; 0B04A020 95C01000
	ALU 0x63, @0xf7f, KC0[], KC1[]                                                    ; 00000F7F A18C0000
	MEM_RAT_CACHELESS STORE_RAW T27.X, T28.X, 0                                       ; 0E0DA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T12.X, T26.X, 0                                       ; 0D062020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T25.X, 0                                       ; 0C85A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T24.X, 0                                       ; 0C0BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T18.X, 0                                       ; 090B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T17.X, 0                                       ; 088B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T16.X, 0                                       ; 080B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T22.X, T15.X, 0                                       ; 078B2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T23.X, T14.X, 0                                       ; 070BA020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T6.X, T13.X, 0                                        ; 06832020 95C01000
	POP @0x263 POP:1                                                                  ; 00000263 83800001
	ALU_PUSH_BEFORE 1, @0xfe3, KC0[], KC1[]                                           ; 00000FE3 A4040000
	JUMP @0x27c POP:1                                                                 ; 0000027C 82800001
	ALU 6, @0xfe5, KC0[], KC1[]                                                       ; 00000FE5 A0180000
	TEX 2 @0x4f0                                                                      ; 000004F0 80400800
	ALU 19, @0xfec, KC0[], KC1[]                                                      ; 00000FEC A04C0000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T14.X, 0                                       ; 0705A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T6.X, T13.X, 0                                        ; 06832020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T12.X, 0                                        ; 0602A020 95C01000
	ALU 2, @0x1000, KC0[], KC1[]                                                      ; 00001000 A0080000
	TEX 2 @0x4f6                                                                      ; 000004F6 80400800
	ALU 20, @0x1003, KC0[], KC1[]                                                     ; 00001003 A0500000
	MEM_RAT_CACHELESS STORE_RAW T11.X, T21.X, 0                                       ; 0A85A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T6.X, T18.X, 0                                        ; 09032020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T17.X, 0                                        ; 0882A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T19.X, T16.X, 0                                       ; 0809A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T14.X, 0                                       ; 0707A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T13.X, T12.X, 0                                       ; 0606A020 95C01000
	ALU 0x56, @0x1018, KC0[], KC1[]                                                   ; 00001018 A1580000
	MEM_RAT_CACHELESS STORE_RAW T15.X, T2.X, 0                                        ; 0107A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T14.X, T13.X, 0                                       ; 06872020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T1.X, T12.X, 0                                        ; 0600A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T20.X, T11.X, 0                                       ; 058A2020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T10.X, T6.X, 0                                        ; 03052020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T3.X, T4.X, 0                                         ; 0201A020 95C01000
	POP @0x27c POP:1                                                                  ; 0000027C 83800001
	ALU_PUSH_BEFORE 4, @0x106f, KC0[], KC1[]                                          ; 0000106F A4100000
	JUMP @0x281 POP:1                                                                 ; 00000281 82800001
	ALU 4, @0x1074, KC0[], KC1[]                                                      ; 00001074 A0100000
	MEM_RAT_CACHELESS STORE_RAW T5.X, T1.X, 0                                         ; 0082A020 95C01000
	POP @0x281 POP:1                                                                  ; 00000281 83800001
	ALU 4, @0x1079, KC0[], KC1[]                                                      ; 00001079 A0100000
	MEM_RAT_CACHELESS STORE_RAW T9.X, T0.X, 0                                         ; 0004A020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T8.X, T2.X, 0                                         ; 01042020 95C01000
	MEM_RAT_CACHELESS STORE_RAW T7.X, T1.X, 0                                         ; 0083A020 95C01000
	POP @0x286 POP:1                                                                  ; 00000286 83800001
	CF_END                                                                            ; 00000000 80200000
	PAD                                                                               ; 00000000 00000000
	Fetch clause starting at 0x288:                                                   ; 
	VTX_READ_32 T3.X, T3.X, 8                                                         ; 10030140 135FF003 00080008 00000000
	VTX_READ_32 T7.X, T7.X, 4                                                         ; 10070140 135FF007 00080004 00000000
	VTX_READ_32 T4.X, T4.X, 0                                                         ; 10040140 135FF004 00080000 00000000
	VTX_READ_32 T1.X, T1.X, 28                                                        ; 10010140 135FF001 0008001C 00000000
	VTX_READ_32 T12.X, T12.X, 12                                                      ; 100C0140 135FF00C 0008000C 00000000
	VTX_READ_32 T5.X, T5.X, 24                                                        ; 10050140 135FF005 00080018 00000000
	Fetch clause starting at 0x294:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 0                                                       ; 10120140 135FF012 00080000 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	VTX_READ_32 T16.X, T16.X, 0                                                       ; 10100140 135FF010 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 8                                                       ; 100F0140 135FF00F 00080008 00000000
	VTX_READ_32 T14.X, T14.X, 12                                                      ; 100E0140 135FF00E 0008000C 00000000
	VTX_READ_32 T13.X, T13.X, 16                                                      ; 100D0140 135FF00D 00080010 00000000
	VTX_READ_32 T10.X, T10.X, 20                                                      ; 100A0140 135FF00A 00080014 00000000
	Fetch clause starting at 0x2a2:                                                   ; 
	VTX_READ_32 T16.X, T16.X, 0                                                       ; 10100140 135FF010 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 20                                                      ; 100F0140 135FF00F 00080014 00000000
	VTX_READ_32 T14.X, T14.X, 0                                                       ; 100E0140 135FF00E 00080000 00000000
	VTX_READ_32 T13.X, T13.X, 16                                                      ; 100D0140 135FF00D 00080010 00000000
	Fetch clause starting at 0x2aa:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 8                                                       ; 10130140 135FF013 00080008 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	VTX_READ_32 T13.X, T13.X, 4                                                       ; 100D0140 135FF00D 00080004 00000000
	Fetch clause starting at 0x2b0:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 0                                                       ; 10170140 135FF017 00080000 00000000
	VTX_READ_32 T21.X, T21.X, 8                                                       ; 10150140 135FF015 00080008 00000000
	VTX_READ_32 T16.X, T16.X, 8                                                       ; 10100140 135FF010 00080008 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	VTX_READ_32 T14.X, T14.X, 0                                                       ; 100E0140 135FF00E 00080000 00000000
	Fetch clause starting at 0x2ba:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 0x5c                                                    ; 100F0140 135FF00F 0008005C 00000000
	VTX_READ_32 T27.X, T27.X, 0x58                                                    ; 101B0140 135FF01B 00080058 00000000
	VTX_READ_32 T26.X, T26.X, 0x68                                                    ; 101A0140 135FF01A 00080068 00000000
	VTX_READ_32 T25.X, T25.X, 0x6c                                                    ; 10190140 135FF019 0008006C 00000000
	VTX_READ_32 T24.X, T24.X, 4                                                       ; 10180140 135FF018 00080004 00000000
	VTX_READ_32 T13.X, T13.X, 8                                                       ; 100D0140 135FF00D 00080008 00000000
	VTX_READ_32 T22.X, T22.X, 4                                                       ; 10160140 135FF016 00080004 00000000
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x2ca:                                                   ; 
	VTX_READ_32 T21.X, T21.X, 8                                                       ; 10150140 135FF015 00080008 00000000
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	VTX_READ_32 T23.X, T23.X, 0x80                                                    ; 10170140 135FF017 00080080 00000000
	VTX_READ_32 T22.X, T22.X, 0x78                                                    ; 10160140 135FF016 00080078 00000000
	VTX_READ_32 T16.X, T16.X, 0x60                                                    ; 10100140 135FF010 00080060 00000000
	VTX_READ_32 T14.X, T14.X, 0x70                                                    ; 100E0140 135FF00E 00080070 00000000
	VTX_READ_32 T13.X, T13.X, 0x7c                                                    ; 100D0140 135FF00D 0008007C 00000000
	Fetch clause starting at 0x2d8:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 4                                                       ; 10170140 135FF017 00080004 00000000
	Fetch clause starting at 0x2da:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 0                                                       ; 10180140 135FF018 00080000 00000000
	VTX_READ_32 T13.X, T13.X, 0                                                       ; 100D0140 135FF00D 00080000 00000000
	Fetch clause starting at 0x2de:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 4                                                       ; 101C0140 135FF01C 00080004 00000000
	VTX_READ_32 T27.X, T27.X, 0                                                       ; 101B0140 135FF01B 00080000 00000000
	VTX_READ_32 T24.X, T24.X, 0                                                       ; 10180140 135FF018 00080000 00000000
	VTX_READ_32 T25.X, T25.X, 4                                                       ; 10190140 135FF019 00080004 00000000
	Fetch clause starting at 0x2e6:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 0                                                       ; 10180140 135FF018 00080000 00000000
	VTX_READ_32 T31.X, T31.X, 0                                                       ; 101F0140 135FF01F 00080000 00000000
	VTX_READ_32 T23.X, T23.X, 8                                                       ; 10170140 135FF017 00080008 00000000
	VTX_READ_32 T30.X, T30.X, 0                                                       ; 101E0140 135FF01E 00080000 00000000
	VTX_READ_32 T26.X, T26.X, 8                                                       ; 101A0140 135FF01A 00080008 00000000
	VTX_READ_32 T13.X, T13.X, 8                                                       ; 100D0140 135FF00D 00080008 00000000
	VTX_READ_32 T29.X, T29.X, 4                                                       ; 101D0140 135FF01D 00080004 00000000
	Fetch clause starting at 0x2f4:                                                   ; 
	VTX_READ_32 T29.X, T29.X, 0                                                       ; 101D0140 135FF01D 00080000 00000000
	VTX_READ_32 T28.X, T28.X, 0                                                       ; 101C0140 135FF01C 00080000 00000000
	VTX_READ_32 T27.X, T27.X, 0                                                       ; 101B0140 135FF01B 00080000 00000000
	VTX_READ_32 T26.X, T26.X, 0                                                       ; 101A0140 135FF01A 00080000 00000000
	VTX_READ_32 T25.X, T25.X, 0                                                       ; 10190140 135FF019 00080000 00000000
	VTX_READ_32 T23.X, T23.X, 0                                                       ; 10170140 135FF017 00080000 00000000
	VTX_READ_32 T13.X, T13.X, 0                                                       ; 100D0140 135FF00D 00080000 00000000
	Fetch clause starting at 0x302:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 8                                                       ; 10110140 135FF011 00080008 00000000
	Fetch clause starting at 0x304:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 0                                                       ; 10120140 135FF012 00080000 00000000
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	Fetch clause starting at 0x308:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 4                                                       ; 10120140 135FF012 00080004 00000000
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	VTX_READ_32 T22.X, T22.X, 4                                                       ; 10160140 135FF016 00080004 00000000
	Fetch clause starting at 0x30e:                                                   ; 
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	VTX_READ_32 T24.X, T24.X, 0                                                       ; 10180140 135FF018 00080000 00000000
	VTX_READ_32 T19.X, T19.X, 4                                                       ; 10130140 135FF013 00080004 00000000
	Fetch clause starting at 0x314:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 0                                                       ; 10170140 135FF017 00080000 00000000
	Fetch clause starting at 0x316:                                                   ; 
	VTX_READ_32 T21.X, T21.X, 8                                                       ; 10150140 135FF015 00080008 00000000
	VTX_READ_32 T20.X, T20.X, 0                                                       ; 10140140 135FF014 00080000 00000000
	VTX_READ_32 T22.X, T22.X, 4                                                       ; 10160140 135FF016 00080004 00000000
	Fetch clause starting at 0x31c:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 64                                                      ; 100F0140 135FF00F 00080040 00000000
	Fetch clause starting at 0x31e:                                                   ; 
	VTX_READ_32 T14.X, T14.X, 60                                                      ; 100E0140 135FF00E 0008003C 00000000
	VTX_READ_32 T15.X, T15.X, 4                                                       ; 100F0140 135FF00F 00080004 00000000
	Fetch clause starting at 0x322:                                                   ; 
	VTX_READ_32 T16.X, T16.X, 0                                                       ; 10100140 135FF010 00080000 00000000
	Fetch clause starting at 0x324:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 12                                                      ; 10180140 135FF018 0008000C 00000000
	VTX_READ_32 T23.X, T23.X, 8                                                       ; 10170140 135FF017 00080008 00000000
	VTX_READ_32 T19.X, T19.X, 4                                                       ; 10130140 135FF013 00080004 00000000
	Fetch clause starting at 0x32a:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 4                                                       ; 100F0140 135FF00F 00080004 00000000
	Fetch clause starting at 0x32c:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 0xa4                                                    ; 100F0140 135FF00F 000800A4 00000000
	Fetch clause starting at 0x32e:                                                   ; 
	VTX_READ_32 T16.X, T16.X, 0xa0                                                    ; 10100140 135FF010 000800A0 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	Fetch clause starting at 0x332:                                                   ; 
	VTX_READ_32 T13.X, T13.X, 40                                                      ; 100D0140 135FF00D 00080028 00000000
	Fetch clause starting at 0x334:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 0                                                       ; 10120140 135FF012 00080000 00000000
	VTX_READ_32 T17.X, T17.X, 32                                                      ; 10110140 135FF011 00080020 00000000
	VTX_READ_32 T16.X, T16.X, 4                                                       ; 10100140 135FF010 00080004 00000000
	VTX_READ_32 T15.X, T15.X, 36                                                      ; 100F0140 135FF00F 00080024 00000000
	VTX_READ_32 T14.X, T14.X, 8                                                       ; 100E0140 135FF00E 00080008 00000000
	Fetch clause starting at 0x33e:                                                   ; 
	VTX_READ_32 T13.X, T13.X, 0xe4                                                    ; 100D0140 135FF00D 000800E4 00000000
	Fetch clause starting at 0x340:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T18.X, T18.X, 4                                                       ; 10120140 135FF012 00080004 00000000
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	VTX_READ_32 T16.X, T16.X, 8                                                       ; 10100140 135FF010 00080008 00000000
	VTX_READ_32 T15.X, T15.X, 12                                                      ; 100F0140 135FF00F 0008000C 00000000
	VTX_READ_32 T14.X, T14.X, 16                                                      ; 100E0140 135FF00E 00080010 00000000
	VTX_READ_32 T13.X, T13.X, 20                                                      ; 100D0140 135FF00D 00080014 00000000
	Fetch clause starting at 0x34e:                                                   ; 
	VTX_READ_32 T12.X, T12.X, 0                                                       ; 100C0140 135FF00C 00080000 00000000
	VTX_READ_32 T16.X, T16.X, 20                                                      ; 10100140 135FF010 00080014 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	VTX_READ_32 T14.X, T14.X, 16                                                      ; 100E0140 135FF00E 00080010 00000000
	Fetch clause starting at 0x356:                                                   ; 
	VTX_READ_32 T14.X, T14.X, 8                                                       ; 100E0140 135FF00E 00080008 00000000
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	VTX_READ_32 T16.X, T16.X, 4                                                       ; 10100140 135FF010 00080004 00000000
	Fetch clause starting at 0x35c:                                                   ; 
	VTX_READ_32 T26.X, T26.X, 0                                                       ; 101A0140 135FF01A 00080000 00000000
	VTX_READ_32 T24.X, T24.X, 8                                                       ; 10180140 135FF018 00080008 00000000
	VTX_READ_32 T22.X, T22.X, 8                                                       ; 10160140 135FF016 00080008 00000000
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	Fetch clause starting at 0x366:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 0x5c                                                    ; 10110140 135FF011 0008005C 00000000
	VTX_READ_32 T21.X, T21.X, 0x58                                                    ; 10150140 135FF015 00080058 00000000
	VTX_READ_32 T20.X, T20.X, 0x68                                                    ; 10140140 135FF014 00080068 00000000
	VTX_READ_32 T19.X, T19.X, 0x6c                                                    ; 10130140 135FF013 0008006C 00000000
	VTX_READ_32 T18.X, T18.X, 4                                                       ; 10120140 135FF012 00080004 00000000
	VTX_READ_32 T16.X, T16.X, 8                                                       ; 10100140 135FF010 00080008 00000000
	VTX_READ_32 T25.X, T25.X, 4                                                       ; 10190140 135FF019 00080004 00000000
	VTX_READ_32 T23.X, T23.X, 4                                                       ; 10170140 135FF017 00080004 00000000
	Fetch clause starting at 0x376:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 8                                                       ; 100B0140 135FF00B 00080008 00000000
	VTX_READ_32 T16.X, T16.X, 4                                                       ; 10100140 135FF010 00080004 00000000
	VTX_READ_32 T24.X, T24.X, 0x80                                                    ; 10180140 135FF018 00080080 00000000
	VTX_READ_32 T23.X, T23.X, 0x78                                                    ; 10170140 135FF017 00080078 00000000
	VTX_READ_32 T22.X, T22.X, 0x60                                                    ; 10160140 135FF016 00080060 00000000
	VTX_READ_32 T18.X, T18.X, 0x70                                                    ; 10120140 135FF012 00080070 00000000
	VTX_READ_32 T15.X, T15.X, 0x7c                                                    ; 100F0140 135FF00F 0008007C 00000000
	Fetch clause starting at 0x384:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 4                                                       ; 10120140 135FF012 00080004 00000000
	Fetch clause starting at 0x386:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	Fetch clause starting at 0x38a:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 4                                                       ; 10170140 135FF017 00080004 00000000
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x392:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T26.X, T26.X, 0                                                       ; 101A0140 135FF01A 00080000 00000000
	VTX_READ_32 T18.X, T18.X, 8                                                       ; 10120140 135FF012 00080008 00000000
	VTX_READ_32 T25.X, T25.X, 0                                                       ; 10190140 135FF019 00080000 00000000
	VTX_READ_32 T21.X, T21.X, 8                                                       ; 10150140 135FF015 00080008 00000000
	VTX_READ_32 T15.X, T15.X, 8                                                       ; 100F0140 135FF00F 00080008 00000000
	VTX_READ_32 T24.X, T24.X, 4                                                       ; 10180140 135FF018 00080004 00000000
	Fetch clause starting at 0x3a0:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 0                                                       ; 10180140 135FF018 00080000 00000000
	VTX_READ_32 T23.X, T23.X, 0                                                       ; 10170140 135FF017 00080000 00000000
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	VTX_READ_32 T21.X, T21.X, 0                                                       ; 10150140 135FF015 00080000 00000000
	VTX_READ_32 T20.X, T20.X, 0                                                       ; 10140140 135FF014 00080000 00000000
	VTX_READ_32 T18.X, T18.X, 0                                                       ; 10120140 135FF012 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	Fetch clause starting at 0x3ae:                                                   ; 
	VTX_READ_32 T13.X, T13.X, 8                                                       ; 100D0140 135FF00D 00080008 00000000
	Fetch clause starting at 0x3b0:                                                   ; 
	VTX_READ_32 T12.X, T12.X, 0                                                       ; 100C0140 135FF00C 00080000 00000000
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	Fetch clause starting at 0x3b4:                                                   ; 
	VTX_READ_32 T13.X, T13.X, 4                                                       ; 100D0140 135FF00D 00080004 00000000
	VTX_READ_32 T12.X, T12.X, 0                                                       ; 100C0140 135FF00C 00080000 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	Fetch clause starting at 0x3ba:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T14.X, T14.X, 4                                                       ; 100E0140 135FF00E 00080004 00000000
	Fetch clause starting at 0x3c0:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 0                                                       ; 100B0140 135FF00B 00080000 00000000
	Fetch clause starting at 0x3c2:                                                   ; 
	VTX_READ_32 T12.X, T12.X, 8                                                       ; 100C0140 135FF00C 00080008 00000000
	VTX_READ_32 T11.X, T11.X, 0x9c                                                    ; 100B0140 135FF00B 0008009C 00000000
	Fetch clause starting at 0x3c6:                                                   ; 
	VTX_READ_32 T16.X, T16.X, 0                                                       ; 10100140 135FF010 00080000 00000000
	VTX_READ_32 T15.X, T15.X, 0x94                                                    ; 100F0140 135FF00F 00080094 00000000
	VTX_READ_32 T14.X, T14.X, 4                                                       ; 100E0140 135FF00E 00080004 00000000
	VTX_READ_32 T13.X, T13.X, 0x98                                                    ; 100D0140 135FF00D 00080098 00000000
	Fetch clause starting at 0x3ce:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 0                                                       ; 100B0140 135FF00B 00080000 00000000
	Fetch clause starting at 0x3d0:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 0                                                       ; 100B0140 135FF00B 00080000 00000000
	Fetch clause starting at 0x3d2:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 64                                                      ; 10170140 135FF017 00080040 00000000
	VTX_READ_32 T22.X, T22.X, 56                                                      ; 10160140 135FF016 00080038 00000000
	VTX_READ_32 T21.X, T21.X, 60                                                      ; 10150140 135FF015 0008003C 00000000
	VTX_READ_32 T20.X, T20.X, 24                                                      ; 10140140 135FF014 00080018 00000000
	VTX_READ_32 T19.X, T19.X, 0                                                       ; 10130140 135FF013 00080000 00000000
	VTX_READ_32 T18.X, T18.X, 28                                                      ; 10120140 135FF012 0008001C 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	VTX_READ_32 T16.X, T16.X, 12                                                      ; 10100140 135FF010 0008000C 00000000
	VTX_READ_32 T13.X, T13.X, 32                                                      ; 100D0140 135FF00D 00080020 00000000
	VTX_READ_32 T11.X, T11.X, 8                                                       ; 100B0140 135FF00B 00080008 00000000
	VTX_READ_32 T4.X, T4.X, 16                                                        ; 10040140 135FF004 00080010 00000000
	VTX_READ_32 T3.X, T3.X, 20                                                        ; 10030140 135FF003 00080014 00000000
	Fetch clause starting at 0x3ea:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 60                                                      ; 10180140 135FF018 0008003C 00000000
	VTX_READ_32 T23.X, T23.X, 52                                                      ; 10170140 135FF017 00080034 00000000
	VTX_READ_32 T22.X, T22.X, 36                                                      ; 10160140 135FF016 00080024 00000000
	VTX_READ_32 T21.X, T21.X, 44                                                      ; 10150140 135FF015 0008002C 00000000
	VTX_READ_32 T20.X, T20.X, 56                                                      ; 10140140 135FF014 00080038 00000000
	VTX_READ_32 T19.X, T19.X, 40                                                      ; 10130140 135FF013 00080028 00000000
	VTX_READ_32 T12.X, T12.X, 48                                                      ; 100C0140 135FF00C 00080030 00000000
	Fetch clause starting at 0x3f8:                                                   ; 
	VTX_READ_32 T14.X, T14.X, 64                                                      ; 100E0140 135FF00E 00080040 00000000
	Fetch clause starting at 0x3fa:                                                   ; 
	VTX_READ_32 T14.X, T14.X, 4                                                       ; 100E0140 135FF00E 00080004 00000000
	Fetch clause starting at 0x3fc:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 0                                                       ; 100F0140 135FF00F 00080000 00000000
	Fetch clause starting at 0x3fe:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 12                                                      ; 10110140 135FF011 0008000C 00000000
	VTX_READ_32 T16.X, T16.X, 8                                                       ; 10100140 135FF010 00080008 00000000
	VTX_READ_32 T12.X, T12.X, 4                                                       ; 100C0140 135FF00C 00080004 00000000
	Fetch clause starting at 0x404:                                                   ; 
	VTX_READ_32 T14.X, T14.X, 4                                                       ; 100E0140 135FF00E 00080004 00000000
	Fetch clause starting at 0x406:                                                   ; 
	VTX_READ_32 T21.X, T21.X, 8                                                       ; 10150140 135FF015 00080008 00000000
	VTX_READ_32 T20.X, T20.X, 0x54                                                    ; 10140140 135FF014 00080054 00000000
	VTX_READ_32 T19.X, T19.X, 0x4c                                                    ; 10130140 135FF013 0008004C 00000000
	VTX_READ_32 T18.X, T18.X, 0                                                       ; 10120140 135FF012 00080000 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	VTX_READ_32 T15.X, T15.X, 0x50                                                    ; 100F0140 135FF00F 00080050 00000000
	Fetch clause starting at 0x412:                                                   ; 
	VTX_READ_32 T10.X, T10.X, 0                                                       ; 100A0140 135FF00A 00080000 00000000
	Fetch clause starting at 0x414:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 0                                                       ; 10110140 135FF011 00080000 00000000
	Fetch clause starting at 0x416:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 0x8c                                                    ; 10110140 135FF011 0008008C 00000000
	VTX_READ_32 T10.X, T10.X, 16                                                      ; 100A0140 135FF00A 00080010 00000000
	Fetch clause starting at 0x41a:                                                   ; 
	VTX_READ_32 T16.X, T16.X, 0                                                       ; 10100140 135FF010 00080000 00000000
	VTX_READ_32 T19.X, T19.X, 0x90                                                    ; 10130140 135FF013 00080090 00000000
	VTX_READ_32 T18.X, T18.X, 0x88                                                    ; 10120140 135FF012 00080088 00000000
	Fetch clause starting at 0x420:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 12                                                      ; 10120140 135FF012 0008000C 00000000
	VTX_READ_32 T19.X, T19.X, 8                                                       ; 10130140 135FF013 00080008 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	Fetch clause starting at 0x426:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	Fetch clause starting at 0x428:                                                   ; 
	VTX_READ_32 T20.X, T20.X, 40                                                      ; 10140140 135FF014 00080028 00000000
	VTX_READ_32 T19.X, T19.X, 36                                                      ; 10130140 135FF013 00080024 00000000
	VTX_READ_32 T17.X, T17.X, 32                                                      ; 10110140 135FF011 00080020 00000000
	Fetch clause starting at 0x42e:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 0x60                                                    ; 10130140 135FF013 00080060 00000000
	VTX_READ_32 T18.X, T18.X, 0x5c                                                    ; 10120140 135FF012 0008005C 00000000
	VTX_READ_32 T5.X, T5.X, 0x58                                                      ; 10050140 135FF005 00080058 00000000
	Fetch clause starting at 0x434:                                                   ; 
	VTX_READ_32 T10.X, T10.X, 8                                                       ; 100A0140 135FF00A 00080008 00000000
	VTX_READ_32 T7.X, T7.X, 4                                                         ; 10070140 135FF007 00080004 00000000
	VTX_READ_32 T12.X, T12.X, 0                                                       ; 100C0140 135FF00C 00080000 00000000
	Fetch clause starting at 0x43a:                                                   ; 
	VTX_READ_32 T17.X, T17.X, 0x8c                                                    ; 10110140 135FF011 0008008C 00000000
	VTX_READ_32 T16.X, T16.X, 0x74                                                    ; 10100140 135FF010 00080074 00000000
	VTX_READ_32 T21.X, T21.X, 4                                                       ; 10150140 135FF015 00080004 00000000
	VTX_READ_32 T18.X, T18.X, 0x80                                                    ; 10120140 135FF012 00080080 00000000
	Fetch clause starting at 0x442:                                                   ; 
	VTX_READ_32 T15.X, T15.X, 0x7c                                                    ; 100F0140 135FF00F 0008007C 00000000
	VTX_READ_32 T14.X, T14.X, 0x70                                                    ; 100E0140 135FF00E 00080070 00000000
	VTX_READ_32 T13.X, T13.X, 0x88                                                    ; 100D0140 135FF00D 00080088 00000000
	VTX_READ_32 T20.X, T20.X, 0                                                       ; 10140140 135FF014 00080000 00000000
	VTX_READ_32 T19.X, T19.X, 0x68                                                    ; 10130140 135FF013 00080068 00000000
	Fetch clause starting at 0x44c:                                                   ; 
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	VTX_READ_32 T25.X, T25.X, 0x64                                                    ; 10190140 135FF019 00080064 00000000
	VTX_READ_32 T11.X, T11.X, 0x90                                                    ; 100B0140 135FF00B 00080090 00000000
	VTX_READ_32 T10.X, T10.X, 0x78                                                    ; 100A0140 135FF00A 00080078 00000000
	VTX_READ_32 T12.X, T12.X, 0x84                                                    ; 100C0140 135FF00C 00080084 00000000
	VTX_READ_32 T9.X, T9.X, 8                                                         ; 10090140 135FF009 00080008 00000000
	Fetch clause starting at 0x458:                                                   ; 
	VTX_READ_32 T24.X, T24.X, 20                                                      ; 10180140 135FF018 00080014 00000000
	Fetch clause starting at 0x45a:                                                   ; 
	VTX_READ_32 T27.X, T27.X, 0                                                       ; 101B0140 135FF01B 00080000 00000000
	Fetch clause starting at 0x45c:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 12                                                      ; 101C0140 135FF01C 0008000C 00000000
	VTX_READ_32 T29.X, T29.X, 8                                                       ; 101D0140 135FF01D 00080008 00000000
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x462:                                                   ; 
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x464:                                                   ; 
	VTX_READ_32 T27.X, T27.X, 16                                                      ; 101B0140 135FF01B 00080010 00000000
	Fetch clause starting at 0x466:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 0                                                       ; 101C0140 135FF01C 00080000 00000000
	Fetch clause starting at 0x468:                                                   ; 
	VTX_READ_32 T29.X, T29.X, 12                                                      ; 101D0140 135FF01D 0008000C 00000000
	VTX_READ_32 T30.X, T30.X, 8                                                       ; 101E0140 135FF01E 00080008 00000000
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x46e:                                                   ; 
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x470:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 24                                                      ; 101C0140 135FF01C 00080018 00000000
	Fetch clause starting at 0x472:                                                   ; 
	VTX_READ_32 T29.X, T29.X, 0                                                       ; 101D0140 135FF01D 00080000 00000000
	Fetch clause starting at 0x474:                                                   ; 
	VTX_READ_32 T20.X, T20.X, 12                                                      ; 10140140 135FF014 0008000C 00000000
	VTX_READ_32 T31.X, T31.X, 4                                                       ; 101F0140 135FF01F 00080004 00000000
	VTX_READ_32 T30.X, T30.X, 8                                                       ; 101E0140 135FF01E 00080008 00000000
	Fetch clause starting at 0x47a:                                                   ; 
	VTX_READ_32 T20.X, T20.X, 4                                                       ; 10140140 135FF014 00080004 00000000
	Fetch clause starting at 0x47c:                                                   ; 
	VTX_READ_32 T26.X, T26.X, 28                                                      ; 101A0140 135FF01A 0008001C 00000000
	Fetch clause starting at 0x47e:                                                   ; 
	VTX_READ_32 T29.X, T29.X, 0                                                       ; 101D0140 135FF01D 00080000 00000000
	Fetch clause starting at 0x480:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 12                                                      ; 101C0140 135FF01C 0008000C 00000000
	VTX_READ_32 T31.X, T31.X, 4                                                       ; 101F0140 135FF01F 00080004 00000000
	VTX_READ_32 T30.X, T30.X, 8                                                       ; 101E0140 135FF01E 00080008 00000000
	Fetch clause starting at 0x486:                                                   ; 
	VTX_READ_32 T28.X, T28.X, 4                                                       ; 101C0140 135FF01C 00080004 00000000
	Fetch clause starting at 0x488:                                                   ; 
	VTX_READ_32 T21.X, T21.X, 16                                                      ; 10150140 135FF015 00080010 00000000
	Fetch clause starting at 0x48a:                                                   ; 
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	Fetch clause starting at 0x48c:                                                   ; 
	VTX_READ_32 T23.X, T23.X, 12                                                      ; 10170140 135FF017 0008000C 00000000
	VTX_READ_32 T24.X, T24.X, 8                                                       ; 10180140 135FF018 00080008 00000000
	VTX_READ_32 T19.X, T19.X, 4                                                       ; 10130140 135FF013 00080004 00000000
	Fetch clause starting at 0x492:                                                   ; 
	VTX_READ_32 T19.X, T19.X, 4                                                       ; 10130140 135FF013 00080004 00000000
	Fetch clause starting at 0x494:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 0                                                       ; 100B0140 135FF00B 00080000 00000000
	VTX_READ_32 T9.X, T9.X, 0                                                         ; 10090140 135FF009 00080000 00000000
	Fetch clause starting at 0x498:                                                   ; 
	VTX_READ_32 T18.X, T18.X, 12                                                      ; 10120140 135FF012 0008000C 00000000
	VTX_READ_32 T25.X, T25.X, 0                                                       ; 10190140 135FF019 00080000 00000000
	VTX_READ_32 T6.X, T6.X, 0                                                         ; 10060140 135FF006 00080000 00000000
	VTX_READ_32 T24.X, T24.X, 4                                                       ; 10180140 135FF018 00080004 00000000
	VTX_READ_32 T17.X, T17.X, 4                                                       ; 10110140 135FF011 00080004 00000000
	VTX_READ_32 T23.X, T23.X, 8                                                       ; 10170140 135FF017 00080008 00000000
	VTX_READ_32 T16.X, T16.X, 8                                                       ; 10100140 135FF010 00080008 00000000
	Fetch clause starting at 0x4a6:                                                   ; 
	VTX_READ_32 T7.X, T7.X, 0                                                         ; 10070140 135FF007 00080000 00000000
	Fetch clause starting at 0x4a8:                                                   ; 
	VTX_READ_32 T29.X, T29.X, 48                                                      ; 101D0140 135FF01D 00080030 00000000
	VTX_READ_32 T28.X, T28.X, 4                                                       ; 101C0140 135FF01C 00080004 00000000
	VTX_READ_32 T27.X, T27.X, 16                                                      ; 101B0140 135FF01B 00080010 00000000
	VTX_READ_32 T26.X, T26.X, 20                                                      ; 101A0140 135FF01A 00080014 00000000
	VTX_READ_32 T25.X, T25.X, 52                                                      ; 10190140 135FF019 00080034 00000000
	VTX_READ_32 T12.X, T12.X, 0                                                       ; 100C0140 135FF00C 00080000 00000000
	VTX_READ_32 T8.X, T8.X, 0                                                         ; 10080140 135FF008 00080000 00000000
	Fetch clause starting at 0x4b6:                                                   ; 
	VTX_READ_32 T25.X, T25.X, 32                                                      ; 10190140 135FF019 00080020 00000000
	VTX_READ_32 T12.X, T12.X, 12                                                      ; 100C0140 135FF00C 0008000C 00000000
	VTX_READ_32 T30.X, T30.X, 8                                                       ; 101E0140 135FF01E 00080008 00000000
	VTX_READ_32 T8.X, T8.X, 28                                                        ; 10080140 135FF008 0008001C 00000000
	VTX_READ_32 T24.X, T24.X, 36                                                      ; 10180140 135FF018 00080024 00000000
	VTX_READ_32 T23.X, T23.X, 24                                                      ; 10170140 135FF017 00080018 00000000
	VTX_READ_32 T22.X, T22.X, 0                                                       ; 10160140 135FF016 00080000 00000000
	VTX_READ_32 T18.X, T18.X, 60                                                      ; 10120140 135FF012 0008003C 00000000
	VTX_READ_32 T17.X, T17.X, 56                                                      ; 10110140 135FF011 00080038 00000000
	Fetch clause starting at 0x4c8:                                                   ; 
	VTX_READ_32 T8.X, T8.X, 0x134                                                     ; 10080140 135FF008 00080134 00000000
	VTX_READ_32 T18.X, T18.X, 0x118                                                   ; 10120140 135FF012 00080118 00000000
	VTX_READ_32 T17.X, T17.X, 0x110                                                   ; 10110140 135FF011 00080110 00000000
	VTX_READ_32 T16.X, T16.X, 0x114                                                   ; 10100140 135FF010 00080114 00000000
	VTX_READ_32 T15.X, T15.X, 0x128                                                   ; 100F0140 135FF00F 00080128 00000000
	VTX_READ_32 T14.X, T14.X, 0x120                                                   ; 100E0140 135FF00E 00080120 00000000
	VTX_READ_32 T13.X, T13.X, 0x124                                                   ; 100D0140 135FF00D 00080124 00000000
	VTX_READ_32 T9.X, T9.X, 44                                                        ; 10090140 135FF009 0008002C 00000000
	VTX_READ_32 T6.X, T6.X, 40                                                        ; 10060140 135FF006 00080028 00000000
	Fetch clause starting at 0x4da:                                                   ; 
	VTX_READ_32 T12.X, T12.X, 0x208                                                   ; 100C0140 135FF00C 00080208 00000000
	VTX_READ_32 T6.X, T6.X, 0x20c                                                     ; 10060140 135FF006 0008020C 00000000
	VTX_READ_32 T31.X, T31.X, 0x10c                                                   ; 101F0140 135FF01F 0008010C 00000000
	VTX_READ_32 T30.X, T30.X, 0x11c                                                   ; 101E0140 135FF01E 0008011C 00000000
	VTX_READ_32 T7.X, T7.X, 0x12c                                                     ; 10070140 135FF007 0008012C 00000000
	VTX_READ_32 T27.X, T27.X, 0x13c                                                   ; 101B0140 135FF01B 0008013C 00000000
	VTX_READ_32 T24.X, T24.X, 0x108                                                   ; 10180140 135FF018 00080108 00000000
	VTX_READ_32 T26.X, T26.X, 0x100                                                   ; 101A0140 135FF01A 00080100 00000000
	VTX_READ_32 T28.X, T28.X, 0x138                                                   ; 101C0140 135FF01C 00080138 00000000
	VTX_READ_32 T29.X, T29.X, 0x130                                                   ; 101D0140 135FF01D 00080130 00000000
	VTX_READ_32 T25.X, T25.X, 0x104                                                   ; 10190140 135FF019 00080104 00000000
	Fetch clause starting at 0x4f0:                                                   ; 
	VTX_READ_32 T11.X, T11.X, 32                                                      ; 100B0140 135FF00B 00080020 00000000
	VTX_READ_32 T6.X, T6.X, 36                                                        ; 10060140 135FF006 00080024 00000000
	VTX_READ_32 T5.X, T5.X, 40                                                        ; 10050140 135FF005 00080028 00000000
	Fetch clause starting at 0x4f6:                                                   ; 
	VTX_READ_32 T5.X, T5.X, 64                                                        ; 10050140 135FF005 00080040 00000000
	VTX_READ_32 T6.X, T6.X, 60                                                        ; 10060140 135FF006 0008003C 00000000
	VTX_READ_32 T11.X, T11.X, 56                                                      ; 100B0140 135FF00B 00080038 00000000
	ALU clause starting at 0x4fc:                                                     ; 
	  MULLO_INT             * T0.Y, KC0[1].Z, T1.X,                                   ; 80002881 20004790
	  ADD_INT               * T1.W, T0.X, PS,                                         ; 801FE000 60201A10
	  SETGT_UINT            * T0.W, PV.W, literal.x,                                  ; 801FACFE 60001F10
	65535(9.183409e-41), 0(0.000000e+00)                                              ; 0000FFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x501:                                                     ; 
	  MOV                     T0.W, KC0[2].Y,                                         ; 00000482 60000C90
	  MULLO_INT             * T0.X, T1.W, literal.x,                                  ; 801FAC01 00004790
	336(4.708363e-43), 0(0.000000e+00)                                                ; 00000150 00000000
	  ADD_INT               * T0.X, PV.W, PS,                                         ; 801FECFE 00001A10
	  MOV                     T5.X, PV.X,                                             ; 000000FE 00A00C90
	  MOV                     T0.W, KC0[3].Y,                                         ; 00000483 60000C90
	  MULLO_INT             * T0.Y, T1.W, literal.x,                                  ; 801FAC01 20004790
	20(2.802597e-44), 0(0.000000e+00)                                                 ; 00000014 00000000
	  ADD_INT               * T11.X, PV.W, PS,                                        ; 801FECFE 01601A10
	  MOV                     T12.X, PV.X,                                            ; 000000FE 01800C90
	  MOV                   * T1.X, T0.X,                                             ; 80000000 00200C90
	  MOV                     T4.X, T0.X,                                             ; 00000000 00800C90
	  MOV                   * T7.X, T0.X,                                             ; 80000000 00E00C90
	  MOV                   * T3.X, T0.X,                                             ; 80000000 00600C90
	ALU clause starting at 0x50f:                                                     ; 
	  MOV                   * T0.W, literal.x,                                        ; 800000FD 60000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T8.W, PV.W,                                             ; 00000CFE 61000C90
	  MOV                   * T2.W, KC0[3].W,                                         ; 80000C83 60400C90
	  MOV                     T8.X, KC0[4].X,                                         ; 00000084 01000C90
	  SETE_INT                T0.Y, T5.X, 0.0,                                        ; 001F0005 20001D10
	  SETNE_INT               T0.Z, T12.X, literal.x,  BS:VEC_120/SCL_212             ; 001FA00C 40081E90
	  MOV                     T3.W, KC0[3].X,                                         ; 00000083 60600C90
	  MULLO_INT             * T1.Y, T1.W, literal.y,                                  ; 809FAC01 20204790
	-1(-nan), 48(6.726233e-44)                                                        ; FFFFFFFF 00000030
	  ADD_INT                 T2.X, PV.W, PS,                                         ; 001FECFE 00401A10
	  MOV                     T4.Y, KC0[4].Y,                                         ; 00000484 20800C90
	  MOV                     T4.Z, KC0[4].Z,                                         ; 00000884 40800C90
	  MOV                     T6.W, KC0[4].W,                                         ; 00000C84 60C00C90
	  AND_INT               * T3.W, PV.Y, PV.Z,                                       ; 811FC4FE 60601810
	  ADD_INT                 T6.X, T0.X, literal.x,                                  ; 001FA000 00C01A10
	  MOV                     T3.Y, KC0[5].X,                                         ; 00000085 20600C90
	  MOV                     T1.Z, KC0[5].Y,                                         ; 00000485 40200C90
	  MOV                     T7.W, KC0[5].W,                                         ; 00000C85 60E00C90
	  AND_INT               * T3.W, PS, 1,                                            ; 801F40FF 60601810
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT                 T9.X, T0.X, literal.x,                                  ; 001FA000 01201A10
	  MOV                     T0.Y, literal.y,                                        ; 000004FD 20000C90
	  MOV                     T0.Z, KC0[6].Y,                                         ; 00000486 40000C90
	  MOV                     T5.W, KC0[6].Z,                                         ; 00000886 60A00C90
	  SETE_INT              * T3.W, PS, 0.0,                                          ; 801F00FF 60601D10
	44(6.165713e-44), 1(1.401298e-45)                                                 ; 0000002C 00000001
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0x52b:                                                     ; 
	  MOV                     T10.X, T2.X,                                            ; 00000002 01400C90
	  MOV                   * T13.X, T2.X,                                            ; 80000002 01A00C90
	  MOV                     T14.X, T2.X,                                            ; 00000002 01C00C90
	  MOV                   * T15.X, T2.X,                                            ; 80000002 01E00C90
	  MOV                     T16.X, T11.X,                                           ; 0000000B 02000C90
	  MOV                   * T17.X, T2.X,                                            ; 80000002 02200C90
	  MOV                   * T18.X, T2.X,                                            ; 80000002 02400C90
	ALU clause starting at 0x532:                                                     ; 
	  MOV                     T19.X, -T10.X,                                          ; 0000100A 02600C90
	  ADD_INT               * T3.W, T9.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA009 60681A10
	8(1.121039e-44), 0(0.000000e+00)                                                  ; 00000008 00000000
	  LSHR                    T20.X, PV.W, literal.x,                                 ; 001FACFE 02800B10
	  MOV                   * T21.X, -T13.X,                                          ; 8000100D 02A00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T3.W, T9.X, literal.x,                                  ; 801FA009 60601A10
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  LSHR                    T22.X, PV.W, literal.x,                                 ; 001FACFE 02C00B10
	  MOV                   * T23.X, -T14.X,                                          ; 8000100E 02E00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  LSHR                  * T24.X, T9.X, literal.x,                                 ; 801FA009 03000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE           * T10.X, T16.X, T10.X, T15.X,                             ; 80014010 0143000F
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	64(8.968310e-44), 0(0.000000e+00)                                                 ; 00000040 00000000
	  LSHR                    T15.X, PV.W, literal.x,                                 ; 001FACFE 01E00B10
	  MULADD_IEEE           * T13.X, T16.X, T13.X, T17.X,                             ; 8001A010 01A30011
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	60(8.407791e-44), 0(0.000000e+00)                                                 ; 0000003C 00000000
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  MULADD_IEEE           * T14.X, T16.X, T14.X, T18.X,                             ; 8001C010 01C30012
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	56(7.847271e-44), 0(0.000000e+00)                                                 ; 00000038 00000000
	  LSHR                  * T16.X, PV.W, literal.x,                                 ; 801FACFE 02000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x54e:                                                     ; 
	  MOV                     T13.X, T11.X,                                           ; 0000000B 01A00C90
	  MULLO_INT             * T0.Y, T12.X, literal.x,                                 ; 801FA00C 20004790
	152(2.129974e-43), 0(0.000000e+00)                                                ; 00000098 00000000
	  ADD_INT               * T17.X, T4.Z, PS,                                        ; 801FE804 02201A10
	  MOV                     T14.X, PV.X,                                            ; 000000FE 01C00C90
	  MOV                   * T15.X, PV.X,                                            ; 800000FE 01E00C90
	  LSHL                  * T3.W, T12.X, literal.x,                                 ; 801FA00C 60600B90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T16.X, T4.Y, PV.W,                                      ; 819FC404 02001A10
	ALU clause starting at 0x557:                                                     ; 
	  ADD_INT               * T10.X, T0.X, literal.x,                                 ; 801FA000 01401A10
	104(1.457350e-43), 0(0.000000e+00)                                                ; 00000068 00000000
	  LSHR                  * T18.X, PV.X, literal.x,                                 ; 801FA0FE 02400B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x55b:                                                     ; 
	  ADD_INT               * T4.W, T15.X, T13.X,                                     ; 8001A00F 60801A10
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T18.X, T7.W, PS,                                        ; 801FEC07 02401A10
	  MOV                     T13.X, PV.X,                                            ; 000000FE 01A00C90
	  MOV                   * T15.X, PV.X,                                            ; 800000FE 01E00C90
	  MOV                   * T19.X, T18.X,                                           ; 80000012 02600C90
	ALU clause starting at 0x562:                                                     ; 
	  ADD_INT               * T4.W, T13.X, T14.X,                                     ; 8001C00D 60801A10
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT                 T13.X, T6.W, PS,                                        ; 001FEC06 01A01A10
	  ADD_INT               * T4.W, T15.X, T14.X,                                     ; 8001C00F 60801A10
	  MOV                     T15.X, PV.X,                                            ; 000000FE 01E00C90
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T16.X, T6.W, PS,                                        ; 801FEC06 02001A10
	  MOV                     T20.X, PV.X,                                            ; 000000FE 02800C90
	  ADD_INT                 T4.W, T19.X, T14.X,                                     ; 0001C013 60801A10
	  MOV                   * T14.X, PV.X,                                            ; 800000FE 01C00C90
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T21.X, T6.W, PS,                                        ; 801FEC06 02A01A10
	  MOV                     T22.X, PV.X,                                            ; 000000FE 02C00C90
	  MOV                   * T23.X, PV.X,                                            ; 800000FE 02E00C90
	ALU clause starting at 0x573:                                                     ; 
	  MOV                     T24.X, T13.X,                                           ; 0000000D 03000C90
	  MOV                   * T25.X, T17.X,                                           ; 80000011 03200C90
	  MOV                     T26.X, T17.X,                                           ; 00000011 03400C90
	  MOV                   * T27.X, T17.X,                                           ; 80000011 03600C90
	  ADD                   * T4.W, T15.X, -T14.X,                                    ; 8201C00F 60800010
	  ADD                   * T8.W, T21.X, -T16.X,                                    ; 82020015 61000010
	  MOV                     T15.X, T17.X,                                           ; 00000011 01E00C90
	  MUL_IEEE                T9.W, T4.W, PV.W,                                       ; 019FCC04 61200110
	  ADD                   * T10.W, T23.X, -T14.X,                                   ; 8201C017 61400010
	ALU clause starting at 0x57c:                                                     ; 
	  ADD                   * T11.W, T22.X, -T20.X,                                   ; 82028016 61600010
	  ADD                   * T12.W, T13.X, -T16.X,                                   ; 8202000D 61800010
	  MUL_IEEE                T2.Z, PV.W, T11.W,                                      ; 01816CFE 40400110
	  MULADD_IEEE             T9.W, PV.W, T10.W, -T9.W, BS:VEC_120/SCL_212            ; 01814CFE 612B1C09
	  ADD                   * T12.W, T24.X, -T20.X,                                   ; 82028018 61800010
	  MUL_IEEE                T3.Z, PS, T10.W,  BS:VEC_021/SCL_122                    ; 018140FF 40640110
	  MUL_IEEE                T10.W, PV.W, PV.W,                                      ; 019FCCFE 61400110
	  MULADD_IEEE           * T8.W, PS, T8.W, -PV.Z,                                  ; 818100FF 610318FE
	  MULADD_IEEE             T10.W, PS, PS, PV.W,                                    ; 001FE0FF 61430CFE
	  MULADD_IEEE           * T4.W, T4.W, T11.W, -PV.Z,                               ; 81816C04 608318FE
	  MOV                     T13.X, T17.X,                                           ; 00000011 01A00C90
	  MULADD_IEEE             T10.W, PS, PS, PV.W,                                    ; 001FE0FF 61430CFE
	  MOV                   * T14.X, T17.X,                                           ; 80000011 01C00C90
	  RECIPSQRT_CLAMPED     * T0.Y, PV.W,                                             ; 80000CFE 20004390
	  MOV                     T16.X, T17.X,                                           ; 00000011 02000C90
	  MUL NON-IEEE            T10.W, T10.W, PS,                                       ; 001FEC0A 61400090
	  MOV                   * T22.X, T17.X,                                           ; 80000011 02C00C90
	  RECIP_IEEE            * T0.Y, PV.W,                                             ; 80000CFE 20004310
	  MOV                     T23.X, T17.X,                                           ; 00000011 02E00C90
	  MUL_IEEE                T9.W, T9.W, PS,                                         ; 001FEC09 61200110
	  MOV                   * T20.X, T11.X,                                           ; 8000000B 02800C90
	  MUL_IEEE                T2.Z, PV.W, T25.X,                                      ; 00032CFE 40400110
	  MUL_IEEE                T10.W, PV.W, T26.X,  BS:VEC_021/SCL_122                 ; 00034CFE 61440110
	  MUL_IEEE              * T8.W, T8.W, T0.Y,                                       ; 80800C08 61000110
	  MOV                     T21.X, T11.X,                                           ; 0000000B 02A00C90
	  MULADD_IEEE             T3.Z, T27.X, PS, PV.W, BS:VEC_120/SCL_212               ; 001FE01B 406B0CFE
	  MULADD_IEEE             T10.W, T15.X, PS, PV.Z, BS:VEC_201                      ; 001FE00F 615308FE
	  MUL_IEEE              * T4.W, T4.W, T0.Y,                                       ; 80800C04 60800110
	ALU clause starting at 0x598:                                                     ; 
	  MULADD_IEEE             T10.W, T13.X, T4.W, T10.W, BS:VEC_201                   ; 0180800D 61530C0A
	  MUL_IEEE              * T9.W, T9.W, T14.X,                                      ; 8001CC09 61200110
	  MULADD_IEEE             T2.Z, T16.X, T8.W, PS, BS:VEC_021/SCL_122               ; 01810010 404700FF
	  MUL_IEEE                T8.W, PV.W, PV.W,                                       ; 019FCCFE 61000110
	  MULADD_IEEE           * T9.W, T22.X, T4.W, T3.Z,                                ; 81808016 61230803
	  MULADD_IEEE             T8.W, PS, PS, PV.W,                                     ; 001FE0FF 61030CFE
	  MULADD_IEEE           * T4.W, T23.X, T4.W, PV.Z,                                ; 81808017 608308FE
	  MULADD_IEEE             T8.W, PS, PS, PV.W,                                     ; 001FE0FF 61030CFE
	  ADD_INT               * T11.W, T0.X, literal.x,                                 ; 801FA000 61601A10
	84(1.177091e-43), 0(0.000000e+00)                                                 ; 00000054 00000000
	  RECIPSQRT_CLAMPED     * T0.Y, PV.W,                                             ; 80000CFE 20004390
	  LSHR                    T13.X, T11.W, literal.x,                                ; 001FAC0B 01A00B10
	  MUL NON-IEEE            T8.W, T8.W, PS,  BS:VEC_120/SCL_212                     ; 001FEC08 61080090
	  ADD_INT               * T11.W, T0.X, literal.y,                                 ; 809FA000 61601A10
	2(2.802597e-45), 80(1.121039e-43)                                                 ; 00000002 00000050
	  LSHR                    T22.X, PS, literal.x,                                   ; 001FA0FF 02C00B10
	  RECIP_IEEE            * T0.Y, PV.W,                                             ; 80000CFE 20004310
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T14.X, T10.W, PS,                                       ; 001FEC0A 01C00110
	  MUL_IEEE              * T16.X, T9.W, PS,                                        ; 801FEC09 02000110
	  MUL_IEEE                T15.X, T4.W, T0.Y,                                      ; 00800C04 01E00110
	  MOV                     T16.Y, PV.X,                                            ; 000000FE 22000C90
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	76(1.064987e-43), 0(0.000000e+00)                                                 ; 0000004C 00000000
	  LSHR                    T23.X, PV.W, literal.x,                                 ; 001FACFE 02E00B10
	  MOV                   * T16.Z, PV.X,                                            ; 800000FE 42000C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x5b3:                                                     ; 
	  MOV                   * T23.X, T17.X,                                           ; 80000011 02E00C90
	ALU clause starting at 0x5b4:                                                     ; 
	  ADD_INT                 T22.X, T18.X, literal.x,                                ; 001FA012 02C01A10
	  SETE_INT                T4.W, T23.X, literal.y,  BS:VEC_120/SCL_212             ; 009FA017 60881D10
	  MOV                   * T13.X, T16.X,                                           ; 80000010 01A00C90
	4(5.605194e-45), -1(-nan)                                                         ; 00000004 FFFFFFFF
	  MOV                     T13.Y, T16.Y,                                           ; 00000410 21A00C90
	  MOV                     T13.Z, T16.Z,                                           ; 00000810 41A00C90
	  MOV                   * T13.W, T16.W,                                           ; 80000C10 61A00C90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), T4.W, 0.0,              ; 801F0C04 00002104
	ALU clause starting at 0x5bc:                                                     ; 
	  MOV                     T13.X, T22.X,                                           ; 00000016 01A00C90
	  MOV                   * T24.X, T18.X,                                           ; 80000012 03000C90
	ALU clause starting at 0x5be:                                                     ; 
	  ADD_INT               * T4.W, T13.X, T23.X,                                     ; 8002E00D 60801A10
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T13.X, T3.Y, PS,                                        ; 801FE403 01A01A10
	  MOV                     T25.X, PV.X,                                            ; 000000FE 03200C90
	  ADD_INT                 T4.W, T24.X, T23.X,                                     ; 0002E018 60801A10
	  MOV                   * T24.X, PV.X,                                            ; 800000FE 03000C90
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T26.X, T3.Y, PS,                                        ; 801FE403 03401A10
	  MOV                     T27.X, PV.X,                                            ; 000000FE 03600C90
	  MOV                   * T28.X, PV.X,                                            ; 800000FE 03800C90
	ALU clause starting at 0x5ca:                                                     ; 
	  ADD_INT               * T4.W, T23.X, T19.X,                                     ; 80026017 60801A10
	  MULLO_INT             * T0.Y, PV.W, literal.x,                                  ; 801FACFE 20004790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T23.X, T3.Y, PS,                                        ; 801FE403 02E01A10
	  MOV                     T29.X, PV.X,                                            ; 000000FE 03A00C90
	  MOV                   * T30.X, PV.X,                                            ; 800000FE 03C00C90
	  ADD                   * T4.W, -T20.X, 1.0,                                      ; 801F3014 60800010
	  ADD_INT                 T31.X, T17.X, literal.x,                                ; 001FA011 03E01A10
	  MUL_IEEE              * T2.Z, T20.X, T25.X,  BS:VEC_120/SCL_212                 ; 80032014 40480110
	108(1.513402e-43), 0(0.000000e+00)                                                ; 0000006C 00000000
	  MUL_IEEE                T8.W, T20.X, T24.X,  BS:VEC_021/SCL_122                 ; 00030014 61040110
	  ADD                   * T4.W, T4.W, -T21.X,                                     ; 8202AC04 60800010
	  ADD_INT                 T24.X, T17.X, literal.x,                                ; 001FA011 03001A10
	  MULADD_IEEE             T8.W, PS, T27.X, PV.W, BS:VEC_021/SCL_122               ; 000360FF 61070CFE
	  MULADD_IEEE           * T9.W, PS, T28.X, T2.Z,                                  ; 800380FF 61230802
	92(1.289195e-43), 0(0.000000e+00)                                                 ; 0000005C 00000000
	ALU clause starting at 0x5da:                                                     ; 
	  MULADD_IEEE           * T9.W, T21.X, T29.X, T9.W,                               ; 8003A015 61230C09
	  MUL_IEEE              * T10.W, T20.X, T13.X,                                    ; 8001A014 61400110
	  MULADD_IEEE             T2.Z, T4.W, T26.X, PV.W, BS:VEC_102/SCL_221             ; 00034C04 404F0CFE
	  MUL_IEEE                T4.W, T9.W, T9.W,  BS:VEC_201                           ; 01812C09 60900110
	  MULADD_IEEE           * T8.W, T21.X, T30.X, T8.W,                               ; 8003C015 61030C08
	  MULADD_IEEE             T4.W, PS, PS, PV.W,                                     ; 001FE0FF 60830CFE
	  MULADD_IEEE           * T10.W, T21.X, T23.X, PV.Z,                              ; 8002E015 614308FE
	  ADD_INT                 T13.X, T17.X, literal.x,                                ; 001FA011 01A01A10
	  MULADD_IEEE             T4.W, PS, PS, PV.W,                                     ; 001FE0FF 60830CFE
	  ADD_INT               * T23.X, T17.X, literal.y,                                ; 809FA011 02E01A10
	104(1.457350e-43), 88(1.233143e-43)                                               ; 00000068 00000058
	  RECIPSQRT_CLAMPED     * T0.Y, PV.W,                                             ; 80000CFE 20004390
	  ADD_INT                 T25.X, T17.X, literal.x,                                ; 001FA011 03201A10
	  MUL NON-IEEE            T4.W, T4.W, PS,                                         ; 001FEC04 60800090
	  ADD_INT               * T26.X, T17.X, literal.y,                                ; 809FA011 03401A10
	124(1.737610e-43), 112(1.569454e-43)                                              ; 0000007C 00000070
	  RECIP_IEEE            * T0.Y, PV.W,                                             ; 80000CFE 20004310
	  ADD_INT                 T27.X, T17.X, literal.x,                                ; 001FA011 03601A10
	  MUL_IEEE                T4.W, T9.W, PS,                                         ; 001FEC09 60800110
	  ADD_INT               * T28.X, T17.X, literal.y,                                ; 809FA011 03801A10
	96(1.345247e-43), 120(1.681558e-43)                                               ; 00000060 00000078
	  MUL_IEEE                T9.W, PV.W, T31.X,                                      ; 0003ECFE 61200110
	  MUL_IEEE              * T8.W, T8.W, T0.Y,                                       ; 80800C08 61000110
	  ADD_INT                 T29.X, T17.X, literal.x,                                ; 001FA011 03A01A10
	  MULADD_IEEE             T9.W, T24.X, PS, PV.W, BS:VEC_120/SCL_212               ; 001FE018 612B0CFE
	  MUL_IEEE              * T10.W, T10.W, T0.Y,                                     ; 80800C0A 61400110
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	ALU clause starting at 0x5f5:                                                     ; 
	  MUL_IEEE              * T11.W, T4.W, T13.X,                                     ; 8001AC04 61600110
	  MULADD_IEEE             T2.Z, T23.X, T8.W, PV.W,                                ; 01810017 40430CFE
	  MULADD_IEEE           * T9.W, T25.X, T10.W, T9.W, BS:VEC_120/SCL_212            ; 81814019 612B0C09
	  MUL_IEEE              * T4.W, T4.W, T26.X,                                      ; 80034C04 60800110
	  MULADD_IEEE             T3.Z, T27.X, T8.W, PV.W, BS:VEC_021/SCL_122             ; 0181001B 40670CFE
	  MUL_IEEE                T4.W, T9.W, T9.W,                                       ; 01812C09 60800110
	  MULADD_IEEE           * T8.W, T28.X, T10.W, T2.Z,                               ; 8181401C 61030802
	  MULADD_IEEE             T4.W, PS, PS, PV.W,                                     ; 001FE0FF 60830CFE
	  MULADD_IEEE           * T10.W, T29.X, T10.W, PV.Z,                              ; 8181401D 614308FE
	  MULADD_IEEE           * T4.W, PS, PS, PV.W,                                     ; 801FE0FF 60830CFE
	  RECIPSQRT_CLAMPED     * T0.Y, PV.W,                                             ; 80000CFE 20004390
	  MUL NON-IEEE          * T4.W, T4.W, PS,                                         ; 801FEC04 60800090
	  RECIP_IEEE            * T0.Y, PV.W,                                             ; 80000CFE 20004310
	  MUL_IEEE              * T13.Z, T10.W, PS,                                       ; 801FEC0A 41A00110
	  MUL_IEEE              * T13.Y, T9.W, T0.Y,                                      ; 80800C09 21A00110
	  MUL_IEEE              * T13.X, T8.W, T0.Y,                                      ; 80800C08 01A00110
	ALU clause starting at 0x605:                                                     ; 
	  MOV                     T23.X, 0.0,                                             ; 000000F8 02E00C90
	  MOV                     T23.Y, 0.0,                                             ; 000000F8 22E00C90
	  SETE_INT              * T4.W, T17.X, literal.x,                                 ; 801FA011 60801D10
	-1(-nan), 0(0.000000e+00)                                                         ; FFFFFFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x60a:                                                     ; 
	  ADD_INT                 T4.W, T17.X, T19.X,  BS:VEC_102/SCL_221                 ; 00026011 608C1A10
	  ADD_INT               * T8.W, T22.X, T17.X,                                     ; 80022016 61001A10
	  LSHL                  * T4.W, PV.W, literal.x,                                  ; 801FACFE 60800B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT                 T19.X, T1.Z, PV.W,                                      ; 019FC801 02601A10
	  LSHL                  * T4.W, T8.W, literal.x,                                  ; 801FAC08 60800B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT                 T22.X, T1.Z, PV.W,                                      ; 019FC801 02C01A10
	  ADD_INT               * T4.W, T18.X, T17.X,                                     ; 80022012 60801A10
	  MOV                     T17.X, PV.X,                                            ; 000000FE 02200C90
	  LSHL                  * T4.W, PV.W, literal.x,                                  ; 801FACFE 60800B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT               * T18.X, T1.Z, PV.W,                                      ; 819FC801 02401A10
	  MOV                     T24.X, PV.X,                                            ; 000000FE 03000C90
	  ADD                   * T4.W, -T20.X, 1.0,                                      ; 801F3014 60800010
	ALU clause starting at 0x619:                                                     ; 
	  MUL_IEEE                T8.W, T20.X, T22.X,  BS:VEC_021/SCL_122                 ; 0002C014 61040110
	  ADD                   * T4.W, T4.W, -T21.X,                                     ; 8202AC04 60800010
	  MOV                     T22.X, T19.X,                                           ; 00000013 02C00C90
	  MUL_IEEE              * T9.W, T20.X, T17.X,  BS:VEC_120/SCL_212                 ; 80022014 61280110
	  MULADD_IEEE           * T8.W, T4.W, T18.X, T8.W,                                ; 80024C04 61030C08
	ALU clause starting at 0x61e:                                                     ; 
	  MULADD_IEEE             T23.Y, T21.X, T19.X, T8.W,                              ; 00026015 22E30C08
	  MULADD_IEEE           * T4.W, T4.W, T24.X, T9.W, BS:VEC_021/SCL_122             ; 80030C04 60870C09
	  MULADD_IEEE           * T23.X, T21.X, T22.X, PV.W,                              ; 8002C015 02E30CFE
	ALU clause starting at 0x621:                                                     ; 
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	72(1.008935e-43), 0(0.000000e+00)                                                 ; 00000048 00000000
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  MOV                   * T18.X, T23.Y,                                           ; 80000417 02400C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	68(9.528830e-44), 0(0.000000e+00)                                                 ; 00000044 00000000
	  LSHR                  * T19.X, PV.W, literal.x,                                 ; 801FACFE 02600B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x62a:                                                     ; 
	  ADD_INT               * T23.X, T5.W, T3.W,                                      ; 81806C05 02E01A10
	ALU clause starting at 0x62b:                                                     ; 
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	108(1.513402e-43), 0(0.000000e+00)                                                ; 0000006C 00000000
	  LSHR                  * T17.X, PV.W, literal.x,                                 ; 801FACFE 02200B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x62f:                                                     ; 
	  MOV                   * T17.X, T13.Y,                                           ; 8000040D 02200C90
	  SETNE_DX10              T3.W, |PV.X|, |PV.X|,                                   ; 001FC0FE 60600793
	  SETNE_DX10            * T4.W, |T13.X|, |T13.X|,                                 ; 8001A00D 60800793
	  MOV                     T18.X, T13.Z,                                           ; 0000080D 02400C90
	  OR_INT                  T4.W, PS, PV.W,                                         ; 019FC0FF 60801890
	  SETGE_DX10            * T8.W, |T17.X|, |T13.X|,                                 ; 8001A011 61000713
	  MOV                     T2.Z, literal.x,                                        ; 000000FD 40400C90
	  MUL_IEEE                T3.W, PV.X, PV.X,                                       ; 001FC0FE 60600110
	  OR_INT                * T4.W, PS, PV.W,                                         ; 819FC0FF 60801890
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MULADD_IEEE           * T4.W, T17.X, T17.X, T3.W, Pred_sel_one                  ; E0022011 60830C03
	  RECIPSQRT_CLAMPED     * T0.Y, T4.W, Pred_sel_one                                ; E0000C04 20004390
	  MUL NON-IEEE          * T4.W, T4.W, T0.Y, Pred_sel_one                          ; E0800C04 60800090
	  RECIP_IEEE            * T0.Y, T4.W, Pred_sel_one                                ; E0000C04 20004310
	  MUL_IEEE                T19.Y, T18.X, T0.Y, Pred_sel_one                        ; 60800012 22600110
	  MUL_IEEE              * T4.W, T17.X, T0.Y, Pred_sel_one BS:VEC_120/SCL_212      ; E0800011 60880110
	  MOV                   * T19.Z, -T4.W, Pred_sel_one                              ; E0001C04 42600C90
	  MOV                     T19.X, 0.0, Pred_sel_one                                ; 600000F8 02600C90
	  MOV                   * T2.Z, literal.x, Pred_sel_one                           ; E00000FD 40400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x644:                                                     ; 
	  SETNE_INT             * T4.W, T2.Z, 1,                                          ; 801F4802 60801E90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MULADD_IEEE           * T3.W, T13.X, T13.X, T3.W, Pred_sel_zero                 ; C001A00D 60630C03
	  RECIPSQRT_CLAMPED     * T0.Y, T3.W, Pred_sel_zero                               ; C0000C03 20004390
	  MUL NON-IEEE          * T3.W, T3.W, T0.Y, Pred_sel_zero                         ; C0800C03 60600090
	  RECIP_IEEE            * T0.Y, T3.W, Pred_sel_zero                               ; C0000C03 20004310
	  MUL_IEEE              * T3.W, T18.X, T0.Y, Pred_sel_zero                        ; C0800012 60600110
	  MOV                   * T19.X, -T3.W, Pred_sel_zero                             ; C0001C03 02600C90
	  MUL_IEEE              * T19.Z, T13.X, T0.Y, Pred_sel_zero                       ; C080000D 42600110
	  MOV                   * T19.Y, 0.0, Pred_sel_zero                               ; C00000F8 22600C90
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	96(1.345247e-43), 0(0.000000e+00)                                                 ; 00000060 00000000
	  LSHR                    T20.X, PV.W, literal.x,                                 ; 001FACFE 02800B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 92(1.289195e-43)                                                 ; 00000002 0000005C
	  LSHR                    T21.X, PV.W, literal.x,                                 ; 001FACFE 02A00B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 88(1.233143e-43)                                                 ; 00000002 00000058
	  LSHR                    T22.X, PV.W, literal.x,                                 ; 001FACFE 02C00B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 144(2.017870e-43)                                                ; 00000002 00000090
	  LSHR                    T24.X, PV.W, literal.x,                                 ; 001FACFE 03000B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 140(1.961818e-43)                                                ; 00000002 0000008C
	  LSHR                    T25.X, PV.W, literal.x,                                 ; 001FACFE 03200B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 136(1.905766e-43)                                                ; 00000002 00000088
	  LSHR                    T26.X, PV.W, literal.x,                                 ; 001FACFE 03400B10
	  MOV                   * T27.X, T19.Y,                                           ; 80000413 03600C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE              * T3.W, T17.X, T19.X,                                     ; 80026011 60600110
	  MULADD_IEEE             T28.X, T13.X, T27.X, -PV.W,                             ; 0003600D 03831CFE
	  MOV                   * T29.X, T19.Z,                                           ; 80000813 03A00C90
	  ADD_INT               * T3.W, T0.X, literal.x,                                  ; 801FA000 60601A10
	132(1.849714e-43), 0(0.000000e+00)                                                ; 00000084 00000000
	  LSHR                    T30.X, PV.W, literal.x,                                 ; 001FACFE 03C00B10
	  MUL_IEEE              * T3.W, T13.X, T29.X,                                     ; 8003A00D 60600110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T31.X, T18.X, T19.X, -PV.W,                             ; 00026012 03E31CFE
	  ADD_INT               * T3.W, T0.X, literal.x,  BS:VEC_201                      ; 801FA000 60701A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  LSHR                    T32.X, PV.W, literal.x,                                 ; 001FACFE 04000B10
	  MUL_IEEE              * T3.W, T18.X, T27.X,                                     ; 80036012 60600110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T33.X, T17.X, T29.X, -PV.W,                             ; 0003A011 04231CFE
	  ADD_INT               * T3.W, T0.X, literal.x,  BS:VEC_201                      ; 801FA000 60701A10
	124(1.737610e-43), 0(0.000000e+00)                                                ; 0000007C 00000000
	  LSHR                    T34.X, PV.W, literal.x,                                 ; 001FACFE 04400B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 120(1.681558e-43)                                                ; 00000002 00000078
	  LSHR                    T35.X, PV.W, literal.x,                                 ; 001FACFE 04600B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 116(1.625506e-43)                                                ; 00000002 00000074
	  LSHR                    T36.X, PV.W, literal.x,                                 ; 001FACFE 04800B10
	  ADD_INT               * T3.W, T0.X, literal.y,                                  ; 809FA000 60601A10
	2(2.802597e-45), 112(1.569454e-43)                                                ; 00000002 00000070
	  LSHR                  * T37.X, PV.W, literal.x,                                 ; 801FACFE 04A00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x67e:                                                     ; 
	  SETE_INT              * T3.W, T23.X, literal.x,                                 ; 801FA017 60601D10
	-1(-nan), 0(0.000000e+00)                                                         ; FFFFFFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x681:                                                     ; 
	  MOV                     T19.X, 0.0,                                             ; 000000F8 02600C90
	  MOV                     T19.Y, 0.0,                                             ; 000000F8 22600C90
	  MOV                     T19.Z, 0.0,                                             ; 000000F8 42600C90
	  MOV                   * T22.X, T9.X,                                            ; 80000009 02C00C90
	  MOV                     T20.X, T9.X,                                            ; 00000009 02800C90
	  MOV                   * T21.X, T9.X,                                            ; 80000009 02A00C90
	ALU clause starting at 0x687:                                                     ; 
	  MUL_IEEE              * T3.W, T22.X, T14.X,                                     ; 8001C016 60600110
	  MULADD_IEEE           * T3.W, T16.X, T20.X, PV.W,                               ; 80028010 60630CFE
	  MULADD_IEEE           * T3.W, T15.X, T21.X, PV.W,                               ; 8002A00F 60630CFE
	  SETGE_DX10            * T3.W, 0.0, PV.W,                                        ; 819FC0F8 60600710
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x68c:                                                     ; 
	  MULLO_INT             * T0.Y, T23.X, literal.x,                                 ; 801FA017 20004790
	68(9.528830e-44), 0(0.000000e+00)                                                 ; 00000044 00000000
	  ADD_INT               * T15.X, T0.Z, PS,                                        ; 801FE800 01E01A10
	  MOV                   * T14.X, PV.X,                                            ; 800000FE 01C00C90
	ALU clause starting at 0x690:                                                     ; 
	  MULLO_INT             * T0.Y, T15.X, literal.x,                                 ; 801FA00F 20004790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T15.X, T2.W, PS,                                        ; 801FEC02 01E01A10
	ALU clause starting at 0x693:                                                     ; 
	  MOV                     T19.X, 0.0,                                             ; 000000F8 02600C90
	  MOV                     T19.Y, 0.0,                                             ; 000000F8 22600C90
	  MOV                     T19.Z, 0.0,                                             ; 000000F8 42600C90
	  SETE_INT              * T3.W, T15.X, literal.x,                                 ; 801FA00F 60601D10
	-1(-nan), 0(0.000000e+00)                                                         ; FFFFFFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x699:                                                     ; 
	  MULLO_INT             * T0.Y, T15.X, literal.x,                                 ; 801FA00F 20004790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T15.X, T8.X, PS,                                        ; 801FE008 01E01A10
	  MOV                   * T16.X, PV.X,                                            ; 800000FE 02000C90
	ALU clause starting at 0x69d:                                                     ; 
	  MOV                   * T3.W, literal.x,                                        ; 800000FD 60600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T4.W, PV.W,                                             ; 00000CFE 60800C90
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T9.W, 1, T16.X,                                         ; 800200FA 61201D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x6a4:                                                     ; 
	  MOV                     T4.W, literal.x,                                        ; 000000FD 60800C90
	  SETE_INT              * T8.W, T16.X, 1,                                         ; 801F4010 61001D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0x6a8:                                                     ; 
	  MOV                     T19.X, T15.X,                                           ; 0000000F 02600C90
	  MOV                   * T23.X, T15.X,                                           ; 8000000F 02E00C90
	  MOV                   * T24.X, T15.X,                                           ; 8000000F 03000C90
	ALU clause starting at 0x6ab:                                                     ; 
	  MOV                     T19.Y, T23.X,                                           ; 00000017 22600C90
	  MOV                     T19.Z, T24.X,  BS:VEC_120/SCL_212                       ; 00000018 42680C90
	  MOV                   * T4.W, literal.x,                                        ; 800000FD 60800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x6af:                                                     ; 
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x6b1:                                                     ; 
	  BFE_INT               * T8.W, T8.W, 0.0, 1,                                     ; 801F0C08 6100A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T3.W, literal.x, Pred_sel_zero                          ; 400000FD 60600C90
	  SETNE_INT             * T4.W, T16.X, 0.0, Pred_sel_zero                         ; C01F0010 60801E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T4.W, T4.W, 1,                                          ; 801F4C04 60801810
	  SETE_INT              * T4.W, PV.W, 0.0,                                        ; 801F0CFE 60801D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x6b9:                                                     ; 
	  MOV                   * T3.W, literal.x,                                        ; 800000FD 60600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x6bb:                                                     ; 
	  SETNE_INT             * T3.W, T3.W, 1,                                          ; 801F4C03 60601E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x6bd:                                                     ; 
	  MOV                   * T15.Y, T15.X,                                           ; 8000000F 21E00C90
	  MOV                   * T15.Z, T15.X,                                           ; 8000000F 41E00C90
	  MOV                     T19.X, T15.X,                                           ; 0000000F 02600C90
	  MOV                     T19.Y, T15.Y,                                           ; 0000040F 22600C90
	  MOV                     T19.Z, PV.Z,                                            ; 000008FE 42600C90
	  MOV                   * T19.W, T15.W,                                           ; 80000C0F 62600C90
	ALU clause starting at 0x6c3:                                                     ; 
	  SETE_DX10               T3.W, T19.X, 0.0,                                       ; 001F0013 60600610
	  SETE_DX10             * T4.W, T19.Y, 0.0,                                       ; 801F0413 60800610
	  AND_INT                 T3.W, PV.W, PS,                                         ; 001FECFE 60601810
	  SETE_DX10             * T4.W, T19.Z, 0.0,                                       ; 801F0813 60800610
	  AND_INT               * T3.W, PV.W, PS,                                         ; 801FECFE 60601810
	  SETGT_INT             * T3.W, 0.0, PV.W,                                        ; 819FC0F8 60601D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x6ca:                                                     ; 
	  MOV                   * T15.X, T0.X,                                            ; 80000000 01E00C90
	ALU clause starting at 0x6cb:                                                     ; 
	  MOV                     T3.W, literal.x,                                        ; 000000FD 60600C90
	  SETNE_INT             * T4.W, T15.X, 0.0,                                       ; 801F000F 60801E90
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0x6cf:                                                     ; 
	  MOV                     T15.X, T11.X,                                           ; 0000000B 01E00C90
	  MOV                   * T16.X, T0.X,                                            ; 80000000 02000C90
	ALU clause starting at 0x6d1:                                                     ; 
	  MUL_IEEE              * T3.W, T22.X, T17.X,                                     ; 80022016 60600110
	  MULADD_IEEE           * T3.W, T20.X, T13.X, PV.W,                               ; 8001A014 60630CFE
	  MULADD_IEEE           * T3.W, T21.X, T18.X, PV.W,                               ; 80024015 60630CFE
	  MUL_IEEE              * T4.W, T14.X, T15.X,                                     ; 8001E00E 60800110
	  MUL_IEEE                T4.W, T15.X, PV.W,                                      ; 019FC00F 60800110
	  RECIP_IEEE            * T0.Y, |T3.W|,                                           ; 80000C03 20004311
	  MUL_IEEE              * T3.W, PV.W, PS,                                         ; 801FECFE 60600110
	  MUL_IEEE              * T3.W, PV.W, literal.x,                                  ; 801FACFE 60600110
	1048576000(2.500000e-01), 0(0.000000e+00)                                         ; 3E800000 00000000
	  MUL_IEEE              * T3.W, PV.W, PV.W,                                       ; 819FCCFE 60600110
	  MULADD_IEEE             T3.W, T16.X, T16.X, PV.W,                               ; 00020010 60630CFE
	  MUL_IEEE              * T4.W, T16.X, T16.X,                                     ; 80020010 60800110
	  RECIP_IEEE            * T0.Y, PV.W,                                             ; 80000CFE 20004310
	  MUL_IEEE              * T3.W, T4.W, PS,                                         ; 801FEC04 60600110
	ALU clause starting at 0x6df:                                                     ; 
	  MOV                   * T13.X, T0.X,                                            ; 80000000 01A00C90
	ALU clause starting at 0x6e0:                                                     ; 
	  MOV                     T14.X, T6.X,                                            ; 00000006 01C00C90
	  MOV                   * T15.X, T0.X,                                            ; 80000000 01E00C90
	  MOV                     T16.X, T6.X,                                            ; 00000006 02000C90
	  MOV                   * T17.X, T0.X,                                            ; 80000000 02200C90
	  MOV                     T18.X, T6.X,                                            ; 00000006 02400C90
	  MUL_IEEE              * T4.W, T3.W, T13.X,                                      ; 8001AC03 60800110
	ALU clause starting at 0x6e6:                                                     ; 
	  MULADD_IEEE             T13.X, T19.Z, T4.W, T14.X,                              ; 01808813 01A3000E
	  ADD_INT               * T4.W, T6.X, literal.x,                                  ; 801FA006 60801A10
	8(1.121039e-44), 0(0.000000e+00)                                                  ; 00000008 00000000
	  LSHR                    T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00B10
	  MUL_IEEE              * T4.W, T3.W, T15.X,                                      ; 8001EC03 60800110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T15.X, T19.Y, PV.W, T16.X,                              ; 019FC413 01E30010
	  ADD_INT               * T4.W, T6.X, literal.x,                                  ; 801FA006 60801A10
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  LSHR                    T16.X, PV.W, literal.x,                                 ; 001FACFE 02000B10
	  MUL_IEEE              * T3.W, T3.W, T17.X,                                      ; 80022C03 60600110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T17.X, T19.X, PV.W, T18.X, BS:VEC_021/SCL_122           ; 019FC013 02270012
	  LSHR                  * T18.X, T6.X, literal.x,                                 ; 801FA006 02400B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x6f5:                                                     ; 
	  MOV                     T0.Y, literal.x,                                        ; 000000FD 20000C90
	  MOV                   * T8.W, literal.y,                                        ; 800004FD 61000C90
	0(0.000000e+00), 1(1.401298e-45)                                                  ; 00000000 00000001
	ALU clause starting at 0x6f8:                                                     ; 
	  MOV                   * T9.W, T0.W,                                             ; 80000C00 61200C90
	  BFE_INT               * T3.W, T0.Y, 0.0, 1,                                     ; 801F0400 6060A0FA
	  MOV                   * T3.Z, T0.W,                                             ; 80000C00 40600C90
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), T3.W, 0.0,              ; 801F0C03 00002284
	ALU clause starting at 0x6fc:                                                     ; 
	  CNDE_INT                T0.Y, T5.X, literal.x, T5.X,                            ; 001FA005 20038005
	  MOV                   * T0.W, literal.y,                                        ; 800004FD 60000C90
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  MOV                     T3.W, PV.W,                                             ; 00000CFE 60600C90
	  MOV                   * T9.W, PV.W,                                             ; 80000CFE 61200C90
	  MOV                     T3.Z, T0.W,                                             ; 00000C00 40600C90
	  MOV                     T4.W, literal.x,                                        ; 000000FD 60800C90
	  SETGT_INT             * T10.W, literal.y, T0.Y,                                 ; 808004FD 61401D90
	1(1.401298e-45), 3(4.203895e-45)                                                  ; 00000001 00000003
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0x706:                                                     ; 
	  MOV                   * T4.W, literal.x,                                        ; 800000FD 60800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                   * T3.W, PV.W,                                             ; 80000CFE 60600C90
	  MOV                     T3.Z, T4.W,                                             ; 00000C04 40600C90
	  MOV                     T9.W, literal.x,                                        ; 000000FD 61200C90
	  SETGT_INT             * T10.W, T0.Y, literal.y,                                 ; 809FA400 61401D90
	1(1.401298e-45), 3(4.203895e-45)                                                  ; 00000001 00000003
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002108
	  MOV                     T3.Z, literal.x, Pred_sel_zero                          ; 400000FD 40600C90
	  SETNE_INT               T3.W, T0.Y, literal.y, Pred_sel_zero                    ; 409FA400 60601E90
	  MOV                   * T9.W, literal.z, Pred_sel_zero                          ; C00008FD 61200C90
	1(1.401298e-45), 4(5.605194e-45)                                                  ; 00000001 00000004
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T2.Y, T3.X,                                             ; 00000003 20400C90
	  MOV                   * T1.Y, T7.X,                                             ; 80000007 20200C90
	  MOV                   * T2.Z, T4.X,                                             ; 80000004 40400C90
	ALU clause starting at 0x716:                                                     ; 
	  BFE_INT                 T4.W, T4.W, 0.0, 1,                                     ; 001F0C04 6080A0FA
	  MOV                   * T10.W, T0.W,                                            ; 80000C00 61400C90
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0x719:                                                     ; 
	  MOV                     T4.W, literal.x,                                        ; 000000FD 60800C90
	  SETGT_INT             * T10.W, T0.Y, 1,                                         ; 801F4400 61401D90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0x71d:                                                     ; 
	  MOV                     T4.W, literal.x,                                        ; 000000FD 60800C90
	  SETNE_INT             * T9.W, T12.X, literal.y,                                 ; 809FA00C 61201E90
	1(1.401298e-45), -1(-nan)                                                         ; 00000001 FFFFFFFF
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0x721:                                                     ; 
	  MOV                   * T13.X, T0.X,                                            ; 80000000 01A00C90
	ALU clause starting at 0x722:                                                     ; 
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	288(4.035740e-43), 0(0.000000e+00)                                                ; 00000120 00000000
	  LSHR                  * T14.X, PV.W, literal.x,                                 ; 801FACFE 01C00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x726:                                                     ; 
	  MOV                     T13.X, T2.X,                                            ; 00000002 01A00C90
	  MOV                   * T14.X, T2.X,                                            ; 80000002 01C00C90
	  MOV                     T15.X, T2.X,                                            ; 00000002 01E00C90
	  MOV                   * T16.X, T2.X,                                            ; 80000002 02000C90
	  MOV                     T17.X, T11.X,                                           ; 0000000B 02200C90
	  MOV                   * T18.X, T2.X,                                            ; 80000002 02400C90
	  MOV                   * T19.X, T2.X,                                            ; 80000002 02600C90
	ALU clause starting at 0x72d:                                                     ; 
	  MOV                     T20.X, -T13.X,                                          ; 0000100D 02800C90
	  ADD_INT               * T4.W, T0.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA000 60881A10
	240(3.363116e-43), 0(0.000000e+00)                                                ; 000000F0 00000000
	  LSHR                    T21.X, PV.W, literal.x,                                 ; 001FACFE 02A00B10
	  MOV                   * T22.X, -T14.X,                                          ; 8000100E 02C00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	236(3.307064e-43), 0(0.000000e+00)                                                ; 000000EC 00000000
	  LSHR                    T23.X, PV.W, literal.x,                                 ; 001FACFE 02E00B10
	  MOV                   * T24.X, -T15.X,                                          ; 8000100F 03000C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	232(3.251012e-43), 0(0.000000e+00)                                                ; 000000E8 00000000
	  LSHR                    T25.X, PV.W, literal.x,                                 ; 001FACFE 03200B10
	  MULADD_IEEE           * T13.X, T17.X, T13.X, T16.X,                             ; 8001A011 01A30010
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	252(3.531272e-43), 0(0.000000e+00)                                                ; 000000FC 00000000
	  LSHR                    T16.X, PV.W, literal.x,                                 ; 001FACFE 02000B10
	  MULADD_IEEE           * T14.X, T17.X, T14.X, T18.X,                             ; 8001C011 01C30012
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	248(3.475220e-43), 0(0.000000e+00)                                                ; 000000F8 00000000
	  LSHR                    T18.X, PV.W, literal.x,                                 ; 001FACFE 02400B10
	  MULADD_IEEE           * T15.X, T17.X, T15.X, T19.X,                             ; 8001E011 01E30013
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	244(3.419168e-43), 0(0.000000e+00)                                                ; 000000F4 00000000
	  LSHR                  * T17.X, PV.W, literal.x,                                 ; 801FACFE 02200B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x74b:                                                     ; 
	  MOV                     T14.X, T11.X,                                           ; 0000000B 01C00C90
	  MULLO_INT             * T4.W, T12.X, literal.x,                                 ; 801FA00C 60804790
	152(2.129974e-43), 0(0.000000e+00)                                                ; 00000098 00000000
	  ADD_INT               * T13.X, T4.Z, PS,                                        ; 801FE804 01A01A10
	  MOV                     T15.X, PV.X,                                            ; 000000FE 01E00C90
	  MOV                   * T16.X, PV.X,                                            ; 800000FE 02000C90
	  LSHL                  * T4.W, T12.X, literal.x,                                 ; 801FA00C 60800B90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T12.X, T4.Y, PV.W,                                      ; 819FC404 01801A10
	ALU clause starting at 0x754:                                                     ; 
	  ADD_INT               * T9.W, T0.X, literal.x,                                  ; 801FA000 61201A10
	292(4.091792e-43), 0(0.000000e+00)                                                ; 00000124 00000000
	  LSHR                  * T17.X, PV.W, literal.x,                                 ; 801FACFE 02200B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x758:                                                     ; 
	  ADD_INT               * T9.W, T16.X, T14.X,                                     ; 8001C010 61201A10
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T12.X, T7.W, PS,                                        ; 801FEC07 01801A10
	  MOV                     T16.X, PV.X,                                            ; 000000FE 02000C90
	  MOV                   * T17.X, PV.X,                                            ; 800000FE 02200C90
	  MOV                   * T14.X, T12.X,                                           ; 8000000C 01C00C90
	ALU clause starting at 0x75f:                                                     ; 
	  ADD_INT               * T7.W, T16.X, T15.X,                                     ; 8001E010 60E01A10
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T16.X, T6.W, PS,                                        ; 801FEC06 02001A10
	  MOV                     T18.X, PV.X,                                            ; 000000FE 02400C90
	  MOV                   * T19.X, T13.X,                                           ; 8000000D 02600C90
	  MOV                     T20.X, T13.X,                                           ; 0000000D 02800C90
	  MOV                   * T21.X, T13.X,                                           ; 8000000D 02A00C90
	  ADD_INT               * T7.W, T17.X, T15.X,                                     ; 8001E011 60E01A10
	  MOV                     T17.X, T16.X,                                           ; 00000010 02200C90
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T22.X, T6.W, PS,                                        ; 801FEC06 02C01A10
	  MOV                     T23.X, PV.X,                                            ; 000000FE 02E00C90
	  ADD_INT                 T7.W, T14.X, T15.X,                                     ; 0001E00E 60E01A10
	  MOV                   * T15.X, PV.X,                                            ; 800000FE 01E00C90
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T24.X, T6.W, PS,                                        ; 801FEC06 03001A10
	  MOV                     T25.X, PV.X,                                            ; 000000FE 03200C90
	  MOV                   * T26.X, PV.X,                                            ; 800000FE 03400C90
	ALU clause starting at 0x774:                                                     ; 
	  ADD                   * T6.W, T17.X, -T15.X,                                    ; 8201E011 60C00010
	  ADD                   * T7.W, T24.X, -T22.X,                                    ; 8202C018 60E00010
	  MOV                     T17.X, T13.X,                                           ; 0000000D 02200C90
	  MUL_IEEE                T9.W, T6.W, PV.W,                                       ; 019FCC06 61200110
	  ADD                   * T10.W, T26.X, -T15.X,                                   ; 8201E01A 61400010
	ALU clause starting at 0x779:                                                     ; 
	  ADD                   * T11.W, T25.X, -T23.X,                                   ; 8202E019 61600010
	  ADD                   * T12.W, T16.X, -T22.X,                                   ; 8202C010 61800010
	  MUL_IEEE                T4.Z, PV.W, T11.W,                                      ; 01816CFE 40800110
	  MULADD_IEEE             T9.W, PV.W, T10.W, -T9.W, BS:VEC_120/SCL_212            ; 01814CFE 612B1C09
	  ADD                   * T12.W, T18.X, -T23.X,                                   ; 8202E012 61800010
	  MUL_IEEE                T5.Z, PS, T10.W,  BS:VEC_021/SCL_122                    ; 018140FF 40A40110
	  MUL_IEEE                T10.W, PV.W, PV.W,                                      ; 019FCCFE 61400110
	  MULADD_IEEE           * T7.W, PS, T7.W, -PV.Z,                                  ; 8180E0FF 60E318FE
	  MULADD_IEEE             T10.W, PS, PS, PV.W,                                    ; 001FE0FF 61430CFE
	  MULADD_IEEE           * T6.W, T6.W, T11.W, -PV.Z,                               ; 81816C06 60C318FE
	  MULADD_IEEE           * T10.W, PS, PS, PV.W,                                    ; 801FE0FF 61430CFE
	  MOV                     T15.X, T13.X,                                           ; 0000000D 01E00C90
	  RECIPSQRT_CLAMPED     * T4.Y, PV.W,                                             ; 80000CFE 20804390
	  MOV                     T18.X, T13.X,                                           ; 0000000D 02400C90
	  MUL NON-IEEE            T10.W, T10.W, PS,                                       ; 001FEC0A 61400090
	  MOV                   * T22.X, T13.X,                                           ; 8000000D 02C00C90
	  RECIP_IEEE            * T4.Y, PV.W,                                             ; 80000CFE 20804310
	  MOV                     T23.X, T13.X,                                           ; 0000000D 02E00C90
	  MUL_IEEE                T9.W, T9.W, PS,                                         ; 001FEC09 61200110
	  MOV                   * T24.X, T13.X,                                           ; 8000000D 03000C90
	  MUL_IEEE                T4.Z, PV.W, T19.X,                                      ; 00026CFE 40800110
	  MUL_IEEE                T10.W, PV.W, T20.X,  BS:VEC_021/SCL_122                 ; 00028CFE 61440110
	  MUL_IEEE              * T7.W, T7.W, T4.Y,                                       ; 80808C07 60E00110
	  MOV                     T16.X, T11.X,                                           ; 0000000B 02000C90
	  MULADD_IEEE             T5.Z, T21.X, PS, PV.W, BS:VEC_120/SCL_212               ; 001FE015 40AB0CFE
	  MULADD_IEEE             T10.W, T17.X, PS, PV.Z, BS:VEC_201                      ; 001FE011 615308FE
	  MUL_IEEE              * T6.W, T6.W, T4.Y,                                       ; 80808C06 60C00110
	ALU clause starting at 0x794:                                                     ; 
	  MULADD_IEEE             T10.W, T15.X, T6.W, T10.W, BS:VEC_201                   ; 0180C00F 61530C0A
	  MUL_IEEE              * T9.W, T9.W, T18.X,                                      ; 80024C09 61200110
	  MULADD_IEEE             T4.Z, T22.X, T7.W, PS, BS:VEC_021/SCL_122               ; 0180E016 408700FF
	  MUL_IEEE                T7.W, PV.W, PV.W,                                       ; 019FCCFE 60E00110
	  MULADD_IEEE           * T9.W, T23.X, T6.W, T5.Z,                                ; 8180C017 61230805
	  MULADD_IEEE             T7.W, PS, PS, PV.W,                                     ; 001FE0FF 60E30CFE
	  MULADD_IEEE           * T6.W, T24.X, T6.W, PV.Z,                                ; 8180C018 60C308FE
	  MULADD_IEEE             T7.W, PS, PS, PV.W,                                     ; 001FE0FF 60E30CFE
	  ADD_INT               * T11.W, T0.X, literal.x,                                 ; 801FA000 61601A10
	272(3.811532e-43), 0(0.000000e+00)                                                ; 00000110 00000000
	  RECIPSQRT_CLAMPED     * T4.Y, PV.W,                                             ; 80000CFE 20804390
	  LSHR                    T17.X, T11.W, literal.x,                                ; 001FAC0B 02200B10
	  MUL NON-IEEE            T7.W, T7.W, PS,  BS:VEC_120/SCL_212                     ; 001FEC07 60E80090
	  ADD_INT               * T11.W, T0.X, literal.y,                                 ; 809FA000 61601A10
	2(2.802597e-45), 268(3.755480e-43)                                                ; 00000002 0000010C
	  LSHR                    T18.X, PS, literal.x,                                   ; 001FA0FF 02400B10
	  RECIP_IEEE            * T4.Y, PV.W,                                             ; 80000CFE 20804310
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T19.X, T10.W, PS,                                       ; 001FEC0A 02600110
	  MUL_IEEE              * T15.X, T9.W, PS,                                        ; 801FEC09 01E00110
	  MUL_IEEE                T20.X, T6.W, T4.Y,                                      ; 00808C06 02800110
	  MOV                     T15.Y, PV.X,                                            ; 000000FE 21E00C90
	  ADD_INT               * T6.W, T0.X, literal.x,                                  ; 801FA000 60C01A10
	264(3.699428e-43), 0(0.000000e+00)                                                ; 00000108 00000000
	  LSHR                    T21.X, PV.W, literal.x,                                 ; 001FACFE 02A00B10
	  MOV                   * T15.Z, PV.X,                                            ; 800000FE 41E00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x7af:                                                     ; 
	  MOV                   * T18.X, T13.X,                                           ; 8000000D 02400C90
	ALU clause starting at 0x7b0:                                                     ; 
	  ADD_INT                 T17.X, T12.X, literal.x,                                ; 001FA00C 02201A10
	  SETE_INT              * T6.W, T18.X, literal.y,  BS:VEC_120/SCL_212             ; 809FA012 60C81D10
	4(5.605194e-45), -1(-nan)                                                         ; 00000004 FFFFFFFF
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x7b4:                                                     ; 
	  MOV                     T15.X, T17.X,                                           ; 00000011 01E00C90
	  MOV                   * T19.X, T12.X,                                           ; 8000000C 02600C90
	ALU clause starting at 0x7b6:                                                     ; 
	  ADD_INT               * T6.W, T15.X, T18.X,                                     ; 8002400F 60C01A10
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T15.X, T3.Y, PS,                                        ; 801FE403 01E01A10
	  MOV                     T20.X, PV.X,                                            ; 000000FE 02800C90
	  ADD_INT                 T6.W, T19.X, T18.X,                                     ; 00024013 60C01A10
	  MOV                   * T19.X, PV.X,                                            ; 800000FE 02600C90
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T21.X, T3.Y, PS,                                        ; 801FE403 02A01A10
	  MOV                     T22.X, PV.X,                                            ; 000000FE 02C00C90
	  MOV                   * T23.X, PV.X,                                            ; 800000FE 02E00C90
	ALU clause starting at 0x7c2:                                                     ; 
	  ADD_INT               * T6.W, T18.X, T14.X,                                     ; 8001C012 60C01A10
	  MULLO_INT             * T4.Y, PV.W, literal.x,                                  ; 801FACFE 20804790
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  ADD_INT               * T18.X, T3.Y, PS,                                        ; 801FE403 02401A10
	  MOV                     T24.X, PV.X,                                            ; 000000FE 03000C90
	  MOV                   * T25.X, PV.X,                                            ; 800000FE 03200C90
	  ADD                   * T6.W, -T16.X, 1.0,                                      ; 801F3010 60C00010
	  ADD_INT                 T26.X, T13.X, literal.x,                                ; 001FA00D 03401A10
	  MUL_IEEE              * T4.Z, T16.X, T20.X,  BS:VEC_120/SCL_212                 ; 80028010 40880110
	108(1.513402e-43), 0(0.000000e+00)                                                ; 0000006C 00000000
	  MUL_IEEE                T7.W, T16.X, T19.X,  BS:VEC_021/SCL_122                 ; 00026010 60E40110
	  ADD                   * T6.W, T6.W, -T11.X,                                     ; 82016C06 60C00010
	  ADD_INT                 T19.X, T13.X, literal.x,                                ; 001FA00D 02601A10
	  MULADD_IEEE             T7.W, PS, T22.X, PV.W, BS:VEC_021/SCL_122               ; 0002C0FF 60E70CFE
	  MULADD_IEEE           * T9.W, PS, T23.X, T4.Z,                                  ; 8002E0FF 61230804
	92(1.289195e-43), 0(0.000000e+00)                                                 ; 0000005C 00000000
	ALU clause starting at 0x7d2:                                                     ; 
	  MULADD_IEEE           * T9.W, T11.X, T24.X, T9.W,                               ; 8003000B 61230C09
	  MUL_IEEE              * T10.W, T16.X, T15.X,                                    ; 8001E010 61400110
	  MULADD_IEEE             T4.Z, T6.W, T21.X, PV.W, BS:VEC_102/SCL_221             ; 0002AC06 408F0CFE
	  MUL_IEEE                T6.W, T9.W, T9.W,  BS:VEC_201                           ; 01812C09 60D00110
	  MULADD_IEEE           * T7.W, T11.X, T25.X, T7.W,                               ; 8003200B 60E30C07
	  MULADD_IEEE             T6.W, PS, PS, PV.W,                                     ; 001FE0FF 60C30CFE
	  MULADD_IEEE           * T10.W, T11.X, T18.X, PV.Z,                              ; 8002400B 614308FE
	  ADD_INT                 T15.X, T13.X, literal.x,                                ; 001FA00D 01E01A10
	  MULADD_IEEE             T6.W, PS, PS, PV.W,                                     ; 001FE0FF 60C30CFE
	  ADD_INT               * T18.X, T13.X, literal.y,                                ; 809FA00D 02401A10
	104(1.457350e-43), 88(1.233143e-43)                                               ; 00000068 00000058
	  RECIPSQRT_CLAMPED     * T3.Y, PV.W,                                             ; 80000CFE 20604390
	  ADD_INT                 T20.X, T13.X, literal.x,                                ; 001FA00D 02801A10
	  MUL NON-IEEE            T6.W, T6.W, PS,                                         ; 001FEC06 60C00090
	  ADD_INT               * T21.X, T13.X, literal.y,                                ; 809FA00D 02A01A10
	124(1.737610e-43), 112(1.569454e-43)                                              ; 0000007C 00000070
	  RECIP_IEEE            * T3.Y, PV.W,                                             ; 80000CFE 20604310
	  ADD_INT                 T22.X, T13.X, literal.x,                                ; 001FA00D 02C01A10
	  MUL_IEEE                T6.W, T9.W, PS,                                         ; 001FEC09 60C00110
	  ADD_INT               * T23.X, T13.X, literal.y,                                ; 809FA00D 02E01A10
	96(1.345247e-43), 120(1.681558e-43)                                               ; 00000060 00000078
	  MUL_IEEE                T9.W, PV.W, T26.X,                                      ; 00034CFE 61200110
	  MUL_IEEE              * T7.W, T7.W, T3.Y,                                       ; 80806C07 60E00110
	  ADD_INT                 T24.X, T13.X, literal.x,                                ; 001FA00D 03001A10
	  MULADD_IEEE             T9.W, T19.X, PS, PV.W, BS:VEC_120/SCL_212               ; 001FE013 612B0CFE
	  MUL_IEEE              * T10.W, T10.W, T3.Y,                                     ; 80806C0A 61400110
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	ALU clause starting at 0x7ed:                                                     ; 
	  MUL_IEEE              * T11.W, T6.W, T15.X,                                     ; 8001EC06 61600110
	  MULADD_IEEE             T4.Z, T18.X, T7.W, PV.W,                                ; 0180E012 40830CFE
	  MULADD_IEEE           * T9.W, T20.X, T10.W, T9.W, BS:VEC_120/SCL_212            ; 81814014 612B0C09
	  MUL_IEEE              * T6.W, T6.W, T21.X,                                      ; 8002AC06 60C00110
	  MULADD_IEEE             T5.Z, T22.X, T7.W, PV.W, BS:VEC_021/SCL_122             ; 0180E016 40A70CFE
	  MUL_IEEE                T6.W, T9.W, T9.W,                                       ; 01812C09 60C00110
	  MULADD_IEEE           * T7.W, T23.X, T10.W, T4.Z,                               ; 81814017 60E30804
	  MULADD_IEEE             T6.W, PS, PS, PV.W,                                     ; 001FE0FF 60C30CFE
	  MULADD_IEEE           * T10.W, T24.X, T10.W, PV.Z,                              ; 81814018 614308FE
	  MULADD_IEEE           * T6.W, PS, PS, PV.W,                                     ; 801FE0FF 60C30CFE
	  RECIPSQRT_CLAMPED     * T3.Y, PV.W,                                             ; 80000CFE 20604390
	  MUL NON-IEEE          * T6.W, T6.W, PS,                                         ; 801FEC06 60C00090
	  RECIP_IEEE            * T3.Y, PV.W,                                             ; 80000CFE 20604310
	  MUL_IEEE              * T15.Z, T10.W, PS,                                       ; 801FEC0A 41E00110
	  MUL_IEEE              * T15.Y, T9.W, T3.Y,                                      ; 80806C09 21E00110
	  MUL_IEEE              * T15.X, T7.W, T3.Y,                                      ; 80806C07 01E00110
	ALU clause starting at 0x7fd:                                                     ; 
	  MOV                     T18.X, 0.0,                                             ; 000000F8 02400C90
	  MOV                     T18.Y, 0.0,                                             ; 000000F8 22400C90
	  SETE_INT              * T6.W, T13.X, literal.x,                                 ; 801FA00D 60C01D10
	-1(-nan), 0(0.000000e+00)                                                         ; FFFFFFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x802:                                                     ; 
	  ADD_INT                 T6.W, T13.X, T14.X,  BS:VEC_102/SCL_221                 ; 0001C00D 60CC1A10
	  ADD_INT               * T7.W, T17.X, T13.X,                                     ; 8001A011 60E01A10
	  LSHL                  * T6.W, PV.W, literal.x,                                  ; 801FACFE 60C00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT                 T14.X, T1.Z, PV.W,                                      ; 019FC801 01C01A10
	  LSHL                  * T6.W, T7.W, literal.x,                                  ; 801FAC07 60C00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT                 T17.X, T1.Z, PV.W,                                      ; 019FC801 02201A10
	  ADD_INT               * T6.W, T12.X, T13.X,                                     ; 8001A00C 60C01A10
	  MOV                     T12.X, PV.X,                                            ; 000000FE 01800C90
	  LSHL                  * T6.W, PV.W, literal.x,                                  ; 801FACFE 60C00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT               * T13.X, T1.Z, PV.W,                                      ; 819FC801 01A01A10
	  MOV                     T19.X, PV.X,                                            ; 000000FE 02600C90
	  ADD                   * T6.W, -T16.X, 1.0,                                      ; 801F3010 60C00010
	ALU clause starting at 0x811:                                                     ; 
	  MUL_IEEE                T7.W, T16.X, T17.X,  BS:VEC_021/SCL_122                 ; 00022010 60E40110
	  ADD                   * T6.W, T6.W, -T11.X,                                     ; 82016C06 60C00010
	  MOV                     T17.X, T14.X,                                           ; 0000000E 02200C90
	  MUL_IEEE              * T9.W, T16.X, T12.X,  BS:VEC_120/SCL_212                 ; 80018010 61280110
	  MULADD_IEEE           * T7.W, T6.W, T13.X, T7.W,                                ; 8001AC06 60E30C07
	ALU clause starting at 0x816:                                                     ; 
	  MULADD_IEEE             T18.Y, T11.X, T14.X, T7.W,                              ; 0001C00B 22430C07
	  MULADD_IEEE           * T6.W, T6.W, T19.X, T9.W, BS:VEC_021/SCL_122             ; 80026C06 60C70C09
	  MULADD_IEEE           * T18.X, T11.X, T17.X, PV.W,                              ; 8002200B 02430CFE
	ALU clause starting at 0x819:                                                     ; 
	  ADD_INT               * T6.W, T0.X, literal.x,                                  ; 801FA000 60C01A10
	260(3.643376e-43), 0(0.000000e+00)                                                ; 00000104 00000000
	  LSHR                    T11.X, PV.W, literal.x,                                 ; 001FACFE 01600B10
	  MOV                   * T12.X, T18.Y,                                           ; 80000412 01800C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T6.W, T0.X, literal.x,                                  ; 801FA000 60C01A10
	256(3.587324e-43), 0(0.000000e+00)                                                ; 00000100 00000000
	  LSHR                  * T13.X, PV.W, literal.x,                                 ; 801FACFE 01A00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x822:                                                     ; 
	  ADD_INT               * T11.X, T5.W, T4.W,                                      ; 81808C05 01601A10
	ALU clause starting at 0x823:                                                     ; 
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	296(4.147843e-43), 0(0.000000e+00)                                                ; 00000128 00000000
	  LSHR                  * T12.X, PV.W, literal.x,                                 ; 801FACFE 01800B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x827:                                                     ; 
	  MOV                   * T11.X, T15.Y,                                           ; 8000040F 01600C90
	  SETNE_DX10              T4.W, |PV.X|, |PV.X|,                                   ; 001FC0FE 60800793
	  SETNE_DX10            * T5.W, |T15.X|, |T15.X|,                                 ; 8001E00F 60A00793
	  MOV                     T12.X, T15.Z,                                           ; 0000080F 01800C90
	  OR_INT                  T5.W, PS, PV.W,                                         ; 019FC0FF 60A01890
	  SETGE_DX10            * T6.W, |T11.X|, |T15.X|,                                 ; 8001E00B 60C00713
	  MOV                     T1.Z, literal.x,                                        ; 000000FD 40200C90
	  MUL_IEEE                T4.W, PV.X, PV.X,                                       ; 001FC0FE 60800110
	  OR_INT                * T5.W, PS, PV.W,                                         ; 819FC0FF 60A01890
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MULADD_IEEE           * T5.W, T11.X, T11.X, T4.W, Pred_sel_one                  ; E001600B 60A30C04
	  RECIPSQRT_CLAMPED     * T1.Z, T5.W, Pred_sel_one                                ; E0000C05 40204390
	  MUL NON-IEEE          * T5.W, T5.W, T1.Z, Pred_sel_one                          ; E1002C05 60A00090
	  RECIP_IEEE            * T1.Z, T5.W, Pred_sel_one                                ; E0000C05 40204310
	  MUL_IEEE                T13.Y, T12.X, T1.Z, Pred_sel_one                        ; 6100200C 21A00110
	  MUL_IEEE              * T5.W, T11.X, T1.Z, Pred_sel_one BS:VEC_120/SCL_212      ; E100200B 60A80110
	  MOV                   * T13.Z, -T5.W, Pred_sel_one                              ; E0001C05 41A00C90
	  MOV                     T13.X, 0.0, Pred_sel_one                                ; 600000F8 01A00C90
	  MOV                   * T1.Z, literal.x, Pred_sel_one                           ; E00000FD 40200C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x83c:                                                     ; 
	  SETNE_INT             * T5.W, T1.Z, 1,                                          ; 801F4801 60A01E90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MULADD_IEEE           * T4.W, T15.X, T15.X, T4.W, Pred_sel_zero                 ; C001E00F 60830C04
	  RECIPSQRT_CLAMPED     * T1.Z, T4.W, Pred_sel_zero                               ; C0000C04 40204390
	  MUL NON-IEEE          * T4.W, T4.W, T1.Z, Pred_sel_zero                         ; C1002C04 60800090
	  RECIP_IEEE            * T1.Z, T4.W, Pred_sel_zero                               ; C0000C04 40204310
	  MUL_IEEE              * T4.W, T12.X, T1.Z, Pred_sel_zero                        ; C100200C 60800110
	  MOV                   * T13.X, -T4.W, Pred_sel_zero                             ; C0001C04 01A00C90
	  MUL_IEEE              * T13.Z, T15.X, T1.Z, Pred_sel_zero                       ; C100200F 41A00110
	  MOV                   * T13.Y, 0.0, Pred_sel_zero                               ; C00000F8 21A00C90
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	284(3.979688e-43), 0(0.000000e+00)                                                ; 0000011C 00000000
	  LSHR                    T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 280(3.923636e-43)                                                ; 00000002 00000118
	  LSHR                    T16.X, PV.W, literal.x,                                 ; 001FACFE 02000B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 276(3.867584e-43)                                                ; 00000002 00000114
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 332(4.652311e-43)                                                ; 00000002 0000014C
	  LSHR                    T18.X, PV.W, literal.x,                                 ; 001FACFE 02400B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 328(4.596259e-43)                                                ; 00000002 00000148
	  LSHR                    T19.X, PV.W, literal.x,                                 ; 001FACFE 02600B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 324(4.540207e-43)                                                ; 00000002 00000144
	  LSHR                    T20.X, PV.W, literal.x,                                 ; 001FACFE 02800B10
	  MOV                   * T21.X, T13.Y,                                           ; 8000040D 02A00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE              * T4.W, T11.X, T13.X,                                     ; 8001A00B 60800110
	  MULADD_IEEE             T22.X, T15.X, T21.X, -PV.W,                             ; 0002A00F 02C31CFE
	  MOV                   * T23.X, T13.Z,                                           ; 8000080D 02E00C90
	  ADD_INT               * T4.W, T0.X, literal.x,                                  ; 801FA000 60801A10
	320(4.484155e-43), 0(0.000000e+00)                                                ; 00000140 00000000
	  LSHR                    T24.X, PV.W, literal.x,                                 ; 001FACFE 03000B10
	  MUL_IEEE              * T4.W, T15.X, T23.X,                                     ; 8002E00F 60800110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T25.X, T12.X, T13.X, -PV.W,                             ; 0001A00C 03231CFE
	  ADD_INT               * T4.W, T0.X, literal.x,  BS:VEC_201                      ; 801FA000 60901A10
	316(4.428103e-43), 0(0.000000e+00)                                                ; 0000013C 00000000
	  LSHR                    T26.X, PV.W, literal.x,                                 ; 001FACFE 03400B10
	  MUL_IEEE              * T4.W, T12.X, T21.X,                                     ; 8002A00C 60800110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T27.X, T11.X, T23.X, -PV.W,                             ; 0002E00B 03631CFE
	  ADD_INT               * T4.W, T0.X, literal.x,  BS:VEC_201                      ; 801FA000 60901A10
	312(4.372051e-43), 0(0.000000e+00)                                                ; 00000138 00000000
	  LSHR                    T28.X, PV.W, literal.x,                                 ; 001FACFE 03800B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 308(4.315999e-43)                                                ; 00000002 00000134
	  LSHR                    T29.X, PV.W, literal.x,                                 ; 001FACFE 03A00B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 304(4.259947e-43)                                                ; 00000002 00000130
	  LSHR                    T30.X, PV.W, literal.x,                                 ; 001FACFE 03C00B10
	  ADD_INT               * T4.W, T0.X, literal.y,                                  ; 809FA000 60801A10
	2(2.802597e-45), 300(4.203895e-43)                                                ; 00000002 0000012C
	  LSHR                    T31.X, PV.W, literal.x,                                 ; 001FACFE 03E00B10
	  MOV                   * T4.W, literal.y,                                        ; 800004FD 60800C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x877:                                                     ; 
	  BFE_INT               * T4.W, T4.W, 0.0, 1,                                     ; 801F0C04 6080A0FA
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0x879:                                                     ; 
	  MOV                     T11.X, T0.X,                                            ; 00000000 01600C90
	  MOV                   * T12.X, T6.X,                                            ; 80000006 01800C90
	ALU clause starting at 0x87b:                                                     ; 
	  ADD                     T11.X, T12.X, T11.X,                                    ; 0001600C 01600010
	  ADD_INT               * T4.W, T6.X, literal.x,  BS:VEC_201                      ; 801FA006 60901A10
	8(1.121039e-44), 0(0.000000e+00)                                                  ; 00000008 00000000
	  LSHR                    T12.X, PV.W, literal.x,                                 ; 001FACFE 01800B10
	  MOV                   * T13.X, T0.X,                                            ; 80000000 01A00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MOV                     T14.X, T6.X,                                            ; 00000006 01C00C90
	  MOV                   * T15.X, T0.X,                                            ; 80000000 01E00C90
	  MOV                   * T16.X, T6.X,                                            ; 80000006 02000C90
	ALU clause starting at 0x884:                                                     ; 
	  ADD                     T13.X, T14.X, T13.X,                                    ; 0001A00E 01A00010
	  ADD_INT               * T4.W, T6.X, literal.x,  BS:VEC_201                      ; 801FA006 60901A10
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  LSHR                    T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00B10
	  ADD                   * T15.X, T16.X, T15.X,                                    ; 8001E010 01E00010
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  LSHR                  * T16.X, T6.X, literal.x,                                 ; 801FA006 02000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x88c:                                                     ; 
	  MOV                     T9.W, literal.x,                                        ; 000000FD 61200C90
	  MOV                   * T4.W, literal.y,                                        ; 800004FD 60800C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	ALU clause starting at 0x88f:                                                     ; 
	  MOV                     T10.W, literal.x,                                       ; 000000FD 61400C90
	  SETNE_INT             * T4.W, T4.W, 1,                                          ; 801F4C04 60801E90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MOV                     T10.W, literal.x, Pred_sel_zero                         ; 400000FD 61400C90
	  SETNE_INT             * T3.W, T0.Y, 1, Pred_sel_zero                            ; C01F4400 60601E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	ALU clause starting at 0x896:                                                     ; 
	  BFE_INT               * T3.W, T3.W, 0.0, 1,                                     ; 801F0C03 6060A0FA
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T3.Z, literal.x, Pred_sel_one                           ; E00000FD 40600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T10.W, T3.Z, Pred_sel_one                               ; 60000803 61400C90
	  MOV                   * T3.W, T7.X, Pred_sel_one                                ; E0000007 60600C90
	  MOV                     T0.Y, T3.X, Pred_sel_one                                ; 60000003 20000C90
	  MOV                     T4.W, T4.X, Pred_sel_one BS:VEC_120/SCL_212             ; 60000004 60880C90
	  MOV                   * T0.W, literal.x, Pred_sel_one                           ; E00000FD 60000C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	ALU clause starting at 0x8a0:                                                     ; 
	  SETNE_INT             * T5.W, T10.W, 1,                                         ; 801F4C0A 60A01E90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  ADD_INT                 T10.X, T0.X, literal.x, Pred_sel_zero                   ; 401FA000 01401A10
	  MOV                   * T8.W, literal.y, Pred_sel_zero                          ; C00004FD 61000C90
	104(1.457350e-43), 1(1.401298e-45)                                                ; 00000068 00000001
	ALU clause starting at 0x8a5:                                                     ; 
	  BFE_INT               * T5.W, T8.W, 0.0, 1,                                     ; 801F0C08 60A0A0FA
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0x8a7:                                                     ; 
	  MOV                   * T11.X, T10.X,                                           ; 8000000A 01600C90
	ALU clause starting at 0x8a8:                                                     ; 
	  MULLO_INT             * T1.Z, T11.X, literal.x,                                 ; 801FA00B 40204790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T11.X, T2.W, PS,                                        ; 801FEC02 01601A10
	ALU clause starting at 0x8ab:                                                     ; 
	  SETE_INT                T5.W, T11.X, 0.0,                                       ; 001F000B 60A01D10
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0x8af:                                                     ; 
	  MOV                     T12.X, 0.0,                                             ; 000000F8 01800C90
	  MOV                     T12.Y, 0.0,                                             ; 000000F8 21800C90
	  MOV                     T12.Z, 0.0,                                             ; 000000F8 41800C90
	  LSHL                    T5.W, T4.X, literal.x,                                  ; 001FA004 60A00B90
	  LSHL                  * T6.W, T7.X, literal.y,                                  ; 809FA007 60C00B90
	13(1.821688e-44), 2(2.802597e-45)                                                 ; 0000000D 00000002
	  XOR_INT               * T5.W, PV.W, T4.X,                                       ; 80008CFE 60A01910
	  LSHR                    T11.X, PV.W, literal.x,                                 ; 001FACFE 01600B10
	  LSHL                    T3.Y, T3.X, literal.y,                                  ; 009FA003 20600B90
	  LSHL                    T1.Z, T7.X, literal.z,  BS:VEC_120/SCL_212              ; 011FA007 40280B90
	  XOR_INT                 T5.W, T6.W, T7.X,                                       ; 0000EC06 60A01910
	  LSHL                  * T6.W, T4.X, literal.w,                                  ; 819FA004 60C00B90
	19(2.662467e-44), 3(4.203895e-45)                                                 ; 00000013 00000003
	4(5.605194e-45), 12(1.681558e-44)                                                 ; 00000004 0000000C
	  AND_INT                 T4.X, PS, literal.x,                                    ; 001FA0FF 00801810
	  LSHR                    T4.Y, PV.W, literal.y,                                  ; 009FACFE 20800B10
	  AND_INT                 T4.Z, PV.Z, literal.z,                                  ; 011FA8FE 40801810
	  LSHL                    T5.W, T3.X, literal.w,                                  ; 019FA003 60A00B90
	  XOR_INT               * T7.W, PV.Y, T3.X,                                       ; 800064FE 60E01910
	-8192(-nan), 25(3.503246e-44)                                                     ; FFFFE000 00000019
	-128(-nan), 17(2.382207e-44)                                                      ; FFFFFF80 00000011
	  LSHR                    T3.Y, PS, literal.x,                                    ; 001FA0FF 20600B10
	  AND_INT                 T5.Z, PV.W, literal.y,                                  ; 009FACFE 40A01810
	  OR_INT                  T5.W, PV.Y, PV.Z,                                       ; 011FC4FE 60A01890
	  OR_INT                * T8.W, T11.X, PV.X,                                      ; 801FC00B 61001890
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  XOR_INT                 T9.W, PV.W, PS,                                         ; 001FECFE 61201910
	  OR_INT                * T10.W, PV.Y, PV.Z,                                      ; 811FC4FE 61401890
	  XOR_INT               * T9.W, PV.W, PS,                                         ; 801FECFE 61201910
	  AND_INT               * T9.W, PV.W, literal.x,                                  ; 801FACFE 61201810
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T3.X, PV.W,                                             ; 80000CFE 00604E10
	  ADD                   * T9.W, PS, 0.0,                                          ; 801F00FF 61200010
	  MUL_IEEE              * T9.W, PV.W, literal.x,                                  ; 801FACFE 61200110
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  MUL_IEEE              * T9.W, PV.W, literal.x,                                  ; 801FACFE 61200110
	1082130432(4.000000e+00), 0(0.000000e+00)                                         ; 40800000 00000000
	  FLOOR                 * T9.W, PV.W,                                             ; 80000CFE 61200A10
	  TRUNC                 * T9.W, PV.W,                                             ; 80000CFE 61200890
	  FLT_TO_UINT           * T3.X, PV.W,                                             ; 80000CFE 00604D10
	  SETGT_UINT            * T9.W, PS, literal.x,                                    ; 801FA0FF 61201F10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  CNDE_INT              * T9.W, PV.W, T3.X, literal.x,                            ; 80006CFE 612380FD
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  MULLO_INT             * T3.X, PV.W, literal.x,                                  ; 801FACFE 00604790
	68(9.528830e-44), 0(0.000000e+00)                                                 ; 00000044 00000000
	  ADD_INT               * T14.X, T0.Z, PS,                                        ; 801FE800 01C01A10
	  MOV                     T3.X, PV.X,                                             ; 000000FE 00600C90
	  MOV                   * T4.X, PV.X,                                             ; 800000FE 00800C90
	  MOV                     T11.X, T14.X,                                           ; 0000000E 01600C90
	  MOV                   * T13.X, T14.X,                                           ; 8000000E 01A00C90
	  LSHL                    T9.W, T7.X, literal.x,                                  ; 001FA007 61200B90
	  LSHL                  * T5.W, T5.W, literal.y,                                  ; 809FAC05 60A00B90
	6(8.407791e-45), 4(5.605194e-45)                                                  ; 00000006 00000004
	  MOV                     T16.X, T14.X,                                           ; 0000000E 02000C90
	  AND_INT                 T0.Z, PS, literal.x,                                    ; 001FA0FF 40001810
	  LSHL                    T11.W, T8.W, literal.y,                                 ; 009FAC08 61600B90
	  XOR_INT               * T9.W, PV.W, T1.Z,                                       ; 81002CFE 61201910
	-128(-nan), 13(1.821688e-44)                                                      ; FFFFFF80 0000000D
	  MOV                     T17.X, T14.X,                                           ; 0000000E 02200C90
	  LSHR                    T3.Y, PS, literal.x,                                    ; 001FA0FF 20600B10
	  LSHL                    T1.Z, T10.W, literal.y,                                 ; 009FAC0A 40200B90
	  LSHL                    T8.W, T8.W, literal.z,  BS:VEC_201                      ; 011FAC08 61100B90
	  XOR_INT               * T6.W, PV.W, T6.W,                                       ; 8180CCFE 60C01910
	25(3.503246e-44), 3(4.203895e-45)                                                 ; 00000019 00000003
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  MOV                     T18.X, T14.X,                                           ; 0000000E 02400C90
	  LSHR                    T4.Y, PS, literal.x,                                    ; 001FA0FF 20800B10
	  AND_INT                 T4.Z, PV.W, literal.y,                                  ; 009FACFE 40801810
	  LSHL                    T6.W, T7.W, literal.z,                                  ; 011FAC07 60C00B90
	  XOR_INT               * T7.W, PV.Z, T10.W,                                      ; 818148FE 60E01910
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	6(8.407791e-45), 0(0.000000e+00)                                                  ; 00000006 00000000
	  MOV                     T19.X, T14.X,                                           ; 0000000E 02600C90
	  LSHR                    T5.Y, PS, literal.x,                                    ; 001FA0FF 20A00B10
	  AND_INT                 T1.Z, PV.W, literal.y,                                  ; 009FACFE 40201810
	  OR_INT                  T6.W, PV.Y, PV.Z,                                       ; 011FC4FE 60C01890
	  OR_INT                * T9.W, T0.Z, T3.Y,                                       ; 80806800 61201890
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  MOV                     T20.X, T14.X,                                           ; 0000000E 02800C90
	  XOR_INT                 T10.W, PS, PV.W,                                        ; 019FC0FF 61401910
	  OR_INT                * T11.W, PV.Y, PV.Z,                                      ; 811FC4FE 61601890
	  MOV                     T21.X, T0.X,                                            ; 00000000 02A00C90
	  LSHL                    T0.Z, T7.X, literal.x,  BS:VEC_120/SCL_212              ; 001FA007 40080B90
	  LSHL                    T14.W, T9.W, literal.y,                                 ; 009FAC09 61C00B90
	  XOR_INT               * T9.W, PV.W, PS,                                         ; 801FECFE 61201910
	10(1.401298e-44), 4(5.605194e-45)                                                 ; 0000000A 00000004
	  MOV                     T22.X, T0.X,                                            ; 00000000 02C00C90
	  AND_INT                 T3.Y, PS, literal.x,                                    ; 001FA0FF 20601810
	  AND_INT                 T1.Z, PV.W, literal.y,                                  ; 009FACFE 40201810
	  LSHL                    T9.W, T6.W, literal.z,                                  ; 011FAC06 61200B90
	  XOR_INT               * T5.W, T5.W, PV.Z,                                       ; 811FCC05 60A01910
	16777215(2.350989e-38), -128(-nan)                                                ; 00FFFFFF FFFFFF80
	13(1.821688e-44), 0(0.000000e+00)                                                 ; 0000000D 00000000
	  MOV                     T23.X, T0.X,                                            ; 00000000 02E00C90
	  LSHR                    T4.Y, PS, literal.x,                                    ; 001FA0FF 20800B10
	  LSHL                    T0.Z, T11.W, literal.y,                                 ; 009FAC0B 40000B90
	  LSHL                    T5.W, T6.W, literal.z,  BS:VEC_201                      ; 011FAC06 60B00B90
	  XOR_INT               * T6.W, PV.W, T8.W,                                       ; 81810CFE 60C01910
	25(3.503246e-44), 3(4.203895e-45)                                                 ; 00000019 00000003
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	ALU clause starting at 0x914:                                                     ; 
	  LSHR                    T5.Y, T6.W, literal.x,                                  ; 001FAC06 20A00B10
	  AND_INT                 T4.Z, T5.W, literal.y,  BS:VEC_120/SCL_212              ; 009FAC05 40881810
	  LSHL                  * T6.W, T7.W, literal.z,  BS:VEC_201                      ; 811FAC07 60D00B90
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	6(8.407791e-45), 0(0.000000e+00)                                                  ; 00000006 00000000
	  XOR_INT               * T7.W, T0.Z, T11.W,                                      ; 81816800 60E01910
	  LSHR                    T15.X, PV.W, literal.x,                                 ; 001FACFE 01E00B10
	  AND_INT                 T6.Y, T6.W, literal.y,                                  ; 009FAC06 20C01810
	  OR_INT                  T4.Z, T5.Y, T4.Z,                                       ; 01008405 40801890
	  OR_INT                  T6.W, T1.Z, T4.Y,                                       ; 00808801 60C01890
	  UINT_TO_FLT           * T0.Z, T3.Y,                                             ; 80000403 40004E10
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  XOR_INT                 T1.Z, PV.Z, PV.W,                                       ; 019FC8FE 40201910
	  OR_INT                  T16.W, PV.X, PV.Y,                                      ; 009FC0FE 62001890
	  ADD                   * T8.W, PS, 0.0,                                          ; 801F00FF 61000010
	  MUL_IEEE                T8.W, PS, literal.x,                                    ; 001FA0FF 61000110
	  XOR_INT               * T9.W, PV.Z, PV.W,                                       ; 819FC8FE 61201910
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  AND_INT                 T9.W, PS, literal.x,                                    ; 001FA0FF 61201810
	  RECIPSQRT_CLAMPED     * T0.Z, PV.W,                                             ; 80000CFE 40004390
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T1.Z, PV.W,                                             ; 80000CFE 40204E10
	  ADD                     T10.W, PS, 0.0,                                         ; 001F00FF 61400010
	  MUL NON-IEEE          * T8.W, T8.W, T0.Z,                                       ; 81000C08 61000090
	  ADD                     T9.W, -PS, 1.0,                                         ; 001F30FF 61200010
	  MUL_IEEE              * T10.W, PV.W, literal.x,                                 ; 801FACFE 61400110
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  MUL_IEEE                T8.W, PS, T8.W,                                         ; 018100FF 61000110
	  ADD                   * T10.W, -PV.W, 1.0,                                      ; 801F3CFE 61400010
	  MUL_IEEE                T11.W, T3.X, T9.W,                                      ; 01812003 61600110
	  ADD                   * T10.W, PS, -PV.W,                                       ; 839FC0FF 61400010
	  MUL_IEEE                T13.W, T4.X, T9.W,                                      ; 01812004 61A00110
	  MULADD_IEEE           * T11.W, PS, T11.X, PV.W,                                 ; 800160FF 61630CFE
	  MULADD_IEEE             T15.Z, T8.W, T13.X, PS, BS:VEC_021/SCL_122              ; 0001AC08 41E700FF
	  MUL_IEEE                T11.W, T16.X, T9.W,                                     ; 01812010 61600110
	  MULADD_IEEE           * T13.W, T10.W, T17.X, PV.W,                              ; 80022C0A 61A30CFE
	  MULADD_IEEE             T15.Y, T8.W, T18.X, PS, BS:VEC_021/SCL_122              ; 00024C08 21E700FF
	  MUL_IEEE                T13.W, T0.X, T0.X,                                      ; 00000000 61A00110
	  MULADD_IEEE           * T11.W, T10.W, T19.X, PV.W,                              ; 80026C0A 61630CFE
	  MULADD_IEEE             T15.X, T8.W, T20.X, PS,                                 ; 00028C08 01E300FF
	  MULADD_IEEE           * T11.W, T0.X, T0.X, PV.W,                                ; 80000000 61630CFE
	  MULADD_IEEE           * T15.W, T0.X, T0.X, PV.W,                                ; 80000000 61E30CFE
	  ADD                     T1.Z, T15.Y, -T21.X,                                    ; 0202A40F 40200010
	  ADD                   * T11.W, T16.X, -T19.X,  BS:VEC_021/SCL_122               ; 82026010 61640010
	  ADD                   * T13.W, T13.X, -T11.X,                                   ; 8201600D 61A00010
	  MUL_IEEE                T0.Z, T11.W, PV.W,                                      ; 019FCC0B 40000110
	  MUL_IEEE                T17.W, T1.Z, T1.Z,                                      ; 01002801 62200110
	  ADD                   * T18.W, T15.X, -T22.X,                                   ; 8202C00F 62400010
	  ADD                   * T13.X, T20.X, -T19.X,                                   ; 82026014 01A00010
	  ADD                   * T4.Y, T3.X, -T11.X,                                     ; 82016003 20800010
	  ADD                     T5.Z, T18.X, -T17.X,  BS:VEC_021/SCL_122                ; 02022012 40A40010
	  MULADD_IEEE             T17.W, T18.W, T18.W, T17.W,                             ; 01824C12 62230C11
	  ADD                   * T19.W, T15.Z, -T23.X,                                   ; 8202E80F 62600010
	  MULADD_IEEE             T3.Y, PS, PS, PV.W,                                     ; 001FE0FF 20630CFE
	  MUL_IEEE                T6.Z, T4.Y, PV.Z,                                       ; 011FC404 40C00110
	  MULADD_IEEE             T17.W, T4.Y, T13.X, -T0.Z, BS:VEC_102/SCL_221           ; 0001A404 622F1800
	  ADD                   * T20.W, T4.X, -T17.X,                                    ; 82022004 62800010
	  MUL_IEEE                T4.Y, PS, T13.X,                                        ; 0001A0FF 20800110
	  MUL_IEEE                T7.Z, PV.W, PV.W,                                       ; 019FCCFE 40E00110
	  MULADD_IEEE             T13.W, PS, T13.W, -PV.Z,                                ; 0181A0FF 61A318FE
	  RECIPSQRT_CLAMPED     * T0.Z, PV.Y,                                             ; 800004FE 40004390
	  MUL NON-IEEE            T0.Z, T3.Y, PS,                                         ; 001FE403 40000090
	  MULADD_IEEE             T20.W, PV.W, PV.W, PV.Z,                                ; 019FCCFE 628308FE
	  MULADD_IEEE           * T21.W, T11.W, T5.Z, -PV.Y,                              ; 8100AC0B 62A314FE
	  MULADD_IEEE             T20.W, PS, PS, PV.W,                                    ; 001FE0FF 62830CFE
	  RECIP_IEEE            * T3.X, PV.Z,                                             ; 800008FE 00604310
	  MUL_IEEE                T11.Z, T19.W, PS,                                       ; 001FEC13 41600110
	  RECIPSQRT_CLAMPED     * T4.X, PV.W,                                             ; 80000CFE 00804390
	  MUL_IEEE                T11.Y, T1.Z, T3.X,                                      ; 00006801 21600110
	  MUL NON-IEEE          * T19.W, T20.W, PS,                                       ; 801FEC14 62600090
	  MUL_IEEE                T11.X, T18.W, T3.X,                                     ; 00006C12 01600110
	  RECIP_IEEE            * T1.Z, PV.W,                                             ; 80000CFE 40204310
	  MUL_IEEE                T16.X, T17.W, PS,                                       ; 001FEC11 02000110
	  MUL_IEEE              * T18.X, T13.W, PS,                                       ; 801FEC0D 02400110
	  MUL_IEEE                T17.X, T21.W, T1.Z,                                     ; 01002C15 02200110
	  MOV                   * T18.Y, PV.X,                                            ; 800000FE 22400C90
	  MOV                     T18.Z, PV.X,                                            ; 000000FE 42400C90
	  MUL_IEEE              * T13.W, T16.X, -T11.Y,                                   ; 82816010 61A00110
	  MULADD_IEEE           * T13.W, T18.X, -T11.X, PV.W,                             ; 82016012 61A30CFE
	  MULADD_IEEE             T13.W, T17.X, -T11.Z, PV.W,                             ; 03016011 61A30CFE
	  LSHL                  * T17.W, T16.W, literal.x,                                ; 801FAC10 62200B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  LSHL                    T13.X, T4.Z, literal.x,                                 ; 001FA804 01A00B90
	  LSHL                    T4.Y, T7.W, literal.y,                                  ; 009FAC07 20800B90
	  XOR_INT                 T5.Z, PS, T16.W,                                        ; 018200FF 40A01910
	  LSHL                    T7.W, T7.X, literal.z,                                  ; 011FA007 60E00B90
	  LSHL                  * T16.W, T4.Z, literal.w,                                 ; 819FA804 62000B90
	12(1.681558e-44), 6(8.407791e-45)                                                 ; 0000000C 00000006
	14(1.961818e-44), 13(1.821688e-44)                                                ; 0000000E 0000000D
	  XOR_INT                 T4.X, PS, T5.W,                                         ; 0180A0FF 00801910
	  XOR_INT                 T5.Y, T14.W, PV.W,                                      ; 019FCC0E 20A01910
	  LSHL                    T1.Z, T6.W, literal.x,  BS:VEC_201                      ; 001FAC06 40300B90
	  LSHR                    T6.W, PV.Z, literal.y,                                  ; 009FA8FE 60C00B10
	  AND_INT               * T5.W, PV.Y, literal.z,                                  ; 811FA4FE 60A01810
	4(5.605194e-45), 11(1.541428e-44)                                                 ; 00000004 0000000B
	-2097152(-nan), 0(0.000000e+00)                                                   ; FFE00000 00000000
	  OR_INT                  T3.X, PV.W, PS,                                         ; 001FECFE 00601890
	  AND_INT                 T4.Y, PV.Z, literal.x,                                  ; 001FA8FE 20801810
	  LSHR                    T4.Z, PV.Y, literal.y,                                  ; 009FA4FE 40800B10
	  LSHR                    T5.W, PV.X, literal.z,                                  ; 011FA0FE 60A00B10
	  AND_INT               * T7.W, T13.X, literal.w,                                 ; 819FA00D 60E01810
	-128(-nan), 25(3.503246e-44)                                                      ; FFFFFF80 00000019
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  OR_INT                  T4.X, PV.W, PS,                                         ; 001FECFE 00801890
	  OR_INT                  T5.W, PV.Y, PV.Z,                                       ; 011FC4FE 60A01890
	  SETGT_DX10            * T7.W, literal.x, T13.W,                                 ; 8181A0FD 60E00690
	953267991(1.000000e-04), 0(0.000000e+00)                                          ; 38D1B717 00000000
	ALU clause starting at 0x97f:                                                     ; 
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), T7.W, 0.0,              ; 801F0C07 00002104
	ALU clause starting at 0x980:                                                     ; 
	  MOV                     T12.X, T14.X,                                           ; 0000000E 01800C90
	  MOV                   * T19.X, T14.X,                                           ; 8000000E 02600C90
	  MOV                     T20.X, T14.X,                                           ; 0000000E 02800C90
	  MOV                   * T21.X, T14.X,                                           ; 8000000E 02A00C90
	  MOV                     T22.X, T14.X,                                           ; 0000000E 02C00C90
	  MOV                   * T23.X, T14.X,                                           ; 8000000E 02E00C90
	  MOV                   * T24.X, T14.X,                                           ; 8000000E 03000C90
	ALU clause starting at 0x987:                                                     ; 
	  XOR_INT               * T7.W, T4.X, T5.W,                                       ; 8180A004 60E01910
	  XOR_INT               * T7.W, PV.W, T3.X,                                       ; 80006CFE 60E01910
	  AND_INT               * T7.W, PV.W, literal.x,                                  ; 801FACFE 60E01810
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T4.Y, PV.W,                                             ; 80000CFE 20804E10
	  ADD                   * T7.W, PS, 0.0,                                          ; 801F00FF 60E00010
	  MUL_IEEE                T25.X, PV.W, literal.x,                                 ; 001FACFE 03200110
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	864026624(5.960464e-08), 224(3.138909e-43)                                        ; 33800000 000000E0
	  LSHR                    T26.X, PV.W, literal.x,                                 ; 001FACFE 03400B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 220(3.082857e-43)                                                ; 00000002 000000DC
	  LSHR                    T27.X, PV.W, literal.x,                                 ; 001FACFE 03600B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 216(3.026805e-43)                                                ; 00000002 000000D8
	  LSHR                    T28.X, PV.W, literal.x,                                 ; 001FACFE 03800B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 212(2.970753e-43)                                                ; 00000002 000000D4
	  LSHR                    T29.X, PV.W, literal.x,                                 ; 001FACFE 03A00B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 208(2.914701e-43)                                                ; 00000002 000000D0
	  LSHR                    T30.X, PV.W, literal.x,                                 ; 001FACFE 03C00B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 204(2.858649e-43)                                                ; 00000002 000000CC
	  LSHR                    T31.X, PV.W, literal.x,                                 ; 001FACFE 03E00B10
	  MUL_IEEE                T7.W, T9.W, T12.X,                                      ; 00018C09 60E00110
	  ADD_INT               * T12.W, T0.X, literal.y,                                 ; 809FA000 61801A10
	2(2.802597e-45), 200(2.802597e-43)                                                ; 00000002 000000C8
	  LSHR                    T12.X, PS, literal.x,                                   ; 001FA0FF 01800B10
	  MULADD_IEEE           * T7.W, T10.W, T19.X, PV.W,                               ; 80026C0A 60E30CFE
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T19.X, T8.W, T20.X, PV.W,                               ; 00028C08 02630CFE
	  MUL_IEEE                T7.W, T9.W, T21.X,  BS:VEC_102/SCL_221                  ; 0002AC09 60EC0110
	  ADD_INT               * T9.W, T0.X, literal.x,                                  ; 801FA000 61201A10
	196(2.746545e-43), 0(0.000000e+00)                                                ; 000000C4 00000000
	  LSHR                    T20.X, PS, literal.x,                                   ; 001FA0FF 02800B10
	  MULADD_IEEE           * T7.W, T10.W, T22.X, PV.W,                               ; 8002CC0A 60E30CFE
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T21.X, T8.W, T23.X, PV.W,                               ; 0002EC08 02A30CFE
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	192(2.690493e-43), 0(0.000000e+00)                                                ; 000000C0 00000000
	  LSHR                    T22.X, PV.W, literal.x,                                 ; 001FACFE 02C00B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 188(2.634441e-43)                                                ; 00000002 000000BC
	  LSHR                    T23.X, PV.W, literal.x,                                 ; 001FACFE 02E00B10
	  MOV                   * T32.X, T15.Z,                                           ; 8000080F 04000C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	184(2.578389e-43), 0(0.000000e+00)                                                ; 000000B8 00000000
	  LSHR                    T33.X, PV.W, literal.x,                                 ; 001FACFE 04200B10
	  MOV                   * T34.X, T15.Y,                                           ; 8000040F 04400C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	180(2.522337e-43), 0(0.000000e+00)                                                ; 000000B4 00000000
	  LSHR                    T35.X, PV.W, literal.x,                                 ; 001FACFE 04600B10
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	2(2.802597e-45), 176(2.466285e-43)                                                ; 00000002 000000B0
	  LSHR                    T36.X, PV.W, literal.x,                                 ; 001FACFE 04800B10
	  MOV                   * T37.X, -T18.Z,                                          ; 80001812 04A00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	172(2.410233e-43), 0(0.000000e+00)                                                ; 000000AC 00000000
	  LSHR                    T38.X, PV.W, literal.x,                                 ; 001FACFE 04C00B10
	  MOV                   * T39.X, -T18.Y,                                          ; 80001412 04E00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	168(2.354181e-43), 0(0.000000e+00)                                                ; 000000A8 00000000
	  LSHR                    T40.X, PV.W, literal.x,                                 ; 001FACFE 05000B10
	  MOV                   * T41.X, -T18.X,                                          ; 80001012 05200C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x9cd:                                                     ; 
	  MULLO_INT             * T4.Y, T14.X, literal.x,                                 ; 801FA00E 20804790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T14.X, T2.W, PS,                                        ; 801FEC02 01C01A10
	ALU clause starting at 0x9d0:                                                     ; 
	  MOV                     T12.X, 0.0,                                             ; 000000F8 01800C90
	  MOV                     T12.Y, 0.0,                                             ; 000000F8 21800C90
	  MOV                     T12.Z, 0.0,                                             ; 000000F8 41800C90
	  MUL_IEEE                T7.W, T3.Y, T24.X,                                      ; 00030403 60E00110
	  RECIP_IEEE            * T3.Y, T13.W,                                            ; 80000C0D 20604310
	  MUL_IEEE                T7.W, PV.W, PS,                                         ; 001FECFE 60E00110
	  SETE_INT              * T8.W, T14.X, literal.x,                                 ; 801FA00E 61001D10
	-1(-nan), 0(0.000000e+00)                                                         ; FFFFFFFF 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0x9d9:                                                     ; 
	  MULLO_INT             * T3.Y, T14.X, literal.x,                                 ; 801FA00E 20604790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T14.X, T8.X, PS,                                        ; 801FE008 01C01A10
	  MOV                   * T15.X, PV.X,                                            ; 800000FE 01E00C90
	ALU clause starting at 0x9dd:                                                     ; 
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T9.W, PV.W,                                             ; 00000CFE 61200C90
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T12.W, 1, T15.X,                                        ; 8001E0FA 61801D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x9e4:                                                     ; 
	  MOV                     T9.W, literal.x,                                        ; 000000FD 61200C90
	  SETE_INT              * T10.W, T15.X, 1,                                        ; 801F400F 61401D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0x9e8:                                                     ; 
	  MOV                     T12.X, T14.X,                                           ; 0000000E 01800C90
	  MOV                   * T16.X, T14.X,                                           ; 8000000E 02000C90
	  MOV                   * T17.X, T14.X,                                           ; 8000000E 02200C90
	ALU clause starting at 0x9eb:                                                     ; 
	  MOV                     T12.Y, T16.X,                                           ; 00000010 21800C90
	  MOV                     T12.Z, T17.X,  BS:VEC_120/SCL_212                       ; 00000011 41880C90
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x9ef:                                                     ; 
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x9f1:                                                     ; 
	  BFE_INT               * T10.W, T10.W, 0.0, 1,                                   ; 801F0C0A 6140A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T8.W, literal.x, Pred_sel_zero                          ; 400000FD 61000C90
	  SETNE_INT             * T9.W, T15.X, 0.0, Pred_sel_zero                         ; C01F000F 61201E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T9.W, T9.W, 1,                                          ; 801F4C09 61201810
	  SETE_INT              * T9.W, PV.W, 0.0,                                        ; 801F0CFE 61201D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x9f9:                                                     ; 
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0x9fb:                                                     ; 
	  SETNE_INT             * T8.W, T8.W, 1,                                          ; 801F4C08 61001E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0x9fd:                                                     ; 
	  MOV                   * T14.Y, T14.X,                                           ; 8000000E 21C00C90
	  MOV                   * T14.Z, T14.X,                                           ; 8000000E 41C00C90
	  MOV                     T12.X, T14.X,                                           ; 0000000E 01800C90
	  MOV                     T12.Y, T14.Y,                                           ; 0000040E 21800C90
	  MOV                     T12.Z, PV.Z,                                            ; 000008FE 41800C90
	  MOV                   * T12.W, T14.W,                                           ; 80000C0E 61800C90
	ALU clause starting at 0xa03:                                                     ; 
	  SETE_DX10               T8.W, T12.X, 0.0,                                       ; 001F000C 61000610
	  SETE_DX10             * T9.W, T12.Y, 0.0,                                       ; 801F040C 61200610
	  AND_INT                 T8.W, PV.W, PS,                                         ; 001FECFE 61001810
	  SETE_DX10             * T9.W, T12.Z, 0.0,                                       ; 801F080C 61200610
	  AND_INT               * T8.W, PV.W, PS,                                         ; 801FECFE 61001810
	  SETGT_INT               T8.W, 0.0, PV.W,                                        ; 019FC0F8 61001D90
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa0c:                                                     ; 
	  MOV                     T15.X, T0.X,                                            ; 00000000 01E00C90
	  MOV                   * T17.X, T9.X,                                            ; 80000009 02200C90
	  MOV                     T18.X, T9.X,                                            ; 00000009 02400C90
	  MOV                   * T19.X, T0.X,                                            ; 80000000 02600C90
	  MOV                     T20.X, T0.X,                                            ; 00000000 02800C90
	  MOV                   * T21.X, T9.X,                                            ; 80000009 02A00C90
	ALU clause starting at 0xa12:                                                     ; 
	  MOV                     T16.X, 0.0,                                             ; 000000F8 02000C90
	  MOV                     T16.Y, 0.0,                                             ; 000000F8 22000C90
	  MOV                     T16.Z, 0.0,                                             ; 000000F8 42000C90
	  MOV                   * T14.X, T11.Y,                                           ; 8000040B 01C00C90
	  MUL_IEEE                T8.W, PS, T15.X,                                        ; 0001E0FF 61000110
	  MUL_IEEE              * T9.W, T17.X, T15.X,                                     ; 8001E011 61200110
	  MOV                     T15.X, T11.Z,                                           ; 0000080B 01E00C90
	  MULADD_IEEE             T10.W, T18.X, T19.X, PS,                                ; 00026012 614300FF
	  MULADD_IEEE           * T8.W, T11.X, T19.X, PV.W,                               ; 8002600B 61030CFE
	  MULADD_IEEE             T9.W, PV.X, T20.X, PS,                                  ; 000280FE 612300FF
	  MULADD_IEEE           * T10.W, T21.X, T20.X, PV.W,                              ; 80028015 61430CFE
	  SETGE_DX10              T3.Y, |PS|, literal.x,                                  ; 001FA0FF 20600711
	  SETNE_DX10              T4.Z, |PS|, |PS|,                                       ; 001FE0FF 40800793
	  SETGE_DX10              T8.W, |PV.W|, literal.x,                                ; 001FACFE 61000711
	  SETNE_DX10            * T13.W, |PV.W|, |PV.W|,                                  ; 819FCCFE 61A00793
	953267991(1.000000e-04), 0(0.000000e+00)                                          ; 38D1B717 00000000
	  OR_INT                  T8.W, PV.W, PS,                                         ; 001FECFE 61001890
	  OR_INT                * T13.W, PV.Y, PV.Z,                                      ; 811FC4FE 61A01890
	  AND_INT               * T8.W, PV.W, PS,                                         ; 801FECFE 61001810
	  AND_INT               * T8.W, PV.W, 1,                                          ; 801F4CFE 61001810
	  SETE_INT              * T8.W, PV.W, 0.0,                                        ; 801F0CFE 61001D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa28:                                                     ; 
	  MULLO_INT             * T3.Y, T10.X, literal.x,                                 ; 801FA00A 20604790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T10.X, T2.W, PS,                                        ; 801FEC02 01401A10
	  MOV                   * T17.X, PV.X,                                            ; 800000FE 02200C90
	ALU clause starting at 0xa2c:                                                     ; 
	  MUL_IEEE                T8.W, T9.W, T10.W,                                      ; 01814C09 61000110
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T13.W, PS,                                              ; 000000FF 61A00C90
	  MOV                   * T14.W, literal.x,                                       ; 800000FD 61C00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T10.W, literal.x, T17.X,                                ; 800220FD 61401D90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                     T16.X, 0.0, Pred_sel_zero                               ; 400000F8 02000C90
	  MOV                     T16.Y, 0.0, Pred_sel_zero                               ; 400000F8 22000C90
	  MOV                     T16.Z, 0.0, Pred_sel_zero                               ; 400000F8 42000C90
	  SETNE_INT               T13.W, T17.X, literal.x, Pred_sel_zero                  ; 401FA011 61A01E90
	  MOV                   * T14.W, literal.y, Pred_sel_zero                         ; C00004FD 61C00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0xa3b:                                                     ; 
	  MOV                     T10.W, T9.W,                                            ; 00000C09 61400C90
	  SETNE_INT             * T14.W, T14.W, 1,                                        ; 801F4C0E 61C01E90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MOV                     T10.W, literal.x, Pred_sel_zero                         ; 400000FD 61400C90
	  SETNE_INT             * T13.W, T17.X, 0.0, Pred_sel_zero                        ; C01F0011 61A01E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T13.W, T13.W, 1,                                        ; 801F4C0D 61A01810
	  SETE_INT              * T13.W, PV.W, 0.0,                                       ; 801F0CFE 61A01D10
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T16.X, 0.0, Pred_sel_one                                ; 600000F8 02000C90
	  MOV                     T16.Y, 0.0, Pred_sel_one                                ; 600000F8 22000C90
	  MOV                     T16.Z, 0.0, Pred_sel_one                                ; 600000F8 42000C90
	  SETE_DX10               T9.W, T8.W, 0.0, Pred_sel_one                           ; 601F0C08 61200610
	  SETNE_DX10            * T10.W, T8.W, T8.W, Pred_sel_one                         ; E1810C08 61400790
	  OR_INT                  T9.W, T9.W, T10.W, Pred_sel_one                         ; 61814C09 61201890
	  SETE_INT              * T13.W, T17.X, 0.0, Pred_sel_one                         ; E01F0011 61A01D10
	  MOV                     T10.W, literal.x, Pred_sel_one                          ; 600000FD 61400C90
	  AND_INT               * T9.W, T9.W, T13.W, Pred_sel_one                         ; E181AC09 61201810
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  BFE_INT               * T10.W, T10.W, 0.0, 1,                                   ; 801F0C0A 6140A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T16.X, 0.0, Pred_sel_zero                               ; 400000F8 02000C90
	  MOV                     T16.Y, 0.0, Pred_sel_zero                               ; 400000F8 22000C90
	  MOV                     T16.Z, 0.0, Pred_sel_zero                               ; 400000F8 42000C90
	  SETGE_DX10              T9.W, T8.W, 0.0, Pred_sel_zero                          ; 401F0C08 61200710
	  SETNE_DX10            * T8.W, T8.W, T8.W, Pred_sel_zero                         ; C1810C08 61000790
	  OR_INT                * T9.W, T9.W, T8.W, Pred_sel_zero                         ; C1810C09 61201890
	  AND_INT               * T8.W, T9.W, 1,                                          ; 801F4C09 61001810
	  SETE_INT              * T8.W, PV.W, 0.0,                                        ; 801F0CFE 61001D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa59:                                                     ; 
	  MOV                   * T17.X, T0.X,                                            ; 80000000 02200C90
	ALU clause starting at 0xa5a:                                                     ; 
	  MOV                     T18.X, T0.X,                                            ; 00000000 02400C90
	  MOV                   * T19.X, T0.X,                                            ; 80000000 02600C90
	  MULLO_INT             * T3.Y, T10.X, literal.x,                                 ; 801FA00A 20604790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT                 T16.X, T8.X, PS,                                        ; 001FE008 02001A10
	  MUL_IEEE              * T8.W, T14.X, T17.X,  BS:VEC_120/SCL_212                 ; 8002200E 61080110
	ALU clause starting at 0xa60:                                                     ; 
	  MULADD_IEEE           * T8.W, T11.X, T18.X, T8.W,                               ; 8002400B 61030C08
	  MULADD_IEEE           * T8.W, T15.X, T19.X, PV.W,                               ; 8002600F 61030CFE
	  MUL_IEEE              * T8.W, PV.W, literal.x,                                  ; 801FACFE 61000110
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  MOV                     T8.W, |PV.W|,                                           ; 00000CFE 61000C91
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T10.W, PS,                                              ; 000000FF 61400C90
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T14.W, 1, T16.X,                                        ; 800200FA 61C01D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa6c:                                                     ; 
	  MOV                     T10.W, literal.x,                                       ; 000000FD 61400C90
	  SETE_INT              * T13.W, T16.X, 1,                                        ; 801F4010 61A01D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xa70:                                                     ; 
	  MULLO_INT             * T3.Y, T10.X, literal.x,                                 ; 801FA00A 20604790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T18.X, T8.X, PS,                                        ; 801FE008 02401A10
	  MOV                     T19.X, PV.X,                                            ; 000000FE 02600C90
	  MOV                   * T17.X, PV.X,                                            ; 800000FE 02200C90
	ALU clause starting at 0xa75:                                                     ; 
	  MOV                     T17.Y, T19.X,                                           ; 00000013 22200C90
	  MOV                     T17.Z, T18.X,  BS:VEC_120/SCL_212                       ; 00000012 42280C90
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xa79:                                                     ; 
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xa7b:                                                     ; 
	  BFE_INT               * T13.W, T13.W, 0.0, 1,                                   ; 801F0C0D 61A0A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T9.W, literal.x, Pred_sel_zero                          ; 400000FD 61200C90
	  SETNE_INT             * T10.W, T16.X, 0.0, Pred_sel_zero                        ; C01F0010 61401E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T10.W, T10.W, 1,                                        ; 801F4C0A 61401810
	  SETE_INT              * T10.W, PV.W, 0.0,                                       ; 801F0CFE 61401D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa83:                                                     ; 
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xa85:                                                     ; 
	  SETNE_INT             * T9.W, T9.W, 1,                                          ; 801F4C09 61201E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xa87:                                                     ; 
	  MULLO_INT             * T3.Y, T10.X, literal.x,                                 ; 801FA00A 20604790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T17.X, T8.X, PS,                                        ; 801FE008 02201A10
	ALU clause starting at 0xa8a:                                                     ; 
	  MOV                   * T17.Y, T17.X,                                           ; 80000011 22200C90
	  MOV                   * T17.Z, T17.X,                                           ; 80000011 42200C90
	ALU clause starting at 0xa8c:                                                     ; 
	  SETGT_DX10              T9.W, T0.X, T17.W,                                      ; 01822000 61200690
	  MUL_IEEE              * T10.W, T17.W, T0.X,                                     ; 80000C11 61400110
	  CNDE_INT                T3.Y, PV.W, PS, T0.X,                                   ; 001FECFE 20638000
	  SETGT_DX10              T4.Z, T17.W, T0.X,                                      ; 00000C11 40800690
	  SETGT_DX10              T9.W, 0.0, T17.Z,                                       ; 010220F8 61200690
	  MUL_IEEE              * T10.W, T17.Z, literal.x,                                ; 801FA811 61400110
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  SETGT_DX10              T10.X, 0.0, T17.Y,                                      ; 008220F8 01400690
	  MUL_IEEE                T4.Y, T17.Y, literal.x,                                 ; 001FA411 20800110
	  CNDE_INT                T5.Z, PV.W, PS, 0.0,                                    ; 001FECFE 40A380F8
	  SETGT_DX10              T9.W, T17.Z, 1.0,                                       ; 001F2811 61200690
	  CNDE_INT              * T16.W, PV.Z, PV.Y, T0.X,                                ; 809FC8FE 62038000
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  SETGT_DX10              T18.X, 0.0, T17.X,                                      ; 000220F8 02400690
	  MUL_IEEE                T3.Y, T17.X, literal.x,                                 ; 001FA011 20600110
	  CNDE_INT                T16.Z, PV.W, PV.Z, literal.x,                           ; 011FCCFE 420380FD
	  CNDE_INT                T9.W, PV.X, PV.Y, 0.0,                                  ; 009FC0FE 612380F8
	  SETGT_DX10            * T10.W, T17.Y, 1.0,                                      ; 801F2411 61400690
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  CNDE_INT                T16.Y, PS, PV.W, literal.x,                             ; 019FC0FF 220380FD
	  CNDE_INT                T9.W, PV.X, PV.Y, 0.0,                                  ; 009FC0FE 612380F8
	  SETGT_DX10            * T10.W, T17.X, 1.0,                                      ; 801F2011 61400690
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  CNDE_INT              * T16.X, PS, PV.W, literal.x,                             ; 819FC0FF 020380FD
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	ALU clause starting at 0xaa5:                                                     ; 
	  ADD_INT                 T10.X, T0.X, literal.x,                                 ; 001FA000 01401A10
	  SETE_DX10               T9.W, T16.X, 0.0,  BS:VEC_120/SCL_212                   ; 001F0010 61280610
	  SETE_DX10             * T10.W, T16.Y, 0.0,                                      ; 801F0410 61400610
	56(7.847271e-44), 0(0.000000e+00)                                                 ; 00000038 00000000
	  AND_INT                 T9.W, PV.W, PS,                                         ; 001FECFE 61201810
	  SETE_DX10             * T10.W, T16.Z, 0.0,                                      ; 801F0810 61400610
	  AND_INT               * T9.W, PV.W, PS,                                         ; 801FECFE 61201810
	  SETGT_INT               T10.W, 0.0, PV.W,                                       ; 019FC0F8 61401D90
	  MOV                   * T9.W, literal.x,                                        ; 800000FD 61200C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xab0:                                                     ; 
	  MOV                     T5.X, T0.X,                                             ; 00000000 00A00C90
	  MOV                   * T18.X, T0.X,                                            ; 80000000 02400C90
	  MOV                     T17.X, T0.X,                                            ; 00000000 02200C90
	  MOV                   * T19.X, T0.X,                                            ; 80000000 02600C90
	  MOV                   * T20.X, T0.X,                                            ; 80000000 02800C90
	ALU clause starting at 0xab5:                                                     ; 
	  MOV                   * T17.Y, T19.X,                                           ; 80000013 22200C90
	  MOV                     T19.X, T0.X,                                            ; 00000000 02600C90
	  MOV                     T17.Z, T20.X,  BS:VEC_201                               ; 00000014 42300C90
	  MOV                     T0.W, literal.x,                                        ; 000000FD 60000C90
	  SETGT_UINT            * T3.W, literal.y, T1.X,                                  ; 800024FD 60601F10
	1065353216(1.000000e+00), 5(7.006492e-45)                                         ; 3F800000 00000005
	ALU clause starting at 0xabb:                                                     ; 
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), T3.W, 0.0,              ; 801F0C03 00002104
	ALU clause starting at 0xabc:                                                     ; 
	  MAX                   * T0.W, T16.Y, T16.Z,                                     ; 81020410 60000190
	  MAX                   * T3.W, T16.X, PV.W,                                      ; 819FC010 60600190
	  SETGT_DX10              T4.W, PV.W, 1.0,                                        ; 001F2CFE 60800690
	  MOV                   * T0.W, literal.x,                                        ; 800000FD 60000C90
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MAX                   * T0.W, T3.W, 0.5, Pred_sel_zero                          ; C01F8C03 60000190
	ALU clause starting at 0xac3:                                                     ; 
	  LSHL                    T3.W, T7.X, literal.x,                                  ; 001FA007 60600B90
	  LSHL                  * T4.W, T4.X, literal.y,                                  ; 809FA004 60800B90
	18(2.522337e-44), 13(1.821688e-44)                                                ; 00000012 0000000D
	  XOR_INT               * T3.W, T1.Z, PV.W,                                       ; 819FC801 60601910
	  LSHR                    T7.X, PV.W, literal.x,                                  ; 001FACFE 00E00B10
	  LSHL                    T0.Y, T3.X, literal.y,                                  ; 009FA003 20000B90
	  LSHL                    T1.Z, T4.X, literal.z,  BS:VEC_120/SCL_212              ; 011FA004 40280B90
	  XOR_INT                 T3.W, T4.W, T13.X,  BS:VEC_021/SCL_122                  ; 0001AC04 60641910
	  LSHL                  * T4.W, T5.W, literal.w,                                  ; 819FAC05 60800B90
	25(3.503246e-44), 3(4.203895e-45)                                                 ; 00000019 00000003
	12(1.681558e-44), 4(5.605194e-45)                                                 ; 0000000C 00000004
	  AND_INT                 T13.X, PS, literal.x,                                   ; 001FA0FF 01A01810
	  LSHR                    T3.Y, PV.W, literal.y,                                  ; 009FACFE 20600B10
	  AND_INT                 T1.Z, PV.Z, literal.z,                                  ; 011FA8FE 40201810
	  LSHL                    T3.W, T6.W, literal.w,                                  ; 019FAC06 60600B90
	  XOR_INT               * T4.W, PV.Y, T3.X,                                       ; 800064FE 60801910
	-128(-nan), 19(2.662467e-44)                                                      ; FFFFFF80 00000013
	-8192(-nan), 17(2.382207e-44)                                                     ; FFFFE000 00000011
	  MUL_IEEE                T20.X, T8.W, T0.W,                                      ; 01800C08 02800110
	  LSHR                    T0.Y, PS, literal.x,                                    ; 001FA0FF 20000B10
	  AND_INT                 T4.Z, PV.W, literal.y,                                  ; 009FACFE 40801810
	  OR_INT                  T4.W, PV.Y, PV.Z,                                       ; 011FC4FE 60801890
	  OR_INT                * T3.W, PV.X, T7.X,                                       ; 8000E0FE 60601890
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  XOR_INT                 T7.X, PV.W, PS,                                         ; 001FECFE 00E01910
	  OR_INT                  T0.Y, PV.Y, PV.Z,                                       ; 011FC4FE 20001890
	  MUL_IEEE                T1.Z, T14.X, T18.X,                                     ; 0002400E 40200110
	  MUL_IEEE                T0.W, PV.X, PV.X,                                       ; 001FC0FE 60000110
	  MUL_IEEE              * T6.W, T7.W, literal.x,                                  ; 801FAC07 60C00110
	1048576000(2.500000e-01), 0(0.000000e+00)                                         ; 3E800000 00000000
	  MULADD_IEEE             T3.Y, PS, PS, PV.W,                                     ; 001FE0FF 20630CFE
	  MULADD_IEEE             T1.Z, T11.X, T5.X, PV.Z,                                ; 0000A00B 402308FE
	  XOR_INT                 T0.W, PV.X, PV.Y,                                       ; 009FC0FE 60001910
	  RECIP_IEEE            * T4.Y, PS,                                               ; 800000FF 20804310
	  AND_INT                 T5.Y, PV.W, literal.x,                                  ; 001FACFE 20A01810
	  MULADD_IEEE             T1.Z, T15.X, T19.X, PV.Z,                               ; 0002600F 402308FE
	  MUL_IEEE                T0.W, T6.W, T6.W,                                       ; 0180CC06 60000110
	  RECIP_IEEE            * T3.Y, PV.Y,                                             ; 800004FE 20604310
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  MUL_IEEE                T4.Z, PV.W, PS,                                         ; 001FECFE 40800110
	  MUL_IEEE                T0.W, |PV.Z|, T4.Y,                                     ; 008088FE 60000111
	  UINT_TO_FLT           * T1.Z, PV.Y,                                             ; 800004FE 40204E10
	  MUL_IEEE                T0.W, PV.W, PV.Z,                                       ; 011FCCFE 60000110
	  ADD                   * T6.W, PS, 0.0,                                          ; 801F00FF 60C00010
	  MUL_IEEE                T5.X, PS, literal.x,                                    ; 001FA0FF 00A00110
	  MUL_IEEE                T6.W, T17.Z, PV.W,                                      ; 019FC811 60C00110
	  ADD_INT               * T7.W, T0.X, literal.y,                                  ; 809FA000 60E01A10
	864026624(5.960464e-08), 228(3.194960e-43)                                        ; 33800000 000000E4
	  LSHR                    T7.X, PS, literal.x,                                    ; 001FA0FF 00E00B10
	  MUL_IEEE              * T6.W, T16.Z, PV.W,                                      ; 819FC810 60C00110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T13.X, T12.Z, PV.W,                                     ; 019FC80C 01A00110
	  MUL_IEEE                T6.W, T17.Y, T0.W,                                      ; 01800411 60C00110
	  ADD_INT               * T7.W, T0.X, literal.x,                                  ; 801FA000 60E01A10
	156(2.186026e-43), 0(0.000000e+00)                                                ; 0000009C 00000000
	  LSHR                    T18.X, PS, literal.x,                                   ; 001FA0FF 02400B10
	  MUL_IEEE              * T6.W, T16.Y, PV.W,                                      ; 819FC410 60C00110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T19.X, T12.Y, PV.W,                                     ; 019FC40C 02600110
	  MUL_IEEE                T0.W, T17.X, T0.W,                                      ; 01800011 60000110
	  ADD_INT               * T6.W, T0.X, literal.x,                                  ; 801FA000 60C01A10
	152(2.129974e-43), 0(0.000000e+00)                                                ; 00000098 00000000
	  LSHR                    T17.X, PS, literal.x,                                   ; 001FA0FF 02200B10
	  MUL_IEEE              * T0.W, T16.X, PV.W,                                      ; 819FC010 60000110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T12.X, T12.X, PV.W,                                     ; 019FC00C 01800110
	  ADD_INT               * T0.W, T0.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA000 60081A10
	148(2.073922e-43), 0(0.000000e+00)                                                ; 00000094 00000000
	  LSHR                  * T16.X, PV.W, literal.x,                                 ; 801FACFE 02000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0xb09:                                                     ; 
	  MOV                     T7.X, T10.X,                                            ; 0000000A 00E00C90
	  MOV                   * T12.X, T10.X,                                           ; 8000000A 01800C90
	ALU clause starting at 0xb0b:                                                     ; 
	  ADD_INT               * T0.W, T12.X, literal.x,                                 ; 801FA00C 60001A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T7.W, PV.W, -T12.X,                                     ; 02018CFE 60E00010
	  MOV                   * T0.W, literal.x,                                        ; 800000FD 60000C90
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  MOV                     T6.W, PS,                                               ; 000000FF 60C00C90
	  SETGT_DX10            * T8.W, |PV.W|, literal.x,                                ; 801FACFE 61000691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MOV                   * T6.W, |T7.W|, Pred_sel_zero                             ; C0000C07 60C00C91
	  MAX                   * T6.W, T6.W, literal.x, Pred_sel_zero                    ; C01FAC06 60C00190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T7.W, T7.X, literal.x,                                  ; 801FA007 60E01A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T8.W, PV.W, -T7.X,                                      ; 0200ECFE 61000010
	  MOV                   * T7.W, T0.W,                                             ; 80000C00 60E00C90
	  SETGT_DX10            * T9.W, |PV.W|, literal.x,                                ; 801FACFE 61200691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T7.W, |T8.W|, Pred_sel_zero                             ; C0000C08 60E00C91
	  MAX                   * T7.W, T7.W, literal.x, Pred_sel_zero                    ; C01FAC07 60E00190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T8.W, T10.X, literal.x,                                 ; 801FA00A 61001A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T9.W, PV.W, -T10.X,                                     ; 02014CFE 61200010
	  MOV                   * T8.W, T0.W,                                             ; 80000C00 61000C90
	  SETGT_DX10            * T10.W, |PV.W|, literal.x,                               ; 801FACFE 61400691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T8.W, |T9.W|, Pred_sel_zero                             ; C0000C09 61000C91
	  MAX                   * T8.W, T8.W, literal.x, Pred_sel_zero                    ; C01FAC08 61000190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T9.W, T0.Z, literal.x,                                  ; 801FA800 61201A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T9.W, PV.W, -T0.Z,                                      ; 03000CFE 61200010
	  MAX                   * T7.W, T7.W, T8.W,                                       ; 81810C07 60E00190
	  MAX                     T6.W, T6.W, PS,                                         ; 001FEC06 60C00190
	  SETGT_DX10            * T7.W, |PV.W|, literal.x,                                ; 801FACFE 60E00691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MOV                   * T0.W, |T9.W|, Pred_sel_zero                             ; C0000C09 60000C91
	  MAX                   * T0.W, T0.W, literal.x, Pred_sel_zero                    ; C01FAC00 60000190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  MOV                     T5.X, literal.x,                                        ; 000000FD 00A00C90
	  MAX                   * T13.X, T6.W, T0.W,                                      ; 81800C06 01A00190
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD                     T16.X, T0.Z, -PS,                                       ; 021FE800 02000010
	  ADD_INT               * T0.W, T2.X, literal.x,                                  ; 801FA002 60001A10
	28(3.923636e-44), 0(0.000000e+00)                                                 ; 0000001C 00000000
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 24(3.363116e-44)                                                 ; 00000002 00000018
	  LSHR                    T18.X, PV.W, literal.x,                                 ; 001FACFE 02400B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 20(2.802597e-44)                                                 ; 00000002 00000014
	  LSHR                    T19.X, PV.W, literal.x,                                 ; 001FACFE 02600B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 16(2.242078e-44)                                                 ; 00000002 00000010
	  LSHR                    T20.X, PV.W, literal.x,                                 ; 001FACFE 02800B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 12(1.681558e-44)                                                 ; 00000002 0000000C
	  LSHR                    T21.X, PV.W, literal.x,                                 ; 001FACFE 02A00B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 8(1.121039e-44)                                                  ; 00000002 00000008
	  LSHR                    T22.X, PV.W, literal.x,                                 ; 001FACFE 02C00B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 4(5.605194e-45)                                                  ; 00000002 00000004
	  LSHR                    T23.X, PV.W, literal.x,                                 ; 001FACFE 02E00B10
	  LSHR                  * T24.X, T2.X, literal.x,                                 ; 801FA002 03000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MOV                     T0.W, literal.x,                                        ; 000000FD 60000C90
	  MOV                   * T9.W, literal.y,                                        ; 800004FD 61200C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	ALU clause starting at 0xb54:                                                     ; 
	  MOV                   * T7.X, T5.W,                                             ; 80000C05 00E00C90
	ALU clause starting at 0xb55:                                                     ; 
	  MOV                     T11.X, literal.x,                                       ; 000000FD 01600C90
	  BFE_INT               * T5.W, T9.W, 0.0, 1,                                     ; 801F0C09 60A0A0FA
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xb59:                                                     ; 
	  MOV                     T3.Z, literal.x,                                        ; 000000FD 40600C90
	  SETGT_UINT            * T5.W, literal.y, T1.X,                                  ; 800024FD 60A01F10
	1(1.401298e-45), 16(2.242078e-44)                                                 ; 00000001 00000010
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xb5d:                                                     ; 
	  LSHL                  * T5.W, T4.X, literal.x,                                  ; 801FA004 60A00B90
	13(1.821688e-44), 0(0.000000e+00)                                                 ; 0000000D 00000000
	  MOV                     T12.X, T0.X,                                            ; 00000000 01800C90
	  LSHL                    T6.W, T4.X, literal.x,  BS:VEC_120/SCL_212              ; 001FA004 60C80B90
	  XOR_INT               * T5.W, PV.W, T4.X,                                       ; 80008CFE 60A01910
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  MOV                     T10.X, T0.X,                                            ; 00000000 01400C90
	  LSHR                    T5.W, PS, literal.x,                                    ; 001FA0FF 60A00B10
	  AND_INT               * T7.W, PV.W, literal.y,                                  ; 809FACFE 60E01810
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  MOV                     T11.X, T0.X,                                            ; 00000000 01600C90
	  LSHL                    T8.W, T3.X, literal.x,  BS:VEC_120/SCL_212              ; 001FA003 61080B90
	  OR_INT                * T7.W, PV.W, PS,                                         ; 801FECFE 60E01890
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  MOV                     T25.X, T0.X,                                            ; 00000000 03200C90
	  LSHL                    T1.Y, PS, literal.x,                                    ; 001FA0FF 20200B90
	  LSHL                    T0.Z, T3.X, literal.y,  BS:VEC_120/SCL_212              ; 009FA003 40080B90
	  XOR_INT                 T5.W, PV.W, T3.X,                                       ; 00006CFE 60A01910
	  LSHL                  * T8.W, T7.X, literal.z,                                  ; 811FA007 61000B90
	12(1.681558e-44), 17(2.382207e-44)                                                ; 0000000C 00000011
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MOV                     T19.X, T0.X,                                            ; 00000000 02600C90
	  LSHL                    T2.Y, T7.X, literal.x,  BS:VEC_120/SCL_212              ; 001FA007 20480B90
	  XOR_INT                 T1.Z, PS, T7.X,                                         ; 0000E0FF 40201910
	  LSHR                    T8.W, PV.W, literal.y,                                  ; 009FACFE 61000B10
	  AND_INT               * T9.W, PV.Z, literal.z,                                  ; 811FA8FE 61201810
	4(5.605194e-45), 11(1.541428e-44)                                                 ; 00000004 0000000B
	-2097152(-nan), 0(0.000000e+00)                                                   ; FFE00000 00000000
	  MOV                     T20.X, T9.X,                                            ; 00000009 02800C90
	  OR_INT                  T3.Y, PV.W, PS,                                         ; 001FECFE 20601890
	  LSHR                    T0.Z, PV.Z, literal.x,                                  ; 001FA8FE 40000B10
	  AND_INT                 T8.W, PV.Y, literal.y,                                  ; 009FA4FE 61001810
	  LSHL                  * T9.W, T7.W, literal.z,                                  ; 811FAC07 61200B90
	25(3.503246e-44), -128(-nan)                                                      ; 00000019 FFFFFF80
	13(1.821688e-44), 0(0.000000e+00)                                                 ; 0000000D 00000000
	  MOV                     T13.X, T0.X,                                            ; 00000000 01A00C90
	  XOR_INT                 T4.Y, PS, T6.W,                                         ; 0180C0FF 20801910
	  OR_INT                  T0.Z, PV.Z, PV.W,                                       ; 019FC8FE 40001890
	  LSHL                    T6.W, T7.X, literal.x,  BS:VEC_120/SCL_212              ; 001FA007 60C80B90
	  LSHL                  * T8.W, PV.Y, literal.y,                                  ; 809FA4FE 61000B90
	6(8.407791e-45), 3(4.203895e-45)                                                  ; 00000006 00000003
	  MOV                     T14.X, T0.X,                                            ; 00000000 01C00C90
	  LSHL                    T5.Y, T5.W, literal.x,                                  ; 001FAC05 20A00B90
	  XOR_INT                 T1.Z, PS, T3.Y,                                         ; 008060FF 40201910
	  XOR_INT                 T6.W, PV.W, T2.Y,  BS:VEC_021/SCL_122                   ; 00804CFE 60C41910
	  LSHL                  * T5.W, PV.Z, literal.y,                                  ; 809FA8FE 60A00B90
	6(8.407791e-45), 4(5.605194e-45)                                                  ; 00000006 00000004
	  MOV                     T15.X, T0.X,                                            ; 00000000 01E00C90
	  AND_INT                 T2.Y, PS, literal.x,                                    ; 001FA0FF 20401810
	  LSHR                    T2.Z, PV.W, literal.y,                                  ; 009FACFE 40400B10
	  LSHR                    T6.W, PV.Z, literal.z,                                  ; 011FA8FE 60C00B10
	  AND_INT               * T8.W, PV.Y, literal.w,                                  ; 819FA4FE 61001810
	-128(-nan), 25(3.503246e-44)                                                      ; FFFFFF80 00000019
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  OR_INT                  T3.X, PV.W, PS,                                         ; 001FECFE 00601890
	  OR_INT                  T1.Z, PV.Y, PV.Z,                                       ; 011FC4FE 40201890
	  LSHR                    T8.W, T4.Y, literal.x,                                  ; 001FA404 61000B10
	  AND_INT               * T9.W, T1.Y, literal.y,                                  ; 809FA401 61201810
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  OR_INT                  T4.X, PV.W, PS,                                         ; 001FECFE 00801890
	  XOR_INT                 T8.W, PV.X, PV.Z,                                       ; 011FC0FE 61001910
	  MOV                   * T18.X, T0.X,                                            ; 80000000 02400C90
	  XOR_INT               * T8.W, PV.W, PV.X,                                       ; 801FCCFE 61001910
	  MOV                     T21.X, T9.X,                                            ; 00000009 02A00C90
	  AND_INT                 T8.W, PV.W, literal.x,                                  ; 001FACFE 61001810
	  XOR_INT               * T9.W, T0.Z, T3.Y,                                       ; 80806800 61201910
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  MOV                     T16.X, T0.X,                                            ; 00000000 02000C90
	  XOR_INT                 T7.W, PS, T7.W,                                         ; 0180E0FF 60E01910
	  UINT_TO_FLT           * T2.Y, PV.W,                                             ; 80000CFE 20404E10
	  MOV                     T17.X, T0.X,                                            ; 00000000 02200C90
	  ADD_INT                 T0.Z, T0.X, literal.x,                                  ; 001FA000 40001A10
	  ADD                     T8.W, PS, 0.0,                                          ; 001F00FF 61000010
	  AND_INT               * T7.W, PV.W, literal.y,                                  ; 809FACFE 60E01810
	100(1.401298e-43), 16777215(2.350989e-38)                                         ; 00000064 00FFFFFF
	ALU clause starting at 0xba8:                                                     ; 
	  MUL_IEEE                T2.Z, T21.X, T18.X,                                     ; 00024015 40400110
	  MUL_IEEE              * T9.W, T21.X, T16.X,  BS:VEC_021/SCL_122                 ; 80020015 61240110
	  MUL_IEEE              * T10.W, T21.X, T17.X,                                    ; 80022015 61400110
	ALU clause starting at 0xbab:                                                     ; 
	  MULLO_INT             * T2.Y, T19.X, literal.x,                                 ; 801FA013 20404790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT                 T22.X, T2.W, PS,                                        ; 001FEC02 02C01A10
	  MULADD_IEEE             T3.Y, T20.X, T13.X, T10.W,                              ; 0001A014 20630C0A
	  MULADD_IEEE           * T3.Z, T20.X, T14.X, T9.W, BS:VEC_021/SCL_122            ; 8001C014 40670C09
	  MULADD_IEEE             T9.W, T20.X, T15.X, T2.Z,                               ; 0001E014 61230802
	  UINT_TO_FLT           * T2.Z, T7.W,                                             ; 80000C07 40404E10
	ALU clause starting at 0xbb2:                                                     ; 
	  MULADD_IEEE             T23.X, T9.X, T12.X, T9.W,                               ; 00018009 02E30C09
	  MULADD_IEEE           * T2.Y, T9.X, T10.X, T3.Z, BS:VEC_021/SCL_122             ; 80014009 20470803
	  MULADD_IEEE             T21.Z, T9.X, T11.X, T3.Y,                               ; 00016009 42A30403
	  MUL_IEEE                T7.W, T8.W, literal.x,                                  ; 001FAC08 60E00110
	  ADD                   * T8.W, T2.Z, 0.0,                                        ; 801F0802 61000010
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  MUL_IEEE              * T8.W, PS, literal.x,                                    ; 801FA0FF 61000110
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  MOV                     T9.X, T21.X,                                            ; 00000015 01200C90
	  MOV                     T9.Y, T21.Y,                                            ; 00000415 21200C90
	  MOV                     T9.Z, T21.Z,                                            ; 00000815 41200C90
	  MOV                     T9.W, T21.W,                                            ; 00000C15 61200C90
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T11.W, PS,                                              ; 000000FF 61600C90
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T13.W, literal.x, T22.X,                                ; 8002C0FD 61A01D90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xbc6:                                                     ; 
	  MOV                     T11.W, literal.x,                                       ; 000000FD 61600C90
	  SETE_INT              * T12.W, T22.X, literal.y,                                ; 809FA016 61801D10
	1(1.401298e-45), 2(2.802597e-45)                                                  ; 00000001 00000002
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xbca:                                                     ; 
	  MULLO_INT             * T2.Z, T19.X, literal.x,                                 ; 801FA013 40404790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T26.X, T2.W, PS,                                        ; 801FEC02 03401A10
	  MOV                   * T24.X, PV.X,                                            ; 800000FE 03000C90
	ALU clause starting at 0xbce:                                                     ; 
	  MULLO_INT             * T2.Z, T24.X, literal.x,                                 ; 801FA018 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T27.X, T8.X, PS,                                        ; 801FE008 03601A10
	ALU clause starting at 0xbd1:                                                     ; 
	  MOV                   * T11.W, literal.x,                                       ; 800000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T12.W, PV.W,                                            ; 00000CFE 61800C90
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T14.W, 1, T27.X,                                        ; 800360FA 61C01D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xbd8:                                                     ; 
	  MOV                     T12.W, literal.x,                                       ; 000000FD 61800C90
	  SETE_INT              * T13.W, T27.X, 1,                                        ; 801F401B 61A01D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xbdc:                                                     ; 
	  MULLO_INT             * T2.Z, T24.X, literal.x,                                 ; 801FA018 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T28.X, T8.X, PS,                                        ; 801FE008 03801A10
	  MOV                     T29.X, PV.X,                                            ; 000000FE 03A00C90
	  MOV                   * T20.X, PV.X,                                            ; 800000FE 02800C90
	ALU clause starting at 0xbe1:                                                     ; 
	  MOV                     T20.Y, T29.X,                                           ; 0000001D 22800C90
	  MOV                     T20.Z, T28.X,  BS:VEC_120/SCL_212                       ; 0000001C 42880C90
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xbe5:                                                     ; 
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xbe7:                                                     ; 
	  BFE_INT               * T13.W, T13.W, 0.0, 1,                                   ; 801F0C0D 61A0A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T11.W, literal.x, Pred_sel_zero                         ; 400000FD 61600C90
	  SETNE_INT             * T12.W, T27.X, 0.0, Pred_sel_zero                        ; C01F001B 61801E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T12.W, T12.W, 1,                                        ; 801F4C0C 61801810
	  SETE_INT              * T12.W, PV.W, 0.0,                                       ; 801F0CFE 61801D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xbef:                                                     ; 
	  MOV                   * T11.W, literal.x,                                       ; 800000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xbf1:                                                     ; 
	  SETNE_INT             * T11.W, T11.W, 1,                                        ; 801F4C0B 61601E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xbf3:                                                     ; 
	  MULLO_INT             * T2.Z, T24.X, literal.x,                                 ; 801FA018 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T20.X, T8.X, PS,                                        ; 801FE008 02801A10
	ALU clause starting at 0xbf6:                                                     ; 
	  MOV                   * T20.Y, T20.X,                                           ; 80000014 22800C90
	  MOV                   * T20.Z, T20.X,                                           ; 80000014 42800C90
	ALU clause starting at 0xbf8:                                                     ; 
	  MOV                   * T27.X, T26.X,                                           ; 8000001A 03600C90
	ALU clause starting at 0xbf9:                                                     ; 
	  MULLO_INT             * T2.Z, T27.X, literal.x,                                 ; 801FA01B 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T28.X, T8.X, PS,                                        ; 801FE008 03801A10
	ALU clause starting at 0xbfc:                                                     ; 
	  SETGT_DX10            * T11.W, T0.X, T20.W,                                     ; 81828000 61600690
	  CNDE_INT                T2.Z, PV.W, T20.W, T0.X,                                ; 01828CFE 40438000
	  SETGT_DX10              T11.W, T20.W, T0.X,                                     ; 00000C14 61600690
	  SETGT_DX10            * T12.W, 0.0, T20.Z,                                      ; 810280F8 61800690
	  SETGT_DX10              T3.Y, 0.0, T20.Y,                                       ; 008280F8 20600690
	  CNDE_INT                T3.Z, PS, T20.Z, 0.0,                                   ; 010280FF 406380F8
	  SETGT_DX10              T12.W, T20.Z, 1.0,                                      ; 001F2814 61800690
	  CNDE_INT              * T24.W, PV.W, PV.Z, T0.X,                                ; 811FCCFE 63038000
	  SETGT_DX10              T4.Y, 0.0, T20.X,                                       ; 000280F8 20800690
	  CNDE_INT                T24.Z, PV.W, PV.Z, literal.x,                           ; 011FCCFE 430380FD
	  CNDE_INT                T11.W, PV.Y, T20.Y, 0.0,                                ; 008284FE 616380F8
	  SETGT_DX10            * T12.W, T20.Y, 1.0,                                      ; 801F2414 61800690
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  CNDE_INT                T24.Y, PS, PV.W, literal.x,                             ; 019FC0FF 230380FD
	  CNDE_INT                T11.W, PV.Y, T20.X, 0.0,                                ; 000284FE 616380F8
	  SETGT_DX10            * T12.W, T20.X, 1.0,                                      ; 801F2014 61800690
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  CNDE_INT                T24.X, PS, PV.W, literal.x,                             ; 019FC0FF 030380FD
	  MOV                   * T11.W, literal.y,                                       ; 800004FD 61600C90
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  MOV                     T12.W, PV.W,                                            ; 00000CFE 61800C90
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T14.W, 1, T28.X,                                        ; 800380FA 61C01D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc15:                                                     ; 
	  MOV                     T12.W, literal.x,                                       ; 000000FD 61800C90
	  SETE_INT              * T13.W, T28.X, 1,                                        ; 801F401C 61A01D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xc19:                                                     ; 
	  MULLO_INT             * T2.Z, T27.X, literal.x,                                 ; 801FA01B 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T29.X, T8.X, PS,                                        ; 801FE008 03A01A10
	  MOV                     T30.X, PV.X,                                            ; 000000FE 03C00C90
	  MOV                   * T20.X, PV.X,                                            ; 800000FE 02800C90
	ALU clause starting at 0xc1e:                                                     ; 
	  MOV                     T20.Y, T30.X,                                           ; 0000001E 22800C90
	  MOV                     T20.Z, T29.X,  BS:VEC_120/SCL_212                       ; 0000001D 42880C90
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xc22:                                                     ; 
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xc24:                                                     ; 
	  BFE_INT               * T13.W, T13.W, 0.0, 1,                                   ; 801F0C0D 61A0A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T11.W, literal.x, Pred_sel_zero                         ; 400000FD 61600C90
	  SETNE_INT             * T12.W, T28.X, 0.0, Pred_sel_zero                        ; C01F001C 61801E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T12.W, T12.W, 1,                                        ; 801F4C0C 61801810
	  SETE_INT              * T12.W, PV.W, 0.0,                                       ; 801F0CFE 61801D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc2c:                                                     ; 
	  MOV                   * T11.W, literal.x,                                       ; 800000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xc2e:                                                     ; 
	  SETNE_INT             * T11.W, T11.W, 1,                                        ; 801F4C0B 61601E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc30:                                                     ; 
	  MULLO_INT             * T2.Z, T27.X, literal.x,                                 ; 801FA01B 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T20.X, T8.X, PS,                                        ; 801FE008 02801A10
	ALU clause starting at 0xc33:                                                     ; 
	  MOV                   * T20.Y, T20.X,                                           ; 80000014 22800C90
	  MOV                   * T20.Z, T20.X,                                           ; 80000014 42800C90
	ALU clause starting at 0xc35:                                                     ; 
	  MOV                     T28.X, 0.0,                                             ; 000000F8 03800C90
	  MOV                     T28.Y, 0.0,                                             ; 000000F8 23800C90
	  MOV                     T28.Z, 0.0,                                             ; 000000F8 43800C90
	  SETGT_DX10            * T11.W, T0.X, T20.W,                                     ; 81828000 61600690
	  CNDE_INT                T2.Z, PV.W, T20.W, T0.X,                                ; 01828CFE 40438000
	  SETGT_DX10              T11.W, T20.W, T0.X,                                     ; 00000C14 61600690
	  SETGT_DX10            * T12.W, 0.0, T20.Z,                                      ; 810280F8 61800690
	  SETGT_DX10              T3.Y, 0.0, T20.Y,                                       ; 008280F8 20600690
	  CNDE_INT                T3.Z, PS, T20.Z, 0.0,                                   ; 010280FF 406380F8
	  SETGT_DX10              T12.W, T20.Z, 1.0,                                      ; 001F2814 61800690
	  CNDE_INT              * T27.W, PV.W, PV.Z, T0.X,                                ; 811FCCFE 63638000
	  SETGT_DX10              T4.Y, 0.0, T20.X,                                       ; 000280F8 20800690
	  CNDE_INT                T27.Z, PV.W, PV.Z, literal.x,                           ; 011FCCFE 436380FD
	  CNDE_INT                T11.W, PV.Y, T20.Y, 0.0,                                ; 008284FE 616380F8
	  SETGT_DX10            * T12.W, T20.Y, 1.0,                                      ; 801F2414 61800690
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  CNDE_INT                T27.Y, PS, PV.W, literal.x,                             ; 019FC0FF 236380FD
	  CNDE_INT                T11.W, PV.Y, T20.X, 0.0,                                ; 000284FE 616380F8
	  SETGT_DX10            * T12.W, T20.X, 1.0,                                      ; 801F2014 61800690
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  CNDE_INT              * T27.X, PS, PV.W, literal.x,                             ; 819FC0FF 036380FD
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  SETE_DX10               T3.Y, PV.X, 0.0,                                        ; 001F00FE 20600610
	  SETE_DX10               T2.Z, T27.Y, 0.0,                                       ; 001F041B 40400610
	  SETE_DX10               T11.W, T24.X, 0.0,                                      ; 001F0018 61600610
	  SETE_DX10             * T12.W, T24.Y, 0.0,                                      ; 801F0418 61800610
	  AND_INT                 T4.Y, PV.W, PS,                                         ; 001FECFE 20801810
	  SETE_DX10               T3.Z, T24.Z, 0.0,                                       ; 001F0818 40600610
	  AND_INT                 T11.W, PV.Y, PV.Z,                                      ; 011FC4FE 61601810
	  SETE_DX10             * T12.W, T27.Z, 0.0,                                      ; 801F081B 61800610
	  AND_INT                 T16.W, PV.W, PS,                                        ; 001FECFE 62001810
	  AND_INT               * T15.W, PV.Y, PV.Z,                                      ; 811FC4FE 61E01810
	  AND_INT                 T12.W, PV.W, PS,                                        ; 001FECFE 61801810
	  MOV                   * T11.W, literal.x,                                       ; 800000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  SETGT_INT               T12.W, 0.0, PV.W,                                       ; 019FC0F8 61801D90
	  MOV                   * T13.W, PS,                                              ; 800000FF 61A00C90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc5b:                                                     ; 
	  MOV                   * T28.X, T26.X,                                           ; 8000001A 03800C90
	ALU clause starting at 0xc5c:                                                     ; 
	  MULLO_INT             * T2.Z, T28.X, literal.x,                                 ; 801FA01C 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T29.X, T8.X, PS,                                        ; 801FE008 03A01A10
	ALU clause starting at 0xc5f:                                                     ; 
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T13.W, PV.W,                                            ; 00000CFE 61A00C90
	  MOV                   * T14.W, literal.x,                                       ; 800000FD 61C00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T17.W, 1, T29.X,                                        ; 8003A0FA 62201D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc66:                                                     ; 
	  MOV                     T13.W, literal.x,                                       ; 000000FD 61A00C90
	  SETE_INT              * T14.W, T29.X, 1,                                        ; 801F401D 61C01D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xc6a:                                                     ; 
	  MULLO_INT             * T2.Z, T28.X, literal.x,                                 ; 801FA01C 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T20.X, T8.X, PS,                                        ; 801FE008 02801A10
	  MOV                     T30.X, PV.X,                                            ; 000000FE 03C00C90
	  MOV                   * T31.X, PV.X,                                            ; 800000FE 03E00C90
	ALU clause starting at 0xc6f:                                                     ; 
	  MUL_IEEE              * T13.W, T30.X, literal.x,                                ; 801FA01E 61A00110
	1060574394(7.151600e-01), 0(0.000000e+00)                                         ; 3F3714BA 00000000
	  MULADD_IEEE           * T13.W, T31.X, literal.x, PV.W,                          ; 801FA01F 61A30CFE
	1046070893(2.126710e-01), 0(0.000000e+00)                                         ; 3E59C66D 00000000
	  MULADD_IEEE             T20.X, T20.X, literal.x, PV.W,                          ; 001FA014 02830CFE
	  MOV                   * T13.W, literal.y,                                       ; 800004FD 61A00C90
	1033096535(7.216900e-02), 0(0.000000e+00)                                         ; 3D93CD57 00000000
	ALU clause starting at 0xc76:                                                     ; 
	  MOV                   * T14.W, literal.x,                                       ; 800000FD 61C00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xc78:                                                     ; 
	  BFE_INT               * T14.W, T14.W, 0.0, 1,                                   ; 801F0C0E 61C0A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T12.W, literal.x, Pred_sel_zero                         ; 400000FD 61800C90
	  SETNE_INT             * T13.W, T29.X, 0.0, Pred_sel_zero                        ; C01F001D 61A01E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T13.W, T13.W, 1,                                        ; 801F4C0D 61A01810
	  SETE_INT              * T13.W, PV.W, 0.0,                                       ; 801F0CFE 61A01D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc80:                                                     ; 
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xc82:                                                     ; 
	  SETNE_INT             * T12.W, T12.W, 1,                                        ; 801F4C0C 61801E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc84:                                                     ; 
	  MULLO_INT             * T2.Z, T28.X, literal.x,                                 ; 801FA01C 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T20.X, T8.X, PS,                                        ; 801FE008 02801A10
	ALU clause starting at 0xc87:                                                     ; 
	  MULLO_INT             * T2.Z, T26.X, literal.x,                                 ; 801FA01A 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T29.X, T8.X, PS,                                        ; 801FE008 03A01A10
	ALU clause starting at 0xc8a:                                                     ; 
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T13.W, PV.W,                                            ; 00000CFE 61A00C90
	  MOV                   * T14.W, literal.x,                                       ; 800000FD 61C00C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T17.W, 1, T29.X,                                        ; 8003A0FA 62201D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xc91:                                                     ; 
	  MOV                     T13.W, literal.x,                                       ; 000000FD 61A00C90
	  SETE_INT              * T14.W, T29.X, 1,                                        ; 801F401D 61C01D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xc95:                                                     ; 
	  MULLO_INT             * T2.Z, T26.X, literal.x,                                 ; 801FA01A 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T28.X, T8.X, PS,                                        ; 801FE008 03801A10
	  MOV                     T30.X, PV.X,                                            ; 000000FE 03C00C90
	  MOV                   * T31.X, PV.X,                                            ; 800000FE 03E00C90
	ALU clause starting at 0xc9a:                                                     ; 
	  MUL_IEEE              * T13.W, T30.X, literal.x,                                ; 801FA01E 61A00110
	1060574394(7.151600e-01), 0(0.000000e+00)                                         ; 3F3714BA 00000000
	  MULADD_IEEE           * T13.W, T31.X, literal.x, PV.W,                          ; 801FA01F 61A30CFE
	1046070893(2.126710e-01), 0(0.000000e+00)                                         ; 3E59C66D 00000000
	  MULADD_IEEE             T28.X, T28.X, literal.x, PV.W,                          ; 001FA01C 03830CFE
	  MOV                   * T13.W, literal.y,                                       ; 800004FD 61A00C90
	1033096535(7.216900e-02), 0(0.000000e+00)                                         ; 3D93CD57 00000000
	ALU clause starting at 0xca1:                                                     ; 
	  MOV                   * T14.W, literal.x,                                       ; 800000FD 61C00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xca3:                                                     ; 
	  BFE_INT               * T14.W, T14.W, 0.0, 1,                                   ; 801F0C0E 61C0A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T12.W, literal.x, Pred_sel_zero                         ; 400000FD 61800C90
	  SETNE_INT             * T13.W, T29.X, 0.0, Pred_sel_zero                        ; C01F001D 61A01E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T13.W, T13.W, 1,                                        ; 801F4C0D 61A01810
	  SETE_INT              * T13.W, PV.W, 0.0,                                       ; 801F0CFE 61A01D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xcab:                                                     ; 
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xcad:                                                     ; 
	  SETNE_INT             * T12.W, T12.W, 1,                                        ; 801F4C0C 61801E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xcaf:                                                     ; 
	  MULLO_INT             * T2.Z, T26.X, literal.x,                                 ; 801FA01A 40404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T28.X, T8.X, PS,                                        ; 801FE008 03801A10
	ALU clause starting at 0xcb2:                                                     ; 
	  RECIP_IEEE            * T2.Z, T20.X,                                            ; 80000014 40404310
	  SETGE_DX10              T3.Z, 0.0, T21.Z,                                       ; 0102A0F8 40600710
	  SETNE_DX10              T12.W, T21.Z, T21.Z,                                    ; 0102A815 61800790
	  MUL_IEEE              * T14.W, T28.X, PS,                                       ; 801FE01C 61C00110
	  MOV                     T17.W, PS,                                              ; 000000FF 62200C90
	  OR_INT                * T13.W, PV.Z, PV.W,                                      ; 819FC8FE 61A01890
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  RECIP_IEEE            * T2.Z, T28.X, Pred_sel_zero                              ; C000001C 40404310
	  MUL_IEEE              * T17.W, T20.X, T2.Z, Pred_sel_zero                       ; C1004014 62200110
	  MOV                     T12.W, literal.x,                                       ; 000000FD 61800C90
	  SETGT_INT             * T16.W, 0.0, T16.W,                                      ; 818200F8 62001D90
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  CNDGE_INT             * T12.W, T15.W, literal.x, 0.0, Pred_sel_zero             ; C01FAC0F 6183C0F8
	1056964608(5.000000e-01), 0(0.000000e+00)                                         ; 3F000000 00000000
	  SETNE_DX10              T15.W, T12.W, T12.W,                                    ; 01818C0C 61E00790
	  SETNE_DX10            * T16.W, T25.X, T25.X,                                    ; 80032019 62000790
	  OR_INT                  T15.W, PV.W, PS,                                        ; 001FECFE 61E01890
	  SETGE_DX10            * T18.W, T25.X, T12.W,                                    ; 81818019 62400710
	  MOV                     T2.Z, literal.x,                                        ; 000000FD 40400C90
	  MOV                     T16.W, literal.y,                                       ; 000004FD 62000C90
	  OR_INT                * T15.W, PS, PV.W,                                        ; 819FC0FF 61E01890
	0(0.000000e+00), 1(1.401298e-45)                                                  ; 00000000 00000001
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xcca:                                                     ; 
	  MOV                     T9.X, -T2.Y,                                            ; 00001402 01200C90
	  MOV                     T9.Y, -T23.X,                                           ; 00001017 21200C90
	  MUL_IEEE                T15.W, T14.W, T14.W,                                    ; 0181CC0E 61E00110
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), T13.W, 0.0,                 ; 801F0C0D 00002288
	  RECIP_IEEE            * T15.W, PV.W, Pred_sel_zero                              ; C0000CFE 61E04310
	  MOV                     T26.X, 1.0,                                             ; 000000F9 03400C90
	  MOV                     T26.Y, 1.0,                                             ; 000000F9 23400C90
	  MOV                     T26.Z, 1.0,                                             ; 000000F9 43400C90
	  MUL_IEEE              * T13.W, T21.Z, T21.Z,                                    ; 8102A815 61A00110
	  ADD                   * T13.W, -PV.W, 1.0,                                      ; 801F3CFE 61A00010
	  MAX                   * T13.W, PV.W, 0.0,                                       ; 801F0CFE 61A00190
	  MUL_IEEE              * T13.W, T15.W, PV.W,                                     ; 819FCC0F 61A00110
	  MOV                     T4.Z, |T21.Z|,                                          ; 00000815 40800C91
	  SETGE_DX10            * T15.W, PV.W, 1.0,                                       ; 801F2CFE 61E00710
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xcd9:                                                     ; 
	  ADD                   * T13.W, -T13.W, 1.0,                                     ; 801F3C0D 61A00010
	  MAX                   * T13.W, PV.W, 0.0,                                       ; 801F0CFE 61A00190
	  RECIPSQRT_CLAMPED     * T2.Z, PV.W,                                             ; 80000CFE 40404390
	  MUL NON-IEEE            T20.X, T13.W, PS,                                       ; 001FEC0D 02800090
	  MOV                     T2.Z, T14.W,  BS:VEC_120/SCL_212                        ; 00000C0E 40480C90
	  SETGT_DX10            * T13.W, T21.Z, 0.0,                                      ; 801F0815 61A00690
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  RECIP_IEEE            * T2.Z, T14.W, Pred_sel_zero                              ; C0000C0E 40404310
	  MULADD_IEEE             T13.W, T20.X, T2.Z, T4.Z,                               ; 01004014 61A30804
	  MUL_IEEE              * T15.W, T20.X, T2.Z,                                     ; 81004014 61E00110
	  MULADD_IEEE             T3.Y, T4.Z, T2.Z, T20.X,                                ; 01004804 20630014
	  ADD                     T3.Z, T4.Z, -PS,                                        ; 021FE804 40600010
	  MUL_IEEE                T15.W, T4.Z, T2.Z,                                      ; 01004804 61E00110
	  RECIP_IEEE            * T2.Z, PV.W,                                             ; 80000CFE 40404310
	  ADD                     T5.Z, T20.X, -PV.W,                                     ; 039FC014 40A00010
	  MUL_IEEE                T13.W, PV.Z, PS,                                        ; 001FE8FE 61A00110
	  RECIP_IEEE            * T2.Z, PV.Y,                                             ; 800004FE 40404310
	  MUL_IEEE                T13.W, PV.W, PV.W,                                      ; 019FCCFE 61A00110
	  MUL_IEEE              * T15.W, PV.Z, PS,                                        ; 801FE8FE 61E00110
	  MULADD_IEEE           * T13.W, PS, PS, PV.W,                                    ; 801FE0FF 61A30CFE
	  MUL_IEEE                T26.X, PV.W, 0.5,                                       ; 001F8CFE 03400110
	  MULADD_IEEE           * T13.W, T0.X, T0.X, T0.X,                                ; 80000000 61A30000
	  MUL_IEEE              * T26.W, PV.W, T0.X,                                      ; 80000CFE 63400110
	  MOV                   * T26.Y, T26.X,                                           ; 8000001A 23400C90
	  MOV                   * T26.Z, T26.X,                                           ; 8000001A 43400C90
	ALU clause starting at 0xcf2:                                                     ; 
	  ADD                     T20.X, -T12.W, 1.0,                                     ; 001F3C0C 02800010
	  MUL_IEEE              * T25.W, T27.W, T26.W,  BS:VEC_120/SCL_212                ; 81834C1B 63280110
	  MUL_IEEE              * T25.Z, T27.Z, T26.Z,                                    ; 8103481B 43200110
	  MUL_IEEE              * T25.Y, T27.Y, T26.Y,                                    ; 8083441B 23200110
	  MUL_IEEE                T25.X, T27.X, T26.X,                                    ; 0003401B 03200110
	  MOV                     T2.Z, literal.x,                                        ; 000000FD 40400C90
	  MOV                     T15.W, literal.y,                                       ; 000004FD 61E00C90
	  MOV                   * T16.W, literal.z,                                       ; 800008FD 62000C90
	1(1.401298e-45), 3(4.203895e-45)                                                  ; 00000001 00000003
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xcfc:                                                     ; 
	  BFE_INT               * T13.W, T16.W, 0.0, 1,                                   ; 801F0C10 61A0A0FA
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xcfe:                                                     ; 
	  MUL_IEEE              * T13.W, T21.Z, T21.Z,                                    ; 8102A815 61A00110
	  ADD                   * T13.W, -PV.W, 1.0,                                      ; 801F3CFE 61A00010
	  MAX                     T16.W, PV.W, 0.0,                                       ; 001F0CFE 62000190
	  MUL_IEEE              * T13.W, T17.W, T17.W,                                    ; 81822C11 61A00110
	  MUL_IEEE              * T16.W, PS, PV.W,                                        ; 819FC0FF 62000110
	  SETGT_DX10              T18.W, 1.0, PV.W,                                       ; 019FC0F9 62400690
	  SETNE_DX10            * T19.W, PV.W, PV.W,                                      ; 819FCCFE 62600790
	  OR_INT                * T18.W, PV.W, PS,                                        ; 801FECFE 62401890
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xd07:                                                     ; 
	  ADD                   * T9.W, -T16.W, 1.0,                                      ; 801F3C10 61200010
	  MAX                   * T9.W, PV.W, 0.0,                                        ; 801F0CFE 61200190
	  RECIPSQRT_CLAMPED     * T2.Z, PV.W,                                             ; 80000CFE 40404390
	  CNDGT                   T15.W, T21.Z, literal.x, 1.0,                           ; 001FA815 61E340F9
	  MUL NON-IEEE          * T9.W, T9.W, PS,                                         ; 801FEC09 61200090
	-1082130432(-1.000000e+00), 0(0.000000e+00)                                       ; BF800000 00000000
	  MUL_IEEE              * T9.Z, PV.W, PS,                                         ; 801FECFE 41200110
	  MUL_IEEE                T9.X, T2.Y, -T17.W,                                     ; 03822402 01200110
	  MUL_IEEE              * T9.Y, T23.X, -T17.W,                                    ; 83822017 21200110
	  SETGE_DX10              T16.W, 0.0, T9.Z,                                       ; 010120F8 62000710
	  SETNE_DX10            * T17.W, T9.Z, T9.Z,                                      ; 81012809 62200790
	  MUL_IEEE                T15.W, T14.W, T14.W,                                    ; 0181CC0E 61E00110
	  OR_INT                * T16.W, PV.W, PS,                                        ; 801FECFE 62001890
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  RECIP_IEEE            * T15.W, T15.W, Pred_sel_zero                             ; C0000C0F 61E04310
	  MOV                     T20.X, 1.0,                                             ; 000000F9 02800C90
	  MOV                     T20.Y, 1.0,                                             ; 000000F9 22800C90
	  MOV                     T20.Z, 1.0,                                             ; 000000F9 42800C90
	  MUL_IEEE              * T16.W, T9.Z, T9.Z,                                      ; 81012809 62000110
	  ADD                   * T16.W, -PV.W, 1.0,                                      ; 801F3CFE 62000010
	  MAX                   * T16.W, PV.W, 0.0,                                       ; 801F0CFE 62000190
	  MUL_IEEE              * T15.W, T15.W, PV.W,                                     ; 819FCC0F 61E00110
	  MOV                     T4.Z, |T9.Z|,                                           ; 00000809 40800C91
	  SETGE_DX10            * T16.W, PV.W, 1.0,                                       ; 801F2CFE 62000710
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xd20:                                                     ; 
	  ADD                   * T15.W, -T15.W, 1.0,                                     ; 801F3C0F 61E00010
	  MAX                   * T15.W, PV.W, 0.0,                                       ; 801F0CFE 61E00190
	  RECIPSQRT_CLAMPED     * T2.Y, PV.W,                                             ; 80000CFE 20404390
	  MUL NON-IEEE            T20.X, T15.W, PS,                                       ; 001FEC0F 02800090
	  SETGT_DX10            * T15.W, T9.Z, 0.0,                                       ; 801F0809 61E00690
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  RECIP_IEEE            * T14.W, T14.W, Pred_sel_zero                             ; C0000C0E 61C04310
	  MULADD_IEEE             T15.W, T20.X, T14.W, T4.Z,                              ; 0181C014 61E30804
	  MUL_IEEE              * T16.W, T20.X, T14.W,                                    ; 8181C014 62000110
	  MULADD_IEEE             T2.Y, T4.Z, T14.W, T20.X,                               ; 0181C804 20430014
	  ADD                     T2.Z, T4.Z, -PS,                                        ; 021FE804 40400010
	  MUL_IEEE                T14.W, T4.Z, T14.W,                                     ; 0181C804 61C00110
	  RECIP_IEEE            * T3.Y, PV.W,                                             ; 80000CFE 20604310
	  ADD                     T3.Z, T20.X, -PV.W,                                     ; 039FC014 40600010
	  MUL_IEEE                T14.W, PV.Z, PS,                                        ; 001FE8FE 61C00110
	  RECIP_IEEE            * T2.Y, PV.Y,                                             ; 800004FE 20404310
	  MUL_IEEE                T14.W, PV.W, PV.W,                                      ; 019FCCFE 61C00110
	  MUL_IEEE              * T15.W, PV.Z, PS,                                        ; 801FE8FE 61E00110
	  MULADD_IEEE           * T14.W, PS, PS, PV.W,                                    ; 801FE0FF 61C30CFE
	  MUL_IEEE                T20.X, PV.W, 0.5,                                       ; 001F8CFE 02800110
	  MULADD_IEEE           * T14.W, T0.X, T0.X, T0.X,                                ; 80000000 61C30000
	  MUL_IEEE              * T20.W, PV.W, T0.X,                                      ; 80000CFE 62800110
	  MOV                   * T20.Y, T20.X,                                           ; 80000014 22800C90
	  MOV                   * T20.Z, T20.X,                                           ; 80000014 42800C90
	ALU clause starting at 0xd38:                                                     ; 
	  MUL_IEEE                T14.W, T0.X, T0.X,                                      ; 00000000 61C00110
	  ADD                   * T15.W, -T20.Z, 1.0,                                     ; 801F3814 61E00010
	  ADD                     T2.Z, -T20.Y, 1.0,                                      ; 001F3414 40400010
	  MUL_IEEE                T15.W, T13.W, PS,                                       ; 001FEC0D 61E00110
	  MUL_IEEE              * T25.W, T24.W, PV.W,                                     ; 819FCC18 63200110
	  MUL_IEEE                T25.Z, T24.Z, PV.W,                                     ; 019FC818 43200110
	  ADD                     T14.W, -T20.X, 1.0,                                     ; 001F3014 61C00010
	  MUL_IEEE              * T15.W, T13.W, PV.Z,                                     ; 811FCC0D 61E00110
	  MOV                     T20.X, T12.W,                                           ; 00000C0C 02800C90
	  MUL_IEEE                T25.Y, T24.Y, PS,                                       ; 001FE418 23200110
	  MUL_IEEE              * T12.W, T13.W, PV.W,  BS:VEC_120/SCL_212                 ; 819FCC0D 61880110
	  MUL_IEEE                T25.X, T24.X, PV.W,                                     ; 019FC018 03200110
	  MOV                     T2.Z, literal.x,                                        ; 000000FD 40400C90
	  MOV                   * T15.W, literal.y,                                       ; 800004FD 61E00C90
	1(1.401298e-45), 5(7.006492e-45)                                                  ; 00000001 00000005
	ALU clause starting at 0xd47:                                                     ; 
	  MOV                     T28.X, 0.0,                                             ; 000000F8 03800C90
	  MOV                     T28.Y, 0.0,                                             ; 000000F8 23800C90
	  MOV                     T28.Z, 0.0,                                             ; 000000F8 43800C90
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xd4c:                                                     ; 
	  BFE_INT               * T12.W, T2.Z, 0.0, 1,                                    ; 801F0802 6180A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  RECIP_IEEE            * T2.Y, T4.Z, Pred_sel_zero                               ; C0000804 20404310
	  MUL_IEEE              * T28.Z, T25.Z, T2.Y, Pred_sel_zero                       ; C0804819 43800110
	  MUL_IEEE              * T28.Y, T25.Y, T2.Y, Pred_sel_zero                       ; C0804419 23800110
	  MUL_IEEE                T28.X, T25.X, T2.Y, Pred_sel_zero                       ; 40804019 03800110
	  MOV                   * T13.W, T15.W, Pred_sel_zero                             ; C0000C0F 61A00C90
	ALU clause starting at 0xd53:                                                     ; 
	  MOV                   * T12.W, literal.x,                                       ; 800000FD 61800C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xd55:                                                     ; 
	  BFE_INT               * T12.W, T12.W, 0.0, 1,                                   ; 801F0C0C 6180A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T10.W, literal.x, Pred_sel_zero                         ; 400000FD 61400C90
	  SETNE_INT             * T11.W, T22.X, 0.0, Pred_sel_zero                        ; C01F0016 61601E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T11.W, T11.W, 1,                                        ; 801F4C0B 61601810
	  SETE_INT              * T11.W, PV.W, 0.0,                                       ; 801F0CFE 61601D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xd5d:                                                     ; 
	  MOV                     T28.X, 0.0,                                             ; 000000F8 03800C90
	  MOV                     T28.Y, 0.0,                                             ; 000000F8 23800C90
	  MOV                     T28.Z, 0.0,                                             ; 000000F8 43800C90
	  MOV                   * T13.W, literal.x,                                       ; 800000FD 61A00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                   * T10.W, PV.W,                                            ; 80000CFE 61400C90
	ALU clause starting at 0xd63:                                                     ; 
	  SETNE_INT             * T10.W, T10.W, 1,                                        ; 801F4C0A 61401E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xd65:                                                     ; 
	  MOV                     T28.X, 0.0,                                             ; 000000F8 03800C90
	  MOV                     T28.Y, 0.0,                                             ; 000000F8 23800C90
	  MOV                     T28.Z, 0.0,                                             ; 000000F8 43800C90
	  MOV                     T13.W, literal.x,                                       ; 000000FD 61A00C90
	  SETGT_DX10            * T9.W, literal.y, |T21.Z|,                               ; 8102A4FD 61200692
	0(0.000000e+00), 953267991(1.000000e-04)                                          ; 00000000 38D1B717
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0xd6c:                                                     ; 
	  ADD                     T9.W, T8.W, T8.W,                                       ; 01810C08 61200010
	  ADD                   * T7.W, T7.W, T7.W,                                       ; 8180EC07 60E00010
	  ADD                     T8.W, PS, literal.x,                                    ; 001FA0FF 61000010
	  ADD                   * T7.W, PV.W, literal.x,                                  ; 801FACFE 60E00010
	-1082130432(-1.000000e+00), 0(0.000000e+00)                                       ; BF800000 00000000
	  SETNE_DX10              T2.Z, PS, 0.0,                                          ; 001F00FF 40400790
	  SETNE_DX10              T9.W, PV.W, 0.0,                                        ; 001F0CFE 61200790
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	-1082130432(-1.000000e+00), 0(0.000000e+00)                                       ; BF800000 00000000
	  CNDGE_INT               T20.X, T21.Z, literal.x, PS,                            ; 001FA815 0283C0FF
	  OR_INT                * T9.W, PV.Z, PV.W,                                       ; 819FC8FE 61201890
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  MOV                     T20.Y, PV.X,                                            ; 000000FE 22800C90
	  AND_INT                 T9.W, PV.W, 1,                                          ; 001F4CFE 61201810
	  MOV                   * T10.W, literal.x,                                       ; 800000FD 61400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T20.Z, T20.X,                                           ; 00000014 42800C90
	  MOV                     T11.W, PS,                                              ; 000000FF 61600C90
	  SETE_INT              * T9.W, PV.W, 0.0,                                        ; 801F0CFE 61201D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0xd80:                                                     ; 
	  SETNE_DX10              T10.W, T7.W, T7.W,                                      ; 0180EC07 61400790
	  SETNE_DX10            * T9.W, -T8.W, -T8.W,                                     ; 83811C08 61200790
	  OR_INT                  T9.W, PV.W, PS,                                         ; 001FECFE 61201890
	  SETGT_DX10            * T12.W, -T8.W, T7.W,                                     ; 8180FC08 61800690
	  MOV                     T11.W, literal.x,                                       ; 000000FD 61600C90
	  OR_INT                * T9.W, PS, PV.W,                                         ; 819FC0FF 61201890
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002104
	ALU clause starting at 0xd88:                                                     ; 
	  SETNE_DX10            * T9.W, T8.W, T8.W,                                       ; 81810C08 61200790
	  OR_INT                  T9.W, T10.W, PV.W,                                      ; 019FCC0A 61201890
	  SETGE_DX10            * T12.W, T8.W, T7.W,                                      ; 8180EC08 61800710
	  MOV                     T11.W, literal.x,                                       ; 000000FD 61600C90
	  OR_INT                * T9.W, PS, PV.W,                                         ; 819FC0FF 61201890
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  RECIP_IEEE            * T2.Y, T8.W, Pred_sel_one                                ; E0000C08 20404310
	  MUL_IEEE                T9.W, T7.W, T2.Y, Pred_sel_one                          ; 60804C07 61200110
	  MOV                   * T11.W, literal.x, Pred_sel_one                          ; E00000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  ADD                   * T9.W, -T9.W, literal.x, Pred_sel_one                    ; E01FBC09 61200010
	1073741824(2.000000e+00), 0(0.000000e+00)                                         ; 40000000 00000000
	ALU clause starting at 0xd95:                                                     ; 
	  MOV                     T2.Z, T8.W,                                             ; 00000C08 40400C90
	  SETNE_INT             * T11.W, T11.W, 1,  BS:VEC_120/SCL_212                    ; 801F4C0B 61681E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xd98:                                                     ; 
	  RECIP_IEEE            * T2.Y, T7.W,                                             ; 80000C07 20404310
	  MUL_IEEE                T9.W, T8.W, PS,                                         ; 001FEC08 61200110
	  SETGT_DX10            * T11.W, T8.W, 0.0,                                       ; 801F0C08 61600690
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  ADD                   * T9.W, T9.W, literal.x, Pred_sel_zero                    ; C01FAC09 61200010
	1090519040(8.000000e+00), 0(0.000000e+00)                                         ; 41000000 00000000
	  MOV                   * T2.Z, T7.W,                                             ; 80000C07 40400C90
	ALU clause starting at 0xd9f:                                                     ; 
	  MOV                   * T11.W, literal.x,                                       ; 800000FD 61600C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xda1:                                                     ; 
	  SETNE_INT             * T11.W, T11.W, 1,                                        ; 801F4C0B 61601E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xda3:                                                     ; 
	  SETNE_DX10            * T9.W, T8.W, T8.W,                                       ; 81810C08 61200790
	  OR_INT                  T9.W, T10.W, PV.W,                                      ; 019FCC0A 61201890
	  SETGT_DX10            * T11.W, T7.W, T8.W,                                      ; 81810C07 61600690
	  MOV                     T10.W, literal.x,                                       ; 000000FD 61400C90
	  OR_INT                * T9.W, PS, PV.W,                                         ; 819FC0FF 61201890
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  RECIP_IEEE            * T2.Y, T7.W, Pred_sel_zero                               ; C0000C07 20404310
	  MUL_IEEE              * T9.W, T8.W, T2.Y, Pred_sel_zero                         ; C0804C08 61200110
	  MOV                     T2.Z, -T7.W, Pred_sel_zero                              ; 40001C07 40400C90
	  MOV                     T10.W, literal.x, Pred_sel_zero                         ; 400000FD 61400C90
	  ADD                   * T9.W, T9.W, literal.y, Pred_sel_zero                    ; C09FAC09 61200010
	0(0.000000e+00), 1082130432(4.000000e+00)                                         ; 00000000 40800000
	ALU clause starting at 0xdb0:                                                     ; 
	  SETNE_INT             * T10.W, T10.W, 1,                                        ; 801F4C0A 61401E90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T2.Z, -T8.W, Pred_sel_zero                              ; C0001C08 40400C90
	  RECIP_IEEE            * T2.Y, T2.Z, Pred_sel_zero                               ; C0000802 20404310
	  MUL_IEEE              * T7.W, T7.W, T2.Y, Pred_sel_zero                         ; C0804C07 60E00110
	  ADD                   * T9.W, T7.W, literal.x, Pred_sel_zero                    ; C01FAC07 61200010
	1086324736(6.000000e+00), 0(0.000000e+00)                                         ; 40C00000 00000000
	ALU clause starting at 0xdb7:                                                     ; 
	  MUL_IEEE              * T7.W, T9.W, literal.x,                                  ; 801FAC09 60E00110
	1061752795(7.853982e-01), 0(0.000000e+00)                                         ; 3F490FDB 00000000
	  MULADD_IEEE           * T7.W, PV.W, literal.x, 0.5,                             ; 801FACFE 60E300FC
	1042479491(1.591549e-01), 0(0.000000e+00)                                         ; 3E22F983 00000000
	  FRACT                 * T7.W, PV.W,                                             ; 80000CFE 60E00810
	  ADD                   * T7.W, PV.W, literal.x,                                  ; 801FACFE 60E00010
	-1090519040(-5.000000e-01), 0(0.000000e+00)                                       ; BF000000 00000000
	  SIN                   * T2.Y, PV.W,                                             ; 80000CFE 20404690
	  COS                   * T3.Y, T7.W,                                             ; 80000C07 20604710
	  MUL_IEEE                T11.W, T2.Z, PS,                                        ; 001FE802 61600110
	  MUL_IEEE              * T10.W, T2.Z, T2.Y,                                      ; 80804802 61400110
	ALU clause starting at 0xdc2:                                                     ; 
	  MOV                     T28.X, 0.0,                                             ; 000000F8 03800C90
	  MOV                     T28.Y, 0.0,                                             ; 000000F8 23800C90
	  MOV                     T28.Z, 0.0,                                             ; 000000F8 43800C90
	  MUL_IEEE              * T7.W, T11.W, T11.W,                                     ; 81816C0B 60E00110
	  ADD                     T7.W, -PV.W, 1.0,                                       ; 001F3CFE 60E00010
	  MUL_IEEE              * T8.W, T10.W, T10.W,                                     ; 81814C0A 61000110
	  ADD                   * T7.W, PV.W, -PS,                                        ; 821FECFE 60E00010
	  MAX                   * T7.W, PV.W, 0.0,                                        ; 801F0CFE 60E00190
	  RECIPSQRT_CLAMPED     * T2.Y, PV.W,                                             ; 80000CFE 20404390
	  MUL NON-IEEE          * T7.W, T7.W, PS,                                         ; 801FEC07 60E00090
	  MUL_IEEE                T9.Z, T20.Z, PV.W,                                      ; 019FC814 41200110
	  MUL_IEEE              * T9.W, T20.W, T0.X,                                      ; 80000C14 61200110
	  MUL_IEEE              * T9.Y, T20.Y, T10.W,                                     ; 81814414 21200110
	  MUL_IEEE                T9.X, T20.X, T11.W,                                     ; 01816014 01200110
	  MUL_IEEE              * T20.X, T7.W, literal.x,                                 ; 801FAC07 02800110
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  MOV                     T4.Z, |T9.Z|,                                           ; 00000809 40800C91
	  SETGT_DX10              T7.W, literal.x, |T9.Z|,                                ; 010120FD 60E00692
	  MOV                   * T13.W, literal.y,                                       ; 800004FD 61A00C90
	953267991(1.000000e-04), 0(0.000000e+00)                                          ; 38D1B717 00000000
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xdd7:                                                     ; 
	  MULLO_INT             * T2.Y, T19.X, literal.x,                                 ; 801FA013 20404790
	48(6.726233e-44), 0(0.000000e+00)                                                 ; 00000030 00000000
	  ADD_INT               * T21.X, T2.W, PS,                                        ; 801FEC02 02A01A10
	ALU clause starting at 0xdda:                                                     ; 
	  MULLO_INT             * T2.Y, T21.X, literal.x,                                 ; 801FA015 20404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T22.X, T8.X, PS,                                        ; 801FE008 02C01A10
	ALU clause starting at 0xddd:                                                     ; 
	  MOV                   * T2.W, literal.x,                                        ; 800000FD 60400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MOV                     T7.W, PV.W,                                             ; 00000CFE 60E00C90
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETGT_INT             * T10.W, 1, T22.X,                                        ; 8002C0FA 61401D90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xde4:                                                     ; 
	  MOV                     T7.W, literal.x,                                        ; 000000FD 60E00C90
	  SETE_INT              * T8.W, T22.X, 1,                                         ; 801F4016 61001D10
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PS, 0.0,                ; 801F00FF 00002284
	ALU clause starting at 0xde8:                                                     ; 
	  MULLO_INT             * T2.Y, T21.X, literal.x,                                 ; 801FA015 20404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T23.X, T8.X, PS,                                        ; 801FE008 02E01A10
	  MOV                     T24.X, PV.X,                                            ; 000000FE 03000C90
	  MOV                   * T19.X, PV.X,                                            ; 800000FE 02600C90
	ALU clause starting at 0xded:                                                     ; 
	  MOV                     T19.Y, T24.X,                                           ; 00000018 22600C90
	  MOV                     T19.Z, T23.X,  BS:VEC_120/SCL_212                       ; 00000017 42680C90
	  MOV                   * T7.W, literal.x,                                        ; 800000FD 60E00C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xdf1:                                                     ; 
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xdf3:                                                     ; 
	  BFE_INT               * T8.W, T8.W, 0.0, 1,                                     ; 801F0C08 6100A0FA
	  PRED_SETE_INT         * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002108
	  MOV                     T2.W, literal.x, Pred_sel_zero                          ; 400000FD 60400C90
	  SETNE_INT             * T7.W, T22.X, 0.0, Pred_sel_zero                         ; C01F0016 60E01E90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  AND_INT               * T7.W, T7.W, 1,                                          ; 801F4C07 60E01810
	  SETE_INT              * T7.W, PV.W, 0.0,                                        ; 801F0CFE 60E01D10
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xdfb:                                                     ; 
	  MOV                   * T2.W, literal.x,                                        ; 800000FD 60400C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	ALU clause starting at 0xdfd:                                                     ; 
	  SETNE_INT             * T2.W, T2.W, 1,                                          ; 801F4C02 60401E90
	  PRED_SETE_INT         * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002104
	ALU clause starting at 0xdff:                                                     ; 
	  MULLO_INT             * T2.Y, T21.X, literal.x,                                 ; 801FA015 20404790
	268(3.755480e-43), 0(0.000000e+00)                                                ; 0000010C 00000000
	  ADD_INT               * T19.X, T8.X, PS,                                        ; 801FE008 02601A10
	ALU clause starting at 0xe02:                                                     ; 
	  MOV                   * T19.Y, T19.X,                                           ; 80000013 22600C90
	  MOV                   * T19.Z, T19.X,                                           ; 80000013 42600C90
	ALU clause starting at 0xe04:                                                     ; 
	  SETGT_DX10              T2.W, T0.X, T19.W,                                      ; 01826000 60400690
	  MUL_IEEE              * T7.W, T19.W, T0.X,                                      ; 80000C13 60E00110
	  CNDE_INT                T2.Y, PV.W, PS, T0.X,                                   ; 001FECFE 20438000
	  SETGT_DX10              T2.Z, T19.W, T0.X,                                      ; 00000C13 40400690
	  SETGT_DX10              T2.W, 0.0, T19.Z,                                       ; 010260F8 60400690
	  MUL_IEEE              * T7.W, T19.Z, literal.x,                                 ; 801FA813 60E00110
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  SETGT_DX10              T8.X, 0.0, T19.Y,                                       ; 008260F8 01000690
	  MUL_IEEE                T3.Y, T19.Y, literal.x,                                 ; 001FA413 20600110
	  CNDE_INT                T3.Z, PV.W, PS, 0.0,                                    ; 001FECFE 406380F8
	  SETGT_DX10              T2.W, T19.Z, 1.0,                                       ; 001F2813 60400690
	  CNDE_INT              * T28.W, PV.Z, PV.Y, T0.X,                                ; 809FC8FE 63838000
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  SETGT_DX10              T21.X, 0.0, T19.X,                                      ; 000260F8 02A00690
	  MUL_IEEE                T2.Y, T19.X, literal.x,                                 ; 001FA013 20400110
	  CNDE_INT                T28.Z, PV.W, PV.Z, literal.x,                           ; 011FCCFE 438380FD
	  CNDE_INT                T2.W, PV.X, PV.Y, 0.0,                                  ; 009FC0FE 604380F8
	  SETGT_DX10            * T7.W, T19.Y, 1.0,                                       ; 801F2413 60E00690
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  CNDE_INT                T28.Y, PS, PV.W, literal.x,                             ; 019FC0FF 238380FD
	  CNDE_INT                T2.W, PV.X, PV.Y, 0.0,                                  ; 009FC0FE 604380F8
	  SETGT_DX10            * T7.W, T19.X, 1.0,                                       ; 801F2013 60E00690
	1050868099(3.183099e-01), 0(0.000000e+00)                                         ; 3EA2F983 00000000
	  CNDE_INT                T28.X, PS, PV.W, literal.x,                             ; 019FC0FF 038380FD
	  MOV                   * T13.W, literal.y,                                       ; 800004FD 61A00C90
	1050868099(3.183099e-01), 2(2.802597e-45)                                         ; 3EA2F983 00000002
	ALU clause starting at 0xe1e:                                                     ; 
	  MOV                     T21.X, 0.0,                                             ; 000000F8 02A00C90
	  MOV                     T21.Y, 0.0,                                             ; 000000F8 22A00C90
	  MOV                     T21.Z, 0.0,                                             ; 000000F8 42A00C90
	  SETE_DX10               T2.W, T28.X, 0.0,                                       ; 001F001C 60400610
	  SETE_DX10             * T7.W, T28.Y, 0.0,                                       ; 801F041C 60E00610
	  AND_INT                 T2.W, PV.W, PS,                                         ; 001FECFE 60401810
	  SETE_DX10             * T7.W, T28.Z, 0.0,                                       ; 801F081C 60E00610
	  AND_INT               * T2.W, PV.W, PS,                                         ; 801FECFE 60401810
	  SETGT_INT             * T2.W, 0.0, PV.W,                                        ; 819FC0F8 60401D90
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MUL_IEEE                T2.W, T9.Y, T12.X, Pred_sel_zero BS:VEC_021/SCL_122     ; 40018409 60440110
	  MUL_IEEE              * T7.W, T9.Y, T18.X, Pred_sel_zero                        ; C0024409 60E00110
	  MULADD_IEEE           * T2.W, T10.X, T9.X, T2.W, Pred_sel_zero                  ; C001200A 60430C02
	  MULADD_IEEE             T19.Z, T11.X, T9.Z, T2.W, Pred_sel_zero                 ; 4101200B 42630C02
	  MUL_IEEE              * T2.W, T9.Y, T15.X, Pred_sel_zero                        ; C001E409 60400110
	  MULADD_IEEE           * T7.W, T16.X, T9.X, T7.W, Pred_sel_zero                  ; C0012010 60E30C07
	  MULADD_IEEE             T19.Y, T17.X, T9.Z, T7.W, Pred_sel_zero                 ; 41012011 22630C07
	  MUL_IEEE              * T7.W, T0.X, T0.X, Pred_sel_zero BS:VEC_120/SCL_212      ; C0000000 60E80110
	  MULADD_IEEE           * T2.W, T14.X, T9.X, T2.W, Pred_sel_zero                  ; C001200E 60430C02
	  MULADD_IEEE             T19.X, T13.X, T9.Z, T2.W, Pred_sel_zero                 ; 4101200D 02630C02
	  MULADD_IEEE           * T2.W, T0.X, T0.X, T7.W, Pred_sel_zeroBS:VEC_120/SCL_212 ; C0000000 604B0C07
	  MULADD_IEEE           * T19.W, T0.X, T0.X, T2.W, Pred_sel_zero                  ; C0000000 62630C02
	  MOV                     T21.X, T28.X, Pred_sel_zero                             ; 4000001C 02A00C90
	  MOV                     T21.Y, T28.Y, Pred_sel_zero                             ; 4000041C 22A00C90
	  MOV                     T21.Z, T28.Z, Pred_sel_zero                             ; 4000081C 42A00C90
	  MOV                   * T21.W, T28.W, Pred_sel_zero                             ; C0000C1C 62A00C90
	ALU clause starting at 0xe38:                                                     ; 
	  MAX                   * T2.W, T21.Y, T21.Z,                                     ; 8102A415 60400190
	  MAX                     T2.W, T21.X, PV.W,                                      ; 019FC015 60400190
	  MOV                   * T7.W, literal.x,                                        ; 800000FD 60E00C90
	1065353216(1.000000e+00), 0(0.000000e+00)                                         ; 3F800000 00000000
	  SETGT_DX10            * T8.W, PV.W, 1.0,                                        ; 801F2CFE 61000690
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MAX                   * T7.W, T2.W, 0.5, Pred_sel_zero                          ; C01F8C02 60E00190
	  AND_INT               * T10.X, T13.W, 1,                                        ; 801F4C0D 01401810
	  SETE_INT                T2.W, PV.X, 0.0,                                        ; 001F00FE 60401D10
	  SETGT_UINT            * T8.W, T1.X, literal.x,                                  ; 801FA001 61001F10
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  AND_INT               * T2.W, PS, PV.W,                                         ; 819FC0FF 60401810
	  MOV                     T11.X, literal.x,                                       ; 000000FD 01600C90
	  AND_INT               * T9.W, PV.W, 1,                                          ; 801F4CFE 61201810
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  MOV                     T2.W, PV.X,                                             ; 000000FE 60400C90
	  MOV                   * T8.W, literal.x,                                        ; 800000FD 61000C90
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  SETE_INT              * T9.W, T9.W, 0.0,                                        ; 801F0C09 61201D10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  LSHL                    T2.Z, T4.X, literal.x, Pred_sel_zero                    ; 401FA004 40400B90
	  LSHL                    T2.W, T7.X, literal.y, Pred_sel_zero BS:VEC_120/SCL_212 ; 409FA007 60480B90
	  LSHL                  * T8.W, T3.X, literal.z, Pred_sel_zero                    ; C11FA003 61000B90
	12(1.681558e-44), 10(1.401298e-44)                                                ; 0000000C 0000000A
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  LSHL                    T7.X, T6.W, literal.x, Pred_sel_zero                    ; 401FAC06 00E00B90
	  XOR_INT                 T2.Y, T8.W, T3.X, Pred_sel_zero BS:VEC_120/SCL_212      ; 40006C08 20481910
	  LSHL                  * T1.Z, T1.Z, literal.y, Pred_sel_zero                    ; C09FA801 40200B90
	17(2.382207e-44), 4(5.605194e-45)                                                 ; 00000011 00000004
	  XOR_INT                 T2.W, T5.W, T2.W, Pred_sel_zero                         ; 41804C05 60401910
	  LSHL                  * T5.W, T4.X, literal.x, Pred_sel_zero                    ; C01FA004 60A00B90
	13(1.821688e-44), 0(0.000000e+00)                                                 ; 0000000D 00000000
	  XOR_INT                 T4.X, T5.W, T1.Y, Pred_sel_zero                         ; 40802C05 00801910
	  LSHR                    T1.Y, T2.W, literal.x, Pred_sel_zero BS:VEC_120/SCL_212 ; 401FAC02 20280B10
	  AND_INT                 T1.Z, T1.Z, literal.y, Pred_sel_zero                    ; 409FA801 40201810
	  LSHR                    T2.W, T2.Y, literal.z, Pred_sel_zero                    ; 411FA402 60400B10
	  AND_INT               * T5.W, T7.X, literal.w, Pred_sel_zero                    ; C19FA007 60A01810
	25(3.503246e-44), -128(-nan)                                                      ; 00000019 FFFFFF80
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  OR_INT                  T3.X, T2.W, T5.W, Pred_sel_zero                         ; 4180AC02 00601890
	  OR_INT                  T1.Z, T1.Z, T1.Y, Pred_sel_zero                         ; 40802801 40201890
	  LSHR                    T2.W, T4.X, literal.x, Pred_sel_zero                    ; 401FA004 60400B10
	  AND_INT               * T5.W, T2.Z, literal.y, Pred_sel_zero                    ; C09FA802 60A01810
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  OR_INT                  T4.X, T2.W, T5.W, Pred_sel_zero                         ; 4180AC02 00801890
	  XOR_INT               * T2.W, T3.X, T1.Z, Pred_sel_zero                         ; C1002003 60401910
	  XOR_INT               * T2.W, T2.W, T4.X, Pred_sel_zero                         ; C0008C02 60401910
	  AND_INT               * T2.W, T2.W, literal.x, Pred_sel_zero                    ; C01FAC02 60401810
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T1.Y, T2.W, Pred_sel_zero                               ; C0000C02 20204E10
	  ADD                   * T2.W, T1.Y, 0.0, Pred_sel_zero                          ; C01F0401 60400010
	  MUL_IEEE              * T2.W, T2.W, literal.x, Pred_sel_zero                    ; C01FAC02 60400110
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  SETGT_DX10              T2.W, T7.W, T2.W, Pred_sel_zero                         ; 41804C07 60400690
	  MOV                   * T8.W, literal.x, Pred_sel_zero                          ; C00000FD 61000C90
	1(1.401298e-45), 0(0.000000e+00)                                                  ; 00000001 00000000
	  SETE_DX10               T5.W, T21.X, 0.0,                                       ; 001F0015 60A00610
	  SETE_DX10             * T6.W, T21.Y, 0.0,                                       ; 801F0415 60C00610
	  AND_INT                 T5.W, PV.W, PS,                                         ; 001FECFE 60A01810
	  SETE_DX10             * T6.W, T21.Z, 0.0,                                       ; 801F0815 60C00610
	  AND_INT               * T5.W, PV.W, PS,                                         ; 801FECFE 60A01810
	  SETGT_INT               T5.W, 0.0, PV.W,                                        ; 019FC0F8 60A01D90
	  XOR_INT               * T2.W, T2.W, 1,                                          ; 801F4C02 60401910
	  MOV                     T7.X, T1.Z,                                             ; 00000801 00E00C90
	  OR_INT                * T3.Z, PS, PV.W,                                         ; 819FC0FF 40601890
	ALU clause starting at 0xe79:                                                     ; 
	  MOV                     T2.Y, T3.X,                                             ; 00000003 20400C90
	  MOV                   * T1.Y, T7.X,                                             ; 80000007 20200C90
	  MOV                   * T2.Z, T4.X,                                             ; 80000004 40400C90
	ALU clause starting at 0xe7c:                                                     ; 
	  ADD_INT                 T5.Z, T0.X, literal.x,                                  ; 001FA000 40A01A10
	  BFE_INT                 T5.W, T3.Z, 0.0, 1,                                     ; 001F0803 60A0A0FA
	  ADD_INT               * T2.W, T0.X, literal.y,                                  ; 809FA000 60401A10
	28(3.923636e-44), 24(3.363116e-44)                                                ; 0000001C 00000018
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xe81:                                                     ; 
	  MOV                     T7.X, 0.0,                                              ; 000000F8 00E00C90
	  MOV                     T7.Y, 0.0,                                              ; 000000F8 20E00C90
	  LSHL                  * T5.W, T1.W, 1,                                          ; 801F4C01 60A00B90
	  OR_INT                * T5.W, PV.W, 1,                                          ; 801F4CFE 60A01890
	  LSHL                    T5.W, PV.W, literal.x,                                  ; 001FACFE 60A00B90
	  MOV                   * T6.W, KC0[2].W,                                         ; 80000C82 60C00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T8.X, PS, PV.W,                                         ; 819FC0FF 01001A10
	  MOV                     T9.X, PV.X,                                             ; 000000FE 01200C90
	  LSHL                  * T5.W, T1.W, literal.x,                                  ; 801FAC01 60A00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  ADD_INT               * T12.X, T6.W, PV.W,                                      ; 819FCC06 01801A10
	  MOV                     T11.X, PV.X,                                            ; 000000FE 01600C90
	  LSHL                  * T5.W, T2.Y, literal.x,                                  ; 801FA402 60A00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	ALU clause starting at 0xe90:                                                     ; 
	  LSHL                    T6.W, T1.Y, literal.x,                                  ; 001FA401 60C00B90
	  XOR_INT               * T5.W, T5.W, T2.Y,                                       ; 80804C05 60A01910
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  LSHR                    T13.X, PS, literal.x,                                   ; 001FA0FF 01A00B10
	  LSHL                    T3.Y, T1.Y, literal.y,                                  ; 009FA401 20600B90
	  XOR_INT                 T3.Z, PV.W, T1.Y,                                       ; 00802CFE 40601910
	  LSHL                    T6.W, T2.Z, literal.z,                                  ; 011FA802 60C00B90
	  LSHL                  * T9.W, T2.Y, literal.w,                                  ; 819FA402 61200B90
	11(1.541428e-44), 4(5.605194e-45)                                                 ; 0000000B 00000004
	13(1.821688e-44), 17(2.382207e-44)                                                ; 0000000D 00000011
	  AND_INT                 T14.X, PS, literal.x,                                   ; 001FA0FF 01C01810
	  LSHL                    T2.Y, T2.Z, literal.y,                                  ; 009FA802 20400B90
	  XOR_INT                 T2.Z, PV.W, T2.Z,                                       ; 01004CFE 40401910
	  LSHR                    T6.W, PV.Z, literal.z,                                  ; 011FA8FE 60C00B10
	  AND_INT               * T9.W, PV.Y, literal.w,                                  ; 819FA4FE 61201810
	-2097152(-nan), 12(1.681558e-44)                                                  ; FFE00000 0000000C
	25(3.503246e-44), -128(-nan)                                                      ; 00000019 FFFFFF80
	  OR_INT                  T4.Y, PV.W, PS,                                         ; 001FECFE 20801890
	  LSHR                    T2.Z, PV.Z, literal.x,                                  ; 001FA8FE 40400B10
	  AND_INT                 T6.W, PV.Y, literal.y,                                  ; 009FA4FE 60C01810
	  OR_INT                * T9.W, T13.X, PV.X,                                      ; 801FC00D 61201890
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  LSHL                    T5.Y, T1.Y, literal.x,                                  ; 001FA401 20A00B90
	  LSHL                    T3.Z, PS, literal.y,                                    ; 009FA0FF 40600B90
	  OR_INT                  T6.W, PV.Z, PV.W,                                       ; 019FC8FE 60C01890
	  LSHL                  * T10.W, PV.Y, literal.z,                                 ; 811FA4FE 61400B90
	6(8.407791e-45), 3(4.203895e-45)                                                  ; 00000006 00000003
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  AND_INT                 T13.X, PS, literal.x,                                   ; 001FA0FF 01A01810
	  LSHL                    T6.Y, PV.W, literal.y,                                  ; 009FACFE 20C00B90
	  LSHL                    T2.Z, T5.W, literal.z,                                  ; 011FAC05 40400B90
	  XOR_INT                 T5.W, PV.Z, T9.W,                                       ; 018128FE 60A01910
	  XOR_INT               * T11.W, PV.Y, T3.Y,                                      ; 808064FE 61601910
	-128(-nan), 13(1.821688e-44)                                                      ; FFFFFF80 0000000D
	6(8.407791e-45), 0(0.000000e+00)                                                  ; 00000006 00000000
	  LSHR                    T14.X, PS, literal.x,                                   ; 001FA0FF 01C00B10
	  LSHR                    T3.Y, PV.W, literal.y,                                  ; 009FACFE 20600B10
	  AND_INT                 T2.Z, PV.Z, literal.z,                                  ; 011FA8FE 40401810
	  LSHL                    T11.W, T6.W, literal.w,                                 ; 019FAC06 61600B90
	  XOR_INT               * T12.W, PV.Y, T2.Y,                                      ; 808044FE 61801910
	25(3.503246e-44), 11(1.541428e-44)                                                ; 00000019 0000000B
	-2097152(-nan), 12(1.681558e-44)                                                  ; FFE00000 0000000C
	  LSHR                    T2.Y, PS, literal.x,                                    ; 001FA0FF 20400B10
	  AND_INT                 T3.Z, PV.W, literal.y,                                  ; 009FACFE 40601810
	  OR_INT                  T12.W, PV.Y, PV.Z,                                      ; 011FC4FE 61801890
	  OR_INT                * T13.W, T13.X, PV.X,                                     ; 801FC00D 61A01890
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  XOR_INT                 T14.W, PV.W, PS,                                        ; 001FECFE 61C01910
	  OR_INT                * T15.W, PV.Y, PV.Z,                                      ; 811FC4FE 61E01890
	  MULADD_IEEE             T2.Z, T9.X, literal.x, 0.5,                             ; 001FA009 404300FC
	  XOR_INT                 T14.W, PV.W, PS,                                        ; 001FECFE 61C01910
	  ADD_INT               * T16.W, T6.X, literal.y,                                 ; 809FA006 62001A10
	1139802112(4.800000e+02), 8(1.121039e-44)                                         ; 43F00000 00000008
	  LSHR                    T9.X, PS, literal.x,                                    ; 001FA0FF 01200B10
	  AND_INT                 T3.Z, PV.W, literal.y,                                  ; 009FACFE 40601810
	  MULADD_IEEE             T14.W, T11.X, literal.z, 0.5,                           ; 011FA00B 61C300FC
	  FLOOR                 * T16.W, PV.Z,                                            ; 800008FE 62000A10
	2(2.802597e-45), 16777215(2.350989e-38)                                           ; 00000002 00FFFFFF
	1142947840(6.400000e+02), 0(0.000000e+00)                                         ; 44200000 00000000
	  MOV                     T11.X, literal.x,                                       ; 000000FD 01600C90
	  TRUNC                   T2.Z, PS,                                               ; 000000FF 40400890
	  FLOOR                   T14.W, PV.W,                                            ; 00000CFE 61C00A10
	  UINT_TO_FLT           * T2.Y, PV.Z,                                             ; 800008FE 20404E10
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  LSHR                    T13.X, T6.X, literal.x,                                 ; 001FA006 01A00B10
	  TRUNC                   T3.Z, PV.W,                                             ; 00000CFE 40600890
	  ADD                     T14.W, PS, 0.0,                                         ; 001F00FF 61C00010
	  FLT_TO_UINT           * T2.Y, PV.Z,                                             ; 800008FE 20404D10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00110
	  FLT_TO_UINT           * T2.Z, PV.Z,                                             ; 800008FE 40404D10
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  LSHR                    T15.X, T8.X, literal.x,                                 ; 001FA008 01E00B10
	  SETGT_UINT              T3.Y, PS, literal.y,                                    ; 009FA0FF 20601F10
	  ADD_INT                 T2.Z, PS, literal.z,                                    ; 011FA0FF 40401A10
	  SETGT_UINT            * T14.W, T2.Y, literal.w,                                 ; 819FA402 61C01F10
	2(2.802597e-45), 638(8.940284e-43)                                                ; 00000002 0000027E
	643(9.010349e-43), 478(6.698207e-43)                                              ; 00000283 000001DE
	  MULLO_INT             * T2.Y, T2.Y, literal.x,                                  ; 801FA402 20404790
	642(8.996336e-43), 0(0.000000e+00)                                                ; 00000282 00000000
	  MOV                     T16.X, T6.X,                                            ; 00000006 02000C90
	  CNDE_INT                T14.W, T14.W, PS, literal.x,                            ; 001FEC0E 61C380FD
	  CNDE_INT              * T16.W, T3.Y, T2.Z, literal.y,                           ; 81004403 620384FD
	307518(4.309245e-40), 1282(1.796465e-42)                                          ; 0004B13E 00000502
	  MOV                     T17.X, T6.X,                                            ; 00000006 02200C90
	  ADD_INT               * T14.W, PV.W, PS,                                        ; 801FECFE 61C01A10
	  LSHL                    T14.W, PV.W, literal.x,                                 ; 001FACFE 61C00B90
	  MOV                   * T16.W, KC0[3].Z,                                        ; 80000883 62000C90
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  ADD_INT               * T18.X, PS, PV.W,                                        ; 819FC0FF 02401A10
	  LSHR                    T22.X, PV.X, literal.x,                                 ; 001FA0FE 02C00B10
	  XOR_INT                 T9.W, T4.Y, T9.W,                                       ; 01812404 61201910
	  MOV                   * T23.X, PV.X,                                            ; 800000FE 02E00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  XOR_INT               * T6.W, PV.W, T6.W,                                       ; 8180CCFE 60C01910
	  MOV                     T24.X, T18.X,                                           ; 00000012 03000C90
	  AND_INT                 T6.W, PV.W, literal.x,                                  ; 001FACFE 60C01810
	  MOV                   * T25.X, T18.X,                                           ; 80000012 03200C90
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T2.Y, PV.W,                                             ; 80000CFE 20404E10
	ALU clause starting at 0xef4:                                                     ; 
	  ADD                     T16.Z, T16.X, T23.X,                                    ; 0002E010 42000010
	  ADD                   * T6.W, T2.Y, 0.0,                                        ; 801F0402 60C00010
	  MUL_IEEE                T23.X, PV.W, literal.x,                                 ; 001FACFE 02E00110
	  ADD                   * T16.Y, T17.X, T24.X,                                    ; 80030011 22000010
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  ADD                     T16.X, T6.X, T25.X,                                     ; 00032006 02000010
	  LSHR                  * T6.X, T12.X, literal.x,                                 ; 801FA00C 00C00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD                   * T16.W, T18.X, 1.0,                                      ; 801F2012 62000010
	ALU clause starting at 0xefd:                                                     ; 
	  MOV                     T6.W, KC0[2].Z,                                         ; 00000882 60C00C90
	  LSHL                  * T1.W, T1.W, literal.x,                                  ; 801FAC01 60200B90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T6.X, PV.W, PS,                                         ; 801FECFE 00C01A10
	  MOV                   * T7.X, PV.X,                                             ; 800000FE 00E00C90
	ALU clause starting at 0xf02:                                                     ; 
	  ADD_INT                 T7.X, T7.X, 1,                                          ; 001F4007 00E01A10
	  LSHR                  * T6.X, T6.X, literal.x,                                  ; 801FA006 00C00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0xf05:                                                     ; 
	  MOV                   * T7.X, KC0[6].X,                                         ; 80000086 00E00C90
	  MOV                     T6.X, PV.X,                                             ; 000000FE 00C00C90
	  MOV                   * T9.X, PV.X,                                             ; 800000FE 01200C90
	  MOV                     T13.X, T7.X,                                            ; 00000007 01A00C90
	  MOV                   * T14.X, T7.X,                                            ; 80000007 01C00C90
	  MOV                     T15.X, T7.X,                                            ; 00000007 01E00C90
	  MOV                   * T16.X, T7.X,                                            ; 80000007 02000C90
	  MOV                     T17.X, T7.X,                                            ; 00000007 02200C90
	  MOV                   * T18.X, T7.X,                                            ; 80000007 02400C90
	  MOV                     T22.X, T7.X,                                            ; 00000007 02C00C90
	  MOV                   * T23.X, T7.X,                                            ; 80000007 02E00C90
	  MOV                     T24.X, T7.X,                                            ; 00000007 03000C90
	  MOV                   * T25.X, T7.X,                                            ; 80000007 03200C90
	  MOV                     T26.X, T7.X,                                            ; 00000007 03400C90
	  MOV                   * T27.X, T7.X,                                            ; 80000007 03600C90
	  MOV                     T28.X, T7.X,                                            ; 00000007 03800C90
	  MOV                   * T29.X, T7.X,                                            ; 80000007 03A00C90
	ALU clause starting at 0xf16:                                                     ; 
	  ADD                   * T1.W, -T8.X, 1.0,                                       ; 801F3008 60200010
	  MOV                     T8.X, T7.X,                                             ; 00000007 01000C90
	  MUL_IEEE                T1.W, PV.W, literal.x,                                  ; 001FACFE 60200110
	  MOV                   * T30.X, T7.X,                                            ; 80000007 03C00C90
	1139802112(4.800000e+02), 0(0.000000e+00)                                         ; 43F00000 00000000
	  MUL_IEEE                T6.W, T12.X, literal.x,                                 ; 001FA00C 60C00110
	  MIN                   * T1.W, PV.W, literal.y,                                  ; 809FACFE 60200210
	1142947840(6.400000e+02), 1139769344(4.790000e+02)                                ; 44200000 43EF8000
	  MOV                     T12.X, T7.X,                                            ; 00000007 01800C90
	  MUL_IEEE                T2.Z, T25.X, PS,  BS:VEC_120/SCL_212                    ; 001FE019 40480110
	  MUL_IEEE                T9.W, PS, T26.X,  BS:VEC_021/SCL_122                    ; 000340FF 61240110
	  MIN                   * T6.W, PV.W, literal.x,                                  ; 801FACFE 60C00210
	1142931456(6.390000e+02), 0(0.000000e+00)                                         ; 441FC000 00000000
	  MOV                     T25.X, T7.X,                                            ; 00000007 03200C90
	  MULADD_IEEE             T3.Z, T27.X, PS, PV.W, BS:VEC_120/SCL_212               ; 001FE01B 406B0CFE
	  MUL_IEEE              * T9.W, T1.W, T28.X,  BS:VEC_021/SCL_122                  ; 80038C01 61240110
	  MULADD_IEEE           * T14.W, T29.X, T6.W, T2.Z,                               ; 8180C01D 61C30802
	ALU clause starting at 0xf27:                                                     ; 
	  MULADD_IEEE           * T14.W, T17.X, 0.0, T14.W,                               ; 801F0011 61C30C0E
	  MOV                     T17.X, T7.X,                                            ; 00000007 02200C90
	  ADD                     T2.Z, T18.X, PV.W,  BS:VEC_120/SCL_212                  ; 019FC012 40480010
	  MULADD_IEEE           * T9.W, T22.X, T6.W, T9.W, BS:VEC_201                     ; 8180C016 61330C09
	  MULADD_IEEE           * T14.W, T23.X, 0.0, T3.Z,                                ; 801F0017 61C30803
	  MOV                     T18.X, T7.X,                                            ; 00000007 02400C90
	  MUL_IEEE                T2.Y, T1.W, T24.X,                                      ; 00030C01 20400110
	  ADD                   * T3.Z, T8.X, PV.W,  BS:VEC_201                           ; 819FC008 40700010
	  MULADD_IEEE             T1.W, T30.X, 0.0, T9.W,                                 ; 001F001E 60230C09
	  RECIP_IEEE            * T2.Z, T2.Z,                                             ; 80000802 40404310
	  MOV                     T8.X, T7.X,                                             ; 00000007 01000C90
	  ADD                     T6.Z, T12.X, PV.W,  BS:VEC_120/SCL_212                  ; 019FC00C 40C80010
	  MUL_IEEE                T9.W, PS, T3.Z,                                         ; 010060FF 61200110
	  MULADD_IEEE           * T1.W, T25.X, T6.W, T2.Y,                                ; 8180C019 60230402
	ALU clause starting at 0xf35:                                                     ; 
	  MULADD_IEEE           * T1.W, T6.X, 0.0, T1.W,                                  ; 801F0006 60230C01
	  ADD                     T3.Z, T9.X, PV.W,                                       ; 019FC009 40600010
	  MUL_IEEE                T1.W, T9.W, T9.W,                                       ; 01812C09 60200110
	  MUL_IEEE              * T6.W, T2.Z, T6.Z,                                       ; 8100C802 60C00110
	  MULADD_IEEE             T1.W, PS, PS, PV.W,                                     ; 001FE0FF 60230CFE
	  MUL_IEEE              * T14.W, T2.Z, PV.Z,                                      ; 811FC802 61C00110
	  MULADD_IEEE           * T1.W, PS, PS, PV.W,                                     ; 801FE0FF 60230CFE
	  RECIPSQRT_CLAMPED     * T2.Y, PV.W,                                             ; 80000CFE 20404390
	  MUL NON-IEEE          * T1.W, T1.W, PS,                                         ; 801FEC01 60200090
	  RECIP_IEEE            * T1.W, PV.W,                                             ; 80000CFE 60204310
	  MUL_IEEE              * T16.W, T9.W, PS,                                        ; 801FEC09 62000110
	  MUL_IEEE                T17.W, PV.W, T13.X,                                     ; 0001ACFE 62200110
	  MUL_IEEE              * T18.W, T6.W, T1.W,                                      ; 81802C06 62400110
	  MULADD_IEEE             T17.W, T14.X, PS, PV.W,                                 ; 001FE00E 62230CFE
	  MUL_IEEE              * T1.W, T14.W, T1.W,                                      ; 81802C0E 60200110
	  MULADD_IEEE             T9.X, T15.X, PS, PV.W,                                  ; 001FE00F 01230CFE
	  MUL_IEEE                T17.W, T16.W, T16.X,                                    ; 00020C10 62200110
	  ADD_INT               * T20.W, T2.X, literal.x,                                 ; 801FA002 62801A10
	20(2.802597e-44), 0(0.000000e+00)                                                 ; 00000014 00000000
	  LSHR                    T22.X, PS, literal.x,                                   ; 001FA0FF 02C00B10
	  MULADD_IEEE           * T17.W, T17.X, T18.W, PV.W,                              ; 81824011 62230CFE
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T23.X, T18.X, T1.W, PV.W,                               ; 01802012 02E30CFE
	  MOV                   * T24.X, T7.X,                                            ; 80000007 03000C90
	  MOV                     T25.X, T7.X,                                            ; 00000007 03200C90
	  MOV                   * T26.X, T7.X,                                            ; 80000007 03400C90
	  MOV                     T27.X, T7.X,                                            ; 00000007 03600C90
	  MOV                   * T28.X, T7.X,                                            ; 80000007 03800C90
	  MOV                     T29.X, T7.X,                                            ; 00000007 03A00C90
	  MOV                   * T30.X, T7.X,                                            ; 80000007 03C00C90
	  MOV                     T31.X, T7.X,                                            ; 00000007 03E00C90
	  MOV                   * T6.X, T7.X,                                             ; 80000007 00C00C90
	  MOV                     T12.X, T7.X,                                            ; 00000007 01800C90
	  MUL_IEEE              * T17.W, T9.W, T8.X,                                      ; 80010C09 62200110
	ALU clause starting at 0xf57:                                                     ; 
	  MUL_IEEE                T2.Y, T16.W, T25.X,                                     ; 00032C10 20400110
	  MULADD_IEEE           * T2.Z, T29.X, T6.W, T17.W,                               ; 8180C01D 40430C11
	  MUL_IEEE                T16.W, T9.W, T13.X,                                     ; 0001AC09 62000110
	  ADD_INT               * T17.W, T2.X, literal.x,                                 ; 801FA002 62201A10
	16(2.242078e-44), 0(0.000000e+00)                                                 ; 00000010 00000000
	  LSHR                    T8.X, PS, literal.x,                                    ; 001FA0FF 01000B10
	  MULADD_IEEE             T3.Z, T14.X, T6.W, PV.W, BS:VEC_021/SCL_122             ; 0180C00E 40670CFE
	  MULADD_IEEE             T16.W, T28.X, T14.W, T2.Z, BS:VEC_102/SCL_221           ; 0181C01C 620F0802
	  MULADD_IEEE           * T17.W, T26.X, T18.W, T2.Y,                              ; 8182401A 62230402
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MULADD_IEEE             T28.X, T24.X, T1.W, PS,                                 ; 01802018 038300FF
	  ADD                     T2.Y, T27.X, PV.W,  BS:VEC_120/SCL_212                  ; 019FC01B 20480010
	  MULADD_IEEE           * T2.Z, T15.X, T14.W, PV.Z, BS:VEC_201                    ; 8181C00F 405308FE
	  MUL_IEEE                T16.W, T9.W, T16.X,                                     ; 00020C09 62000110
	  ADD_INT               * T17.W, T2.X, literal.x,                                 ; 801FA002 62201A10
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  LSHR                    T15.X, PS, literal.x,                                   ; 001FA0FF 01E00B10
	  MULADD_IEEE             T3.Z, T17.X, T6.W, PV.W,                                ; 0180C011 40630CFE
	  ADD                     T16.W, T7.X, T2.Z,  BS:VEC_120/SCL_212                  ; 01004007 62080010
	  RECIP_IEEE            * T2.Y, T2.Y,                                             ; 80000402 20404310
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T13.X, PS, PV.W,                                        ; 019FC0FF 01A00110
	  MULADD_IEEE             T2.Z, T18.X, T14.W, PV.Z,                               ; 0181C012 404308FE
	  MUL_IEEE                T9.W, T9.W, T25.X,                                      ; 00032C09 61200110
	  ADD_INT               * T16.W, T2.X, literal.x,                                 ; 801FA002 62001A10
	8(1.121039e-44), 0(0.000000e+00)                                                  ; 00000008 00000000
	  LSHR                    T7.X, PS, literal.x,                                    ; 001FA0FF 00E00B10
	  MULADD_IEEE             T6.W, T26.X, T6.W, PV.W,                                ; 0180C01A 60C30CFE
	  ADD                   * T9.W, T30.X, PV.Z,                                      ; 811FC01E 61200010
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T14.X, T2.Y, PS,                                        ; 001FE402 01C00110
	  MULADD_IEEE             T6.W, T24.X, T14.W, PV.W,                               ; 0181C018 60C30CFE
	  ADD_INT               * T9.W, T2.X, literal.x,                                  ; 801FA002 61201A10
	4(5.605194e-45), 0(0.000000e+00)                                                  ; 00000004 00000000
	  LSHR                    T16.X, PS, literal.x,                                   ; 001FA0FF 02000B10
	  ADD                   * T6.W, T31.X, PV.W,                                      ; 819FC01F 60C00010
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T17.X, T2.Y, PV.W,                                      ; 019FC402 02200110
	  LSHR                  * T18.X, T2.X, literal.x,                                 ; 801FA002 02400B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0xf7f:                                                     ; 
	  LSHL                  * T6.W, T12.W, literal.x,                                 ; 801FAC0C 60C00B90
	3(4.203895e-45), 0(0.000000e+00)                                                  ; 00000003 00000000
	  LSHL                    T2.Z, T5.W, literal.x,                                  ; 001FAC05 40400B90
	  XOR_INT                 T5.W, PV.W, T12.W,                                      ; 01818CFE 60A01910
	  LSHL                  * T6.W, T1.Y, literal.y,                                  ; 809FA401 60C00B90
	6(8.407791e-45), 10(1.401298e-44)                                                 ; 00000006 0000000A
	  XOR_INT                 T8.X, T10.W, PS,                                        ; 001FEC0A 01001910
	  LSHL                    T1.Y, T13.W, literal.x,  BS:VEC_120/SCL_212             ; 001FAC0D 20280B90
	  LSHL                    T3.Z, T15.W, literal.y,  BS:VEC_201                     ; 009FAC0F 40700B90
	  LSHR                    T5.W, PV.W, literal.z,                                  ; 011FACFE 60A00B10
	  AND_INT               * T6.W, PV.Z, literal.w,                                  ; 819FA8FE 60C01810
	4(5.605194e-45), 13(1.821688e-44)                                                 ; 00000004 0000000D
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  OR_INT                  T7.X, PV.W, PS,                                         ; 001FECFE 00E01890
	  LSHL                    T2.Y, T15.W, literal.x,                                 ; 001FAC0F 20400B90
	  XOR_INT                 T2.Z, PV.Z, T11.W,                                      ; 018168FE 40401910
	  AND_INT                 T5.W, PV.Y, literal.y,                                  ; 009FA4FE 60A01810
	  LSHR                  * T6.W, PV.X, literal.z,                                  ; 811FA0FE 60C00B10
	12(1.681558e-44), -128(-nan)                                                      ; 0000000C FFFFFF80
	25(3.503246e-44), 0(0.000000e+00)                                                 ; 00000019 00000000
	  OR_INT                  T8.X, PV.W, PS,                                         ; 001FECFE 01001890
	  LSHR                    T5.W, PV.Z, literal.x,                                  ; 001FA8FE 60A00B10
	  AND_INT               * T6.W, PV.Y, literal.y,                                  ; 809FA4FE 60C01810
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  OR_INT                  T9.X, PV.W, PS,                                         ; 001FECFE 01201890
	  XOR_INT                 T5.W, T7.X, PV.X,                                       ; 001FC007 60A01910
	  ADD_INT               * T6.W, T17.X, literal.x,                                 ; 801FA011 60C01A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  XOR_INT               * T5.W, PV.W, PV.X,                                       ; 801FCCFE 60A01910
	  AND_INT                 T2.Z, PV.W, literal.x,                                  ; 001FACFE 40401810
	  ADD                     T9.W, T6.W, -T17.X,                                     ; 02022C06 61200010
	  MOV                   * T5.W, literal.y,                                        ; 800004FD 60A00C90
	16777215(2.350989e-38), 1036831949(1.000000e-01)                                  ; 00FFFFFF 3DCCCCCD
	  MOV                     T6.W, PS,                                               ; 000000FF 60C00C90
	  SETGT_DX10            * T10.W, |PV.W|, literal.x,                               ; 801FACFE 61400691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  UINT_TO_FLT           * T1.Y, T2.Z,                                             ; 80000802 20204E10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), T10.W, 0.0,                 ; 801F0C0A 00002288
	  MOV                   * T6.W, |T9.W|, Pred_sel_zero                             ; C0000C09 60C00C91
	  MAX                   * T6.W, T6.W, literal.x, Pred_sel_zero                    ; C01FAC06 60C00190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T9.W, T14.X, literal.x,                                 ; 801FA00E 61201A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T10.W, PV.W, -T14.X,                                    ; 0201CCFE 61400010
	  MOV                   * T9.W, T5.W,                                             ; 80000C05 61200C90
	  ADD                     T2.Y, T12.X, -T6.X,                                     ; 0200C00C 20400010
	  ADD                     T2.Z, T1.Y, 0.0,                                        ; 001F0401 40400010
	  SETGT_DX10              T11.W, |PV.W|, literal.x,                               ; 001FACFE 61600691
	  RECIP_IEEE            * T1.Y, T1.W,                                             ; 80000C01 20204310
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T1.W, |T10.W|, Pred_sel_zero                            ; C0000C0A 60200C91
	  MAX                   * T9.W, T1.W, literal.x, Pred_sel_zero                    ; C01FAC01 61200190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T1.W, T13.X, literal.x,                                 ; 801FA00D 60201A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  MUL_IEEE                T12.X, T2.Y, T1.Y,                                      ; 00802402 01800110
	  ADD                     T1.W, PV.W, -T13.X,                                     ; 0201ACFE 60200010
	  MUL_IEEE              * T6.X, T2.Z, literal.x,                                  ; 801FA802 00C00110
	864026624(5.960464e-08), 0(0.000000e+00)                                          ; 33800000 00000000
	  SETGT_DX10            * T10.W, |PV.W|, literal.x,                               ; 801FACFE 61400691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T1.W, |T1.W|, Pred_sel_zero                             ; C0000C01 60200C91
	  MAX                   * T5.W, T1.W, literal.x, Pred_sel_zero                    ; C01FAC01 60A00190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T1.W, T0.X, literal.x,                                  ; 801FA000 60201A10
	100(1.401298e-43), 0(0.000000e+00)                                                ; 00000064 00000000
	  LSHR                    T13.X, PV.W, literal.x,                                 ; 001FACFE 01A00B10
	  ADD_INT               * T1.W, T0.X, literal.y,                                  ; 809FA000 60201A10
	2(2.802597e-45), 164(2.298129e-43)                                                ; 00000002 000000A4
	  LSHR                    T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00B10
	  ADD_INT               * T1.W, T0.X, literal.y,                                  ; 809FA000 60201A10
	2(2.802597e-45), 160(2.242078e-43)                                                ; 00000002 000000A0
	  LSHR                    T15.X, PV.W, literal.x,                                 ; 001FACFE 01E00B10
	  ADD_INT               * T1.W, T0.X, literal.y,                                  ; 809FA000 60201A10
	2(2.802597e-45), 40(5.605194e-44)                                                 ; 00000002 00000028
	  LSHR                    T16.X, PV.W, literal.x,                                 ; 001FACFE 02000B10
	  ADD_INT               * T1.W, T0.X, literal.y,                                  ; 809FA000 60201A10
	2(2.802597e-45), 36(5.044674e-44)                                                 ; 00000002 00000024
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  ADD_INT               * T1.W, T0.X, literal.y,                                  ; 809FA000 60201A10
	2(2.802597e-45), 32(4.484155e-44)                                                 ; 00000002 00000020
	  LSHR                    T18.X, PV.W, literal.x,                                 ; 001FACFE 02400B10
	  MOV                   * T22.X, literal.y,                                       ; 800004FD 02C00C90
	2(2.802597e-45), 1065353216(1.000000e+00)                                         ; 00000002 3F800000
	  MOV                     T23.X, literal.x,                                       ; 000000FD 02E00C90
	  LSHR                  * T24.X, T5.Z, literal.y,                                 ; 809FA805 03000B10
	1(1.401298e-45), 2(2.802597e-45)                                                  ; 00000001 00000002
	  LSHR                    T25.X, T2.W, literal.x,                                 ; 001FAC02 03200B10
	  ADD_INT               * T1.W, T2.X, literal.y,                                  ; 809FA002 60201A10
	2(2.802597e-45), 28(3.923636e-44)                                                 ; 00000002 0000001C
	  LSHR                    T26.X, PV.W, literal.x,                                 ; 001FACFE 03400B10
	  MAX                   * T1.W, T9.W, T5.W,                                       ; 8180AC09 60200190
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MAX                     T27.X, T6.W, PV.W,                                      ; 019FCC06 03600190
	  ADD_INT               * T1.W, T2.X, literal.x,                                  ; 801FA002 60201A10
	24(3.363116e-44), 0(0.000000e+00)                                                 ; 00000018 00000000
	  LSHR                  * T28.X, PV.W, literal.x,                                 ; 801FACFE 03800B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0xfe3:                                                     ; 
	  BFE_INT               * T1.W, T11.X, 0.0, 1,                                    ; 801F000B 6020A0FA
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0xfe5:                                                     ; 
	  AND_INT               * T0.W, T8.W, 1,                                          ; 801F4C08 60001810
	  SETE_INT              * T0.W, PV.W, 0.0,                                        ; 801F0CFE 60001D10
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MUL_IEEE              * T20.X, T20.X, T7.W, Pred_sel_zero                       ; C180E014 02800110
	  MOV                     T5.X, T0.X,                                             ; 00000000 00A00C90
	  MOV                   * T6.X, T0.X,                                             ; 80000000 00C00C90
	  MOV                   * T11.X, T0.X,                                            ; 80000000 01600C90
	ALU clause starting at 0xfec:                                                     ; 
	  RECIP_IEEE            * T0.Y, T20.X,                                            ; 80000014 20004310
	  MUL_IEEE              * T0.W, T4.Z, PS,                                         ; 801FE804 60000110
	  MUL_IEEE              * T1.W, T21.Z, PV.W,                                      ; 819FC815 60200110
	  MUL_IEEE                T5.X, T5.X, PV.W,                                       ; 019FC005 00A00110
	  ADD_INT               * T1.W, T0.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA000 60281A10
	40(5.605194e-44), 0(0.000000e+00)                                                 ; 00000028 00000000
	  LSHR                    T12.X, PV.W, literal.x,                                 ; 001FACFE 01800B10
	  MUL_IEEE              * T1.W, T21.Y, T0.W,                                      ; 81800415 60200110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T6.X, T6.X, PV.W,                                       ; 019FC006 00C00110
	  ADD_INT               * T1.W, T0.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA000 60281A10
	36(5.044674e-44), 0(0.000000e+00)                                                 ; 00000024 00000000
	  LSHR                    T13.X, PV.W, literal.x,                                 ; 001FACFE 01A00B10
	  MUL_IEEE              * T0.W, T21.X, T0.W,                                      ; 81800015 60000110
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  MUL_IEEE                T11.X, T11.X, PV.W,                                     ; 019FC00B 01600110
	  ADD_INT               * T0.W, T0.X, literal.x,  BS:VEC_120/SCL_212              ; 801FA000 60081A10
	32(4.484155e-44), 0(0.000000e+00)                                                 ; 00000020 00000000
	  LSHR                  * T14.X, PV.W, literal.x,                                 ; 801FACFE 01C00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x1000:                                                    ; 
	  MOV                     T11.X, T0.X,                                            ; 00000000 01600C90
	  MOV                   * T6.X, T0.X,                                             ; 80000000 00C00C90
	  MOV                   * T5.X, T0.X,                                             ; 80000000 00A00C90
	ALU clause starting at 0x1003:                                                    ; 
	  ADD_INT               * T0.W, T2.X, literal.x,                                  ; 801FA002 60001A10
	20(2.802597e-44), 0(0.000000e+00)                                                 ; 00000014 00000000
	  LSHR                    T12.X, PV.W, literal.x,                                 ; 001FACFE 01800B10
	  MOV                   * T13.X, T19.Z,                                           ; 80000813 01A00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T0.W, T2.X, literal.x,                                  ; 801FA002 60001A10
	16(2.242078e-44), 0(0.000000e+00)                                                 ; 00000010 00000000
	  LSHR                    T14.X, PV.W, literal.x,                                 ; 001FACFE 01C00B10
	  MOV                   * T15.X, T19.Y,                                           ; 80000413 01E00C90
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  ADD_INT               * T0.W, T2.X, literal.x,                                  ; 801FA002 60001A10
	12(1.681558e-44), 0(0.000000e+00)                                                 ; 0000000C 00000000
	  LSHR                    T16.X, PV.W, literal.x,                                 ; 001FACFE 02000B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 8(1.121039e-44)                                                  ; 00000002 00000008
	  LSHR                    T17.X, PV.W, literal.x,                                 ; 001FACFE 02200B10
	  ADD_INT               * T0.W, T2.X, literal.y,                                  ; 809FA002 60001A10
	2(2.802597e-45), 4(5.605194e-45)                                                  ; 00000002 00000004
	  LSHR                    T18.X, PV.W, literal.x,                                 ; 001FACFE 02400B10
	  LSHR                  * T21.X, T2.X, literal.x,                                 ; 801FA002 02A00B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x1018:                                                    ; 
	  ADD_INT               * T0.W, T11.X, literal.x,                                 ; 801FA00B 60001A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T3.W, PV.W, -T11.X,                                     ; 02016CFE 60600010
	  MOV                   * T1.W, literal.x,                                        ; 800000FD 60200C90
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  MOV                     T0.W, PS,                                               ; 000000FF 60000C90
	  SETGT_DX10            * T4.W, |PV.W|, literal.x,                                ; 801FACFE 60800691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PS, 0.0,                    ; 801F00FF 00002288
	  MOV                   * T0.W, |T3.W|, Pred_sel_zero                             ; C0000C03 60000C91
	  MAX                   * T0.W, T0.W, literal.x, Pred_sel_zero                    ; C01FAC00 60000190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T3.W, T6.X, literal.x,                                  ; 801FA006 60601A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                     T3.W, PV.W, -T6.X,                                      ; 0200CCFE 60600010
	  MOV                   * T5.W, T1.W,                                             ; 80000C01 60A00C90
	  SETGT_DX10            * T4.W, |PV.W|, literal.x,                                ; 801FACFE 60800691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T3.W, |T3.W|, Pred_sel_zero                             ; C0000C03 60600C91
	  MAX                   * T5.W, T3.W, literal.x, Pred_sel_zero                    ; C01FAC03 60A00190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  ADD_INT               * T3.W, T5.X, literal.x,                                  ; 801FA005 60601A10
	128(1.793662e-43), 0(0.000000e+00)                                                ; 00000080 00000000
	  ADD                   * T3.W, PV.W, -T5.X,                                      ; 8200ACFE 60600010
	  SETGT_DX10            * T4.W, |PV.W|, literal.x,                                ; 801FACFE 60800691
	1036831949(1.000000e-01), 0(0.000000e+00)                                         ; 3DCCCCCD 00000000
	  PRED_SETNE_INT        * Pred,PredicateBit (MASKED), PV.W, 0.0,                  ; 801F0CFE 00002288
	  MOV                   * T1.W, |T3.W|, Pred_sel_zero                             ; C0000C03 60200C91
	  MAX                   * T1.W, T1.W, literal.x, Pred_sel_zero                    ; C01FAC01 60200190
	814313567(1.000000e-09), 0(0.000000e+00)                                          ; 3089705F 00000000
	  LSHL                    T3.W, T1.Z, literal.x,                                  ; 001FA801 60600B90
	  LSHL                  * T4.W, T3.X, literal.y,                                  ; 809FA003 60800B90
	2(2.802597e-45), 3(4.203895e-45)                                                  ; 00000002 00000003
	  XOR_INT               * T3.W, PV.W, T1.Z,                                       ; 81002CFE 60601910
	  LSHR                    T5.X, PV.W, literal.x,                                  ; 001FACFE 00A00B10
	  LSHL                    T0.Y, T3.X, literal.y,                                  ; 009FA003 20000B90
	  XOR_INT                 T2.Z, T4.W, T3.X,                                       ; 00006C04 40401910
	  LSHL                    T3.W, T4.X, literal.z,  BS:VEC_201                      ; 011FA004 60700B90
	  LSHL                  * T4.W, T1.Z, literal.w,                                  ; 819FA801 60800B90
	25(3.503246e-44), 17(2.382207e-44)                                                ; 00000019 00000011
	13(1.821688e-44), 4(5.605194e-45)                                                 ; 0000000D 00000004
	  AND_INT                 T3.X, PS, literal.x,                                    ; 001FA0FF 00601810
	  LSHL                    T1.Y, T4.X, literal.y,                                  ; 009FA004 20200B90
	  XOR_INT                 T1.Z, PV.W, T4.X,                                       ; 00008CFE 40201910
	  LSHR                    T3.W, PV.Z, literal.z,                                  ; 011FA8FE 60600B10
	  AND_INT               * T4.W, PV.Y, literal.w,                                  ; 819FA4FE 60801810
	-128(-nan), 12(1.681558e-44)                                                      ; FFFFFF80 0000000C
	11(1.541428e-44), -2097152(-nan)                                                  ; 0000000B FFE00000
	  OR_INT                  T0.Y, PV.W, PS,                                         ; 001FECFE 20001890
	  LSHR                    T1.Z, PV.Z, literal.x,                                  ; 001FA8FE 40200B10
	  AND_INT                 T4.W, PV.Y, literal.y,                                  ; 009FA4FE 60801810
	  OR_INT                * T3.W, T5.X, PV.X,                                       ; 801FC005 60601890
	19(2.662467e-44), -8192(-nan)                                                     ; 00000013 FFFFE000
	  XOR_INT                 T6.W, PS, PV.Y,                                         ; 009FC0FF 60C01910
	  OR_INT                * T4.W, PV.Z, PV.W,                                       ; 819FC8FE 60801890
	  XOR_INT               * T6.W, PV.W, PS,                                         ; 801FECFE 60C01910
	  AND_INT               * T6.W, PV.W, literal.x,                                  ; 801FACFE 60C01810
	16777215(2.350989e-38), 0(0.000000e+00)                                           ; 00FFFFFF 00000000
	  UINT_TO_FLT           * T1.Y, PV.W,                                             ; 80000CFE 20204E10
	  MOV                     T5.X, literal.x,                                        ; 000000FD 00A00C90
	  ADD                   * T6.W, PS, 0.0,                                          ; 801F00FF 60C00010
	0(0.000000e+00), 0(0.000000e+00)                                                  ; 00000000 00000000
	  MUL_IEEE                T3.X, PV.W, literal.x,                                  ; 001FACFE 00600110
	  LSHR                  * T4.X, T0.Z, literal.y,                                  ; 809FA800 00800B10
	864026624(5.960464e-08), 2(2.802597e-45)                                          ; 33800000 00000002
	  ADD_INT               * T6.W, T0.X, literal.x,                                  ; 801FA000 60C01A10
	164(2.298129e-43), 0(0.000000e+00)                                                ; 000000A4 00000000
	  LSHR                    T6.X, PV.W, literal.x,                                  ; 001FACFE 00C00B10
	  ADD_INT               * T6.W, T0.X, literal.y,                                  ; 809FA000 60C01A10
	2(2.802597e-45), 160(2.242078e-43)                                                ; 00000002 000000A0
	  LSHR                    T11.X, PV.W, literal.x,                                 ; 001FACFE 01600B10
	  ADD_INT               * T1.X, T1.X, 1,                                          ; 801F4001 00201A10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  LSHR                    T12.X, T5.Z, literal.x,                                 ; 001FA805 01800B10
	  ADD_INT               * T6.W, T2.X, literal.y,                                  ; 809FA002 60C01A10
	2(2.802597e-45), 28(3.923636e-44)                                                 ; 00000002 0000001C
	  LSHR                    T13.X, PV.W, literal.x,                                 ; 001FACFE 01A00B10
	  MOV                   * T14.X, literal.y,                                       ; 800004FD 01C00C90
	2(2.802597e-45), 2139095040(inf)                                                  ; 00000002 7F800000
	  MAX                   * T1.W, T5.W, T1.W,                                       ; 81802C05 60200190
	  MAX                     T15.X, T0.W, PV.W,                                      ; 019FCC00 01E00190
	  ADD_INT               * T0.W, T2.X, literal.x,                                  ; 801FA002 60001A10
	24(3.363116e-44), 0(0.000000e+00)                                                 ; 00000018 00000000
	  LSHR                    T2.X, PV.W, literal.x,                                  ; 001FACFE 00400B10
	  MOV                   * T0.W, literal.y,                                        ; 800004FD 60000C90
	2(2.802597e-45), 1(1.401298e-45)                                                  ; 00000002 00000001
	ALU clause starting at 0x106f:                                                    ; 
	  ADD_INT                 T0.Z, T0.X, literal.x,                                  ; 001FA000 40001A10
	  BFE_INT                 T1.W, T0.W, 0.0, 1,                                     ; 001F0C00 6020A0FA
	  ADD_INT               * T0.W, T0.X, literal.y,                                  ; 809FA000 60001A10
	8(1.121039e-44), 4(5.605194e-45)                                                  ; 00000008 00000004
	  PRED_SETNE_INT        * ExecMask,PredicateBit (MASKED), PV.W, 0.0,              ; 801F0CFE 00002284
	ALU clause starting at 0x1074:                                                    ; 
	  MOV                     T9.X, T4.W,                                             ; 00000C04 01200C90
	  MOV                   * T8.X, T3.W,                                             ; 80000C03 01000C90
	  MOV                     T7.X, T0.Y,                                             ; 00000400 00E00C90
	  LSHR                  * T1.X, T2.W, literal.x,                                  ; 801FAC02 00200B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	ALU clause starting at 0x1079:                                                    ; 
	  LSHR                    T1.X, T0.Z, literal.x,                                  ; 001FA800 00200B10
	  LSHR                  * T2.X, T0.W, literal.x,                                  ; 801FAC00 00400B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000
	  LSHR                  * T0.X, T0.X, literal.x,                                  ; 801FA000 00000B10
	2(2.802597e-45), 0(0.000000e+00)                                                  ; 00000002 00000000

bytecode 8444 dw -- 42 gprs -- 3 nstack -------------
shader 3 -- E
--------------------------------------
input 0 : 1024
input 1 : 1
input 2 : 1
input 3 : 65536
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 4952064
input 10 : 1310720
input 11 : 26972160
input 12 : 27762688
input 13 : 0
input 14 : 51113984
input 15 : 1572864
input 16 : 1576960
input 17 : 1581056
input 18 : 1585152
input 19 : 1589248
input 20 : 56066048
input 21 : 4272128
input 22 : 58748928
input 23 : 59318272
input 24 : 30908416
input 25 : 4599808
input 26 : 4603904
Using 2 pipes, 2 wavefronts per thread block, allocating 0 dwords lds.
*** evergreen_set_global_binding first = 0 n = 18
*** evergreen_set_compute_resources: start = 0 count = 0
* r600_compute_global_transfer_map()
level = 0, usage = 1, box(x = 0, y = 0, z = 0 width = 4951104, height = 1, depth = 1)
Buffer id = 0 offset = 0 (box.x)
* r600_compute_global_transfer_map()
level = 0, usage = 1, box(x = 0, y = 0, z = 0 width = 262144, height = 1, depth = 1)
Buffer id = 3 offset = 0 (box.x)
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 4
* compute_memory_finalize_pending()
  + list: offset = 0 id = 6 size = 327680 (1310720 bytes)
  + list: offset = 393216 id = 9 size = 60 (240 bytes)
  + list: offset = 394240 id = 10 size = 603 (2412 bytes)
  + list: offset = 395264 id = 11 size = 7 (28 bytes)
  + list: offset = 396288 id = 12 size = 266 (1064 bytes)
  + list: offset = 397312 id = 13 size = 670140 (2680560 bytes)
  + list: offset = 1068032 id = 15 size = 81502 (326008 bytes)
  + list: offset = 1149952 id = 18 size = 68 (272 bytes)
  + list: offset = 1150976 id = 19 size = 7 (28 bytes)
  + list: offset = 1238016 id = 1 size = 5505024 (22020096 bytes)
  + list: offset = 6743040 id = 2 size = 131073 (524292 bytes)
  + list: offset = 6940672 id = 4 size = 786432 (3145728 bytes)
  + list: offset = 7727104 id = 5 size = 132 (528 bytes)
  + list: offset = 7728128 id = 7 size = 1217076 (4868304 bytes)
  + list: offset = 8945664 id = 8 size = 3832532 (15330128 bytes)
  + list: offset = 14016512 id = 14 size = 670140 (2680560 bytes)
  + list: offset = 14687232 id = 16 size = 141693 (566772 bytes)
  + list: offset = 14829568 id = 17 size = 782382 (3129528 bytes)
bind rat: 0 
*** evergreen_launch_grid: pc = 0
input 0 : 1024
input 1 : 1
input 2 : 1
input 3 : 65536
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 27762688
input 10 : 0
input 11 : 30912512
input 12 : 35782656
input 13 : 65536
input 14 : 0
Using 2 pipes, 2 wavefronts per thread block, allocating 2048 dwords lds.
*** evergreen_set_global_binding first = 0 n = 4
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_bind_compute_state
*** evergreen_set_compute_resources: start = 0 count = 0
*** evergreen_set_global_binding first = 0 n = 18
* compute_memory_finalize_pending()
  + list: offset = 0 id = 6 size = 327680 (1310720 bytes)
  + list: offset = 393216 id = 9 size = 60 (240 bytes)
  + list: offset = 394240 id = 10 size = 603 (2412 bytes)
  + list: offset = 395264 id = 11 size = 7 (28 bytes)
  + list: offset = 396288 id = 12 size = 266 (1064 bytes)
  + list: offset = 397312 id = 13 size = 670140 (2680560 bytes)
  + list: offset = 1068032 id = 15 size = 81502 (326008 bytes)
  + list: offset = 1149952 id = 18 size = 68 (272 bytes)
  + list: offset = 1150976 id = 19 size = 7 (28 bytes)
  + list: offset = 1238016 id = 1 size = 5505024 (22020096 bytes)
  + list: offset = 6743040 id = 2 size = 131073 (524292 bytes)
  + list: offset = 6940672 id = 4 size = 786432 (3145728 bytes)
  + list: offset = 7727104 id = 5 size = 132 (528 bytes)
  + list: offset = 7728128 id = 7 size = 1217076 (4868304 bytes)
  + list: offset = 8945664 id = 8 size = 3832532 (15330128 bytes)
  + list: offset = 14016512 id = 14 size = 670140 (2680560 bytes)
  + list: offset = 14687232 id = 16 size = 141693 (566772 bytes)
  + list: offset = 14829568 id = 17 size = 782382 (3129528 bytes)
* compute_memory_prealloc_chunk() size_in_dw = 1237776
  + Found space for Item 0x436e4a0 id = 0 start_in_dw = 12778496 (51113984 bytes) size_in_dw = 1237776 (4951104 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 12778496
* compute_memory_prealloc_chunk() size_in_dw = 65536
  + Found space for Item 0x3503560 id = 3 start_in_dw = 327680 (1310720 bytes) size_in_dw = 65536 (262144 bytes)
* compute_memory_postalloc_chunck() start_in_dw = 327680
bind rat: 0 
*** evergreen_launch_grid: pc = 2
input 0 : 1024
input 1 : 1
input 2 : 1
input 3 : 65536
input 4 : 1
input 5 : 1
input 6 : 64
input 7 : 1
input 8 : 1
input 9 : 4952064
input 10 : 1310720
input 11 : 26972160
input 12 : 27762688
input 13 : 0
input 14 : 51113984
input 15 : 1572864
input 16 : 1576960
input 17 : 1581056
input 18 : 1585152
input 19 : 1589248
input 20 : 56066048
input 21 : 4272128
input 22 : 58748928
input 23 : 59318272
input 24 : 30908416
input 25 : 4599808
input 26 : 4603904
Using 2 pipes, 2 wavefronts per thread block, allocating 0 dwords lds.
*** evergreen_set_global_binding first = 0 n = 18
*** evergreen_set_compute_resources: start = 0 count = 0
timeout on cs lockup likely happen at cs 0x0000000a dw 0x0000019d
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
timeout on cs lockup likely happen at cs 0x0000026a dw 0x00000494
Killed