diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 4b5bb5d..e0a5c8b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1066,6 +1066,13 @@ nv50_disp_base_init(struct nouveau_object *object)
 	if (ret)
 		return ret;
 
+	nv_mask(priv, 0x100c18, 0x00000000, 0x000027ff);
+	nv_mask(priv, 0x100c14, 0x00000000, 0x00000001);
+	nv_mask(priv, 0x100c1c, 0x00000000, 0x000027fc);
+	nv_mask(priv, 0x100c14, 0x00000000, 0x00000002);
+	nv_mask(priv, 0x100c24, 0x00000002, 0x000027fd);
+	nv_mask(priv, 0x100c14, 0x00000000, 0x00010000);
+
 	/* The below segments of code copying values from one register to
 	 * another appear to inform EVO of the display capabilities or
 	 * something similar.  NFI what the 0x614004 caps are for..
@@ -1119,6 +1126,14 @@ nv50_disp_base_init(struct nouveau_object *object)
 	/* enable supervisor interrupts, disable everything else */
 	nv_wr32(priv, 0x61002c, 0x00000370);
 	nv_wr32(priv, 0x610028, 0x00000000);
+
+	nv_mask(priv, 0x100f64, 0xffffffff, 0x81000081);
+	nv_mask(priv, 0x100f68, 0xffffffff, 0x00004789);
+	nv_mask(priv, 0x100f6c, 0xffffffff, 0x00000b16);
+	nv_mask(priv, 0x100f30, 0x00006000, 0x00000000);
+	nv_mask(priv, 0x100b18, 0x00300722, 0x00000000);
+	nv_wr32(priv, 0x100bf0, 0xfffefffe);
+	nv_wr32(priv, 0x100bf4, 0xffffffff);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 38e0aa2..7473fad 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -921,6 +921,9 @@ nv50_graph_init(struct nouveau_object *object)
 	if (ret)
 		return ret;
 
+	nv_wr32(priv, 0x100ca0, 0x00000002);
+	nv_wr32(priv, 0x100ca4, 0x00000002);
+
 	/* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
 	nv_wr32(priv, 0x40008c, 0x00000004);
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
index 4150b0d..a5e5888a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
@@ -294,6 +294,7 @@ nv50_fb_init(struct nouveau_object *object)
 	 * cause IOMMU "read from address 0" errors (rh#561267)
 	 */
 	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
+	nv_wr32(priv, 0x100c9c, 0x200);
 
 	/* This is needed to get meaningful information from 100c90
 	 * on traps. No idea what these values mean exactly. */