--- /tmp/X1 2007-07-10 01:40:46.026619559 +0200 +++ /tmp/X2 2007-07-10 01:40:55.025246762 +0200 @@ -1,4 +1,4 @@ -(II) intel(0): Hardware state on X startup: +(II) intel(0): Hardware state at EnterVT: (II) intel(0): DumpRegsBegin (II) intel(0): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II) intel(0): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) @@ -6,7 +6,7 @@ (II) intel(0): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II) intel(0): D_STATE: 0x0000030f (II) intel(0): DSPCLK_GATE_D: 0x00000000 -(II) intel(0): RENCLK_GATE_D1: 0x00000000 +(II) intel(0): RENCLK_GATE_D1: 0x00000001 (II) intel(0): RENCLK_GATE_D2: 0x00000000 (II) intel(0): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II) intel(0): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) @@ -24,57 +24,57 @@ (II) intel(0): DVOB_SRCDIM: 0x00000000 (II) intel(0): DVOC_SRCDIM: 0x00000000 (II) intel(0): PP_CONTROL: 0x00000001 (power target: on) -(II) intel(0): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) -(II) intel(0): PFIT_CONTROL: 0x00000668 +(II) intel(0): PP_STATUS: 0xd0000009 (on, ready, sequencing on) +(II) intel(0): PFIT_CONTROL: 0x00000008 (II) intel(0): PFIT_PGM_RATIOS: 0x00000000 (II) intel(0): PORT_HOTPLUG_EN: 0x00000000 (II) intel(0): PORT_HOTPLUG_STAT: 0x00000000 -(II) intel(0): DSPACNTR: 0x00000000 (disabled, pipe A) -(II) intel(0): DSPASTRIDE: 0x00000000 (0 bytes) +(II) intel(0): DSPACNTR: 0x58000000 (disabled, pipe A) +(II) intel(0): DSPASTRIDE: 0x00002000 (8192 bytes) (II) intel(0): DSPAPOS: 0x00000000 (0, 0) -(II) intel(0): DSPASIZE: 0x00000000 (1, 1) -(II) intel(0): DSPABASE: 0x00000000 +(II) intel(0): DSPASIZE: 0x01df027f (640, 480) +(II) intel(0): DSPABASE: 0x000f0000 (II) intel(0): DSPASURF: 0x00000000 (II) intel(0): DSPATILEOFF: 0x00000000 -(II) intel(0): PIPEACONF: 0x80000000 (enabled, single-wide) +(II) intel(0): PIPEACONF: 0x00000000 (disabled, single-wide) (II) intel(0): PIPEASRC: 0x027f01df (640, 480) -(II) intel(0): FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) +(II) intel(0): FPA0: 0x0004140e (n = 4, m1 = 20, m2 = 14) (II) intel(0): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) -(II) intel(0): DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4) +(II) intel(0): DPLL_A: 0x10860000 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 4) (II) intel(0): DPLL_A_MD: 0x00000000 -(II) intel(0): HTOTAL_A: 0x031f027f (640 active, 800 total) -(II) intel(0): HBLANK_A: 0x03170287 (648 start, 792 end) -(II) intel(0): HSYNC_A: 0x02ef028f (656 start, 752 end) -(II) intel(0): VTOTAL_A: 0x020c01df (480 active, 525 total) -(II) intel(0): VBLANK_A: 0x020401e7 (488 start, 517 end) -(II) intel(0): VSYNC_A: 0x01eb01e9 (490 start, 492 end) +(II) intel(0): HTOTAL_A: 0x033f027f (640 active, 832 total) +(II) intel(0): HBLANK_A: 0x033f027f (640 start, 832 end) +(II) intel(0): HSYNC_A: 0x02bf0297 (664 start, 704 end) +(II) intel(0): VTOTAL_A: 0x020701df (480 active, 520 total) +(II) intel(0): VBLANK_A: 0x020701e8 (489 start, 520 end) +(II) intel(0): VSYNC_A: 0x01ea01e8 (489 start, 491 end) (II) intel(0): BCLRPAT_A: 0x00000000 (II) intel(0): VSYNCSHIFT_A: 0x00000000 -(II) intel(0): DSPBCNTR: 0xc9000000 (enabled, pipe B) -(II) intel(0): DSPBSTRIDE: 0x00000400 (1024 bytes) +(II) intel(0): DSPBCNTR: 0xd9000000 (enabled, pipe B) +(II) intel(0): DSPBSTRIDE: 0x00002000 (8192 bytes) (II) intel(0): DSPBPOS: 0x00000000 (0, 0) (II) intel(0): DSPBSIZE: 0x02ff03ff (1024, 768) -(II) intel(0): DSPBBASE: 0x00000000 +(II) intel(0): DSPBBASE: 0x000f0000 (II) intel(0): DSPBSURF: 0x00000000 (II) intel(0): DSPBTILEOFF: 0x00000000 (II) intel(0): PIPEBCONF: 0x80000000 (enabled, single-wide) (II) intel(0): PIPEBSRC: 0x03ff02ff (1024, 768) -(II) intel(0): FPB0: 0x00061207 (n = 6, m1 = 18, m2 = 7) +(II) intel(0): FPB0: 0x0005160e (n = 5, m1 = 22, m2 = 14) (II) intel(0): FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) -(II) intel(0): DPLL_B: 0x90016000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 1, p2 = 14) +(II) intel(0): DPLL_B: 0x90010000 (enabled, non-dvo, default clock, LVDS mode, p1 = 1, p2 = 14) (II) intel(0): DPLL_B_MD: 0x00000000 (II) intel(0): HTOTAL_B: 0x053f03ff (1024 active, 1344 total) (II) intel(0): HBLANK_B: 0x053f03ff (1024 start, 1344 end) (II) intel(0): HSYNC_B: 0x049f0417 (1048 start, 1184 end) (II) intel(0): VTOTAL_B: 0x032502ff (768 active, 806 total) -(II) intel(0): VBLANK_B: 0x032502ff (768 start, 806 end) +(II) intel(0): VBLANK_B: 0x03250302 (771 start, 806 end) (II) intel(0): VSYNC_B: 0x03080302 (771 start, 777 end) (II) intel(0): BCLRPAT_B: 0x00000000 (II) intel(0): VSYNCSHIFT_B: 0x00000000 (II) intel(0): VCLK_DIVISOR_VGA0: 0x00021207 (II) intel(0): VCLK_DIVISOR_VGA1: 0x00031406 (II) intel(0): VCLK_POST_DIV: 0x0000888b -(II) intel(0): VGACNTRL: 0xa114008e (disabled) +(II) intel(0): VGACNTRL: 0x80000000 (disabled) (II) intel(0): TV_CTL: 0x00000000 (II) intel(0): TV_DAC: 0x00000000 (II) intel(0): TV_CSC_Y: 0x00000000 @@ -135,7 +135,7 @@ (II) intel(0): CR0e: 0x06 (II) intel(0): CR0f: 0x66 (II) intel(0): CR10: 0x9c -(II) intel(0): CR11: 0x8e +(II) intel(0): CR11: 0x0e (II) intel(0): CR12: 0x8f (II) intel(0): CR13: 0x28 (II) intel(0): CR14: 0x1f @@ -155,6 +155,6 @@ (II) intel(0): CR22: 0x23 (II) intel(0): CR23: 0x00 (II) intel(0): CR24: 0x00 -(II) intel(0): pipe A dot 50307 n 2 m1 18 m2 7 p1 13 p2 4 -(II) intel(0): pipe B dot 97321 n 6 m1 18 m2 7 p1 1 p2 14 -(II) intel(0): DumpRegsEnd \ No hay ningún carácter de nueva línea al final del fichero +(II) intel(0): pipe A dot 63000 n 4 m1 20 m2 14 p1 8 p2 4 +(II) intel(0): pipe B dot 133224 n 5 m1 22 m2 14 p1 1 p2 14 +(II) intel(0): DumpRegsEnd