From e2ca76e23c6cd27b7c7b08e953aeaac540f4d75d Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 23 Sep 2014 06:24:46 -0700 Subject: [PATCH 2/2] drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw,chv to logical ring Similar to: commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b Author: Kenneth Graunke Date: Mon Jan 27 14:20:16 2014 -0800 drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround. On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set must be preceded by a PIPE_CONTROL with the "CS Stall" bit set. Documented on the BSpec 3D workarounds page. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 992d6d06..ca7ec10 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1155,6 +1155,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, struct intel_engine_cs *ring = ringbuf->ring; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; u32 flags = 0; + int ret; flags |= PIPE_CONTROL_CS_STALL; @@ -1172,6 +1173,15 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + + + /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ + ret = gen8_emit_pipe_control(ring, + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD, + 0); + if (ret) + return ret; } return gen8_emit_pipe_control(ringbuf, flags, scratch_addr); -- 1.9.3