commit dfea516af03dd208c1964c6cc197205f194fd55f
Author: Michel Dänzer <michel.daenzer@amd.com>
Date:   Wed Oct 8 16:01:47 2014 +0900

    r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled
    
    We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
    access may not work.

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 17aca01..13df495 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -924,7 +924,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
 	 * the CPU is much happier reading out of cached system memory
 	 * than uncached VRAM.
 	 */
-	if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
+	if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
 		use_staging_texture = TRUE;
 
 	/* Untiled buffers in VRAM, which is slow for CPU reads */