--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -827,7 +827,6 @@ enum punit_power_well {
 # define MI_FLUSH_ENABLE				(1 << 12)
 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
 # define MODE_IDLE					(1 << 9)
-# define STOP_RING					(1 << 8)
 
 #define GEN6_GT_MODE	0x20d0
 #define GEN7_GT_MODE	0x7008
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c	2014-08-14 04:36:35.000000000 +0200
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c	2014-08-15 20:47:34.352384250 +0200
@@ -455,30 +455,6 @@ static void ring_setup_phys_status_page(
 	I915_WRITE(HWS_PGA, addr);
 }
 
-static bool stop_ring(struct intel_engine_cs *ring)
-{
-	struct drm_i915_private *dev_priv = to_i915(ring->dev);
-
-	if (!IS_GEN2(ring->dev)) {
-		I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
-		if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
-			DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
-			return false;
-		}
-	}
-
-	I915_WRITE_CTL(ring, 0);
-	I915_WRITE_HEAD(ring, 0);
-	ring->write_tail(ring, 0);
-
-	if (!IS_GEN2(ring->dev)) {
-		(void)I915_READ_CTL(ring);
-		I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
-	}
-
-	return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
-}
-
 static int init_ring_common(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -486,11 +462,26 @@ static int init_ring_common(struct intel
 	struct intel_ringbuffer *ringbuf = ring->buffer;
 	struct drm_i915_gem_object *obj = ringbuf->obj;
 	int ret = 0;
+	u32 head;
 
 	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (!stop_ring(ring)) {
-		/* G45 ring initialization often fails to reset head to zero */
+	/* Stop the ring if it's running. */
+	I915_WRITE_CTL(ring, 0);
+	I915_WRITE_HEAD(ring, 0);
+	ring->write_tail(ring, 0);
+	if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
+		DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
+
+	if (I915_NEED_GFX_HWS(dev))
+		intel_ring_setup_status_page(ring);
+	else
+		ring_setup_phys_status_page(ring);
+
+	head = I915_READ_HEAD(ring) & HEAD_ADDR;
+
+	/* G45 ring initialization fails to reset head to zero */
+	if (head != 0) {
 		DRM_DEBUG_KMS("%s head not reset to zero "
 			      "ctl %08x head %08x tail %08x start %08x\n",
 			      ring->name,
@@ -499,7 +490,9 @@ static int init_ring_common(struct intel
 			      I915_READ_TAIL(ring),
 			      I915_READ_START(ring));
 
-		if (!stop_ring(ring)) {
+		I915_WRITE_HEAD(ring, 0);
+
+		if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 			DRM_ERROR("failed to set %s head to zero "
 				  "ctl %08x head %08x tail %08x start %08x\n",
 				  ring->name,
@@ -507,16 +500,9 @@ static int init_ring_common(struct intel
 				  I915_READ_HEAD(ring),
 				  I915_READ_TAIL(ring),
 				  I915_READ_START(ring));
-			ret = -EIO;
-			goto out;
 		}
 	}
 
-	if (I915_NEED_GFX_HWS(dev))
-		intel_ring_setup_status_page(ring);
-	else
-		ring_setup_phys_status_page(ring);
-
 	/* Initialize the ring. This must happen _after_ we've cleared the ring
 	 * registers with the above sequence (the readback of the HEAD registers
 	 * also enforces ordering), otherwise the hw might lose the new ring
@@ -1475,12 +1475,19 @@ void intel_cleanup_ring_buffer(struct in
 {
 	struct drm_i915_private *dev_priv = to_i915(ring->dev);
 	struct intel_ringbuffer *ringbuf = ring->buffer;
+	int ret;
 
 	if (!intel_ring_initialized(ring))
 		return;
 
-	intel_stop_ring_buffer(ring);
-	WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
+	/* Disable the ring buffer. The ring must be idle at this point */
+	dev_priv = ring->dev->dev_private;
+	ret = intel_ring_idle(ring);
+	if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
+		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
+			  ring->name, ret);
+
+	I915_WRITE_CTL(ring, 0);
 
 	iounmap(ringbuf->virtual_start);
 
@@ -2373,19 +2380,3 @@ intel_ring_invalidate_all_caches(struct
 	ring->gpu_caches_dirty = false;
 	return 0;
 }
-
-void
-intel_stop_ring_buffer(struct intel_engine_cs *ring)
-{
-	int ret;
-
-	if (!intel_ring_initialized(ring))
-		return;
-
-	ret = intel_ring_idle(ring);
-	if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
-		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
-			  ring->name, ret);
-
-	stop_ring(ring);
-}
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -34,7 +34,6 @@ struct  intel_hw_status_page {
 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 
 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
-#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
 
 enum intel_ring_hangcheck_action {
 	HANGCHECK_IDLE = 0,
@@ -284,7 +284,6 @@ intel_write_status_page(struct intel_eng
 #define I915_GEM_HWS_SCRATCH_INDEX	0x30
 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
-void intel_stop_ring_buffer(struct intel_engine_cs *ring);
 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
 
 int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
--- a/drivers/gpu/drm/i915/i915_gem.c	2014-08-14 04:36:35.000000000 +0200
+++ b/drivers/gpu/drm/i915/i915_gem.c	2014-08-16 00:52:36.946232144 +0200
@@ -4486,17 +4486,6 @@ void i915_gem_vma_destroy(struct i915_vm
 	kfree(vma);
 }
 
-static void
-i915_gem_stop_ringbuffers(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_engine_cs *ring;
-	int i;
-
-	for_each_ring(ring, dev_priv, i)
-		intel_stop_ring_buffer(ring);
-}
-
 int
 i915_gem_suspend(struct drm_device *dev)
 {
@@ -4507,7 +4507,7 @@ i915_gem_suspend(struct drm_device *dev)
 		i915_gem_evict_everything(dev);
 
 	i915_kernel_lost_context(dev);
-	i915_gem_stop_ringbuffers(dev);
+	i915_gem_cleanup_ringbuffer(dev);
 
 	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
 	 * We need to replace this with a semaphore, or something.