[ 161.470886] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 161.470887] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 161.470889] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 161.470891] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 161.470894] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 161.470899] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 161.470900] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 161.470902] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 161.470904] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 161.470905] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 161.470907] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 161.470909] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 161.470911] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 161.470913] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 161.470914] [drm:intel_dump_pipe_config] requested mode: [ 161.470917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 161.470918] [drm:intel_dump_pipe_config] adjusted mode: [ 161.470920] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 161.470923] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 161.470924] [drm:intel_dump_pipe_config] port clock: 270000 [ 161.470925] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 161.470927] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 161.470929] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 161.470930] [drm:intel_dump_pipe_config] ips: 1 [ 161.470931] [drm:intel_dump_pipe_config] double wide: 0 [ 161.470934] [drm:intel_display_power_get] enabling always-on [ 161.470946] [drm:intel_edp_panel_on] Turn eDP power on [ 161.470950] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 162.017133] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 162.017137] [drm:wait_panel_status] Wait complete [ 162.017140] [drm:wait_panel_on] Wait for panel power on [ 162.017144] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 162.226234] [drm:wait_panel_status] Wait complete [ 162.226240] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 162.226247] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 162.227304] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 162.227751] [drm:intel_dp_start_link_train] clock recovery OK [ 162.228499] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 162.228732] [drm:intel_edp_backlight_on] [ 162.228734] [drm:intel_panel_enable_backlight] pipe A [ 162.228740] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 162.228746] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 162.228750] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 162.263251] [drm:intel_update_fbc] disabled per chip default [ 162.263254] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 162.263257] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 162.263259] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 162.263260] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 162.263262] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 162.263263] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 162.263264] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 162.263266] [drm:check_crtc_state] [CRTC:8] [ 162.263272] [drm:check_crtc_state] [CRTC:12] [ 162.263273] [drm:check_crtc_state] [CRTC:16] [ 162.263275] [drm:check_shared_dpll_state] WRPLL 1 [ 162.263277] [drm:check_shared_dpll_state] WRPLL 2 [ 162.278737] [drm:drm_mode_setcrtc] [CRTC:8] [ 162.278740] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 162.278743] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 162.278746] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 162.278748] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 162.278750] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 162.278752] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 162.278755] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 162.295392] [drm:intel_edp_backlight_off] [ 162.496372] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 162.512530] [drm:intel_edp_panel_off] Turn eDP power off [ 162.512534] [drm:wait_panel_off] Wait for panel power off time [ 162.512537] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 162.567408] [drm:wait_panel_status] Wait complete [ 162.567414] [drm:intel_update_fbc] no output, disabling [ 162.567417] [drm:intel_display_power_put] disabling always-on [ 162.567420] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 162.567422] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 162.567424] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 162.567425] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 162.567426] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 162.567428] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 162.567429] [drm:check_crtc_state] [CRTC:8] [ 162.567431] [drm:check_crtc_state] [CRTC:12] [ 162.567432] [drm:check_crtc_state] [CRTC:16] [ 162.567434] [drm:check_shared_dpll_state] WRPLL 1 [ 162.567436] [drm:check_shared_dpll_state] WRPLL 2 [ 162.567440] [drm:drm_mode_setcrtc] [CRTC:8] [ 162.567442] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 162.567444] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 162.567446] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 162.567447] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 162.567449] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 162.567450] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 162.567452] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 162.567453] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 162.567455] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 162.567457] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 162.567459] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 162.567464] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 162.567466] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 162.567468] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 162.567469] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 162.567471] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 162.567472] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 162.567474] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 162.567476] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 162.567478] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 162.567479] [drm:intel_dump_pipe_config] requested mode: [ 162.567482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 162.567483] [drm:intel_dump_pipe_config] adjusted mode: [ 162.567485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 162.567488] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 162.567489] [drm:intel_dump_pipe_config] port clock: 270000 [ 162.567490] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 162.567492] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 162.567494] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 162.567495] [drm:intel_dump_pipe_config] ips: 1 [ 162.567496] [drm:intel_dump_pipe_config] double wide: 0 [ 162.567498] [drm:intel_display_power_get] enabling always-on [ 162.567510] [drm:intel_edp_panel_on] Turn eDP power on [ 162.567514] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 163.113700] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 163.124698] [drm:wait_panel_status] Wait complete [ 163.124702] [drm:wait_panel_on] Wait for panel power on [ 163.124706] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 163.333806] [drm:wait_panel_status] Wait complete [ 163.333813] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 163.333819] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 163.333972] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 163.333978] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 163.334584] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 163.334592] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 163.334897] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 163.335345] [drm:intel_dp_start_link_train] clock recovery OK [ 163.336093] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 163.336324] [drm:intel_edp_backlight_on] [ 163.336325] [drm:intel_panel_enable_backlight] pipe A [ 163.336332] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 163.336338] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 163.336342] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 163.370823] [drm:intel_update_fbc] disabled per chip default [ 163.370826] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 163.370829] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 163.370830] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 163.370832] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 163.370833] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 163.370835] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 163.370836] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 163.370837] [drm:check_crtc_state] [CRTC:8] [ 163.370843] [drm:check_crtc_state] [CRTC:12] [ 163.370845] [drm:check_crtc_state] [CRTC:16] [ 163.370847] [drm:check_shared_dpll_state] WRPLL 1 [ 163.370848] [drm:check_shared_dpll_state] WRPLL 2 [ 163.386329] [drm:drm_mode_setcrtc] [CRTC:8] [ 163.386332] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 163.386335] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 163.386338] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 163.386340] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 163.386342] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 163.386344] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 163.386346] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 163.402986] [drm:intel_edp_backlight_off] [ 163.603945] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 163.620102] [drm:intel_edp_panel_off] Turn eDP power off [ 163.620106] [drm:wait_panel_off] Wait for panel power off time [ 163.620109] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 163.674981] [drm:wait_panel_status] Wait complete [ 163.674987] [drm:intel_update_fbc] no output, disabling [ 163.674990] [drm:intel_display_power_put] disabling always-on [ 163.674993] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 163.674994] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 163.674996] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 163.674997] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 163.674998] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 163.675000] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 163.675001] [drm:check_crtc_state] [CRTC:8] [ 163.675003] [drm:check_crtc_state] [CRTC:12] [ 163.675005] [drm:check_crtc_state] [CRTC:16] [ 163.675006] [drm:check_shared_dpll_state] WRPLL 1 [ 163.675008] [drm:check_shared_dpll_state] WRPLL 2 [ 163.675012] [drm:drm_mode_setcrtc] [CRTC:8] [ 163.675014] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 163.675016] [drm:intel_crtc_set_config] [CRTC:8] [FB:39] #connectors=1 (x y) (0 0) [ 163.675018] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 163.675019] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 163.675021] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 163.675022] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 163.675024] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 163.675026] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 163.675027] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 163.675029] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 163.675032] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 163.675036] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 163.675038] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 163.675040] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 163.675041] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 163.675043] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 163.675044] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 163.675046] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 163.675048] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 163.675050] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 163.675051] [drm:intel_dump_pipe_config] requested mode: [ 163.675054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 163.675055] [drm:intel_dump_pipe_config] adjusted mode: [ 163.675057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 163.675060] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 163.675061] [drm:intel_dump_pipe_config] port clock: 270000 [ 163.675062] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 163.675064] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 163.675066] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 163.675067] [drm:intel_dump_pipe_config] ips: 1 [ 163.675068] [drm:intel_dump_pipe_config] double wide: 0 [ 163.675070] [drm:intel_display_power_get] enabling always-on [ 163.675082] [drm:intel_edp_panel_on] Turn eDP power on [ 163.675086] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 164.221269] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 164.221272] [drm:wait_panel_status] Wait complete [ 164.221275] [drm:wait_panel_on] Wait for panel power on [ 164.221279] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 164.430371] [drm:wait_panel_status] Wait complete [ 164.430374] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 164.430380] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 164.431434] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 164.431880] [drm:intel_dp_start_link_train] clock recovery OK [ 164.432628] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 164.432860] [drm:intel_edp_backlight_on] [ 164.432862] [drm:intel_panel_enable_backlight] pipe A [ 164.432868] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 164.432873] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 164.432877] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 164.467390] [drm:intel_update_fbc] disabled per chip default [ 164.467393] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 164.467396] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 164.467398] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 164.467400] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 164.467401] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 164.467402] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 164.467404] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 164.467405] [drm:check_crtc_state] [CRTC:8] [ 164.467411] [drm:check_crtc_state] [CRTC:12] [ 164.467413] [drm:check_crtc_state] [CRTC:16] [ 164.467415] [drm:check_shared_dpll_state] WRPLL 1 [ 164.467416] [drm:check_shared_dpll_state] WRPLL 2 [ 164.484231] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 164.484234] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 164.484236] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 164.484238] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 164.484239] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 164.484241] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 164.484243] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 164.499520] [drm:intel_edp_backlight_off] [ 164.700512] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 164.716669] [drm:intel_edp_panel_off] Turn eDP power off [ 164.716673] [drm:wait_panel_off] Wait for panel power off time [ 164.716678] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 164.771547] [drm:wait_panel_status] Wait complete [ 164.771553] [drm:intel_update_fbc] no output, disabling [ 164.771556] [drm:intel_display_power_put] disabling always-on [ 164.771560] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 164.771562] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 164.771563] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 164.771564] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 164.771566] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 164.771567] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 164.771569] [drm:check_crtc_state] [CRTC:8] [ 164.771570] [drm:check_crtc_state] [CRTC:12] [ 164.771572] [drm:check_crtc_state] [CRTC:16] [ 164.771574] [drm:check_shared_dpll_state] WRPLL 1 [ 164.771576] [drm:check_shared_dpll_state] WRPLL 2 [ 164.772911] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 164.772915] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 164.772918] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [ 164.772920] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] [ 164.772922] [drm:intel_dp_detect] [CONNECTOR:19:eDP-1] [ 164.772924] [drm:intel_display_power_get] enabling always-on [ 164.772926] [drm:intel_display_power_put] disabling always-on [ 164.772933] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 164.772936] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] probed modes : [ 164.772939] [drm:drm_mode_debug_printmodeline] Modeline 20:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 164.772941] [drm:drm_mode_debug_printmodeline] Modeline 21:"1920x1080" 40 92520 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa [ 164.772944] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [ 164.772975] [drm:add_framebuffer_internal] [FB:36] [ 164.772980] [drm:add_framebuffer_internal] [FB:39] [ 164.772985] [drm:add_framebuffer_internal] [FB:40] [ 164.813178] [drm:drm_mode_setcrtc] [CRTC:12] [ 164.813186] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 164.813190] [drm:intel_crtc_set_config] [CRTC:12] [FB:36] #connectors=1 (x y) (0 0) [ 164.813194] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 164.813197] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 164.813199] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 164.813202] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 164.813204] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 164.813207] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 164.813211] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 164.813214] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 164.813218] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 164.813226] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 164.813229] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 164.813232] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 164.813234] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 164.813236] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 164.813237] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 164.813239] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 164.813241] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 164.813243] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 164.813245] [drm:intel_dump_pipe_config] requested mode: [ 164.813247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 164.813249] [drm:intel_dump_pipe_config] adjusted mode: [ 164.813251] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 164.813254] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 164.813255] [drm:intel_dump_pipe_config] port clock: 270000 [ 164.813257] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 164.813258] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 164.813260] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 164.813261] [drm:intel_dump_pipe_config] ips: 0 [ 164.813263] [drm:intel_dump_pipe_config] double wide: 0 [ 164.813268] [drm:intel_display_power_get] enabling always-on [ 164.816710] [drm:intel_edp_panel_on] Turn eDP power on [ 164.816715] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 165.317840] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 165.328838] [drm:wait_panel_status] Wait complete [ 165.328843] [drm:wait_panel_on] Wait for panel power on [ 165.328847] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 165.537945] [drm:wait_panel_status] Wait complete [ 165.537952] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 165.537958] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 165.539023] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 165.539470] [drm:intel_dp_start_link_train] clock recovery OK [ 165.540220] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 165.540456] [drm:intel_edp_backlight_on] [ 165.540458] [drm:intel_panel_enable_backlight] pipe B [ 165.540465] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 165.540471] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 165.540477] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 165.557086] [drm:intel_update_fbc] disabled per chip default [ 165.557090] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 165.557093] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 165.557096] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 165.557098] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 165.557099] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 165.557101] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 165.557102] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 165.557104] [drm:check_crtc_state] [CRTC:8] [ 165.557106] [drm:check_crtc_state] [CRTC:12] [ 165.557114] [drm:check_crtc_state] [CRTC:16] [ 165.557116] [drm:check_shared_dpll_state] WRPLL 1 [ 165.557118] [drm:check_shared_dpll_state] WRPLL 2 [ 165.573785] [drm:drm_mode_setcrtc] [CRTC:12] [ 165.573787] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 165.573790] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 165.573791] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 165.573793] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 165.573794] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 165.573796] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 165.573798] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 165.573805] [drm:intel_edp_backlight_off] [ 165.774067] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 165.792224] [drm:intel_edp_panel_off] Turn eDP power off [ 165.792228] [drm:wait_panel_off] Wait for panel power off time [ 165.792233] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 165.847103] [drm:wait_panel_status] Wait complete [ 165.847109] [drm:intel_update_fbc] no output, disabling [ 165.847113] [drm:intel_display_power_put] disabling always-on [ 165.847116] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 165.847118] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 165.847119] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 165.847120] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 165.847122] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 165.847123] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 165.847125] [drm:check_crtc_state] [CRTC:8] [ 165.847126] [drm:check_crtc_state] [CRTC:12] [ 165.847128] [drm:check_crtc_state] [CRTC:16] [ 165.847130] [drm:check_shared_dpll_state] WRPLL 1 [ 165.847131] [drm:check_shared_dpll_state] WRPLL 2 [ 165.847136] [drm:drm_mode_setcrtc] [CRTC:12] [ 165.847138] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 165.847140] [drm:intel_crtc_set_config] [CRTC:12] [FB:36] #connectors=1 (x y) (0 0) [ 165.847142] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 165.847143] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 165.847145] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 165.847147] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 165.847148] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 165.847149] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 165.847152] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 165.847154] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 165.847156] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 165.847161] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 165.847162] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 165.847164] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 165.847166] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 165.847167] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 165.847169] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 165.847171] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 165.847173] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 165.847175] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 165.847176] [drm:intel_dump_pipe_config] requested mode: [ 165.847179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 165.847180] [drm:intel_dump_pipe_config] adjusted mode: [ 165.847182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 165.847185] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 165.847186] [drm:intel_dump_pipe_config] port clock: 270000 [ 165.847188] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 165.847189] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 165.847191] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 165.847192] [drm:intel_dump_pipe_config] ips: 0 [ 165.847193] [drm:intel_dump_pipe_config] double wide: 0 [ 165.847196] [drm:intel_display_power_get] enabling always-on [ 165.847208] [drm:intel_edp_panel_on] Turn eDP power on [ 165.847212] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 166.393388] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 166.426402] [drm:wait_panel_status] Wait complete [ 166.426406] [drm:wait_panel_on] Wait for panel power on [ 166.426409] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 166.635510] [drm:wait_panel_status] Wait complete [ 166.635517] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 166.635523] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 166.636579] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 166.637025] [drm:intel_dp_start_link_train] clock recovery OK [ 166.637773] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 166.638006] [drm:intel_edp_backlight_on] [ 166.638007] [drm:intel_panel_enable_backlight] pipe B [ 166.638014] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 166.638019] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 166.638023] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 166.654637] [drm:intel_update_fbc] disabled per chip default [ 166.654640] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 166.654643] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 166.654645] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 166.654647] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 166.654648] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 166.654649] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 166.654650] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 166.654653] [drm:check_crtc_state] [CRTC:8] [ 166.654655] [drm:check_crtc_state] [CRTC:12] [ 166.654660] [drm:check_crtc_state] [CRTC:16] [ 166.654662] [drm:check_shared_dpll_state] WRPLL 1 [ 166.654664] [drm:check_shared_dpll_state] WRPLL 2 [ 166.671339] [drm:drm_mode_setcrtc] [CRTC:12] [ 166.671342] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 166.671345] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 166.671347] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 166.671349] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 166.671352] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 166.671354] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 166.671357] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 166.671365] [drm:intel_edp_backlight_off] [ 166.871636] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 166.889794] [drm:intel_edp_panel_off] Turn eDP power off [ 166.889798] [drm:wait_panel_off] Wait for panel power off time [ 166.889801] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 166.944670] [drm:wait_panel_status] Wait complete [ 166.944676] [drm:intel_update_fbc] no output, disabling [ 166.944679] [drm:intel_display_power_put] disabling always-on [ 166.944682] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 166.944684] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 166.944686] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 166.944687] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 166.944688] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 166.944690] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 166.944691] [drm:check_crtc_state] [CRTC:8] [ 166.944693] [drm:check_crtc_state] [CRTC:12] [ 166.944695] [drm:check_crtc_state] [CRTC:16] [ 166.944696] [drm:check_shared_dpll_state] WRPLL 1 [ 166.944698] [drm:check_shared_dpll_state] WRPLL 2 [ 166.944702] [drm:drm_mode_setcrtc] [CRTC:12] [ 166.944705] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 166.944706] [drm:intel_crtc_set_config] [CRTC:12] [FB:39] #connectors=1 (x y) (0 0) [ 166.944708] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 166.944710] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 166.944711] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 166.944713] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 166.944714] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 166.944716] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 166.944718] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 166.944720] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 166.944722] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 166.944726] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 166.944728] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 166.944730] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 166.944732] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 166.944733] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 166.944734] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 166.944736] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 166.944738] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 166.944740] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 166.944742] [drm:intel_dump_pipe_config] requested mode: [ 166.944744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 166.944746] [drm:intel_dump_pipe_config] adjusted mode: [ 166.944748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 166.944750] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 166.944752] [drm:intel_dump_pipe_config] port clock: 270000 [ 166.944753] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 166.944755] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 166.944756] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 166.944758] [drm:intel_dump_pipe_config] ips: 0 [ 166.944759] [drm:intel_dump_pipe_config] double wide: 0 [ 166.944761] [drm:intel_display_power_get] enabling always-on [ 166.944773] [drm:intel_edp_panel_on] Turn eDP power on [ 166.944777] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 167.490958] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 167.523969] [drm:wait_panel_status] Wait complete [ 167.523973] [drm:wait_panel_on] Wait for panel power on [ 167.523976] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 167.733077] [drm:wait_panel_status] Wait complete [ 167.733080] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 167.733087] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 167.734143] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 167.734590] [drm:intel_dp_start_link_train] clock recovery OK [ 167.735337] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 167.735570] [drm:intel_edp_backlight_on] [ 167.735572] [drm:intel_panel_enable_backlight] pipe B [ 167.735578] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 167.735584] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 167.735587] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 167.752202] [drm:intel_update_fbc] disabled per chip default [ 167.752204] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 167.752207] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 167.752209] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 167.752211] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 167.752212] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 167.752213] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 167.752215] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 167.752217] [drm:check_crtc_state] [CRTC:8] [ 167.752219] [drm:check_crtc_state] [CRTC:12] [ 167.752225] [drm:check_crtc_state] [CRTC:16] [ 167.752227] [drm:check_shared_dpll_state] WRPLL 1 [ 167.752228] [drm:check_shared_dpll_state] WRPLL 2 [ 167.768901] [drm:drm_mode_setcrtc] [CRTC:12] [ 167.768904] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 167.768907] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 167.768910] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 167.768912] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 167.768914] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 167.768916] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 167.768918] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 167.768924] [drm:intel_edp_backlight_off] [ 167.969203] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 167.987359] [drm:intel_edp_panel_off] Turn eDP power off [ 167.987367] [drm:wait_panel_off] Wait for panel power off time [ 167.987371] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 168.042237] [drm:wait_panel_status] Wait complete [ 168.042244] [drm:intel_update_fbc] no output, disabling [ 168.042248] [drm:intel_display_power_put] disabling always-on [ 168.042252] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 168.042254] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 168.042256] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 168.042257] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 168.042258] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 168.042260] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 168.042261] [drm:check_crtc_state] [CRTC:8] [ 168.042263] [drm:check_crtc_state] [CRTC:12] [ 168.042269] [drm:check_crtc_state] [CRTC:16] [ 168.042271] [drm:check_shared_dpll_state] WRPLL 1 [ 168.042272] [drm:check_shared_dpll_state] WRPLL 2 [ 168.042278] [drm:drm_mode_setcrtc] [CRTC:12] [ 168.042281] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 168.042283] [drm:intel_crtc_set_config] [CRTC:12] [FB:36] #connectors=1 (x y) (0 0) [ 168.042285] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 168.042287] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 168.042288] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 168.042290] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 168.042292] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 168.042294] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 168.042296] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 168.042298] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 168.042301] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 168.042306] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 168.042307] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 168.042310] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 168.042311] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 168.042313] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 168.042314] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 168.042316] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 168.042318] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 168.042320] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 168.042322] [drm:intel_dump_pipe_config] requested mode: [ 168.042324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 168.042326] [drm:intel_dump_pipe_config] adjusted mode: [ 168.042328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 168.042331] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 168.042332] [drm:intel_dump_pipe_config] port clock: 270000 [ 168.042333] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 168.042335] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 168.042337] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 168.042338] [drm:intel_dump_pipe_config] ips: 0 [ 168.042340] [drm:intel_dump_pipe_config] double wide: 0 [ 168.042342] [drm:intel_display_power_get] enabling always-on [ 168.042356] [drm:intel_edp_panel_on] Turn eDP power on [ 168.042359] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 168.588526] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 168.621536] [drm:wait_panel_status] Wait complete [ 168.621540] [drm:wait_panel_on] Wait for panel power on [ 168.621543] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 168.830644] [drm:wait_panel_status] Wait complete [ 168.830648] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 168.830654] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 168.831714] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 168.832161] [drm:intel_dp_start_link_train] clock recovery OK [ 168.832913] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 168.833147] [drm:intel_edp_backlight_on] [ 168.833149] [drm:intel_panel_enable_backlight] pipe B [ 168.833155] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 168.833161] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 168.833165] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 168.849778] [drm:intel_update_fbc] disabled per chip default [ 168.849782] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 168.849785] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 168.849787] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 168.849788] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 168.849790] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 168.849791] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 168.849793] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 168.849795] [drm:check_crtc_state] [CRTC:8] [ 168.849796] [drm:check_crtc_state] [CRTC:12] [ 168.849802] [drm:check_crtc_state] [CRTC:16] [ 168.849805] [drm:check_shared_dpll_state] WRPLL 1 [ 168.849806] [drm:check_shared_dpll_state] WRPLL 2 [ 168.866476] [drm:drm_mode_setcrtc] [CRTC:12] [ 168.866479] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 168.866482] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 168.866485] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 168.866487] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 168.866490] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 168.866492] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 168.866495] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 168.866503] [drm:intel_edp_backlight_off] [ 169.066769] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 169.084925] [drm:intel_edp_panel_off] Turn eDP power off [ 169.084930] [drm:wait_panel_off] Wait for panel power off time [ 169.084933] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 169.139804] [drm:wait_panel_status] Wait complete [ 169.139811] [drm:intel_update_fbc] no output, disabling [ 169.139814] [drm:intel_display_power_put] disabling always-on [ 169.139817] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 169.139819] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 169.139821] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 169.139822] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 169.139823] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 169.139824] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 169.139826] [drm:check_crtc_state] [CRTC:8] [ 169.139828] [drm:check_crtc_state] [CRTC:12] [ 169.139830] [drm:check_crtc_state] [CRTC:16] [ 169.139832] [drm:check_shared_dpll_state] WRPLL 1 [ 169.139834] [drm:check_shared_dpll_state] WRPLL 2 [ 169.139838] [drm:drm_mode_setcrtc] [CRTC:12] [ 169.139841] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 169.139843] [drm:intel_crtc_set_config] [CRTC:12] [FB:39] #connectors=1 (x y) (0 0) [ 169.139844] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 169.139846] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 169.139848] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 169.139850] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:12] [ 169.139851] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 169.139853] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 169.139855] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0 [ 169.139857] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 169.139859] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 169.139864] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 169.139866] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 169.139868] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 169.139869] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B [ 169.139871] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 169.139872] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 169.139874] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 169.139876] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 169.139878] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 169.139879] [drm:intel_dump_pipe_config] requested mode: [ 169.139882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 169.139883] [drm:intel_dump_pipe_config] adjusted mode: [ 169.139886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 169.139888] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 169.139890] [drm:intel_dump_pipe_config] port clock: 270000 [ 169.139891] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 169.139893] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 169.139895] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 169.139896] [drm:intel_dump_pipe_config] ips: 0 [ 169.139897] [drm:intel_dump_pipe_config] double wide: 0 [ 169.139900] [drm:intel_display_power_get] enabling always-on [ 169.139912] [drm:intel_edp_panel_on] Turn eDP power on [ 169.139916] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 169.686089] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 169.730109] [drm:wait_panel_status] Wait complete [ 169.730113] [drm:wait_panel_on] Wait for panel power on [ 169.730116] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 169.939217] [drm:wait_panel_status] Wait complete [ 169.939224] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 169.939230] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 169.940287] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 169.940734] [drm:intel_dp_start_link_train] clock recovery OK [ 169.941483] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 169.941717] [drm:intel_edp_backlight_on] [ 169.941718] [drm:intel_panel_enable_backlight] pipe B [ 169.941725] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 169.941730] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 169.941734] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 169.958349] [drm:intel_update_fbc] disabled per chip default [ 169.958352] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 169.958355] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 169.958357] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 169.958359] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 169.958361] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 169.958362] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 169.958363] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 169.958365] [drm:check_crtc_state] [CRTC:8] [ 169.958367] [drm:check_crtc_state] [CRTC:12] [ 169.958373] [drm:check_crtc_state] [CRTC:16] [ 169.958375] [drm:check_shared_dpll_state] WRPLL 1 [ 169.958377] [drm:check_shared_dpll_state] WRPLL 2 [ 169.976403] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 169.976406] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=0 [ 169.976408] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 169.976410] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 169.976411] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 169.976413] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 169.976415] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2 [ 169.976421] [drm:intel_edp_backlight_off] [ 170.177342] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 170.193498] [drm:intel_edp_panel_off] Turn eDP power off [ 170.193503] [drm:wait_panel_off] Wait for panel power off time [ 170.193507] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 170.248377] [drm:wait_panel_status] Wait complete [ 170.248383] [drm:intel_update_fbc] no output, disabling [ 170.248387] [drm:intel_display_power_put] disabling always-on [ 170.248390] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 170.248392] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 170.248394] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 170.248395] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 170.248396] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 170.248397] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 170.248399] [drm:check_crtc_state] [CRTC:8] [ 170.248401] [drm:check_crtc_state] [CRTC:12] [ 170.248403] [drm:check_crtc_state] [CRTC:16] [ 170.248405] [drm:check_shared_dpll_state] WRPLL 1 [ 170.248407] [drm:check_shared_dpll_state] WRPLL 2 [ 170.249822] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 170.249825] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 170.249829] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [ 170.249831] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] [ 170.249832] [drm:intel_dp_detect] [CONNECTOR:19:eDP-1] [ 170.249834] [drm:intel_display_power_get] enabling always-on [ 170.249836] [drm:intel_display_power_put] disabling always-on [ 170.249843] [drm:drm_edid_to_eld] ELD: no CEA Extension found [ 170.249846] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] probed modes : [ 170.249849] [drm:drm_mode_debug_printmodeline] Modeline 20:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 170.249851] [drm:drm_mode_debug_printmodeline] Modeline 21:"1920x1080" 40 92520 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa [ 170.249854] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [ 170.249886] [drm:add_framebuffer_internal] [FB:36] [ 170.249890] [drm:add_framebuffer_internal] [FB:39] [ 170.249896] [drm:add_framebuffer_internal] [FB:40] [ 170.290108] [drm:drm_mode_setcrtc] [CRTC:16] [ 170.290115] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 170.290120] [drm:intel_crtc_set_config] [CRTC:16] [FB:36] #connectors=1 (x y) (0 0) [ 170.290123] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 170.290126] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 170.290129] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 170.290132] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:16] [ 170.290134] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 170.290137] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 170.290140] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0 [ 170.290144] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 170.290149] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 170.290156] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 170.290158] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 170.290162] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 170.290165] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C [ 170.290167] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 170.290168] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 170.290171] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 170.290173] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 170.290175] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 170.290176] [drm:intel_dump_pipe_config] requested mode: [ 170.290179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 170.290180] [drm:intel_dump_pipe_config] adjusted mode: [ 170.290183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 170.290185] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 170.290187] [drm:intel_dump_pipe_config] port clock: 270000 [ 170.290188] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 170.290190] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 170.290192] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 170.290193] [drm:intel_dump_pipe_config] ips: 0 [ 170.290194] [drm:intel_dump_pipe_config] double wide: 0 [ 170.290199] [drm:intel_display_power_get] enabling always-on [ 170.293651] [drm:intel_edp_panel_on] Turn eDP power on [ 170.293656] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 170.794665] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 170.827676] [drm:wait_panel_status] Wait complete [ 170.827680] [drm:wait_panel_on] Wait for panel power on [ 170.827684] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 171.036786] [drm:wait_panel_status] Wait complete [ 171.036793] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 171.036800] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 171.037868] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 171.038315] [drm:intel_dp_start_link_train] clock recovery OK [ 171.039066] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 171.039300] [drm:intel_edp_backlight_on] [ 171.039302] [drm:intel_panel_enable_backlight] pipe C [ 171.039310] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 171.039316] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 171.039322] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 171.055932] [drm:intel_update_fbc] disabled per chip default [ 171.055936] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 171.055940] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 171.055943] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 171.055946] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 171.055948] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 171.055949] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 171.055950] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 171.055952] [drm:check_crtc_state] [CRTC:8] [ 171.055954] [drm:check_crtc_state] [CRTC:12] [ 171.055956] [drm:check_crtc_state] [CRTC:16] [ 171.055963] [drm:check_shared_dpll_state] WRPLL 1 [ 171.055965] [drm:check_shared_dpll_state] WRPLL 2 [ 171.072633] [drm:drm_mode_setcrtc] [CRTC:16] [ 171.072635] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 171.072638] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 171.072640] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 171.072641] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 171.072643] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 171.072644] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 171.072647] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4 [ 171.072653] [drm:intel_edp_backlight_off] [ 171.272910] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 171.291064] [drm:intel_edp_panel_off] Turn eDP power off [ 171.291070] [drm:wait_panel_off] Wait for panel power off time [ 171.291073] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 171.345944] [drm:wait_panel_status] Wait complete [ 171.345951] [drm:intel_update_fbc] no output, disabling [ 171.345954] [drm:intel_display_power_put] disabling always-on [ 171.345958] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 171.345959] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 171.345961] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 171.345962] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 171.345963] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 171.345965] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 171.345966] [drm:check_crtc_state] [CRTC:8] [ 171.345968] [drm:check_crtc_state] [CRTC:12] [ 171.345970] [drm:check_crtc_state] [CRTC:16] [ 171.345972] [drm:check_shared_dpll_state] WRPLL 1 [ 171.345974] [drm:check_shared_dpll_state] WRPLL 2 [ 171.345978] [drm:drm_mode_setcrtc] [CRTC:16] [ 171.345981] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 171.345983] [drm:intel_crtc_set_config] [CRTC:16] [FB:36] #connectors=1 (x y) (0 0) [ 171.345985] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 171.345986] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 171.345988] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 171.345990] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:16] [ 171.345991] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 171.345993] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 171.345995] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0 [ 171.345997] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 171.345999] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 171.346004] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 171.346006] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 171.346008] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 171.346010] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C [ 171.346011] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 171.346012] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 171.346014] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 171.346017] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 171.346019] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 171.346020] [drm:intel_dump_pipe_config] requested mode: [ 171.346023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 171.346024] [drm:intel_dump_pipe_config] adjusted mode: [ 171.346026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 171.346029] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 171.346030] [drm:intel_dump_pipe_config] port clock: 270000 [ 171.346032] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 171.346034] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 171.346035] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 171.346036] [drm:intel_dump_pipe_config] ips: 0 [ 171.346038] [drm:intel_dump_pipe_config] double wide: 0 [ 171.346040] [drm:intel_display_power_get] enabling always-on [ 171.346053] [drm:intel_edp_panel_on] Turn eDP power on [ 171.346056] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 171.892235] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 171.925243] [drm:wait_panel_status] Wait complete [ 171.925247] [drm:wait_panel_on] Wait for panel power on [ 171.925250] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 172.134351] [drm:wait_panel_status] Wait complete [ 172.134354] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 172.134361] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 172.135421] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 172.135868] [drm:intel_dp_start_link_train] clock recovery OK [ 172.136618] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 172.136851] [drm:intel_edp_backlight_on] [ 172.136853] [drm:intel_panel_enable_backlight] pipe C [ 172.136860] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 172.136865] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 172.136869] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 172.153483] [drm:intel_update_fbc] disabled per chip default [ 172.153486] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 172.153489] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 172.153491] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 172.153493] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 172.153494] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 172.153496] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 172.153497] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 172.153499] [drm:check_crtc_state] [CRTC:8] [ 172.153501] [drm:check_crtc_state] [CRTC:12] [ 172.153503] [drm:check_crtc_state] [CRTC:16] [ 172.153509] [drm:check_shared_dpll_state] WRPLL 1 [ 172.153510] [drm:check_shared_dpll_state] WRPLL 2 [ 172.170187] [drm:drm_mode_setcrtc] [CRTC:16] [ 172.170189] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 172.170193] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 172.170195] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 172.170197] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 172.170200] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 172.170202] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 172.170205] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4 [ 172.170214] [drm:intel_edp_backlight_off] [ 172.370476] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 172.388631] [drm:intel_edp_panel_off] Turn eDP power off [ 172.388636] [drm:wait_panel_off] Wait for panel power off time [ 172.388639] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 172.443511] [drm:wait_panel_status] Wait complete [ 172.443517] [drm:intel_update_fbc] no output, disabling [ 172.443520] [drm:intel_display_power_put] disabling always-on [ 172.443523] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 172.443525] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 172.443527] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 172.443528] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 172.443529] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 172.443530] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 172.443532] [drm:check_crtc_state] [CRTC:8] [ 172.443534] [drm:check_crtc_state] [CRTC:12] [ 172.443536] [drm:check_crtc_state] [CRTC:16] [ 172.443538] [drm:check_shared_dpll_state] WRPLL 1 [ 172.443540] [drm:check_shared_dpll_state] WRPLL 2 [ 172.443544] [drm:drm_mode_setcrtc] [CRTC:16] [ 172.443546] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 172.443549] [drm:intel_crtc_set_config] [CRTC:16] [FB:39] #connectors=1 (x y) (0 0) [ 172.443550] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 172.443552] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 172.443553] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 172.443555] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:16] [ 172.443557] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 172.443558] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 172.443560] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0 [ 172.443562] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 172.443565] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 172.443570] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 172.443571] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 172.443573] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 172.443575] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C [ 172.443576] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 172.443578] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 172.443580] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 172.443582] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 172.443584] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 172.443585] [drm:intel_dump_pipe_config] requested mode: [ 172.443588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 172.443589] [drm:intel_dump_pipe_config] adjusted mode: [ 172.443591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 172.443594] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 172.443595] [drm:intel_dump_pipe_config] port clock: 270000 [ 172.443597] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 172.443598] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 172.443600] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 172.443601] [drm:intel_dump_pipe_config] ips: 0 [ 172.443603] [drm:intel_dump_pipe_config] double wide: 0 [ 172.443605] [drm:intel_display_power_get] enabling always-on [ 172.443618] [drm:intel_edp_panel_on] Turn eDP power on [ 172.443621] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 172.989796] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 173.022810] [drm:wait_panel_status] Wait complete [ 173.022814] [drm:wait_panel_on] Wait for panel power on [ 173.022817] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 173.231918] [drm:wait_panel_status] Wait complete [ 173.231925] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 173.231931] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 173.232985] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 173.233432] [drm:intel_dp_start_link_train] clock recovery OK [ 173.234180] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 173.234412] [drm:intel_edp_backlight_on] [ 173.234414] [drm:intel_panel_enable_backlight] pipe C [ 173.234421] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 173.234426] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 173.234430] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 173.251044] [drm:intel_update_fbc] disabled per chip default [ 173.251047] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 173.251050] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 173.251052] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 173.251054] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 173.251055] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 173.251057] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 173.251058] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 173.251060] [drm:check_crtc_state] [CRTC:8] [ 173.251062] [drm:check_crtc_state] [CRTC:12] [ 173.251064] [drm:check_crtc_state] [CRTC:16] [ 173.251070] [drm:check_shared_dpll_state] WRPLL 1 [ 173.251071] [drm:check_shared_dpll_state] WRPLL 2 [ 173.267743] [drm:drm_mode_setcrtc] [CRTC:16] [ 173.267746] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 173.267749] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 173.267752] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 173.267754] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 173.267757] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 173.267759] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 173.267762] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4 [ 173.267769] [drm:intel_edp_backlight_off] [ 173.468041] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 173.486197] [drm:intel_edp_panel_off] Turn eDP power off [ 173.486202] [drm:wait_panel_off] Wait for panel power off time [ 173.486205] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 173.541078] [drm:wait_panel_status] Wait complete [ 173.541084] [drm:intel_update_fbc] no output, disabling [ 173.541087] [drm:intel_display_power_put] disabling always-on [ 173.541090] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 173.541091] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 173.541093] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 173.541094] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 173.541095] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 173.541097] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 173.541098] [drm:check_crtc_state] [CRTC:8] [ 173.541100] [drm:check_crtc_state] [CRTC:12] [ 173.541102] [drm:check_crtc_state] [CRTC:16] [ 173.541104] [drm:check_shared_dpll_state] WRPLL 1 [ 173.541106] [drm:check_shared_dpll_state] WRPLL 2 [ 173.541110] [drm:drm_mode_setcrtc] [CRTC:16] [ 173.541112] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 173.541114] [drm:intel_crtc_set_config] [CRTC:16] [FB:36] #connectors=1 (x y) (0 0) [ 173.541116] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 173.541117] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 173.541119] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 173.541120] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:16] [ 173.541122] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 173.541123] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 173.541125] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0 [ 173.541127] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 173.541130] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 173.541134] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 173.541136] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 173.541138] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 173.541139] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C [ 173.541141] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 173.541142] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 173.541144] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 173.541146] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 173.541148] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 173.541150] [drm:intel_dump_pipe_config] requested mode: [ 173.541152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 173.541153] [drm:intel_dump_pipe_config] adjusted mode: [ 173.541156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 173.541158] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 173.541159] [drm:intel_dump_pipe_config] port clock: 270000 [ 173.541161] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 173.541163] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 173.541164] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 173.541166] [drm:intel_dump_pipe_config] ips: 0 [ 173.541167] [drm:intel_dump_pipe_config] double wide: 0 [ 173.541169] [drm:intel_display_power_get] enabling always-on [ 173.541181] [drm:intel_edp_panel_on] Turn eDP power on [ 173.541185] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 174.087369] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 174.131386] [drm:wait_panel_status] Wait complete [ 174.131391] [drm:wait_panel_on] Wait for panel power on [ 174.131395] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 174.340491] [drm:wait_panel_status] Wait complete [ 174.340495] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 174.340502] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 174.341560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 174.342006] [drm:intel_dp_start_link_train] clock recovery OK [ 174.342754] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 174.342987] [drm:intel_edp_backlight_on] [ 174.342989] [drm:intel_panel_enable_backlight] pipe C [ 174.342995] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 174.343001] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 174.343004] [drm:ironlake_update_primary_plane] Writing base 0107D000 00000000 0 0 7680 [ 174.359619] [drm:intel_update_fbc] disabled per chip default [ 174.359622] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 174.359624] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 174.359626] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 174.359628] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 174.359629] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 174.359630] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 174.359632] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 174.359634] [drm:check_crtc_state] [CRTC:8] [ 174.359636] [drm:check_crtc_state] [CRTC:12] [ 174.359638] [drm:check_crtc_state] [CRTC:16] [ 174.359644] [drm:check_shared_dpll_state] WRPLL 1 [ 174.359645] [drm:check_shared_dpll_state] WRPLL 2 [ 174.376317] [drm:drm_mode_setcrtc] [CRTC:16] [ 174.376320] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 174.376323] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 174.376326] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 174.376328] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 174.376330] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 174.376332] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 174.376335] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4 [ 174.376342] [drm:intel_edp_backlight_off] [ 174.576614] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 174.594770] [drm:intel_edp_panel_off] Turn eDP power off [ 174.594774] [drm:wait_panel_off] Wait for panel power off time [ 174.594778] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 174.649650] [drm:wait_panel_status] Wait complete [ 174.649656] [drm:intel_update_fbc] no output, disabling [ 174.649659] [drm:intel_display_power_put] disabling always-on [ 174.649662] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 174.649664] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 174.649665] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 174.649667] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 174.649668] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 174.649669] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 174.649671] [drm:check_crtc_state] [CRTC:8] [ 174.649672] [drm:check_crtc_state] [CRTC:12] [ 174.649674] [drm:check_crtc_state] [CRTC:16] [ 174.649676] [drm:check_shared_dpll_state] WRPLL 1 [ 174.649678] [drm:check_shared_dpll_state] WRPLL 2 [ 174.649681] [drm:drm_mode_setcrtc] [CRTC:16] [ 174.649684] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 174.649686] [drm:intel_crtc_set_config] [CRTC:16] [FB:39] #connectors=1 (x y) (0 0) [ 174.649687] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 174.649689] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 174.649691] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 174.649692] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:16] [ 174.649694] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 174.649695] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 174.649697] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0 [ 174.649699] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 174.649701] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 174.649706] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 174.649707] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 174.649709] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 174.649711] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C [ 174.649712] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 174.649714] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 174.649716] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 174.649718] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 174.649719] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 174.649721] [drm:intel_dump_pipe_config] requested mode: [ 174.649723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 174.649725] [drm:intel_dump_pipe_config] adjusted mode: [ 174.649727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 174.649729] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 174.649731] [drm:intel_dump_pipe_config] port clock: 270000 [ 174.649732] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 174.649734] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 174.649735] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 174.649737] [drm:intel_dump_pipe_config] ips: 0 [ 174.649738] [drm:intel_dump_pipe_config] double wide: 0 [ 174.649740] [drm:intel_display_power_get] enabling always-on [ 174.649752] [drm:intel_edp_panel_on] Turn eDP power on [ 174.649756] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 175.195939] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 175.228950] [drm:wait_panel_status] Wait complete [ 175.228953] [drm:wait_panel_on] Wait for panel power on [ 175.228957] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 175.438057] [drm:wait_panel_status] Wait complete [ 175.438061] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 175.438067] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 175.439121] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 175.439568] [drm:intel_dp_start_link_train] clock recovery OK [ 175.440316] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 175.440548] [drm:intel_edp_backlight_on] [ 175.440550] [drm:intel_panel_enable_backlight] pipe C [ 175.440556] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 175.440562] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 175.440565] [drm:ironlake_update_primary_plane] Writing base 01866000 00000000 0 0 7680 [ 175.457180] [drm:intel_update_fbc] disabled per chip default [ 175.457183] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 175.457185] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 175.457187] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 175.457189] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 175.457190] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 175.457191] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 175.457193] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 175.457195] [drm:check_crtc_state] [CRTC:8] [ 175.457198] [drm:check_crtc_state] [CRTC:12] [ 175.457199] [drm:check_crtc_state] [CRTC:16] [ 175.457205] [drm:check_shared_dpll_state] WRPLL 1 [ 175.457207] [drm:check_shared_dpll_state] WRPLL 2 [ 175.475236] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 175.475239] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=0 [ 175.475241] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 175.475243] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 175.475244] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 175.475246] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 175.475248] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4 [ 175.475253] [drm:intel_edp_backlight_off] [ 175.676182] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 175.692338] [drm:intel_edp_panel_off] Turn eDP power off [ 175.692342] [drm:wait_panel_off] Wait for panel power off time [ 175.692346] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 175.747217] [drm:wait_panel_status] Wait complete [ 175.747223] [drm:intel_update_fbc] no output, disabling [ 175.747227] [drm:intel_display_power_put] disabling always-on [ 175.747230] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 175.747232] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 175.747233] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 175.747234] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 175.747236] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 175.747237] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 175.747239] [drm:check_crtc_state] [CRTC:8] [ 175.747240] [drm:check_crtc_state] [CRTC:12] [ 175.747242] [drm:check_crtc_state] [CRTC:16] [ 175.747244] [drm:check_shared_dpll_state] WRPLL 1 [ 175.747245] [drm:check_shared_dpll_state] WRPLL 2 [ 175.748588] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748591] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748596] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748598] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748599] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748601] [drm:intel_display_power_get] enabling always-on [ 175.748605] [drm:intel_display_power_put] disabling always-on [ 175.748607] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748609] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748611] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748612] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748613] [drm:intel_display_power_get] enabling always-on [ 175.748616] [drm:intel_display_power_put] disabling always-on [ 175.748617] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748624] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748627] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748629] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748630] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748632] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748633] [drm:intel_display_power_get] enabling always-on [ 175.748636] [drm:intel_display_power_put] disabling always-on [ 175.748638] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748640] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748641] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748642] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748644] [drm:intel_display_power_get] enabling always-on [ 175.748647] [drm:intel_display_power_put] disabling always-on [ 175.748649] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748652] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748655] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748657] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748658] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748660] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748661] [drm:intel_display_power_get] enabling always-on [ 175.748665] [drm:intel_display_power_put] disabling always-on [ 175.748666] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748668] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [ 175.748669] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [ 175.748670] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [ 175.748672] [drm:intel_display_power_get] enabling always-on [ 175.748675] [drm:intel_display_power_put] disabling always-on [ 175.748677] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [ 175.748680] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748683] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.748685] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.748687] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.748688] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.748690] [drm:intel_display_power_get] enabling always-on [ 175.748849] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.748850] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.748852] [drm:intel_display_power_put] disabling always-on [ 175.748853] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.748855] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.748857] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.748858] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.748859] [drm:intel_display_power_get] enabling always-on [ 175.749013] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.749015] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.749016] [drm:intel_display_power_put] disabling always-on [ 175.749018] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.749022] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749024] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749026] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.749028] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.749029] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.749031] [drm:intel_display_power_get] enabling always-on [ 175.749186] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.749187] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.749189] [drm:intel_display_power_put] disabling always-on [ 175.749190] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.749192] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.749193] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.749195] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.749196] [drm:intel_display_power_get] enabling always-on [ 175.749356] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.749362] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.749370] [drm:intel_display_power_put] disabling always-on [ 175.749374] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.749388] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749393] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749399] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.749402] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.749405] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.749409] [drm:intel_display_power_get] enabling always-on [ 175.749567] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.749569] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.749570] [drm:intel_display_power_put] disabling always-on [ 175.749572] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.749575] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [ 175.749576] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [ 175.749577] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [ 175.749579] [drm:intel_display_power_get] enabling always-on [ 175.749734] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [ 175.749736] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [ 175.749737] [drm:intel_display_power_put] disabling always-on [ 175.749738] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [ 175.749744] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749746] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.749748] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.749750] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.749751] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.749752] [drm:intel_display_power_get] enabling always-on [ 175.749910] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.749912] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.749913] [drm:intel_display_power_put] disabling always-on [ 175.749914] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.749916] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.749918] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.749919] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.749920] [drm:intel_display_power_get] enabling always-on [ 175.750078] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.750079] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.750081] [drm:intel_display_power_put] disabling always-on [ 175.750082] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.750086] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.750088] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.750090] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.750092] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.750093] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.750095] [drm:intel_display_power_get] enabling always-on [ 175.750251] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.750254] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.750256] [drm:intel_display_power_put] disabling always-on [ 175.750259] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.750263] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.750265] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.750267] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.750270] [drm:intel_display_power_get] enabling always-on [ 175.750429] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.750431] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.750432] [drm:intel_display_power_put] disabling always-on [ 175.750434] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.750439] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.750442] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [ 175.750444] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.750445] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.750447] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.750448] [drm:intel_display_power_get] enabling always-on [ 175.750606] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.750607] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.750609] [drm:intel_display_power_put] disabling always-on [ 175.750610] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.750612] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [ 175.750613] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [ 175.750615] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [ 175.750616] [drm:intel_display_power_get] enabling always-on [ 175.750772] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [ 175.750774] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [ 175.750775] [drm:intel_display_power_put] disabling always-on [ 175.750776] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [ 175.751490] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [ 175.751492] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 175.751493] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 175.751494] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 175.751495] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 175.751496] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 175.751497] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 175.751499] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 175.751500] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 175.751502] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 175.751507] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 175.751508] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 175.751510] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 175.751511] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 175.751512] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 175.751512] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 175.751514] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 175.751516] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 175.751517] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 175.751517] [drm:intel_dump_pipe_config] requested mode: [ 175.751520] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 175.751520] [drm:intel_dump_pipe_config] adjusted mode: [ 175.751522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 175.751524] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 175.751524] [drm:intel_dump_pipe_config] port clock: 270000 [ 175.751525] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 175.751526] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 175.751527] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 175.751528] [drm:intel_dump_pipe_config] ips: 1 [ 175.751529] [drm:intel_dump_pipe_config] double wide: 0 [ 175.751531] [drm:intel_display_power_get] enabling always-on [ 175.751545] [drm:intel_edp_panel_on] Turn eDP power on [ 175.751548] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 176.293503] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 176.326517] [drm:wait_panel_status] Wait complete [ 176.326520] [drm:wait_panel_on] Wait for panel power on [ 176.326522] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 176.535624] [drm:wait_panel_status] Wait complete [ 176.535631] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 176.535636] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 176.536693] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 176.537139] [drm:intel_dp_start_link_train] clock recovery OK [ 176.537887] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 176.538121] [drm:intel_edp_backlight_on] [ 176.538122] [drm:intel_panel_enable_backlight] pipe A [ 176.538128] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 176.538133] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 176.538138] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 7680 [ 176.572644] [drm:intel_update_fbc] disabled per chip default [ 176.572647] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 176.572649] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 176.572652] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 176.572653] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 176.572653] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 176.572654] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 176.572655] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 176.572656] [drm:check_crtc_state] [CRTC:8] [ 176.572662] [drm:check_crtc_state] [CRTC:12] [ 176.572663] [drm:check_crtc_state] [CRTC:16] [ 176.572664] [drm:check_shared_dpll_state] WRPLL 1 [ 176.572665] [drm:check_shared_dpll_state] WRPLL 2 [ 176.572668] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 176.572670] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 176.572671] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 176.572672] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 176.572673] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 176.572674] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 176.581517] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [ 176.581523] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 176.581526] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 176.581530] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 176.581533] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 176.581536] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 176.581538] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 176.581541] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 176.581544] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 179.538185] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 179.538195] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 777.637786] [drm:intel_edp_backlight_off] [ 777.838267] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 777.856279] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 777.856287] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 777.856437] [drm:intel_edp_panel_off] Turn eDP power off [ 777.856440] [drm:wait_panel_off] Wait for panel power off time [ 777.856443] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 777.911304] [drm:wait_panel_status] Wait complete [ 777.911312] [drm:intel_update_fbc] no output, disabling [ 777.911313] [drm:intel_display_power_put] disabling always-on [ 777.911317] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 777.911318] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 777.911319] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 777.911320] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 777.911321] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 777.911321] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 777.911322] [drm:check_crtc_state] [CRTC:8] [ 777.911324] [drm:check_crtc_state] [CRTC:12] [ 777.911325] [drm:check_crtc_state] [CRTC:16] [ 777.911327] [drm:check_shared_dpll_state] WRPLL 1 [ 777.911328] [drm:check_shared_dpll_state] WRPLL 2 [ 780.864830] [drm:intel_display_power_get] enabling always-on [ 780.864834] [drm:intel_display_power_put] disabling always-on [10660.783090] [drm:i915_gem_open] [10660.783133] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [10660.783137] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [10660.783139] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10660.783143] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [10660.783145] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [10660.783148] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [10660.783154] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [10660.783155] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [10660.783158] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [10660.783160] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [10660.783161] [drm:intel_dump_pipe_config] cpu_transcoder: D [10660.783163] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [10660.783165] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [10660.783167] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [10660.783169] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [10660.783170] [drm:intel_dump_pipe_config] requested mode: [10660.783173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [10660.783175] [drm:intel_dump_pipe_config] adjusted mode: [10660.783177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [10660.783180] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [10660.783181] [drm:intel_dump_pipe_config] port clock: 270000 [10660.783183] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [10660.783184] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [10660.783186] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [10660.783188] [drm:intel_dump_pipe_config] ips: 1 [10660.783189] [drm:intel_dump_pipe_config] double wide: 0 [10660.783192] [drm:intel_display_power_get] enabling always-on [10660.783210] [drm:intel_edp_panel_on] Turn eDP power on [10660.783214] [drm:wait_panel_power_cycle] Wait for panel power cycle [10660.783217] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [10660.783219] [drm:wait_panel_status] Wait complete [10660.783223] [drm:wait_panel_on] Wait for panel power on [10660.783226] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [10660.992048] [drm:wait_panel_status] Wait complete [10660.992053] [drm:edp_panel_vdd_on] Turning eDP VDD on [10660.992059] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [10660.993125] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [10660.993575] [drm:intel_dp_start_link_train] clock recovery OK [10660.994327] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [10660.994561] [drm:intel_edp_backlight_on] [10660.994563] [drm:intel_panel_enable_backlight] pipe A [10660.994572] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [10660.994578] [drm:intel_edp_psr_enable] PSR not supported by this panel [10660.994584] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 7680 [10661.029067] [drm:intel_update_fbc] disabled per chip default [10661.029071] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [10661.029075] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [10661.029077] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [10661.029079] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [10661.029080] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [10661.029081] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [10661.029083] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [10661.029088] [drm:check_crtc_state] [CRTC:8] [10661.029096] [drm:check_crtc_state] [CRTC:12] [10661.029098] [drm:check_crtc_state] [CRTC:16] [10661.029100] [drm:check_shared_dpll_state] WRPLL 1 [10661.029102] [drm:check_shared_dpll_state] WRPLL 2 [10661.029104] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [10661.029107] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [10661.029108] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10661.029111] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [10661.029112] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [10661.029114] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10661.036017] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [10661.036020] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [10661.036022] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10661.043884] [drm:i915_gem_open] [10661.043901] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [10661.045800] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [10661.045809] [drm:drm_mode_addfb] [FB:36] [10661.045950] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [10661.045954] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6] [10661.046025] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [10661.046035] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [10661.046200] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [10661.046206] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [10661.046229] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [10661.046233] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [10661.046256] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [10661.046259] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [10661.081103] [drm:drm_mode_addfb] [FB:36] [10661.081306] [drm:drm_mode_setcrtc] [CRTC:8] [10661.081310] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [10661.081312] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [10661.081316] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1 [10661.081318] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10661.093411] [drm:ironlake_update_primary_plane] Writing base 01090000 00000000 0 0 7680 [10661.094585] [drm:drm_mode_setcrtc] [CRTC:12] [10661.094587] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [10661.094589] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [10661.094591] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10661.094595] [drm:drm_mode_setcrtc] [CRTC:16] [10661.094597] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [10661.094598] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [10661.094600] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10663.994605] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [10663.994618] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [10690.231527] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [10690.231531] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] [10690.231534] [drm:intel_dp_detect] [CONNECTOR:19:eDP-1] [10690.231545] [drm:drm_edid_to_eld] ELD: no CEA Extension found [10690.231549] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] probed modes : [10690.231552] [drm:drm_mode_debug_printmodeline] Modeline 20:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [10690.231555] [drm:drm_mode_debug_printmodeline] Modeline 21:"1920x1080" 40 92520 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa [10690.231558] [drm:drm_mode_getconnector] [CONNECTOR:19:?] [10690.231739] [drm:drm_mode_getconnector] [CONNECTOR:28:?] [10690.231741] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] [10690.231742] [drm:intel_dp_detect] [CONNECTOR:28:DP-1] [10690.231748] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] disconnected [10690.231752] [drm:drm_mode_getconnector] [CONNECTOR:32:?] [10690.231753] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] [10690.231755] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1] [10690.231913] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1) [10690.231915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [10690.231917] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected [10690.231920] [drm:drm_mode_getconnector] [CONNECTOR:35:?] [10690.231921] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] [10690.231923] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2] [10690.232082] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1) [10690.232083] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc [10690.232085] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected [10690.233135] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/937 [10690.233138] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [10690.233157] [drm:intel_edp_backlight_power] panel power control backlight disable [10690.434294] [drm:drm_mode_setcrtc] [CRTC:8] [10690.434298] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [10690.434300] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [10690.434302] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [10690.434303] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [10690.434305] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [10690.434307] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [10690.434310] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [10690.442541] [drm:intel_edp_backlight_off] [10690.643368] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [10690.659380] [drm:edp_panel_vdd_on] Turning eDP VDD on [10690.659387] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [10690.659540] [drm:intel_edp_panel_off] Turn eDP power off [10690.659544] [drm:wait_panel_off] Wait for panel power off time [10690.659548] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [10690.714401] [drm:wait_panel_status] Wait complete [10690.714410] [drm:intel_update_fbc] no output, disabling [10690.714415] [drm:intel_display_power_put] disabling always-on [10690.714419] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [10690.714421] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [10690.714422] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [10690.714424] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [10690.714425] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [10690.714426] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [10690.714428] [drm:check_crtc_state] [CRTC:8] [10690.714430] [drm:check_crtc_state] [CRTC:12] [10690.714432] [drm:check_crtc_state] [CRTC:16] [10690.714434] [drm:check_shared_dpll_state] WRPLL 1 [10690.714436] [drm:check_shared_dpll_state] WRPLL 2 [10690.717340] [drm:drm_mode_addfb] [FB:39] [10690.717487] [drm:drm_mode_setcrtc] [CRTC:8] [10690.717491] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [10690.717493] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [10690.717496] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [10690.717498] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [10690.717499] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [10690.717501] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [10690.717502] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [10690.717504] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [10690.717507] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [10690.717509] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [10690.717512] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [10690.717517] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [10690.717519] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [10690.717526] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [10690.717528] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [10690.717530] [drm:intel_dump_pipe_config] cpu_transcoder: D [10690.717531] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [10690.717533] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [10690.717535] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [10690.717537] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [10690.717539] [drm:intel_dump_pipe_config] requested mode: [10690.717542] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [10690.717543] [drm:intel_dump_pipe_config] adjusted mode: [10690.717545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [10690.717548] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [10690.717549] [drm:intel_dump_pipe_config] port clock: 270000 [10690.717551] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [10690.717553] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [10690.717554] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [10690.717556] [drm:intel_dump_pipe_config] ips: 1 [10690.717557] [drm:intel_dump_pipe_config] double wide: 0 [10690.717560] [drm:intel_display_power_get] enabling always-on [10690.745105] [drm:intel_edp_panel_on] Turn eDP power on [10690.745110] [drm:wait_panel_power_cycle] Wait for panel power cycle [10691.260692] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [10691.260694] [drm:wait_panel_status] Wait complete [10691.260698] [drm:wait_panel_on] Wait for panel power on [10691.260701] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [10691.469794] [drm:wait_panel_status] Wait complete [10691.469798] [drm:edp_panel_vdd_on] Turning eDP VDD on [10691.469805] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [10691.470860] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [10691.471307] [drm:intel_dp_start_link_train] clock recovery OK [10691.472055] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [10691.472291] [drm:intel_edp_backlight_on] [10691.472293] [drm:intel_panel_enable_backlight] pipe A [10691.472300] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [10691.472305] [drm:intel_edp_psr_enable] PSR not supported by this panel [10691.472311] [drm:ironlake_update_primary_plane] Writing base 01090000 00000000 0 0 7680 [10691.506812] [drm:intel_update_fbc] disabled per chip default [10691.506816] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [10691.506819] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [10691.506821] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [10691.506823] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [10691.506824] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [10691.506825] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [10691.506827] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [10691.506828] [drm:check_crtc_state] [CRTC:8] [10691.506835] [drm:check_crtc_state] [CRTC:12] [10691.506837] [drm:check_crtc_state] [CRTC:16] [10691.506839] [drm:check_shared_dpll_state] WRPLL 1 [10691.506841] [drm:check_shared_dpll_state] WRPLL 2 [10691.506860] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=937/937 [10691.506862] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [10693.665935] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [10693.665944] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007