[  237.666244] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.666245] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.666247] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.666249] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.666251] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.666252] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.666254] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.666255] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.666256] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.666257] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.666258] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.666259] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.666261] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.666262] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.666264] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.666265] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.666266] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.666267] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.666268] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.666270] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.666271] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.666273] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.666274] [drm:intel_dump_pipe_config] requested mode:
[  237.666276] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.666277] [drm:intel_dump_pipe_config] adjusted mode:
[  237.666278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.666280] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.666281] [drm:intel_dump_pipe_config] port clock: 108000
[  237.666282] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.666283] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.666285] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.666286] [drm:intel_dump_pipe_config] ips: 0
[  237.666286] [drm:intel_dump_pipe_config] double wide: 0
[  237.666288] [drm:intel_display_power_get] enabling always-on
[  237.666301] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.666302] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.666303] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.667657] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.667659] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.668315] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.668317] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.668318] [drm:gen6_fdi_link_train] FDI train done.
[  237.668321] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.668322] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.670200] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.670202] [drm:intel_update_fbc] disabled per chip default
[  237.670204] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.670208] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.670211] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.670213] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.670215] [drm:check_crtc_state] [CRTC:8]
[  237.670228] [drm:check_crtc_state] [CRTC:12]
[  237.670229] [drm:check_shared_dpll_state] PCH DPLL A
[  237.670232] [drm:check_shared_dpll_state] PCH DPLL B
[  237.670238] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.670239] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.670241] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.670242] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.670243] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.670244] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.670245] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.670246] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.703819] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.703824] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.704235] [drm:intel_update_fbc] no output, disabling
[  237.704237] [drm:intel_display_power_put] disabling always-on
[  237.704242] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.704244] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.704246] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.704249] [drm:check_crtc_state] [CRTC:8]
[  237.704250] [drm:check_crtc_state] [CRTC:12]
[  237.704251] [drm:check_shared_dpll_state] PCH DPLL A
[  237.704255] [drm:check_shared_dpll_state] PCH DPLL B
[  237.704262] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.704263] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.704265] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.704267] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.704269] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.704271] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.704272] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.704273] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.704274] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.704276] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.704277] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.704278] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.704279] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.704281] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.704282] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.704283] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.704284] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.704285] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.704286] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.704288] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.704290] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.704291] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.704292] [drm:intel_dump_pipe_config] requested mode:
[  237.704294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.704295] [drm:intel_dump_pipe_config] adjusted mode:
[  237.704296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.704298] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.704299] [drm:intel_dump_pipe_config] port clock: 108000
[  237.704300] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.704301] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.704303] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.704303] [drm:intel_dump_pipe_config] ips: 0
[  237.704304] [drm:intel_dump_pipe_config] double wide: 0
[  237.704306] [drm:intel_display_power_get] enabling always-on
[  237.704318] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.704319] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.704320] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.705675] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.705677] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.706333] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.706335] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.706336] [drm:gen6_fdi_link_train] FDI train done.
[  237.706339] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.706340] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.708217] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.708219] [drm:intel_update_fbc] disabled per chip default
[  237.708222] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.708226] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.708228] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.708231] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.708233] [drm:check_crtc_state] [CRTC:8]
[  237.708245] [drm:check_crtc_state] [CRTC:12]
[  237.708247] [drm:check_shared_dpll_state] PCH DPLL A
[  237.708250] [drm:check_shared_dpll_state] PCH DPLL B
[  237.708256] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.708257] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.708258] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.708260] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.708261] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.708262] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.708263] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.708264] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.741837] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.741842] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.742253] [drm:intel_update_fbc] no output, disabling
[  237.742256] [drm:intel_display_power_put] disabling always-on
[  237.742261] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.742263] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.742265] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.742267] [drm:check_crtc_state] [CRTC:8]
[  237.742269] [drm:check_crtc_state] [CRTC:12]
[  237.742270] [drm:check_shared_dpll_state] PCH DPLL A
[  237.742274] [drm:check_shared_dpll_state] PCH DPLL B
[  237.742282] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.742283] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.742285] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.742287] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.742289] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.742290] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.742291] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.742293] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.742294] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.742295] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.742296] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.742297] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.742299] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.742300] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.742302] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.742303] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.742304] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.742305] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.742306] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.742308] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.742309] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.742311] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.742311] [drm:intel_dump_pipe_config] requested mode:
[  237.742313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.742314] [drm:intel_dump_pipe_config] adjusted mode:
[  237.742316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.742318] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.742319] [drm:intel_dump_pipe_config] port clock: 108000
[  237.742320] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.742321] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.742322] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.742323] [drm:intel_dump_pipe_config] ips: 0
[  237.742324] [drm:intel_dump_pipe_config] double wide: 0
[  237.742326] [drm:intel_display_power_get] enabling always-on
[  237.742338] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.742339] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.742340] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.743694] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.743695] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.744351] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.744353] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.744354] [drm:gen6_fdi_link_train] FDI train done.
[  237.744357] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.744358] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.746236] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.746238] [drm:intel_update_fbc] disabled per chip default
[  237.746240] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.746244] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.746247] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.746249] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.746251] [drm:check_crtc_state] [CRTC:8]
[  237.746264] [drm:check_crtc_state] [CRTC:12]
[  237.746265] [drm:check_shared_dpll_state] PCH DPLL A
[  237.746269] [drm:check_shared_dpll_state] PCH DPLL B
[  237.746274] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.746275] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.746277] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.746278] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.746279] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.746280] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.746281] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.746282] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.779854] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.779859] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.780270] [drm:intel_update_fbc] no output, disabling
[  237.780273] [drm:intel_display_power_put] disabling always-on
[  237.780277] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.780280] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.780282] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.780284] [drm:check_crtc_state] [CRTC:8]
[  237.780285] [drm:check_crtc_state] [CRTC:12]
[  237.780287] [drm:check_shared_dpll_state] PCH DPLL A
[  237.780291] [drm:check_shared_dpll_state] PCH DPLL B
[  237.780299] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.780300] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.780301] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.780303] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.780305] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.780307] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.780308] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.780309] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.780310] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.780312] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.780313] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.780314] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.780315] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.780317] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.780318] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.780320] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.780321] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.780322] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.780323] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.780324] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.780326] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.780327] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.780328] [drm:intel_dump_pipe_config] requested mode:
[  237.780330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.780331] [drm:intel_dump_pipe_config] adjusted mode:
[  237.780333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.780334] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.780335] [drm:intel_dump_pipe_config] port clock: 108000
[  237.780336] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.780338] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.780339] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.780340] [drm:intel_dump_pipe_config] ips: 0
[  237.780341] [drm:intel_dump_pipe_config] double wide: 0
[  237.780342] [drm:intel_display_power_get] enabling always-on
[  237.780355] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.780356] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.780357] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.781711] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.781713] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.782369] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.782371] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.782372] [drm:gen6_fdi_link_train] FDI train done.
[  237.782375] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.782376] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.784254] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.784256] [drm:intel_update_fbc] disabled per chip default
[  237.784259] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.784262] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.784265] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.784267] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.784269] [drm:check_crtc_state] [CRTC:8]
[  237.784282] [drm:check_crtc_state] [CRTC:12]
[  237.784283] [drm:check_shared_dpll_state] PCH DPLL A
[  237.784287] [drm:check_shared_dpll_state] PCH DPLL B
[  237.784293] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.784294] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.784295] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.784296] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.784297] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.784298] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.784299] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.784301] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.817871] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.817876] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.818287] [drm:intel_update_fbc] no output, disabling
[  237.818289] [drm:intel_display_power_put] disabling always-on
[  237.818294] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.818297] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.818299] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.818301] [drm:check_crtc_state] [CRTC:8]
[  237.818302] [drm:check_crtc_state] [CRTC:12]
[  237.818304] [drm:check_shared_dpll_state] PCH DPLL A
[  237.818308] [drm:check_shared_dpll_state] PCH DPLL B
[  237.818316] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.818317] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.818318] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.818321] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.818323] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.818324] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.818325] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.818327] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.818328] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.818329] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.818330] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.818331] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.818333] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.818334] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.818336] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.818337] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.818338] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.818339] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.818340] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.818342] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.818343] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.818344] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.818345] [drm:intel_dump_pipe_config] requested mode:
[  237.818347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.818348] [drm:intel_dump_pipe_config] adjusted mode:
[  237.818350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.818352] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.818353] [drm:intel_dump_pipe_config] port clock: 108000
[  237.818354] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.818355] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.818356] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.818357] [drm:intel_dump_pipe_config] ips: 0
[  237.818358] [drm:intel_dump_pipe_config] double wide: 0
[  237.818360] [drm:intel_display_power_get] enabling always-on
[  237.818372] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.818373] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.818374] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.819728] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.819729] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.820385] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.820386] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.820387] [drm:gen6_fdi_link_train] FDI train done.
[  237.820390] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.820391] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.822268] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.822270] [drm:intel_update_fbc] disabled per chip default
[  237.822273] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.822277] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.822279] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.822282] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.822284] [drm:check_crtc_state] [CRTC:8]
[  237.822296] [drm:check_crtc_state] [CRTC:12]
[  237.822298] [drm:check_shared_dpll_state] PCH DPLL A
[  237.822301] [drm:check_shared_dpll_state] PCH DPLL B
[  237.822307] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.822308] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.822310] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.822311] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.822312] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.822313] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.822314] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.822315] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.827081] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on RC6p off RC6pp off
[  237.830870] [drm:gen6_enable_rps] Overclocking supported. Max: 1350MHz, Overclock max: 1350MHz
[  237.855887] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.855892] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.856303] [drm:intel_update_fbc] no output, disabling
[  237.856305] [drm:intel_display_power_put] disabling always-on
[  237.856310] [drm:intel_runtime_suspend] Suspending device
[  237.856320] [drm:intel_runtime_suspend] Device suspended
[  237.856331] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.856332] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.856332] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.856333] [drm:check_crtc_state] [CRTC:8]
[  237.856334] [drm:check_crtc_state] [CRTC:12]
[  237.856335] [drm:check_shared_dpll_state] PCH DPLL A
[  237.856336] [drm:check_shared_dpll_state] PCH DPLL B
[  237.856340] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.856341] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.856343] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.856345] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.856347] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.856349] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.856350] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.856351] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.856352] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.856354] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.856355] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.856356] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.856357] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.856359] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.856360] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.856361] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.856363] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.856363] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.856364] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.856366] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.856368] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.856369] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.856370] [drm:intel_dump_pipe_config] requested mode:
[  237.856372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.856373] [drm:intel_dump_pipe_config] adjusted mode:
[  237.856374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.856376] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.856377] [drm:intel_dump_pipe_config] port clock: 108000
[  237.856378] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.856379] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.856381] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.856382] [drm:intel_dump_pipe_config] ips: 0
[  237.856382] [drm:intel_dump_pipe_config] double wide: 0
[  237.877906] [drm:intel_runtime_resume] Resuming device
[  237.877908] [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0
[  237.899915] [drm:intel_runtime_resume] Device resumed
[  237.899918] [drm:intel_display_power_get] enabling always-on
[  237.899932] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.899933] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.899934] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.901289] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.901291] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.901947] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.901949] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.901950] [drm:gen6_fdi_link_train] FDI train done.
[  237.901953] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.901954] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.903831] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.903833] [drm:intel_update_fbc] disabled per chip default
[  237.903836] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.903840] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.903843] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.903845] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.903847] [drm:check_crtc_state] [CRTC:8]
[  237.903860] [drm:check_crtc_state] [CRTC:12]
[  237.903861] [drm:check_shared_dpll_state] PCH DPLL A
[  237.903864] [drm:check_shared_dpll_state] PCH DPLL B
[  237.903871] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.903872] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.903874] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.903875] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.903876] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.903877] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.903878] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.903880] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.936926] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.936932] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.937343] [drm:intel_update_fbc] no output, disabling
[  237.937345] [drm:intel_display_power_put] disabling always-on
[  237.937350] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.937352] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.937354] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.937357] [drm:check_crtc_state] [CRTC:8]
[  237.937358] [drm:check_crtc_state] [CRTC:12]
[  237.937359] [drm:check_shared_dpll_state] PCH DPLL A
[  237.937364] [drm:check_shared_dpll_state] PCH DPLL B
[  237.937370] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.937371] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.937373] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.937375] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.937377] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.937379] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.937380] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.937381] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.937382] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.937383] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.937384] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.937385] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.937387] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.937388] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.937390] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.937391] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.937392] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.937393] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.937394] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.937396] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.937397] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.937399] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.937400] [drm:intel_dump_pipe_config] requested mode:
[  237.937402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.937403] [drm:intel_dump_pipe_config] adjusted mode:
[  237.937404] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.937406] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.937407] [drm:intel_dump_pipe_config] port clock: 108000
[  237.937408] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.937409] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.937410] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.937411] [drm:intel_dump_pipe_config] ips: 0
[  237.937412] [drm:intel_dump_pipe_config] double wide: 0
[  237.937414] [drm:intel_display_power_get] enabling always-on
[  237.937426] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.937427] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.937429] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.938782] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.938784] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.939440] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.939442] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.939443] [drm:gen6_fdi_link_train] FDI train done.
[  237.939446] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.939450] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.941327] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.941329] [drm:intel_update_fbc] disabled per chip default
[  237.941331] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.941335] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.941338] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.941340] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.941342] [drm:check_crtc_state] [CRTC:8]
[  237.941355] [drm:check_crtc_state] [CRTC:12]
[  237.941356] [drm:check_shared_dpll_state] PCH DPLL A
[  237.941359] [drm:check_shared_dpll_state] PCH DPLL B
[  237.941365] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.941366] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.941367] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.941368] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.941369] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.941370] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.941371] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.941373] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  237.974944] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  237.974949] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  237.975361] [drm:intel_update_fbc] no output, disabling
[  237.975363] [drm:intel_display_power_put] disabling always-on
[  237.975368] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.975370] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.975372] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.975374] [drm:check_crtc_state] [CRTC:8]
[  237.975375] [drm:check_crtc_state] [CRTC:12]
[  237.975376] [drm:check_shared_dpll_state] PCH DPLL A
[  237.975381] [drm:check_shared_dpll_state] PCH DPLL B
[  237.975388] [drm:drm_mode_setcrtc] [CRTC:12]
[  237.975390] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  237.975391] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  237.975394] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.975396] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  237.975397] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  237.975398] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  237.975400] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.975401] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.975402] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  237.975403] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.975404] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  237.975405] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  237.975407] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  237.975408] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  237.975410] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  237.975411] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  237.975412] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  237.975413] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  237.975414] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  237.975416] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  237.975417] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  237.975418] [drm:intel_dump_pipe_config] requested mode:
[  237.975420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.975421] [drm:intel_dump_pipe_config] adjusted mode:
[  237.975423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  237.975424] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  237.975425] [drm:intel_dump_pipe_config] port clock: 108000
[  237.975426] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  237.975428] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  237.975429] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  237.975430] [drm:intel_dump_pipe_config] ips: 0
[  237.975431] [drm:intel_dump_pipe_config] double wide: 0
[  237.975432] [drm:intel_display_power_get] enabling always-on
[  237.975445] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  237.975446] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  237.975447] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  237.976801] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  237.976803] [drm:gen6_fdi_link_train] FDI train 1 done.
[  237.977459] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  237.977461] [drm:gen6_fdi_link_train] FDI train 2 done.
[  237.977462] [drm:gen6_fdi_link_train] FDI train done.
[  237.977465] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  237.977466] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  237.979343] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  237.979345] [drm:intel_update_fbc] disabled per chip default
[  237.979347] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  237.979351] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  237.979354] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  237.979356] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  237.979358] [drm:check_crtc_state] [CRTC:8]
[  237.979371] [drm:check_crtc_state] [CRTC:12]
[  237.979372] [drm:check_shared_dpll_state] PCH DPLL A
[  237.979376] [drm:check_shared_dpll_state] PCH DPLL B
[  237.979381] [drm:drm_mode_setcrtc] [CRTC:8]
[  237.979382] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  237.979383] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  237.979384] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  237.979385] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  237.979386] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  237.979387] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  237.979389] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.012961] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.012967] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.013378] [drm:intel_update_fbc] no output, disabling
[  238.013380] [drm:intel_display_power_put] disabling always-on
[  238.013385] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.013387] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.013389] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.013391] [drm:check_crtc_state] [CRTC:8]
[  238.013393] [drm:check_crtc_state] [CRTC:12]
[  238.013394] [drm:check_shared_dpll_state] PCH DPLL A
[  238.013399] [drm:check_shared_dpll_state] PCH DPLL B
[  238.013406] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.013407] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.013409] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.013411] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.013413] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.013414] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.013416] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.013417] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.013418] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.013419] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.013420] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.013421] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.013423] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.013424] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.013426] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.013427] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.013428] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.013429] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.013430] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.013432] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.013433] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.013435] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.013436] [drm:intel_dump_pipe_config] requested mode:
[  238.013438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.013438] [drm:intel_dump_pipe_config] adjusted mode:
[  238.013440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.013442] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.013443] [drm:intel_dump_pipe_config] port clock: 108000
[  238.013444] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.013445] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.013446] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.013447] [drm:intel_dump_pipe_config] ips: 0
[  238.013448] [drm:intel_dump_pipe_config] double wide: 0
[  238.013450] [drm:intel_display_power_get] enabling always-on
[  238.013462] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.013463] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.013464] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.014819] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.014820] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.015476] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.015478] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.015479] [drm:gen6_fdi_link_train] FDI train done.
[  238.015482] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.015483] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.017360] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.017362] [drm:intel_update_fbc] disabled per chip default
[  238.017365] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.017369] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.017371] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.017373] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.017375] [drm:check_crtc_state] [CRTC:8]
[  238.017388] [drm:check_crtc_state] [CRTC:12]
[  238.017389] [drm:check_shared_dpll_state] PCH DPLL A
[  238.017393] [drm:check_shared_dpll_state] PCH DPLL B
[  238.017398] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.017399] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.017400] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.017401] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.017402] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.017403] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.017404] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.017406] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.050979] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.050984] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.051395] [drm:intel_update_fbc] no output, disabling
[  238.051397] [drm:intel_display_power_put] disabling always-on
[  238.051402] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.051404] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.051407] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.051409] [drm:check_crtc_state] [CRTC:8]
[  238.051410] [drm:check_crtc_state] [CRTC:12]
[  238.051411] [drm:check_shared_dpll_state] PCH DPLL A
[  238.051416] [drm:check_shared_dpll_state] PCH DPLL B
[  238.051423] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.051424] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.051426] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.051428] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.051430] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.051432] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.051433] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.051434] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.051435] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.051437] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.051438] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.051439] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.051440] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.051442] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.051443] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.051444] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.051446] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.051446] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.051447] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.051449] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.051451] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.051452] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.051453] [drm:intel_dump_pipe_config] requested mode:
[  238.051455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.051456] [drm:intel_dump_pipe_config] adjusted mode:
[  238.051457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.051459] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.051460] [drm:intel_dump_pipe_config] port clock: 108000
[  238.051461] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.051462] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.051464] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.051464] [drm:intel_dump_pipe_config] ips: 0
[  238.051465] [drm:intel_dump_pipe_config] double wide: 0
[  238.051467] [drm:intel_display_power_get] enabling always-on
[  238.051480] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.051481] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.051482] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.052836] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.052838] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.053494] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.053495] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.053496] [drm:gen6_fdi_link_train] FDI train done.
[  238.053499] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.053500] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.055379] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.055381] [drm:intel_update_fbc] disabled per chip default
[  238.055383] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.055387] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.055389] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.055392] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.055394] [drm:check_crtc_state] [CRTC:8]
[  238.055407] [drm:check_crtc_state] [CRTC:12]
[  238.055408] [drm:check_shared_dpll_state] PCH DPLL A
[  238.055411] [drm:check_shared_dpll_state] PCH DPLL B
[  238.055417] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.055418] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.055419] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.055420] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.055421] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.055422] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.055423] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.055425] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.088997] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.089002] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.089413] [drm:intel_update_fbc] no output, disabling
[  238.089415] [drm:intel_display_power_put] disabling always-on
[  238.089420] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.089422] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.089424] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.089426] [drm:check_crtc_state] [CRTC:8]
[  238.089428] [drm:check_crtc_state] [CRTC:12]
[  238.089429] [drm:check_shared_dpll_state] PCH DPLL A
[  238.089433] [drm:check_shared_dpll_state] PCH DPLL B
[  238.089440] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.089441] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.089443] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.089445] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.089447] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.089448] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.089450] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.089451] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.089452] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.089453] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.089454] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.089455] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.089457] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.089458] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.089460] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.089461] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.089462] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.089463] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.089464] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.089466] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.089468] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.089469] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.089470] [drm:intel_dump_pipe_config] requested mode:
[  238.089472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.089473] [drm:intel_dump_pipe_config] adjusted mode:
[  238.089474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.089476] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.089477] [drm:intel_dump_pipe_config] port clock: 108000
[  238.089478] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.089479] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.089481] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.089481] [drm:intel_dump_pipe_config] ips: 0
[  238.089482] [drm:intel_dump_pipe_config] double wide: 0
[  238.089484] [drm:intel_display_power_get] enabling always-on
[  238.089497] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.089498] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.089499] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.090853] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.090856] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.091512] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.091514] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.091515] [drm:gen6_fdi_link_train] FDI train done.
[  238.091518] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.091521] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.093398] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.093400] [drm:intel_update_fbc] disabled per chip default
[  238.093403] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.093407] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.093409] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.093411] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.093414] [drm:check_crtc_state] [CRTC:8]
[  238.093426] [drm:check_crtc_state] [CRTC:12]
[  238.093427] [drm:check_shared_dpll_state] PCH DPLL A
[  238.093431] [drm:check_shared_dpll_state] PCH DPLL B
[  238.093436] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.093437] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.093439] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.093440] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.093441] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.093442] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.093443] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.093444] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.127013] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.127019] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.127429] [drm:intel_update_fbc] no output, disabling
[  238.127431] [drm:intel_display_power_put] disabling always-on
[  238.127436] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.127438] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.127441] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.127443] [drm:check_crtc_state] [CRTC:8]
[  238.127444] [drm:check_crtc_state] [CRTC:12]
[  238.127445] [drm:check_shared_dpll_state] PCH DPLL A
[  238.127450] [drm:check_shared_dpll_state] PCH DPLL B
[  238.127457] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.127459] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.127460] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.127462] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.127464] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.127466] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.127467] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.127468] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.127469] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.127471] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.127472] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.127473] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.127474] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.127476] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.127477] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.127479] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.127480] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.127481] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.127481] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.127483] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.127485] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.127486] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.127487] [drm:intel_dump_pipe_config] requested mode:
[  238.127489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.127490] [drm:intel_dump_pipe_config] adjusted mode:
[  238.127492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.127493] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.127494] [drm:intel_dump_pipe_config] port clock: 108000
[  238.127495] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.127496] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.127498] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.127499] [drm:intel_dump_pipe_config] ips: 0
[  238.127499] [drm:intel_dump_pipe_config] double wide: 0
[  238.127501] [drm:intel_display_power_get] enabling always-on
[  238.127514] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.127515] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.127516] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.128870] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.128872] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.129528] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.129530] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.129531] [drm:gen6_fdi_link_train] FDI train done.
[  238.129534] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.129535] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.131412] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.131414] [drm:intel_update_fbc] disabled per chip default
[  238.131417] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.131420] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.131423] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.131425] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.131427] [drm:check_crtc_state] [CRTC:8]
[  238.131440] [drm:check_crtc_state] [CRTC:12]
[  238.131441] [drm:check_shared_dpll_state] PCH DPLL A
[  238.131445] [drm:check_shared_dpll_state] PCH DPLL B
[  238.131450] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.131451] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.131452] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.131453] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.131454] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.131455] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.131456] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.131458] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.165032] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.165037] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.165448] [drm:intel_update_fbc] no output, disabling
[  238.165450] [drm:intel_display_power_put] disabling always-on
[  238.165455] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.165457] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.165460] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.165462] [drm:check_crtc_state] [CRTC:8]
[  238.165463] [drm:check_crtc_state] [CRTC:12]
[  238.165464] [drm:check_shared_dpll_state] PCH DPLL A
[  238.165469] [drm:check_shared_dpll_state] PCH DPLL B
[  238.165477] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.165478] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.165479] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.165481] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.165483] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.165485] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.165486] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.165488] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.165489] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.165490] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.165491] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.165492] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.165493] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.165495] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.165496] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.165498] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.165499] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.165500] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.165501] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.165502] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.165504] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.165505] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.165506] [drm:intel_dump_pipe_config] requested mode:
[  238.165508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.165509] [drm:intel_dump_pipe_config] adjusted mode:
[  238.165511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.165512] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.165513] [drm:intel_dump_pipe_config] port clock: 108000
[  238.165514] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.165516] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.165517] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.165518] [drm:intel_dump_pipe_config] ips: 0
[  238.165519] [drm:intel_dump_pipe_config] double wide: 0
[  238.165520] [drm:intel_display_power_get] enabling always-on
[  238.165533] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.165534] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.165535] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.166890] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.166892] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.167548] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.167550] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.167551] [drm:gen6_fdi_link_train] FDI train done.
[  238.167554] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.167555] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.169432] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.169434] [drm:intel_update_fbc] disabled per chip default
[  238.169436] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.169440] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.169442] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.169445] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.169447] [drm:check_crtc_state] [CRTC:8]
[  238.169460] [drm:check_crtc_state] [CRTC:12]
[  238.169461] [drm:check_shared_dpll_state] PCH DPLL A
[  238.169464] [drm:check_shared_dpll_state] PCH DPLL B
[  238.169469] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.169470] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.169472] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.169473] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.169474] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.169475] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.169476] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.169477] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.203049] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.203054] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.203465] [drm:intel_update_fbc] no output, disabling
[  238.203468] [drm:intel_display_power_put] disabling always-on
[  238.203472] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.203474] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.203476] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.203479] [drm:check_crtc_state] [CRTC:8]
[  238.203480] [drm:check_crtc_state] [CRTC:12]
[  238.203481] [drm:check_shared_dpll_state] PCH DPLL A
[  238.203486] [drm:check_shared_dpll_state] PCH DPLL B
[  238.203493] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.203494] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.203496] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.203498] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.203500] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.203502] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.203503] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.203504] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.203505] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.203506] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.203507] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.203509] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.203510] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.203511] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.203513] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.203514] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.203515] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.203516] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.203517] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.203519] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.203520] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.203522] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.203523] [drm:intel_dump_pipe_config] requested mode:
[  238.203525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.203526] [drm:intel_dump_pipe_config] adjusted mode:
[  238.203527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.203529] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.203530] [drm:intel_dump_pipe_config] port clock: 108000
[  238.203531] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.203532] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.203534] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.203534] [drm:intel_dump_pipe_config] ips: 0
[  238.203535] [drm:intel_dump_pipe_config] double wide: 0
[  238.203537] [drm:intel_display_power_get] enabling always-on
[  238.203549] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.203550] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.203552] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.204905] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.204907] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.205563] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.205565] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.205566] [drm:gen6_fdi_link_train] FDI train done.
[  238.205569] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.205570] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.207447] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.207449] [drm:intel_update_fbc] disabled per chip default
[  238.207452] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.207456] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.207458] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.207460] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.207462] [drm:check_crtc_state] [CRTC:8]
[  238.207475] [drm:check_crtc_state] [CRTC:12]
[  238.207476] [drm:check_shared_dpll_state] PCH DPLL A
[  238.207480] [drm:check_shared_dpll_state] PCH DPLL B
[  238.207485] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.207486] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.207487] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.207488] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.207489] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.207490] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.207491] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.207493] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.241065] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.241070] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.241482] [drm:intel_update_fbc] no output, disabling
[  238.241484] [drm:intel_display_power_put] disabling always-on
[  238.241489] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.241491] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.241493] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.241495] [drm:check_crtc_state] [CRTC:8]
[  238.241497] [drm:check_crtc_state] [CRTC:12]
[  238.241498] [drm:check_shared_dpll_state] PCH DPLL A
[  238.241502] [drm:check_shared_dpll_state] PCH DPLL B
[  238.241508] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.241510] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.241511] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.241514] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.241516] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.241517] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.241518] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.241520] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.241521] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.241522] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.241523] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.241524] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.241526] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.241527] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.241529] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.241530] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.241531] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.241532] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.241533] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.241535] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.241536] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.241537] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.241538] [drm:intel_dump_pipe_config] requested mode:
[  238.241540] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.241541] [drm:intel_dump_pipe_config] adjusted mode:
[  238.241543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.241545] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.241546] [drm:intel_dump_pipe_config] port clock: 108000
[  238.241547] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.241548] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.241549] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.241550] [drm:intel_dump_pipe_config] ips: 0
[  238.241551] [drm:intel_dump_pipe_config] double wide: 0
[  238.241553] [drm:intel_display_power_get] enabling always-on
[  238.241565] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.241566] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.241567] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.242921] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.242924] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.243580] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.243582] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.243583] [drm:gen6_fdi_link_train] FDI train done.
[  238.243586] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.243587] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.245464] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.245466] [drm:intel_update_fbc] disabled per chip default
[  238.245469] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.245473] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.245475] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.245478] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.245480] [drm:check_crtc_state] [CRTC:8]
[  238.245492] [drm:check_crtc_state] [CRTC:12]
[  238.245494] [drm:check_shared_dpll_state] PCH DPLL A
[  238.245497] [drm:check_shared_dpll_state] PCH DPLL B
[  238.245503] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.245504] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.245505] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.245507] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.245507] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.245508] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.245510] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.245511] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.279084] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.279089] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.279500] [drm:intel_update_fbc] no output, disabling
[  238.279502] [drm:intel_display_power_put] disabling always-on
[  238.279507] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.279510] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.279512] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.279514] [drm:check_crtc_state] [CRTC:8]
[  238.279515] [drm:check_crtc_state] [CRTC:12]
[  238.279517] [drm:check_shared_dpll_state] PCH DPLL A
[  238.279521] [drm:check_shared_dpll_state] PCH DPLL B
[  238.279529] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.279530] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.279531] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.279534] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.279536] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.279537] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.279538] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.279540] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.279541] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.279542] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.279543] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.279544] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.279545] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.279547] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.279548] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.279550] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.279551] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.279552] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.279553] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.279554] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.279556] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.279557] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.279558] [drm:intel_dump_pipe_config] requested mode:
[  238.279560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.279561] [drm:intel_dump_pipe_config] adjusted mode:
[  238.279563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.279565] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.279566] [drm:intel_dump_pipe_config] port clock: 108000
[  238.279566] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.279568] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.279569] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.279570] [drm:intel_dump_pipe_config] ips: 0
[  238.279571] [drm:intel_dump_pipe_config] double wide: 0
[  238.279572] [drm:intel_display_power_get] enabling always-on
[  238.279585] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.279586] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.279587] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.280942] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.280944] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.281600] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.281602] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.281603] [drm:gen6_fdi_link_train] FDI train done.
[  238.281606] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.281607] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.283484] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.283486] [drm:intel_update_fbc] disabled per chip default
[  238.283488] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.283492] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.283495] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.283497] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.283499] [drm:check_crtc_state] [CRTC:8]
[  238.283512] [drm:check_crtc_state] [CRTC:12]
[  238.283513] [drm:check_shared_dpll_state] PCH DPLL A
[  238.283517] [drm:check_shared_dpll_state] PCH DPLL B
[  238.283522] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.283523] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.283525] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.283526] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.283527] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.283528] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.283529] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.283531] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.317101] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.317107] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.317518] [drm:intel_update_fbc] no output, disabling
[  238.317520] [drm:intel_display_power_put] disabling always-on
[  238.317525] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.317527] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.317529] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.317531] [drm:check_crtc_state] [CRTC:8]
[  238.317533] [drm:check_crtc_state] [CRTC:12]
[  238.317534] [drm:check_shared_dpll_state] PCH DPLL A
[  238.317538] [drm:check_shared_dpll_state] PCH DPLL B
[  238.317545] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.317546] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.317548] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.317550] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.317552] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.317553] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.317555] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.317556] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.317557] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.317558] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.317559] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.317560] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.317562] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.317563] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.317565] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.317566] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.317567] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.317568] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.317569] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.317571] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.317572] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.317574] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.317575] [drm:intel_dump_pipe_config] requested mode:
[  238.317576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.317577] [drm:intel_dump_pipe_config] adjusted mode:
[  238.317579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.317581] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.317582] [drm:intel_dump_pipe_config] port clock: 108000
[  238.317583] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.317584] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.317585] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.317586] [drm:intel_dump_pipe_config] ips: 0
[  238.317587] [drm:intel_dump_pipe_config] double wide: 0
[  238.317589] [drm:intel_display_power_get] enabling always-on
[  238.317601] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.317602] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.317603] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.318957] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.318959] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.319615] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.319617] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.319618] [drm:gen6_fdi_link_train] FDI train done.
[  238.319621] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.319622] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.321499] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.321501] [drm:intel_update_fbc] disabled per chip default
[  238.321503] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.321507] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.321510] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.321512] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.321514] [drm:check_crtc_state] [CRTC:8]
[  238.321527] [drm:check_crtc_state] [CRTC:12]
[  238.321528] [drm:check_shared_dpll_state] PCH DPLL A
[  238.321532] [drm:check_shared_dpll_state] PCH DPLL B
[  238.321537] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.321538] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.321540] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.321541] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.321542] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.321543] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.321544] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.321545] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.355119] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.355124] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.355535] [drm:intel_update_fbc] no output, disabling
[  238.355537] [drm:intel_display_power_put] disabling always-on
[  238.355542] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.355544] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.355546] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.355549] [drm:check_crtc_state] [CRTC:8]
[  238.355550] [drm:check_crtc_state] [CRTC:12]
[  238.355551] [drm:check_shared_dpll_state] PCH DPLL A
[  238.355556] [drm:check_shared_dpll_state] PCH DPLL B
[  238.355563] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.355564] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.355566] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.355568] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.355570] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.355572] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.355573] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.355574] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.355575] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.355577] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.355578] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.355579] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.355580] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.355582] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.355583] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.355584] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.355586] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.355587] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.355587] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.355589] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.355591] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.355592] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.355593] [drm:intel_dump_pipe_config] requested mode:
[  238.355595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.355596] [drm:intel_dump_pipe_config] adjusted mode:
[  238.355598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.355599] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.355600] [drm:intel_dump_pipe_config] port clock: 108000
[  238.355601] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.355602] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.355604] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.355605] [drm:intel_dump_pipe_config] ips: 0
[  238.355605] [drm:intel_dump_pipe_config] double wide: 0
[  238.355607] [drm:intel_display_power_get] enabling always-on
[  238.355620] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.355621] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.355622] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.356977] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.356979] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.357635] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.357637] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.357638] [drm:gen6_fdi_link_train] FDI train done.
[  238.357641] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.357642] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.359519] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.359521] [drm:intel_update_fbc] disabled per chip default
[  238.359524] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.359528] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.359530] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.359533] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.359535] [drm:check_crtc_state] [CRTC:8]
[  238.359547] [drm:check_crtc_state] [CRTC:12]
[  238.359548] [drm:check_shared_dpll_state] PCH DPLL A
[  238.359552] [drm:check_shared_dpll_state] PCH DPLL B
[  238.359558] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.359559] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.359560] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.359561] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.359562] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.359563] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.359564] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.359566] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.393137] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.393142] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.393553] [drm:intel_update_fbc] no output, disabling
[  238.393555] [drm:intel_display_power_put] disabling always-on
[  238.393559] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.393562] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.393564] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.393566] [drm:check_crtc_state] [CRTC:8]
[  238.393567] [drm:check_crtc_state] [CRTC:12]
[  238.393569] [drm:check_shared_dpll_state] PCH DPLL A
[  238.393573] [drm:check_shared_dpll_state] PCH DPLL B
[  238.393581] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.393582] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.393583] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.393586] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.393587] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.393589] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.393590] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.393592] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.393593] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.393594] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.393595] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.393596] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.393597] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.393599] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.393601] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.393602] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.393603] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.393604] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.393605] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.393607] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.393608] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.393609] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.393610] [drm:intel_dump_pipe_config] requested mode:
[  238.393612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.393613] [drm:intel_dump_pipe_config] adjusted mode:
[  238.393615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.393617] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.393618] [drm:intel_dump_pipe_config] port clock: 108000
[  238.393619] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.393620] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.393621] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.393622] [drm:intel_dump_pipe_config] ips: 0
[  238.393623] [drm:intel_dump_pipe_config] double wide: 0
[  238.393625] [drm:intel_display_power_get] enabling always-on
[  238.393637] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.393638] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.393639] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.394993] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.394995] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.395651] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.395653] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.395654] [drm:gen6_fdi_link_train] FDI train done.
[  238.395657] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.395658] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.397536] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.397538] [drm:intel_update_fbc] disabled per chip default
[  238.397541] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.397545] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.397547] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.397549] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.397551] [drm:check_crtc_state] [CRTC:8]
[  238.397564] [drm:check_crtc_state] [CRTC:12]
[  238.397565] [drm:check_shared_dpll_state] PCH DPLL A
[  238.397569] [drm:check_shared_dpll_state] PCH DPLL B
[  238.397575] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.397575] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.397577] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.397578] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.397579] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.397580] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.397581] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.397583] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.431154] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.431159] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.431570] [drm:intel_update_fbc] no output, disabling
[  238.431572] [drm:intel_display_power_put] disabling always-on
[  238.431577] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.431580] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.431582] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.431584] [drm:check_crtc_state] [CRTC:8]
[  238.431585] [drm:check_crtc_state] [CRTC:12]
[  238.431587] [drm:check_shared_dpll_state] PCH DPLL A
[  238.431591] [drm:check_shared_dpll_state] PCH DPLL B
[  238.431599] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.431600] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.431601] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.431604] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.431606] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.431607] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.431608] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.431610] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.431611] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.431612] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.431613] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.431614] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.431616] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.431617] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.431619] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.431620] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.431621] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.431622] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.431623] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.431624] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.431626] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.431627] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.431628] [drm:intel_dump_pipe_config] requested mode:
[  238.431630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.431631] [drm:intel_dump_pipe_config] adjusted mode:
[  238.431633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.431635] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.431636] [drm:intel_dump_pipe_config] port clock: 108000
[  238.431637] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.431638] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.431639] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.431640] [drm:intel_dump_pipe_config] ips: 0
[  238.431641] [drm:intel_dump_pipe_config] double wide: 0
[  238.431643] [drm:intel_display_power_get] enabling always-on
[  238.431655] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.431656] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.431657] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.433011] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.433013] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.433669] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.433671] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.433672] [drm:gen6_fdi_link_train] FDI train done.
[  238.433675] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.433676] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.435554] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.435556] [drm:intel_update_fbc] disabled per chip default
[  238.435559] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.435562] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.435565] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.435567] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.435569] [drm:check_crtc_state] [CRTC:8]
[  238.435582] [drm:check_crtc_state] [CRTC:12]
[  238.435583] [drm:check_shared_dpll_state] PCH DPLL A
[  238.435587] [drm:check_shared_dpll_state] PCH DPLL B
[  238.435592] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.435593] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.435595] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.435596] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.435597] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.435598] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.435599] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.435600] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.469172] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.469177] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.469588] [drm:intel_update_fbc] no output, disabling
[  238.469590] [drm:intel_display_power_put] disabling always-on
[  238.469595] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.469597] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.469599] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.469601] [drm:check_crtc_state] [CRTC:8]
[  238.469603] [drm:check_crtc_state] [CRTC:12]
[  238.469604] [drm:check_shared_dpll_state] PCH DPLL A
[  238.469608] [drm:check_shared_dpll_state] PCH DPLL B
[  238.469616] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.469617] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.469619] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.469621] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.469623] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.469624] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.469625] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.469627] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.469628] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.469629] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.469630] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.469631] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.469633] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.469634] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.469636] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.469637] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.469638] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.469639] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.469640] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.469642] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.469643] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.469644] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.469645] [drm:intel_dump_pipe_config] requested mode:
[  238.469647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.469648] [drm:intel_dump_pipe_config] adjusted mode:
[  238.469650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.469652] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.469653] [drm:intel_dump_pipe_config] port clock: 108000
[  238.469654] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.469655] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.469656] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.469657] [drm:intel_dump_pipe_config] ips: 0
[  238.469658] [drm:intel_dump_pipe_config] double wide: 0
[  238.469660] [drm:intel_display_power_get] enabling always-on
[  238.469672] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.469673] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.469674] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.471028] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.471031] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.471687] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.471689] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.471690] [drm:gen6_fdi_link_train] FDI train done.
[  238.471693] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.471694] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.473571] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.473573] [drm:intel_update_fbc] disabled per chip default
[  238.473576] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.473580] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.473582] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.473585] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.473587] [drm:check_crtc_state] [CRTC:8]
[  238.473599] [drm:check_crtc_state] [CRTC:12]
[  238.473601] [drm:check_shared_dpll_state] PCH DPLL A
[  238.473604] [drm:check_shared_dpll_state] PCH DPLL B
[  238.473610] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.473611] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.473613] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.473614] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.473615] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.473616] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.473617] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.473618] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.507189] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.507195] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.507606] [drm:intel_update_fbc] no output, disabling
[  238.507608] [drm:intel_display_power_put] disabling always-on
[  238.507613] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.507615] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.507617] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.507620] [drm:check_crtc_state] [CRTC:8]
[  238.507621] [drm:check_crtc_state] [CRTC:12]
[  238.507622] [drm:check_shared_dpll_state] PCH DPLL A
[  238.507627] [drm:check_shared_dpll_state] PCH DPLL B
[  238.507634] [drm:drm_mode_setcrtc] [CRTC:12]
[  238.507635] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.507637] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.507639] [drm:drm_mode_setcrtc] [CRTC:8]
[  238.507641] [drm:drm_mode_setcrtc] [CONNECTOR:14:VGA-1]
[  238.507643] [drm:intel_crtc_set_config] [CRTC:8] [FB:24] #connectors=1 (x y) (0 0)
[  238.507644] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.507645] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.507646] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.507648] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.507649] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.507650] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.507651] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.507653] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.507654] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.507655] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.507657] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.507657] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.507658] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.507660] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.507662] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.507663] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.507664] [drm:intel_dump_pipe_config] requested mode:
[  238.507666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.507667] [drm:intel_dump_pipe_config] adjusted mode:
[  238.507668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.507670] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.507671] [drm:intel_dump_pipe_config] port clock: 108000
[  238.507672] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.507673] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.507675] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.507676] [drm:intel_dump_pipe_config] ips: 0
[  238.507676] [drm:intel_dump_pipe_config] double wide: 0
[  238.507678] [drm:intel_display_power_get] enabling always-on
[  238.507691] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.507692] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.507693] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.509047] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.509049] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.509705] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.509707] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.509708] [drm:gen6_fdi_link_train] FDI train done.
[  238.509711] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.509712] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.511589] [drm:ironlake_update_primary_plane] Writing base 0069D000 00000000 0 0 5120
[  238.511591] [drm:intel_update_fbc] disabled per chip default
[  238.511594] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.511598] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.511601] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.511603] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.511605] [drm:check_crtc_state] [CRTC:8]
[  238.511618] [drm:check_crtc_state] [CRTC:12]
[  238.511619] [drm:check_shared_dpll_state] PCH DPLL A
[  238.511623] [drm:check_shared_dpll_state] PCH DPLL B
[  238.511675] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
[  238.511677] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.511678] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [NOCRTC]
[  238.511679] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.511680] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.511681] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
[  238.511683] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  238.545207] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 8
[  238.545212] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
[  238.545623] [drm:intel_update_fbc] no output, disabling
[  238.545625] [drm:intel_display_power_put] disabling always-on
[  238.545630] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.545632] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.545634] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.545636] [drm:check_crtc_state] [CRTC:8]
[  238.545638] [drm:check_crtc_state] [CRTC:12]
[  238.545639] [drm:check_shared_dpll_state] PCH DPLL A
[  238.545643] [drm:check_shared_dpll_state] PCH DPLL B
[  238.545947] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0)
[  238.545949] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
[  238.545950] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
[  238.545950] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
[  238.545951] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.545952] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
[  238.545953] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
[  238.545954] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  238.545955] [drm:connected_sink_compute_bpp] [CONNECTOR:14:VGA-1] checking for sink bpp constrains
[  238.545956] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  238.545957] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  238.545957] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
[  238.545958] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  238.545958] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  238.545960] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 5033164, gmch_n: 8388608, link_m: 209715, link_n: 524288, tu: 64
[  238.545961] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  238.545962] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  238.545962] [drm:intel_dump_pipe_config] requested mode:
[  238.545964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.545964] [drm:intel_dump_pipe_config] adjusted mode:
[  238.545965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5
[  238.545966] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x48 flags: 0x5
[  238.545967] [drm:intel_dump_pipe_config] port clock: 108000
[  238.545968] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
[  238.545968] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  238.545969] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  238.545969] [drm:intel_dump_pipe_config] ips: 0
[  238.545970] [drm:intel_dump_pipe_config] double wide: 0
[  238.545971] [drm:intel_display_power_get] enabling always-on
[  238.545983] [drm:intel_get_shared_dpll] CRTC:8 allocated PCH DPLL A
[  238.545983] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
[  238.545984] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
[  238.547338] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
[  238.547340] [drm:gen6_fdi_link_train] FDI train 1 done.
[  238.547995] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
[  238.547997] [drm:gen6_fdi_link_train] FDI train 2 done.
[  238.547997] [drm:gen6_fdi_link_train] FDI train done.
[  238.548000] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0) for crtc 8
[  238.548001] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
[  238.549877] [drm:ironlake_update_primary_plane] Writing base 0019D000 00000000 0 0 5120
[  238.549879] [drm:intel_update_fbc] disabled per chip default
[  238.549881] [drm:intel_connector_check_state] [CONNECTOR:14:VGA-1]
[  238.549884] [drm:check_encoder_state] [ENCODER:15:DAC-15]
[  238.549886] [drm:check_encoder_state] [ENCODER:16:TMDS-16]
[  238.549888] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
[  238.549890] [drm:check_crtc_state] [CRTC:8]
[  238.549902] [drm:check_crtc_state] [CRTC:12]
[  238.549903] [drm:check_shared_dpll_state] PCH DPLL A
[  238.549906] [drm:check_shared_dpll_state] PCH DPLL B
[  238.549909] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.549911] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.549911] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.549914] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0)
[  238.549915] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
[  238.549916] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.549924] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0)
[  238.549925] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
[  238.549925] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.553917] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0)
[  238.553919] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
[  238.553920] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  238.553922] [drm:intel_crtc_set_config] [CRTC:12] [NOFB]
[  238.553923] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
[  238.553924] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:VGA-1] to [CRTC:8]
[  239.836029] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on RC6p off RC6pp off
[  239.839805] [drm:gen6_enable_rps] Overclocking supported. Max: 1350MHz, Overclock max: 1350MHz