[ 670.184920] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 670.184922] [drm:intel_dump_pipe_config] port clock: 270000 [ 670.184924] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 670.184926] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 670.184927] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 670.184929] [drm:intel_dump_pipe_config] ips: 1 [ 670.184931] [drm:intel_dump_pipe_config] double wide: 0 [ 670.184933] [drm:intel_display_power_get] enabling always-on [ 670.184946] [drm:intel_edp_panel_on] Turn eDP power on [ 670.184950] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 670.731093] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 670.753102] [drm:wait_panel_status] Wait complete [ 670.753106] [drm:wait_panel_on] Wait for panel power on [ 670.753110] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 670.962210] [drm:wait_panel_status] Wait complete [ 670.962218] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 670.962224] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 670.963271] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 670.963712] [drm:intel_dp_start_link_train] clock recovery OK [ 670.964456] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 670.964688] [drm:intel_edp_backlight_on] [ 670.964690] [drm:intel_panel_enable_backlight] pipe A [ 670.964697] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 670.964702] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 670.964707] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 670.999228] [drm:intel_update_fbc] disabled per chip default [ 670.999232] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 670.999235] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 670.999237] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 670.999238] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 670.999240] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 670.999241] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 670.999242] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 670.999244] [drm:check_crtc_state] [CRTC:8] [ 670.999250] [drm:check_crtc_state] [CRTC:12] [ 670.999251] [drm:check_crtc_state] [CRTC:16] [ 670.999257] [drm:check_shared_dpll_state] WRPLL 1 [ 670.999258] [drm:check_shared_dpll_state] WRPLL 2 [ 670.999263] [drm:drm_mode_setcrtc] [CRTC:8] [ 670.999264] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 670.999266] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 670.999268] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 670.999269] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 670.999271] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 670.999272] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 670.999274] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 671.014672] [drm:intel_edp_backlight_off] [ 671.215340] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 671.233496] [drm:intel_edp_panel_off] Turn eDP power off [ 671.233503] [drm:wait_panel_off] Wait for panel power off time [ 671.233507] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 671.288378] [drm:wait_panel_status] Wait complete [ 671.288385] [drm:intel_update_fbc] no output, disabling [ 671.288388] [drm:intel_display_power_put] disabling always-on [ 671.288391] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 671.288393] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 671.288395] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 671.288396] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 671.288397] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 671.288399] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 671.288400] [drm:check_crtc_state] [CRTC:8] [ 671.288405] [drm:check_crtc_state] [CRTC:12] [ 671.288407] [drm:check_crtc_state] [CRTC:16] [ 671.288408] [drm:check_shared_dpll_state] WRPLL 1 [ 671.288410] [drm:check_shared_dpll_state] WRPLL 2 [ 671.288414] [drm:drm_mode_setcrtc] [CRTC:12] [ 671.288415] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 671.288417] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 671.288419] [drm:drm_mode_setcrtc] [CRTC:16] [ 671.288421] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 671.288423] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 671.288425] [drm:drm_mode_setcrtc] [CRTC:8] [ 671.288427] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 671.288429] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 671.288431] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 671.288433] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 671.288434] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 671.288436] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 671.288437] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 671.288439] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 671.288441] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 671.288443] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 671.288445] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 671.288450] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 671.288451] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 671.288454] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 671.288455] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 671.288456] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 671.288458] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 671.288460] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 671.288462] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 671.288464] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 671.288465] [drm:intel_dump_pipe_config] requested mode: [ 671.288468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 671.288470] [drm:intel_dump_pipe_config] adjusted mode: [ 671.288472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 671.288474] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 671.288476] [drm:intel_dump_pipe_config] port clock: 270000 [ 671.288477] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 671.288479] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 671.288481] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 671.288482] [drm:intel_dump_pipe_config] ips: 1 [ 671.288483] [drm:intel_dump_pipe_config] double wide: 0 [ 671.288486] [drm:intel_display_power_get] enabling always-on [ 671.288498] [drm:intel_edp_panel_on] Turn eDP power on [ 671.288502] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 671.834663] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 671.856672] [drm:wait_panel_status] Wait complete [ 671.856677] [drm:wait_panel_on] Wait for panel power on [ 671.856680] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 672.065780] [drm:wait_panel_status] Wait complete [ 672.065784] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 672.065791] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 672.066840] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 672.067282] [drm:intel_dp_start_link_train] clock recovery OK [ 672.068026] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 672.068258] [drm:intel_edp_backlight_on] [ 672.068260] [drm:intel_panel_enable_backlight] pipe A [ 672.068267] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 672.068272] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 672.068276] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 672.102798] [drm:intel_update_fbc] disabled per chip default [ 672.102801] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 672.102804] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 672.102806] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 672.102808] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 672.102809] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 672.102810] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 672.102812] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 672.102813] [drm:check_crtc_state] [CRTC:8] [ 672.102819] [drm:check_crtc_state] [CRTC:12] [ 672.102825] [drm:check_crtc_state] [CRTC:16] [ 672.102826] [drm:check_shared_dpll_state] WRPLL 1 [ 672.102828] [drm:check_shared_dpll_state] WRPLL 2 [ 672.102832] [drm:drm_mode_setcrtc] [CRTC:8] [ 672.102833] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 672.102836] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 672.102837] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 672.102839] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 672.102840] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 672.102842] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 672.102844] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 672.118242] [drm:intel_edp_backlight_off] [ 672.318911] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 672.337065] [drm:intel_edp_panel_off] Turn eDP power off [ 672.337072] [drm:wait_panel_off] Wait for panel power off time [ 672.337076] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 672.391949] [drm:wait_panel_status] Wait complete [ 672.391956] [drm:intel_update_fbc] no output, disabling [ 672.391959] [drm:intel_display_power_put] disabling always-on [ 672.391962] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 672.391963] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 672.391965] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 672.391966] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 672.391967] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 672.391969] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 672.391974] [drm:check_crtc_state] [CRTC:8] [ 672.391976] [drm:check_crtc_state] [CRTC:12] [ 672.391977] [drm:check_crtc_state] [CRTC:16] [ 672.391978] [drm:check_shared_dpll_state] WRPLL 1 [ 672.391980] [drm:check_shared_dpll_state] WRPLL 2 [ 672.391983] [drm:drm_mode_setcrtc] [CRTC:12] [ 672.391985] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 672.391987] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 672.391989] [drm:drm_mode_setcrtc] [CRTC:16] [ 672.391990] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 672.391992] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 672.391994] [drm:drm_mode_setcrtc] [CRTC:8] [ 672.391997] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 672.391999] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 672.392000] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 672.392002] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 672.392004] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 672.392005] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 672.392007] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 672.392008] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 672.392010] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 672.392012] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 672.392014] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 672.392019] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 672.392020] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 672.392023] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 672.392024] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 672.392025] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 672.392027] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 672.392029] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 672.392031] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 672.392033] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 672.392034] [drm:intel_dump_pipe_config] requested mode: [ 672.392037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 672.392038] [drm:intel_dump_pipe_config] adjusted mode: [ 672.392041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 672.392043] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 672.392045] [drm:intel_dump_pipe_config] port clock: 270000 [ 672.392046] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 672.392048] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 672.392049] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 672.392051] [drm:intel_dump_pipe_config] ips: 1 [ 672.392052] [drm:intel_dump_pipe_config] double wide: 0 [ 672.392054] [drm:intel_display_power_get] enabling always-on [ 672.392067] [drm:intel_edp_panel_on] Turn eDP power on [ 672.392070] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 672.938235] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 672.949238] [drm:wait_panel_status] Wait complete [ 672.949242] [drm:wait_panel_on] Wait for panel power on [ 672.949245] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 673.158345] [drm:wait_panel_status] Wait complete [ 673.158349] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 673.158355] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 673.159403] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 673.159845] [drm:intel_dp_start_link_train] clock recovery OK [ 673.160588] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 673.160820] [drm:intel_edp_backlight_on] [ 673.160822] [drm:intel_panel_enable_backlight] pipe A [ 673.160829] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 673.160834] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 673.160838] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 673.195363] [drm:intel_update_fbc] disabled per chip default [ 673.195366] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 673.195369] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 673.195371] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 673.195373] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 673.195374] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 673.195376] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 673.195377] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 673.195378] [drm:check_crtc_state] [CRTC:8] [ 673.195388] [drm:check_crtc_state] [CRTC:12] [ 673.195390] [drm:check_crtc_state] [CRTC:16] [ 673.195391] [drm:check_shared_dpll_state] WRPLL 1 [ 673.195392] [drm:check_shared_dpll_state] WRPLL 2 [ 673.195397] [drm:drm_mode_setcrtc] [CRTC:8] [ 673.195398] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 673.195400] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 673.195402] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 673.195403] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 673.195405] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 673.195406] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 673.195409] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 673.210804] [drm:intel_edp_backlight_off] [ 673.411474] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 673.429637] [drm:intel_edp_panel_off] Turn eDP power off [ 673.429642] [drm:wait_panel_off] Wait for panel power off time [ 673.429646] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 673.484513] [drm:wait_panel_status] Wait complete [ 673.484520] [drm:intel_update_fbc] no output, disabling [ 673.484523] [drm:intel_display_power_put] disabling always-on [ 673.484526] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 673.484528] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 673.484529] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 673.484531] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 673.484532] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 673.484537] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 673.484539] [drm:check_crtc_state] [CRTC:8] [ 673.484541] [drm:check_crtc_state] [CRTC:12] [ 673.484542] [drm:check_crtc_state] [CRTC:16] [ 673.484543] [drm:check_shared_dpll_state] WRPLL 1 [ 673.484545] [drm:check_shared_dpll_state] WRPLL 2 [ 673.484549] [drm:drm_mode_setcrtc] [CRTC:12] [ 673.484550] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 673.484552] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 673.484555] [drm:drm_mode_setcrtc] [CRTC:16] [ 673.484556] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 673.484558] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 673.484560] [drm:drm_mode_setcrtc] [CRTC:8] [ 673.484563] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 673.484565] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 673.484567] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 673.484568] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 673.484570] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 673.484571] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 673.484573] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 673.484574] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 673.484576] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 673.484578] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 673.484581] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 673.484586] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 673.484587] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 673.484589] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 673.484591] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 673.484592] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 673.484593] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 673.484596] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 673.484598] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 673.484600] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 673.484601] [drm:intel_dump_pipe_config] requested mode: [ 673.484604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 673.484605] [drm:intel_dump_pipe_config] adjusted mode: [ 673.484607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 673.484610] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 673.484611] [drm:intel_dump_pipe_config] port clock: 270000 [ 673.484613] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 673.484614] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 673.484616] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 673.484617] [drm:intel_dump_pipe_config] ips: 1 [ 673.484619] [drm:intel_dump_pipe_config] double wide: 0 [ 673.484621] [drm:intel_display_power_get] enabling always-on [ 673.484633] [drm:intel_edp_panel_on] Turn eDP power on [ 673.484637] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 674.030797] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 674.052807] [drm:wait_panel_status] Wait complete [ 674.052811] [drm:wait_panel_on] Wait for panel power on [ 674.052814] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 674.261915] [drm:wait_panel_status] Wait complete [ 674.261925] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 674.261931] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 674.262985] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 674.263426] [drm:intel_dp_start_link_train] clock recovery OK [ 674.264173] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 674.264406] [drm:intel_edp_backlight_on] [ 674.264408] [drm:intel_panel_enable_backlight] pipe A [ 674.264414] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 674.264420] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 674.264424] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 674.298933] [drm:intel_update_fbc] disabled per chip default [ 674.298936] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 674.298940] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 674.298941] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 674.298943] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 674.298944] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 674.298946] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 674.298947] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 674.298949] [drm:check_crtc_state] [CRTC:8] [ 674.298958] [drm:check_crtc_state] [CRTC:12] [ 674.298960] [drm:check_crtc_state] [CRTC:16] [ 674.298961] [drm:check_shared_dpll_state] WRPLL 1 [ 674.298963] [drm:check_shared_dpll_state] WRPLL 2 [ 674.298967] [drm:drm_mode_setcrtc] [CRTC:8] [ 674.298969] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 674.298971] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 674.298973] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 674.298974] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 674.298975] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 674.298977] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 674.298979] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 674.314391] [drm:intel_edp_backlight_off] [ 674.515047] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 674.533204] [drm:intel_edp_panel_off] Turn eDP power off [ 674.533208] [drm:wait_panel_off] Wait for panel power off time [ 674.533212] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 674.588083] [drm:wait_panel_status] Wait complete [ 674.588090] [drm:intel_update_fbc] no output, disabling [ 674.588094] [drm:intel_display_power_put] disabling always-on [ 674.588097] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 674.588099] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 674.588101] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 674.588102] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 674.588107] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 674.588108] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 674.588110] [drm:check_crtc_state] [CRTC:8] [ 674.588112] [drm:check_crtc_state] [CRTC:12] [ 674.588113] [drm:check_crtc_state] [CRTC:16] [ 674.588114] [drm:check_shared_dpll_state] WRPLL 1 [ 674.588116] [drm:check_shared_dpll_state] WRPLL 2 [ 674.588121] [drm:drm_mode_setcrtc] [CRTC:12] [ 674.588122] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 674.588124] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 674.588127] [drm:drm_mode_setcrtc] [CRTC:16] [ 674.588128] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 674.588130] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 674.588132] [drm:drm_mode_setcrtc] [CRTC:8] [ 674.588135] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 674.588137] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 674.588139] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 674.588141] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 674.588142] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 674.588144] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 674.588145] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 674.588147] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 674.588149] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 674.588151] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 674.588153] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 674.588158] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 674.588159] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 674.588162] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 674.588163] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 674.588165] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 674.588166] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 674.588168] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 674.588170] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 674.588172] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 674.588173] [drm:intel_dump_pipe_config] requested mode: [ 674.588176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 674.588178] [drm:intel_dump_pipe_config] adjusted mode: [ 674.588180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 674.588182] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 674.588184] [drm:intel_dump_pipe_config] port clock: 270000 [ 674.588185] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 674.588187] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 674.588188] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 674.588190] [drm:intel_dump_pipe_config] ips: 1 [ 674.588191] [drm:intel_dump_pipe_config] double wide: 0 [ 674.588194] [drm:intel_display_power_get] enabling always-on [ 674.588206] [drm:intel_edp_panel_on] Turn eDP power on [ 674.588210] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 675.134368] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 675.156377] [drm:wait_panel_status] Wait complete [ 675.156381] [drm:wait_panel_on] Wait for panel power on [ 675.156385] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 675.365485] [drm:wait_panel_status] Wait complete [ 675.365489] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 675.365495] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 675.366541] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 675.366983] [drm:intel_dp_start_link_train] clock recovery OK [ 675.367726] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 675.367959] [drm:intel_edp_backlight_on] [ 675.367961] [drm:intel_panel_enable_backlight] pipe A [ 675.367968] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 675.367973] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 675.367978] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 675.402503] [drm:intel_update_fbc] disabled per chip default [ 675.402507] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 675.402509] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 675.402511] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 675.402513] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 675.402514] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 675.402516] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 675.402517] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 675.402519] [drm:check_crtc_state] [CRTC:8] [ 675.402528] [drm:check_crtc_state] [CRTC:12] [ 675.402530] [drm:check_crtc_state] [CRTC:16] [ 675.402531] [drm:check_shared_dpll_state] WRPLL 1 [ 675.402533] [drm:check_shared_dpll_state] WRPLL 2 [ 675.402537] [drm:drm_mode_setcrtc] [CRTC:8] [ 675.402539] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 675.402541] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 675.402542] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 675.402544] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 675.402545] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 675.402547] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 675.402549] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 675.417943] [drm:intel_edp_backlight_off] [ 675.618616] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 675.636773] [drm:intel_edp_panel_off] Turn eDP power off [ 675.636777] [drm:wait_panel_off] Wait for panel power off time [ 675.636780] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 675.691654] [drm:wait_panel_status] Wait complete [ 675.691661] [drm:intel_update_fbc] no output, disabling [ 675.691664] [drm:intel_display_power_put] disabling always-on [ 675.691667] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 675.691668] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 675.691670] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 675.691671] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 675.691676] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 675.691678] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 675.691679] [drm:check_crtc_state] [CRTC:8] [ 675.691681] [drm:check_crtc_state] [CRTC:12] [ 675.691682] [drm:check_crtc_state] [CRTC:16] [ 675.691683] [drm:check_shared_dpll_state] WRPLL 1 [ 675.691685] [drm:check_shared_dpll_state] WRPLL 2 [ 675.691689] [drm:drm_mode_setcrtc] [CRTC:12] [ 675.691690] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 675.691692] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 675.691695] [drm:drm_mode_setcrtc] [CRTC:16] [ 675.691696] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 675.691698] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 675.691700] [drm:drm_mode_setcrtc] [CRTC:8] [ 675.691703] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 675.691705] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 675.691706] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 675.691708] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 675.691709] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 675.691711] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 675.691712] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 675.691714] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 675.691716] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 675.691718] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 675.691720] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 675.691725] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 675.691726] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 675.691728] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 675.691730] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 675.691731] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 675.691733] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 675.691735] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 675.691737] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 675.691739] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 675.691740] [drm:intel_dump_pipe_config] requested mode: [ 675.691743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 675.691744] [drm:intel_dump_pipe_config] adjusted mode: [ 675.691747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 675.691749] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 675.691750] [drm:intel_dump_pipe_config] port clock: 270000 [ 675.691752] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 675.691754] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 675.691755] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 675.691757] [drm:intel_dump_pipe_config] ips: 1 [ 675.691758] [drm:intel_dump_pipe_config] double wide: 0 [ 675.691760] [drm:intel_display_power_get] enabling always-on [ 675.691773] [drm:intel_edp_panel_on] Turn eDP power on [ 675.691777] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 676.237940] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 676.259947] [drm:wait_panel_status] Wait complete [ 676.259952] [drm:wait_panel_on] Wait for panel power on [ 676.259955] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 676.469055] [drm:wait_panel_status] Wait complete [ 676.469059] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 676.469066] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 676.470117] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 676.470558] [drm:intel_dp_start_link_train] clock recovery OK [ 676.471302] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 676.471535] [drm:intel_edp_backlight_on] [ 676.471537] [drm:intel_panel_enable_backlight] pipe A [ 676.471543] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 676.471549] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 676.471553] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 676.504845] [drm:intel_update_fbc] disabled per chip default [ 676.504849] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 676.504852] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 676.504854] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 676.504857] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 676.504858] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 676.504859] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 676.504861] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 676.504862] [drm:check_crtc_state] [CRTC:8] [ 676.504868] [drm:check_crtc_state] [CRTC:12] [ 676.504870] [drm:check_crtc_state] [CRTC:16] [ 676.504871] [drm:check_shared_dpll_state] WRPLL 1 [ 676.504873] [drm:check_shared_dpll_state] WRPLL 2 [ 676.504877] [drm:drm_mode_setcrtc] [CRTC:8] [ 676.504879] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 676.504881] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 676.504883] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 676.504884] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 676.504885] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 676.504887] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 676.504889] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 676.521518] [drm:intel_edp_backlight_off] [ 676.722185] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 676.740344] [drm:intel_edp_panel_off] Turn eDP power off [ 676.740348] [drm:wait_panel_off] Wait for panel power off time [ 676.740351] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 676.795224] [drm:wait_panel_status] Wait complete [ 676.795230] [drm:intel_update_fbc] no output, disabling [ 676.795233] [drm:intel_display_power_put] disabling always-on [ 676.795236] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 676.795238] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 676.795240] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 676.795245] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 676.795246] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 676.795247] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 676.795249] [drm:check_crtc_state] [CRTC:8] [ 676.795250] [drm:check_crtc_state] [CRTC:12] [ 676.795252] [drm:check_crtc_state] [CRTC:16] [ 676.795253] [drm:check_shared_dpll_state] WRPLL 1 [ 676.795255] [drm:check_shared_dpll_state] WRPLL 2 [ 676.795258] [drm:drm_mode_setcrtc] [CRTC:12] [ 676.795260] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 676.795262] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 676.795264] [drm:drm_mode_setcrtc] [CRTC:16] [ 676.795266] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 676.795267] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 676.795270] [drm:drm_mode_setcrtc] [CRTC:8] [ 676.795272] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 676.795274] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 676.795276] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 676.795278] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 676.795279] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 676.795281] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 676.795282] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 676.795284] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 676.795286] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 676.795288] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 676.795290] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 676.795295] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 676.795296] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 676.795298] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 676.795300] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 676.795301] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 676.795303] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 676.795305] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 676.795307] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 676.795309] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 676.795310] [drm:intel_dump_pipe_config] requested mode: [ 676.795313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 676.795314] [drm:intel_dump_pipe_config] adjusted mode: [ 676.795317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 676.795319] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 676.795320] [drm:intel_dump_pipe_config] port clock: 270000 [ 676.795322] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 676.795324] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 676.795325] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 676.795326] [drm:intel_dump_pipe_config] ips: 1 [ 676.795328] [drm:intel_dump_pipe_config] double wide: 0 [ 676.795330] [drm:intel_display_power_get] enabling always-on [ 676.795342] [drm:intel_edp_panel_on] Turn eDP power on [ 676.795346] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 677.341508] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 677.352511] [drm:wait_panel_status] Wait complete [ 677.352515] [drm:wait_panel_on] Wait for panel power on [ 677.352519] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 677.561619] [drm:wait_panel_status] Wait complete [ 677.561627] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 677.561634] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 677.562687] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 677.563128] [drm:intel_dp_start_link_train] clock recovery OK [ 677.563875] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 677.564108] [drm:intel_edp_backlight_on] [ 677.564110] [drm:intel_panel_enable_backlight] pipe A [ 677.564117] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 677.564122] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 677.564126] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 677.598638] [drm:intel_update_fbc] disabled per chip default [ 677.598641] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 677.598644] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 677.598646] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 677.598648] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 677.598649] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 677.598650] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 677.598652] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 677.598653] [drm:check_crtc_state] [CRTC:8] [ 677.598663] [drm:check_crtc_state] [CRTC:12] [ 677.598664] [drm:check_crtc_state] [CRTC:16] [ 677.598666] [drm:check_shared_dpll_state] WRPLL 1 [ 677.598667] [drm:check_shared_dpll_state] WRPLL 2 [ 677.598672] [drm:drm_mode_setcrtc] [CRTC:8] [ 677.598674] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 677.598676] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 677.598677] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 677.598679] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 677.598680] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 677.598682] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 677.598684] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 677.614093] [drm:intel_edp_backlight_off] [ 677.814750] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 677.832907] [drm:intel_edp_panel_off] Turn eDP power off [ 677.832911] [drm:wait_panel_off] Wait for panel power off time [ 677.832915] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 677.887788] [drm:wait_panel_status] Wait complete [ 677.887794] [drm:intel_update_fbc] no output, disabling [ 677.887797] [drm:intel_display_power_put] disabling always-on [ 677.887800] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 677.887802] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 677.887804] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 677.887809] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 677.887810] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 677.887811] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 677.887813] [drm:check_crtc_state] [CRTC:8] [ 677.887815] [drm:check_crtc_state] [CRTC:12] [ 677.887816] [drm:check_crtc_state] [CRTC:16] [ 677.887817] [drm:check_shared_dpll_state] WRPLL 1 [ 677.887819] [drm:check_shared_dpll_state] WRPLL 2 [ 677.887822] [drm:drm_mode_setcrtc] [CRTC:12] [ 677.887824] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 677.887826] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 677.887828] [drm:drm_mode_setcrtc] [CRTC:16] [ 677.887830] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 677.887831] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 677.887834] [drm:drm_mode_setcrtc] [CRTC:8] [ 677.887836] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 677.887838] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 677.887840] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 677.887841] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 677.887843] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 677.887845] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 677.887846] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 677.887847] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 677.887849] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 677.887851] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 677.887854] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 677.887858] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 677.887860] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 677.887862] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 677.887864] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 677.887865] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 677.887866] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 677.887868] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 677.887871] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 677.887873] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 677.887874] [drm:intel_dump_pipe_config] requested mode: [ 677.887877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 677.887878] [drm:intel_dump_pipe_config] adjusted mode: [ 677.887880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 677.887883] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 677.887884] [drm:intel_dump_pipe_config] port clock: 270000 [ 677.887886] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 677.887887] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 677.887889] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 677.887890] [drm:intel_dump_pipe_config] ips: 1 [ 677.887892] [drm:intel_dump_pipe_config] double wide: 0 [ 677.887894] [drm:intel_display_power_get] enabling always-on [ 677.887907] [drm:intel_edp_panel_on] Turn eDP power on [ 677.887910] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 678.434074] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 678.456082] [drm:wait_panel_status] Wait complete [ 678.456086] [drm:wait_panel_on] Wait for panel power on [ 678.456089] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 678.665189] [drm:wait_panel_status] Wait complete [ 678.665193] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 678.665200] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 678.666253] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 678.666694] [drm:intel_dp_start_link_train] clock recovery OK [ 678.667437] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 678.667670] [drm:intel_edp_backlight_on] [ 678.667671] [drm:intel_panel_enable_backlight] pipe A [ 678.667678] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 678.667683] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 678.667687] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 678.700980] [drm:intel_update_fbc] disabled per chip default [ 678.700984] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 678.700988] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 678.700990] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 678.700992] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 678.700993] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 678.700994] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 678.700995] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 678.700997] [drm:check_crtc_state] [CRTC:8] [ 678.701003] [drm:check_crtc_state] [CRTC:12] [ 678.701004] [drm:check_crtc_state] [CRTC:16] [ 678.701006] [drm:check_shared_dpll_state] WRPLL 1 [ 678.701007] [drm:check_shared_dpll_state] WRPLL 2 [ 678.701012] [drm:drm_mode_setcrtc] [CRTC:8] [ 678.701013] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 678.701015] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 678.701017] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 678.701018] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 678.701020] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 678.701021] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 678.701023] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 678.717653] [drm:intel_edp_backlight_off] [ 678.918320] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 678.936477] [drm:intel_edp_panel_off] Turn eDP power off [ 678.936481] [drm:wait_panel_off] Wait for panel power off time [ 678.936485] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 678.991358] [drm:wait_panel_status] Wait complete [ 678.991365] [drm:intel_update_fbc] no output, disabling [ 678.991368] [drm:intel_display_power_put] disabling always-on [ 678.991371] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 678.991372] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 678.991378] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 678.991379] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 678.991381] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 678.991382] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 678.991383] [drm:check_crtc_state] [CRTC:8] [ 678.991385] [drm:check_crtc_state] [CRTC:12] [ 678.991386] [drm:check_crtc_state] [CRTC:16] [ 678.991388] [drm:check_shared_dpll_state] WRPLL 1 [ 678.991389] [drm:check_shared_dpll_state] WRPLL 2 [ 678.991393] [drm:drm_mode_setcrtc] [CRTC:12] [ 678.991394] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 678.991396] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 678.991399] [drm:drm_mode_setcrtc] [CRTC:16] [ 678.991400] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 678.991402] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 678.991404] [drm:drm_mode_setcrtc] [CRTC:8] [ 678.991407] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 678.991409] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 678.991410] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 678.991412] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 678.991414] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 678.991415] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 678.991417] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 678.991418] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 678.991420] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 678.991422] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 678.991425] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 678.991429] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 678.991431] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 678.991433] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 678.991434] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 678.991436] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 678.991437] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 678.991439] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 678.991441] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 678.991443] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 678.991445] [drm:intel_dump_pipe_config] requested mode: [ 678.991447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 678.991449] [drm:intel_dump_pipe_config] adjusted mode: [ 678.991451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 678.991453] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 678.991455] [drm:intel_dump_pipe_config] port clock: 270000 [ 678.991456] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 678.991458] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 678.991459] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 678.991461] [drm:intel_dump_pipe_config] ips: 1 [ 678.991462] [drm:intel_dump_pipe_config] double wide: 0 [ 678.991464] [drm:intel_display_power_get] enabling always-on [ 678.991477] [drm:intel_edp_panel_on] Turn eDP power on [ 678.991481] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 679.537642] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 679.559652] [drm:wait_panel_status] Wait complete [ 679.559656] [drm:wait_panel_on] Wait for panel power on [ 679.559659] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 679.768760] [drm:wait_panel_status] Wait complete [ 679.768764] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 679.768770] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 679.769823] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 679.770265] [drm:intel_dp_start_link_train] clock recovery OK [ 679.771008] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 679.771241] [drm:intel_edp_backlight_on] [ 679.771243] [drm:intel_panel_enable_backlight] pipe A [ 679.771250] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 679.771255] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 679.771259] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 679.804551] [drm:intel_update_fbc] disabled per chip default [ 679.804555] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 679.804559] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 679.804561] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 679.804563] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 679.804564] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 679.804566] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 679.804567] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 679.804568] [drm:check_crtc_state] [CRTC:8] [ 679.804574] [drm:check_crtc_state] [CRTC:12] [ 679.804576] [drm:check_crtc_state] [CRTC:16] [ 679.804577] [drm:check_shared_dpll_state] WRPLL 1 [ 679.804579] [drm:check_shared_dpll_state] WRPLL 2 [ 679.804583] [drm:drm_mode_setcrtc] [CRTC:8] [ 679.804584] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 679.804586] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 679.804588] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 679.804589] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 679.804591] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 679.804592] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 679.804594] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 679.821225] [drm:intel_edp_backlight_off] [ 680.021891] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 680.040047] [drm:intel_edp_panel_off] Turn eDP power off [ 680.040051] [drm:wait_panel_off] Wait for panel power off time [ 680.040055] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 680.094932] [drm:wait_panel_status] Wait complete [ 680.094941] [drm:intel_update_fbc] no output, disabling [ 680.094946] [drm:intel_display_power_put] disabling always-on [ 680.094950] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 680.094952] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 680.094953] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 680.094955] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 680.094956] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 680.094957] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 680.094959] [drm:check_crtc_state] [CRTC:8] [ 680.094961] [drm:check_crtc_state] [CRTC:12] [ 680.094962] [drm:check_crtc_state] [CRTC:16] [ 680.094964] [drm:check_shared_dpll_state] WRPLL 1 [ 680.094965] [drm:check_shared_dpll_state] WRPLL 2 [ 680.094972] [drm:drm_mode_setcrtc] [CRTC:12] [ 680.094973] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 680.094976] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 680.094979] [drm:drm_mode_setcrtc] [CRTC:16] [ 680.094980] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 680.094982] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 680.094985] [drm:drm_mode_setcrtc] [CRTC:8] [ 680.094987] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 680.094989] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 680.094991] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 680.094993] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 680.094994] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 680.094996] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 680.094998] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 680.094999] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 680.095002] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 680.095004] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 680.095006] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 680.095011] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 680.095013] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 680.095015] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 680.095017] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 680.095018] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 680.095020] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 680.095022] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 680.095024] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 680.095026] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 680.095027] [drm:intel_dump_pipe_config] requested mode: [ 680.095030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 680.095031] [drm:intel_dump_pipe_config] adjusted mode: [ 680.095034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 680.095036] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 680.095038] [drm:intel_dump_pipe_config] port clock: 270000 [ 680.095039] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 680.095041] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 680.095043] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 680.095044] [drm:intel_dump_pipe_config] ips: 1 [ 680.095045] [drm:intel_dump_pipe_config] double wide: 0 [ 680.095048] [drm:intel_display_power_get] enabling always-on [ 680.095062] [drm:intel_edp_panel_on] Turn eDP power on [ 680.095065] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 680.641215] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 680.663222] [drm:wait_panel_status] Wait complete [ 680.663226] [drm:wait_panel_on] Wait for panel power on [ 680.663229] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 680.872330] [drm:wait_panel_status] Wait complete [ 680.872334] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 680.872340] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 680.872491] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 680.872497] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 680.873105] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 680.873111] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 680.873415] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 680.873856] [drm:intel_dp_start_link_train] clock recovery OK [ 680.874603] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 680.874832] [drm:intel_edp_backlight_on] [ 680.874833] [drm:intel_panel_enable_backlight] pipe A [ 680.874840] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 680.874849] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 680.874853] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 680.908142] [drm:intel_update_fbc] disabled per chip default [ 680.908146] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 680.908149] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 680.908150] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 680.908152] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 680.908154] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 680.908155] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 680.908156] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 680.908158] [drm:check_crtc_state] [CRTC:8] [ 680.908164] [drm:check_crtc_state] [CRTC:12] [ 680.908166] [drm:check_crtc_state] [CRTC:16] [ 680.908167] [drm:check_shared_dpll_state] WRPLL 1 [ 680.908169] [drm:check_shared_dpll_state] WRPLL 2 [ 680.908173] [drm:drm_mode_setcrtc] [CRTC:8] [ 680.908175] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 680.908177] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 680.908178] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 680.908179] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 680.908181] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 680.908183] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 680.908185] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 680.924819] [drm:intel_edp_backlight_off] [ 681.125459] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 681.143617] [drm:intel_edp_panel_off] Turn eDP power off [ 681.143622] [drm:wait_panel_off] Wait for panel power off time [ 681.143625] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 681.198499] [drm:wait_panel_status] Wait complete [ 681.198505] [drm:intel_update_fbc] no output, disabling [ 681.198508] [drm:intel_display_power_put] disabling always-on [ 681.198512] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 681.198517] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 681.198519] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 681.198520] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 681.198521] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 681.198523] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 681.198524] [drm:check_crtc_state] [CRTC:8] [ 681.198526] [drm:check_crtc_state] [CRTC:12] [ 681.198527] [drm:check_crtc_state] [CRTC:16] [ 681.198528] [drm:check_shared_dpll_state] WRPLL 1 [ 681.198530] [drm:check_shared_dpll_state] WRPLL 2 [ 681.198534] [drm:drm_mode_setcrtc] [CRTC:12] [ 681.198535] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 681.198537] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 681.198540] [drm:drm_mode_setcrtc] [CRTC:16] [ 681.198541] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 681.198543] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 681.198545] [drm:drm_mode_setcrtc] [CRTC:8] [ 681.198548] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 681.198550] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 681.198551] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 681.198553] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 681.198555] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 681.198556] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 681.198558] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 681.198559] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 681.198561] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 681.198563] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 681.198566] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 681.198570] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 681.198572] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 681.198574] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 681.198575] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 681.198577] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 681.198578] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 681.198580] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 681.198582] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 681.198584] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 681.198586] [drm:intel_dump_pipe_config] requested mode: [ 681.198589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 681.198590] [drm:intel_dump_pipe_config] adjusted mode: [ 681.198592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 681.198595] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 681.198596] [drm:intel_dump_pipe_config] port clock: 270000 [ 681.198597] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 681.198599] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 681.198601] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 681.198602] [drm:intel_dump_pipe_config] ips: 1 [ 681.198603] [drm:intel_dump_pipe_config] double wide: 0 [ 681.198606] [drm:intel_display_power_get] enabling always-on [ 681.198618] [drm:intel_edp_panel_on] Turn eDP power on [ 681.198622] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 681.744783] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 681.755786] [drm:wait_panel_status] Wait complete [ 681.755790] [drm:wait_panel_on] Wait for panel power on [ 681.755793] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 681.964894] [drm:wait_panel_status] Wait complete [ 681.964898] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 681.964905] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 681.965958] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 681.966399] [drm:intel_dp_start_link_train] clock recovery OK [ 681.967146] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 681.967378] [drm:intel_edp_backlight_on] [ 681.967380] [drm:intel_panel_enable_backlight] pipe A [ 681.967386] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 681.967392] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 681.967396] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 682.001912] [drm:intel_update_fbc] disabled per chip default [ 682.001916] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 682.001919] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 682.001920] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 682.001922] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 682.001924] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 682.001925] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 682.001926] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 682.001932] [drm:check_crtc_state] [CRTC:8] [ 682.001938] [drm:check_crtc_state] [CRTC:12] [ 682.001939] [drm:check_crtc_state] [CRTC:16] [ 682.001941] [drm:check_shared_dpll_state] WRPLL 1 [ 682.001942] [drm:check_shared_dpll_state] WRPLL 2 [ 682.001947] [drm:drm_mode_setcrtc] [CRTC:8] [ 682.001948] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 682.001950] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 682.001952] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 682.001953] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 682.001954] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 682.001956] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 682.001958] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 682.017362] [drm:intel_edp_backlight_off] [ 682.218024] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 682.236182] [drm:intel_edp_panel_off] Turn eDP power off [ 682.236186] [drm:wait_panel_off] Wait for panel power off time [ 682.236190] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 682.291063] [drm:wait_panel_status] Wait complete [ 682.291070] [drm:intel_update_fbc] no output, disabling [ 682.291073] [drm:intel_display_power_put] disabling always-on [ 682.291080] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 682.291081] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 682.291083] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 682.291084] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 682.291086] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 682.291087] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 682.291088] [drm:check_crtc_state] [CRTC:8] [ 682.291090] [drm:check_crtc_state] [CRTC:12] [ 682.291091] [drm:check_crtc_state] [CRTC:16] [ 682.291093] [drm:check_shared_dpll_state] WRPLL 1 [ 682.291094] [drm:check_shared_dpll_state] WRPLL 2 [ 682.291098] [drm:drm_mode_setcrtc] [CRTC:12] [ 682.291100] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 682.291102] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 682.291104] [drm:drm_mode_setcrtc] [CRTC:16] [ 682.291105] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 682.291107] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 682.291110] [drm:drm_mode_setcrtc] [CRTC:8] [ 682.291112] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 682.291114] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 682.291116] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 682.291117] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 682.291119] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 682.291120] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 682.291122] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 682.291123] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 682.291125] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 682.291127] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 682.291130] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 682.291134] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 682.291135] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 682.291138] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 682.291139] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 682.291141] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 682.291142] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 682.291144] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 682.291146] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 682.291148] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 682.291149] [drm:intel_dump_pipe_config] requested mode: [ 682.291152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 682.291154] [drm:intel_dump_pipe_config] adjusted mode: [ 682.291156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 682.291158] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 682.291160] [drm:intel_dump_pipe_config] port clock: 270000 [ 682.291161] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 682.291163] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 682.291165] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 682.291166] [drm:intel_dump_pipe_config] ips: 1 [ 682.291167] [drm:intel_dump_pipe_config] double wide: 0 [ 682.291169] [drm:intel_display_power_get] enabling always-on [ 682.291182] [drm:intel_edp_panel_on] Turn eDP power on [ 682.291186] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 682.837347] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 682.859357] [drm:wait_panel_status] Wait complete [ 682.859361] [drm:wait_panel_on] Wait for panel power on [ 682.859365] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 683.068464] [drm:wait_panel_status] Wait complete [ 683.068469] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 683.068479] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 683.069527] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 683.069968] [drm:intel_dp_start_link_train] clock recovery OK [ 683.070715] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 683.070949] [drm:intel_edp_backlight_on] [ 683.070951] [drm:intel_panel_enable_backlight] pipe A [ 683.070957] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 683.070963] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 683.070967] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 683.105482] [drm:intel_update_fbc] disabled per chip default [ 683.105485] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 683.105488] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 683.105490] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 683.105492] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 683.105493] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 683.105494] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 683.105499] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 683.105501] [drm:check_crtc_state] [CRTC:8] [ 683.105507] [drm:check_crtc_state] [CRTC:12] [ 683.105508] [drm:check_crtc_state] [CRTC:16] [ 683.105510] [drm:check_shared_dpll_state] WRPLL 1 [ 683.105511] [drm:check_shared_dpll_state] WRPLL 2 [ 683.105516] [drm:drm_mode_setcrtc] [CRTC:8] [ 683.105517] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 683.105519] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 683.105521] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 683.105522] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 683.105524] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 683.105526] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 683.105528] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 683.120931] [drm:intel_edp_backlight_off] [ 683.321595] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 683.339752] [drm:intel_edp_panel_off] Turn eDP power off [ 683.339756] [drm:wait_panel_off] Wait for panel power off time [ 683.339760] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 683.394633] [drm:wait_panel_status] Wait complete [ 683.394639] [drm:intel_update_fbc] no output, disabling [ 683.394642] [drm:intel_display_power_put] disabling always-on [ 683.394649] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 683.394651] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 683.394652] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 683.394654] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 683.394655] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 683.394657] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 683.394658] [drm:check_crtc_state] [CRTC:8] [ 683.394660] [drm:check_crtc_state] [CRTC:12] [ 683.394661] [drm:check_crtc_state] [CRTC:16] [ 683.394662] [drm:check_shared_dpll_state] WRPLL 1 [ 683.394664] [drm:check_shared_dpll_state] WRPLL 2 [ 683.394668] [drm:drm_mode_setcrtc] [CRTC:12] [ 683.394669] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 683.394671] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 683.394674] [drm:drm_mode_setcrtc] [CRTC:16] [ 683.394675] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 683.394677] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 683.394679] [drm:drm_mode_setcrtc] [CRTC:8] [ 683.394681] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 683.394683] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 683.394685] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 683.394687] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 683.394688] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 683.394690] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 683.394691] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 683.394693] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 683.394695] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 683.394697] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 683.394699] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 683.394704] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 683.394705] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 683.394707] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 683.394709] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 683.394710] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 683.394712] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 683.394714] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 683.394716] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 683.394718] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 683.394719] [drm:intel_dump_pipe_config] requested mode: [ 683.394722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 683.394723] [drm:intel_dump_pipe_config] adjusted mode: [ 683.394726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 683.394728] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 683.394730] [drm:intel_dump_pipe_config] port clock: 270000 [ 683.394731] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 683.394733] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 683.394734] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 683.394736] [drm:intel_dump_pipe_config] ips: 1 [ 683.394737] [drm:intel_dump_pipe_config] double wide: 0 [ 683.394739] [drm:intel_display_power_get] enabling always-on [ 683.394752] [drm:intel_edp_panel_on] Turn eDP power on [ 683.394755] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 683.940917] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 683.962927] [drm:wait_panel_status] Wait complete [ 683.962931] [drm:wait_panel_on] Wait for panel power on [ 683.962934] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 684.172034] [drm:wait_panel_status] Wait complete [ 684.172042] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 684.172052] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 684.173100] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 684.173541] [drm:intel_dp_start_link_train] clock recovery OK [ 684.174286] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 684.174519] [drm:intel_edp_backlight_on] [ 684.174520] [drm:intel_panel_enable_backlight] pipe A [ 684.174527] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 684.174533] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 684.174537] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 684.209052] [drm:intel_update_fbc] disabled per chip default [ 684.209056] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 684.209059] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 684.209061] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 684.209062] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 684.209064] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 684.209069] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 684.209070] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 684.209072] [drm:check_crtc_state] [CRTC:8] [ 684.209078] [drm:check_crtc_state] [CRTC:12] [ 684.209079] [drm:check_crtc_state] [CRTC:16] [ 684.209080] [drm:check_shared_dpll_state] WRPLL 1 [ 684.209082] [drm:check_shared_dpll_state] WRPLL 2 [ 684.209086] [drm:drm_mode_setcrtc] [CRTC:8] [ 684.209088] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 684.209090] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 684.209091] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 684.209093] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 684.209094] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 684.209096] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 684.209098] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 684.224502] [drm:intel_edp_backlight_off] [ 684.425164] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 684.443324] [drm:intel_edp_panel_off] Turn eDP power off [ 684.443328] [drm:wait_panel_off] Wait for panel power off time [ 684.443332] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 684.498203] [drm:wait_panel_status] Wait complete [ 684.498210] [drm:intel_update_fbc] no output, disabling [ 684.498213] [drm:intel_display_power_put] disabling always-on [ 684.498221] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 684.498223] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 684.498224] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 684.498226] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 684.498227] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 684.498228] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 684.498230] [drm:check_crtc_state] [CRTC:8] [ 684.498231] [drm:check_crtc_state] [CRTC:12] [ 684.498233] [drm:check_crtc_state] [CRTC:16] [ 684.498234] [drm:check_shared_dpll_state] WRPLL 1 [ 684.498236] [drm:check_shared_dpll_state] WRPLL 2 [ 684.498240] [drm:drm_mode_setcrtc] [CRTC:12] [ 684.498242] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 684.498244] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 684.498247] [drm:drm_mode_setcrtc] [CRTC:16] [ 684.498248] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 684.498250] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 684.498252] [drm:drm_mode_setcrtc] [CRTC:8] [ 684.498255] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 684.498257] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 684.498259] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 684.498260] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 684.498262] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 684.498264] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 684.498265] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 684.498266] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 684.498269] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 684.498271] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 684.498273] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 684.498278] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 684.498279] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 684.498281] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 684.498283] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 684.498284] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 684.498286] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 684.498288] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 684.498290] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 684.498292] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 684.498293] [drm:intel_dump_pipe_config] requested mode: [ 684.498296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 684.498297] [drm:intel_dump_pipe_config] adjusted mode: [ 684.498300] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 684.498302] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 684.498303] [drm:intel_dump_pipe_config] port clock: 270000 [ 684.498305] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 684.498307] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 684.498308] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 684.498310] [drm:intel_dump_pipe_config] ips: 1 [ 684.498311] [drm:intel_dump_pipe_config] double wide: 0 [ 684.498313] [drm:intel_display_power_get] enabling always-on [ 684.498326] [drm:intel_edp_panel_on] Turn eDP power on [ 684.498330] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 685.044489] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 685.055491] [drm:wait_panel_status] Wait complete [ 685.055495] [drm:wait_panel_on] Wait for panel power on [ 685.055499] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 685.264599] [drm:wait_panel_status] Wait complete [ 685.264603] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 685.264613] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 685.265662] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 685.266103] [drm:intel_dp_start_link_train] clock recovery OK [ 685.266849] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 685.267082] [drm:intel_edp_backlight_on] [ 685.267084] [drm:intel_panel_enable_backlight] pipe A [ 685.267091] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 685.267096] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 685.267100] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 685.301617] [drm:intel_update_fbc] disabled per chip default [ 685.301621] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 685.301624] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 685.301626] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 685.301627] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 685.301632] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 685.301634] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 685.301635] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 685.301637] [drm:check_crtc_state] [CRTC:8] [ 685.301643] [drm:check_crtc_state] [CRTC:12] [ 685.301644] [drm:check_crtc_state] [CRTC:16] [ 685.301645] [drm:check_shared_dpll_state] WRPLL 1 [ 685.301647] [drm:check_shared_dpll_state] WRPLL 2 [ 685.301651] [drm:drm_mode_setcrtc] [CRTC:8] [ 685.301653] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 685.301655] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 685.301657] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 685.301658] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 685.301659] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 685.301661] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 685.301663] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 685.317066] [drm:intel_edp_backlight_off] [ 685.517729] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 685.535887] [drm:intel_edp_panel_off] Turn eDP power off [ 685.535891] [drm:wait_panel_off] Wait for panel power off time [ 685.535894] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 685.590767] [drm:wait_panel_status] Wait complete [ 685.590774] [drm:intel_update_fbc] no output, disabling [ 685.590777] [drm:intel_display_power_put] disabling always-on [ 685.590784] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 685.590786] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 685.590787] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 685.590788] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 685.590790] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 685.590791] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 685.590792] [drm:check_crtc_state] [CRTC:8] [ 685.590794] [drm:check_crtc_state] [CRTC:12] [ 685.590795] [drm:check_crtc_state] [CRTC:16] [ 685.590797] [drm:check_shared_dpll_state] WRPLL 1 [ 685.590798] [drm:check_shared_dpll_state] WRPLL 2 [ 685.590802] [drm:drm_mode_setcrtc] [CRTC:12] [ 685.590804] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 685.590806] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 685.590808] [drm:drm_mode_setcrtc] [CRTC:16] [ 685.590810] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 685.590811] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 685.590814] [drm:drm_mode_setcrtc] [CRTC:8] [ 685.590816] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 685.590818] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 685.590820] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 685.590822] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 685.590823] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 685.590825] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 685.590826] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 685.590828] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 685.590830] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 685.590832] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 685.590834] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 685.590839] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 685.590840] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 685.590842] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 685.590844] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 685.590845] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 685.590847] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 685.590849] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 685.590851] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 685.590853] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 685.590854] [drm:intel_dump_pipe_config] requested mode: [ 685.590857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 685.590858] [drm:intel_dump_pipe_config] adjusted mode: [ 685.590861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 685.590863] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 685.590864] [drm:intel_dump_pipe_config] port clock: 270000 [ 685.590866] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 685.590868] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 685.590869] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 685.590871] [drm:intel_dump_pipe_config] ips: 1 [ 685.590872] [drm:intel_dump_pipe_config] double wide: 0 [ 685.590874] [drm:intel_display_power_get] enabling always-on [ 685.590887] [drm:intel_edp_panel_on] Turn eDP power on [ 685.590890] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 686.137052] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 686.159061] [drm:wait_panel_status] Wait complete [ 686.159065] [drm:wait_panel_on] Wait for panel power on [ 686.159069] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 686.368169] [drm:wait_panel_status] Wait complete [ 686.368173] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 686.368183] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 686.369232] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 686.369673] [drm:intel_dp_start_link_train] clock recovery OK [ 686.370418] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 686.370651] [drm:intel_edp_backlight_on] [ 686.370653] [drm:intel_panel_enable_backlight] pipe A [ 686.370660] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 686.370665] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 686.370669] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 686.405187] [drm:intel_update_fbc] disabled per chip default [ 686.405190] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 686.405193] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 686.405195] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 686.405197] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 686.405202] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 686.405203] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 686.405204] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 686.405206] [drm:check_crtc_state] [CRTC:8] [ 686.405212] [drm:check_crtc_state] [CRTC:12] [ 686.405213] [drm:check_crtc_state] [CRTC:16] [ 686.405215] [drm:check_shared_dpll_state] WRPLL 1 [ 686.405216] [drm:check_shared_dpll_state] WRPLL 2 [ 686.405221] [drm:drm_mode_setcrtc] [CRTC:8] [ 686.405223] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 686.405225] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 686.405226] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 686.405228] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 686.405229] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 686.405231] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 686.405233] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 686.420635] [drm:intel_edp_backlight_off] [ 686.621300] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 686.639456] [drm:intel_edp_panel_off] Turn eDP power off [ 686.639460] [drm:wait_panel_off] Wait for panel power off time [ 686.639464] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 686.694337] [drm:wait_panel_status] Wait complete [ 686.694344] [drm:intel_update_fbc] no output, disabling [ 686.694351] [drm:intel_display_power_put] disabling always-on [ 686.694354] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 686.694356] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 686.694357] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 686.694359] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 686.694360] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 686.694361] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 686.694363] [drm:check_crtc_state] [CRTC:8] [ 686.694364] [drm:check_crtc_state] [CRTC:12] [ 686.694366] [drm:check_crtc_state] [CRTC:16] [ 686.694367] [drm:check_shared_dpll_state] WRPLL 1 [ 686.694369] [drm:check_shared_dpll_state] WRPLL 2 [ 686.694372] [drm:drm_mode_setcrtc] [CRTC:12] [ 686.694374] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 686.694376] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 686.694378] [drm:drm_mode_setcrtc] [CRTC:16] [ 686.694379] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 686.694381] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 686.694384] [drm:drm_mode_setcrtc] [CRTC:8] [ 686.694386] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1] [ 686.694388] [drm:intel_crtc_set_config] [CRTC:8] [FB:36] #connectors=1 (x y) (0 0) [ 686.694390] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 686.694392] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 686.694393] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 686.694395] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 686.694396] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 686.694398] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 686.694400] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 686.694402] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 686.694404] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 686.694408] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 686.694410] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 686.694412] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 686.694414] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 686.694415] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 686.694417] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 686.694419] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 686.694421] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 686.694423] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 686.694424] [drm:intel_dump_pipe_config] requested mode: [ 686.694427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 686.694428] [drm:intel_dump_pipe_config] adjusted mode: [ 686.694430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 686.694433] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 686.694434] [drm:intel_dump_pipe_config] port clock: 270000 [ 686.694436] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 686.694437] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 686.694439] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 686.694440] [drm:intel_dump_pipe_config] ips: 1 [ 686.694442] [drm:intel_dump_pipe_config] double wide: 0 [ 686.694444] [drm:intel_display_power_get] enabling always-on [ 686.694457] [drm:intel_edp_panel_on] Turn eDP power on [ 686.694460] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 687.240622] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000 [ 687.262631] [drm:wait_panel_status] Wait complete [ 687.262635] [drm:wait_panel_on] Wait for panel power on [ 687.262643] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 687.471739] [drm:wait_panel_status] Wait complete [ 687.471744] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 687.471751] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 687.471900] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 687.471907] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003 [ 687.472514] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 687.472521] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 687.472825] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 687.473267] [drm:intel_dp_start_link_train] clock recovery OK [ 687.474011] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 687.474240] [drm:intel_edp_backlight_on] [ 687.474241] [drm:intel_panel_enable_backlight] pipe A [ 687.474252] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 687.474257] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 687.474262] [drm:ironlake_update_primary_plane] Writing base 0106A000 00000000 0 0 7680 [ 687.508757] [drm:intel_update_fbc] disabled per chip default [ 687.508761] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 687.508764] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 687.508766] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 687.508771] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 687.508772] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 687.508774] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 687.508775] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 687.508776] [drm:check_crtc_state] [CRTC:8] [ 687.508782] [drm:check_crtc_state] [CRTC:12] [ 687.508784] [drm:check_crtc_state] [CRTC:16] [ 687.508785] [drm:check_shared_dpll_state] WRPLL 1 [ 687.508787] [drm:check_shared_dpll_state] WRPLL 2 [ 687.508831] pm_rpm: starting subtest modeset-non-lpsp-stress-no-wait [ 687.508842] [drm:drm_mode_setcrtc] [CRTC:8] [ 687.508844] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 687.508846] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 687.508848] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [NOCRTC] [ 687.508849] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 687.508850] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 687.508852] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 687.508854] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 687.524228] [drm:intel_edp_backlight_off] [ 687.724870] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 687.743026] [drm:intel_edp_panel_off] Turn eDP power off [ 687.743030] [drm:wait_panel_off] Wait for panel power off time [ 687.743034] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 687.797908] [drm:wait_panel_status] Wait complete [ 687.797918] [drm:intel_update_fbc] no output, disabling [ 687.797921] [drm:intel_display_power_put] disabling always-on [ 687.797925] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 687.797926] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 687.797928] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 687.797929] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 687.797930] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 687.797932] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 687.797933] [drm:check_crtc_state] [CRTC:8] [ 687.797935] [drm:check_crtc_state] [CRTC:12] [ 687.797936] [drm:check_crtc_state] [CRTC:16] [ 687.797937] [drm:check_shared_dpll_state] WRPLL 1 [ 687.797939] [drm:check_shared_dpll_state] WRPLL 2 [ 687.797943] [drm:drm_mode_setcrtc] [CRTC:12] [ 687.797945] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 687.797947] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 687.797949] [drm:drm_mode_setcrtc] [CRTC:16] [ 687.797951] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 687.797952] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 687.797955] [drm:drm_mode_setcrtc] Unknown CRTC ID 0 [ 687.798017] pm_rpm: starting subtest modeset-pc8-residency-stress [ 687.798026] [drm:drm_mode_setcrtc] [CRTC:8] [ 687.798027] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 687.798029] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 687.798031] [drm:drm_mode_setcrtc] [CRTC:12] [ 687.798033] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 687.798034] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 687.798037] [drm:drm_mode_setcrtc] [CRTC:16] [ 687.798042] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 687.798044] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 690.474291] [drm:intel_display_power_get] enabling always-on [ 690.474295] [drm:intel_display_power_put] disabling always-on [ 807.920475] pm_rpm: starting subtest modeset-stress-extra-wait [ 807.920490] [drm:drm_mode_setcrtc] [CRTC:8] [ 807.920492] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 807.920495] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 807.920498] [drm:drm_mode_setcrtc] [CRTC:12] [ 807.920499] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 807.920501] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 807.920504] [drm:drm_mode_setcrtc] [CRTC:16] [ 807.920505] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 807.920507] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 817.930272] pm_rpm: starting subtest system-suspend [ 817.930282] [drm:drm_mode_setcrtc] [CRTC:8] [ 817.930284] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 817.930286] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 817.930289] [drm:drm_mode_setcrtc] [CRTC:12] [ 817.930291] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 817.930293] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 817.930295] [drm:drm_mode_setcrtc] [CRTC:16] [ 817.930296] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 817.930298] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 827.940039] pm_rpm: starting subtest gem-execbuf-stress [ 827.940048] [drm:drm_mode_setcrtc] [CRTC:8] [ 827.940050] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 827.940052] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 827.940055] [drm:drm_mode_setcrtc] [CRTC:12] [ 827.940056] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 827.940058] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 827.940060] [drm:drm_mode_setcrtc] [CRTC:16] [ 827.940061] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 827.940063] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 837.949794] pm_rpm: starting subtest gem-execbuf-stress-pc8 [ 837.949803] [drm:drm_mode_setcrtc] [CRTC:8] [ 837.949804] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 837.949806] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 837.949809] [drm:drm_mode_setcrtc] [CRTC:12] [ 837.949810] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 837.949812] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 837.949814] [drm:drm_mode_setcrtc] [CRTC:16] [ 837.949815] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 837.949817] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 847.959550] pm_rpm: starting subtest gem-execbuf-stress-extra-wait [ 847.959560] [drm:drm_mode_setcrtc] [CRTC:8] [ 847.959561] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 847.959564] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 847.959567] [drm:drm_mode_setcrtc] [CRTC:12] [ 847.959568] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 847.959570] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 847.959572] [drm:drm_mode_setcrtc] [CRTC:16] [ 847.959573] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 847.959575] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 857.969418] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [ 857.969420] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 857.969421] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0 [ 857.969422] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 857.969423] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 857.969424] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 857.969425] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 857.969427] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 857.969429] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains [ 857.969432] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz [ 857.969436] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24 [ 857.969437] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [ 857.969439] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 857.969440] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A [ 857.969441] [drm:intel_dump_pipe_config] cpu_transcoder: D [ 857.969442] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 857.969443] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 857.969445] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [ 857.969446] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [ 857.969447] [drm:intel_dump_pipe_config] requested mode: [ 857.969449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 857.969450] [drm:intel_dump_pipe_config] adjusted mode: [ 857.969451] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [ 857.969453] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [ 857.969454] [drm:intel_dump_pipe_config] port clock: 270000 [ 857.969455] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [ 857.969456] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 857.969457] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 857.969457] [drm:intel_dump_pipe_config] ips: 1 [ 857.969458] [drm:intel_dump_pipe_config] double wide: 0 [ 857.969461] [drm:intel_display_power_get] enabling always-on [ 857.969477] [drm:intel_edp_panel_on] Turn eDP power on [ 857.969481] [drm:wait_panel_power_cycle] Wait for panel power cycle [ 857.969484] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [ 857.969485] [drm:wait_panel_status] Wait complete [ 857.969488] [drm:wait_panel_on] Wait for panel power on [ 857.969491] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [ 858.177929] [drm:wait_panel_status] Wait complete [ 858.177931] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 858.177937] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 858.178993] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 858.179434] [drm:intel_dp_start_link_train] clock recovery OK [ 858.180176] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful [ 858.180407] [drm:intel_edp_backlight_on] [ 858.180408] [drm:intel_panel_enable_backlight] pipe A [ 858.180415] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [ 858.180423] [drm:intel_edp_psr_enable] PSR not supported by this panel [ 858.180429] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 7680 [ 858.213717] [drm:intel_update_fbc] disabled per chip default [ 858.213720] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1] [ 858.213722] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 858.213724] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 858.213725] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 858.213726] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 858.213727] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 858.213728] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 858.213729] [drm:check_crtc_state] [CRTC:8] [ 858.213737] [drm:check_crtc_state] [CRTC:12] [ 858.213738] [drm:check_crtc_state] [CRTC:16] [ 858.213739] [drm:check_shared_dpll_state] WRPLL 1 [ 858.213740] [drm:check_shared_dpll_state] WRPLL 2 [ 858.213742] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 858.213744] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 858.213745] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 858.213746] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 858.213748] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 858.213748] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 858.223323] [drm:intel_crtc_set_config] [CRTC:8] [FB:38] #connectors=1 (x y) (0 0) [ 858.223327] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 858.223330] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 858.223332] [drm:intel_crtc_set_config] [CRTC:12] [NOFB] [ 858.223334] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0 [ 858.223336] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 858.223338] [drm:intel_crtc_set_config] [CRTC:16] [NOFB] [ 858.223339] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0 [ 858.223341] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8] [ 861.186486] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 861.186494] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007 [ 1459.963754] [drm:intel_edp_backlight_off] [ 1460.163923] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [ 1460.181935] [drm:edp_panel_vdd_on] Turning eDP VDD on [ 1460.181941] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [ 1460.182089] [drm:intel_edp_panel_off] Turn eDP power off [ 1460.182092] [drm:wait_panel_off] Wait for panel power off time [ 1460.182095] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000 [ 1460.236961] [drm:wait_panel_status] Wait complete [ 1460.236967] [drm:intel_update_fbc] no output, disabling [ 1460.236969] [drm:intel_display_power_put] disabling always-on [ 1460.236972] [drm:check_encoder_state] [ENCODER:18:TMDS-18] [ 1460.236973] [drm:check_encoder_state] [ENCODER:27:TMDS-27] [ 1460.236974] [drm:check_encoder_state] [ENCODER:29:DP MST-29] [ 1460.236975] [drm:check_encoder_state] [ENCODER:30:DP MST-30] [ 1460.236976] [drm:check_encoder_state] [ENCODER:31:DP MST-31] [ 1460.236976] [drm:check_encoder_state] [ENCODER:34:TMDS-34] [ 1460.236977] [drm:check_crtc_state] [CRTC:8] [ 1460.236979] [drm:check_crtc_state] [CRTC:12] [ 1460.236980] [drm:check_crtc_state] [CRTC:16] [ 1460.236981] [drm:check_shared_dpll_state] WRPLL 1 [ 1460.236982] [drm:check_shared_dpll_state] WRPLL 2 [ 1463.193495] [drm:intel_display_power_get] enabling always-on [ 1463.193499] [drm:intel_display_power_put] disabling always-on