p11-kit: couldn't load module: /usr/lib/i386-linux-gnu/pkcs11/p11-kit-trust.so: /usr/lib/i386-linux-gnu/pkcs11/p11-kit-trust.so: cannot open shared object file: No such file or directory fixme:wbemprox:client_security_SetBlanket 0x7d60e544, 0x1358f0, 10, 0, (null), 3, 3, (nil), 0x00000000 fixme:wbemprox:client_security_Release 0x7d60e544 fixme:thread:start_thread Started native thread 00000022 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = extractelement <4 x float> %22, i32 2 %26 = extractelement <4 x float> %22, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[0:3], s[8:9], 0x4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[8:9], 0x0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x0 ; C0C20700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], FOG DCL CONST[0..7] DCL TEMP[0] IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[1].yzw, IMM[0].xxxy 1: MUL TEMP[0], IN[0].xxxx, CONST[0] 2: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 3: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 4: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 5: DP4 TEMP[0], IN[0], CONST[6] 6: ABS OUT[1].x, TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 96) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 100) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 104) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 108) %33 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0 %35 = add i32 %5, %7 %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %34, i32 0, i32 %35) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = fmul float %37, %13 %42 = fmul float %37, %14 %43 = fmul float %37, %15 %44 = fmul float %37, %16 %45 = fmul float %38, %17 %46 = fadd float %45, %41 %47 = fmul float %38, %18 %48 = fadd float %47, %42 %49 = fmul float %38, %19 %50 = fadd float %49, %43 %51 = fmul float %38, %20 %52 = fadd float %51, %44 %53 = fmul float %39, %21 %54 = fadd float %53, %46 %55 = fmul float %39, %22 %56 = fadd float %55, %48 %57 = fmul float %39, %23 %58 = fadd float %57, %50 %59 = fmul float %39, %24 %60 = fadd float %59, %52 %61 = fmul float %40, %25 %62 = fadd float %61, %54 %63 = fmul float %40, %26 %64 = fadd float %63, %56 %65 = fmul float %40, %27 %66 = fadd float %65, %58 %67 = fmul float %40, %28 %68 = fadd float %67, %60 %69 = fmul float %37, %29 %70 = fmul float %38, %30 %71 = fadd float %69, %70 %72 = fmul float %39, %31 %73 = fadd float %71, %72 %74 = fmul float %40, %32 %75 = fadd float %73, %74 %76 = call float @fabs(float %75) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x19 ; C2020119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v1, v4 ; 10080901 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x18 ; C2020118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v0, v5, v4, 0, 0 ; D2820004 04120B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1a ; C202011A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1b ; C202011B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 V_MOV_B32_e32 v5, 0x7fffffff ; 7E0A02FF 7FFFFFFF V_AND_B32_e32 v4, v4, v5 ; 36080B04 V_MOV_B32_e32 v5, 1.000000e+00 ; 7E0A02F2 V_MOV_B32_e32 v6, 0.000000e+00 ; 7E0C0280 EXP 15, 32, 0, 0, 0, v4, v6, v6, v5 ; F800020F 05060604 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], FOG, PERSPECTIVE DCL OUT[0], COLOR DCL CONST[1..2] DCL TEMP[0..1] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV_SAT TEMP[0], IMM[0].xyyy 1: MAD_SAT TEMP[1].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy 2: LRP OUT[0].xyz, TEMP[1].xxxx, TEMP[0], CONST[2] 3: MOV OUT[0].w, TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40) %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %31 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %32 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %33 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %34 = fmul float %29, %24 %35 = fadd float %34, %25 %36 = call float @llvm.AMDIL.clamp.(float %35, float 0.000000e+00, float 1.000000e+00) %37 = call float @llvm.AMDGPU.lrp(float %36, float %30, float %26) %38 = call float @llvm.AMDGPU.lrp(float %36, float %31, float %27) %39 = call float @llvm.AMDGPU.lrp(float %36, float %32, float %28) %40 = call i32 @llvm.SI.packf16(float %37, float %38) %41 = bitcast i32 %40 to float %42 = call i32 @llvm.SI.packf16(float %39, float %33) %43 = bitcast i32 %42 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_BUFFER_LOAD_DWORD s5, s[0:3], 0x5 ; C2028105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v0, s5 ; 7E000205 V_MAD_F32 v0, v2, s4, v0, 0, 0 ; D2820000 04000902 V_ADD_F32_e64 v0, v0, 0, 1, 0 ; D2060800 00010100 V_SUB_F32_e32 v1, 1.000000e+00, v0 ; 080200F2 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v1 ; 10040204 V_ADD_F32_e64 v3, 0.000000e+00, 0, 1, 0 ; D2060803 00010080 V_MAD_F32 v2, v0, v3, v2, 0, 0 ; D2820002 040A0700 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v1 ; 10080204 V_ADD_F32_e64 v5, 1.000000e+00, 0, 1, 0 ; D2060805 000100F2 V_MAD_F32 v4, v0, v5, v4, 0, 0 ; D2820004 04120B00 V_CVT_PKRTZ_F16_F32_e32 v2, v4, v2 ; 5E040504 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xa ; C200010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s0, v1 ; 10020200 V_MAD_F32 v0, v0, v3, v1, 0, 0 ; D2820000 04060700 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v3 ; 5E000700 EXP 15, 0, 1, 1, 1, v2, v0, v2, v0 ; F8001C0F 00020002 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = add i32 %5, %7 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %31) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = add i32 %5, %7 %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %39) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %33, %13 %46 = fmul float %33, %14 %47 = fmul float %33, %15 %48 = fmul float %33, %16 %49 = fmul float %34, %17 %50 = fadd float %49, %45 %51 = fmul float %34, %18 %52 = fadd float %51, %46 %53 = fmul float %34, %19 %54 = fadd float %53, %47 %55 = fmul float %34, %20 %56 = fadd float %55, %48 %57 = fmul float %35, %21 %58 = fadd float %57, %50 %59 = fmul float %35, %22 %60 = fadd float %59, %52 %61 = fmul float %35, %23 %62 = fadd float %61, %54 %63 = fmul float %35, %24 %64 = fadd float %63, %56 %65 = fmul float %36, %25 %66 = fadd float %65, %58 %67 = fmul float %36, %26 %68 = fadd float %67, %60 %69 = fmul float %36, %27 %70 = fadd float %69, %62 %71 = fmul float %36, %28 %72 = fadd float %71, %64 %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00) %74 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00) %75 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00) %76 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %73, float %74, float %75, float %76) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v5, v4, 0, 1, 0 ; D2060805 00010104 V_ADD_F32_e64 v6, v3, 0, 1, 0 ; D2060806 00010103 V_ADD_F32_e64 v7, v2, 0, 1, 0 ; D2060807 00010102 V_ADD_F32_e64 v1, v1, 0, 1, 0 ; D2060801 00010101 EXP 15, 32, 0, 0, 0, v1, v7, v6, v5 ; F800020F 05060701 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_INTERP_P1_F32 v4, v0, 1, 0, [m0] ; C8100100 V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 EXP 15, 0, 0, 1, 1, v5, v4, v3, v2 ; F800180F 02030405 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_CVT_PKRTZ_F16_F32_e32 v2, v3, v2 ; 5E040503 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v4, v0, 0, 0, [m0] ; C8100000 V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0] ; C8110001 V_CVT_PKRTZ_F16_F32_e32 v0, v4, v3 ; 5E000704 EXP 15, 0, 1, 1, 1, v0, v2, v0, v2 ; F8001C0F 02000200 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = add i32 %5, %7 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %31) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = add i32 %5, %7 %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %39) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %33, %13 %46 = fmul float %33, %14 %47 = fmul float %33, %15 %48 = fmul float %33, %16 %49 = fmul float %34, %17 %50 = fadd float %49, %45 %51 = fmul float %34, %18 %52 = fadd float %51, %46 %53 = fmul float %34, %19 %54 = fadd float %53, %47 %55 = fmul float %34, %20 %56 = fadd float %55, %48 %57 = fmul float %35, %21 %58 = fadd float %57, %50 %59 = fmul float %35, %22 %60 = fadd float %59, %52 %61 = fmul float %35, %23 %62 = fadd float %61, %54 %63 = fmul float %35, %24 %64 = fadd float %63, %56 %65 = fmul float %36, %25 %66 = fadd float %65, %58 %67 = fmul float %36, %26 %68 = fadd float %67, %60 %69 = fmul float %36, %27 %70 = fadd float %69, %62 %71 = fmul float %36, %28 %72 = fadd float %71, %64 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %41, float %42, float %43, float %44) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0].xyz, TEMP[0], CONST[4] 4: MOV TEMP[0].xyz, TEMP[0].xyzx 5: MOV TEMP[0].w, CONST[4].wwww 6: MOV OUT[0], TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %35 = fdiv float %32, %34 %36 = fdiv float %33, %34 %37 = bitcast float %35 to i32 %38 = bitcast float %36 to i32 %39 = insertelement <2 x i32> undef, i32 %37, i32 0 %40 = insertelement <2 x i32> %39, i32 %38, i32 1 %41 = bitcast <8 x i32> %29 to <32 x i8> %42 = bitcast <4 x i32> %31 to <16 x i8> %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2) %44 = extractelement <4 x float> %43, i32 0 %45 = extractelement <4 x float> %43, i32 1 %46 = extractelement <4 x float> %43, i32 2 %47 = fmul float %44, %24 %48 = fmul float %45, %25 %49 = fmul float %46, %26 %50 = call i32 @llvm.SI.packf16(float %47, float %48) %51 = bitcast i32 %50 to float %52 = call i32 @llvm.SI.packf16(float %49, float %27) %53 = bitcast i32 %52 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[8:11], s[4:5], 0x0 ; C0840500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800700 00430004 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v3, s4 ; 7E060204 V_MUL_F32_e32 v3, v1, v3 ; 10060701 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x10 ; C2020110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 V_CVT_PKRTZ_F16_F32_e32 v3, v4, v3 ; 5E060704 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v0, v2, v4 ; 10000902 S_BUFFER_LOAD_DWORD s0, s[0:3], 0x13 ; C2000113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CVT_PKRTZ_F16_F32_e64 v0, v0, s0, 0, 0 ; D25E0000 00000100 EXP 15, 0, 1, 1, 1, v3, v0, v3, v0 ; F8001C0F 00030003 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %35 = fdiv float %32, %34 %36 = fdiv float %33, %34 %37 = bitcast float %35 to i32 %38 = bitcast float %36 to i32 %39 = insertelement <2 x i32> undef, i32 %37, i32 0 %40 = insertelement <2 x i32> %39, i32 %38, i32 1 %41 = bitcast <8 x i32> %29 to <32 x i8> %42 = bitcast <4 x i32> %31 to <16 x i8> %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2) %44 = extractelement <4 x float> %43, i32 0 %45 = extractelement <4 x float> %43, i32 1 %46 = extractelement <4 x float> %43, i32 2 %47 = extractelement <4 x float> %43, i32 3 %48 = fmul float %44, %24 %49 = fmul float %45, %25 %50 = fmul float %46, %26 %51 = fmul float %47, %27 %52 = call i32 @llvm.SI.packf16(float %48, float %49) %53 = bitcast i32 %52 to float %54 = call i32 @llvm.SI.packf16(float %50, float %51) %55 = bitcast i32 %54 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[8:11], s[4:5], 0x0 ; C0840500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x13 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v3, v4 ; 10080903 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v2, v5 ; 100A0B02 V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4 ; 5E080905 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v1, v5 ; 100A0B01 S_BUFFER_LOAD_DWORD s0, s[0:3], 0x10 ; C2000110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s0 ; 7E0C0200 V_MUL_F32_e32 v0, v0, v6 ; 10000D00 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5 ; 5E000B00 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 fixme:win:EnumDisplayDevicesW ((null),0,0x32e548,0x00000000), stub! fixme:thread:SetThreadIdealProcessor (0x74): stub fixme:thread:SetThreadIdealProcessor (0x84): stub fixme:thread:SetThreadIdealProcessor (0x7c): stub fixme:thread:SetThreadIdealProcessor (0x8c): stub fixme:thread:SetThreadIdealProcessor (0x94): stub fixme:thread:SetThreadIdealProcessor (0x9c): stub fixme:thread:SetThreadIdealProcessor (0xa4): stub fixme:thread:start_thread Started native thread 0000002a fixme:thread:start_thread Started native thread 0000002b fixme:thread:start_thread Started native thread 0000002c fixme:thread:SetThreadIdealProcessor (0xfffffffe): stub fixme:d3d9:try_native  Native Direct3D 9 is disabled. For more informations visit https://wiki.ixit.cz/d3d9 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = extractelement <4 x float> %22, i32 2 %26 = extractelement <4 x float> %22, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[0:3], s[8:9], 0x4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[8:9], 0x0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x0 ; C0C20700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], FOG DCL CONST[0..7] DCL TEMP[0] IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[1].yzw, IMM[0].xxxy 1: MUL TEMP[0], IN[0].xxxx, CONST[0] 2: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 3: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 4: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 5: DP4 TEMP[0], IN[0], CONST[6] 6: ABS OUT[1].x, TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 96) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 100) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 104) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 108) %33 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0 %35 = add i32 %5, %7 %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %34, i32 0, i32 %35) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = fmul float %37, %13 %42 = fmul float %37, %14 %43 = fmul float %37, %15 %44 = fmul float %37, %16 %45 = fmul float %38, %17 %46 = fadd float %45, %41 %47 = fmul float %38, %18 %48 = fadd float %47, %42 %49 = fmul float %38, %19 %50 = fadd float %49, %43 %51 = fmul float %38, %20 %52 = fadd float %51, %44 %53 = fmul float %39, %21 %54 = fadd float %53, %46 %55 = fmul float %39, %22 %56 = fadd float %55, %48 %57 = fmul float %39, %23 %58 = fadd float %57, %50 %59 = fmul float %39, %24 %60 = fadd float %59, %52 %61 = fmul float %40, %25 %62 = fadd float %61, %54 %63 = fmul float %40, %26 %64 = fadd float %63, %56 %65 = fmul float %40, %27 %66 = fadd float %65, %58 %67 = fmul float %40, %28 %68 = fadd float %67, %60 %69 = fmul float %37, %29 %70 = fmul float %38, %30 %71 = fadd float %69, %70 %72 = fmul float %39, %31 %73 = fadd float %71, %72 %74 = fmul float %40, %32 %75 = fadd float %73, %74 %76 = call float @fabs(float %75) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x19 ; C2020119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v1, v4 ; 10080901 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x18 ; C2020118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v0, v5, v4, 0, 0 ; D2820004 04120B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1a ; C202011A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1b ; C202011B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 V_MOV_B32_e32 v5, 0x7fffffff ; 7E0A02FF 7FFFFFFF V_AND_B32_e32 v4, v4, v5 ; 36080B04 V_MOV_B32_e32 v5, 1.000000e+00 ; 7E0A02F2 V_MOV_B32_e32 v6, 0.000000e+00 ; 7E0C0280 EXP 15, 32, 0, 0, 0, v4, v6, v6, v5 ; F800020F 05060604 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], FOG, PERSPECTIVE DCL OUT[0], COLOR DCL CONST[1..2] DCL TEMP[0..1] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV_SAT TEMP[0], IMM[0].xyyy 1: MAD_SAT TEMP[1].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy 2: LRP OUT[0].xyz, TEMP[1].xxxx, TEMP[0], CONST[2] 3: MOV OUT[0].w, TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40) %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %31 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %32 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %33 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %34 = fmul float %29, %24 %35 = fadd float %34, %25 %36 = call float @llvm.AMDIL.clamp.(float %35, float 0.000000e+00, float 1.000000e+00) %37 = call float @llvm.AMDGPU.lrp(float %36, float %30, float %26) %38 = call float @llvm.AMDGPU.lrp(float %36, float %31, float %27) %39 = call float @llvm.AMDGPU.lrp(float %36, float %32, float %28) %40 = call i32 @llvm.SI.packf16(float %37, float %38) %41 = bitcast i32 %40 to float %42 = call i32 @llvm.SI.packf16(float %39, float %33) %43 = bitcast i32 %42 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_BUFFER_LOAD_DWORD s5, s[0:3], 0x5 ; C2028105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v0, s5 ; 7E000205 V_MAD_F32 v0, v2, s4, v0, 0, 0 ; D2820000 04000902 V_ADD_F32_e64 v0, v0, 0, 1, 0 ; D2060800 00010100 V_SUB_F32_e32 v1, 1.000000e+00, v0 ; 080200F2 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v1 ; 10040204 V_ADD_F32_e64 v3, 0.000000e+00, 0, 1, 0 ; D2060803 00010080 V_MAD_F32 v2, v0, v3, v2, 0, 0 ; D2820002 040A0700 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v1 ; 10080204 V_ADD_F32_e64 v5, 1.000000e+00, 0, 1, 0 ; D2060805 000100F2 V_MAD_F32 v4, v0, v5, v4, 0, 0 ; D2820004 04120B00 V_CVT_PKRTZ_F16_F32_e32 v2, v4, v2 ; 5E040504 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xa ; C200010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s0, v1 ; 10020200 V_MAD_F32 v0, v0, v3, v1, 0, 0 ; D2820000 04060700 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v3 ; 5E000700 EXP 15, 0, 1, 1, 1, v2, v0, v2, v0 ; F8001C0F 00020002 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = add i32 %5, %7 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %31) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = add i32 %5, %7 %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %39) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %33, %13 %46 = fmul float %33, %14 %47 = fmul float %33, %15 %48 = fmul float %33, %16 %49 = fmul float %34, %17 %50 = fadd float %49, %45 %51 = fmul float %34, %18 %52 = fadd float %51, %46 %53 = fmul float %34, %19 %54 = fadd float %53, %47 %55 = fmul float %34, %20 %56 = fadd float %55, %48 %57 = fmul float %35, %21 %58 = fadd float %57, %50 %59 = fmul float %35, %22 %60 = fadd float %59, %52 %61 = fmul float %35, %23 %62 = fadd float %61, %54 %63 = fmul float %35, %24 %64 = fadd float %63, %56 %65 = fmul float %36, %25 %66 = fadd float %65, %58 %67 = fmul float %36, %26 %68 = fadd float %67, %60 %69 = fmul float %36, %27 %70 = fadd float %69, %62 %71 = fmul float %36, %28 %72 = fadd float %71, %64 %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00) %74 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00) %75 = call float @llvm.AMDIL.clamp.(float %43, float 0.000000e+00, float 1.000000e+00) %76 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %73, float %74, float %75, float %76) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v5, v4, 0, 1, 0 ; D2060805 00010104 V_ADD_F32_e64 v6, v3, 0, 1, 0 ; D2060806 00010103 V_ADD_F32_e64 v7, v2, 0, 1, 0 ; D2060807 00010102 V_ADD_F32_e64 v1, v1, 0, 1, 0 ; D2060801 00010101 EXP 15, 32, 0, 0, 0, v1, v7, v6, v5 ; F800020F 05060701 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_INTERP_P1_F32 v4, v0, 1, 0, [m0] ; C8100100 V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 EXP 15, 0, 0, 1, 1, v5, v4, v3, v2 ; F800180F 02030405 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_CVT_PKRTZ_F16_F32_e32 v2, v3, v2 ; 5E040503 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v4, v0, 0, 0, [m0] ; C8100000 V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0] ; C8110001 V_CVT_PKRTZ_F16_F32_e32 v0, v4, v3 ; 5E000704 EXP 15, 0, 1, 1, 1, v0, v2, v0, v2 ; F8001C0F 02000200 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = add i32 %5, %7 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %30, i32 0, i32 %31) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = add i32 %5, %7 %40 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %39) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %33, %13 %46 = fmul float %33, %14 %47 = fmul float %33, %15 %48 = fmul float %33, %16 %49 = fmul float %34, %17 %50 = fadd float %49, %45 %51 = fmul float %34, %18 %52 = fadd float %51, %46 %53 = fmul float %34, %19 %54 = fadd float %53, %47 %55 = fmul float %34, %20 %56 = fadd float %55, %48 %57 = fmul float %35, %21 %58 = fadd float %57, %50 %59 = fmul float %35, %22 %60 = fadd float %59, %52 %61 = fmul float %35, %23 %62 = fadd float %61, %54 %63 = fmul float %35, %24 %64 = fadd float %63, %56 %65 = fmul float %36, %25 %66 = fadd float %65, %58 %67 = fmul float %36, %26 %68 = fadd float %67, %60 %69 = fmul float %36, %27 %70 = fadd float %69, %62 %71 = fmul float %36, %28 %72 = fadd float %71, %64 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %41, float %42, float %43, float %44) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %66, float %68, float %70, float %72) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v0, v5 ; 100A0B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e32 v6, v0, v6 ; 100C0D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e32 v7, v0, v7 ; 100E0F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xc ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0].xyz, TEMP[0], CONST[4] 4: MOV TEMP[0].xyz, TEMP[0].xyzx 5: MOV TEMP[0].w, CONST[4].wwww 6: MOV OUT[0], TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %35 = fdiv float %32, %34 %36 = fdiv float %33, %34 %37 = bitcast float %35 to i32 %38 = bitcast float %36 to i32 %39 = insertelement <2 x i32> undef, i32 %37, i32 0 %40 = insertelement <2 x i32> %39, i32 %38, i32 1 %41 = bitcast <8 x i32> %29 to <32 x i8> %42 = bitcast <4 x i32> %31 to <16 x i8> %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2) %44 = extractelement <4 x float> %43, i32 0 %45 = extractelement <4 x float> %43, i32 1 %46 = extractelement <4 x float> %43, i32 2 %47 = fmul float %44, %24 %48 = fmul float %45, %25 %49 = fmul float %46, %26 %50 = call i32 @llvm.SI.packf16(float %47, float %48) %51 = bitcast i32 %50 to float %52 = call i32 @llvm.SI.packf16(float %49, float %27) %53 = bitcast i32 %52 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[8:11], s[4:5], 0x0 ; C0840500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800700 00430004 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v3, s4 ; 7E060204 V_MUL_F32_e32 v3, v1, v3 ; 10060701 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x10 ; C2020110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v0, v4 ; 10080900 V_CVT_PKRTZ_F16_F32_e32 v3, v4, v3 ; 5E060704 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v0, v2, v4 ; 10000902 S_BUFFER_LOAD_DWORD s0, s[0:3], 0x13 ; C2000113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CVT_PKRTZ_F16_F32_e64 v0, v0, s0, 0, 0 ; D25E0000 00000100 EXP 15, 0, 1, 1, 1, v3, v0, v3, v0 ; F8001C0F 00030003 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %35 = fdiv float %32, %34 %36 = fdiv float %33, %34 %37 = bitcast float %35 to i32 %38 = bitcast float %36 to i32 %39 = insertelement <2 x i32> undef, i32 %37, i32 0 %40 = insertelement <2 x i32> %39, i32 %38, i32 1 %41 = bitcast <8 x i32> %29 to <32 x i8> %42 = bitcast <4 x i32> %31 to <16 x i8> %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2) %44 = extractelement <4 x float> %43, i32 0 %45 = extractelement <4 x float> %43, i32 1 %46 = extractelement <4 x float> %43, i32 2 %47 = extractelement <4 x float> %43, i32 3 %48 = fmul float %44, %24 %49 = fmul float %45, %25 %50 = fmul float %46, %26 %51 = fmul float %47, %27 %52 = call i32 @llvm.SI.packf16(float %48, float %49) %53 = bitcast i32 %52 to float %54 = call i32 @llvm.SI.packf16(float %50, float %51) %55 = bitcast i32 %54 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[8:11], s[4:5], 0x0 ; C0840500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x13 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e32 v4, v3, v4 ; 10080903 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v2, v5 ; 100A0B02 V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4 ; 5E080905 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e32 v5, v1, v5 ; 100A0B01 S_BUFFER_LOAD_DWORD s0, s[0:3], 0x10 ; C2000110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s0 ; 7E0C0200 V_MUL_F32_e32 v0, v0, v6 ; 10000D00 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5 ; 5E000B00 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 ((null),0,0x32e358,0x00000000), stub! VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = extractelement <4 x float> %22, i32 2 %26 = extractelement <4 x float> %22, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[0:3], s[8:9], 0x4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[8:9], 0x0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x0 ; C0C20700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 fixme:d3d:debug_d3dformat Unrecognized 0x31495441 (as fourcc: ATI1) WINED3DFORMAT! fixme:d3d:wined3d_get_format Can't find format unrecognized (0x31495441) in the format lookup table fixme:d3d:debug_d3dformat Unrecognized 0x34324644 (as fourcc: DF24) WINED3DFORMAT! fixme:d3d:wined3d_get_format Can't find format unrecognized (0x34324644) in the format lookup table fixme:d3d:debug_d3dformat Unrecognized 0x36314644 (as fourcc: DF16) WINED3DFORMAT! fixme:d3d:wined3d_get_format Can't find format unrecognized (0x36314644) in the format lookup table fixme:d3d:debug_d3dformat Unrecognized 0x34324644 (as fourcc: DF24) WINED3DFORMAT! fixme:d3d:wined3d_get_format Can't find format unrecognized (0x34324644) in the format lookup table fixme:d3d:debug_d3dformat Unrecognized 0x434f5441 (as fourcc: ATOC) WINED3DFORMAT! fixme:d3d:wined3d_get_format Can't find format unrecognized (0x434f5441) in the format lookup table FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %35, float %36, float %37, float %38) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x0 ; C0C20700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 3D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %11) %29 = bitcast float %26 to i32 %30 = bitcast float %27 to i32 %31 = bitcast float %28 to i32 %32 = insertelement <4 x i32> undef, i32 %29, i32 0 %33 = insertelement <4 x i32> %32, i32 %30, i32 1 %34 = insertelement <4 x i32> %33, i32 %31, i32 2 %35 = insertelement <4 x i32> %34, i32 undef, i32 3 %36 = bitcast <8 x i32> %23 to <32 x i8> %37 = bitcast <4 x i32> %25 to <16 x i8> %38 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %35, <32 x i8> %36, <16 x i8> %37, i32 3) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = call i32 @llvm.SI.packf16(float %39, float %40) %44 = bitcast i32 %43 to float %45 = call i32 @llvm.SI.packf16(float %41, float %42) %46 = bitcast i32 %45 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %44, float %46, float %44, float %46) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v4, v0, 2, 0, [m0] ; C8100200 V_INTERP_P2_F32 v4, [v4], v1, 2, 0, [m0] ; C8110201 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x0 ; C0C20700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:5], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 fixme:d3d9:Direct3DShaderValidatorCreate9 stub VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], GENERIC[0] DCL CONST[0..4] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 2.0000, 0.0000, 0.0000, 0.0000} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0] 4: MOV TEMP[1].xw, TEMP[0].xxzw 5: MUL TEMP[2].x, TEMP[0].yyyy, CONST[4].yyyy 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MAD TEMP[1].xy, CONST[4].zwww, TEMP[0].wwww, TEMP[1].xyyy 8: MAD TEMP[0].x, TEMP[0].zzzz, IMM[0].xxxx, -TEMP[0].wwww 9: MOV TEMP[1].z, TEMP[0].xxxx 10: MOV OUT[2], IN[1] 11: MOV OUT[0], TEMP[1] 12: MOV_SAT OUT[1], IN[2] 13: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 68) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 72) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 76) %32 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0 %34 = add i32 %5, %7 %35 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %33, i32 0, i32 %34) %36 = extractelement <4 x float> %35, i32 0 %37 = extractelement <4 x float> %35, i32 1 %38 = extractelement <4 x float> %35, i32 2 %39 = extractelement <4 x float> %35, i32 3 %40 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0 %42 = add i32 %5, %7 %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %42) %44 = extractelement <4 x float> %43, i32 0 %45 = extractelement <4 x float> %43, i32 1 %46 = extractelement <4 x float> %43, i32 2 %47 = extractelement <4 x float> %43, i32 3 %48 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = add i32 %5, %7 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = extractelement <4 x float> %51, i32 3 %56 = fmul float %13, %36 %57 = fmul float %14, %36 %58 = fmul float %15, %36 %59 = fmul float %16, %36 %60 = fmul float %17, %37 %61 = fadd float %60, %56 %62 = fmul float %18, %37 %63 = fadd float %62, %57 %64 = fmul float %19, %37 %65 = fadd float %64, %58 %66 = fmul float %20, %37 %67 = fadd float %66, %59 %68 = fmul float %21, %38 %69 = fadd float %68, %61 %70 = fmul float %22, %38 %71 = fadd float %70, %63 %72 = fmul float %23, %38 %73 = fadd float %72, %65 %74 = fmul float %24, %38 %75 = fadd float %74, %67 %76 = fmul float %25, %39 %77 = fadd float %76, %69 %78 = fmul float %26, %39 %79 = fadd float %78, %71 %80 = fmul float %27, %39 %81 = fadd float %80, %73 %82 = fmul float %28, %39 %83 = fadd float %82, %75 %84 = fmul float %79, %29 %85 = fmul float %30, %83 %86 = fadd float %85, %77 %87 = fmul float %31, %83 %88 = fadd float %87, %84 %89 = fsub float -0.000000e+00, %83 %90 = fmul float %81, 2.000000e+00 %91 = fadd float %90, %89 %92 = call float @llvm.AMDIL.clamp.(float %52, float 0.000000e+00, float 1.000000e+00) %93 = call float @llvm.AMDIL.clamp.(float %53, float 0.000000e+00, float 1.000000e+00) %94 = call float @llvm.AMDIL.clamp.(float %54, float 0.000000e+00, float 1.000000e+00) %95 = call float @llvm.AMDIL.clamp.(float %55, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %95) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %86, float %88, float %91, float %83) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x8 ; C0820908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v5, v4, 0, 1, 0 ; D2060805 00010104 V_ADD_F32_e64 v6, v3, 0, 1, 0 ; D2060806 00010103 V_ADD_F32_e64 v7, v2, 0, 1, 0 ; D2060807 00010102 V_ADD_F32_e64 v1, v1, 0, 1, 0 ; D2060801 00010101 EXP 15, 32, 0, 0, 0, v1, v7, v6, v5 ; F800020F 05060701 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v1, v2, v3, v4 ; F800021F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v0 ; 10080004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v1, v4, 0, 0 ; D2820004 04120204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v2, v4, 0, 0 ; D2820004 04120404 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xc ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v3, v4, 0, 0 ; D2820004 04120604 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v0 ; 100A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v1, v5, 0, 0 ; D2820005 04160204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xb ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v2, v5, 0, 0 ; D2820005 04160404 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xf ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v3, v5, 0, 0 ; D2820005 04160604 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v5, v4, 0, 0 ; D2820004 04120A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s4, v0 ; 100C0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s4, v1, v6, 0, 0 ; D2820006 041A0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s4, v2, v6, 0, 0 ; D2820006 041A0404 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xd ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s4, v3, v6, 0, 0 ; D2820006 041A0604 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s4, v6 ; 100C0C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x13 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s4, v5, v6, 0, 0 ; D2820006 041A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s4, v0 ; 100E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0x6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v1, v7, 0, 0 ; D2820007 041E0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0xa ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v2, v7, 0, 0 ; D2820007 041E0404 S_BUFFER_LOAD_DWORD s0, s[0:3], 0xe ; C200010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v3, v7, 0, 0 ; D2820000 041E0600 V_ADD_F32_e32 v0, v0, v0 ; 06000100 V_SUB_F32_e32 v0, v0, v5 ; 08000B00 EXP 15, 12, 0, 1, 0, v4, v6, v0, v5 ; F80008CF 05000604 S_ENDPGM ; BF810000 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL OUT[1], COLOR[1] DCL SAMP[0] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 0.0000, 0.5000, 0.0000, 0.0000} 0: ADD TEMP[0].xy, IN[1].xyyy, IMM[0].xyyy 1: MOV TEMP[1].xy, IN[1].xyyy 2: TEX TEMP[1], TEMP[1], SAMP[0], 2D 3: MOV TEMP[2].w, TEMP[1].wwww 4: MOV TEMP[0].xy, TEMP[0].xyyy 5: TEX TEMP[0], TEMP[0], SAMP[0], 2D 6: MAD TEMP[3].x, TEMP[0].wwww, IN[1].zzzz, IN[1].wwww 7: MOV_SAT TEMP[3].x, TEMP[3].xxxx 8: LRP TEMP[2].xyz, TEMP[3].xxxx, TEMP[1].xyzz, TEMP[0].xyzz 9: MUL TEMP[2], TEMP[2], IN[0] 10: MOV OUT[0], TEMP[2] 11: MOV OUT[1], TEMP[2] 12: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %28 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %29 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %30 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %31 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %32 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %5, <2 x i32> %7) %34 = fadd float %30, 0.000000e+00 %35 = fadd float %31, 5.000000e-01 %36 = bitcast float %30 to i32 %37 = bitcast float %31 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = bitcast <8 x i32> %23 to <32 x i8> %41 = bitcast <4 x i32> %25 to <16 x i8> %42 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %40, <16 x i8> %41, i32 2) %43 = extractelement <4 x float> %42, i32 0 %44 = extractelement <4 x float> %42, i32 1 %45 = extractelement <4 x float> %42, i32 2 %46 = extractelement <4 x float> %42, i32 3 %47 = bitcast float %34 to i32 %48 = bitcast float %35 to i32 %49 = insertelement <2 x i32> undef, i32 %47, i32 0 %50 = insertelement <2 x i32> %49, i32 %48, i32 1 %51 = bitcast <8 x i32> %23 to <32 x i8> %52 = bitcast <4 x i32> %25 to <16 x i8> %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %51, <16 x i8> %52, i32 2) %54 = extractelement <4 x float> %53, i32 0 %55 = extractelement <4 x float> %53, i32 1 %56 = extractelement <4 x float> %53, i32 2 %57 = extractelement <4 x float> %53, i32 3 %58 = fmul float %57, %32 %59 = fadd float %58, %33 %60 = call float @llvm.AMDIL.clamp.(float %59, float 0.000000e+00, float 1.000000e+00) %61 = call float @llvm.AMDGPU.lrp(float %60, float %43, float %54) %62 = call float @llvm.AMDGPU.lrp(float %60, float %44, float %55) %63 = call float @llvm.AMDGPU.lrp(float %60, float %45, float %56) %64 = fmul float %61, %26 %65 = fmul float %62, %27 %66 = fmul float %63, %28 %67 = fmul float %46, %29 %68 = call i32 @llvm.SI.packf16(float %64, float %65) %69 = bitcast i32 %68 to float %70 = call i32 @llvm.SI.packf16(float %66, float %67) %71 = bitcast i32 %70 to float %72 = call i32 @llvm.SI.packf16(float %64, float %65) %73 = bitcast i32 %72 to float %74 = call i32 @llvm.SI.packf16(float %66, float %67) %75 = bitcast i32 %74 to float call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 0, i32 1, float %69, float %71, float %69, float %71) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %73, float %75, float %73, float %75) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 1, [m0] ; C8080400 V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0] ; C8090401 V_INTERP_P1_F32 v4, v0, 1, 1, [m0] ; C8100500 V_INTERP_P2_F32 v4, [v4], v1, 1, 1, [m0] ; C8110501 V_ADD_F32_e32 v3, 5.000000e-01, v4 ; 060608F0 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x0 ; C0800500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[5:8], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030502 V_INTERP_P1_F32 v9, v0, 3, 1, [m0] ; C8240700 V_INTERP_P2_F32 v9, [v9], v1, 3, 1, [m0] ; C8250701 V_INTERP_P1_F32 v10, v0, 2, 1, [m0] ; C8280600 V_INTERP_P2_F32 v10, [v10], v1, 2, 1, [m0] ; C8290601 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v9, v8, v10, v9, 0, 0 ; D2820009 04261508 V_ADD_F32_e64 v9, v9, 0, 1, 0 ; D2060809 00010109 V_SUB_F32_e32 v10, 1.000000e+00, v9 ; 081412F2 V_MUL_F32_e32 v11, v10, v6 ; 10160D0A V_MOV_B32_e32 v3, v4 ; 7E060304 IMAGE_SAMPLE v[12:15], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030C02 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v9, v13, v11, 0, 0 ; D2820002 042E1B09 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_MUL_F32_e32 v2, v2, v3 ; 10040702 V_MUL_F32_e32 v3, v10, v5 ; 10060B0A V_MAD_F32 v3, v9, v12, v3, 0, 0 ; D2820003 040E1909 V_INTERP_P1_F32 v4, v0, 0, 0, [m0] ; C8100000 V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0] ; C8110001 V_MUL_F32_e32 v3, v3, v4 ; 10060903 V_CVT_PKRTZ_F16_F32_e32 v2, v3, v2 ; 5E040503 V_MUL_F32_e32 v3, v10, v7 ; 10060F0A V_MAD_F32 v3, v9, v14, v3, 0, 0 ; D2820003 040E1D09 V_INTERP_P1_F32 v4, v0, 2, 0, [m0] ; C8100200 V_INTERP_P2_F32 v4, [v4], v1, 2, 0, [m0] ; C8110201 V_MUL_F32_e32 v3, v3, v4 ; 10060903 V_INTERP_P1_F32 v4, v0, 3, 0, [m0] ; C8100300 V_INTERP_P2_F32 v4, [v4], v1, 3, 0, [m0] ; C8110301 V_MUL_F32_e32 v0, v15, v4 ; 1000090F V_CVT_PKRTZ_F16_F32_e32 v0, v3, v0 ; 5E000103 EXP 15, 0, 1, 0, 0, v2, v0, v2, v0 ; F800040F 00020002 EXP 15, 1, 1, 1, 1, v2, v0, v2, v0 ; F8001C1F 00020002 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL OUT[4], GENERIC[12] DCL OUT[5], GENERIC[13] DCL OUT[6], GENERIC[14] DCL OUT[7], GENERIC[15] DCL OUT[8], GENERIC[16] DCL OUT[9], GENERIC[17] DCL OUT[10], GENERIC[18] DCL OUT[11], GENERIC[19] DCL OUT[12], GENERIC[20] DCL CONST[0..256] DCL TEMP[0..8], LOCAL DCL TEMP[9..20], ARRAY(1), LOCAL DCL ADDR[0] IMM[0] FLT32 { 1.0000, 0.0000, 0.5000, 2.0000} IMM[1] INT32 {1, 2, 0, 0} 0: MAD TEMP[0].xy, IN[1].xyyy, CONST[106].xyyy, CONST[106].zwww 1: MUL TEMP[1].x, CONST[107].xxxx, IN[4].xxxx 2: FRC TEMP[2].x, TEMP[1].xxxx 3: ADD TEMP[3].x, TEMP[1].xxxx, -TEMP[2].xxxx 4: FSLT TEMP[2].x, -TEMP[2].xxxx, TEMP[2].xxxx 5: UIF TEMP[2].xxxx :0 6: MOV TEMP[2].x, IMM[0].xxxx 7: ELSE :0 8: MOV TEMP[2].x, IMM[0].yyyy 9: ENDIF 10: FSLT TEMP[4].x, TEMP[1].xxxx, -TEMP[1].xxxx 11: UIF TEMP[4].xxxx :0 12: MOV TEMP[4].x, IMM[0].xxxx 13: ELSE :0 14: MOV TEMP[4].x, IMM[0].yyyy 15: ENDIF 16: MAD TEMP[1].x, TEMP[4].xxxx, TEMP[2].xxxx, TEMP[3].xxxx 17: ABS TEMP[2].x, TEMP[1].xxxx 18: ADD TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz 19: FLR TEMP[2].x, TEMP[2].xxxx 20: SSG TEMP[3].x, TEMP[1].xxxx 21: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 22: F2I TEMP[2].x, TEMP[2].xxxx 23: MAD TEMP[3].xyz, IN[0].xyxx, CONST[107].yyzz, CONST[107].zzyy 24: MOV TEMP[1].xyw, TEMP[3].xyxz 25: MOV TEMP[1].z, IN[2].wwww 26: UARL ADDR[0].x, TEMP[2].xxxx 27: UARL ADDR[0].x, TEMP[2].xxxx 28: DP4 TEMP[3].x, TEMP[1], CONST[ADDR[0].x] 29: UADD TEMP[4].x, TEMP[2].xxxx, IMM[1].xxxx 30: UARL ADDR[0].x, TEMP[4].xxxx 31: DP4 TEMP[4].x, TEMP[1], CONST[ADDR[0].x] 32: MOV TEMP[3].y, TEMP[4].xxxx 33: UADD TEMP[4].x, TEMP[2].xxxx, IMM[1].yyyy 34: UARL ADDR[0].x, TEMP[4].xxxx 35: DP4 TEMP[4].x, TEMP[1], CONST[ADDR[0].x] 36: MOV TEMP[3].z, TEMP[4].xxxx 37: ADD TEMP[1].xyz, TEMP[3].xyzz, -CONST[105].xyzz 38: ADD TEMP[3].xyz, TEMP[3].xyzz, -CONST[104].xyzz 39: MUL TEMP[4], TEMP[1].yyyy, CONST[97] 40: MAD TEMP[4], CONST[96], TEMP[1].xxxx, TEMP[4] 41: MAD TEMP[1], CONST[98], TEMP[1].zzzz, TEMP[4] 42: ADD TEMP[5], TEMP[1], CONST[99] 43: RCP TEMP[1].x, CONST[103].yyyy 44: MUL TEMP[6].xyz, TEMP[1].xxxx, TEMP[3].xyzz 45: UARL ADDR[0].x, TEMP[2].xxxx 46: DP3 TEMP[7].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 47: MOV TEMP[1].z, TEMP[7].xxxx 48: UADD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx 49: UARL ADDR[0].x, TEMP[7].xxxx 50: UARL ADDR[0].x, TEMP[7].xxxx 51: DP3 TEMP[1].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 52: UADD TEMP[7].x, TEMP[2].xxxx, IMM[1].yyyy 53: UARL ADDR[0].x, TEMP[7].xxxx 54: DP3 TEMP[7].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 55: MOV TEMP[1].y, TEMP[7].xxxx 56: DP3 TEMP[7].x, TEMP[1].xyzz, TEMP[1].xyzz 57: ABS TEMP[7].x, TEMP[7].xxxx 58: RSQ TEMP[7].x, TEMP[7].xxxx 59: MUL TEMP[1].xyz, TEMP[7].xxxx, TEMP[1].xyzz 60: MUL TEMP[3].xyz, TEMP[1].xxxx, CONST[101].xyzz 61: MAD TEMP[3].xyz, CONST[100].xyzz, TEMP[1].zzzz, TEMP[3].xyzz 62: MAD TEMP[3].xyz, CONST[102].xyzz, TEMP[1].yyyy, TEMP[3].xyzz 63: MOV TEMP[7].x, TEMP[3].xxxx 64: UARL ADDR[0].x, TEMP[2].xxxx 65: DP3 TEMP[8].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 66: MOV TEMP[4].y, TEMP[8].xxxx 67: UADD TEMP[8].x, TEMP[2].xxxx, IMM[1].xxxx 68: UARL ADDR[0].x, TEMP[8].xxxx 69: DP3 TEMP[8].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 70: MOV TEMP[4].z, TEMP[8].xxxx 71: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].yyyy 72: UARL ADDR[0].x, TEMP[2].xxxx 73: UARL ADDR[0].x, TEMP[2].xxxx 74: DP3 TEMP[4].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 75: DP3 TEMP[2].x, TEMP[4].xyzz, TEMP[4].xyzz 76: ABS TEMP[2].x, TEMP[2].xxxx 77: RSQ TEMP[2].x, TEMP[2].xxxx 78: MUL TEMP[4].xyz, TEMP[2].xxxx, TEMP[4].xyzz 79: MUL TEMP[2].xyz, TEMP[1].xyzz, TEMP[4].xyzz 80: MAD TEMP[1].xyz, TEMP[4].zxyy, TEMP[1].yzxx, -TEMP[2].xyzz 81: MUL TEMP[1].xyz, TEMP[1].xyzz, IN[3].wwww 82: MUL TEMP[2].xyz, TEMP[1].yyyy, CONST[101].xyzz 83: MAD TEMP[8].xyz, CONST[100].xyzz, TEMP[1].xxxx, TEMP[2].xyzz 84: MAD TEMP[1].xyz, CONST[102].xyzz, TEMP[1].zzzz, TEMP[8].xyzz 85: MOV TEMP[7].y, TEMP[1].xxxx 86: MUL TEMP[2].xyz, TEMP[4].zzzz, CONST[101].xyzz 87: MAD TEMP[2].xyz, CONST[100].xyzz, TEMP[4].yyyy, TEMP[2].xyzz 88: MAD TEMP[4].xyz, CONST[102].xyzz, TEMP[4].xxxx, TEMP[2].xyzz 89: MOV TEMP[7].z, TEMP[4].xxxx 90: MOV TEMP[2].x, TEMP[3].yyyy 91: MOV TEMP[3].x, TEMP[3].zzzz 92: MOV TEMP[2].y, TEMP[1].yyyy 93: MOV TEMP[3].y, TEMP[1].zzzz 94: MOV TEMP[2].z, TEMP[4].yyyy 95: MOV TEMP[3].z, TEMP[4].zzzz 96: MOV TEMP[1].xw, TEMP[5].xxzw 97: MOV TEMP[9].xy, TEMP[0].xyxx 98: MOV TEMP[10].xyz, TEMP[6].xyzx 99: MOV TEMP[11].xyz, TEMP[7].xyzx 100: MOV TEMP[12].xyz, TEMP[2].xyzx 101: MOV TEMP[13].xyz, TEMP[3].xyzx 102: MOV TEMP[9].zw, IMM[0].yyyy 103: MOV TEMP[10].w, IMM[0].yyyy 104: MOV TEMP[11].w, IMM[0].yyyy 105: MOV TEMP[12].w, IMM[0].yyyy 106: MOV TEMP[13].w, IMM[0].yyyy 107: MUL TEMP[0].x, TEMP[5].yyyy, CONST[256].yyyy 108: MOV TEMP[1].y, TEMP[0].xxxx 109: MAD TEMP[1].xy, CONST[256].zwww, TEMP[5].wwww, TEMP[1].xyyy 110: MAD TEMP[0].x, TEMP[5].zzzz, IMM[0].wwww, -TEMP[5].wwww 111: MOV TEMP[1].z, TEMP[0].xxxx 112: MOV OUT[0], TEMP[1] 113: MOV OUT[1], TEMP[9] 114: MOV OUT[2], TEMP[10] 115: MOV OUT[3], TEMP[11] 116: MOV OUT[4], TEMP[12] 117: MOV OUT[5], TEMP[13] 118: MOV OUT[6], TEMP[14] 119: MOV OUT[7], TEMP[15] 120: MOV OUT[8], TEMP[16] 121: MOV OUT[9], TEMP[17] 122: MOV OUT[10], TEMP[18] 123: MOV OUT[11], TEMP[19] 124: MOV OUT[12], TEMP[20] 125: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1536) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1540) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1544) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1548) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1552) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1556) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1560) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1564) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1568) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1572) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1576) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1580) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1584) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1588) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1592) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1596) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1600) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1604) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1608) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1616) %33 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1620) %34 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1624) %35 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1632) %36 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1636) %37 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1640) %38 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1652) %39 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1664) %40 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1668) %41 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1672) %42 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1680) %43 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1684) %44 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1688) %45 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1696) %46 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1700) %47 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1704) %48 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1708) %49 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1712) %50 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1716) %51 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1720) %52 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4100) %53 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4104) %54 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4108) %55 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0 %57 = add i32 %5, %7 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0 %63 = add i32 %5, %7 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0 %69 = add i32 %5, %7 %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69) %71 = extractelement <4 x float> %70, i32 0 %72 = extractelement <4 x float> %70, i32 1 %73 = extractelement <4 x float> %70, i32 2 %74 = extractelement <4 x float> %70, i32 3 %75 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 3 %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0 %77 = add i32 %5, %7 %78 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %76, i32 0, i32 %77) %79 = extractelement <4 x float> %78, i32 0 %80 = extractelement <4 x float> %78, i32 1 %81 = extractelement <4 x float> %78, i32 2 %82 = extractelement <4 x float> %78, i32 3 %83 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 4 %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0 %85 = add i32 %10, %6 %86 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %84, i32 0, i32 %85) %87 = extractelement <4 x float> %86, i32 0 %88 = fmul float %65, %45 %89 = fadd float %88, %47 %90 = fmul float %66, %46 %91 = fadd float %90, %48 %92 = fmul float %49, %87 %93 = call float @llvm.AMDIL.fraction.(float %92) %94 = fsub float -0.000000e+00, %93 %95 = fadd float %92, %94 %96 = fsub float -0.000000e+00, %93 %97 = fcmp olt float %96, %93 %98 = sext i1 %97 to i32 %99 = bitcast i32 %98 to float %100 = bitcast float %99 to i32 %101 = icmp ne i32 %100, 0 %. = select i1 %101, float 1.000000e+00, float 0.000000e+00 %102 = fsub float -0.000000e+00, %92 %103 = fcmp olt float %92, %102 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to float %106 = bitcast float %105 to i32 %107 = icmp ne i32 %106, 0 %temp16.0 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %108 = fmul float %temp16.0, %. %109 = fadd float %108, %95 %110 = call float @fabs(float %109) %111 = fadd float %110, 5.000000e-01 %112 = call float @floor(float %111) %113 = fcmp ugt float %109, 0.000000e+00 %114 = select i1 %113, float 1.000000e+00, float %109 %115 = fcmp uge float %114, 0.000000e+00 %116 = select i1 %115, float %114, float -1.000000e+00 %117 = fmul float %112, %116 %118 = fptosi float %117 to i32 %119 = bitcast i32 %118 to float %120 = fmul float %59, %50 %121 = fadd float %120, %51 %122 = fmul float %60, %50 %123 = fadd float %122, %51 %124 = fmul float %59, %51 %125 = fadd float %124, %50 %126 = bitcast float %119 to i32 %127 = shl i32 %126, 4 %128 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %127) %129 = shl i32 %126, 4 %130 = add i32 %129, 4 %131 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %130) %132 = shl i32 %126, 4 %133 = add i32 %132, 8 %134 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %133) %135 = shl i32 %126, 4 %136 = add i32 %135, 12 %137 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %136) %138 = fmul float %121, %128 %139 = fmul float %123, %131 %140 = fadd float %138, %139 %141 = fmul float %74, %134 %142 = fadd float %140, %141 %143 = fmul float %125, %137 %144 = fadd float %142, %143 %145 = bitcast float %119 to i32 %146 = add i32 %145, 1 %147 = bitcast i32 %146 to float %148 = bitcast float %147 to i32 %149 = shl i32 %148, 4 %150 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %149) %151 = shl i32 %148, 4 %152 = add i32 %151, 4 %153 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %152) %154 = shl i32 %148, 4 %155 = add i32 %154, 8 %156 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %155) %157 = shl i32 %148, 4 %158 = add i32 %157, 12 %159 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %158) %160 = fmul float %121, %150 %161 = fmul float %123, %153 %162 = fadd float %160, %161 %163 = fmul float %74, %156 %164 = fadd float %162, %163 %165 = fmul float %125, %159 %166 = fadd float %164, %165 %167 = bitcast float %119 to i32 %168 = add i32 %167, 2 %169 = bitcast i32 %168 to float %170 = bitcast float %169 to i32 %171 = shl i32 %170, 4 %172 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %171) %173 = shl i32 %170, 4 %174 = add i32 %173, 4 %175 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %174) %176 = shl i32 %170, 4 %177 = add i32 %176, 8 %178 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %177) %179 = shl i32 %170, 4 %180 = add i32 %179, 12 %181 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %180) %182 = fmul float %121, %172 %183 = fmul float %123, %175 %184 = fadd float %182, %183 %185 = fmul float %74, %178 %186 = fadd float %184, %185 %187 = fmul float %125, %181 %188 = fadd float %186, %187 %189 = fsub float -0.000000e+00, %42 %190 = fadd float %144, %189 %191 = fsub float -0.000000e+00, %43 %192 = fadd float %166, %191 %193 = fsub float -0.000000e+00, %44 %194 = fadd float %188, %193 %195 = fsub float -0.000000e+00, %39 %196 = fadd float %144, %195 %197 = fsub float -0.000000e+00, %40 %198 = fadd float %166, %197 %199 = fsub float -0.000000e+00, %41 %200 = fadd float %188, %199 %201 = fmul float %192, %17 %202 = fmul float %192, %18 %203 = fmul float %192, %19 %204 = fmul float %192, %20 %205 = fmul float %13, %190 %206 = fadd float %205, %201 %207 = fmul float %14, %190 %208 = fadd float %207, %202 %209 = fmul float %15, %190 %210 = fadd float %209, %203 %211 = fmul float %16, %190 %212 = fadd float %211, %204 %213 = fmul float %21, %194 %214 = fadd float %213, %206 %215 = fmul float %22, %194 %216 = fadd float %215, %208 %217 = fmul float %23, %194 %218 = fadd float %217, %210 %219 = fmul float %24, %194 %220 = fadd float %219, %212 %221 = fadd float %214, %25 %222 = fadd float %216, %26 %223 = fadd float %218, %27 %224 = fadd float %220, %28 %225 = fdiv float 1.000000e+00, %38 %226 = fmul float %225, %196 %227 = fmul float %225, %198 %228 = fmul float %225, %200 %229 = bitcast float %119 to i32 %230 = shl i32 %229, 4 %231 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %230) %232 = shl i32 %229, 4 %233 = add i32 %232, 4 %234 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %233) %235 = shl i32 %229, 4 %236 = add i32 %235, 8 %237 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %236) %238 = fmul float %79, %231 %239 = fmul float %80, %234 %240 = fadd float %239, %238 %241 = fmul float %81, %237 %242 = fadd float %240, %241 %243 = bitcast float %119 to i32 %244 = add i32 %243, 1 %245 = bitcast i32 %244 to float %246 = bitcast float %245 to i32 %247 = shl i32 %246, 4 %248 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %247) %249 = shl i32 %246, 4 %250 = add i32 %249, 4 %251 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %250) %252 = shl i32 %246, 4 %253 = add i32 %252, 8 %254 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %253) %255 = fmul float %79, %248 %256 = fmul float %80, %251 %257 = fadd float %256, %255 %258 = fmul float %81, %254 %259 = fadd float %257, %258 %260 = bitcast float %119 to i32 %261 = add i32 %260, 2 %262 = bitcast i32 %261 to float %263 = bitcast float %262 to i32 %264 = shl i32 %263, 4 %265 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %264) %266 = shl i32 %263, 4 %267 = add i32 %266, 4 %268 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %267) %269 = shl i32 %263, 4 %270 = add i32 %269, 8 %271 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %270) %272 = fmul float %79, %265 %273 = fmul float %80, %268 %274 = fadd float %273, %272 %275 = fmul float %81, %271 %276 = fadd float %274, %275 %277 = fmul float %259, %259 %278 = fmul float %276, %276 %279 = fadd float %278, %277 %280 = fmul float %242, %242 %281 = fadd float %279, %280 %282 = call float @fabs(float %281) %283 = call float @llvm.AMDGPU.rsq.clamped.f32(float %282) %284 = fmul float %283, %259 %285 = fmul float %283, %276 %286 = fmul float %283, %242 %287 = fmul float %284, %32 %288 = fmul float %284, %33 %289 = fmul float %284, %34 %290 = fmul float %29, %286 %291 = fadd float %290, %287 %292 = fmul float %30, %286 %293 = fadd float %292, %288 %294 = fmul float %31, %286 %295 = fadd float %294, %289 %296 = fmul float %35, %285 %297 = fadd float %296, %291 %298 = fmul float %36, %285 %299 = fadd float %298, %293 %300 = fmul float %37, %285 %301 = fadd float %300, %295 %302 = bitcast float %119 to i32 %303 = shl i32 %302, 4 %304 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %303) %305 = shl i32 %302, 4 %306 = add i32 %305, 4 %307 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %306) %308 = shl i32 %302, 4 %309 = add i32 %308, 8 %310 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %309) %311 = fmul float %71, %304 %312 = fmul float %72, %307 %313 = fadd float %312, %311 %314 = fmul float %73, %310 %315 = fadd float %313, %314 %316 = bitcast float %119 to i32 %317 = add i32 %316, 1 %318 = bitcast i32 %317 to float %319 = bitcast float %318 to i32 %320 = shl i32 %319, 4 %321 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %320) %322 = shl i32 %319, 4 %323 = add i32 %322, 4 %324 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %323) %325 = shl i32 %319, 4 %326 = add i32 %325, 8 %327 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %326) %328 = fmul float %71, %321 %329 = fmul float %72, %324 %330 = fadd float %329, %328 %331 = fmul float %73, %327 %332 = fadd float %330, %331 %333 = bitcast float %119 to i32 %334 = add i32 %333, 2 %335 = bitcast i32 %334 to float %336 = bitcast float %335 to i32 %337 = shl i32 %336, 4 %338 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %337) %339 = shl i32 %336, 4 %340 = add i32 %339, 4 %341 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %340) %342 = shl i32 %336, 4 %343 = add i32 %342, 8 %344 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %343) %345 = fmul float %71, %338 %346 = fmul float %72, %341 %347 = fadd float %346, %345 %348 = fmul float %73, %344 %349 = fadd float %347, %348 %350 = fmul float %349, %349 %351 = fmul float %315, %315 %352 = fadd float %351, %350 %353 = fmul float %332, %332 %354 = fadd float %352, %353 %355 = call float @fabs(float %354) %356 = call float @llvm.AMDGPU.rsq.clamped.f32(float %355) %357 = fmul float %356, %349 %358 = fmul float %356, %315 %359 = fmul float %356, %332 %360 = fmul float %284, %357 %361 = fmul float %285, %358 %362 = fmul float %286, %359 %363 = fsub float -0.000000e+00, %360 %364 = fmul float %359, %285 %365 = fadd float %364, %363 %366 = fsub float -0.000000e+00, %361 %367 = fmul float %357, %286 %368 = fadd float %367, %366 %369 = fsub float -0.000000e+00, %362 %370 = fmul float %358, %284 %371 = fadd float %370, %369 %372 = fmul float %365, %82 %373 = fmul float %368, %82 %374 = fmul float %371, %82 %375 = fmul float %373, %32 %376 = fmul float %373, %33 %377 = fmul float %373, %34 %378 = fmul float %29, %372 %379 = fadd float %378, %375 %380 = fmul float %30, %372 %381 = fadd float %380, %376 %382 = fmul float %31, %372 %383 = fadd float %382, %377 %384 = fmul float %35, %374 %385 = fadd float %384, %379 %386 = fmul float %36, %374 %387 = fadd float %386, %381 %388 = fmul float %37, %374 %389 = fadd float %388, %383 %390 = fmul float %359, %32 %391 = fmul float %359, %33 %392 = fmul float %359, %34 %393 = fmul float %29, %358 %394 = fadd float %393, %390 %395 = fmul float %30, %358 %396 = fadd float %395, %391 %397 = fmul float %31, %358 %398 = fadd float %397, %392 %399 = fmul float %35, %357 %400 = fadd float %399, %394 %401 = fmul float %36, %357 %402 = fadd float %401, %396 %403 = fmul float %37, %357 %404 = fadd float %403, %398 %405 = fmul float %222, %52 %406 = fmul float %53, %224 %407 = fadd float %406, %221 %408 = fmul float %54, %224 %409 = fadd float %408, %405 %410 = fsub float -0.000000e+00, %224 %411 = fmul float %223, 2.000000e+00 %412 = fadd float %411, %410 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %89, float %91, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %226, float %227, float %228, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %297, float %385, float %400, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %299, float %387, float %402, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %301, float %389, float %404, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 40, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 41, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 42, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 43, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %407, float %409, float %412, float %224) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_MOV_B32 s4, 0x6ac ; BE8403FF 000006AC S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s4 ; 7E020204 S_MOV_B32 s4, 0x6a4 ; BE8403FF 000006A4 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s4 ; 7E040204 V_ADD_I32_e32 v0, s10, v0 ; 4A00000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[4:7], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010400 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v1, v5, v2, v1, 0, 0 ; D2820001 04060505 S_MOV_B32 s4, 0x6a8 ; BE8403FF 000006A8 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s4 ; 7E040204 S_MOV_B32 s4, 0x6a0 ; BE8403FF 000006A0 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v2, v4, v8, v2, 0, 0 ; D2820002 040A1104 V_MOV_B32_e32 v4, 0.000000e+00 ; 7E080280 EXP 15, 32, 0, 0, 0, v2, v1, v4, v4 ; F800020F 04040102 S_MOV_B32 s4, 0x6b0 ; BE8403FF 000006B0 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT expcnt(0) ; BF8C070F V_ADD_I32_e32 v1, s11, v3 ; 4A02060B S_LOAD_DWORDX4 s[12:15], s[8:9], 0x10 ; C0860910 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[5:8], s[12:15][v1] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80030501 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v1, s4, v5 ; 10020A04 V_FRACT_F32_e32 v2, v1 ; 7E044101 V_SUB_F32_e32 v3, v1, v2 ; 08060501 V_MOV_B32_e32 v5, 0x80000000 ; 7E0A02FF 80000000 V_XOR_B32_e32 v6, v1, v5 ; 3A0C0B01 V_CMP_LT_F32_e32 vcc, v1, v6 ; 7C020D01 V_CNDMASK_B32_e64 v1, 0, 1.000000e+00, vcc, 0, 0, 0, 0 ; D2000001 01A9E480 V_XOR_B32_e32 v5, v2, v5 ; 3A0A0B02 V_CMP_LT_F32_e32 vcc, v5, v2 ; 7C020505 V_CNDMASK_B32_e64 v2, 0, 1.000000e+00, vcc, 0, 0, 0, 0 ; D2000002 01A9E480 V_MAD_F32 v1, v1, v2, v3, 0, 0 ; D2820001 040E0501 V_CMP_U_F32_e32 vcc, v1, v1 ; 7C100301 V_CMP_GT_F32_e64 s[4:5], v1, 0.000000e+00, 0, 0 ; D0080004 00010101 V_CNDMASK_B32_e64 v2, 0, -1, s[4:5], 0, 0, 0, 0 ; D2000002 00118280 V_CNDMASK_B32_e64 v3, 0, -1, vcc, 0, 0, 0, 0 ; D2000003 01A98280 V_OR_B32_e32 v2, v2, v3 ; 38040702 V_CMP_NE_I32_e64 s[4:5], v2, 0, 0, 0 ; D10A0004 00010102 V_CNDMASK_B32_e64 v2, v1, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000002 0011E501 V_CMP_U_F32_e32 vcc, v2, v2 ; 7C100502 V_CMP_GE_F32_e64 s[4:5], v2, 0.000000e+00, 0, 0 ; D00C0004 00010102 V_CNDMASK_B32_e64 v3, 0, -1, s[4:5], 0, 0, 0, 0 ; D2000003 00118280 V_CNDMASK_B32_e64 v5, 0, -1, vcc, 0, 0, 0, 0 ; D2000005 01A98280 V_OR_B32_e32 v3, v3, v5 ; 38060B03 V_CMP_NE_I32_e64 s[4:5], v3, 0, 0, 0 ; D10A0004 00010103 V_CNDMASK_B32_e64 v2, -1.000000e+00, v2, s[4:5], 0, 0, 0, 0 ; D2000002 001204F3 V_ADD_F32_e64 v1, 5.000000e-01, |v1|, 0, 0 ; D2060201 000202F0 V_FLOOR_F32_e32 v1, v1 ; 7E024901 V_MUL_F32_e32 v1, v1, v2 ; 10020501 V_CVT_I32_F32_e32 v1, v1 ; 7E021101 V_LSHLREV_B32_e32 v2, 4, v1 ; 34040284 BUFFER_LOAD_DWORD v3, s[0:3] + v2 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000302 V_OR_B32_e32 v5, 4, v2 ; 380A0484 BUFFER_LOAD_DWORD v5, s[0:3] + v5 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000505 S_MOV_B32 s4, 0x6b8 ; BE8403FF 000006B8 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MOV_B32_e32 v6, s4 ; 7E0C0204 S_MOV_B32 s4, 0x6b4 ; BE8403FF 000006B4 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[8:11], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010800 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v12, v9, v7, v6, 0, 0 ; D282000C 041A0F09 V_MUL_F32_e32 v13, v12, v5 ; 101A0B0C V_MAD_F32 v14, v8, v7, v6, 0, 0 ; D282000E 041A0F08 V_MAD_F32 v13, v14, v3, v13, 0, 0 ; D282000D 0436070E V_OR_B32_e32 v15, 8, v2 ; 381E0488 BUFFER_LOAD_DWORD v15, s[0:3] + v15 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000F0F S_LOAD_DWORDX4 s[4:7], s[8:9], 0x8 ; C0820908 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[16:19], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80011000 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v13, v19, v15, v13, 0, 0 ; D282000D 04361F13 V_OR_B32_e32 v2, 12, v2 ; 3804048C BUFFER_LOAD_DWORD v2, s[0:3] + v2 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000202 V_MAD_F32 v6, v8, v6, v7, 0, 0 ; D2820006 041E0D08 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v6, v2, v13, 0, 0 ; D2820002 04360506 S_MOV_B32 s4, 0x680 ; BE8403FF 00000680 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v7, s4, v2 ; 0A0E0404 S_MOV_B32 s4, 0x674 ; BE8403FF 00000674 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v8, s4 ; 7E105404 V_MUL_F32_e32 v7, v8, v7 ; 100E0F08 V_ADD_I32_e32 v9, 2, v1 ; 4A120282 V_LSHLREV_B32_e32 v9, 4, v9 ; 34121284 BUFFER_LOAD_DWORD v10, s[0:3] + v9 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000A09 V_OR_B32_e32 v11, 4, v9 ; 38161284 BUFFER_LOAD_DWORD v11, s[0:3] + v11 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000B0B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v13, v12, v11 ; 101A170C V_MAD_F32 v13, v14, v10, v13, 0, 0 ; D282000D 0436150E V_OR_B32_e32 v20, 8, v9 ; 38281288 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v13, v19, v20, v13, 0, 0 ; D282000D 04362913 V_OR_B32_e32 v9, 12, v9 ; 3812128C BUFFER_LOAD_DWORD v9, s[0:3] + v9 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000909 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v9, v6, v9, v13, 0, 0 ; D2820009 04361306 S_MOV_B32 s4, 0x688 ; BE8403FF 00000688 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v13, s4, v9 ; 0A1A1204 V_MUL_F32_e32 v13, v8, v13 ; 101A1B08 V_ADD_I32_e32 v1, 1, v1 ; 4A020281 V_LSHLREV_B32_e32 v1, 4, v1 ; 34020284 BUFFER_LOAD_DWORD v21, s[0:3] + v1 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001501 V_OR_B32_e32 v22, 4, v1 ; 382C0284 BUFFER_LOAD_DWORD v22, s[0:3] + v22 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v12, v12, v22 ; 10182D0C V_MAD_F32 v12, v14, v21, v12, 0, 0 ; D282000C 04322B0E V_OR_B32_e32 v14, 8, v1 ; 381C0288 BUFFER_LOAD_DWORD v14, s[0:3] + v14 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000E0E S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v12, v19, v14, v12, 0, 0 ; D282000C 04321D13 V_OR_B32_e32 v1, 12, v1 ; 3802028C BUFFER_LOAD_DWORD v1, s[0:3] + v1 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000101 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v1, v6, v1, v12, 0, 0 ; D2820001 04320306 S_MOV_B32 s4, 0x684 ; BE8403FF 00000684 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v6, s4, v1 ; 0A0C0204 V_MUL_F32_e32 v6, v8, v6 ; 100C0D08 EXP 15, 33, 0, 0, 0, v7, v6, v13, v4 ; F800021F 040D0607 S_WAITCNT expcnt(0) ; BF8C070F V_MUL_F32_e32 v6, v16, v3 ; 100C0710 V_MAD_F32 v6, v17, v5, v6, 0, 0 ; D2820006 041A0B11 V_MAD_F32 v6, v18, v15, v6, 0, 0 ; D2820006 041A1F12 V_MUL_F32_e32 v7, v16, v10 ; 100E1510 V_MAD_F32 v7, v17, v11, v7, 0, 0 ; D2820007 041E1711 V_MAD_F32 v7, v18, v20, v7, 0, 0 ; D2820007 041E2912 V_MUL_F32_e32 v8, v7, v7 ; 10100F07 V_MAD_F32 v8, v6, v6, v8, 0, 0 ; D2820008 04220D06 V_MUL_F32_e32 v12, v16, v21 ; 10182B10 V_MAD_F32 v12, v17, v22, v12, 0, 0 ; D282000C 04322D11 V_MAD_F32 v12, v18, v14, v12, 0, 0 ; D282000C 04321D12 V_MAD_F32 v8, v12, v12, v8, 0, 0 ; D2820008 0422190C V_MOV_B32_e32 v13, 0x7fffffff ; 7E1A02FF 7FFFFFFF V_AND_B32_e32 v8, v8, v13 ; 36101B08 V_RSQ_CLAMP_F32_e32 v8, v8 ; 7E105908 V_MUL_F32_e32 v7, v8, v7 ; 100E0F08 S_LOAD_DWORDX4 s[4:7], s[8:9], 0xc ; C082090C S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[16:19], s[4:7][v0] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80011000 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v0, v16, v10 ; 10001510 V_MAD_F32 v0, v17, v11, v0, 0, 0 ; D2820000 04021711 V_MAD_F32 v0, v18, v20, v0, 0, 0 ; D2820000 04022912 V_MUL_F32_e32 v10, v16, v21 ; 10142B10 V_MAD_F32 v10, v17, v22, v10, 0, 0 ; D282000A 042A2D11 V_MAD_F32 v10, v18, v14, v10, 0, 0 ; D282000A 042A1D12 V_MUL_F32_e32 v11, v10, v10 ; 1016150A V_MAD_F32 v11, v0, v0, v11, 0, 0 ; D282000B 042E0100 V_MUL_F32_e32 v3, v16, v3 ; 10060710 V_MAD_F32 v3, v17, v5, v3, 0, 0 ; D2820003 040E0B11 V_MAD_F32 v3, v18, v15, v3, 0, 0 ; D2820003 040E1F12 V_MAD_F32 v5, v3, v3, v11, 0, 0 ; D2820005 042E0703 V_AND_B32_e32 v5, v5, v13 ; 360A1B05 V_RSQ_CLAMP_F32_e32 v5, v5 ; 7E0A5905 V_MUL_F32_e32 v10, v5, v10 ; 10141505 V_MUL_F32_e32 v11, v10, v7 ; 10160F0A V_MUL_F32_e32 v0, v5, v0 ; 10000105 V_MUL_F32_e32 v12, v8, v12 ; 10181908 V_MUL_F32_e32 v13, v12, v0 ; 101A010C V_SUB_F32_e32 v11, v13, v11 ; 0816170D V_MUL_F32_e32 v11, v11, v19 ; 1016270B V_MUL_F32_e32 v6, v8, v6 ; 100C0D08 V_MUL_F32_e32 v8, v0, v6 ; 10100D00 V_MUL_F32_e32 v3, v5, v3 ; 10060705 V_MUL_F32_e32 v5, v7, v3 ; 100A0707 V_SUB_F32_e32 v5, v5, v8 ; 080A1105 V_MUL_F32_e32 v5, v5, v19 ; 100A2705 S_MOV_B32 s4, 0x650 ; BE8403FF 00000650 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s4, v5 ; 10100A04 S_MOV_B32 s5, 0x640 ; BE8503FF 00000640 S_BUFFER_LOAD_DWORD s5, s[0:3], s5 ; C2028005 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s5, v11, v8, 0, 0 ; D2820008 04221605 V_MUL_F32_e32 v13, v3, v12 ; 101A1903 V_MUL_F32_e32 v14, v6, v10 ; 101C1506 V_SUB_F32_e32 v13, v14, v13 ; 081A1B0E V_MUL_F32_e32 v13, v13, v19 ; 101A270D S_MOV_B32 s6, 0x660 ; BE8603FF 00000660 S_BUFFER_LOAD_DWORD s6, s[0:3], s6 ; C2030006 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v13, v8, 0, 0 ; D2820008 04221A06 V_MUL_F32_e32 v14, s4, v12 ; 101C1804 V_MAD_F32 v14, s5, v6, v14, 0, 0 ; D282000E 043A0C05 V_MAD_F32 v14, s6, v7, v14, 0, 0 ; D282000E 043A0E06 V_MUL_F32_e32 v15, s4, v10 ; 101E1404 V_MAD_F32 v15, s5, v3, v15, 0, 0 ; D282000F 043E0605 V_MAD_F32 v15, s6, v0, v15, 0, 0 ; D282000F 043E0006 EXP 15, 34, 0, 0, 0, v15, v8, v14, v4 ; F800022F 040E080F S_MOV_B32 s4, 0x654 ; BE8403FF 00000654 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v8, s4, v5 ; 10100A04 S_MOV_B32 s5, 0x644 ; BE8503FF 00000644 S_BUFFER_LOAD_DWORD s5, s[0:3], s5 ; C2028005 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s5, v11, v8, 0, 0 ; D2820008 04221605 S_MOV_B32 s6, 0x664 ; BE8603FF 00000664 S_BUFFER_LOAD_DWORD s6, s[0:3], s6 ; C2030006 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v13, v8, 0, 0 ; D2820008 04221A06 V_MUL_F32_e32 v14, s4, v12 ; 101C1804 V_MAD_F32 v14, s5, v6, v14, 0, 0 ; D282000E 043A0C05 V_MAD_F32 v14, s6, v7, v14, 0, 0 ; D282000E 043A0E06 V_MUL_F32_e32 v15, s4, v10 ; 101E1404 V_MAD_F32 v15, s5, v3, v15, 0, 0 ; D282000F 043E0605 V_MAD_F32 v15, s6, v0, v15, 0, 0 ; D282000F 043E0006 EXP 15, 35, 0, 0, 0, v15, v8, v14, v4 ; F800023F 040E080F S_MOV_B32 s4, 0x658 ; BE8403FF 00000658 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v5, s4, v5 ; 100A0A04 S_MOV_B32 s5, 0x648 ; BE8503FF 00000648 S_BUFFER_LOAD_DWORD s5, s[0:3], s5 ; C2028005 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s5, v11, v5, 0, 0 ; D2820005 04161605 S_MOV_B32 s6, 0x668 ; BE8603FF 00000668 S_BUFFER_LOAD_DWORD s6, s[0:3], s6 ; C2030006 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s6, v13, v5, 0, 0 ; D2820005 04161A06 V_MUL_F32_e32 v8, s4, v12 ; 10101804 V_MAD_F32 v6, s5, v6, v8, 0, 0 ; D2820006 04220C05 V_MAD_F32 v6, s6, v7, v6, 0, 0 ; D2820006 041A0E06 V_MUL_F32_e32 v7, s4, v10 ; 100E1404 V_MAD_F32 v3, s5, v3, v7, 0, 0 ; D2820003 041E0605 V_MAD_F32 v0, s6, v0, v3, 0, 0 ; D2820000 040E0006 EXP 15, 36, 0, 0, 0, v0, v5, v6, v4 ; F800024F 04060500 EXP 15, 37, 0, 0, 0, v4, v4, v4, v4 ; F800025F 04040404 EXP 15, 38, 0, 0, 0, v4, v4, v4, v4 ; F800026F 04040404 EXP 15, 39, 0, 0, 0, v4, v4, v4, v4 ; F800027F 04040404 EXP 15, 40, 0, 0, 0, v4, v4, v4, v4 ; F800028F 04040404 EXP 15, 41, 0, 0, 0, v4, v4, v4, v4 ; F800029F 04040404 EXP 15, 42, 0, 0, 0, v4, v4, v4, v4 ; F80002AF 04040404 EXP 15, 43, 0, 0, 0, v4, v4, v4, v4 ; F80002BF 04040404 S_MOV_B32 s4, 0x690 ; BE8403FF 00000690 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_SUBREV_F32_e32 v0, s4, v2 ; 0A000404 S_MOV_B32 s4, 0x694 ; BE8403FF 00000694 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v1, s4, v1 ; 0A020204 S_MOV_B32 s4, 0x610 ; BE8403FF 00000610 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v1 ; 10040204 S_MOV_B32 s4, 0x600 ; BE8403FF 00000600 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0 ; D2820002 040A0004 S_MOV_B32 s4, 0x698 ; BE8403FF 00000698 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v3, s4, v9 ; 0A061204 S_MOV_B32 s4, 0x620 ; BE8403FF 00000620 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v3, v2, 0, 0 ; D2820002 040A0604 S_MOV_B32 s4, 0x630 ; BE8403FF 00000630 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v2, s4, v2 ; 06040404 S_MOV_B32 s4, 0x61c ; BE8403FF 0000061C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v1 ; 10080204 S_MOV_B32 s4, 0x60c ; BE8403FF 0000060C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v0, v4, 0, 0 ; D2820004 04120004 S_MOV_B32 s4, 0x62c ; BE8403FF 0000062C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v3, v4, 0, 0 ; D2820004 04120604 S_MOV_B32 s4, 0x63c ; BE8403FF 0000063C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v4, s4, v4 ; 06080804 S_MOV_B32 s4, 0x1008 ; BE8403FF 00001008 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v4, v2, 0, 0 ; D2820002 040A0804 S_MOV_B32 s4, 0x614 ; BE8403FF 00000614 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v1 ; 100A0204 S_MOV_B32 s4, 0x604 ; BE8403FF 00000604 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v0, v5, 0, 0 ; D2820005 04160004 S_MOV_B32 s4, 0x624 ; BE8403FF 00000624 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v3, v5, 0, 0 ; D2820005 04160604 S_MOV_B32 s4, 0x634 ; BE8403FF 00000634 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s4, v5 ; 060A0A04 S_MOV_B32 s4, 0x1004 ; BE8403FF 00001004 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v5 ; 100A0A04 S_MOV_B32 s4, 0x100c ; BE8403FF 0000100C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s4, v4, v5, 0, 0 ; D2820005 04160804 S_MOV_B32 s4, 0x618 ; BE8403FF 00000618 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s4, v1 ; 10020204 S_MOV_B32 s4, 0x608 ; BE8403FF 00000608 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v0, v1, 0, 0 ; D2820000 04060004 S_MOV_B32 s4, 0x628 ; BE8403FF 00000628 S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v3, v0, 0, 0 ; D2820000 04020604 S_MOV_B32 s4, 0x638 ; BE8403FF 00000638 S_BUFFER_LOAD_DWORD s0, s[0:3], s4 ; C2000004 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v0, s0, v0 ; 06000000 V_ADD_F32_e32 v0, v0, v0 ; 06000100 V_SUB_F32_e32 v0, v0, v4 ; 08000900 EXP 15, 12, 0, 1, 0, v2, v5, v0, v4 ; F80008CF 04000502 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[9], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL IN[3], GENERIC[12], PERSPECTIVE DCL IN[4], GENERIC[13], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 2.0000, -1.0000} 0: DP3 TEMP[0].x, IN[4].xyzz, IN[4].xyzz 1: FSEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].xxxx 2: UIF TEMP[1].xxxx :0 3: MOV TEMP[1].xyz, IMM[0].xxxx 4: ELSE :0 5: RSQ TEMP[0].x, TEMP[0].xxxx 6: MUL TEMP[1].xyz, IN[4].xyzz, TEMP[0].xxxx 7: ENDIF 8: MOV TEMP[2].xy, IN[0].xyyy 9: TEX TEMP[2].xy, TEMP[2], SAMP[0], 2D 10: MAD TEMP[2].xy, TEMP[2].yxxx, IMM[0].zzzz, IMM[0].wwww 11: DP2 TEMP[3].x, TEMP[2].xyyy, -TEMP[2].xyyy 12: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy 13: MAX TEMP[3].x, TEMP[3].xxxx, IMM[0].xxxx 14: ABS TEMP[3].x, TEMP[3].xxxx 15: RSQ TEMP[3].x, TEMP[3].xxxx 16: RCP TEMP[3].x, TEMP[3].xxxx 17: MOV TEMP[2].z, TEMP[3].xxxx 18: DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[2].xyzz 19: ADD TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy 20: MOV TEMP[0].z, TEMP[1].xxxx 21: DP3 TEMP[1].x, IN[2].xyzz, IN[2].xyzz 22: FSEQ TEMP[3].x, TEMP[1].xxxx, IMM[0].xxxx 23: UIF TEMP[3].xxxx :0 24: MOV TEMP[3].xyz, IMM[0].xxxx 25: ELSE :0 26: RSQ TEMP[1].x, TEMP[1].xxxx 27: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[1].xxxx 28: ENDIF 29: DP3 TEMP[0].x, TEMP[3].xyzz, TEMP[2].xyzz 30: DP3 TEMP[1].x, IN[3].xyzz, IN[3].xyzz 31: FSEQ TEMP[3].x, TEMP[1].xxxx, IMM[0].xxxx 32: UIF TEMP[3].xxxx :0 33: MOV TEMP[3].xyz, IMM[0].xxxx 34: ELSE :0 35: RSQ TEMP[1].x, TEMP[1].xxxx 36: MUL TEMP[3].xyz, IN[3].xyzz, TEMP[1].xxxx 37: ENDIF 38: DP3 TEMP[1].x, TEMP[3].xyzz, TEMP[2].xyzz 39: MOV TEMP[0].y, TEMP[1].xxxx 40: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 41: ABS TEMP[1].x, TEMP[1].xxxx 42: RSQ TEMP[1].x, TEMP[1].xxxx 43: MUL TEMP[1].xy, TEMP[1].xxxx, TEMP[0].xyyy 44: MOV TEMP[2].xy, IN[0].xyyy 45: TEX TEMP[2].w, TEMP[2], SAMP[1], 2D 46: MUL TEMP[2].x, TEMP[2].wwww, CONST[0].xxxx 47: MOV TEMP[1].w, TEMP[2].xxxx 48: DP3 TEMP[0].x, IN[1].xyzz, IN[1].xyzz 49: ABS TEMP[2].x, TEMP[0].xxxx 50: RSQ TEMP[3].x, TEMP[2].xxxx 51: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[2].xxxx 52: CMP TEMP[0].x, -TEMP[2].xxxx, TEMP[3].xxxx, IMM[0].xxxx 53: MOV TEMP[1].z, -TEMP[0].xxxx 54: MOV OUT[0], TEMP[1] 55: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %26 = load <8 x i32> addrspace(2)* %25, !tbaa !0 %27 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %28 = load <4 x i32> addrspace(2)* %27, !tbaa !0 %29 = getelementptr [32 x <8 x i32>] addrspace(2)* %3, i32 0, i32 1 %30 = load <8 x i32> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [16 x <4 x i32>] addrspace(2)* %2, i32 0, i32 1 %32 = load <4 x i32> addrspace(2)* %31, !tbaa !0 %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %36 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %37 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %38 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %5, <2 x i32> %7) %39 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %5, <2 x i32> %7) %40 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %5, <2 x i32> %7) %41 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %5, <2 x i32> %7) %42 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %5, <2 x i32> %7) %43 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %5, <2 x i32> %7) %44 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %5, <2 x i32> %7) %45 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %5, <2 x i32> %7) %46 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %5, <2 x i32> %7) %47 = fmul float %44, %44 %48 = fmul float %45, %45 %49 = fadd float %48, %47 %50 = fmul float %46, %46 %51 = fadd float %49, %50 %52 = fcmp oeq float %51, 0.000000e+00 %53 = sext i1 %52 to i32 %54 = bitcast i32 %53 to float %55 = bitcast float %54 to i32 %56 = icmp ne i32 %55, 0 br i1 %56, label %ENDIF, label %ELSE ELSE: ; preds = %main_body %57 = call float @llvm.AMDGPU.rsq.clamped.f32(float %51) %58 = fmul float %44, %57 %59 = fmul float %45, %57 %60 = fmul float %46, %57 br label %ENDIF ENDIF: ; preds = %main_body, %ELSE %temp4.0 = phi float [ %58, %ELSE ], [ 0.000000e+00, %main_body ] %temp5.0 = phi float [ %59, %ELSE ], [ 0.000000e+00, %main_body ] %temp6.0 = phi float [ %60, %ELSE ], [ 0.000000e+00, %main_body ] %61 = bitcast float %33 to i32 %62 = bitcast float %34 to i32 %63 = insertelement <2 x i32> undef, i32 %61, i32 0 %64 = insertelement <2 x i32> %63, i32 %62, i32 1 %65 = bitcast <8 x i32> %26 to <32 x i8> %66 = bitcast <4 x i32> %28 to <16 x i8> %67 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %65, <16 x i8> %66, i32 2) %68 = extractelement <4 x float> %67, i32 0 %69 = extractelement <4 x float> %67, i32 1 %70 = fmul float %69, 2.000000e+00 %71 = fadd float %70, -1.000000e+00 %72 = fmul float %68, 2.000000e+00 %73 = fadd float %72, -1.000000e+00 %74 = fsub float -0.000000e+00, %71 %75 = fsub float -0.000000e+00, %73 %76 = fmul float %71, %74 %77 = fmul float %73, %75 %78 = fadd float %76, %77 %79 = fadd float %78, 1.000000e+00 %80 = fcmp uge float %79, 0.000000e+00 %81 = select i1 %80, float %79, float 0.000000e+00 %82 = call float @fabs(float %81) %83 = call float @llvm.AMDGPU.rsq.clamped.f32(float %82) %84 = fdiv float 1.000000e+00, %83 %85 = fmul float %temp4.0, %71 %86 = fmul float %temp5.0, %73 %87 = fadd float %86, %85 %88 = fmul float %temp6.0, %84 %89 = fadd float %87, %88 %90 = fadd float %89, 1.000000e+00 %91 = fmul float %38, %38 %92 = fmul float %39, %39 %93 = fadd float %92, %91 %94 = fmul float %40, %40 %95 = fadd float %93, %94 %96 = fcmp oeq float %95, 0.000000e+00 %97 = sext i1 %96 to i32 %98 = bitcast i32 %97 to float %99 = bitcast float %98 to i32 %100 = icmp ne i32 %99, 0 br i1 %100, label %ENDIF16, label %ELSE18 ELSE18: ; preds = %ENDIF %101 = call float @llvm.AMDGPU.rsq.clamped.f32(float %95) %102 = fmul float %38, %101 %103 = fmul float %39, %101 %104 = fmul float %40, %101 br label %ENDIF16 ENDIF16: ; preds = %ENDIF, %ELSE18 %temp12.0 = phi float [ %102, %ELSE18 ], [ 0.000000e+00, %ENDIF ] %temp13.0 = phi float [ %103, %ELSE18 ], [ 0.000000e+00, %ENDIF ] %temp14.0 = phi float [ %104, %ELSE18 ], [ 0.000000e+00, %ENDIF ] %105 = fmul float %temp12.0, %71 %106 = fmul float %temp13.0, %73 %107 = fadd float %106, %105 %108 = fmul float %temp14.0, %84 %109 = fadd float %107, %108 %110 = fmul float %41, %41 %111 = fmul float %42, %42 %112 = fadd float %111, %110 %113 = fmul float %43, %43 %114 = fadd float %112, %113 %115 = fcmp oeq float %114, 0.000000e+00 %116 = sext i1 %115 to i32 %117 = bitcast i32 %116 to float %118 = bitcast float %117 to i32 %119 = icmp ne i32 %118, 0 br i1 %119, label %ENDIF19, label %ELSE21 ELSE21: ; preds = %ENDIF16 %120 = call float @llvm.AMDGPU.rsq.clamped.f32(float %114) %121 = fmul float %41, %120 %122 = fmul float %42, %120 %123 = fmul float %43, %120 br label %ENDIF19 ENDIF19: ; preds = %ENDIF16, %ELSE21 %temp12.1 = phi float [ %121, %ELSE21 ], [ 0.000000e+00, %ENDIF16 ] %temp13.1 = phi float [ %122, %ELSE21 ], [ 0.000000e+00, %ENDIF16 ] %temp14.1 = phi float [ %123, %ELSE21 ], [ 0.000000e+00, %ENDIF16 ] %124 = fmul float %temp12.1, %71 %125 = fmul float %temp13.1, %73 %126 = fadd float %125, %124 %127 = fmul float %temp14.1, %84 %128 = fadd float %126, %127 %129 = fmul float %109, %109 %130 = fmul float %128, %128 %131 = fadd float %130, %129 %132 = fmul float %90, %90 %133 = fadd float %131, %132 %134 = call float @fabs(float %133) %135 = call float @llvm.AMDGPU.rsq.clamped.f32(float %134) %136 = fmul float %135, %109 %137 = fmul float %135, %128 %138 = bitcast float %33 to i32 %139 = bitcast float %34 to i32 %140 = insertelement <2 x i32> undef, i32 %138, i32 0 %141 = insertelement <2 x i32> %140, i32 %139, i32 1 %142 = bitcast <8 x i32> %30 to <32 x i8> %143 = bitcast <4 x i32> %32 to <16 x i8> %144 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %141, <32 x i8> %142, <16 x i8> %143, i32 2) %145 = extractelement <4 x float> %144, i32 3 %146 = fmul float %145, %24 %147 = fmul float %35, %35 %148 = fmul float %36, %36 %149 = fadd float %148, %147 %150 = fmul float %37, %37 %151 = fadd float %149, %150 %152 = call float @fabs(float %151) %153 = call float @llvm.AMDGPU.rsq.clamped.f32(float %152) %154 = fmul float %153, %152 %155 = fsub float -0.000000e+00, %152 %156 = call float @llvm.AMDGPU.cndlt(float %155, float %154, float 0.000000e+00) %157 = fsub float -0.000000e+00, %156 %158 = call i32 @llvm.SI.packf16(float %136, float %137) %159 = bitcast i32 %158 to float %160 = call i32 @llvm.SI.packf16(float %157, float %146) %161 = bitcast i32 %160 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %159, float %161, float %159, float %161) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readonly } attributes #3 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v11, v0, 1, 4, [m0] ; C82C1100 V_INTERP_P2_F32 v11, [v11], v1, 1, 4, [m0] ; C82D1101 V_INTERP_P1_F32 v13, v0, 0, 4, [m0] ; C8341000 V_INTERP_P2_F32 v13, [v13], v1, 0, 4, [m0] ; C8351001 V_MUL_F32_e32 v2, v13, v13 ; 10041B0D V_MAD_F32 v2, v11, v11, v2, 0, 0 ; D2820002 040A170B V_INTERP_P1_F32 v16, v0, 2, 4, [m0] ; C8401200 V_INTERP_P2_F32 v16, [v16], v1, 2, 4, [m0] ; C8411201 V_MAD_F32 v17, v16, v16, v2, 0, 0 ; D2820011 040A2110 V_CMP_EQ_F32_e64 s[0:1], v17, 0.000000e+00, 0, 0 ; D0040000 00010111 V_CNDMASK_B32_e64 v2, 0, -1, s[0:1], 0, 0, 0, 0 ; D2000002 00018280 V_CMP_EQ_I32_e64 s[10:11], v2, 0, 0, 0 ; D104000A 00010102 V_INTERP_P1_F32 v2, v0, 2, 3, [m0] ; C8080E00 V_INTERP_P2_F32 v2, [v2], v1, 2, 3, [m0] ; C8090E01 V_INTERP_P1_F32 v3, v0, 1, 3, [m0] ; C80C0D00 V_INTERP_P2_F32 v3, [v3], v1, 1, 3, [m0] ; C80D0D01 V_INTERP_P1_F32 v5, v0, 0, 3, [m0] ; C8140C00 V_INTERP_P2_F32 v5, [v5], v1, 0, 3, [m0] ; C8150C01 V_INTERP_P1_F32 v10, v0, 2, 2, [m0] ; C8280A00 V_INTERP_P2_F32 v10, [v10], v1, 2, 2, [m0] ; C8290A01 V_INTERP_P1_F32 v12, v0, 1, 2, [m0] ; C8300900 V_INTERP_P2_F32 v12, [v12], v1, 1, 2, [m0] ; C8310901 V_INTERP_P1_F32 v14, v0, 0, 2, [m0] ; C8380800 V_INTERP_P2_F32 v14, [v14], v1, 0, 2, [m0] ; C8390801 V_INTERP_P1_F32 v4, v0, 2, 1, [m0] ; C8100600 V_INTERP_P2_F32 v4, [v4], v1, 2, 1, [m0] ; C8110601 V_INTERP_P1_F32 v8, v0, 1, 1, [m0] ; C8200500 V_INTERP_P2_F32 v8, [v8], v1, 1, 1, [m0] ; C8210501 V_INTERP_P1_F32 v9, v0, 0, 1, [m0] ; C8240400 V_INTERP_P2_F32 v9, [v9], v1, 0, 1, [m0] ; C8250401 V_INTERP_P1_F32 v7, v0, 1, 0, [m0] ; C81C0100 V_INTERP_P2_F32 v7, [v7], v1, 1, 0, [m0] ; C81D0101 V_INTERP_P1_F32 v6, v0, 0, 0, [m0] ; C8180000 V_INTERP_P2_F32 v6, [v6], v1, 0, 0, [m0] ; C8190001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 V_MOV_B32_e32 v1, 0.000000e+00 ; 7E020280 V_MOV_B32_e32 v15, v1 ; 7E1E0301 V_MOV_B32_e32 v0, v1 ; 7E000301 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[8:9], s[10:11] ; BE88240A S_XOR_B64 s[8:9], exec, s[8:9] ; 8988087E V_RSQ_CLAMP_F32_e32 v1, v17 ; 7E025911 V_MUL_F32_e32 v0, v16, v1 ; 10000310 V_MUL_F32_e32 v15, v11, v1 ; 101E030B V_MUL_F32_e32 v1, v13, v1 ; 1002030D S_OR_B64 exec, exec, s[8:9] ; 88FE087E S_BUFFER_LOAD_DWORD s0, s[0:3], 0x0 ; C2000100 S_LOAD_DWORDX4 s[8:11], s[4:5], 0x0 ; C0840500 S_LOAD_DWORDX8 s[12:19], s[6:7], 0x0 ; C0C60700 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[16:17], 3, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[12:19], s[8:11] ; F0800300 00431006 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v11, v17, v17 ; 06162311 V_ADD_F32_e32 v11, -1.000000e+00, v11 ; 061616F3 V_MUL_F32_e32 v18, v11, v11 ; 1024170B V_ADD_F32_e32 v13, v16, v16 ; 061A2110 V_ADD_F32_e32 v13, -1.000000e+00, v13 ; 061A1AF3 V_MUL_F32_e64 v16, v13, -v13, 0, 0 ; D2100010 40021B0D V_SUB_F32_e32 v16, v16, v18 ; 08202510 V_ADD_F32_e32 v16, 1.000000e+00, v16 ; 062020F2 V_CMP_U_F32_e32 vcc, v16, v16 ; 7C102110 V_CMP_GE_F32_e64 s[2:3], v16, 0.000000e+00, 0, 0 ; D00C0002 00010110 V_CNDMASK_B32_e64 v17, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000011 00098280 V_CNDMASK_B32_e64 v18, 0, -1, vcc, 0, 0, 0, 0 ; D2000012 01A98280 V_OR_B32_e32 v17, v17, v18 ; 38222511 V_CMP_NE_I32_e64 s[2:3], v17, 0, 0, 0 ; D10A0002 00010111 V_CNDMASK_B32_e64 v16, 0, v16, s[2:3], 0, 0, 0, 0 ; D2000010 000A2080 V_MOV_B32_e32 v17, 0x7fffffff ; 7E2202FF 7FFFFFFF V_AND_B32_e32 v16, v16, v17 ; 36202310 V_RSQ_CLAMP_F32_e32 v16, v16 ; 7E205910 V_MUL_F32_e32 v17, v14, v14 ; 10221D0E V_MAD_F32 v17, v12, v12, v17, 0, 0 ; D2820011 0446190C V_MAD_F32 v20, v10, v10, v17, 0, 0 ; D2820014 0446150A V_CMP_EQ_F32_e64 s[2:3], v20, 0.000000e+00, 0, 0 ; D0040002 00010114 V_CNDMASK_B32_e64 v17, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000011 00098280 V_CMP_EQ_I32_e64 s[2:3], v17, 0, 0, 0 ; D1040002 00010111 V_MOV_B32_e32 v18, 0.000000e+00 ; 7E240280 V_MOV_B32_e32 v19, v18 ; 7E260312 V_MOV_B32_e32 v17, v18 ; 7E220312 S_AND_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822402 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E V_RSQ_CLAMP_F32_e32 v18, v20 ; 7E245914 V_MUL_F32_e32 v17, v10, v18 ; 1022250A V_MUL_F32_e32 v19, v12, v18 ; 1026250C V_MUL_F32_e32 v18, v14, v18 ; 1024250E S_OR_B64 exec, exec, s[2:3] ; 88FE027E V_MOV_B32_e32 v10, s0 ; 7E140200 V_MUL_F32_e32 v12, v5, v5 ; 10180B05 V_MAD_F32 v12, v3, v3, v12, 0, 0 ; D282000C 04320703 V_MAD_F32 v21, v2, v2, v12, 0, 0 ; D2820015 04320502 V_CMP_EQ_F32_e64 s[0:1], v21, 0.000000e+00, 0, 0 ; D0040000 00010115 V_CNDMASK_B32_e64 v12, 0, -1, s[0:1], 0, 0, 0, 0 ; D200000C 00018280 V_CMP_EQ_I32_e64 s[0:1], v12, 0, 0, 0 ; D1040000 0001010C V_MOV_B32_e32 v14, 0.000000e+00 ; 7E1C0280 V_MOV_B32_e32 v20, v14 ; 7E28030E V_MOV_B32_e32 v12, v14 ; 7E18030E S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_RSQ_CLAMP_F32_e32 v14, v21 ; 7E1C5915 V_MUL_F32_e32 v12, v2, v14 ; 10181D02 V_MUL_F32_e32 v20, v3, v14 ; 10281D03 V_MUL_F32_e32 v14, v5, v14 ; 101C1D05 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_MUL_F32_e32 v2, v14, v11 ; 1004170E V_MAD_F32 v2, v20, v13, v2, 0, 0 ; D2820002 040A1B14 V_RCP_F32_e32 v3, v16 ; 7E065510 V_MAD_F32 v2, v12, v3, v2, 0, 0 ; D2820002 040A070C V_MUL_F32_e32 v5, v18, v11 ; 100A1712 V_MAD_F32 v5, v19, v13, v5, 0, 0 ; D2820005 04161B13 V_MAD_F32 v5, v17, v3, v5, 0, 0 ; D2820005 04160711 V_MUL_F32_e32 v12, v5, v5 ; 10180B05 V_MAD_F32 v12, v2, v2, v12, 0, 0 ; D282000C 04320502 V_MUL_F32_e32 v1, v1, v11 ; 10021701 V_MAD_F32 v1, v15, v13, v1, 0, 0 ; D2820001 04061B0F V_MAD_F32 v0, v0, v3, v1, 0, 0 ; D2820000 04060700 V_ADD_F32_e32 v0, 1.000000e+00, v0 ; 060000F2 V_MAD_F32 v0, v0, v0, v12, 0, 0 ; D2820000 04320100 V_MOV_B32_e32 v1, 0x7fffffff ; 7E0202FF 7FFFFFFF V_AND_B32_e32 v0, v0, v1 ; 36000300 V_RSQ_CLAMP_F32_e32 v0, v0 ; 7E005900 V_MUL_F32_e32 v1, v0, v2 ; 10020500 V_MUL_F32_e32 v0, v0, v5 ; 10000B00 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 V_MUL_F32_e32 v1, v9, v9 ; 10021309 V_MAD_F32 v1, v8, v8, v1, 0, 0 ; D2820001 04061108 V_MAD_F32 v1, v4, v4, v1, 0, 0 ; D2820001 04060904 V_MOV_B32_e32 v2, 0x7fffffff ; 7E0402FF 7FFFFFFF V_AND_B32_e32 v2, v1, v2 ; 36040501 V_RSQ_CLAMP_F32_e32 v2, v2 ; 7E045902 V_MUL_F32_e64 v2, v2, |v1|, 0, 0 ; D2100202 00020302 V_OR_B32_e32 v1, 0x80000000, v1 ; 380202FF 80000000 V_CMP_GT_F32_e32 vcc, 0, v1 ; 7C080280 V_CNDMASK_B32_e64 v1, 0.000000e+00, v2, vcc, 0, 0, 0, 0 ; D2000001 01AA0480 V_MOV_B32_e32 v2, 0x80000000 ; 7E0402FF 80000000 V_XOR_B32_e32 v1, v1, v2 ; 3A020501 S_LOAD_DWORDX4 s[0:3], s[4:5], 0x4 ; C0800504 S_LOAD_DWORDX8 s[4:11], s[6:7], 0x8 ; C0C20708 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v2, 8, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[4:11], s[0:3] ; F0800800 00010206 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v2, v2, v10 ; 10041502 V_CVT_PKRTZ_F16_F32_e32 v1, v1, v2 ; 5E020501 EXP 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL OUT[4], GENERIC[12] DCL OUT[5], GENERIC[13] DCL OUT[6], GENERIC[14] DCL OUT[7], GENERIC[15] DCL OUT[8], GENERIC[16] DCL OUT[9], GENERIC[17] DCL OUT[10], GENERIC[18] DCL OUT[11], GENERIC[19] DCL OUT[12], GENERIC[20] DCL CONST[0..256] DCL TEMP[0..8], LOCAL DCL TEMP[9..20], ARRAY(1), LOCAL DCL ADDR[0] IMM[0] FLT32 { 1.0000, 0.0000, 0.5000, 2.0000} IMM[1] INT32 {1, 2, 0, 0} 0: MAD TEMP[0].xy, IN[1].xyyy, CONST[106].xyyy, CONST[106].zwww 1: MUL TEMP[1].x, CONST[107].xxxx, IN[4].xxxx 2: FRC TEMP[2].x, TEMP[1].xxxx 3: ADD TEMP[3].x, TEMP[1].xxxx, -TEMP[2].xxxx 4: FSLT TEMP[2].x, -TEMP[2].xxxx, TEMP[2].xxxx 5: UIF TEMP[2].xxxx :0 6: MOV TEMP[2].x, IMM[0].xxxx 7: ELSE :0 8: MOV TEMP[2].x, IMM[0].yyyy 9: ENDIF 10: FSLT TEMP[4].x, TEMP[1].xxxx, -TEMP[1].xxxx 11: UIF TEMP[4].xxxx :0 12: MOV TEMP[4].x, IMM[0].xxxx 13: ELSE :0 14: MOV TEMP[4].x, IMM[0].yyyy 15: ENDIF 16: MAD TEMP[1].x, TEMP[4].xxxx, TEMP[2].xxxx, TEMP[3].xxxx 17: ABS TEMP[2].x, TEMP[1].xxxx 18: ADD TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz 19: FLR TEMP[2].x, TEMP[2].xxxx 20: SSG TEMP[3].x, TEMP[1].xxxx 21: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 22: F2I TEMP[2].x, TEMP[2].xxxx 23: MAD TEMP[3].xyz, IN[0].xyxx, CONST[107].yyzz, CONST[107].zzyy 24: MOV TEMP[1].xyw, TEMP[3].xyxz 25: MOV TEMP[1].z, IN[2].wwww 26: UARL ADDR[0].x, TEMP[2].xxxx 27: UARL ADDR[0].x, TEMP[2].xxxx 28: DP4 TEMP[3].x, TEMP[1], CONST[ADDR[0].x] 29: UADD TEMP[4].x, TEMP[2].xxxx, IMM[1].xxxx 30: UARL ADDR[0].x, TEMP[4].xxxx 31: DP4 TEMP[4].x, TEMP[1], CONST[ADDR[0].x] 32: MOV TEMP[3].y, TEMP[4].xxxx 33: UADD TEMP[4].x, TEMP[2].xxxx, IMM[1].yyyy 34: UARL ADDR[0].x, TEMP[4].xxxx 35: DP4 TEMP[4].x, TEMP[1], CONST[ADDR[0].x] 36: MOV TEMP[3].z, TEMP[4].xxxx 37: ADD TEMP[1].xyz, TEMP[3].xyzz, -CONST[104].xyzz 38: MUL TEMP[4], TEMP[1].yyyy, CONST[97] 39: MAD TEMP[4], CONST[96], TEMP[1].xxxx, TEMP[4] 40: MAD TEMP[1], CONST[98], TEMP[1].zzzz, TEMP[4] 41: ADD TEMP[4], TEMP[1], CONST[99] 42: ADD TEMP[1].xyz, TEMP[3].xyzz, -CONST[103].xyzz 43: ADD TEMP[3].xyz, -TEMP[3].xyzz, CONST[103].xyzz 44: RCP TEMP[5].x, CONST[102].yyyy 45: MUL TEMP[5].xyz, TEMP[5].xxxx, TEMP[1].xyzz 46: UARL ADDR[0].x, TEMP[2].xxxx 47: UARL ADDR[0].x, TEMP[2].xxxx 48: DP3 TEMP[1].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 49: UADD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx 50: UARL ADDR[0].x, TEMP[6].xxxx 51: DP3 TEMP[6].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 52: MOV TEMP[1].y, TEMP[6].xxxx 53: UADD TEMP[6].x, TEMP[2].xxxx, IMM[1].yyyy 54: UARL ADDR[0].x, TEMP[6].xxxx 55: DP3 TEMP[6].x, IN[3].xyzz, CONST[ADDR[0].x].xyzz 56: MOV TEMP[1].z, TEMP[6].xxxx 57: DP3 TEMP[6].x, TEMP[1].xyzz, TEMP[1].xyzz 58: FSEQ TEMP[7].x, TEMP[6].xxxx, IMM[0].yyyy 59: UIF TEMP[7].xxxx :0 60: MOV TEMP[7].xyz, IMM[0].yyyy 61: ELSE :0 62: RSQ TEMP[6].x, TEMP[6].xxxx 63: MUL TEMP[7].xyz, TEMP[1].xyzz, TEMP[6].xxxx 64: ENDIF 65: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[7].xyzz 66: UARL ADDR[0].x, TEMP[2].xxxx 67: UARL ADDR[0].x, TEMP[2].xxxx 68: DP3 TEMP[1].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 69: UADD TEMP[8].x, TEMP[2].xxxx, IMM[1].xxxx 70: UARL ADDR[0].x, TEMP[8].xxxx 71: DP3 TEMP[8].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 72: MOV TEMP[1].y, TEMP[8].xxxx 73: UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].yyyy 74: UARL ADDR[0].x, TEMP[2].xxxx 75: DP3 TEMP[2].x, IN[2].xyzz, CONST[ADDR[0].x].xyzz 76: MOV TEMP[1].z, TEMP[2].xxxx 77: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 78: FSEQ TEMP[8].x, TEMP[2].xxxx, IMM[0].yyyy 79: UIF TEMP[8].xxxx :0 80: MOV TEMP[8].xyz, IMM[0].yyyy 81: ELSE :0 82: RSQ TEMP[2].x, TEMP[2].xxxx 83: MUL TEMP[8].xyz, TEMP[1].xyzz, TEMP[2].xxxx 84: ENDIF 85: MUL TEMP[1].xyz, TEMP[7].yzxx, TEMP[8].zxyy 86: MAD TEMP[1].xyz, TEMP[8].yzxx, TEMP[7].zxyy, -TEMP[1].xyzz 87: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[8].xyzz 88: MOV TEMP[6].z, TEMP[2].xxxx 89: MUL TEMP[1].xyz, TEMP[1].xyzz, IN[3].wwww 90: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[1].xyzz 91: MOV TEMP[6].y, TEMP[2].xxxx 92: MUL TEMP[1].x, CONST[101].wwww, CONST[101].xxxx 93: RCP TEMP[2].x, TEMP[1].xxxx 94: MOV TEMP[1].y, TEMP[2].xxxx 95: MOV TEMP[3].xw, CONST[105].xxxx 96: MUL TEMP[2].xy, TEMP[1].xyyy, CONST[105].xxxx 97: MOV TEMP[3].yz, TEMP[2].yxyy 98: FSLT TEMP[1].x, CONST[107].yyyy, TEMP[1].xxxx 99: UIF TEMP[1].xxxx :0 100: MOV TEMP[1].x, IMM[0].xxxx 101: ELSE :0 102: MOV TEMP[1].x, IMM[0].yyyy 103: ENDIF 104: ADD TEMP[2].xy, -TEMP[3].xyyy, TEMP[3].zwww 105: MAD TEMP[1].xy, TEMP[1].xxxx, TEMP[2].xyyy, TEMP[3].xyyy 106: MOV TEMP[2].xw, TEMP[4].xxzw 107: MOV TEMP[9].xy, TEMP[0].xyxx 108: MOV TEMP[10].xyz, TEMP[5].xyzx 109: MOV TEMP[11].xyz, TEMP[6].xyzx 110: MOV TEMP[12].xy, TEMP[1].xyxx 111: MOV TEMP[9].zw, IMM[0].yyyy 112: MOV TEMP[10].w, IMM[0].yyyy 113: MOV TEMP[11].w, IMM[0].yyyy 114: MOV TEMP[12].zw, IMM[0].yyyy 115: MUL TEMP[0].x, TEMP[4].yyyy, CONST[256].yyyy 116: MOV TEMP[2].y, TEMP[0].xxxx 117: MAD TEMP[2].xy, CONST[256].zwww, TEMP[4].wwww, TEMP[2].xyyy 118: MAD TEMP[0].x, TEMP[4].zzzz, IMM[0].wwww, -TEMP[4].wwww 119: MOV TEMP[2].z, TEMP[0].xxxx 120: MOV OUT[0], TEMP[2] 121: MOV OUT[1], TEMP[9] 122: MOV OUT[2], TEMP[10] 123: MOV OUT[3], TEMP[11] 124: MOV OUT[4], TEMP[12] 125: MOV OUT[5], TEMP[13] 126: MOV OUT[6], TEMP[14] 127: MOV OUT[7], TEMP[15] 128: MOV OUT[8], TEMP[16] 129: MOV OUT[9], TEMP[17] 130: MOV OUT[10], TEMP[18] 131: MOV OUT[11], TEMP[19] 132: MOV OUT[12], TEMP[20] 133: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1536) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1540) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1544) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1548) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1552) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1556) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1560) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1564) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1568) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1572) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1576) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1580) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1584) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1588) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1592) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1596) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1616) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1628) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1636) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1648) %33 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1652) %34 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1656) %35 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1664) %36 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1668) %37 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1672) %38 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1680) %39 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1696) %40 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1700) %41 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1704) %42 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1708) %43 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1712) %44 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1716) %45 = call float @llvm.SI.load.const(<16 x i8> %12, i32 1720) %46 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4100) %47 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4104) %48 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4108) %49 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0 %51 = add i32 %5, %7 %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %51) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0 %57 = add i32 %5, %7 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0 %63 = add i32 %5, %7 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = extractelement <4 x float> %64, i32 2 %68 = extractelement <4 x float> %64, i32 3 %69 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 3 %70 = load <16 x i8> addrspace(2)* %69, !tbaa !0 %71 = add i32 %5, %7 %72 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %70, i32 0, i32 %71) %73 = extractelement <4 x float> %72, i32 0 %74 = extractelement <4 x float> %72, i32 1 %75 = extractelement <4 x float> %72, i32 2 %76 = extractelement <4 x float> %72, i32 3 %77 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 4 %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0 %79 = add i32 %10, %6 %80 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %78, i32 0, i32 %79) %81 = extractelement <4 x float> %80, i32 0 %82 = fmul float %59, %39 %83 = fadd float %82, %41 %84 = fmul float %60, %40 %85 = fadd float %84, %42 %86 = fmul float %43, %81 %87 = call float @llvm.AMDIL.fraction.(float %86) %88 = fsub float -0.000000e+00, %87 %89 = fadd float %86, %88 %90 = fsub float -0.000000e+00, %87 %91 = fcmp olt float %90, %87 %92 = sext i1 %91 to i32 %93 = bitcast i32 %92 to float %94 = bitcast float %93 to i32 %95 = icmp ne i32 %94, 0 %. = select i1 %95, float 1.000000e+00, float 0.000000e+00 %96 = fsub float -0.000000e+00, %86 %97 = fcmp olt float %86, %96 %98 = sext i1 %97 to i32 %99 = bitcast i32 %98 to float %100 = bitcast float %99 to i32 %101 = icmp ne i32 %100, 0 %temp16.0 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %102 = fmul float %temp16.0, %. %103 = fadd float %102, %89 %104 = call float @fabs(float %103) %105 = fadd float %104, 5.000000e-01 %106 = call float @floor(float %105) %107 = fcmp ugt float %103, 0.000000e+00 %108 = select i1 %107, float 1.000000e+00, float %103 %109 = fcmp uge float %108, 0.000000e+00 %110 = select i1 %109, float %108, float -1.000000e+00 %111 = fmul float %106, %110 %112 = fptosi float %111 to i32 %113 = bitcast i32 %112 to float %114 = fmul float %53, %44 %115 = fadd float %114, %45 %116 = fmul float %54, %44 %117 = fadd float %116, %45 %118 = fmul float %53, %45 %119 = fadd float %118, %44 %120 = bitcast float %113 to i32 %121 = shl i32 %120, 4 %122 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %121) %123 = shl i32 %120, 4 %124 = add i32 %123, 4 %125 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %124) %126 = shl i32 %120, 4 %127 = add i32 %126, 8 %128 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %127) %129 = shl i32 %120, 4 %130 = add i32 %129, 12 %131 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %130) %132 = fmul float %115, %122 %133 = fmul float %117, %125 %134 = fadd float %132, %133 %135 = fmul float %68, %128 %136 = fadd float %134, %135 %137 = fmul float %119, %131 %138 = fadd float %136, %137 %139 = bitcast float %113 to i32 %140 = add i32 %139, 1 %141 = bitcast i32 %140 to float %142 = bitcast float %141 to i32 %143 = shl i32 %142, 4 %144 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %143) %145 = shl i32 %142, 4 %146 = add i32 %145, 4 %147 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %146) %148 = shl i32 %142, 4 %149 = add i32 %148, 8 %150 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %149) %151 = shl i32 %142, 4 %152 = add i32 %151, 12 %153 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %152) %154 = fmul float %115, %144 %155 = fmul float %117, %147 %156 = fadd float %154, %155 %157 = fmul float %68, %150 %158 = fadd float %156, %157 %159 = fmul float %119, %153 %160 = fadd float %158, %159 %161 = bitcast float %113 to i32 %162 = add i32 %161, 2 %163 = bitcast i32 %162 to float %164 = bitcast float %163 to i32 %165 = shl i32 %164, 4 %166 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %165) %167 = shl i32 %164, 4 %168 = add i32 %167, 4 %169 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %168) %170 = shl i32 %164, 4 %171 = add i32 %170, 8 %172 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %171) %173 = shl i32 %164, 4 %174 = add i32 %173, 12 %175 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %174) %176 = fmul float %115, %166 %177 = fmul float %117, %169 %178 = fadd float %176, %177 %179 = fmul float %68, %172 %180 = fadd float %178, %179 %181 = fmul float %119, %175 %182 = fadd float %180, %181 %183 = fsub float -0.000000e+00, %35 %184 = fadd float %138, %183 %185 = fsub float -0.000000e+00, %36 %186 = fadd float %160, %185 %187 = fsub float -0.000000e+00, %37 %188 = fadd float %182, %187 %189 = fmul float %186, %17 %190 = fmul float %186, %18 %191 = fmul float %186, %19 %192 = fmul float %186, %20 %193 = fmul float %13, %184 %194 = fadd float %193, %189 %195 = fmul float %14, %184 %196 = fadd float %195, %190 %197 = fmul float %15, %184 %198 = fadd float %197, %191 %199 = fmul float %16, %184 %200 = fadd float %199, %192 %201 = fmul float %21, %188 %202 = fadd float %201, %194 %203 = fmul float %22, %188 %204 = fadd float %203, %196 %205 = fmul float %23, %188 %206 = fadd float %205, %198 %207 = fmul float %24, %188 %208 = fadd float %207, %200 %209 = fadd float %202, %25 %210 = fadd float %204, %26 %211 = fadd float %206, %27 %212 = fadd float %208, %28 %213 = fsub float -0.000000e+00, %32 %214 = fadd float %138, %213 %215 = fsub float -0.000000e+00, %33 %216 = fadd float %160, %215 %217 = fsub float -0.000000e+00, %34 %218 = fadd float %182, %217 %219 = fsub float -0.000000e+00, %138 %220 = fadd float %219, %32 %221 = fsub float -0.000000e+00, %160 %222 = fadd float %221, %33 %223 = fsub float -0.000000e+00, %182 %224 = fadd float %223, %34 %225 = fdiv float 1.000000e+00, %31 %226 = fmul float %225, %214 %227 = fmul float %225, %216 %228 = fmul float %225, %218 %229 = bitcast float %113 to i32 %230 = shl i32 %229, 4 %231 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %230) %232 = shl i32 %229, 4 %233 = add i32 %232, 4 %234 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %233) %235 = shl i32 %229, 4 %236 = add i32 %235, 8 %237 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %236) %238 = fmul float %73, %231 %239 = fmul float %74, %234 %240 = fadd float %239, %238 %241 = fmul float %75, %237 %242 = fadd float %240, %241 %243 = bitcast float %113 to i32 %244 = add i32 %243, 1 %245 = bitcast i32 %244 to float %246 = bitcast float %245 to i32 %247 = shl i32 %246, 4 %248 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %247) %249 = shl i32 %246, 4 %250 = add i32 %249, 4 %251 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %250) %252 = shl i32 %246, 4 %253 = add i32 %252, 8 %254 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %253) %255 = fmul float %73, %248 %256 = fmul float %74, %251 %257 = fadd float %256, %255 %258 = fmul float %75, %254 %259 = fadd float %257, %258 %260 = bitcast float %113 to i32 %261 = add i32 %260, 2 %262 = bitcast i32 %261 to float %263 = bitcast float %262 to i32 %264 = shl i32 %263, 4 %265 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %264) %266 = shl i32 %263, 4 %267 = add i32 %266, 4 %268 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %267) %269 = shl i32 %263, 4 %270 = add i32 %269, 8 %271 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %270) %272 = fmul float %73, %265 %273 = fmul float %74, %268 %274 = fadd float %273, %272 %275 = fmul float %75, %271 %276 = fadd float %274, %275 %277 = fmul float %242, %242 %278 = fmul float %259, %259 %279 = fadd float %278, %277 %280 = fmul float %276, %276 %281 = fadd float %279, %280 %282 = fcmp oeq float %281, 0.000000e+00 %283 = sext i1 %282 to i32 %284 = bitcast i32 %283 to float %285 = bitcast float %284 to i32 %286 = icmp ne i32 %285, 0 br i1 %286, label %ENDIF107, label %ELSE109 ELSE109: ; preds = %main_body %287 = call float @llvm.AMDGPU.rsq.clamped.f32(float %281) %288 = fmul float %242, %287 %289 = fmul float %259, %287 %290 = fmul float %276, %287 br label %ENDIF107 ENDIF107: ; preds = %main_body, %ELSE109 %temp28.0 = phi float [ %288, %ELSE109 ], [ 0.000000e+00, %main_body ] %temp29.0 = phi float [ %289, %ELSE109 ], [ 0.000000e+00, %main_body ] %temp30.0 = phi float [ %290, %ELSE109 ], [ 0.000000e+00, %main_body ] %291 = fmul float %220, %temp28.0 %292 = fmul float %222, %temp29.0 %293 = fadd float %292, %291 %294 = fmul float %224, %temp30.0 %295 = fadd float %293, %294 %296 = bitcast float %113 to i32 %297 = shl i32 %296, 4 %298 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %297) %299 = shl i32 %296, 4 %300 = add i32 %299, 4 %301 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %300) %302 = shl i32 %296, 4 %303 = add i32 %302, 8 %304 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %303) %305 = fmul float %65, %298 %306 = fmul float %66, %301 %307 = fadd float %306, %305 %308 = fmul float %67, %304 %309 = fadd float %307, %308 %310 = bitcast float %113 to i32 %311 = add i32 %310, 1 %312 = bitcast i32 %311 to float %313 = bitcast float %312 to i32 %314 = shl i32 %313, 4 %315 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %314) %316 = shl i32 %313, 4 %317 = add i32 %316, 4 %318 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %317) %319 = shl i32 %313, 4 %320 = add i32 %319, 8 %321 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %320) %322 = fmul float %65, %315 %323 = fmul float %66, %318 %324 = fadd float %323, %322 %325 = fmul float %67, %321 %326 = fadd float %324, %325 %327 = bitcast float %113 to i32 %328 = add i32 %327, 2 %329 = bitcast i32 %328 to float %330 = bitcast float %329 to i32 %331 = shl i32 %330, 4 %332 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %331) %333 = shl i32 %330, 4 %334 = add i32 %333, 4 %335 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %334) %336 = shl i32 %330, 4 %337 = add i32 %336, 8 %338 = call float @llvm.SI.load.const(<16 x i8> %12, i32 %337) %339 = fmul float %65, %332 %340 = fmul float %66, %335 %341 = fadd float %340, %339 %342 = fmul float %67, %338 %343 = fadd float %341, %342 %344 = fmul float %309, %309 %345 = fmul float %326, %326 %346 = fadd float %345, %344 %347 = fmul float %343, %343 %348 = fadd float %346, %347 %349 = fcmp oeq float %348, 0.000000e+00 %350 = sext i1 %349 to i32 %351 = bitcast i32 %350 to float %352 = bitcast float %351 to i32 %353 = icmp ne i32 %352, 0 br i1 %353, label %ENDIF119, label %ELSE121 ELSE121: ; preds = %ENDIF107 %354 = call float @llvm.AMDGPU.rsq.clamped.f32(float %348) %355 = fmul float %309, %354 %356 = fmul float %326, %354 %357 = fmul float %343, %354 br label %ENDIF119 ENDIF119: ; preds = %ENDIF107, %ELSE121 %temp32.0 = phi float [ %355, %ELSE121 ], [ 0.000000e+00, %ENDIF107 ] %temp33.0 = phi float [ %356, %ELSE121 ], [ 0.000000e+00, %ENDIF107 ] %temp34.0 = phi float [ %357, %ELSE121 ], [ 0.000000e+00, %ENDIF107 ] %358 = fmul float %temp29.0, %temp34.0 %359 = fmul float %temp30.0, %temp32.0 %360 = fmul float %temp28.0, %temp33.0 %361 = fsub float -0.000000e+00, %358 %362 = fmul float %temp33.0, %temp30.0 %363 = fadd float %362, %361 %364 = fsub float -0.000000e+00, %359 %365 = fmul float %temp34.0, %temp28.0 %366 = fadd float %365, %364 %367 = fsub float -0.000000e+00, %360 %368 = fmul float %temp32.0, %temp29.0 %369 = fadd float %368, %367 %370 = fmul float %220, %temp32.0 %371 = fmul float %222, %temp33.0 %372 = fadd float %371, %370 %373 = fmul float %224, %temp34.0 %374 = fadd float %372, %373 %375 = fmul float %363, %76 %376 = fmul float %366, %76 %377 = fmul float %369, %76 %378 = fmul float %220, %375 %379 = fmul float %222, %376 %380 = fadd float %379, %378 %381 = fmul float %224, %377 %382 = fadd float %380, %381 %383 = fmul float %30, %29 %384 = fdiv float 1.000000e+00, %383 %385 = fmul float %383, %38 %386 = fmul float %384, %38 %387 = fcmp olt float %44, %383 %388 = sext i1 %387 to i32 %389 = bitcast i32 %388 to float %390 = bitcast float %389 to i32 %391 = icmp ne i32 %390, 0 %.125 = select i1 %391, float 1.000000e+00, float 0.000000e+00 %392 = fsub float -0.000000e+00, %38 %393 = fadd float %392, %386 %394 = fsub float -0.000000e+00, %385 %395 = fadd float %394, %38 %396 = fmul float %.125, %393 %397 = fadd float %396, %38 %398 = fmul float %.125, %395 %399 = fadd float %398, %385 %400 = fmul float %210, %46 %401 = fmul float %47, %212 %402 = fadd float %401, %209 %403 = fmul float %48, %212 %404 = fadd float %403, %400 %405 = fsub float -0.000000e+00, %212 %406 = fmul float %211, 2.000000e+00 %407 = fadd float %406, %405 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %83, float %85, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %226, float %227, float %228, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %295, float %382, float %374, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %397, float %399, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 40, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 41, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 42, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 43, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %402, float %404, float %407, float %212) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0 ; C0800300 S_MOV_B32 s4, 0x6b0 ; BE8403FF 000006B0 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 V_ADD_I32_e32 v1, s11, v3 ; 4A02060B S_LOAD_DWORDX4 s[12:15], s[8:9], 0x10 ; C0860910 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[12:15][v1] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80030101 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v1, s4, v1 ; 10020204 V_FRACT_F32_e32 v2, v1 ; 7E044101 V_SUB_F32_e32 v3, v1, v2 ; 08060501 V_MOV_B32_e32 v4, 0x80000000 ; 7E0802FF 80000000 V_XOR_B32_e32 v5, v1, v4 ; 3A0A0901 V_CMP_LT_F32_e32 vcc, v1, v5 ; 7C020B01 V_CNDMASK_B32_e64 v1, 0, 1.000000e+00, vcc, 0, 0, 0, 0 ; D2000001 01A9E480 V_XOR_B32_e32 v4, v2, v4 ; 3A080902 V_CMP_LT_F32_e32 vcc, v4, v2 ; 7C020504 V_CNDMASK_B32_e64 v2, 0, 1.000000e+00, vcc, 0, 0, 0, 0 ; D2000002 01A9E480 V_MAD_F32 v1, v1, v2, v3, 0, 0 ; D2820001 040E0501 V_CMP_U_F32_e32 vcc, v1, v1 ; 7C100301 V_CMP_GT_F32_e64 s[4:5], v1, 0.000000e+00, 0, 0 ; D0080004 00010101 V_CNDMASK_B32_e64 v2, 0, -1, s[4:5], 0, 0, 0, 0 ; D2000002 00118280 V_CNDMASK_B32_e64 v3, 0, -1, vcc, 0, 0, 0, 0 ; D2000003 01A98280 V_OR_B32_e32 v2, v2, v3 ; 38040702 V_CMP_NE_I32_e64 s[4:5], v2, 0, 0, 0 ; D10A0004 00010102 V_CNDMASK_B32_e64 v2, v1, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000002 0011E501 V_CMP_U_F32_e32 vcc, v2, v2 ; 7C100502 V_CMP_GE_F32_e64 s[4:5], v2, 0.000000e+00, 0, 0 ; D00C0004 00010102 V_CNDMASK_B32_e64 v3, 0, -1, s[4:5], 0, 0, 0, 0 ; D2000003 00118280 V_CNDMASK_B32_e64 v4, 0, -1, vcc, 0, 0, 0, 0 ; D2000004 01A98280 V_OR_B32_e32 v3, v3, v4 ; 38060903 V_CMP_NE_I32_e64 s[4:5], v3, 0, 0, 0 ; D10A0004 00010103 V_CNDMASK_B32_e64 v2, -1.000000e+00, v2, s[4:5], 0, 0, 0, 0 ; D2000002 001204F3 V_ADD_F32_e64 v1, 5.000000e-01, |v1|, 0, 0 ; D2060201 000202F0 V_FLOOR_F32_e32 v1, v1 ; 7E024901 V_MUL_F32_e32 v1, v1, v2 ; 10020501 V_CVT_I32_F32_e32 v20, v1 ; 7E281101 V_ADD_I32_e32 v1, 1, v20 ; 4A022881 V_LSHLREV_B32_e32 v12, 4, v1 ; 34180284 BUFFER_LOAD_DWORD v4, s[0:3] + v12 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 8000040C V_ADD_I32_e32 v21, s10, v0 ; 4A2A000A S_LOAD_DWORDX4 s[4:7], s[8:9], 0xc ; C082090C S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v21] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010015 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v6, v0, v4 ; 100C0900 V_OR_B32_e32 v5, 4, v12 ; 380A1884 BUFFER_LOAD_DWORD v5, s[0:3] + v5 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000505 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v6, v1, v5, v6, 0, 0 ; D2820006 041A0B01 V_OR_B32_e32 v7, 8, v12 ; 380E1888 BUFFER_LOAD_DWORD v7, s[0:3] + v7 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000707 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v25, v2, v7, v6, 0, 0 ; D2820019 041A0F02 V_LSHLREV_B32_e32 v10, 4, v20 ; 34142884 BUFFER_LOAD_DWORD v6, s[0:3] + v10 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 8000060A S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v9, v0, v6 ; 10120D00 V_OR_B32_e32 v8, 4, v10 ; 38101484 BUFFER_LOAD_DWORD v8, s[0:3] + v8 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000808 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v11, v1, v8, v9, 0, 0 ; D282000B 04261101 V_OR_B32_e32 v9, 8, v10 ; 38121488 BUFFER_LOAD_DWORD v9, s[0:3] + v9 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000909 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v30, v2, v9, v11, 0, 0 ; D282001E 042E1302 V_MUL_F32_e32 v11, v30, v30 ; 10163D1E V_MAD_F32 v13, v25, v25, v11, 0, 0 ; D282000D 042E3319 V_ADD_I32_e32 v11, 2, v20 ; 4A162882 V_LSHLREV_B32_e32 v14, 4, v11 ; 341C1684 BUFFER_LOAD_DWORD v11, s[0:3] + v14 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000B0E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v15, v0, v11 ; 101E1700 V_OR_B32_e32 v16, 4, v14 ; 38201C84 BUFFER_LOAD_DWORD v16, s[0:3] + v16 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001010 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v15, v1, v16, v15, 0, 0 ; D282000F 043E2101 V_OR_B32_e32 v17, 8, v14 ; 38221C88 BUFFER_LOAD_DWORD v17, s[0:3] + v17 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001111 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v31, v2, v17, v15, 0, 0 ; D282001F 043E2302 V_MAD_F32 v32, v31, v31, v13, 0, 0 ; D2820020 04363F1F V_CMP_EQ_F32_e64 s[4:5], v32, 0.000000e+00, 0, 0 ; D0040004 00010120 V_CNDMASK_B32_e64 v13, 0, -1, s[4:5], 0, 0, 0, 0 ; D200000D 00118280 V_CMP_EQ_I32_e64 s[40:41], v13, 0, 0, 0 ; D1040028 0001010D V_OR_B32_e32 v10, 12, v10 ; 3814148C BUFFER_LOAD_DWORD v10, s[0:3] + v10 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80000A0A V_OR_B32_e32 v13, 12, v14 ; 381A1C8C BUFFER_LOAD_DWORD v19, s[0:3] + v13 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 8000130D V_OR_B32_e32 v12, 12, v12 ; 3818188C BUFFER_LOAD_DWORD v18, s[0:3] + v12 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 8000120C S_LOAD_DWORDX4 s[4:7], s[8:9], 0x8 ; C0820908 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[12:15], s[4:7][v21] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010C15 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x4 ; C0820904 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[26:29], s[4:7][v21] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80011A15 S_LOAD_DWORDX4 s[4:7], s[8:9], 0x0 ; C0820900 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[21:24], s[4:7][v21] + 0x0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80011515 S_MOV_B32 s4, 0x100c ; BE8403FF 0000100C S_BUFFER_LOAD_DWORD s4, s[0:3], s4 ; C2020004 S_MOV_B32 s5, 0x1008 ; BE8503FF 00001008 S_BUFFER_LOAD_DWORD s5, s[0:3], s5 ; C2028005 S_MOV_B32 s6, 0x1004 ; BE8603FF 00001004 S_BUFFER_LOAD_DWORD s6, s[0:3], s6 ; C2030006 S_MOV_B32 s7, 0x6b8 ; BE8703FF 000006B8 S_BUFFER_LOAD_DWORD s7, s[0:3], s7 ; C2038007 S_MOV_B32 s8, 0x6b4 ; BE8803FF 000006B4 S_BUFFER_LOAD_DWORD s8, s[0:3], s8 ; C2040008 S_MOV_B32 s9, 0x6ac ; BE8903FF 000006AC S_BUFFER_LOAD_DWORD s9, s[0:3], s9 ; C2048009 S_MOV_B32 s10, 0x6a8 ; BE8A03FF 000006A8 S_BUFFER_LOAD_DWORD s10, s[0:3], s10 ; C205000A S_MOV_B32 s11, 0x6a4 ; BE8B03FF 000006A4 S_BUFFER_LOAD_DWORD s11, s[0:3], s11 ; C205800B S_MOV_B32 s12, 0x6a0 ; BE8C03FF 000006A0 S_BUFFER_LOAD_DWORD s12, s[0:3], s12 ; C206000C S_MOV_B32 s13, 0x690 ; BE8D03FF 00000690 S_BUFFER_LOAD_DWORD s13, s[0:3], s13 ; C206800D S_MOV_B32 s14, 0x688 ; BE8E03FF 00000688 S_BUFFER_LOAD_DWORD s14, s[0:3], s14 ; C207000E S_MOV_B32 s15, 0x684 ; BE8F03FF 00000684 S_BUFFER_LOAD_DWORD s15, s[0:3], s15 ; C207800F S_MOV_B32 s16, 0x680 ; BE9003FF 00000680 S_BUFFER_LOAD_DWORD s16, s[0:3], s16 ; C2080010 S_MOV_B32 s17, 0x678 ; BE9103FF 00000678 S_BUFFER_LOAD_DWORD s17, s[0:3], s17 ; C2088011 S_MOV_B32 s18, 0x674 ; BE9203FF 00000674 S_BUFFER_LOAD_DWORD s18, s[0:3], s18 ; C2090012 S_MOV_B32 s19, 0x670 ; BE9303FF 00000670 S_BUFFER_LOAD_DWORD s19, s[0:3], s19 ; C2098013 S_MOV_B32 s20, 0x664 ; BE9403FF 00000664 S_BUFFER_LOAD_DWORD s20, s[0:3], s20 ; C20A0014 S_MOV_B32 s21, 0x65c ; BE9503FF 0000065C S_BUFFER_LOAD_DWORD s21, s[0:3], s21 ; C20A8015 S_MOV_B32 s22, 0x650 ; BE9603FF 00000650 S_BUFFER_LOAD_DWORD s22, s[0:3], s22 ; C20B0016 S_MOV_B32 s23, 0x63c ; BE9703FF 0000063C S_BUFFER_LOAD_DWORD s23, s[0:3], s23 ; C20B8017 S_MOV_B32 s24, 0x638 ; BE9803FF 00000638 S_BUFFER_LOAD_DWORD s24, s[0:3], s24 ; C20C0018 S_MOV_B32 s25, 0x634 ; BE9903FF 00000634 S_BUFFER_LOAD_DWORD s25, s[0:3], s25 ; C20C8019 S_MOV_B32 s26, 0x630 ; BE9A03FF 00000630 S_BUFFER_LOAD_DWORD s26, s[0:3], s26 ; C20D001A S_MOV_B32 s27, 0x62c ; BE9B03FF 0000062C S_BUFFER_LOAD_DWORD s27, s[0:3], s27 ; C20D801B S_MOV_B32 s28, 0x628 ; BE9C03FF 00000628 S_BUFFER_LOAD_DWORD s28, s[0:3], s28 ; C20E001C S_MOV_B32 s29, 0x624 ; BE9D03FF 00000624 S_BUFFER_LOAD_DWORD s29, s[0:3], s29 ; C20E801D S_MOV_B32 s30, 0x620 ; BE9E03FF 00000620 S_BUFFER_LOAD_DWORD s30, s[0:3], s30 ; C20F001E S_MOV_B32 s31, 0x61c ; BE9F03FF 0000061C S_BUFFER_LOAD_DWORD s31, s[0:3], s31 ; C20F801F S_MOV_B32 s32, 0x618 ; BEA003FF 00000618 S_BUFFER_LOAD_DWORD s32, s[0:3], s32 ; C2100020 S_MOV_B32 s33, 0x614 ; BEA103FF 00000614 S_BUFFER_LOAD_DWORD s33, s[0:3], s33 ; C2108021 S_MOV_B32 s34, 0x610 ; BEA203FF 00000610 S_BUFFER_LOAD_DWORD s34, s[0:3], s34 ; C2110022 S_MOV_B32 s35, 0x60c ; BEA303FF 0000060C S_BUFFER_LOAD_DWORD s35, s[0:3], s35 ; C2118023 S_MOV_B32 s36, 0x608 ; BEA403FF 00000608 S_BUFFER_LOAD_DWORD s36, s[0:3], s36 ; C2120024 S_MOV_B32 s37, 0x604 ; BEA503FF 00000604 S_BUFFER_LOAD_DWORD s37, s[0:3], s37 ; C2128025 S_MOV_B32 s38, 0x600 ; BEA603FF 00000600 S_BUFFER_LOAD_DWORD s38, s[0:3], s38 ; C2130026 V_MOV_B32_e32 v40, 0.000000e+00 ; 7E500280 V_MOV_B32_e32 v41, v40 ; 7E520328 V_MOV_B32_e32 v37, v40 ; 7E4A0328 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_AND_SAVEEXEC_B64 s[40:41], s[40:41] ; BEA82428 S_XOR_B64 s[40:41], exec, s[40:41] ; 89A8287E V_RSQ_CLAMP_F32_e32 v32, v32 ; 7E405920 V_MUL_F32_e32 v37, v31, v32 ; 104A411F V_MUL_F32_e32 v41, v25, v32 ; 10524119 V_MUL_F32_e32 v40, v30, v32 ; 1050411E S_OR_B64 exec, exec, s[40:41] ; 88FE287E V_MOV_B32_e32 v25, s4 ; 7E320204 V_MOV_B32_e32 v31, s5 ; 7E3E0205 V_MOV_B32_e32 v30, s6 ; 7E3C0206 V_MOV_B32_e32 v61, s7 ; 7E7A0207 V_MOV_B32_e32 v52, s8 ; 7E680208 V_MOV_B32_e32 v64, s9 ; 7E800209 V_MOV_B32_e32 v63, s10 ; 7E7E020A V_MOV_B32_e32 v66, s11 ; 7E84020B V_MOV_B32_e32 v65, s12 ; 7E82020C V_MOV_B32_e32 v48, s13 ; 7E60020D V_MOV_B32_e32 v35, s14 ; 7E46020E V_MOV_B32_e32 v39, s15 ; 7E4E020F V_MOV_B32_e32 v43, s16 ; 7E560210 V_MOV_B32_e32 v58, s17 ; 7E740211 V_MOV_B32_e32 v60, s18 ; 7E780212 V_MOV_B32_e32 v59, s19 ; 7E760213 V_MOV_B32_e32 v62, s20 ; 7E7C0214 V_MOV_B32_e32 v56, s21 ; 7E700215 V_MOV_B32_e32 v57, s22 ; 7E720216 V_MOV_B32_e32 v36, s23 ; 7E480217 V_MOV_B32_e32 v32, s24 ; 7E400218 V_MOV_B32_e32 v34, s25 ; 7E440219 V_MOV_B32_e32 v46, s26 ; 7E5C021A V_MOV_B32_e32 v45, s27 ; 7E5A021B V_MOV_B32_e32 v33, s28 ; 7E42021C V_MOV_B32_e32 v42, s29 ; 7E54021D V_MOV_B32_e32 v51, s30 ; 7E66021E V_MOV_B32_e32 v50, s31 ; 7E64021F V_MOV_B32_e32 v38, s32 ; 7E4C0220 V_MOV_B32_e32 v47, s33 ; 7E5E0221 V_MOV_B32_e32 v54, s34 ; 7E6C0222 V_MOV_B32_e32 v53, s35 ; 7E6A0223 V_MOV_B32_e32 v44, s36 ; 7E580224 V_MOV_B32_e32 v49, s37 ; 7E620225 V_MOV_B32_e32 v55, s38 ; 7E6E0226 V_ADD_I32_e32 v67, 1, v20 ; 4A862881 V_LSHLREV_B32_e32 v67, 4, v67 ; 34868684 BUFFER_LOAD_DWORD v68, s[0:3] + v67 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004443 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v68, v12, v68 ; 1088890C V_OR_B32_e32 v69, 4, v67 ; 388A8684 BUFFER_LOAD_DWORD v69, s[0:3] + v69 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004545 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v68, v13, v69, v68, 0, 0 ; D2820044 05128B0D V_OR_B32_e32 v67, 8, v67 ; 38868688 BUFFER_LOAD_DWORD v67, s[0:3] + v67 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004343 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v69, v14, v67, v68, 0, 0 ; D2820045 0512870E V_LSHLREV_B32_e32 v67, 4, v20 ; 34862884 BUFFER_LOAD_DWORD v68, s[0:3] + v67 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004443 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v68, v12, v68 ; 1088890C V_OR_B32_e32 v70, 4, v67 ; 388C8684 BUFFER_LOAD_DWORD v70, s[0:3] + v70 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004646 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v68, v13, v70, v68, 0, 0 ; D2820044 05128D0D V_OR_B32_e32 v67, 8, v67 ; 38868688 BUFFER_LOAD_DWORD v67, s[0:3] + v67 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004343 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v70, v14, v67, v68, 0, 0 ; D2820046 0512870E V_MUL_F32_e32 v67, v70, v70 ; 10868D46 V_MAD_F32 v67, v69, v69, v67, 0, 0 ; D2820043 050E8B45 V_ADD_I32_e32 v20, 2, v20 ; 4A282882 V_LSHLREV_B32_e32 v20, 4, v20 ; 34282884 BUFFER_LOAD_DWORD v68, s[0:3] + v20 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v68, v12, v68 ; 1088890C V_OR_B32_e32 v71, 4, v20 ; 388E2884 BUFFER_LOAD_DWORD v71, s[0:3] + v71 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80004747 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v68, v13, v71, v68, 0, 0 ; D2820044 05128F0D V_OR_B32_e32 v20, 8, v20 ; 38282888 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0 + 0x0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v71, v14, v20, v68, 0, 0 ; D2820047 0512290E V_MAD_F32 v72, v71, v71, v67, 0, 0 ; D2820048 050E8F47 V_CMP_EQ_F32_e64 s[0:1], v72, 0.000000e+00, 0, 0 ; D0040000 00010148 V_CNDMASK_B32_e64 v20, 0, -1, s[0:1], 0, 0, 0, 0 ; D2000014 00018280 V_CMP_EQ_I32_e64 s[0:1], v20, 0, 0, 0 ; D1040000 00010114 V_MOV_B32_e32 v20, 0.000000e+00 ; 7E280280 V_MOV_B32_e32 v67, v20 ; 7E860314 V_MOV_B32_e32 v68, v20 ; 7E880314 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_RSQ_CLAMP_F32_e32 v20, v72 ; 7E285948 V_MUL_F32_e32 v68, v71, v20 ; 10882947 V_MUL_F32_e32 v67, v69, v20 ; 10862945 V_MUL_F32_e32 v20, v70, v20 ; 10282946 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_MAD_F32 v64, v27, v66, v64, 0, 0 ; D2820040 0502851B V_MAD_F32 v26, v26, v65, v63, 0, 0 ; D282001A 04FE831A V_MOV_B32_e32 v27, 0.000000e+00 ; 7E360280 EXP 15, 32, 0, 0, 0, v26, v64, v27, v27 ; F800020F 1B1B401A S_WAITCNT expcnt(0) ; BF8C070F V_MAD_F32 v26, v21, v52, v61, 0, 0 ; D282001A 04F66915 V_MAD_F32 v28, v22, v52, v61, 0, 0 ; D282001C 04F66916 V_MUL_F32_e32 v16, v28, v16 ; 1020211C V_MAD_F32 v11, v26, v11, v16, 0, 0 ; D282000B 0442171A V_MAD_F32 v11, v15, v17, v11, 0, 0 ; D282000B 042E230F V_MAD_F32 v16, v21, v61, v52, 0, 0 ; D2820010 04D27B15 V_MAD_F32 v11, v16, v19, v11, 0, 0 ; D282000B 042E2710 V_SUB_F32_e32 v17, v11, v58 ; 0822750B V_RCP_F32_e32 v19, v62 ; 7E26553E V_MUL_F32_e32 v17, v19, v17 ; 10222313 V_MUL_F32_e32 v5, v28, v5 ; 100A0B1C V_MAD_F32 v4, v26, v4, v5, 0, 0 ; D2820004 0416091A V_MAD_F32 v4, v15, v7, v4, 0, 0 ; D2820004 04120F0F V_MAD_F32 v4, v16, v18, v4, 0, 0 ; D2820004 04122510 V_SUB_F32_e32 v5, v4, v60 ; 080A7904 V_MUL_F32_e32 v5, v19, v5 ; 100A0B13 V_MUL_F32_e32 v7, v28, v8 ; 100E111C V_MAD_F32 v6, v26, v6, v7, 0, 0 ; D2820006 041E0D1A V_MAD_F32 v6, v15, v9, v6, 0, 0 ; D2820006 041A130F V_MAD_F32 v6, v16, v10, v6, 0, 0 ; D2820006 041A1510 V_SUB_F32_e32 v7, v6, v59 ; 080E7706 V_MUL_F32_e32 v7, v19, v7 ; 100E0F13 EXP 15, 33, 0, 0, 0, v7, v5, v17, v27 ; F800021F 1B110507 S_WAITCNT expcnt(0) ; BF8C070F V_SUB_F32_e32 v5, v60, v4 ; 080A093C V_SUB_F32_e32 v7, v59, v6 ; 080E0D3B V_MUL_F32_e32 v8, v7, v20 ; 10102907 V_MAD_F32 v8, v5, v67, v8, 0, 0 ; D2820008 04228705 V_SUB_F32_e32 v9, v58, v11 ; 0812173A V_MAD_F32 v8, v9, v68, v8, 0, 0 ; D2820008 04228909 V_MUL_F32_e32 v10, v37, v20 ; 10142925 V_MUL_F32_e32 v12, v68, v40 ; 10185144 V_SUB_F32_e32 v10, v12, v10 ; 0814150C V_MUL_F32_e32 v10, v10, v3 ; 1014070A V_MUL_F32_e32 v10, v5, v10 ; 10141505 V_MUL_F32_e32 v12, v41, v68 ; 10188929 V_MUL_F32_e32 v13, v67, v37 ; 101A4B43 V_SUB_F32_e32 v12, v13, v12 ; 0818190D V_MUL_F32_e32 v12, v12, v3 ; 1018070C V_MAD_F32 v10, v7, v12, v10, 0, 0 ; D282000A 042A1907 V_MUL_F32_e32 v12, v40, v67 ; 10188728 V_MUL_F32_e32 v13, v20, v41 ; 101A5314 V_SUB_F32_e32 v12, v13, v12 ; 0818190D V_MUL_F32_e32 v0, v12, v3 ; 1000070C V_MAD_F32 v0, v9, v0, v10, 0, 0 ; D2820000 042A0109 V_MUL_F32_e32 v1, v7, v40 ; 10025107 V_MAD_F32 v1, v5, v41, v1, 0, 0 ; D2820001 04065305 V_MAD_F32 v1, v9, v37, v1, 0, 0 ; D2820001 04064B09 EXP 15, 34, 0, 0, 0, v1, v0, v8, v27 ; F800022F 1B080001 S_WAITCNT expcnt(0) ; BF8C070F V_MUL_F32_e32 v0, v56, v57 ; 10007338 V_MUL_F32_e32 v1, v0, v48 ; 10026100 V_SUB_F32_e32 v1, v48, v1 ; 08020330 V_CMP_LT_F32_e32 vcc, v52, v0 ; 7C020134 V_CNDMASK_B32_e64 v2, 0, 1.000000e+00, vcc, 0, 0, 0, 0 ; D2000002 01A9E480 V_MUL_F32_e32 v1, v2, v1 ; 10020302 V_MAD_F32 v1, v0, v48, v1, 0, 0 ; D2820001 04066100 V_RCP_F32_e32 v0, v0 ; 7E005500 V_MUL_F32_e32 v0, v0, v48 ; 10006100 V_SUB_F32_e32 v0, v0, v48 ; 08006100 V_MAD_F32 v0, v2, v0, v48, 0, 0 ; D2820000 04C20102 EXP 15, 35, 0, 0, 0, v0, v1, v27, v27 ; F800023F 1B1B0100 EXP 15, 36, 0, 0, 0, v27, v27, v27, v27 ; F800024F 1B1B1B1B EXP 15, 37, 0, 0, 0, v27, v27, v27, v27 ; F800025F 1B1B1B1B EXP 15, 38, 0, 0, 0, v27, v27, v27, v27 ; F800026F 1B1B1B1B EXP 15, 39, 0, 0, 0, v27, v27, v27, v27 ; F800027F 1B1B1B1B EXP 15, 40, 0, 0, 0, v27, v27, v27, v27 ; F800028F 1B1B1B1B EXP 15, 41, 0, 0, 0, v27, v27, v27, v27 ; F800029F 1B1B1B1B EXP 15, 42, 0, 0, 0, v27, v27, v27, v27 ; F80002AF 1B1B1B1B EXP 15, 43, 0, 0, 0, v27, v27, v27, v27 ; F80002BF 1B1B1B1B S_WAITCNT expcnt(0) ; BF8C070F V_SUB_F32_e32 v0, v6, v43 ; 08005706 V_SUB_F32_e32 v1, v4, v39 ; 08024F04 V_MUL_F32_e32 v2, v1, v54 ; 10046D01 V_MAD_F32 v2, v55, v0, v2, 0, 0 ; D2820002 040A0137 V_SUB_F32_e32 v3, v11, v35 ; 0806470B V_MAD_F32 v2, v51, v3, v2, 0, 0 ; D2820002 040A0733 V_ADD_F32_e32 v2, v2, v46 ; 06045D02 V_MUL_F32_e32 v4, v1, v50 ; 10086501 V_MAD_F32 v4, v53, v0, v4, 0, 0 ; D2820004 04120135 V_MAD_F32 v4, v45, v3, v4, 0, 0 ; D2820004 0412072D V_ADD_F32_e32 v4, v4, v36 ; 06084904 V_MAD_F32 v2, v31, v4, v2, 0, 0 ; D2820002 040A091F V_MUL_F32_e32 v5, v1, v47 ; 100A5F01 V_MAD_F32 v5, v49, v0, v5, 0, 0 ; D2820005 04160131 V_MAD_F32 v5, v42, v3, v5, 0, 0 ; D2820005 0416072A V_ADD_F32_e32 v5, v5, v34 ; 060A4505 V_MUL_F32_e32 v5, v5, v30 ; 100A3D05 V_MAD_F32 v5, v25, v4, v5, 0, 0 ; D2820005 04160919 V_MUL_F32_e32 v1, v1, v38 ; 10024D01 V_MAD_F32 v0, v44, v0, v1, 0, 0 ; D2820000 0406012C V_MAD_F32 v0, v33, v3, v0, 0, 0 ; D2820000 04020721 V_ADD_F32_e32 v0, v0, v32 ; 06004100 V_ADD_F32_e32 v0, v0, v0 ; 06000100 V_SUB_F32_e32 v0, v0, v4 ; 08000900 EXP 15, 12, 0, 1, 0, v2, v5, v0, v4 ; F80008CF 04000502 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[9], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL IN[3], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0] DCL TEMP[0..8], LOCAL IMM[0] FLT32 { 0.0000, -0.0312, 0.9688, 1.0000} IMM[1] FLT32 { 0.0000, 128.0000, 32.0000, 0.9375} IMM[2] FLT32 { 0.9062, 0.8750, 0.8438, 0.8125} IMM[3] FLT32 { 0.7812, 0.7500, 0.7188, 0.6875} IMM[4] FLT32 { 0.6562, 0.6250, 0.5938, 0.5625} IMM[5] FLT32 { 0.5312, 0.5000, 0.4688, 0.4375} IMM[6] FLT32 { 0.4062, 0.3750, 0.3438, 0.3125} IMM[7] FLT32 { 0.2812, 0.2500, 0.2188, 0.1875} IMM[8] FLT32 { 0.1562, 0.1250, 0.0938, 0.0625} IMM[9] FLT32 { 0.0312, 0.0000, 0.0000, 0.0000} 0: DP3 TEMP[0].x, IN[1].xyzz, IN[1].xyzz 1: ABS TEMP[1].x, TEMP[0].xxxx 2: RSQ TEMP[2].x, TEMP[1].xxxx 3: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[1].xxxx 4: CMP TEMP[2].x, -TEMP[1].xxxx, TEMP[2].xxxx, IMM[0].xxxx 5: MOV TEMP[1].z, TEMP[2].xxxx 6: DP3 TEMP[0].x, IN[2].xyzz, IN[2].xyzz 7: ABS TEMP[2].x, TEMP[0].xxxx 8: RSQ TEMP[2].x, TEMP[2].xxxx 9: MUL TEMP[0].xy, TEMP[2].xxxx, IN[2].xyyy 10: MUL TEMP[0].xy, TEMP[0].xyyy, IN[3].xyyy 11: MOV TEMP[3].w, IMM[0].xxxx 12: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, IN[0].xyyy 13: MOV TEMP[4].xy, TEMP[2].xyyy 14: MOV TEMP[4].w, IMM[0].xxxx 15: TXL TEMP[5].x, TEMP[4], SAMP[0], 2D 16: MOV TEMP[6].x, IMM[0].zzzz 17: ADD TEMP[7].x, -TEMP[5].xxxx, IMM[0].zzzz 18: MOV TEMP[0].z, TEMP[7].xxxx 19: MOV TEMP[3].xy, IMM[0].xxxx 20: MOV TEMP[3].z, TEMP[5].xxxx 21: MAD TEMP[5].xy, TEMP[5].xxxx, IMM[0].wxxx, IMM[1].xyyy 22: MOV TEMP[6].yw, TEMP[5].yxyy 23: MOV TEMP[6].z, IMM[0].xxxx 24: FSGE TEMP[5].x, TEMP[7].xxxx, IMM[0].xxxx 25: UIF TEMP[5].xxxx :0 26: MOV TEMP[5], TEMP[3] 27: ELSE :0 28: MOV TEMP[5], TEMP[6] 29: ENDIF 30: MOV TEMP[4].xyz, TEMP[5] 31: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 32: MOV TEMP[3].w, TEMP[7].xxxx 33: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 34: UIF TEMP[7].xxxx :0 35: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 36: MOV TEMP[7].xy, TEMP[2].xyyy 37: MOV TEMP[7].w, IMM[0].xxxx 38: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 39: MOV TEMP[6].x, IMM[1].wwww 40: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[1].wwww 41: MOV TEMP[0].z, TEMP[8].xxxx 42: MOV TEMP[3].xy, TEMP[5].xyxx 43: MOV TEMP[3].z, TEMP[7].xxxx 44: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 45: MOV TEMP[6].yw, TEMP[7].yxyy 46: MOV TEMP[6].z, TEMP[5].zzzz 47: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 48: UIF TEMP[5].xxxx :0 49: MOV TEMP[5], TEMP[3] 50: ELSE :0 51: MOV TEMP[5], TEMP[6] 52: ENDIF 53: MOV TEMP[4].xyz, TEMP[5] 54: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 55: MOV TEMP[3].w, TEMP[7].xxxx 56: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 57: UIF TEMP[7].xxxx :0 58: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 59: MOV TEMP[7].xy, TEMP[2].xyyy 60: MOV TEMP[7].w, IMM[0].xxxx 61: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 62: MOV TEMP[6].x, IMM[2].xxxx 63: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[2].xxxx 64: MOV TEMP[0].z, TEMP[8].xxxx 65: MOV TEMP[3].xy, TEMP[5].xyxx 66: MOV TEMP[3].z, TEMP[7].xxxx 67: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 68: MOV TEMP[6].yw, TEMP[7].yxyy 69: MOV TEMP[6].z, TEMP[5].zzzz 70: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 71: UIF TEMP[5].xxxx :0 72: MOV TEMP[5], TEMP[3] 73: ELSE :0 74: MOV TEMP[5], TEMP[6] 75: ENDIF 76: MOV TEMP[4].xyz, TEMP[5] 77: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 78: MOV TEMP[3].w, TEMP[7].xxxx 79: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 80: UIF TEMP[7].xxxx :0 81: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 82: MOV TEMP[7].xy, TEMP[2].xyyy 83: MOV TEMP[7].w, IMM[0].xxxx 84: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 85: MOV TEMP[6].x, IMM[2].yyyy 86: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[2].yyyy 87: MOV TEMP[0].z, TEMP[8].xxxx 88: MOV TEMP[3].xy, TEMP[5].xyxx 89: MOV TEMP[3].z, TEMP[7].xxxx 90: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 91: MOV TEMP[6].yw, TEMP[7].yxyy 92: MOV TEMP[6].z, TEMP[5].zzzz 93: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 94: UIF TEMP[5].xxxx :0 95: MOV TEMP[5], TEMP[3] 96: ELSE :0 97: MOV TEMP[5], TEMP[6] 98: ENDIF 99: MOV TEMP[4], TEMP[5] 100: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 101: MOV TEMP[3].w, TEMP[7].xxxx 102: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 103: UIF TEMP[7].xxxx :0 104: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 105: MOV TEMP[7].xy, TEMP[2].xyyy 106: MOV TEMP[7].w, IMM[0].xxxx 107: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 108: MOV TEMP[6].x, IMM[2].zzzz 109: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[2].zzzz 110: MOV TEMP[0].z, TEMP[8].xxxx 111: MOV TEMP[3].xy, TEMP[5].xyxx 112: MOV TEMP[3].z, TEMP[7].xxxx 113: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 114: MOV TEMP[6].yw, TEMP[7].yxyy 115: MOV TEMP[6].z, TEMP[5].zzzz 116: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 117: UIF TEMP[5].xxxx :0 118: MOV TEMP[5], TEMP[3] 119: ELSE :0 120: MOV TEMP[5], TEMP[6] 121: ENDIF 122: MOV TEMP[4], TEMP[5] 123: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 124: MOV TEMP[3].w, TEMP[7].xxxx 125: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 126: UIF TEMP[7].xxxx :0 127: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 128: MOV TEMP[7].xy, TEMP[2].xyyy 129: MOV TEMP[7].w, IMM[0].xxxx 130: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 131: MOV TEMP[6].x, IMM[2].wwww 132: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[2].wwww 133: MOV TEMP[0].z, TEMP[8].xxxx 134: MOV TEMP[3].xy, TEMP[5].xyxx 135: MOV TEMP[3].z, TEMP[7].xxxx 136: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 137: MOV TEMP[6].yw, TEMP[7].yxyy 138: MOV TEMP[6].z, TEMP[5].zzzz 139: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 140: UIF TEMP[5].xxxx :0 141: MOV TEMP[5], TEMP[3] 142: ELSE :0 143: MOV TEMP[5], TEMP[6] 144: ENDIF 145: MOV TEMP[4], TEMP[5] 146: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 147: MOV TEMP[3].w, TEMP[7].xxxx 148: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 149: UIF TEMP[7].xxxx :0 150: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 151: MOV TEMP[7].xy, TEMP[2].xyyy 152: MOV TEMP[7].w, IMM[0].xxxx 153: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 154: MOV TEMP[6].x, IMM[3].xxxx 155: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[3].xxxx 156: MOV TEMP[0].z, TEMP[8].xxxx 157: MOV TEMP[3].xy, TEMP[5].xyxx 158: MOV TEMP[3].z, TEMP[7].xxxx 159: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 160: MOV TEMP[6].yw, TEMP[7].yxyy 161: MOV TEMP[6].z, TEMP[5].zzzz 162: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 163: UIF TEMP[5].xxxx :0 164: MOV TEMP[5], TEMP[3] 165: ELSE :0 166: MOV TEMP[5], TEMP[6] 167: ENDIF 168: MOV TEMP[4], TEMP[5] 169: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 170: MOV TEMP[3].w, TEMP[7].xxxx 171: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 172: UIF TEMP[7].xxxx :0 173: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 174: MOV TEMP[7].xy, TEMP[2].xyyy 175: MOV TEMP[7].w, IMM[0].xxxx 176: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 177: MOV TEMP[6].x, IMM[3].yyyy 178: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[3].yyyy 179: MOV TEMP[0].z, TEMP[8].xxxx 180: MOV TEMP[3].xy, TEMP[5].xyxx 181: MOV TEMP[3].z, TEMP[7].xxxx 182: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 183: MOV TEMP[6].yw, TEMP[7].yxyy 184: MOV TEMP[6].z, TEMP[5].zzzz 185: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 186: UIF TEMP[5].xxxx :0 187: MOV TEMP[5], TEMP[3] 188: ELSE :0 189: MOV TEMP[5], TEMP[6] 190: ENDIF 191: MOV TEMP[4], TEMP[5] 192: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 193: MOV TEMP[3].w, TEMP[7].xxxx 194: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 195: UIF TEMP[7].xxxx :0 196: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 197: MOV TEMP[7].xy, TEMP[2].xyyy 198: MOV TEMP[7].w, IMM[0].xxxx 199: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 200: MOV TEMP[6].x, IMM[3].zzzz 201: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[3].zzzz 202: MOV TEMP[0].z, TEMP[8].xxxx 203: MOV TEMP[3].xy, TEMP[5].xyxx 204: MOV TEMP[3].z, TEMP[7].xxxx 205: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 206: MOV TEMP[6].yw, TEMP[7].yxyy 207: MOV TEMP[6].z, TEMP[5].zzzz 208: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 209: UIF TEMP[5].xxxx :0 210: MOV TEMP[5], TEMP[3] 211: ELSE :0 212: MOV TEMP[5], TEMP[6] 213: ENDIF 214: MOV TEMP[4], TEMP[5] 215: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 216: MOV TEMP[3].w, TEMP[7].xxxx 217: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 218: UIF TEMP[7].xxxx :0 219: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 220: MOV TEMP[7].xy, TEMP[2].xyyy 221: MOV TEMP[7].w, IMM[0].xxxx 222: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 223: MOV TEMP[6].x, IMM[3].wwww 224: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[3].wwww 225: MOV TEMP[0].z, TEMP[8].xxxx 226: MOV TEMP[3].xy, TEMP[5].xyxx 227: MOV TEMP[3].z, TEMP[7].xxxx 228: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 229: MOV TEMP[6].yw, TEMP[7].yxyy 230: MOV TEMP[6].z, TEMP[5].zzzz 231: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 232: UIF TEMP[5].xxxx :0 233: MOV TEMP[5], TEMP[3] 234: ELSE :0 235: MOV TEMP[5], TEMP[6] 236: ENDIF 237: MOV TEMP[4], TEMP[5] 238: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 239: MOV TEMP[3].w, TEMP[7].xxxx 240: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 241: UIF TEMP[7].xxxx :0 242: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 243: MOV TEMP[7].xy, TEMP[2].xyyy 244: MOV TEMP[7].w, IMM[0].xxxx 245: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 246: MOV TEMP[6].x, IMM[4].xxxx 247: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[4].xxxx 248: MOV TEMP[0].z, TEMP[8].xxxx 249: MOV TEMP[3].xy, TEMP[5].xyxx 250: MOV TEMP[3].z, TEMP[7].xxxx 251: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 252: MOV TEMP[6].yw, TEMP[7].yxyy 253: MOV TEMP[6].z, TEMP[5].zzzz 254: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 255: UIF TEMP[5].xxxx :0 256: MOV TEMP[5], TEMP[3] 257: ELSE :0 258: MOV TEMP[5], TEMP[6] 259: ENDIF 260: MOV TEMP[4], TEMP[5] 261: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 262: MOV TEMP[3].w, TEMP[7].xxxx 263: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 264: UIF TEMP[7].xxxx :0 265: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 266: MOV TEMP[7].xy, TEMP[2].xyyy 267: MOV TEMP[7].w, IMM[0].xxxx 268: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 269: MOV TEMP[6].x, IMM[4].yyyy 270: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[4].yyyy 271: MOV TEMP[0].z, TEMP[8].xxxx 272: MOV TEMP[3].xy, TEMP[5].xyxx 273: MOV TEMP[3].z, TEMP[7].xxxx 274: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 275: MOV TEMP[6].yw, TEMP[7].yxyy 276: MOV TEMP[6].z, TEMP[5].zzzz 277: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 278: UIF TEMP[5].xxxx :0 279: MOV TEMP[5], TEMP[3] 280: ELSE :0 281: MOV TEMP[5], TEMP[6] 282: ENDIF 283: MOV TEMP[4], TEMP[5] 284: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 285: MOV TEMP[3].w, TEMP[7].xxxx 286: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 287: UIF TEMP[7].xxxx :0 288: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 289: MOV TEMP[7].xy, TEMP[2].xyyy 290: MOV TEMP[7].w, IMM[0].xxxx 291: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 292: MOV TEMP[6].x, IMM[4].zzzz 293: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[4].zzzz 294: MOV TEMP[0].z, TEMP[8].xxxx 295: MOV TEMP[3].xy, TEMP[5].xyxx 296: MOV TEMP[3].z, TEMP[7].xxxx 297: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 298: MOV TEMP[6].yw, TEMP[7].yxyy 299: MOV TEMP[6].z, TEMP[5].zzzz 300: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 301: UIF TEMP[5].xxxx :0 302: MOV TEMP[5], TEMP[3] 303: ELSE :0 304: MOV TEMP[5], TEMP[6] 305: ENDIF 306: MOV TEMP[4], TEMP[5] 307: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 308: MOV TEMP[3].w, TEMP[7].xxxx 309: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 310: UIF TEMP[7].xxxx :0 311: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 312: MOV TEMP[7].xy, TEMP[2].xyyy 313: MOV TEMP[7].w, IMM[0].xxxx 314: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 315: MOV TEMP[6].x, IMM[4].wwww 316: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[4].wwww 317: MOV TEMP[0].z, TEMP[8].xxxx 318: MOV TEMP[3].xy, TEMP[5].xyxx 319: MOV TEMP[3].z, TEMP[7].xxxx 320: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 321: MOV TEMP[6].yw, TEMP[7].yxyy 322: MOV TEMP[6].z, TEMP[5].zzzz 323: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 324: UIF TEMP[5].xxxx :0 325: MOV TEMP[5], TEMP[3] 326: ELSE :0 327: MOV TEMP[5], TEMP[6] 328: ENDIF 329: MOV TEMP[4], TEMP[5] 330: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 331: MOV TEMP[3].w, TEMP[7].xxxx 332: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 333: UIF TEMP[7].xxxx :0 334: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 335: MOV TEMP[7].xy, TEMP[2].xyyy 336: MOV TEMP[7].w, IMM[0].xxxx 337: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 338: MOV TEMP[6].x, IMM[5].xxxx 339: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[5].xxxx 340: MOV TEMP[0].z, TEMP[8].xxxx 341: MOV TEMP[3].xy, TEMP[5].xyxx 342: MOV TEMP[3].z, TEMP[7].xxxx 343: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 344: MOV TEMP[6].yw, TEMP[7].yxyy 345: MOV TEMP[6].z, TEMP[5].zzzz 346: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 347: UIF TEMP[5].xxxx :0 348: MOV TEMP[5], TEMP[3] 349: ELSE :0 350: MOV TEMP[5], TEMP[6] 351: ENDIF 352: MOV TEMP[4], TEMP[5] 353: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 354: MOV TEMP[3].w, TEMP[7].xxxx 355: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 356: UIF TEMP[7].xxxx :0 357: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 358: MOV TEMP[7].xy, TEMP[2].xyyy 359: MOV TEMP[7].w, IMM[0].xxxx 360: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 361: MOV TEMP[6].x, IMM[5].yyyy 362: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[5].yyyy 363: MOV TEMP[0].z, TEMP[8].xxxx 364: MOV TEMP[3].xy, TEMP[5].xyxx 365: MOV TEMP[3].z, TEMP[7].xxxx 366: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 367: MOV TEMP[6].yw, TEMP[7].yxyy 368: MOV TEMP[6].z, TEMP[5].zzzz 369: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 370: UIF TEMP[5].xxxx :0 371: MOV TEMP[5], TEMP[3] 372: ELSE :0 373: MOV TEMP[5], TEMP[6] 374: ENDIF 375: MOV TEMP[4], TEMP[5] 376: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 377: MOV TEMP[3].w, TEMP[7].xxxx 378: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 379: UIF TEMP[7].xxxx :0 380: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 381: MOV TEMP[7].xy, TEMP[2].xyyy 382: MOV TEMP[7].w, IMM[0].xxxx 383: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 384: MOV TEMP[6].x, IMM[5].zzzz 385: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[5].zzzz 386: MOV TEMP[0].z, TEMP[8].xxxx 387: MOV TEMP[3].xy, TEMP[5].xyxx 388: MOV TEMP[3].z, TEMP[7].xxxx 389: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 390: MOV TEMP[6].yw, TEMP[7].yxyy 391: MOV TEMP[6].z, TEMP[5].zzzz 392: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 393: UIF TEMP[5].xxxx :0 394: MOV TEMP[5], TEMP[3] 395: ELSE :0 396: MOV TEMP[5], TEMP[6] 397: ENDIF 398: MOV TEMP[4], TEMP[5] 399: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 400: MOV TEMP[3].w, TEMP[7].xxxx 401: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 402: UIF TEMP[7].xxxx :0 403: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 404: MOV TEMP[7].xy, TEMP[2].xyyy 405: MOV TEMP[7].w, IMM[0].xxxx 406: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 407: MOV TEMP[6].x, IMM[5].wwww 408: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[5].wwww 409: MOV TEMP[0].z, TEMP[8].xxxx 410: MOV TEMP[3].xy, TEMP[5].xyxx 411: MOV TEMP[3].z, TEMP[7].xxxx 412: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 413: MOV TEMP[6].yw, TEMP[7].yxyy 414: MOV TEMP[6].z, TEMP[5].zzzz 415: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 416: UIF TEMP[5].xxxx :0 417: MOV TEMP[5], TEMP[3] 418: ELSE :0 419: MOV TEMP[5], TEMP[6] 420: ENDIF 421: MOV TEMP[4], TEMP[5] 422: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 423: MOV TEMP[3].w, TEMP[7].xxxx 424: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 425: UIF TEMP[7].xxxx :0 426: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 427: MOV TEMP[7].xy, TEMP[2].xyyy 428: MOV TEMP[7].w, IMM[0].xxxx 429: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 430: MOV TEMP[6].x, IMM[6].xxxx 431: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[6].xxxx 432: MOV TEMP[0].z, TEMP[8].xxxx 433: MOV TEMP[3].xy, TEMP[5].xyxx 434: MOV TEMP[3].z, TEMP[7].xxxx 435: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 436: MOV TEMP[6].yw, TEMP[7].yxyy 437: MOV TEMP[6].z, TEMP[5].zzzz 438: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 439: UIF TEMP[5].xxxx :0 440: MOV TEMP[5], TEMP[3] 441: ELSE :0 442: MOV TEMP[5], TEMP[6] 443: ENDIF 444: MOV TEMP[4], TEMP[5] 445: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 446: MOV TEMP[3].w, TEMP[7].xxxx 447: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 448: UIF TEMP[7].xxxx :0 449: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 450: MOV TEMP[7].xy, TEMP[2].xyyy 451: MOV TEMP[7].w, IMM[0].xxxx 452: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 453: MOV TEMP[6].x, IMM[6].yyyy 454: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[6].yyyy 455: MOV TEMP[0].z, TEMP[8].xxxx 456: MOV TEMP[3].xy, TEMP[5].xyxx 457: MOV TEMP[3].z, TEMP[7].xxxx 458: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 459: MOV TEMP[6].yw, TEMP[7].yxyy 460: MOV TEMP[6].z, TEMP[5].zzzz 461: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 462: UIF TEMP[5].xxxx :0 463: MOV TEMP[5], TEMP[3] 464: ELSE :0 465: MOV TEMP[5], TEMP[6] 466: ENDIF 467: MOV TEMP[4], TEMP[5] 468: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 469: MOV TEMP[3].w, TEMP[7].xxxx 470: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 471: UIF TEMP[7].xxxx :0 472: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 473: MOV TEMP[7].xy, TEMP[2].xyyy 474: MOV TEMP[7].w, IMM[0].xxxx 475: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 476: MOV TEMP[6].x, IMM[6].zzzz 477: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[6].zzzz 478: MOV TEMP[0].z, TEMP[8].xxxx 479: MOV TEMP[3].xy, TEMP[5].xyxx 480: MOV TEMP[3].z, TEMP[7].xxxx 481: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 482: MOV TEMP[6].yw, TEMP[7].yxyy 483: MOV TEMP[6].z, TEMP[5].zzzz 484: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 485: UIF TEMP[5].xxxx :0 486: MOV TEMP[5], TEMP[3] 487: ELSE :0 488: MOV TEMP[5], TEMP[6] 489: ENDIF 490: MOV TEMP[4], TEMP[5] 491: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 492: MOV TEMP[3].w, TEMP[7].xxxx 493: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 494: UIF TEMP[7].xxxx :0 495: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 496: MOV TEMP[7].xy, TEMP[2].xyyy 497: MOV TEMP[7].w, IMM[0].xxxx 498: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 499: MOV TEMP[6].x, IMM[6].wwww 500: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[6].wwww 501: MOV TEMP[0].z, TEMP[8].xxxx 502: MOV TEMP[3].xy, TEMP[5].xyxx 503: MOV TEMP[3].z, TEMP[7].xxxx 504: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 505: MOV TEMP[6].yw, TEMP[7].yxyy 506: MOV TEMP[6].z, TEMP[5].zzzz 507: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 508: UIF TEMP[5].xxxx :0 509: MOV TEMP[5], TEMP[3] 510: ELSE :0 511: MOV TEMP[5], TEMP[6] 512: ENDIF 513: MOV TEMP[4], TEMP[5] 514: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 515: MOV TEMP[3].w, TEMP[7].xxxx 516: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 517: UIF TEMP[7].xxxx :0 518: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 519: MOV TEMP[7].xy, TEMP[2].xyyy 520: MOV TEMP[7].w, IMM[0].xxxx 521: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 522: MOV TEMP[6].x, IMM[7].xxxx 523: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[7].xxxx 524: MOV TEMP[0].z, TEMP[8].xxxx 525: MOV TEMP[3].xy, TEMP[5].xyxx 526: MOV TEMP[3].z, TEMP[7].xxxx 527: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 528: MOV TEMP[6].yw, TEMP[7].yxyy 529: MOV TEMP[6].z, TEMP[5].zzzz 530: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 531: UIF TEMP[5].xxxx :0 532: MOV TEMP[5], TEMP[3] 533: ELSE :0 534: MOV TEMP[5], TEMP[6] 535: ENDIF 536: MOV TEMP[4], TEMP[5] 537: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 538: MOV TEMP[3].w, TEMP[7].xxxx 539: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 540: UIF TEMP[7].xxxx :0 541: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 542: MOV TEMP[7].xy, TEMP[2].xyyy 543: MOV TEMP[7].w, IMM[0].xxxx 544: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 545: MOV TEMP[6].x, IMM[7].yyyy 546: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[7].yyyy 547: MOV TEMP[0].z, TEMP[8].xxxx 548: MOV TEMP[3].xy, TEMP[5].xyxx 549: MOV TEMP[3].z, TEMP[7].xxxx 550: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 551: MOV TEMP[6].yw, TEMP[7].yxyy 552: MOV TEMP[6].z, TEMP[5].zzzz 553: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 554: UIF TEMP[5].xxxx :0 555: MOV TEMP[5], TEMP[3] 556: ELSE :0 557: MOV TEMP[5], TEMP[6] 558: ENDIF 559: MOV TEMP[4], TEMP[5] 560: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 561: MOV TEMP[3].w, TEMP[7].xxxx 562: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 563: UIF TEMP[7].xxxx :0 564: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 565: MOV TEMP[7].xy, TEMP[2].xyyy 566: MOV TEMP[7].w, IMM[0].xxxx 567: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 568: MOV TEMP[6].x, IMM[7].zzzz 569: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[7].zzzz 570: MOV TEMP[0].z, TEMP[8].xxxx 571: MOV TEMP[3].xy, TEMP[5].xyxx 572: MOV TEMP[3].z, TEMP[7].xxxx 573: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 574: MOV TEMP[6].yw, TEMP[7].yxyy 575: MOV TEMP[6].z, TEMP[5].zzzz 576: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 577: UIF TEMP[5].xxxx :0 578: MOV TEMP[5], TEMP[3] 579: ELSE :0 580: MOV TEMP[5], TEMP[6] 581: ENDIF 582: MOV TEMP[4], TEMP[5] 583: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 584: MOV TEMP[3].w, TEMP[7].xxxx 585: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 586: UIF TEMP[7].xxxx :0 587: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 588: MOV TEMP[7].xy, TEMP[2].xyyy 589: MOV TEMP[7].w, IMM[0].xxxx 590: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 591: MOV TEMP[6].x, IMM[7].wwww 592: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[7].wwww 593: MOV TEMP[0].z, TEMP[8].xxxx 594: MOV TEMP[3].xy, TEMP[5].xyxx 595: MOV TEMP[3].z, TEMP[7].xxxx 596: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 597: MOV TEMP[6].yw, TEMP[7].yxyy 598: MOV TEMP[6].z, TEMP[5].zzzz 599: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 600: UIF TEMP[5].xxxx :0 601: MOV TEMP[5], TEMP[3] 602: ELSE :0 603: MOV TEMP[5], TEMP[6] 604: ENDIF 605: MOV TEMP[4], TEMP[5] 606: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 607: MOV TEMP[3].w, TEMP[7].xxxx 608: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 609: UIF TEMP[7].xxxx :0 610: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 611: MOV TEMP[7].xy, TEMP[2].xyyy 612: MOV TEMP[7].w, IMM[0].xxxx 613: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 614: MOV TEMP[6].x, IMM[8].xxxx 615: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[8].xxxx 616: MOV TEMP[0].z, TEMP[8].xxxx 617: MOV TEMP[3].xy, TEMP[5].xyxx 618: MOV TEMP[3].z, TEMP[7].xxxx 619: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 620: MOV TEMP[6].yw, TEMP[7].yxyy 621: MOV TEMP[6].z, TEMP[5].zzzz 622: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 623: UIF TEMP[5].xxxx :0 624: MOV TEMP[5], TEMP[3] 625: ELSE :0 626: MOV TEMP[5], TEMP[6] 627: ENDIF 628: MOV TEMP[4], TEMP[5] 629: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 630: MOV TEMP[3].w, TEMP[7].xxxx 631: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 632: UIF TEMP[7].xxxx :0 633: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 634: MOV TEMP[7].xy, TEMP[2].xyyy 635: MOV TEMP[7].w, IMM[0].xxxx 636: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 637: MOV TEMP[6].x, IMM[8].yyyy 638: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[8].yyyy 639: MOV TEMP[0].z, TEMP[8].xxxx 640: MOV TEMP[3].xy, TEMP[5].xyxx 641: MOV TEMP[3].z, TEMP[7].xxxx 642: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 643: MOV TEMP[6].yw, TEMP[7].yxyy 644: MOV TEMP[6].z, TEMP[5].zzzz 645: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 646: UIF TEMP[5].xxxx :0 647: MOV TEMP[5], TEMP[3] 648: ELSE :0 649: MOV TEMP[5], TEMP[6] 650: ENDIF 651: MOV TEMP[4], TEMP[5] 652: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 653: MOV TEMP[3].w, TEMP[7].xxxx 654: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 655: UIF TEMP[7].xxxx :0 656: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 657: MOV TEMP[7].xy, TEMP[2].xyyy 658: MOV TEMP[7].w, IMM[0].xxxx 659: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 660: MOV TEMP[6].x, IMM[8].zzzz 661: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[8].zzzz 662: MOV TEMP[0].z, TEMP[8].xxxx 663: MOV TEMP[3].xy, TEMP[5].xyxx 664: MOV TEMP[3].z, TEMP[7].xxxx 665: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 666: MOV TEMP[6].yw, TEMP[7].yxyy 667: MOV TEMP[6].z, TEMP[5].zzzz 668: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 669: UIF TEMP[5].xxxx :0 670: MOV TEMP[5], TEMP[3] 671: ELSE :0 672: MOV TEMP[5], TEMP[6] 673: ENDIF 674: MOV TEMP[4], TEMP[5] 675: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 676: MOV TEMP[3].w, TEMP[7].xxxx 677: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 678: UIF TEMP[7].xxxx :0 679: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 680: MOV TEMP[7].xy, TEMP[2].xyyy 681: MOV TEMP[7].w, IMM[0].xxxx 682: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 683: MOV TEMP[6].x, IMM[8].wwww 684: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[8].wwww 685: MOV TEMP[0].z, TEMP[8].xxxx 686: MOV TEMP[3].xy, TEMP[5].xyxx 687: MOV TEMP[3].z, TEMP[7].xxxx 688: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 689: MOV TEMP[6].yw, TEMP[7].yxyy 690: MOV TEMP[6].z, TEMP[5].zzzz 691: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 692: UIF TEMP[5].xxxx :0 693: MOV TEMP[5], TEMP[3] 694: ELSE :0 695: MOV TEMP[5], TEMP[6] 696: ENDIF 697: MOV TEMP[4], TEMP[5] 698: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 699: MOV TEMP[3].w, TEMP[7].xxxx 700: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 701: UIF TEMP[7].xxxx :0 702: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 703: MOV TEMP[7].xy, TEMP[2].xyyy 704: MOV TEMP[7].w, IMM[0].xxxx 705: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 706: MOV TEMP[6].x, IMM[9].xxxx 707: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[9].xxxx 708: MOV TEMP[0].z, TEMP[8].xxxx 709: MOV TEMP[3].xy, TEMP[5].xyxx 710: MOV TEMP[3].z, TEMP[7].xxxx 711: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 712: MOV TEMP[6].yw, TEMP[7].yxyy 713: MOV TEMP[6].z, TEMP[5].zzzz 714: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 715: UIF TEMP[5].xxxx :0 716: MOV TEMP[5], TEMP[3] 717: ELSE :0 718: MOV TEMP[5], TEMP[6] 719: ENDIF 720: MOV TEMP[4], TEMP[5] 721: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 722: MOV TEMP[3].w, TEMP[7].xxxx 723: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 724: UIF TEMP[7].xxxx :0 725: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 726: MOV TEMP[7].xy, TEMP[2].xyyy 727: MOV TEMP[7].w, IMM[0].xxxx 728: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 729: MOV TEMP[6].x, IMM[0].xxxx 730: MOV TEMP[0].z, -TEMP[7].xxxx 731: MOV TEMP[3].xy, TEMP[5].xyxx 732: MOV TEMP[3].z, TEMP[7].xxxx 733: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 734: MOV TEMP[6].yw, TEMP[7].yxyy 735: MOV TEMP[6].z, TEMP[5].zzzz 736: FSGE TEMP[5].x, TEMP[0].zzzz, IMM[0].xxxx 737: UIF TEMP[5].xxxx :0 738: MOV TEMP[5], TEMP[3] 739: ELSE :0 740: MOV TEMP[5], TEMP[6] 741: ENDIF 742: MOV TEMP[4], TEMP[5] 743: ADD TEMP[7].x, TEMP[5].wwww, IMM[0].wwww 744: MOV TEMP[3].w, TEMP[7].xxxx 745: FSGE TEMP[7].x, IMM[1].zzzz, TEMP[7].xxxx 746: UIF TEMP[7].xxxx :0 747: MAD TEMP[2].xy, TEMP[0].xyyy, IMM[0].yyyy, TEMP[2].xyyy 748: MOV TEMP[7].xy, TEMP[2].xyyy 749: MOV TEMP[7].w, IMM[0].xxxx 750: TXL TEMP[7].x, TEMP[7], SAMP[0], 2D 751: MOV TEMP[6].x, IMM[0].yyyy 752: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[0].yyyy 753: MOV TEMP[3].xy, TEMP[5].xyxx 754: MOV TEMP[3].z, TEMP[7].xxxx 755: MAD TEMP[7].xy, TEMP[7].xxxx, IMM[0].wxxx, IMM[1].xyyy 756: MOV TEMP[6].yw, TEMP[7].yxyy 757: MOV TEMP[6].z, TEMP[5].zzzz 758: FSGE TEMP[5].x, TEMP[8].xxxx, IMM[0].xxxx 759: I2F TEMP[7].x, TEMP[5].xxxx 760: CMP TEMP[3], TEMP[7].xxxx, TEMP[3], TEMP[3] 761: NOT TEMP[5].x, TEMP[5].xxxx 762: I2F TEMP[5].x, TEMP[5].xxxx 763: CMP TEMP[3], TEMP[5].xxxx, TEMP[6], TEMP[3] 764: MOV TEMP[4], TEMP[3] 765: ENDIF 766: ENDIF 767: ENDIF 768: ENDIF 769: ENDIF 770: ENDIF 771: ENDIF 772: ENDIF 773: ENDIF 774: ENDIF 775: ENDIF 776: ENDIF 777: ENDIF 778: ENDIF 779: ENDIF 780: ENDIF 781: ENDIF 782: ENDIF 783: ENDIF 784: ENDIF 785: ENDIF 786: ENDIF 787: ENDIF 788: ENDIF 789: ENDIF 790: ENDIF 791: ENDIF 792: ENDIF 793: ENDIF 794: ENDIF 795: ENDIF 796: ENDIF 797: ADD TEMP[3].x, TEMP[4].xxxx, IMM[9].xxxx 798: ADD TEMP[5].x, -TEMP[4].zzzz, TEMP[3].xxxx 799: ADD TEMP[2].x, -TEMP[4].yyyy, TEMP[4].xxxx 800: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[2].xxxx 801: MAD TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx, -TEMP[3].xxxx 802: ADD TEMP[3].x, TEMP[5].xxxx, -TEMP[2].xxxx 803: RCP TEMP[3].x, TEMP[3].xxxx 804: MAD TEMP[4].x, TEMP[4].xxxx, -TEMP[3].xxxx, IMM[0].wwww 805: MUL TEMP[2].xy, TEMP[4].xxxx, -TEMP[0].xyyy 806: MAD TEMP[0].xy, -TEMP[0].xyyy, TEMP[4].xxxx, IN[0].xyyy 807: MOV TEMP[0].xy, TEMP[0].xyyy 808: TEX TEMP[0].w, TEMP[0], SAMP[1], 2D 809: MUL TEMP[0].x, TEMP[0].wwww, CONST[0].xxxx 810: MOV TEMP[1].w, TEMP[0].xxxx 811: MOV TEMP[1].xy, TEMP[2].xyxx 812: MOV OUT[0], TEMP[1] 813: END wine: Unhandled page fault on read access to 0x3bb763b8 at address 0x7cdb6977 (thread 0009), starting debugger... fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x1 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x55f32b4,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x26 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x55f32b4,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x1 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x55f32b4,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x26 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x55f32b4,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x1 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x5a33ad0,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x26 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x5a33ad0,symt:(nil)) fixme:dbghelp_dwarf:dwarf2_parse_pointer_type Unsupported children fixme:dbghelp_dwarf:dwarf2_parse_subprogram_block Unhandled Tag type 0x26 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x5a33ad0,symt:0x5b909b0) fixme:dbghelp_dwarf:dwarf2_parse_subprogram Unhandled Tag type 0x26 at ctx(0x33c37c,L"radeonsi_dri.so"), for debug_info(abbrev:0x76422f4,symt:0x7a69298) fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_lookup_type Unable to load forward reference for tag 1f fixme:dbghelp_dwarf:dwarf2_parse_pointer_type Unsupported children wine client error:2c: write: Bad file descriptor