From d3923733daaee5a0a56e4ca472b14da066ad355f Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Tue, 4 Nov 2014 16:32:48 +0200 Subject: [PATCH] drm/i915: WaSetupGtModeTdRowDispatch:snb considered harmful Apparently setting this bit to limit TD dispatch is causing problems. The documentation is as thin as always so give up and just leave it to default. Clear all bits to default values in case bios decided intervene. References: https://bugs.freedesktop.org/show_bug.cgi?id=79996 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_pm.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7a69eba..953cdbb 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5519,11 +5519,6 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN, _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); - /* WaSetupGtModeTdRowDispatch:snb */ - if (IS_SNB_GT1(dev)) - I915_WRITE(GEN6_GT_MODE, - _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); - /* WaDisable_RenderCache_OperationalFlush:snb */ I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); @@ -5535,6 +5530,7 @@ static void gen6_init_clock_gating(struct drm_device *dev) * disable bit, which we don't touch here, but it's good * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). */ + I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); I915_WRITE(GEN6_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); -- 1.9.1