FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %35, float %36, float %37, float %38) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %35, float %36, float %37, float %38) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 ERROR: ld.so: object '/home/elad/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MUL TEMP[0], TEMP[0], CONST[0] 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = bitcast <8 x i32> %29 to <32 x i8> %39 = bitcast <4 x i32> %31 to <16 x i8> %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %38, <16 x i8> %39, i32 2) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %41, %24 %46 = fmul float %42, %25 %47 = fmul float %43, %26 %48 = fmul float %44, %27 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %45, float %46, float %47, float %48) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430002 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v3, v4, 0, 0, 0, 0 ; D2100004 02020903 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v2, v5, 0, 0, 0, 0 ; D2100005 02020B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0 ; D2100006 02020D01 S_BUFFER_LOAD_DWORD s0, s[0:3], 0 ; C2000100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s0 ; 7E0E0200 V_MUL_F32_e64 v0, v0, v7, 0, 0, 0, 0 ; D2100000 02020F00 EXP 15, 0, 0, 1, 1, v0, v6, v5, v4 ; F800180F 04050600 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MUL TEMP[0], TEMP[0], CONST[0] 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0 %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = bitcast <8 x i32> %29 to <32 x i8> %39 = bitcast <4 x i32> %31 to <16 x i8> %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %38, <16 x i8> %39, i32 2) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %41, %24 %46 = fmul float %42, %25 %47 = fmul float %43, %26 %48 = fmul float %44, %27 %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float %51 = call i32 @llvm.SI.packf16(float %47, float %48) %52 = bitcast i32 %51 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430002 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v3, v4, 0, 0, 0, 0 ; D2100004 02020903 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v2, v5, 0, 0, 0, 0 ; D2100005 02020B02 V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4 ; 5E080905 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0 ; D2100005 02020B01 S_BUFFER_LOAD_DWORD s0, s[0:3], 0 ; C2000100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s0 ; 7E0C0200 V_MUL_F32_e64 v0, v0, v6, 0, 0, 0, 0 ; D2100000 02020D00 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5 ; 5E000B00 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL OUT[1], POSITION DCL OUT[2], STENCIL DCL SAMP[0] DCL SAMP[1] IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: TEX OUT[1].z, IN[0], SAMP[0], 2D 2: TEX OUT[2].y, IN[0], SAMP[1], 2D 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 1 %27 = load <8 x i32> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 1 %29 = load <4 x i32> addrspace(2)* %28, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %32 = bitcast float %30 to i32 %33 = bitcast float %31 to i32 %34 = insertelement <2 x i32> undef, i32 %32, i32 0 %35 = insertelement <2 x i32> %34, i32 %33, i32 1 %36 = bitcast <8 x i32> %23 to <32 x i8> %37 = bitcast <4 x i32> %25 to <16 x i8> %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %36, <16 x i8> %37, i32 2) %39 = extractelement <4 x float> %38, i32 2 %40 = bitcast float %30 to i32 %41 = bitcast float %31 to i32 %42 = insertelement <2 x i32> undef, i32 %40, i32 0 %43 = insertelement <2 x i32> %42, i32 %41, i32 1 %44 = bitcast <8 x i32> %27 to <32 x i8> %45 = bitcast <4 x i32> %29 to <16 x i8> %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %44, <16 x i8> %45, i32 2) %47 = extractelement <4 x float> %46, i32 1 call void @llvm.SI.export(i32 3, i32 0, i32 0, i32 8, i32 0, float %39, float %47, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[8:11], s[2:3], 4 ; C0840304 S_LOAD_DWORDX8 s[12:19], s[4:5], 8 ; C0C60508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v0, 2, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800200 00430002 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v1, 4, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800400 00010102 V_MOV_B32_e32 v2, 0.000000e+00 ; 7E040280 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 3, 8, 0, 0, 0, v1, v0, v2, v2 ; F8000083 02020001 S_WAITCNT expcnt(0) ; BF8C070F V_MOV_B32_e32 v0, 1.000000e+00 ; 7E0002F2 EXP 15, 0, 0, 1, 1, v2, v2, v2, v0 ; F800180F 00020202 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL OUT[1], POSITION DCL OUT[2], STENCIL DCL SAMP[0] DCL SAMP[1] IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: TEX OUT[1].z, IN[0], SAMP[0], 2D 2: TEX OUT[2].y, IN[0], SAMP[1], 2D 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 1 %27 = load <8 x i32> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 1 %29 = load <4 x i32> addrspace(2)* %28, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %32 = bitcast float %30 to i32 %33 = bitcast float %31 to i32 %34 = insertelement <2 x i32> undef, i32 %32, i32 0 %35 = insertelement <2 x i32> %34, i32 %33, i32 1 %36 = bitcast <8 x i32> %23 to <32 x i8> %37 = bitcast <4 x i32> %25 to <16 x i8> %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %36, <16 x i8> %37, i32 2) %39 = extractelement <4 x float> %38, i32 2 %40 = bitcast float %30 to i32 %41 = bitcast float %31 to i32 %42 = insertelement <2 x i32> undef, i32 %40, i32 0 %43 = insertelement <2 x i32> %42, i32 %41, i32 1 %44 = bitcast <8 x i32> %27 to <32 x i8> %45 = bitcast <4 x i32> %29 to <16 x i8> %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %44, <16 x i8> %45, i32 2) %47 = extractelement <4 x float> %46, i32 1 call void @llvm.SI.export(i32 3, i32 0, i32 0, i32 8, i32 0, float %39, float %47, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[8:11], s[2:3], 4 ; C0840304 S_LOAD_DWORDX8 s[12:19], s[4:5], 8 ; C0C60508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v0, 2, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800200 00430002 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v1, 4, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800400 00010102 V_MOV_B32_e32 v2, 0.000000e+00 ; 7E040280 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 3, 8, 0, 0, 0, v1, v0, v2, v2 ; F8000083 02020001 S_WAITCNT expcnt(0) ; BF8C070F V_MOV_B32_e32 v0, 1.000000e+00 ; 7E0002F2 EXP 15, 0, 0, 1, 1, v2, v2, v2, v0 ; F800180F 00020202 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0039, 255.0000} IMM[1] FLT32 { 0.5000, 128.0000, 32768.0000, 3.0000} IMM[2] FLT32 { 2.0000, 0.0078, 0.0000, 0.0000} 0: MUL TEMP[0].xy, IMM[0].xxxy, IN[0].xyxx 1: MUL TEMP[1].xy, IMM[0].xxxy, IN[0].zyzx 2: MOV TEMP[2].xy, TEMP[0].xyyy 3: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D 4: MOV TEMP[3].xy, TEMP[1].xyyy 5: TEX TEMP[3].x, TEMP[3], SAMP[0], 2D 6: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 7: MUL TEMP[0].xy, IMM[0].xxxy, IN[0].xwxx 8: MOV TEMP[3].xy, TEMP[0].xyyy 9: TEX TEMP[3].x, TEMP[3], SAMP[0], 2D 10: MUL TEMP[1].xy, IMM[0].xxxy, IN[0].zwzx 11: MOV TEMP[4].xy, TEMP[1].xyyy 12: TEX TEMP[4].x, TEMP[4], SAMP[0], 2D 13: MAX TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 14: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 15: ADD TEMP[0].x, TEMP[2].xxxx, CONST[0].zzzz 16: RCP TEMP[0].x, TEMP[0].xxxx 17: MUL TEMP[2].x, TEMP[0].xxxx, CONST[0].wwww 18: MUL TEMP[2].xyz, TEMP[2].xxxx, IMM[1].xyzz 19: FRC TEMP[3].xyz, TEMP[2].xyzz 20: ADD TEMP[2].xyz, TEMP[2].xyzz, -TEMP[3].xyzz 21: MUL TEMP[2].xyz, TEMP[2].xyzz, IMM[0].zzzz 22: FRC TEMP[2].xyz, TEMP[2].xyzz 23: MAD TEMP[1].xyz, TEMP[2].xyzz, IMM[0].wwww, IMM[1].xxxx 24: MOV TEMP[2].xyz, TEMP[2].xyzx 25: FRC TEMP[3].xyz, TEMP[1].xyzz 26: ADD TEMP[1].xyz, -TEMP[3].xyzz, TEMP[1].xyzz 27: DP3 TEMP[1].x, TEMP[1].xyzz, IMM[2].xyzz 28: MAD TEMP[0].x, CONST[0].wwww, TEMP[0].xxxx, -TEMP[1].xxxx 29: MUL TEMP[0].x, TEMP[0].xxxx, IMM[1].wwww 30: MOV TEMP[2].w, TEMP[0].xxxx 31: MOV OUT[0], TEMP[2] 32: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %26 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %27 = load <8 x i32> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %29 = load <4 x i32> addrspace(2)* %28, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %32 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %34 = fmul float 1.000000e+00, %30 %35 = fmul float 1.000000e+00, %31 %36 = fmul float 1.000000e+00, %32 %37 = fmul float 1.000000e+00, %31 %38 = bitcast float %34 to i32 %39 = bitcast float %35 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = bitcast <8 x i32> %27 to <32 x i8> %43 = bitcast <4 x i32> %29 to <16 x i8> %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %42, <16 x i8> %43, i32 2) %45 = extractelement <4 x float> %44, i32 0 %46 = bitcast float %36 to i32 %47 = bitcast float %37 to i32 %48 = insertelement <2 x i32> undef, i32 %46, i32 0 %49 = insertelement <2 x i32> %48, i32 %47, i32 1 %50 = bitcast <8 x i32> %27 to <32 x i8> %51 = bitcast <4 x i32> %29 to <16 x i8> %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %50, <16 x i8> %51, i32 2) %53 = extractelement <4 x float> %52, i32 0 %54 = fcmp uge float %45, %53 %55 = select i1 %54, float %45, float %53 %56 = fmul float 1.000000e+00, %30 %57 = fmul float 1.000000e+00, %33 %58 = bitcast float %56 to i32 %59 = bitcast float %57 to i32 %60 = insertelement <2 x i32> undef, i32 %58, i32 0 %61 = insertelement <2 x i32> %60, i32 %59, i32 1 %62 = bitcast <8 x i32> %27 to <32 x i8> %63 = bitcast <4 x i32> %29 to <16 x i8> %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %62, <16 x i8> %63, i32 2) %65 = extractelement <4 x float> %64, i32 0 %66 = fmul float 1.000000e+00, %32 %67 = fmul float 1.000000e+00, %33 %68 = bitcast float %66 to i32 %69 = bitcast float %67 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = bitcast <8 x i32> %27 to <32 x i8> %73 = bitcast <4 x i32> %29 to <16 x i8> %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %72, <16 x i8> %73, i32 2) %75 = extractelement <4 x float> %74, i32 0 %76 = fcmp uge float %65, %75 %77 = select i1 %76, float %65, float %75 %78 = fcmp uge float %55, %77 %79 = select i1 %78, float %55, float %77 %80 = fadd float %79, %24 %81 = fdiv float 1.000000e+00, %80 %82 = fmul float %81, %25 %83 = fmul float %82, 5.000000e-01 %84 = fmul float %82, 1.280000e+02 %85 = fmul float %82, 3.276800e+04 %86 = call float @llvm.AMDIL.fraction.(float %83) %87 = call float @llvm.AMDIL.fraction.(float %84) %88 = call float @llvm.AMDIL.fraction.(float %85) %89 = fsub float -0.000000e+00, %86 %90 = fadd float %83, %89 %91 = fsub float -0.000000e+00, %87 %92 = fadd float %84, %91 %93 = fsub float -0.000000e+00, %88 %94 = fadd float %85, %93 %95 = fmul float %90, 0x3F6FFF79C0000000 %96 = fmul float %92, 0x3F6FFF79C0000000 %97 = fmul float %94, 0x3F6FFF79C0000000 %98 = call float @llvm.AMDIL.fraction.(float %95) %99 = call float @llvm.AMDIL.fraction.(float %96) %100 = call float @llvm.AMDIL.fraction.(float %97) %101 = fmul float %98, 2.550000e+02 %102 = fadd float %101, 5.000000e-01 %103 = fmul float %99, 2.550000e+02 %104 = fadd float %103, 5.000000e-01 %105 = fmul float %100, 2.550000e+02 %106 = fadd float %105, 5.000000e-01 %107 = call float @llvm.AMDIL.fraction.(float %102) %108 = call float @llvm.AMDIL.fraction.(float %104) %109 = call float @llvm.AMDIL.fraction.(float %106) %110 = fsub float -0.000000e+00, %107 %111 = fadd float %110, %102 %112 = fsub float -0.000000e+00, %108 %113 = fadd float %112, %104 %114 = fsub float -0.000000e+00, %109 %115 = fadd float %114, %106 %116 = fmul float %111, 2.000000e+00 %117 = fmul float %113, 0x3F80004320000000 %118 = fadd float %117, %116 %119 = fmul float %115, 0x3F0040BFE0000000 %120 = fadd float %118, %119 %121 = fsub float -0.000000e+00, %120 %122 = fmul float %25, %81 %123 = fadd float %122, %121 %124 = fmul float %123, 3.000000e+00 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %98, float %99, float %100, float %124) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_INTERP_P1_F32 v2, v0, 2, 0, [m0] ; C8080200 V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0] ; C8090201 S_LOAD_DWORDX4 s[12:15], s[2:3], 0 ; C0860300 S_LOAD_DWORDX8 s[16:23], s[4:5], 0 ; C0C80500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v4, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[16:23], s[12:15] ; F0800100 00640402 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 V_MOV_B32_e32 v6, v3 ; 7E0C0303 IMAGE_SAMPLE v7, 1, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15] ; F0800100 00640705 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_U_F32_e64 s[2:3], v7, v4, 0, 0, 0, 0 ; D0100002 02020907 V_CMP_GE_F32_e64 s[4:5], v7, v4, 0, 0, 0, 0 ; D00C0004 02020907 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v4, v4, v7, s[2:3], 0, 0, 0, 0 ; D2000004 000A0F04 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 IMAGE_SAMPLE v0, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[16:23], s[12:15] ; F0800100 00640002 V_MOV_B32_e32 v6, v3 ; 7E0C0303 IMAGE_SAMPLE v1, 1, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15] ; F0800100 00640105 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_U_F32_e64 s[2:3], v1, v0, 0, 0, 0, 0 ; D0100002 02020101 V_CMP_GE_F32_e64 s[4:5], v1, v0, 0, 0, 0, 0 ; D00C0004 02020101 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v0, v0, v1, s[2:3], 0, 0, 0, 0 ; D2000000 000A0300 V_CMP_U_F32_e64 s[2:3], v0, v4, 0, 0, 0, 0 ; D0100002 02020900 V_CMP_GE_F32_e64 s[4:5], v0, v4, 0, 0, 0, 0 ; D00C0004 02020900 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v0, v4, v0, s[2:3], 0, 0, 0, 0 ; D2000000 000A0104 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v0, s4, v0 ; 06000004 V_RCP_F32_e32 v0, v0 ; 7E005500 S_BUFFER_LOAD_DWORD s0, s[0:3], 3 ; C2000103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s0, v0 ; 10000000 V_MUL_F32_e32 v1, 1.280000e+02, v0 ; 100200FF 43000000 V_FRACT_F32_e32 v2, v1 ; 7E044101 V_SUB_F32_e32 v1, v1, v2 ; 08020501 V_MUL_F32_e32 v1, 3.906000e-03, v1 ; 100202FF 3B7FFBCE V_FRACT_F32_e32 v1, v1 ; 7E024101 V_MOV_B32_e32 v2, 2.550000e+02 ; 7E0402FF 437F0000 V_MAD_F32 v3, v1, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820003 03C20501 V_FRACT_F32_e32 v4, v3 ; 7E084103 V_SUB_F32_e32 v3, v4, v3 ; 08060704 V_MUL_F32_e32 v4, 5.000000e-01, v0 ; 100800F0 V_FRACT_F32_e32 v5, v4 ; 7E0A4104 V_SUB_F32_e32 v4, v4, v5 ; 08080B04 V_MUL_F32_e32 v4, 3.906000e-03, v4 ; 100808FF 3B7FFBCE V_FRACT_F32_e32 v4, v4 ; 7E084104 V_MAD_F32 v5, v4, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820005 03C20504 V_FRACT_F32_e32 v6, v5 ; 7E0C4105 V_SUB_F32_e32 v5, v5, v6 ; 080A0D05 V_ADD_F32_e32 v5, v5, v5 ; 060A0B05 V_MOV_B32_e32 v6, -7.813000e-03 ; 7E0C02FF BC000219 V_MAD_F32 v3, v3, v6, v5, 0, 0, 0, 0 ; D2820003 04160D03 V_MUL_F32_e32 v5, 3.276800e+04, v0 ; 100A00FF 47000000 V_FRACT_F32_e32 v6, v5 ; 7E0C4105 V_SUB_F32_e32 v5, v5, v6 ; 080A0D05 V_MUL_F32_e32 v5, 3.906000e-03, v5 ; 100A0AFF 3B7FFBCE V_FRACT_F32_e32 v5, v5 ; 7E0A4105 V_MAD_F32 v2, v5, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820002 03C20505 V_FRACT_F32_e32 v6, v2 ; 7E0C4102 V_SUB_F32_e32 v2, v2, v6 ; 08040D02 V_MOV_B32_e32 v6, 3.100000e-05 ; 7E0C02FF 380205FF V_MAD_F32 v2, v2, v6, v3, 0, 0, 0, 0 ; D2820002 040E0D02 V_SUB_F32_e32 v0, v2, v0 ; 08000102 V_MUL_F32_e32 v0, -3.000000e+00, v0 ; 100000FF C0400000 EXP 15, 0, 0, 1, 1, v4, v1, v5, v0 ; F800180F 00050104 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0039, 255.0000} IMM[1] FLT32 { 0.5000, 128.0000, 32768.0000, 3.0000} IMM[2] FLT32 { 2.0000, 0.0078, 0.0000, 0.0000} 0: MUL TEMP[0].xy, IMM[0].xxxy, IN[0].xyxx 1: MUL TEMP[1].xy, IMM[0].xxxy, IN[0].zyzx 2: MOV TEMP[2].xy, TEMP[0].xyyy 3: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D 4: MOV TEMP[3].xy, TEMP[1].xyyy 5: TEX TEMP[3].x, TEMP[3], SAMP[0], 2D 6: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 7: MUL TEMP[0].xy, IMM[0].xxxy, IN[0].xwxx 8: MOV TEMP[3].xy, TEMP[0].xyyy 9: TEX TEMP[3].x, TEMP[3], SAMP[0], 2D 10: MUL TEMP[1].xy, IMM[0].xxxy, IN[0].zwzx 11: MOV TEMP[4].xy, TEMP[1].xyyy 12: TEX TEMP[4].x, TEMP[4], SAMP[0], 2D 13: MAX TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 14: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 15: ADD TEMP[0].x, TEMP[2].xxxx, CONST[0].zzzz 16: RCP TEMP[0].x, TEMP[0].xxxx 17: MUL TEMP[2].x, TEMP[0].xxxx, CONST[0].wwww 18: MUL TEMP[2].xyz, TEMP[2].xxxx, IMM[1].xyzz 19: FRC TEMP[3].xyz, TEMP[2].xyzz 20: ADD TEMP[2].xyz, TEMP[2].xyzz, -TEMP[3].xyzz 21: MUL TEMP[2].xyz, TEMP[2].xyzz, IMM[0].zzzz 22: FRC TEMP[2].xyz, TEMP[2].xyzz 23: MAD TEMP[1].xyz, TEMP[2].xyzz, IMM[0].wwww, IMM[1].xxxx 24: MOV TEMP[2].xyz, TEMP[2].xyzx 25: FRC TEMP[3].xyz, TEMP[1].xyzz 26: ADD TEMP[1].xyz, -TEMP[3].xyzz, TEMP[1].xyzz 27: DP3 TEMP[1].x, TEMP[1].xyzz, IMM[2].xyzz 28: MAD TEMP[0].x, CONST[0].wwww, TEMP[0].xxxx, -TEMP[1].xxxx 29: MUL TEMP[0].x, TEMP[0].xxxx, IMM[1].wwww 30: MOV TEMP[2].w, TEMP[0].xxxx 31: MOV OUT[0], TEMP[2] 32: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %26 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %27 = load <8 x i32> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %29 = load <4 x i32> addrspace(2)* %28, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %32 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %34 = fmul float 1.000000e+00, %30 %35 = fmul float 1.000000e+00, %31 %36 = fmul float 1.000000e+00, %32 %37 = fmul float 1.000000e+00, %31 %38 = bitcast float %34 to i32 %39 = bitcast float %35 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = bitcast <8 x i32> %27 to <32 x i8> %43 = bitcast <4 x i32> %29 to <16 x i8> %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %42, <16 x i8> %43, i32 2) %45 = extractelement <4 x float> %44, i32 0 %46 = bitcast float %36 to i32 %47 = bitcast float %37 to i32 %48 = insertelement <2 x i32> undef, i32 %46, i32 0 %49 = insertelement <2 x i32> %48, i32 %47, i32 1 %50 = bitcast <8 x i32> %27 to <32 x i8> %51 = bitcast <4 x i32> %29 to <16 x i8> %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %50, <16 x i8> %51, i32 2) %53 = extractelement <4 x float> %52, i32 0 %54 = fcmp uge float %45, %53 %55 = select i1 %54, float %45, float %53 %56 = fmul float 1.000000e+00, %30 %57 = fmul float 1.000000e+00, %33 %58 = bitcast float %56 to i32 %59 = bitcast float %57 to i32 %60 = insertelement <2 x i32> undef, i32 %58, i32 0 %61 = insertelement <2 x i32> %60, i32 %59, i32 1 %62 = bitcast <8 x i32> %27 to <32 x i8> %63 = bitcast <4 x i32> %29 to <16 x i8> %64 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %62, <16 x i8> %63, i32 2) %65 = extractelement <4 x float> %64, i32 0 %66 = fmul float 1.000000e+00, %32 %67 = fmul float 1.000000e+00, %33 %68 = bitcast float %66 to i32 %69 = bitcast float %67 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = bitcast <8 x i32> %27 to <32 x i8> %73 = bitcast <4 x i32> %29 to <16 x i8> %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %72, <16 x i8> %73, i32 2) %75 = extractelement <4 x float> %74, i32 0 %76 = fcmp uge float %65, %75 %77 = select i1 %76, float %65, float %75 %78 = fcmp uge float %55, %77 %79 = select i1 %78, float %55, float %77 %80 = fadd float %79, %24 %81 = fdiv float 1.000000e+00, %80 %82 = fmul float %81, %25 %83 = fmul float %82, 5.000000e-01 %84 = fmul float %82, 1.280000e+02 %85 = fmul float %82, 3.276800e+04 %86 = call float @llvm.AMDIL.fraction.(float %83) %87 = call float @llvm.AMDIL.fraction.(float %84) %88 = call float @llvm.AMDIL.fraction.(float %85) %89 = fsub float -0.000000e+00, %86 %90 = fadd float %83, %89 %91 = fsub float -0.000000e+00, %87 %92 = fadd float %84, %91 %93 = fsub float -0.000000e+00, %88 %94 = fadd float %85, %93 %95 = fmul float %90, 0x3F6FFF79C0000000 %96 = fmul float %92, 0x3F6FFF79C0000000 %97 = fmul float %94, 0x3F6FFF79C0000000 %98 = call float @llvm.AMDIL.fraction.(float %95) %99 = call float @llvm.AMDIL.fraction.(float %96) %100 = call float @llvm.AMDIL.fraction.(float %97) %101 = fmul float %98, 2.550000e+02 %102 = fadd float %101, 5.000000e-01 %103 = fmul float %99, 2.550000e+02 %104 = fadd float %103, 5.000000e-01 %105 = fmul float %100, 2.550000e+02 %106 = fadd float %105, 5.000000e-01 %107 = call float @llvm.AMDIL.fraction.(float %102) %108 = call float @llvm.AMDIL.fraction.(float %104) %109 = call float @llvm.AMDIL.fraction.(float %106) %110 = fsub float -0.000000e+00, %107 %111 = fadd float %110, %102 %112 = fsub float -0.000000e+00, %108 %113 = fadd float %112, %104 %114 = fsub float -0.000000e+00, %109 %115 = fadd float %114, %106 %116 = fmul float %111, 2.000000e+00 %117 = fmul float %113, 0x3F80004320000000 %118 = fadd float %117, %116 %119 = fmul float %115, 0x3F0040BFE0000000 %120 = fadd float %118, %119 %121 = fsub float -0.000000e+00, %120 %122 = fmul float %25, %81 %123 = fadd float %122, %121 %124 = fmul float %123, 3.000000e+00 %125 = call i32 @llvm.SI.packf16(float %98, float %99) %126 = bitcast i32 %125 to float %127 = call i32 @llvm.SI.packf16(float %100, float %124) %128 = bitcast i32 %127 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %126, float %128, float %126, float %128) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_INTERP_P1_F32 v2, v0, 2, 0, [m0] ; C8080200 V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0] ; C8090201 S_LOAD_DWORDX4 s[12:15], s[2:3], 0 ; C0860300 S_LOAD_DWORDX8 s[16:23], s[4:5], 0 ; C0C80500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v4, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[16:23], s[12:15] ; F0800100 00640402 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 V_MOV_B32_e32 v6, v3 ; 7E0C0303 IMAGE_SAMPLE v7, 1, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15] ; F0800100 00640705 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_U_F32_e64 s[2:3], v7, v4, 0, 0, 0, 0 ; D0100002 02020907 V_CMP_GE_F32_e64 s[4:5], v7, v4, 0, 0, 0, 0 ; D00C0004 02020907 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v4, v4, v7, s[2:3], 0, 0, 0, 0 ; D2000004 000A0F04 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 IMAGE_SAMPLE v0, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[16:23], s[12:15] ; F0800100 00640002 V_MOV_B32_e32 v6, v3 ; 7E0C0303 IMAGE_SAMPLE v1, 1, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15] ; F0800100 00640105 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_U_F32_e64 s[2:3], v1, v0, 0, 0, 0, 0 ; D0100002 02020101 V_CMP_GE_F32_e64 s[4:5], v1, v0, 0, 0, 0, 0 ; D00C0004 02020101 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v0, v0, v1, s[2:3], 0, 0, 0, 0 ; D2000000 000A0300 V_CMP_U_F32_e64 s[2:3], v0, v4, 0, 0, 0, 0 ; D0100002 02020900 V_CMP_GE_F32_e64 s[4:5], v0, v4, 0, 0, 0, 0 ; D00C0004 02020900 S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 V_CNDMASK_B32_e64 v0, v4, v0, s[2:3], 0, 0, 0, 0 ; D2000000 000A0104 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v0, s4, v0 ; 06000004 V_RCP_F32_e32 v0, v0 ; 7E005500 S_BUFFER_LOAD_DWORD s0, s[0:3], 3 ; C2000103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s0, v0 ; 10000000 V_MUL_F32_e32 v1, 1.280000e+02, v0 ; 100200FF 43000000 V_FRACT_F32_e32 v2, v1 ; 7E044101 V_SUB_F32_e32 v1, v1, v2 ; 08020501 V_MUL_F32_e32 v1, 3.906000e-03, v1 ; 100202FF 3B7FFBCE V_FRACT_F32_e32 v1, v1 ; 7E024101 V_MOV_B32_e32 v2, 2.550000e+02 ; 7E0402FF 437F0000 V_MAD_F32 v3, v1, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820003 03C20501 V_FRACT_F32_e32 v4, v3 ; 7E084103 V_SUB_F32_e32 v3, v4, v3 ; 08060704 V_MUL_F32_e32 v4, 5.000000e-01, v0 ; 100800F0 V_FRACT_F32_e32 v5, v4 ; 7E0A4104 V_SUB_F32_e32 v4, v4, v5 ; 08080B04 V_MUL_F32_e32 v4, 3.906000e-03, v4 ; 100808FF 3B7FFBCE V_FRACT_F32_e32 v4, v4 ; 7E084104 V_MAD_F32 v5, v4, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820005 03C20504 V_FRACT_F32_e32 v6, v5 ; 7E0C4105 V_SUB_F32_e32 v5, v5, v6 ; 080A0D05 V_ADD_F32_e32 v5, v5, v5 ; 060A0B05 V_MOV_B32_e32 v6, -7.813000e-03 ; 7E0C02FF BC000219 V_MAD_F32 v3, v3, v6, v5, 0, 0, 0, 0 ; D2820003 04160D03 V_MUL_F32_e32 v5, 3.276800e+04, v0 ; 100A00FF 47000000 V_FRACT_F32_e32 v6, v5 ; 7E0C4105 V_SUB_F32_e32 v5, v5, v6 ; 080A0D05 V_MUL_F32_e32 v5, 3.906000e-03, v5 ; 100A0AFF 3B7FFBCE V_FRACT_F32_e32 v5, v5 ; 7E0A4105 V_MAD_F32 v2, v5, v2, 5.000000e-01, 0, 0, 0, 0 ; D2820002 03C20505 V_FRACT_F32_e32 v6, v2 ; 7E0C4102 V_SUB_F32_e32 v2, v2, v6 ; 08040D02 V_MOV_B32_e32 v6, 3.100000e-05 ; 7E0C02FF 380205FF V_MAD_F32 v2, v2, v6, v3, 0, 0, 0, 0 ; D2820002 040E0D02 V_SUB_F32_e32 v0, v2, v0 ; 08000102 V_MUL_F32_e32 v0, -3.000000e+00, v0 ; 100000FF C0400000 V_CVT_PKRTZ_F16_F32_e32 v0, v5, v0 ; 5E000105 V_CVT_PKRTZ_F16_F32_e32 v1, v4, v1 ; 5E020304 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0..9] DCL TEMP[0..45], LOCAL IMM[0] FLT32 { 255.0000, 0.5000, 2.0000, -1.0000} IMM[1] FLT32 { 2.0000, 0.0078, 0.0000, 0.3333} IMM[2] FLT32 { -2.0000, 1.0000, 0.0145, -69.0000} IMM[3] FLT32 { 50.0000, 161.0000, 48.5004, 635.2987} IMM[4] FLT32 { 10.0000, 0.0000, 123.4560, 0.1571} IMM[5] INT32 {0, 2, 1, 18} IMM[6] FLT32 { 0.1592, 6.2832, -3.1416, 0.0010} IMM[7] FLT32 { -0.0000, -0.9000, -0.9990, 1.8157} IMM[8] FLT32 { 28.5711, 3.6241, 8.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1], TEMP[0] 3: MOV TEMP[2].xy, TEMP[0].xyxx 4: MAD TEMP[3].xyz, TEMP[0].xyzz, IMM[0].xxxx, IMM[0].yyyy 5: FRC TEMP[1].xyz, TEMP[3].xyzz 6: ADD TEMP[3].xyz, TEMP[3].xyzz, -TEMP[1].xyzz 7: MOV TEMP[3].w, TEMP[0].wwww 8: DP4 TEMP[0].x, TEMP[3], IMM[1] 9: MOV TEMP[2].z, TEMP[0].xxxx 10: ADD TEMP[1].x, CONST[8].xxxx, CONST[8].xxxx 11: MAD TEMP[3].xy, TEMP[0].xxxx, CONST[4].zwww, CONST[5].zwww 12: RCP TEMP[0].x, TEMP[0].xxxx 13: MUL TEMP[0].x, TEMP[0].xxxx, CONST[8].xxxx 14: MOV TEMP[3].z, TEMP[0].xxxx 15: RCP TEMP[0].x, TEMP[3].yyyy 16: MUL TEMP[3].x, TEMP[0].xxxx, TEMP[3].xxxx 17: MAD TEMP[0].x, IN[0].xxxx, IMM[0].zzzz, IMM[0].wwww 18: MAD TEMP[4].x, IN[0].yyyy, IMM[2].xxxx, IMM[2].yyyy 19: MUL TEMP[4], TEMP[4].xxxx, CONST[1] 20: MAD TEMP[4], TEMP[0].xxxx, CONST[0], TEMP[4] 21: MAD TEMP[4], TEMP[3].xxxx, CONST[2], TEMP[4] 22: ADD TEMP[4], TEMP[4], CONST[3] 23: RCP TEMP[3].x, TEMP[4].wwww 24: MAD TEMP[0].xyz, TEMP[4].xyzz, TEMP[3].xxxx, CONST[6].xyzz 25: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[9].xxxx 26: FRC TEMP[5].xyz, TEMP[0].xyzz 27: ADD TEMP[0].xyz, TEMP[0].xyzz, -TEMP[5].xyzz 28: MUL TEMP[4].xyz, TEMP[0].xyzz, IMM[2].zzzz 29: FRC TEMP[5].xyz, TEMP[4].xyzz 30: MOV TEMP[6].xyz, TEMP[5].xyzx 31: ADD TEMP[4].xyz, TEMP[4].xyzz, -TEMP[5].xyzz 32: MAD TEMP[0].xyz, TEMP[4].xyzz, IMM[2].wwww, TEMP[0].xyzz 33: ADD TEMP[3].xy, TEMP[0].xyyy, IMM[3].xyyy 34: MUL TEMP[3].xy, TEMP[3].xyyy, TEMP[3].xyyy 35: MUL TEMP[3].x, TEMP[3].yyyy, TEMP[3].xxxx 36: MAD TEMP[0].x, TEMP[0].zzzz, IMM[3].zzzz, IMM[3].wwww 37: RCP TEMP[0].x, TEMP[0].xxxx 38: MUL TEMP[3].x, TEMP[0].xxxx, TEMP[3].xxxx 39: FRC TEMP[0].x, TEMP[3].xxxx 40: MUL TEMP[3].x, TEMP[0].xxxx, IMM[4].xxxx 41: RCP TEMP[0].x, TEMP[1].xxxx 42: MOV TEMP[2].w, TEMP[0].xxxx 43: MOV TEMP[4].w, IMM[4].yyyy 44: MOV TEMP[6].w, IMM[4].yyyy 45: MOV TEMP[3].yw, IMM[4].yyyy 46: MOV TEMP[0].x, IMM[5].xxxx 47: BGNLOOP :0 48: ISGE TEMP[1].x, TEMP[0].xxxx, IMM[5].yyyy 49: UIF TEMP[1].xxxx :0 50: BRK 51: ENDIF 52: MUL TEMP[5].x, TEMP[3].wwww, IMM[4].zzzz 53: MAD TEMP[7].x, TEMP[3].wwww, IMM[4].wwww, TEMP[3].xxxx 54: MAD TEMP[8].x, TEMP[7].xxxx, IMM[6].xxxx, IMM[0].yyyy 55: MOV TEMP[5].y, TEMP[8].xxxx 56: FRC TEMP[9].xy, TEMP[5].xyyy 57: MAD TEMP[10].x, TEMP[9].yyyy, IMM[6].yyyy, IMM[6].zzzz 58: COS TEMP[11].x, TEMP[10].xxxx 59: SIN TEMP[12].x, TEMP[10].xxxx 60: MOV TEMP[11].y, TEMP[12].xxxx 61: ADD TEMP[5].x, TEMP[9].xxxx, IMM[6].wwww 62: MUL TEMP[13].x, TEMP[3].zzzz, TEMP[5].xxxx 63: MAD TEMP[4].xy, TEMP[11].yxyy, -TEMP[13].xxxx, IN[0].xyxx 64: MOV TEMP[14].xy, TEMP[4].xyyy 65: TEX TEMP[15], TEMP[14], SAMP[0], 2D 66: MOV TEMP[16], TEMP[15] 67: MOV TEMP[17].w, TEMP[15].wwww 68: MAD TEMP[4].xyz, TEMP[15].xyzz, IMM[0].xxxx, IMM[0].yyyy 69: FRC TEMP[18].xyz, TEMP[4].xyzz 70: ADD TEMP[17].xyz, TEMP[4].xyzz, -TEMP[18].xyzz 71: DP4 TEMP[4].x, TEMP[17], IMM[1] 72: MAD TEMP[6].xy, TEMP[11].yxyy, TEMP[13].xxxx, IN[0].xyxx 73: MOV TEMP[19].xy, TEMP[6].xyyy 74: TEX TEMP[20], TEMP[19], SAMP[0], 2D 75: MOV TEMP[21], TEMP[20] 76: MOV TEMP[22].w, TEMP[20].wwww 77: MAD TEMP[6].xyz, TEMP[20].xyzz, IMM[0].xxxx, IMM[0].yyyy 78: FRC TEMP[23].xyz, TEMP[6].xyzz 79: MOV TEMP[5].w, TEMP[23].yxyz 80: ADD TEMP[22].xyz, TEMP[6].xyzz, -TEMP[23].xyzz 81: DP4 TEMP[24].x, TEMP[22], IMM[1] 82: MOV TEMP[4].y, TEMP[24].xxxx 83: ADD TEMP[4].xy, TEMP[2].zzzz, -TEMP[4].xyyy 84: MAD_SAT TEMP[25].xy, TEMP[4].xyyy, TEMP[2].wwww, IMM[0].yyyy 85: MOV TEMP[26].xy, TEMP[25].xyxx 86: ADD TEMP[6].xy, TEMP[25].xyyy, IMM[0].wwww 87: FSGE TEMP[27].x, TEMP[6].yyyy, IMM[4].yyyy 88: UIF TEMP[27].xxxx :0 89: MOV TEMP[28].x, IMM[0].wwww 90: ELSE :0 91: MOV TEMP[28].x, IMM[7].xxxx 92: ENDIF 93: FSGE TEMP[29].x, TEMP[6].xxxx, IMM[4].yyyy 94: UIF TEMP[29].xxxx :0 95: MOV TEMP[30].x, TEMP[28].xxxx 96: ELSE :0 97: MOV TEMP[30].x, IMM[7].xxxx 98: ENDIF 99: FSGE TEMP[31].x, TEMP[30].xxxx, IMM[4].yyyy 100: UIF TEMP[31].xxxx :0 101: MOV TEMP[32].xy, TEMP[25].xyxx 102: ELSE :0 103: MOV TEMP[32].xy, IMM[0].yyyy 104: ENDIF 105: ADD TEMP[6].xy, TEMP[32].xyyy, IMM[0].wwww 106: MAD TEMP[6].xy, TEMP[6].xyyy, IMM[4].xxxx, IMM[2].yyyy 107: MAX TEMP[33].xy, TEMP[6].xyyy, IMM[4].yyyy 108: MOV TEMP[5].yz, TEMP[33].yxyy 109: ADD TEMP[34].x, -TEMP[32].yyyy, -TEMP[32].xxxx 110: ADD TEMP[6].xy, -TEMP[33].yxxx, IMM[2].yyyy 111: MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[33].xyyy 112: ADD TEMP[35].x, TEMP[34].xxxx, IMM[2].yyyy 113: MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[35].xxxx, TEMP[32].xyyy 114: MUL TEMP[36].x, TEMP[5].xxxx, TEMP[5].xxxx 115: MAD TEMP[37].x, TEMP[36].xxxx, IMM[7].yyyy, IMM[2].yyyy 116: MOV TEMP[4].z, TEMP[37].xxxx 117: ADD TEMP[4].x, TEMP[4].yyyy, TEMP[4].xxxx 118: MAD TEMP[38].x, TEMP[37].xxxx, TEMP[4].xxxx, TEMP[3].yyyy 119: MOV TEMP[3].y, TEMP[38].xxxx 120: ADD TEMP[39].x, TEMP[3].wwww, IMM[2].yyyy 121: MOV TEMP[3].w, TEMP[39].xxxx 122: UADD TEMP[0].x, TEMP[0].xxxx, IMM[5].zzzz 123: ENDLOOP :0 124: MOV TEMP[0].xy, IN[0].xyyy 125: TEX TEMP[0], TEMP[0], SAMP[1], 2D 126: MOV TEMP[40], TEMP[0] 127: MOV TEMP[4].yzw, TEMP[0] 128: ADD TEMP[0].x, TEMP[0].yyyy, IMM[7].zzzz 129: FSGE TEMP[0].x, TEMP[0].xxxx, IMM[4].yyyy 130: UIF TEMP[0].xxxx :0 131: MOV TEMP[0].x, IMM[4].yyyy 132: ELSE :0 133: MOV TEMP[0].x, IMM[2].yyyy 134: ENDIF 135: ADD TEMP[4].x, -TEMP[3].yyyy, IMM[7].wwww 136: FSGE TEMP[1].x, TEMP[4].xxxx, IMM[4].yyyy 137: UIF TEMP[1].xxxx :0 138: MOV TEMP[1].x, IMM[4].yyyy 139: ELSE :0 140: MOV TEMP[1].x, IMM[2].yyyy 141: ENDIF 142: MOV TEMP[4].x, TEMP[1].xxxx 143: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx 144: MOV TEMP[3].w, TEMP[0].xxxx 145: FSLT TEMP[0].x, -TEMP[0].xxxx, IMM[4].yyyy 146: UIF TEMP[0].xxxx :0 147: MOV TEMP[4].w, IMM[4].yyyy 148: MOV TEMP[6].w, IMM[4].yyyy 149: MOV TEMP[5].x, TEMP[3].yyyy 150: MOV TEMP[5].y, IMM[0].zzzz 151: MOV TEMP[0].x, IMM[5].xxxx 152: BGNLOOP :0 153: ISGE TEMP[1].x, TEMP[0].xxxx, IMM[5].wwww 154: UIF TEMP[1].xxxx :0 155: BRK 156: ENDIF 157: MUL TEMP[7].x, TEMP[5].yyyy, IMM[4].zzzz 158: MAD TEMP[8].x, TEMP[5].yyyy, IMM[4].wwww, TEMP[3].xxxx 159: MAD TEMP[9].x, TEMP[8].xxxx, IMM[6].xxxx, IMM[0].yyyy 160: FRC TEMP[10].x, TEMP[9].xxxx 161: MAD TEMP[11].x, TEMP[10].xxxx, IMM[6].yyyy, IMM[6].zzzz 162: COS TEMP[12].x, TEMP[11].xxxx 163: SIN TEMP[13].x, TEMP[11].xxxx 164: MOV TEMP[12].y, TEMP[13].xxxx 165: FRC TEMP[14].x, TEMP[7].xxxx 166: ADD TEMP[15].x, TEMP[14].xxxx, IMM[6].wwww 167: MUL TEMP[18].x, TEMP[15].xxxx, TEMP[3].zzzz 168: MAD TEMP[4].xy, TEMP[12].yxyy, -TEMP[18].xxxx, IN[0].xyxx 169: MOV TEMP[19].xy, TEMP[4].xyyy 170: TEX TEMP[20], TEMP[19], SAMP[0], 2D 171: MOV TEMP[41], TEMP[20] 172: MOV TEMP[17].w, TEMP[20].wwww 173: MAD TEMP[4].xyz, TEMP[20].xyzz, IMM[0].xxxx, IMM[0].yyyy 174: FRC TEMP[23].xyz, TEMP[4].xyzz 175: ADD TEMP[17].xyz, TEMP[4].xyzz, -TEMP[23].xyzz 176: DP4 TEMP[4].x, TEMP[17], IMM[1] 177: MAD TEMP[6].xy, TEMP[12].yxyy, TEMP[18].xxxx, IN[0].xyxx 178: MOV TEMP[24].xy, TEMP[6].xyyy 179: TEX TEMP[25], TEMP[24], SAMP[0], 2D 180: MOV TEMP[42], TEMP[25] 181: MOV TEMP[22].w, TEMP[25].wwww 182: MAD TEMP[6].xyz, TEMP[25].xyzz, IMM[0].xxxx, IMM[0].yyyy 183: FRC TEMP[27].xyz, TEMP[6].xyzz 184: MOV TEMP[17].xyz, TEMP[27].xyzx 185: ADD TEMP[22].xyz, TEMP[6].xyzz, -TEMP[27].xyzz 186: DP4 TEMP[28].x, TEMP[22], IMM[1] 187: MOV TEMP[4].y, TEMP[28].xxxx 188: ADD TEMP[4].xy, TEMP[2].zzzz, -TEMP[4].xyyy 189: MAD_SAT TEMP[29].xy, TEMP[4].xyyy, TEMP[2].wwww, IMM[0].yyyy 190: MOV TEMP[43].xy, TEMP[29].xyxx 191: ADD TEMP[6].xy, TEMP[29].xyyy, IMM[0].wwww 192: FSGE TEMP[30].x, TEMP[6].yyyy, IMM[4].yyyy 193: UIF TEMP[30].xxxx :0 194: MOV TEMP[31].x, IMM[0].wwww 195: ELSE :0 196: MOV TEMP[31].x, IMM[7].xxxx 197: ENDIF 198: FSGE TEMP[32].x, TEMP[6].xxxx, IMM[4].yyyy 199: UIF TEMP[32].xxxx :0 200: MOV TEMP[33].x, TEMP[31].xxxx 201: ELSE :0 202: MOV TEMP[33].x, IMM[7].xxxx 203: ENDIF 204: FSGE TEMP[34].x, TEMP[33].xxxx, IMM[4].yyyy 205: UIF TEMP[34].xxxx :0 206: MOV TEMP[35].xy, TEMP[29].xyxx 207: ELSE :0 208: MOV TEMP[35].xy, IMM[0].yyyy 209: ENDIF 210: ADD TEMP[6].xy, TEMP[35].xyyy, IMM[0].wwww 211: MAD TEMP[6].xy, TEMP[6].xyyy, IMM[4].xxxx, IMM[2].yyyy 212: MAX TEMP[36].xy, TEMP[6].xyyy, IMM[4].yyyy 213: MOV TEMP[5].zw, TEMP[36].yyxy 214: ADD TEMP[37].x, -TEMP[35].yyyy, -TEMP[35].xxxx 215: ADD TEMP[6].xy, -TEMP[36].yxxx, IMM[2].yyyy 216: MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[36].xyyy 217: ADD TEMP[38].x, TEMP[37].xxxx, IMM[2].yyyy 218: MOV TEMP[4].z, TEMP[38].xxxx 219: MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[38].xxxx, TEMP[35].xyyy 220: MUL TEMP[39].x, TEMP[15].xxxx, TEMP[15].xxxx 221: MAD TEMP[44].x, TEMP[39].xxxx, IMM[7].yyyy, IMM[2].yyyy 222: MOV TEMP[3].w, TEMP[44].xxxx 223: ADD TEMP[4].x, TEMP[4].yyyy, TEMP[4].xxxx 224: MAD TEMP[5].x, TEMP[44].xxxx, TEMP[4].xxxx, TEMP[5].xxxx 225: ADD TEMP[45].x, TEMP[5].yyyy, IMM[2].yyyy 226: MOV TEMP[5].y, TEMP[45].xxxx 227: UADD TEMP[0].x, TEMP[0].xxxx, IMM[5].zzzz 228: ENDLOOP :0 229: MOV TEMP[3].y, TEMP[5].xxxx 230: MOV TEMP[2].z, IMM[8].xxxx 231: ELSE :0 232: MOV TEMP[2].z, IMM[8].yyyy 233: ENDIF 234: RCP TEMP[0].x, TEMP[2].zzzz 235: MAD TEMP[0].x, TEMP[3].yyyy, -TEMP[0].xxxx, IMM[2].yyyy 236: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx 237: MUL TEMP[1].x, IMM[8].zzzz, CONST[7].xxxx 238: ABS TEMP[0].x, TEMP[0].xxxx 239: POW TEMP[3].x, TEMP[0].xxxx, TEMP[1].xxxx 240: MOV_SAT TEMP[0].xy, TEMP[3].xxxx 241: MOV TEMP[0].zw, TEMP[2].yyxy 242: MOV OUT[0], TEMP[0] 243: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 24) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 28) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %34 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40) %35 = call float @llvm.SI.load.const(<16 x i8> %23, i32 44) %36 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %37 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %38 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %39 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60) %40 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %41 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76) %42 = call float @llvm.SI.load.const(<16 x i8> %23, i32 88) %43 = call float @llvm.SI.load.const(<16 x i8> %23, i32 92) %44 = call float @llvm.SI.load.const(<16 x i8> %23, i32 96) %45 = call float @llvm.SI.load.const(<16 x i8> %23, i32 100) %46 = call float @llvm.SI.load.const(<16 x i8> %23, i32 104) %47 = call float @llvm.SI.load.const(<16 x i8> %23, i32 112) %48 = call float @llvm.SI.load.const(<16 x i8> %23, i32 128) %49 = call float @llvm.SI.load.const(<16 x i8> %23, i32 144) %50 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0 %51 = load <8 x i32> addrspace(2)* %50, !tbaa !0 %52 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0 %53 = load <4 x i32> addrspace(2)* %52, !tbaa !0 %54 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 1 %55 = load <8 x i32> addrspace(2)* %54, !tbaa !0 %56 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 1 %57 = load <4 x i32> addrspace(2)* %56, !tbaa !0 %58 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %59 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %60 = bitcast float %58 to i32 %61 = bitcast float %59 to i32 %62 = insertelement <2 x i32> undef, i32 %60, i32 0 %63 = insertelement <2 x i32> %62, i32 %61, i32 1 %64 = bitcast <8 x i32> %51 to <32 x i8> %65 = bitcast <4 x i32> %53 to <16 x i8> %66 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %63, <32 x i8> %64, <16 x i8> %65, i32 2) %67 = extractelement <4 x float> %66, i32 0 %68 = extractelement <4 x float> %66, i32 1 %69 = extractelement <4 x float> %66, i32 2 %70 = extractelement <4 x float> %66, i32 3 %71 = fmul float %67, 2.550000e+02 %72 = fadd float %71, 5.000000e-01 %73 = fmul float %68, 2.550000e+02 %74 = fadd float %73, 5.000000e-01 %75 = fmul float %69, 2.550000e+02 %76 = fadd float %75, 5.000000e-01 %77 = call float @llvm.AMDIL.fraction.(float %72) %78 = call float @llvm.AMDIL.fraction.(float %74) %79 = call float @llvm.AMDIL.fraction.(float %76) %80 = fsub float -0.000000e+00, %77 %81 = fadd float %72, %80 %82 = fsub float -0.000000e+00, %78 %83 = fadd float %74, %82 %84 = fsub float -0.000000e+00, %79 %85 = fadd float %76, %84 %86 = fmul float %81, 2.000000e+00 %87 = fmul float %83, 0x3F80004320000000 %88 = fadd float %86, %87 %89 = fmul float %85, 0x3F0040BFE0000000 %90 = fadd float %88, %89 %91 = fmul float %70, 0x3FD55553E0000000 %92 = fadd float %90, %91 %93 = fadd float %48, %48 %94 = fmul float %92, %40 %95 = fadd float %94, %42 %96 = fmul float %92, %41 %97 = fadd float %96, %43 %98 = fdiv float 1.000000e+00, %92 %99 = fmul float %98, %48 %100 = fdiv float 1.000000e+00, %97 %101 = fmul float %100, %95 %102 = fmul float %58, 2.000000e+00 %103 = fadd float %102, -1.000000e+00 %104 = fmul float %59, -2.000000e+00 %105 = fadd float %104, 1.000000e+00 %106 = fmul float %105, %28 %107 = fmul float %105, %29 %108 = fmul float %105, %30 %109 = fmul float %105, %31 %110 = fmul float %103, %24 %111 = fadd float %110, %106 %112 = fmul float %103, %25 %113 = fadd float %112, %107 %114 = fmul float %103, %26 %115 = fadd float %114, %108 %116 = fmul float %103, %27 %117 = fadd float %116, %109 %118 = fmul float %101, %32 %119 = fadd float %118, %111 %120 = fmul float %101, %33 %121 = fadd float %120, %113 %122 = fmul float %101, %34 %123 = fadd float %122, %115 %124 = fmul float %101, %35 %125 = fadd float %124, %117 %126 = fadd float %119, %36 %127 = fadd float %121, %37 %128 = fadd float %123, %38 %129 = fadd float %125, %39 %130 = fdiv float 1.000000e+00, %129 %131 = fmul float %126, %130 %132 = fadd float %131, %44 %133 = fmul float %127, %130 %134 = fadd float %133, %45 %135 = fmul float %128, %130 %136 = fadd float %135, %46 %137 = fmul float %132, %49 %138 = fmul float %134, %49 %139 = fmul float %136, %49 %140 = call float @llvm.AMDIL.fraction.(float %137) %141 = call float @llvm.AMDIL.fraction.(float %138) %142 = call float @llvm.AMDIL.fraction.(float %139) %143 = fsub float -0.000000e+00, %140 %144 = fadd float %137, %143 %145 = fsub float -0.000000e+00, %141 %146 = fadd float %138, %145 %147 = fsub float -0.000000e+00, %142 %148 = fadd float %139, %147 %149 = fmul float %144, 0x3F8DAE8180000000 %150 = fmul float %146, 0x3F8DAE8180000000 %151 = fmul float %148, 0x3F8DAE8180000000 %152 = call float @llvm.AMDIL.fraction.(float %149) %153 = call float @llvm.AMDIL.fraction.(float %150) %154 = call float @llvm.AMDIL.fraction.(float %151) %155 = fsub float -0.000000e+00, %152 %156 = fadd float %149, %155 %157 = fsub float -0.000000e+00, %153 %158 = fadd float %150, %157 %159 = fsub float -0.000000e+00, %154 %160 = fadd float %151, %159 %161 = fmul float %156, -6.900000e+01 %162 = fadd float %161, %144 %163 = fmul float %158, -6.900000e+01 %164 = fadd float %163, %146 %165 = fmul float %160, -6.900000e+01 %166 = fadd float %165, %148 %167 = fadd float %162, 5.000000e+01 %168 = fadd float %164, 1.610000e+02 %169 = fmul float %167, %167 %170 = fmul float %168, %168 %171 = fmul float %170, %169 %172 = fmul float %166, 0x4048400CC0000000 %173 = fadd float %172, 0x4083DA63C0000000 %174 = fdiv float 1.000000e+00, %173 %175 = fmul float %174, %171 %176 = call float @llvm.AMDIL.fraction.(float %175) %177 = fmul float %176, 1.000000e+01 %178 = fdiv float 1.000000e+00, %93 %179 = bitcast <8 x i32> %51 to <32 x i8> %180 = bitcast <4 x i32> %53 to <16 x i8> %181 = bitcast <8 x i32> %51 to <32 x i8> %182 = bitcast <4 x i32> %53 to <16 x i8> br label %LOOP LOOP: ; preds = %ENDIF, %main_body %temp15.0 = phi float [ 0.000000e+00, %main_body ], [ %359, %ENDIF ] %temp13.0 = phi float [ 0.000000e+00, %main_body ], [ %358, %ENDIF ] %temp.0 = phi float [ 0.000000e+00, %main_body ], [ %362, %ENDIF ] %183 = bitcast float %temp.0 to i32 %184 = icmp sge i32 %183, 2 %185 = sext i1 %184 to i32 %186 = bitcast i32 %185 to float %187 = bitcast float %186 to i32 %188 = icmp ne i32 %187, 0 br i1 %188, label %IF, label %ENDIF IF: ; preds = %LOOP %189 = bitcast float %58 to i32 %190 = bitcast float %59 to i32 %191 = insertelement <2 x i32> undef, i32 %189, i32 0 %192 = insertelement <2 x i32> %191, i32 %190, i32 1 %193 = bitcast <8 x i32> %55 to <32 x i8> %194 = bitcast <4 x i32> %57 to <16 x i8> %195 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %192, <32 x i8> %193, <16 x i8> %194, i32 2) %196 = extractelement <4 x float> %195, i32 1 %197 = fadd float %196, 0xBFEFF7CEE0000000 %198 = fcmp oge float %197, 0.000000e+00 %199 = sext i1 %198 to i32 %200 = bitcast i32 %199 to float %201 = bitcast float %200 to i32 %202 = icmp ne i32 %201, 0 %. = select i1 %202, float 0.000000e+00, float 1.000000e+00 %203 = fsub float -0.000000e+00, %temp13.0 %204 = fadd float %203, 0x3FFD0CEF60000000 %205 = fcmp oge float %204, 0.000000e+00 %206 = sext i1 %205 to i32 %207 = bitcast i32 %206 to float %208 = bitcast float %207 to i32 %209 = icmp ne i32 %208, 0 %temp4.0 = select i1 %209, float 0.000000e+00, float 1.000000e+00 %210 = fadd float %., %temp4.0 %211 = fsub float -0.000000e+00, %210 %212 = fcmp olt float %211, 0.000000e+00 %213 = sext i1 %212 to i32 %214 = bitcast i32 %213 to float %215 = bitcast float %214 to i32 %216 = icmp ne i32 %215, 0 br i1 %216, label %IF200, label %ENDIF199 ENDIF: ; preds = %LOOP %217 = fmul float %temp15.0, 0x405EDD2F20000000 %218 = fmul float %temp15.0, 0x3FC41B3280000000 %219 = fadd float %218, %177 %220 = fmul float %219, 0x3FC45F30E0000000 %221 = fadd float %220, 5.000000e-01 %222 = call float @llvm.AMDIL.fraction.(float %217) %223 = call float @llvm.AMDIL.fraction.(float %221) %224 = fmul float %223, 0x401921FB40000000 %225 = fadd float %224, 0xC00921FB80000000 %226 = call float @llvm.cos.f32(float %225) %227 = call float @llvm.sin.f32(float %225) %228 = fadd float %222, 0x3F50624DE0000000 %229 = fmul float %99, %228 %230 = fsub float -0.000000e+00, %229 %231 = fmul float %227, %230 %232 = fadd float %231, %58 %233 = fsub float -0.000000e+00, %229 %234 = fmul float %226, %233 %235 = fadd float %234, %59 %236 = bitcast float %232 to i32 %237 = bitcast float %235 to i32 %238 = insertelement <2 x i32> undef, i32 %236, i32 0 %239 = insertelement <2 x i32> %238, i32 %237, i32 1 %240 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %239, <32 x i8> %179, <16 x i8> %180, i32 2) %241 = extractelement <4 x float> %240, i32 0 %242 = extractelement <4 x float> %240, i32 1 %243 = extractelement <4 x float> %240, i32 2 %244 = extractelement <4 x float> %240, i32 3 %245 = fmul float %241, 2.550000e+02 %246 = fadd float %245, 5.000000e-01 %247 = fmul float %242, 2.550000e+02 %248 = fadd float %247, 5.000000e-01 %249 = fmul float %243, 2.550000e+02 %250 = fadd float %249, 5.000000e-01 %251 = call float @llvm.AMDIL.fraction.(float %246) %252 = call float @llvm.AMDIL.fraction.(float %248) %253 = call float @llvm.AMDIL.fraction.(float %250) %254 = fsub float -0.000000e+00, %251 %255 = fadd float %246, %254 %256 = fsub float -0.000000e+00, %252 %257 = fadd float %248, %256 %258 = fsub float -0.000000e+00, %253 %259 = fadd float %250, %258 %260 = fmul float %255, 2.000000e+00 %261 = fmul float %257, 0x3F80004320000000 %262 = fadd float %260, %261 %263 = fmul float %259, 0x3F0040BFE0000000 %264 = fadd float %262, %263 %265 = fmul float %244, 0x3FD55553E0000000 %266 = fadd float %264, %265 %267 = fmul float %227, %229 %268 = fadd float %267, %58 %269 = fmul float %226, %229 %270 = fadd float %269, %59 %271 = bitcast float %268 to i32 %272 = bitcast float %270 to i32 %273 = insertelement <2 x i32> undef, i32 %271, i32 0 %274 = insertelement <2 x i32> %273, i32 %272, i32 1 %275 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %274, <32 x i8> %181, <16 x i8> %182, i32 2) %276 = extractelement <4 x float> %275, i32 0 %277 = extractelement <4 x float> %275, i32 1 %278 = extractelement <4 x float> %275, i32 2 %279 = extractelement <4 x float> %275, i32 3 %280 = fmul float %276, 2.550000e+02 %281 = fadd float %280, 5.000000e-01 %282 = fmul float %277, 2.550000e+02 %283 = fadd float %282, 5.000000e-01 %284 = fmul float %278, 2.550000e+02 %285 = fadd float %284, 5.000000e-01 %286 = call float @llvm.AMDIL.fraction.(float %281) %287 = call float @llvm.AMDIL.fraction.(float %283) %288 = call float @llvm.AMDIL.fraction.(float %285) %289 = fsub float -0.000000e+00, %286 %290 = fadd float %281, %289 %291 = fsub float -0.000000e+00, %287 %292 = fadd float %283, %291 %293 = fsub float -0.000000e+00, %288 %294 = fadd float %285, %293 %295 = fmul float %290, 2.000000e+00 %296 = fmul float %292, 0x3F80004320000000 %297 = fadd float %295, %296 %298 = fmul float %294, 0x3F0040BFE0000000 %299 = fadd float %297, %298 %300 = fmul float %279, 0x3FD55553E0000000 %301 = fadd float %299, %300 %302 = fsub float -0.000000e+00, %266 %303 = fadd float %92, %302 %304 = fsub float -0.000000e+00, %301 %305 = fadd float %92, %304 %306 = fmul float %303, %178 %307 = fadd float %306, 5.000000e-01 %308 = fmul float %305, %178 %309 = fadd float %308, 5.000000e-01 %310 = call float @llvm.AMDIL.clamp.(float %307, float 0.000000e+00, float 1.000000e+00) %311 = call float @llvm.AMDIL.clamp.(float %309, float 0.000000e+00, float 1.000000e+00) %312 = fadd float %310, -1.000000e+00 %313 = fadd float %311, -1.000000e+00 %314 = fcmp oge float %313, 0.000000e+00 %315 = sext i1 %314 to i32 %316 = bitcast i32 %315 to float %317 = bitcast float %316 to i32 %318 = icmp ne i32 %317, 0 %.216 = select i1 %318, float -1.000000e+00, float -0.000000e+00 %319 = fcmp oge float %312, 0.000000e+00 %320 = sext i1 %319 to i32 %321 = bitcast i32 %320 to float %322 = bitcast float %321 to i32 %323 = icmp ne i32 %322, 0 %temp120.0 = select i1 %323, float %.216, float -0.000000e+00 %324 = fcmp oge float %temp120.0, 0.000000e+00 %325 = sext i1 %324 to i32 %326 = bitcast i32 %325 to float %327 = bitcast float %326 to i32 %328 = icmp ne i32 %327, 0 %.217 = select i1 %328, float %310, float 5.000000e-01 %.218 = select i1 %328, float %311, float 5.000000e-01 %329 = fadd float %.217, -1.000000e+00 %330 = fadd float %.218, -1.000000e+00 %331 = fmul float %329, 1.000000e+01 %332 = fadd float %331, 1.000000e+00 %333 = fmul float %330, 1.000000e+01 %334 = fadd float %333, 1.000000e+00 %335 = fcmp uge float %332, 0.000000e+00 %336 = select i1 %335, float %332, float 0.000000e+00 %337 = fcmp uge float %334, 0.000000e+00 %338 = select i1 %337, float %334, float 0.000000e+00 %339 = fsub float -0.000000e+00, %.218 %340 = fsub float -0.000000e+00, %.217 %341 = fadd float %339, %340 %342 = fsub float -0.000000e+00, %338 %343 = fadd float %342, 1.000000e+00 %344 = fsub float -0.000000e+00, %336 %345 = fadd float %344, 1.000000e+00 %346 = fmul float %343, %336 %347 = fmul float %345, %338 %348 = fadd float %341, 1.000000e+00 %349 = fmul float %346, %348 %350 = fadd float %349, %.217 %351 = fmul float %347, %348 %352 = fadd float %351, %.218 %353 = fmul float %228, %228 %354 = fmul float %353, 0xBFECCCCCC0000000 %355 = fadd float %354, 1.000000e+00 %356 = fadd float %352, %350 %357 = fmul float %355, %356 %358 = fadd float %357, %temp13.0 %359 = fadd float %temp15.0, 1.000000e+00 %360 = bitcast float %temp.0 to i32 %361 = add i32 %360, 1 %362 = bitcast i32 %361 to float br label %LOOP IF200: ; preds = %IF %363 = bitcast <8 x i32> %51 to <32 x i8> %364 = bitcast <4 x i32> %53 to <16 x i8> %365 = bitcast <8 x i32> %51 to <32 x i8> %366 = bitcast <4 x i32> %53 to <16 x i8> br label %LOOP203 ENDIF199: ; preds = %LOOP203, %IF %temp13.1 = phi float [ %temp13.0, %IF ], [ %temp20.0, %LOOP203 ] %temp10.0 = phi float [ 0x400CFE1760000000, %IF ], [ 0x403C9234E0000000, %LOOP203 ] %367 = fdiv float 1.000000e+00, %temp10.0 %368 = fsub float -0.000000e+00, %367 %369 = fmul float %temp13.1, %368 %370 = fadd float %369, 1.000000e+00 %371 = fadd float %370, %370 %372 = fmul float 8.000000e+00, %47 %373 = call float @fabs(float %371) %374 = call float @llvm.pow.f32(float %373, float %372) %375 = call float @llvm.AMDIL.clamp.(float %374, float 0.000000e+00, float 1.000000e+00) %376 = call float @llvm.AMDIL.clamp.(float %374, float 0.000000e+00, float 1.000000e+00) %377 = call i32 @llvm.SI.packf16(float %375, float %376) %378 = bitcast i32 %377 to float %379 = call i32 @llvm.SI.packf16(float %67, float %68) %380 = bitcast i32 %379 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %378, float %380, float %378, float %380) ret void LOOP203: ; preds = %ENDIF204, %IF200 %temp21.0 = phi float [ 2.000000e+00, %IF200 ], [ %529, %ENDIF204 ] %temp20.0 = phi float [ %temp13.0, %IF200 ], [ %528, %ENDIF204 ] %temp.2 = phi float [ 0.000000e+00, %IF200 ], [ %532, %ENDIF204 ] %381 = bitcast float %temp.2 to i32 %382 = icmp sge i32 %381, 18 %383 = sext i1 %382 to i32 %384 = bitcast i32 %383 to float %385 = bitcast float %384 to i32 %386 = icmp ne i32 %385, 0 br i1 %386, label %ENDIF199, label %ENDIF204 ENDIF204: ; preds = %LOOP203 %387 = fmul float %temp21.0, 0x405EDD2F20000000 %388 = fmul float %temp21.0, 0x3FC41B3280000000 %389 = fadd float %388, %177 %390 = fmul float %389, 0x3FC45F30E0000000 %391 = fadd float %390, 5.000000e-01 %392 = call float @llvm.AMDIL.fraction.(float %391) %393 = fmul float %392, 0x401921FB40000000 %394 = fadd float %393, 0xC00921FB80000000 %395 = call float @llvm.cos.f32(float %394) %396 = call float @llvm.sin.f32(float %394) %397 = call float @llvm.AMDIL.fraction.(float %387) %398 = fadd float %397, 0x3F50624DE0000000 %399 = fmul float %398, %99 %400 = fsub float -0.000000e+00, %399 %401 = fmul float %396, %400 %402 = fadd float %401, %58 %403 = fsub float -0.000000e+00, %399 %404 = fmul float %395, %403 %405 = fadd float %404, %59 %406 = bitcast float %402 to i32 %407 = bitcast float %405 to i32 %408 = insertelement <2 x i32> undef, i32 %406, i32 0 %409 = insertelement <2 x i32> %408, i32 %407, i32 1 %410 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %409, <32 x i8> %363, <16 x i8> %364, i32 2) %411 = extractelement <4 x float> %410, i32 0 %412 = extractelement <4 x float> %410, i32 1 %413 = extractelement <4 x float> %410, i32 2 %414 = extractelement <4 x float> %410, i32 3 %415 = fmul float %411, 2.550000e+02 %416 = fadd float %415, 5.000000e-01 %417 = fmul float %412, 2.550000e+02 %418 = fadd float %417, 5.000000e-01 %419 = fmul float %413, 2.550000e+02 %420 = fadd float %419, 5.000000e-01 %421 = call float @llvm.AMDIL.fraction.(float %416) %422 = call float @llvm.AMDIL.fraction.(float %418) %423 = call float @llvm.AMDIL.fraction.(float %420) %424 = fsub float -0.000000e+00, %421 %425 = fadd float %416, %424 %426 = fsub float -0.000000e+00, %422 %427 = fadd float %418, %426 %428 = fsub float -0.000000e+00, %423 %429 = fadd float %420, %428 %430 = fmul float %425, 2.000000e+00 %431 = fmul float %427, 0x3F80004320000000 %432 = fadd float %430, %431 %433 = fmul float %429, 0x3F0040BFE0000000 %434 = fadd float %432, %433 %435 = fmul float %414, 0x3FD55553E0000000 %436 = fadd float %434, %435 %437 = fmul float %396, %399 %438 = fadd float %437, %58 %439 = fmul float %395, %399 %440 = fadd float %439, %59 %441 = bitcast float %438 to i32 %442 = bitcast float %440 to i32 %443 = insertelement <2 x i32> undef, i32 %441, i32 0 %444 = insertelement <2 x i32> %443, i32 %442, i32 1 %445 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %444, <32 x i8> %365, <16 x i8> %366, i32 2) %446 = extractelement <4 x float> %445, i32 0 %447 = extractelement <4 x float> %445, i32 1 %448 = extractelement <4 x float> %445, i32 2 %449 = extractelement <4 x float> %445, i32 3 %450 = fmul float %446, 2.550000e+02 %451 = fadd float %450, 5.000000e-01 %452 = fmul float %447, 2.550000e+02 %453 = fadd float %452, 5.000000e-01 %454 = fmul float %448, 2.550000e+02 %455 = fadd float %454, 5.000000e-01 %456 = call float @llvm.AMDIL.fraction.(float %451) %457 = call float @llvm.AMDIL.fraction.(float %453) %458 = call float @llvm.AMDIL.fraction.(float %455) %459 = fsub float -0.000000e+00, %456 %460 = fadd float %451, %459 %461 = fsub float -0.000000e+00, %457 %462 = fadd float %453, %461 %463 = fsub float -0.000000e+00, %458 %464 = fadd float %455, %463 %465 = fmul float %460, 2.000000e+00 %466 = fmul float %462, 0x3F80004320000000 %467 = fadd float %465, %466 %468 = fmul float %464, 0x3F0040BFE0000000 %469 = fadd float %467, %468 %470 = fmul float %449, 0x3FD55553E0000000 %471 = fadd float %469, %470 %472 = fsub float -0.000000e+00, %436 %473 = fadd float %92, %472 %474 = fsub float -0.000000e+00, %471 %475 = fadd float %92, %474 %476 = fmul float %473, %178 %477 = fadd float %476, 5.000000e-01 %478 = fmul float %475, %178 %479 = fadd float %478, 5.000000e-01 %480 = call float @llvm.AMDIL.clamp.(float %477, float 0.000000e+00, float 1.000000e+00) %481 = call float @llvm.AMDIL.clamp.(float %479, float 0.000000e+00, float 1.000000e+00) %482 = fadd float %480, -1.000000e+00 %483 = fadd float %481, -1.000000e+00 %484 = fcmp oge float %483, 0.000000e+00 %485 = sext i1 %484 to i32 %486 = bitcast i32 %485 to float %487 = bitcast float %486 to i32 %488 = icmp ne i32 %487, 0 %.219 = select i1 %488, float -1.000000e+00, float -0.000000e+00 %489 = fcmp oge float %482, 0.000000e+00 %490 = sext i1 %489 to i32 %491 = bitcast i32 %490 to float %492 = bitcast float %491 to i32 %493 = icmp ne i32 %492, 0 %temp132.0 = select i1 %493, float %.219, float -0.000000e+00 %494 = fcmp oge float %temp132.0, 0.000000e+00 %495 = sext i1 %494 to i32 %496 = bitcast i32 %495 to float %497 = bitcast float %496 to i32 %498 = icmp ne i32 %497, 0 %.220 = select i1 %498, float %480, float 5.000000e-01 %.221 = select i1 %498, float %481, float 5.000000e-01 %499 = fadd float %.220, -1.000000e+00 %500 = fadd float %.221, -1.000000e+00 %501 = fmul float %499, 1.000000e+01 %502 = fadd float %501, 1.000000e+00 %503 = fmul float %500, 1.000000e+01 %504 = fadd float %503, 1.000000e+00 %505 = fcmp uge float %502, 0.000000e+00 %506 = select i1 %505, float %502, float 0.000000e+00 %507 = fcmp uge float %504, 0.000000e+00 %508 = select i1 %507, float %504, float 0.000000e+00 %509 = fsub float -0.000000e+00, %.221 %510 = fsub float -0.000000e+00, %.220 %511 = fadd float %509, %510 %512 = fsub float -0.000000e+00, %508 %513 = fadd float %512, 1.000000e+00 %514 = fsub float -0.000000e+00, %506 %515 = fadd float %514, 1.000000e+00 %516 = fmul float %513, %506 %517 = fmul float %515, %508 %518 = fadd float %511, 1.000000e+00 %519 = fmul float %516, %518 %520 = fadd float %519, %.220 %521 = fmul float %517, %518 %522 = fadd float %521, %.221 %523 = fmul float %398, %398 %524 = fmul float %523, 0xBFECCCCCC0000000 %525 = fadd float %524, 1.000000e+00 %526 = fadd float %522, %520 %527 = fmul float %525, %526 %528 = fadd float %527, %temp20.0 %529 = fadd float %temp21.0, 1.000000e+00 %530 = bitcast float %temp.2 to i32 %531 = add i32 %530, 1 %532 = bitcast i32 %531 to float br label %LOOP203 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 ; Function Attrs: nounwind readonly declare float @llvm.sin.f32(float) #3 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readonly declare float @fabs(float) #4 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } attributes #4 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} LLVM ERROR: Cannot select: 0xdf42a85c: i32 = truncate 0xdf4187c0 [ORD=47] [ID=184] 0xdf4187c0: i128 = srl 0xdf41d1a4, 0xdf41d230 [ORD=47] [ID=164] 0xdf41d1a4: i128 = bitcast 0xdf41bc84 [ORD=47] [ID=150] 0xdf41bc84: v4i32,ch = load 0xdf9556bc, 0xdf418504, 0xdf418f68 [ORD=34] [ID=119] 0xdf418504: i64,ch = CopyFromReg 0xdf9556bc, 0xdf418478 [ID=110] 0xdf418478: i64 = Register %vreg111 [ID=2] 0xdf418f68: i64 = undef [ID=8] 0xdf41d230: i32 = Constant<64> [ID=107] In function: main ERROR: Passed a NULL mutex ERROR: Passed a NULL mutex