From 4701fad4e66d65ee2f544e8aeafdc0d53a168aa9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 14 Nov 2014 11:02:41 +0000 Subject: [PATCH] drm/i915: Force a CS stall inside gen7 invalidate-caches We use the invalidate-caches flush prior to doing a context switch and so we rely on it being a command barrier. Frob the CS_STALL bit inside the invalidate to make it a full barier before the context switch. In the requests branch that started the hunt, this done as an explicit engine->flush(COMMAND_BARRIER) before the MI_SET_CONTEXT. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83677 Signed-off-by: Chris Wilson Cc: stable@vger.kernel.org --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ae09258..dbe99fa 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -368,6 +368,13 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + /* + * We are also used as barrier before a MI_SET_CONTEXT. + * Make sure we do a fall pipeline stall before the implied + * LRI of render state. + */ + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; + /* Workaround: we must issue a pipe_control with CS-stall bit * set before a pipe_control command that has the state cache * invalidate bit set. */ -- 1.9.1