From 9c6622f384c2e4b1f661ff9a4947855a1ed79b2f Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 18 Nov 2014 13:37:32 -0800
Subject: [PATCH] R600/SI: Don't use fmin_legacy / fmax_legacy with unordered
 compares

---
 lib/Target/R600/AMDGPUISelLowering.cpp | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 2f95b74..e532b8f 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -1028,6 +1028,9 @@ SDValue AMDGPUTargetLowering::CombineFMinMax(SDLoc DL,
     break;
   case ISD::SETULE:
   case ISD::SETULT:
+  case ISD::SETUGE:
+  case ISD::SETUGT:
+    llvm_unreachable("Only ordered comparisons expected");
   case ISD::SETOLE:
   case ISD::SETOLT:
   case ISD::SETLE:
@@ -1041,9 +1044,7 @@ SDValue AMDGPUTargetLowering::CombineFMinMax(SDLoc DL,
   }
   case ISD::SETGT:
   case ISD::SETGE:
-  case ISD::SETUGE:
   case ISD::SETOGE:
-  case ISD::SETUGT:
   case ISD::SETOGT: {
     if (LHS == True)
       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
@@ -2235,6 +2236,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
     SDLoc DL(N);
     EVT VT = N->getValueType(0);
 
+    if (!DCI.isAfterLegalizeVectorOps())
+      break;
+
     if (VT == MVT::f32 ||
         (VT == MVT::f64 &&
          Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
@@ -2250,6 +2254,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
     break;
   }
   case ISD::SELECT: {
+    if (!DCI.isAfterLegalizeVectorOps())
+      break;
+
     SDValue Cond = N->getOperand(0);
     if (Cond.getOpcode() == ISD::SETCC) {
       SDLoc DL(N);
-- 
2.1.2