From d0d306811cc8982c8b810dff7e865b202e849aa7 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Sat, 3 Jan 2015 12:22:47 -0800 Subject: [PATCH 3/3] TEST drm/i915: pedantic scoreboarding Scoreboard flush sequence will be done even when scoreboard cover block size changes (due to dispatch mode, etc) while PSD is idle. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 22979b9..d498361 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6149,6 +6149,7 @@ enum punit_power_well { #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 #define GEN7_MAX_PS_THREAD_DEP (8<<12) +#define GEN7_SCOREBOARD_PEDANT (1<<11) #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) #define GEN7_PSD_WAIT_FOR_SBE (1<<4) #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9fa0ad4..072876c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5997,6 +5997,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, _MASKED_BIT_ENABLE(GEN7_PSD_WAIT_FOR_SBE)); + /* Pedantic scoreboarding */ + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, + _MASKED_BIT_ENABLE(GEN7_SCOREBOARD_PEDANT)); + lpt_init_clock_gating(dev); } -- 2.2.1