From 2da56891a2166821c1f87a0b146b2326fe51caee Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Sun, 4 Jan 2015 15:57:59 -0800 Subject: [PATCH] i965/hsw: Implement end of batch workaround Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 2bd11d7..ce7051f 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -224,6 +224,21 @@ brw_finish_batch(struct brw_context *brw) if (brw->batch.ring == RENDER_RING) brw_perf_monitor_finish_batch(brw); + if (brw->is_haswell) { + /* SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every + * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall. + * + * From the example in the docs, it seems to expect a regular pipe control + * flush here as well. We may have done it already, but meh. + */ + brw_emit_pipe_control_flush(brw, 1 << 7); + BEGIN_BATCH(2); + OUT_BATCH(0x780e << 16 | (2 - 2)); + OUT_BATCH(brw->cc.state_offset | 1); + ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(brw); + } + /* Mark that the current program cache BO has been used by the GPU. * It will be reallocated if we need to put new programs in for the * next batch. -- 2.2.1