X.Org X Server 1.16.99.901 (1.17.0 RC 1) Release Date: 2014-10-28 X Protocol Version 11, Revision 0 Build Operating System: Linux 3.18.1 x86_64 Debian Current Operating System: Linux dhcppc0 3.19.0 #1 SMP Mon Feb 9 05:39:38 CET 2015 x86_64 Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.19.0 root=UUID=d98de994-1aa7-401c-8357-b33173085971 ro quiet iommu=noaperture cgroup_disable=memory Build Date: 29 December 2014 10:50:22AM xorg-server 2:1.16.99.901-1 (http://www.debian.org/support) Current version of pixman: 0.32.6 Before reporting problems, check http://wiki.x.org to make sure that you have the latest version. Markers: (--) probed, (**) from config file, (==) default setting, (++) from command line, (!!) notice, (II) informational, (WW) warning, (EE) error, (NI) not implemented, (??) unknown. (==) Log file: "/var/log/Xorg.0.log", Time: Tue Feb 10 11:12:00 2015 (==) Using config file: "/etc/X11/xorg.conf" (==) Using system config directory "/usr/share/X11/xorg.conf.d" (II) [KMS] Kernel modesetting enabled. ATTENTION: default value of option vblank_mode overridden by environment. ATTENTION: default value of option vblank_mode overridden by environment. VERT DCL IN[0] DCL SV[0], VERTEXID DCL OUT[0], POSITION DCL CONST[0] DCL TEMP[0..1], LOCAL IMM[0] INT32 {1, 2, 0, 0} IMM[1] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: AND TEMP[0].x, SV[0].xxxx, IMM[0].xxxx 1: I2F TEMP[0].x, TEMP[0].xxxx 2: AND TEMP[1].x, SV[0].xxxx, IMM[0].yyyy 3: ISHR TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx 4: I2F TEMP[1].x, TEMP[1].xxxx 5: MOV TEMP[0].y, TEMP[1].xxxx 6: MAD TEMP[0].xy, IN[0].zwww, TEMP[0].xyyy, IN[0].xyyy 7: MAD TEMP[0].xy, TEMP[0].xyyy, CONST[0].xzzz, CONST[0].ywww 8: MOV TEMP[0].zw, IMM[1].yyxy 9: MOV OUT[0], TEMP[0] 10: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = add i32 %10, %6 %20 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %19) %21 = extractelement <4 x float> %20, i32 0 %22 = extractelement <4 x float> %20, i32 1 %23 = extractelement <4 x float> %20, i32 2 %24 = extractelement <4 x float> %20, i32 3 %25 = add i32 %7, %5 %26 = and i32 %25, 1 %27 = bitcast i32 %26 to float %28 = bitcast float %27 to i32 %29 = sitofp i32 %28 to float %30 = and i32 %25, 2 %31 = bitcast i32 %30 to float %32 = bitcast float %31 to i32 %33 = ashr i32 %32, 1 %34 = bitcast i32 %33 to float %35 = bitcast float %34 to i32 %36 = sitofp i32 %35 to float %37 = fmul float %23, %29 %38 = fadd float %37, %21 %39 = fmul float %24, %36 %40 = fadd float %39, %22 %41 = fmul float %38, %13 %42 = fadd float %41, %14 %43 = fmul float %40, %15 %44 = fadd float %43, %16 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %42, float %44, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 v_add_i32_e32 v1, s11, v3 ; 4A02060B s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v1, s[4:7], 0 idxen ; E00C2000 80010101 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 v_and_b32_e32 v5, 1, v0 ; 360A0081 v_and_b32_e32 v0, 2, v0 ; 36000082 v_cvt_f32_i32_e32 v5, v5 ; 7E0A0B05 v_lshrrev_b32_e32 v0, 1, v0 ; 2C000081 v_cvt_f32_i32_e32 v0, v0 ; 7E000B00 v_mad_f32 v1, v3, v5, v1 ; D2820001 04060B03 v_mad_f32 v0, v4, v0, v2 ; D2820000 040A0104 v_mov_b32_e32 v2, 1.0 ; 7E0402F2 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v3, s5 ; 7E060205 v_mov_b32_e32 v4, s0 ; 7E080200 v_mad_f32 v1, s4, v1, v3 ; D2820001 040E0204 v_mad_f32 v0, s6, v0, v4 ; D2820000 04120006 v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v1, v0, v3, v2 ; F80008CF 02030001 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float %30 = call i32 @llvm.SI.packf16(float %26, float %27) %31 = bitcast i32 %30 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e32 v0, s4, v0 ; 5E000004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e32 v1, s6, v1 ; 5E020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = extractelement <4 x float> %22, i32 2 %26 = extractelement <4 x float> %22, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; F800020F 08070605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %35, float %36, float %37, float %38) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C0800500 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 s_endpgm ; BF810000 The XKEYBOARD keymap compiler (xkbcomp) reports: > Warning: Type "ONE_LEVEL" has 1 levels, but has 2 symbols > Ignoring extra symbols Errors from xkbcomp are not fatal to the X server FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C0800500 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL SV[0], VERTEXID DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL CONST[0..2] DCL TEMP[0..2], LOCAL IMM[0] INT32 {1, 2, 0, 0} IMM[1] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: AND TEMP[0].x, SV[0].xxxx, IMM[0].xxxx 1: I2F TEMP[0].x, TEMP[0].xxxx 2: AND TEMP[1].x, SV[0].xxxx, IMM[0].yyyy 3: ISHR TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx 4: I2F TEMP[1].x, TEMP[1].xxxx 5: MOV TEMP[0].y, TEMP[1].xxxx 6: MUL TEMP[0].xy, IN[0].zwww, TEMP[0].xyyy 7: ADD TEMP[1].xy, IN[0].xyyy, TEMP[0].xyyy 8: MAD TEMP[1].xy, TEMP[1].xyyy, CONST[2].xzzz, CONST[2].ywww 9: MOV TEMP[1].zw, IMM[1].yyxy 10: ADD TEMP[2].xy, CONST[0].xyyy, IN[0].xyyy 11: ADD TEMP[0].xy, TEMP[2].xyyy, TEMP[0].xyyy 12: RCP TEMP[2].x, CONST[1].xxxx 13: RCP TEMP[2].y, CONST[1].yyyy 14: MUL TEMP[0].xy, TEMP[0].xyyy, TEMP[2].xyyy 15: MOV OUT[0], TEMP[1] 16: MOV OUT[1], TEMP[0] 17: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %21 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = add i32 %10, %6 %24 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %22, i32 0, i32 %23) %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = add i32 %7, %5 %30 = and i32 %29, 1 %31 = bitcast i32 %30 to float %32 = bitcast float %31 to i32 %33 = sitofp i32 %32 to float %34 = and i32 %29, 2 %35 = bitcast i32 %34 to float %36 = bitcast float %35 to i32 %37 = ashr i32 %36, 1 %38 = bitcast i32 %37 to float %39 = bitcast float %38 to i32 %40 = sitofp i32 %39 to float %41 = fmul float %27, %33 %42 = fmul float %28, %40 %43 = fadd float %25, %41 %44 = fadd float %26, %42 %45 = fmul float %43, %17 %46 = fadd float %45, %18 %47 = fmul float %44, %19 %48 = fadd float %47, %20 %49 = fadd float %13, %25 %50 = fadd float %14, %26 %51 = fadd float %49, %41 %52 = fadd float %50, %42 %53 = fdiv float 1.000000e+00, %15 %54 = fdiv float 1.000000e+00, %16 %55 = fmul float %51, %53 %56 = fmul float %52, %54 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %55, float %56, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %46, float %48, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 v_add_i32_e32 v1, s11, v3 ; 4A02060B s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v1, s[4:7], 0 idxen ; E00C2000 80010101 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x4 ; C2030104 s_buffer_load_dword s7, s[0:3], 0x5 ; C2038105 s_buffer_load_dword s8, s[0:3], 0x8 ; C2040108 s_buffer_load_dword s9, s[0:3], 0x9 ; C2048109 s_buffer_load_dword s10, s[0:3], 0xa ; C205010A s_buffer_load_dword s0, s[0:3], 0xb ; C200010B v_mov_b32_e32 v5, 0 ; 7E0A0280 v_and_b32_e32 v6, 1, v0 ; 360C0081 v_and_b32_e32 v0, 2, v0 ; 36000082 v_cvt_f32_i32_e32 v6, v6 ; 7E0C0B06 v_lshrrev_b32_e32 v0, 1, v0 ; 2C000081 v_cvt_f32_i32_e32 v0, v0 ; 7E000B00 s_waitcnt lgkmcnt(0) ; BF8C007F v_rcp_f32_e32 v7, s6 ; 7E0E5406 v_rcp_f32_e32 v8, s7 ; 7E105407 v_mov_b32_e32 v9, s9 ; 7E120209 v_mov_b32_e32 v10, s0 ; 7E140200 v_mad_f32 v11, v3, v6, v1 ; D282000B 04060D03 v_mad_f32 v9, s8, v11, v9 ; D2820009 04261608 v_mad_f32 v11, v4, v0, v2 ; D282000B 040A0104 v_mad_f32 v10, s10, v11, v10 ; D282000A 042A160A v_add_f32_e32 v1, s4, v1 ; 06020204 v_mad_f32 v1, v3, v6, v1 ; D2820001 04060D03 v_add_f32_e32 v2, s5, v2 ; 06040405 v_mad_f32 v0, v4, v0, v2 ; D2820000 040A0104 v_mul_f32_e32 v1, v7, v1 ; 10020307 v_mul_f32_e32 v0, v8, v0 ; 10000108 exp 15, 32, 0, 0, 0, v1, v0, v5, v5 ; F800020F 05050001 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 12, 0, 1, 0, v9, v10, v5, v0 ; F80008CF 00050A09 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C0800500 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL CONST[0..2] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MAD TEMP[0].xy, IN[0].xyyy, CONST[2].xzzz, CONST[2].ywww 1: MOV TEMP[0].zw, IMM[0].yyxy 2: ADD TEMP[1].xy, CONST[0].xyyy, IN[0].xyyy 3: RCP TEMP[2].x, CONST[1].xxxx 4: RCP TEMP[2].y, CONST[1].yyyy 5: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xyyy 6: MOV OUT[0], TEMP[0] 7: MOV OUT[1], TEMP[1] 8: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %21 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = add i32 %5, %7 %24 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %22, i32 0, i32 %23) %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = fmul float %25, %17 %28 = fadd float %27, %18 %29 = fmul float %26, %19 %30 = fadd float %29, %20 %31 = fadd float %13, %25 %32 = fadd float %14, %26 %33 = fdiv float 1.000000e+00, %15 %34 = fdiv float 1.000000e+00, %16 %35 = fmul float %31, %33 %36 = fmul float %32, %34 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %35, float %36, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %28, float %30, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x4 ; C2030104 s_buffer_load_dword s7, s[0:3], 0x5 ; C2038105 s_buffer_load_dword s8, s[0:3], 0x8 ; C2040108 s_buffer_load_dword s9, s[0:3], 0x9 ; C2048109 s_buffer_load_dword s10, s[0:3], 0xa ; C205010A s_buffer_load_dword s0, s[0:3], 0xb ; C200010B s_waitcnt lgkmcnt(0) ; BF8C007F v_rcp_f32_e32 v2, s6 ; 7E045406 v_rcp_f32_e32 v3, s7 ; 7E065407 v_mov_b32_e32 v4, s9 ; 7E080209 v_mov_b32_e32 v5, s0 ; 7E0A0200 v_mad_f32 v4, s8, v0, v4 ; D2820004 04120008 v_mad_f32 v5, s10, v1, v5 ; D2820005 0416020A v_add_f32_e32 v0, s4, v0 ; 06000004 v_add_f32_e32 v1, s5, v1 ; 06020205 v_mov_b32_e32 v6, 0 ; 7E0C0280 v_mul_f32_e32 v0, v2, v0 ; 10000102 v_mul_f32_e32 v1, v3, v1 ; 10020303 exp 15, 32, 0, 0, 0, v0, v1, v6, v6 ; F800020F 06060100 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 12, 0, 1, 0, v4, v5, v6, v0 ; F80008CF 00060504 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = bitcast <8 x i32> %23 to <32 x i8> %33 = bitcast <4 x i32> %25 to <16 x i8> %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C0800500 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyxx 1: MOV OUT[1], TEMP[0] 2: MOV OUT[0], IN[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 v_mov_b32_e32 v0, 0 ; 7E000280 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v0, v0 ; F800020F 00000605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL CONST[2] DCL TEMP[0..7], LOCAL IMM[0] INT32 {10, -10, 0, 1} IMM[1] UINT32 {4294967295, 0, 0, 0} IMM[2] INT32 {2, 3, 0, 0} IMM[3] FLT32 { 1.0000, 0.5000, 0.0000, 2.0000} IMM[4] FLT32 { 0.0010, 0.0000, 0.0000, 0.0000} 0: ISLT TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: MOV TEMP[0].xy, IN[0].xyyy 3: TEX TEMP[0], TEMP[0], SAMP[0], 2D 4: MOV TEMP[0], TEMP[0] 5: ELSE :0 6: MOV TEMP[1].x, IMM[1].xxxx 7: UADD TEMP[2].x, CONST[0].xxxx, IMM[0].yyyy 8: MUL TEMP[3].xy, IN[0].xyyy, CONST[2].xyyy 9: USEQ TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz 10: UIF TEMP[4].xxxx :0 11: MOV TEMP[4].xy, TEMP[3].xyxx 12: ELSE :0 13: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].wwww 14: UIF TEMP[5].xxxx :0 15: FRC TEMP[5].xy, TEMP[3].xyyy 16: RCP TEMP[6].x, CONST[2].xxxx 17: RCP TEMP[6].y, CONST[2].yyyy 18: FLR TEMP[7].xy, TEMP[3].xyyy 19: MAD TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy, TEMP[7].xyyy 20: ELSE :0 21: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx 22: UIF TEMP[5].xxxx :0 23: FSGE TEMP[5].x, TEMP[3].xxxx, IMM[3].xxxx 24: UIF TEMP[5].xxxx :0 25: MUL TEMP[5].x, CONST[2].zzzz, CONST[2].xxxx 26: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 27: ADD TEMP[3].x, IMM[3].xxxx, -TEMP[5].xxxx 28: ELSE :0 29: FSLT TEMP[5].x, TEMP[3].xxxx, IMM[3].zzzz 30: UIF TEMP[5].xxxx :0 31: MOV TEMP[3].x, IMM[3].zzzz 32: ENDIF 33: ENDIF 34: FSGE TEMP[5].x, TEMP[3].yyyy, IMM[3].xxxx 35: UIF TEMP[5].xxxx :0 36: MUL TEMP[5].x, CONST[2].wwww, CONST[2].yyyy 37: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 38: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 39: MOV TEMP[3].y, TEMP[5].xxxx 40: ELSE :0 41: FSLT TEMP[5].x, TEMP[3].yyyy, IMM[3].zzzz 42: UIF TEMP[5].xxxx :0 43: MOV TEMP[3].y, IMM[3].zzzz 44: ENDIF 45: ENDIF 46: RCP TEMP[5].x, CONST[2].xxxx 47: RCP TEMP[5].y, CONST[2].yyyy 48: MUL TEMP[3].xy, TEMP[3].xyyy, TEMP[5].xyyy 49: ELSE :0 50: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].yyyy 51: UIF TEMP[5].xxxx :0 52: FLR TEMP[5].x, TEMP[3].xxxx 53: ABS TEMP[5].x, TEMP[5].xxxx 54: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 55: FLR TEMP[6].x, TEMP[6].xxxx 56: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 57: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 58: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 59: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 60: UIF TEMP[5].xxxx :0 61: FRC TEMP[5].x, TEMP[3].xxxx 62: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 63: RCP TEMP[6].x, CONST[2].xxxx 64: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 65: ADD TEMP[3].x, IMM[3].wwww, -TEMP[5].xxxx 66: ELSE :0 67: FRC TEMP[5].x, TEMP[3].xxxx 68: RCP TEMP[6].x, CONST[2].xxxx 69: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[6].xxxx 70: ENDIF 71: FLR TEMP[5].x, TEMP[3].yyyy 72: ABS TEMP[5].x, TEMP[5].xxxx 73: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 74: FLR TEMP[6].x, TEMP[6].xxxx 75: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 76: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 77: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 78: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 79: UIF TEMP[5].xxxx :0 80: FRC TEMP[5].x, TEMP[3].yyyy 81: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 82: RCP TEMP[6].x, CONST[2].yyyy 83: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 84: ADD TEMP[5].x, IMM[3].wwww, -TEMP[5].xxxx 85: MOV TEMP[3].y, TEMP[5].xxxx 86: ELSE :0 87: FRC TEMP[5].x, TEMP[3].yyyy 88: RCP TEMP[6].x, CONST[2].yyyy 89: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 90: MOV TEMP[3].y, TEMP[5].xxxx 91: ENDIF 92: ENDIF 93: ENDIF 94: ENDIF 95: MOV TEMP[4].xy, TEMP[3].xyxx 96: ENDIF 97: MOV TEMP[2].xy, TEMP[4].xyxx 98: USEQ TEMP[3].x, CONST[0].xxxx, IMM[0].xxxx 99: UIF TEMP[3].xxxx :0 100: FSGE TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz 101: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[3].xxxx 102: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 103: FSGE TEMP[5].x, TEMP[4].yyyy, IMM[3].zzzz 104: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 105: FSLT TEMP[5].x, TEMP[4].yyyy, IMM[3].xxxx 106: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 107: NOT TEMP[3].x, TEMP[3].xxxx 108: UIF TEMP[3].xxxx :0 109: MOV TEMP[3].xyz, IMM[3].zzzz 110: MOV TEMP[3].w, IMM[3].zzzz 111: MOV TEMP[3], TEMP[3] 112: MOV TEMP[1].x, IMM[1].yyyy 113: ELSE :0 114: FRC TEMP[4].xy, TEMP[4].xyyy 115: RCP TEMP[5].x, CONST[2].xxxx 116: RCP TEMP[5].y, CONST[2].yyyy 117: MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy 118: ENDIF 119: ENDIF 120: UIF TEMP[1].xxxx :0 121: MOV TEMP[2].xy, TEMP[2].xyyy 122: TEX TEMP[2], TEMP[2], SAMP[0], 2D 123: MOV TEMP[3], TEMP[2] 124: ENDIF 125: MOV TEMP[0], TEMP[3] 126: ENDIF 127: MOV OUT[0], TEMP[0] 128: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 44) %29 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %30 = load <8 x i32> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %32 = load <4 x i32> addrspace(2)* %31, !tbaa !0 %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %35 = bitcast float %24 to i32 %36 = icmp slt i32 %35, 10 %37 = sext i1 %36 to i32 %38 = bitcast i32 %37 to float %39 = bitcast float %38 to i32 %40 = icmp ne i32 %39, 0 br i1 %40, label %IF, label %ELSE IF: ; preds = %main_body %41 = bitcast float %33 to i32 %42 = bitcast float %34 to i32 %43 = insertelement <2 x i32> undef, i32 %41, i32 0 %44 = insertelement <2 x i32> %43, i32 %42, i32 1 %45 = bitcast <8 x i32> %30 to <32 x i8> %46 = bitcast <4 x i32> %32 to <16 x i8> %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %44, <32 x i8> %45, <16 x i8> %46, i32 2) %48 = extractelement <4 x float> %47, i32 0 %49 = extractelement <4 x float> %47, i32 1 %50 = extractelement <4 x float> %47, i32 2 %51 = extractelement <4 x float> %47, i32 3 br label %ENDIF ELSE: ; preds = %main_body %52 = bitcast float %24 to i32 %53 = add i32 %52, -10 %54 = bitcast i32 %53 to float %55 = fmul float %33, %25 %56 = fmul float %34, %26 %57 = bitcast float %54 to i32 %58 = icmp eq i32 %57, 0 %59 = sext i1 %58 to i32 %60 = bitcast i32 %59 to float %61 = bitcast float %60 to i32 %62 = icmp ne i32 %61, 0 br i1 %62, label %ENDIF32, label %ELSE34 ENDIF: ; preds = %IF69, %ENDIF62, %IF %temp3.0 = phi float [ %51, %IF ], [ %226, %IF69 ], [ 0.000000e+00, %ENDIF62 ] %temp2.0 = phi float [ %50, %IF ], [ %225, %IF69 ], [ 0.000000e+00, %ENDIF62 ] %temp1.0 = phi float [ %49, %IF ], [ %224, %IF69 ], [ %temp13.7, %ENDIF62 ] %temp.0 = phi float [ %48, %IF ], [ %223, %IF69 ], [ %temp12.6, %ENDIF62 ] %63 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0) %64 = bitcast i32 %63 to float %65 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0) %66 = bitcast i32 %65 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %64, float %66, float %64, float %66) ret void ELSE34: ; preds = %ELSE %67 = bitcast float %54 to i32 %68 = icmp eq i32 %67, 1 %69 = sext i1 %68 to i32 %70 = bitcast i32 %69 to float %71 = bitcast float %70 to i32 %72 = icmp ne i32 %71, 0 br i1 %72, label %IF36, label %ELSE37 ENDIF32: ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE %temp13.0 = phi float [ %56, %ELSE ], [ %88, %IF36 ], [ %132, %ENDIF47 ], [ %56, %ELSE40 ], [ %176, %IF60 ], [ %178, %ELSE61 ] %temp16.0 = phi float [ %55, %ELSE ], [ %86, %IF36 ], [ %131, %ENDIF47 ], [ %55, %ELSE40 ], [ %temp12.5, %ELSE61 ], [ %temp12.5, %IF60 ] %73 = bitcast float %24 to i32 %74 = icmp eq i32 %73, 10 %75 = sext i1 %74 to i32 %76 = bitcast i32 %75 to float %77 = bitcast float %76 to i32 %78 = icmp ne i32 %77, 0 br i1 %78, label %IF63, label %ENDIF62 IF36: ; preds = %ELSE34 %79 = call float @llvm.AMDIL.fraction.(float %55) %80 = call float @llvm.AMDIL.fraction.(float %56) %81 = fdiv float 1.000000e+00, %25 %82 = fdiv float 1.000000e+00, %26 %83 = call float @floor(float %55) %84 = call float @floor(float %56) %85 = fmul float %79, %81 %86 = fadd float %85, %83 %87 = fmul float %80, %82 %88 = fadd float %87, %84 br label %ENDIF32 ELSE37: ; preds = %ELSE34 %89 = bitcast float %54 to i32 %90 = icmp eq i32 %89, 2 %91 = sext i1 %90 to i32 %92 = bitcast i32 %91 to float %93 = bitcast float %92 to i32 %94 = icmp ne i32 %93, 0 br i1 %94, label %IF39, label %ELSE40 IF39: ; preds = %ELSE37 %95 = fcmp oge float %55, 1.000000e+00 %96 = sext i1 %95 to i32 %97 = bitcast i32 %96 to float %98 = bitcast float %97 to i32 %99 = icmp ne i32 %98, 0 br i1 %99, label %IF42, label %ELSE43 ELSE40: ; preds = %ELSE37 %100 = bitcast float %54 to i32 %101 = icmp eq i32 %100, 3 %102 = sext i1 %101 to i32 %103 = bitcast i32 %102 to float %104 = bitcast float %103 to i32 %105 = icmp ne i32 %104, 0 br i1 %105, label %IF54, label %ENDIF32 IF42: ; preds = %IF39 %106 = fmul float %27, %25 %107 = fmul float %106, 5.000000e-01 %108 = fsub float -0.000000e+00, %107 %109 = fadd float 1.000000e+00, %108 br label %ENDIF41 ELSE43: ; preds = %IF39 %110 = fcmp olt float %55, 0.000000e+00 %111 = sext i1 %110 to i32 %112 = bitcast i32 %111 to float %113 = bitcast float %112 to i32 %114 = icmp ne i32 %113, 0 %. = select i1 %114, float 0.000000e+00, float %55 br label %ENDIF41 ENDIF41: ; preds = %ELSE43, %IF42 %temp12.2 = phi float [ %109, %IF42 ], [ %., %ELSE43 ] %115 = fcmp oge float %56, 1.000000e+00 %116 = sext i1 %115 to i32 %117 = bitcast i32 %116 to float %118 = bitcast float %117 to i32 %119 = icmp ne i32 %118, 0 br i1 %119, label %IF48, label %ELSE49 IF48: ; preds = %ENDIF41 %120 = fmul float %28, %26 %121 = fmul float %120, 5.000000e-01 %122 = fsub float -0.000000e+00, %121 %123 = fadd float 1.000000e+00, %122 br label %ENDIF47 ELSE49: ; preds = %ENDIF41 %124 = fcmp olt float %56, 0.000000e+00 %125 = sext i1 %124 to i32 %126 = bitcast i32 %125 to float %127 = bitcast float %126 to i32 %128 = icmp ne i32 %127, 0 %.71 = select i1 %128, float 0.000000e+00, float %56 br label %ENDIF47 ENDIF47: ; preds = %ELSE49, %IF48 %temp13.3 = phi float [ %123, %IF48 ], [ %.71, %ELSE49 ] %129 = fdiv float 1.000000e+00, %25 %130 = fdiv float 1.000000e+00, %26 %131 = fmul float %temp12.2, %129 %132 = fmul float %temp13.3, %130 br label %ENDIF32 IF54: ; preds = %ELSE40 %133 = call float @floor(float %55) %134 = call float @fabs(float %133) %135 = fmul float %134, 5.000000e-01 %136 = call float @floor(float %135) %137 = fmul float 2.000000e+00, %136 %138 = fsub float -0.000000e+00, %137 %139 = fadd float %134, %138 %140 = fsub float -0.000000e+00, %139 %141 = fadd float 1.000000e+00, %140 %142 = fcmp olt float %141, 0x3F50624DE0000000 %143 = sext i1 %142 to i32 %144 = bitcast i32 %143 to float %145 = bitcast float %144 to i32 %146 = icmp ne i32 %145, 0 %147 = call float @llvm.AMDIL.fraction.(float %55) br i1 %146, label %IF57, label %ELSE58 IF57: ; preds = %IF54 %148 = fsub float -0.000000e+00, %147 %149 = fadd float 1.000000e+00, %148 %150 = fdiv float 1.000000e+00, %25 %151 = fmul float %149, %150 %152 = fsub float -0.000000e+00, %151 %153 = fadd float 2.000000e+00, %152 br label %ENDIF56 ELSE58: ; preds = %IF54 %154 = fdiv float 1.000000e+00, %25 %155 = fmul float %147, %154 br label %ENDIF56 ENDIF56: ; preds = %ELSE58, %IF57 %temp12.5 = phi float [ %153, %IF57 ], [ %155, %ELSE58 ] %156 = call float @floor(float %56) %157 = call float @fabs(float %156) %158 = fmul float %157, 5.000000e-01 %159 = call float @floor(float %158) %160 = fmul float 2.000000e+00, %159 %161 = fsub float -0.000000e+00, %160 %162 = fadd float %157, %161 %163 = fsub float -0.000000e+00, %162 %164 = fadd float 1.000000e+00, %163 %165 = fcmp olt float %164, 0x3F50624DE0000000 %166 = sext i1 %165 to i32 %167 = bitcast i32 %166 to float %168 = bitcast float %167 to i32 %169 = icmp ne i32 %168, 0 %170 = call float @llvm.AMDIL.fraction.(float %56) br i1 %169, label %IF60, label %ELSE61 IF60: ; preds = %ENDIF56 %171 = fsub float -0.000000e+00, %170 %172 = fadd float 1.000000e+00, %171 %173 = fdiv float 1.000000e+00, %26 %174 = fmul float %172, %173 %175 = fsub float -0.000000e+00, %174 %176 = fadd float 2.000000e+00, %175 br label %ENDIF32 ELSE61: ; preds = %ENDIF56 %177 = fdiv float 1.000000e+00, %26 %178 = fmul float %170, %177 br label %ENDIF32 IF63: ; preds = %ENDIF32 %179 = fcmp oge float %temp16.0, 0.000000e+00 %180 = sext i1 %179 to i32 %181 = bitcast i32 %180 to float %182 = fcmp olt float %temp16.0, 1.000000e+00 %183 = sext i1 %182 to i32 %184 = bitcast i32 %183 to float %185 = bitcast float %181 to i32 %186 = bitcast float %184 to i32 %187 = and i32 %185, %186 %188 = bitcast i32 %187 to float %189 = fcmp oge float %temp13.0, 0.000000e+00 %190 = sext i1 %189 to i32 %191 = bitcast i32 %190 to float %192 = bitcast float %188 to i32 %193 = bitcast float %191 to i32 %194 = and i32 %192, %193 %195 = bitcast i32 %194 to float %196 = fcmp olt float %temp13.0, 1.000000e+00 %197 = sext i1 %196 to i32 %198 = bitcast i32 %197 to float %199 = bitcast float %195 to i32 %200 = bitcast float %198 to i32 %201 = and i32 %199, %200 %202 = bitcast i32 %201 to float %203 = bitcast float %202 to i32 %204 = xor i32 %203, -1 %205 = bitcast i32 %204 to float %206 = bitcast float %205 to i32 %207 = icmp ne i32 %206, 0 br i1 %207, label %ENDIF62, label %ELSE67 ENDIF62: ; preds = %ELSE67, %IF63, %ENDIF32 %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ] %temp8.0 = phi float [ %temp16.0, %ENDIF32 ], [ %214, %ELSE67 ], [ %temp16.0, %IF63 ] %temp9.0 = phi float [ %temp13.0, %ENDIF32 ], [ %215, %ELSE67 ], [ %temp13.0, %IF63 ] %temp12.6 = phi float [ %76, %ENDIF32 ], [ %205, %ELSE67 ], [ 0.000000e+00, %IF63 ] %temp13.7 = phi float [ %temp13.0, %ENDIF32 ], [ %temp13.0, %ELSE67 ], [ 0.000000e+00, %IF63 ] %208 = bitcast float %temp4.0 to i32 %209 = icmp ne i32 %208, 0 br i1 %209, label %IF69, label %ENDIF ELSE67: ; preds = %IF63 %210 = call float @llvm.AMDIL.fraction.(float %temp16.0) %211 = call float @llvm.AMDIL.fraction.(float %temp13.0) %212 = fdiv float 1.000000e+00, %25 %213 = fdiv float 1.000000e+00, %26 %214 = fmul float %210, %212 %215 = fmul float %211, %213 br label %ENDIF62 IF69: ; preds = %ENDIF62 %216 = bitcast float %temp8.0 to i32 %217 = bitcast float %temp9.0 to i32 %218 = insertelement <2 x i32> undef, i32 %216, i32 0 %219 = insertelement <2 x i32> %218, i32 %217, i32 1 %220 = bitcast <8 x i32> %30 to <32 x i8> %221 = bitcast <4 x i32> %32 to <16 x i8> %222 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %219, <32 x i8> %220, <16 x i8> %221, i32 2) %223 = extractelement <4 x float> %222, i32 0 %224 = extractelement <4 x float> %222, i32 1 %225 = extractelement <4 x float> %222, i32 2 %226 = extractelement <4 x float> %222, i32 3 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x0 ; C2040100 s_load_dwordx4 s[20:23], s[4:5], 0x0 ; C08A0500 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_lt_i32_e64 s[4:5], s8, 10 ; D1020004 00011408 v_cndmask_b32_e64 v0, 0, -1, s[4:5] ; D2000000 00118280 v_cmp_eq_i32_e64 s[4:5], v0, 0 ; D1040004 00010100 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842404 s_xor_b64 s[4:5], exec, s[4:5] ; 8984047E s_cbranch_execz BB0_8 ; BF880000 v_mov_b32_e32 v0, s8 ; 7E000208 s_buffer_load_dword s6, s[0:3], 0x8 ; C2030108 s_buffer_load_dword s7, s[0:3], 0x9 ; C2038109 v_add_i32_e32 v6, -10, v0 ; 4A0C00CA v_cmp_eq_i32_e64 s[10:11], v6, 0 ; D104000A 00010106 v_cndmask_b32_e64 v0, 0, -1, s[10:11] ; D2000000 00298280 v_cmp_eq_i32_e64 s[10:11], v0, 0 ; D104000A 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s6, v2 ; 10000406 v_mul_f32_e32 v1, s7, v3 ; 10020607 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_9 ; BF880000 v_cmp_eq_i32_e64 s[24:25], v6, 1 ; D1040018 00010306 v_cndmask_b32_e64 v4, 0, -1, s[24:25] ; D2000004 00618280 v_cmp_eq_i32_e64 s[24:25], v4, 0 ; D1040018 00010104 s_waitcnt expcnt(0) ; BF8C070F s_and_saveexec_b64 s[24:25], s[24:25] ; BE982418 s_xor_b64 s[24:25], exec, s[24:25] ; 8998187E s_cbranch_execz BB0_10 ; BF880000 v_cmp_eq_i32_e64 s[26:27], v6, 2 ; D104001A 00010506 v_cndmask_b32_e64 v4, 0, -1, s[26:27] ; D2000004 00698280 v_cmp_eq_i32_e64 s[26:27], v4, 0 ; D104001A 00010104 s_and_saveexec_b64 s[26:27], s[26:27] ; BE9A241A s_xor_b64 s[26:27], exec, s[26:27] ; 899A1A7E s_cbranch_execz BB0_13 ; BF880000 v_cmp_eq_i32_e64 s[28:29], v6, 3 ; D104001C 00010706 v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_ne_i32_e64 s[28:29], v4, 0 ; D10A001C 00010104 v_mov_b32_e32 v4, v0 ; 7E080300 v_mov_b32_e32 v5, v1 ; 7E0A0301 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E s_cbranch_execz BB0_29 ; BF880000 v_floor_f32_e32 v4, v0 ; 7E084900 v_mul_f32_e64 v5, 0.5, |v4| ; D2100205 000208F0 v_floor_f32_e32 v5, v5 ; 7E0A4905 v_mad_f32 v4, 2.0, v5, -|v4| ; D2820404 84120AF4 v_add_f32_e32 v4, 1.0, v4 ; 060808F2 v_mov_b32_e32 v5, 0x3a83126f ; 7E0A02FF 3A83126F v_cmp_lt_f32_e32 vcc, v4, v5 ; 7C020B04 v_cndmask_b32_e64 v4, 0, -1, vcc ; D2000004 01A98280 v_fract_f32_e32 v5, v0 ; 7E0A4100 v_cmp_eq_i32_e64 s[30:31], v4, 0 ; D104001E 00010104 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E v_rcp_f32_e32 v4, s6 ; 7E085406 v_mul_f32_e32 v4, v4, v5 ; 10080B04 s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E v_rcp_f32_e32 v4, s6 ; 7E085406 v_subrev_f32_e32 v5, 1.0, v5 ; 0A0A0AF2 v_mad_f32 v4, v5, v4, 2.0 ; D2820004 03D20905 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E v_floor_f32_e32 v5, v1 ; 7E0A4901 v_mul_f32_e64 v6, 0.5, |v5| ; D2100206 00020AF0 v_floor_f32_e32 v6, v6 ; 7E0C4906 v_mad_f32 v5, 2.0, v6, -|v5| ; D2820405 84160CF4 v_add_f32_e32 v5, 1.0, v5 ; 060A0AF2 v_mov_b32_e32 v6, 0x3a83126f ; 7E0C02FF 3A83126F v_cmp_lt_f32_e32 vcc, v5, v6 ; 7C020D05 v_cndmask_b32_e64 v5, 0, -1, vcc ; D2000805 01A98280 v_fract_f32_e32 v6, v1 ; 7E0C4101 v_cmp_eq_i32_e64 s[30:31], v5, 0 ; D104001E 00010105 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E v_rcp_f32_e32 v5, s7 ; 7E0A5407 v_mul_f32_e32 v5, v5, v6 ; 100A0D05 s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E v_rcp_f32_e32 v5, s7 ; 7E0A5407 v_subrev_f32_e32 v6, 1.0, v6 ; 0A0C0CF2 v_mad_f32 v5, v6, v5, 2.0 ; D2820005 03D20B06 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E s_or_b64 exec, exec, s[28:29] ; 88FE1C7E s_or_saveexec_b64 s[26:27], s[26:27] ; BE9A251A s_xor_b64 exec, exec, s[26:27] ; 89FE1A7E s_cbranch_execz BB0_19 ; BF880000 v_cmp_ge_f32_e64 s[28:29], v0, 1.0 ; D00C001C 0001E500 v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_eq_i32_e64 s[28:29], v4, 0 ; D104001C 00010104 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_cmp_lt_f32_e64 s[30:31], v0, 0 ; D002001E 00010100 v_cndmask_b32_e64 v4, 0, -1, s[30:31] ; D2000004 00798280 v_cmp_ne_i32_e64 s[30:31], v4, 0 ; D10A001E 00010104 v_cndmask_b32_e64 v4, v0, 0, s[30:31] ; D2000004 00790100 s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E s_buffer_load_dword s9, s[0:3], 0xa ; C204810A s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s9 ; 7E080209 v_mul_f32_e32 v4, s6, v4 ; 10080806 v_mad_f32 v4, -0.5, v4, 1.0 ; D2820004 03CA08F1 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_cmp_ge_f32_e64 s[28:29], v1, 1.0 ; D00C001C 0001E501 v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_cmp_eq_i32_e64 s[28:29], v5, 0 ; D104001C 00010105 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_cmp_lt_f32_e64 s[30:31], v1, 0 ; D002001E 00010101 v_cndmask_b32_e64 v5, 0, -1, s[30:31] ; D2000805 00798280 v_cmp_ne_i32_e64 s[30:31], v5, 0 ; D10A001E 00010105 v_cndmask_b32_e64 v5, v1, 0, s[30:31] ; D2000805 08790101 s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E s_buffer_load_dword s9, s[0:3], 0xb ; C204810B s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v5, s9 ; 7E0A0209 v_mul_f32_e32 v5, s7, v5 ; 100A0A07 v_mad_f32 v5, -0.5, v5, 1.0 ; D2820005 03CA0AF1 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_rcp_f32_e32 v6, s6 ; 7E0C5406 v_rcp_f32_e32 v7, s7 ; 7E0E5407 v_mul_f32_e32 v4, v6, v4 ; 10080906 v_mul_f32_e32 v5, v7, v5 ; 100A0B07 s_or_b64 exec, exec, s[26:27] ; 88FE1A7E s_or_saveexec_b64 s[24:25], s[24:25] ; BE982518 s_xor_b64 exec, exec, s[24:25] ; 89FE187E v_fract_f32_e32 v4, v0 ; 7E084100 v_fract_f32_e32 v5, v1 ; 7E0A4101 v_rcp_f32_e32 v6, s6 ; 7E0C5406 v_rcp_f32_e32 v7, s7 ; 7E0E5407 v_floor_f32_e32 v0, v0 ; 7E004900 v_floor_f32_e32 v1, v1 ; 7E024901 v_mad_f32 v4, v4, v6, v0 ; D2820004 04020D04 v_mad_f32 v5, v5, v7, v1 ; D2820005 04060F05 s_or_b64 exec, exec, s[24:25] ; 88FE187E v_mov_b32_e32 v1, v5 ; 7E020305 v_mov_b32_e32 v0, v4 ; 7E000304 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_cmp_eq_i32_e64 s[10:11], s8, 10 ; D104000A 00011408 v_cndmask_b32_e64 v4, 0, -1, s[10:11] ; D2000004 00298280 v_cmp_ne_i32_e64 s[10:11], v4, 0 ; D10A000A 00010104 v_mov_b32_e32 v7, -1 ; 7E0E02C1 v_mov_b32_e32 v5, v1 ; 7E0A0301 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_36 ; BF880000 v_mov_b32_e32 v5, 0 ; 7E0A0280 v_cmp_ge_f32_e64 s[24:25], v0, 0 ; D00C0018 00010100 v_cmp_lt_f32_e64 s[26:27], v0, 1.0 ; D002001A 0001E500 s_and_b64 s[24:25], s[24:25], s[26:27] ; 87981A18 v_cndmask_b32_e64 v4, 0, -1, s[24:25] ; D2000004 00618280 v_cmp_ge_f32_e64 s[24:25], v1, 0 ; D00C0018 00010101 v_cndmask_b32_e64 v6, 0, -1, s[24:25] ; D2000006 00618280 v_and_b32_e32 v4, v6, v4 ; 36080906 v_cmp_lt_f32_e64 s[24:25], v1, 1.0 ; D0020018 0001E501 v_cndmask_b32_e64 v6, 0, -1, s[24:25] ; D2000006 00618280 v_and_b32_e32 v4, v6, v4 ; 36080906 v_not_b32_e32 v6, v4 ; 7E0C6F04 v_cmp_eq_i32_e64 s[24:25], v4, -1 ; D1040018 00018304 v_mov_b32_e32 v4, v5 ; 7E080305 v_mov_b32_e32 v7, v5 ; 7E0E0305 s_and_saveexec_b64 s[24:25], s[24:25] ; BE982418 s_xor_b64 s[24:25], exec, s[24:25] ; 8998187E v_rcp_f32_e32 v4, s6 ; 7E085406 v_rcp_f32_e32 v5, s7 ; 7E0A5407 v_fract_f32_e32 v0, v0 ; 7E004100 v_fract_f32_e32 v7, v1 ; 7E0E4101 v_mul_f32_e32 v0, v4, v0 ; 10000104 v_mul_f32_e32 v8, v5, v7 ; 10100F05 v_mov_b32_e32 v5, v1 ; 7E0A0301 v_mov_b32_e32 v7, -1 ; 7E0E02C1 v_mov_b32_e32 v4, v6 ; 7E080306 v_mov_b32_e32 v1, v8 ; 7E020308 s_or_b64 exec, exec, s[24:25] ; 88FE187E s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_mov_b32_e32 v6, 0 ; 7E0C0280 v_cmp_ne_i32_e64 s[6:7], v7, 0 ; D10A0006 00010107 v_mov_b32_e32 v7, v6 ; 7E0E0306 s_and_saveexec_b64 s[6:7], s[6:7] ; BE862406 s_xor_b64 s[6:7], exec, s[6:7] ; 8986067E image_sample v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[12:19], s[20:23] ; F0800F00 00A30400 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[6:7] ; 88FE067E s_or_saveexec_b64 s[4:5], s[4:5] ; BE842504 s_xor_b64 exec, exec, s[4:5] ; 89FE047E image_sample v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[20:23] ; F0800F00 00A30402 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[4:5] ; 88FE047E v_cvt_pkrtz_f16_f32_e32 v0, v4, v5 ; 5E000B04 v_cvt_pkrtz_f16_f32_e32 v1, v6, v7 ; 5E020F06 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyxx 1: MOV OUT[1], TEMP[0] 2: MOV OUT[0], IN[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 v_mov_b32_e32 v0, 0 ; 7E000280 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v0, v0 ; F800020F 00000605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL CONST[3] DCL TEMP[0..7], LOCAL IMM[0] INT32 {10, -10, 0, 1} IMM[1] UINT32 {4294967295, 0, 0, 0} IMM[2] INT32 {2, 3, 0, 0} IMM[3] FLT32 { 1.0000, 0.5000, 0.0000, 2.0000} IMM[4] FLT32 { 0.0010, 0.0000, 0.0000, 0.0000} 0: ISLT TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: MOV TEMP[0].xy, IN[0].xyyy 3: TEX TEMP[0], TEMP[0], SAMP[0], 2D 4: MOV TEMP[0].w, TEMP[0] 5: ELSE :0 6: MOV TEMP[1].x, IMM[1].xxxx 7: UADD TEMP[2].x, CONST[0].xxxx, IMM[0].yyyy 8: MUL TEMP[3].xy, IN[0].xyyy, CONST[3].xyyy 9: USEQ TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz 10: UIF TEMP[4].xxxx :0 11: MOV TEMP[4].xy, TEMP[3].xyxx 12: ELSE :0 13: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].wwww 14: UIF TEMP[5].xxxx :0 15: FRC TEMP[5].xy, TEMP[3].xyyy 16: RCP TEMP[6].x, CONST[3].xxxx 17: RCP TEMP[6].y, CONST[3].yyyy 18: FLR TEMP[7].xy, TEMP[3].xyyy 19: MAD TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy, TEMP[7].xyyy 20: ELSE :0 21: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx 22: UIF TEMP[5].xxxx :0 23: FSGE TEMP[5].x, TEMP[3].xxxx, IMM[3].xxxx 24: UIF TEMP[5].xxxx :0 25: MUL TEMP[5].x, CONST[3].zzzz, CONST[3].xxxx 26: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 27: ADD TEMP[3].x, IMM[3].xxxx, -TEMP[5].xxxx 28: ELSE :0 29: FSLT TEMP[5].x, TEMP[3].xxxx, IMM[3].zzzz 30: UIF TEMP[5].xxxx :0 31: MOV TEMP[3].x, IMM[3].zzzz 32: ENDIF 33: ENDIF 34: FSGE TEMP[5].x, TEMP[3].yyyy, IMM[3].xxxx 35: UIF TEMP[5].xxxx :0 36: MUL TEMP[5].x, CONST[3].wwww, CONST[3].yyyy 37: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 38: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 39: MOV TEMP[3].y, TEMP[5].xxxx 40: ELSE :0 41: FSLT TEMP[5].x, TEMP[3].yyyy, IMM[3].zzzz 42: UIF TEMP[5].xxxx :0 43: MOV TEMP[3].y, IMM[3].zzzz 44: ENDIF 45: ENDIF 46: RCP TEMP[5].x, CONST[3].xxxx 47: RCP TEMP[5].y, CONST[3].yyyy 48: MUL TEMP[3].xy, TEMP[3].xyyy, TEMP[5].xyyy 49: ELSE :0 50: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].yyyy 51: UIF TEMP[5].xxxx :0 52: FLR TEMP[5].x, TEMP[3].xxxx 53: ABS TEMP[5].x, TEMP[5].xxxx 54: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 55: FLR TEMP[6].x, TEMP[6].xxxx 56: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 57: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 58: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 59: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 60: UIF TEMP[5].xxxx :0 61: FRC TEMP[5].x, TEMP[3].xxxx 62: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 63: RCP TEMP[6].x, CONST[3].xxxx 64: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 65: ADD TEMP[3].x, IMM[3].wwww, -TEMP[5].xxxx 66: ELSE :0 67: FRC TEMP[5].x, TEMP[3].xxxx 68: RCP TEMP[6].x, CONST[3].xxxx 69: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[6].xxxx 70: ENDIF 71: FLR TEMP[5].x, TEMP[3].yyyy 72: ABS TEMP[5].x, TEMP[5].xxxx 73: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 74: FLR TEMP[6].x, TEMP[6].xxxx 75: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 76: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 77: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 78: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 79: UIF TEMP[5].xxxx :0 80: FRC TEMP[5].x, TEMP[3].yyyy 81: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 82: RCP TEMP[6].x, CONST[3].yyyy 83: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 84: ADD TEMP[5].x, IMM[3].wwww, -TEMP[5].xxxx 85: MOV TEMP[3].y, TEMP[5].xxxx 86: ELSE :0 87: FRC TEMP[5].x, TEMP[3].yyyy 88: RCP TEMP[6].x, CONST[3].yyyy 89: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 90: MOV TEMP[3].y, TEMP[5].xxxx 91: ENDIF 92: ENDIF 93: ENDIF 94: ENDIF 95: MOV TEMP[4].xy, TEMP[3].xyxx 96: ENDIF 97: MOV TEMP[2].xy, TEMP[4].xyxx 98: USEQ TEMP[3].x, CONST[0].xxxx, IMM[0].xxxx 99: UIF TEMP[3].xxxx :0 100: FSGE TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz 101: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[3].xxxx 102: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 103: FSGE TEMP[5].x, TEMP[4].yyyy, IMM[3].zzzz 104: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 105: FSLT TEMP[5].x, TEMP[4].yyyy, IMM[3].xxxx 106: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 107: NOT TEMP[3].x, TEMP[3].xxxx 108: UIF TEMP[3].xxxx :0 109: MOV TEMP[3].xyz, IMM[3].zzzz 110: MOV TEMP[3].w, IMM[3].zzzz 111: MOV TEMP[3], TEMP[3] 112: MOV TEMP[1].x, IMM[1].yyyy 113: ELSE :0 114: FRC TEMP[4].xy, TEMP[4].xyyy 115: RCP TEMP[5].x, CONST[3].xxxx 116: RCP TEMP[5].y, CONST[3].yyyy 117: MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy 118: ENDIF 119: ENDIF 120: UIF TEMP[1].xxxx :0 121: MOV TEMP[2].xy, TEMP[2].xyyy 122: TEX TEMP[2], TEMP[2], SAMP[0], 2D 123: MOV TEMP[3], TEMP[2] 124: ENDIF 125: MOV TEMP[0].w, TEMP[3] 126: ENDIF 127: MUL TEMP[0], CONST[1], TEMP[0].wwww 128: MOV OUT[0], TEMP[0] 129: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 24) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 28) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60) %33 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %34 = load <8 x i32> addrspace(2)* %33, !tbaa !0 %35 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %36 = load <4 x i32> addrspace(2)* %35, !tbaa !0 %37 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %38 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %39 = bitcast float %24 to i32 %40 = icmp slt i32 %39, 10 %41 = sext i1 %40 to i32 %42 = bitcast i32 %41 to float %43 = bitcast float %42 to i32 %44 = icmp ne i32 %43, 0 br i1 %44, label %IF, label %ELSE IF: ; preds = %main_body %45 = bitcast float %37 to i32 %46 = bitcast float %38 to i32 %47 = insertelement <2 x i32> undef, i32 %45, i32 0 %48 = insertelement <2 x i32> %47, i32 %46, i32 1 %49 = bitcast <8 x i32> %34 to <32 x i8> %50 = bitcast <4 x i32> %36 to <16 x i8> %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %48, <32 x i8> %49, <16 x i8> %50, i32 2) %52 = extractelement <4 x float> %51, i32 3 br label %ENDIF ELSE: ; preds = %main_body %53 = bitcast float %24 to i32 %54 = add i32 %53, -10 %55 = bitcast i32 %54 to float %56 = fmul float %37, %29 %57 = fmul float %38, %30 %58 = bitcast float %55 to i32 %59 = icmp eq i32 %58, 0 %60 = sext i1 %59 to i32 %61 = bitcast i32 %60 to float %62 = bitcast float %61 to i32 %63 = icmp ne i32 %62, 0 br i1 %63, label %ENDIF32, label %ELSE34 ENDIF: ; preds = %IF69, %ENDIF62, %IF %temp3.0 = phi float [ %52, %IF ], [ %228, %IF69 ], [ 0.000000e+00, %ENDIF62 ] %64 = fmul float %25, %temp3.0 %65 = fmul float %26, %temp3.0 %66 = fmul float %27, %temp3.0 %67 = fmul float %28, %temp3.0 %68 = call i32 @llvm.SI.packf16(float %64, float %65) %69 = bitcast i32 %68 to float %70 = call i32 @llvm.SI.packf16(float %66, float %67) %71 = bitcast i32 %70 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %69, float %71, float %69, float %71) ret void ELSE34: ; preds = %ELSE %72 = bitcast float %55 to i32 %73 = icmp eq i32 %72, 1 %74 = sext i1 %73 to i32 %75 = bitcast i32 %74 to float %76 = bitcast float %75 to i32 %77 = icmp ne i32 %76, 0 br i1 %77, label %IF36, label %ELSE37 ENDIF32: ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE %temp16.0 = phi float [ %56, %ELSE ], [ %91, %IF36 ], [ %136, %ENDIF47 ], [ %56, %ELSE40 ], [ %temp12.5, %ELSE61 ], [ %temp12.5, %IF60 ] %temp17.0 = phi float [ %57, %ELSE ], [ %93, %IF36 ], [ %137, %ENDIF47 ], [ %57, %ELSE40 ], [ %181, %IF60 ], [ %183, %ELSE61 ] %78 = bitcast float %24 to i32 %79 = icmp eq i32 %78, 10 %80 = sext i1 %79 to i32 %81 = bitcast i32 %80 to float %82 = bitcast float %81 to i32 %83 = icmp ne i32 %82, 0 br i1 %83, label %IF63, label %ENDIF62 IF36: ; preds = %ELSE34 %84 = call float @llvm.AMDIL.fraction.(float %56) %85 = call float @llvm.AMDIL.fraction.(float %57) %86 = fdiv float 1.000000e+00, %29 %87 = fdiv float 1.000000e+00, %30 %88 = call float @floor(float %56) %89 = call float @floor(float %57) %90 = fmul float %84, %86 %91 = fadd float %90, %88 %92 = fmul float %85, %87 %93 = fadd float %92, %89 br label %ENDIF32 ELSE37: ; preds = %ELSE34 %94 = bitcast float %55 to i32 %95 = icmp eq i32 %94, 2 %96 = sext i1 %95 to i32 %97 = bitcast i32 %96 to float %98 = bitcast float %97 to i32 %99 = icmp ne i32 %98, 0 br i1 %99, label %IF39, label %ELSE40 IF39: ; preds = %ELSE37 %100 = fcmp oge float %56, 1.000000e+00 %101 = sext i1 %100 to i32 %102 = bitcast i32 %101 to float %103 = bitcast float %102 to i32 %104 = icmp ne i32 %103, 0 br i1 %104, label %IF42, label %ELSE43 ELSE40: ; preds = %ELSE37 %105 = bitcast float %55 to i32 %106 = icmp eq i32 %105, 3 %107 = sext i1 %106 to i32 %108 = bitcast i32 %107 to float %109 = bitcast float %108 to i32 %110 = icmp ne i32 %109, 0 br i1 %110, label %IF54, label %ENDIF32 IF42: ; preds = %IF39 %111 = fmul float %31, %29 %112 = fmul float %111, 5.000000e-01 %113 = fsub float -0.000000e+00, %112 %114 = fadd float 1.000000e+00, %113 br label %ENDIF41 ELSE43: ; preds = %IF39 %115 = fcmp olt float %56, 0.000000e+00 %116 = sext i1 %115 to i32 %117 = bitcast i32 %116 to float %118 = bitcast float %117 to i32 %119 = icmp ne i32 %118, 0 %. = select i1 %119, float 0.000000e+00, float %56 br label %ENDIF41 ENDIF41: ; preds = %ELSE43, %IF42 %temp12.2 = phi float [ %114, %IF42 ], [ %., %ELSE43 ] %120 = fcmp oge float %57, 1.000000e+00 %121 = sext i1 %120 to i32 %122 = bitcast i32 %121 to float %123 = bitcast float %122 to i32 %124 = icmp ne i32 %123, 0 br i1 %124, label %IF48, label %ELSE49 IF48: ; preds = %ENDIF41 %125 = fmul float %32, %30 %126 = fmul float %125, 5.000000e-01 %127 = fsub float -0.000000e+00, %126 %128 = fadd float 1.000000e+00, %127 br label %ENDIF47 ELSE49: ; preds = %ENDIF41 %129 = fcmp olt float %57, 0.000000e+00 %130 = sext i1 %129 to i32 %131 = bitcast i32 %130 to float %132 = bitcast float %131 to i32 %133 = icmp ne i32 %132, 0 %.71 = select i1 %133, float 0.000000e+00, float %57 br label %ENDIF47 ENDIF47: ; preds = %ELSE49, %IF48 %temp13.2 = phi float [ %128, %IF48 ], [ %.71, %ELSE49 ] %134 = fdiv float 1.000000e+00, %29 %135 = fdiv float 1.000000e+00, %30 %136 = fmul float %temp12.2, %134 %137 = fmul float %temp13.2, %135 br label %ENDIF32 IF54: ; preds = %ELSE40 %138 = call float @floor(float %56) %139 = call float @fabs(float %138) %140 = fmul float %139, 5.000000e-01 %141 = call float @floor(float %140) %142 = fmul float 2.000000e+00, %141 %143 = fsub float -0.000000e+00, %142 %144 = fadd float %139, %143 %145 = fsub float -0.000000e+00, %144 %146 = fadd float 1.000000e+00, %145 %147 = fcmp olt float %146, 0x3F50624DE0000000 %148 = sext i1 %147 to i32 %149 = bitcast i32 %148 to float %150 = bitcast float %149 to i32 %151 = icmp ne i32 %150, 0 %152 = call float @llvm.AMDIL.fraction.(float %56) br i1 %151, label %IF57, label %ELSE58 IF57: ; preds = %IF54 %153 = fsub float -0.000000e+00, %152 %154 = fadd float 1.000000e+00, %153 %155 = fdiv float 1.000000e+00, %29 %156 = fmul float %154, %155 %157 = fsub float -0.000000e+00, %156 %158 = fadd float 2.000000e+00, %157 br label %ENDIF56 ELSE58: ; preds = %IF54 %159 = fdiv float 1.000000e+00, %29 %160 = fmul float %152, %159 br label %ENDIF56 ENDIF56: ; preds = %ELSE58, %IF57 %temp12.5 = phi float [ %158, %IF57 ], [ %160, %ELSE58 ] %161 = call float @floor(float %57) %162 = call float @fabs(float %161) %163 = fmul float %162, 5.000000e-01 %164 = call float @floor(float %163) %165 = fmul float 2.000000e+00, %164 %166 = fsub float -0.000000e+00, %165 %167 = fadd float %162, %166 %168 = fsub float -0.000000e+00, %167 %169 = fadd float 1.000000e+00, %168 %170 = fcmp olt float %169, 0x3F50624DE0000000 %171 = sext i1 %170 to i32 %172 = bitcast i32 %171 to float %173 = bitcast float %172 to i32 %174 = icmp ne i32 %173, 0 %175 = call float @llvm.AMDIL.fraction.(float %57) br i1 %174, label %IF60, label %ELSE61 IF60: ; preds = %ENDIF56 %176 = fsub float -0.000000e+00, %175 %177 = fadd float 1.000000e+00, %176 %178 = fdiv float 1.000000e+00, %30 %179 = fmul float %177, %178 %180 = fsub float -0.000000e+00, %179 %181 = fadd float 2.000000e+00, %180 br label %ENDIF32 ELSE61: ; preds = %ENDIF56 %182 = fdiv float 1.000000e+00, %30 %183 = fmul float %175, %182 br label %ENDIF32 IF63: ; preds = %ENDIF32 %184 = fcmp oge float %temp16.0, 0.000000e+00 %185 = sext i1 %184 to i32 %186 = bitcast i32 %185 to float %187 = fcmp olt float %temp16.0, 1.000000e+00 %188 = sext i1 %187 to i32 %189 = bitcast i32 %188 to float %190 = bitcast float %186 to i32 %191 = bitcast float %189 to i32 %192 = and i32 %190, %191 %193 = bitcast i32 %192 to float %194 = fcmp oge float %temp17.0, 0.000000e+00 %195 = sext i1 %194 to i32 %196 = bitcast i32 %195 to float %197 = bitcast float %193 to i32 %198 = bitcast float %196 to i32 %199 = and i32 %197, %198 %200 = bitcast i32 %199 to float %201 = fcmp olt float %temp17.0, 1.000000e+00 %202 = sext i1 %201 to i32 %203 = bitcast i32 %202 to float %204 = bitcast float %200 to i32 %205 = bitcast float %203 to i32 %206 = and i32 %204, %205 %207 = bitcast i32 %206 to float %208 = bitcast float %207 to i32 %209 = xor i32 %208, -1 %210 = bitcast i32 %209 to float %211 = bitcast float %210 to i32 %212 = icmp ne i32 %211, 0 br i1 %212, label %ENDIF62, label %ELSE67 ENDIF62: ; preds = %ELSE67, %IF63, %ENDIF32 %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ] %temp8.0 = phi float [ %temp16.0, %ENDIF32 ], [ %219, %ELSE67 ], [ %temp16.0, %IF63 ] %temp9.0 = phi float [ %temp17.0, %ENDIF32 ], [ %220, %ELSE67 ], [ %temp17.0, %IF63 ] %213 = bitcast float %temp4.0 to i32 %214 = icmp ne i32 %213, 0 br i1 %214, label %IF69, label %ENDIF ELSE67: ; preds = %IF63 %215 = call float @llvm.AMDIL.fraction.(float %temp16.0) %216 = call float @llvm.AMDIL.fraction.(float %temp17.0) %217 = fdiv float 1.000000e+00, %29 %218 = fdiv float 1.000000e+00, %30 %219 = fmul float %215, %217 %220 = fmul float %216, %218 br label %ENDIF62 IF69: ; preds = %ENDIF62 %221 = bitcast float %temp8.0 to i32 %222 = bitcast float %temp9.0 to i32 %223 = insertelement <2 x i32> undef, i32 %221, i32 0 %224 = insertelement <2 x i32> %223, i32 %222, i32 1 %225 = bitcast <8 x i32> %34 to <32 x i8> %226 = bitcast <4 x i32> %36 to <16 x i8> %227 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %224, <32 x i8> %225, <16 x i8> %226, i32 2) %228 = extractelement <4 x float> %227, i32 3 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx4 s[24:27], s[2:3], 0x0 ; C08C0300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[24:27], 0x0 ; C2001900 s_load_dwordx4 s[20:23], s[4:5], 0x0 ; C08A0500 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_lt_i32_e64 s[2:3], s0, 10 ; D1020002 00011400 v_cndmask_b32_e64 v0, 0, -1, s[2:3] ; D2000000 00098280 v_cmp_eq_i32_e64 s[2:3], v0, 0 ; D1040002 00010100 s_and_saveexec_b64 s[2:3], s[2:3] ; BE822402 s_xor_b64 s[2:3], exec, s[2:3] ; 8982027E s_cbranch_execz BB0_8 ; BF880000 v_mov_b32_e32 v0, s0 ; 7E000200 s_buffer_load_dword s1, s[24:27], 0xc ; C200990C s_buffer_load_dword s4, s[24:27], 0xd ; C202190D v_add_i32_e32 v6, -10, v0 ; 4A0C00CA v_cmp_eq_i32_e64 s[6:7], v6, 0 ; D1040006 00010106 v_cndmask_b32_e64 v0, 0, -1, s[6:7] ; D2000000 00198280 v_cmp_eq_i32_e64 s[6:7], v0, 0 ; D1040006 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s1, v2 ; 10000401 v_mul_f32_e32 v1, s4, v3 ; 10020604 s_and_saveexec_b64 s[6:7], s[6:7] ; BE862406 s_xor_b64 s[6:7], exec, s[6:7] ; 8986067E s_cbranch_execz BB0_9 ; BF880000 v_cmp_eq_i32_e64 s[8:9], v6, 1 ; D1040008 00010306 v_cndmask_b32_e64 v4, 0, -1, s[8:9] ; D2000004 00218280 v_cmp_eq_i32_e64 s[8:9], v4, 0 ; D1040008 00010104 s_waitcnt expcnt(0) ; BF8C070F s_and_saveexec_b64 s[8:9], s[8:9] ; BE882408 s_xor_b64 s[8:9], exec, s[8:9] ; 8988087E s_cbranch_execz BB0_10 ; BF880000 v_cmp_eq_i32_e64 s[10:11], v6, 2 ; D104000A 00010506 v_cndmask_b32_e64 v4, 0, -1, s[10:11] ; D2000004 00298280 v_cmp_eq_i32_e64 s[10:11], v4, 0 ; D104000A 00010104 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_13 ; BF880000 v_cmp_eq_i32_e64 s[28:29], v6, 3 ; D104001C 00010706 v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_ne_i32_e64 s[28:29], v4, 0 ; D10A001C 00010104 v_mov_b32_e32 v5, v1 ; 7E0A0301 v_mov_b32_e32 v4, v0 ; 7E080300 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E s_cbranch_execz BB0_29 ; BF880000 v_floor_f32_e32 v4, v0 ; 7E084900 v_mul_f32_e64 v5, 0.5, |v4| ; D2100205 000208F0 v_floor_f32_e32 v5, v5 ; 7E0A4905 v_mad_f32 v4, 2.0, v5, -|v4| ; D2820404 84120AF4 v_add_f32_e32 v4, 1.0, v4 ; 060808F2 v_mov_b32_e32 v5, 0x3a83126f ; 7E0A02FF 3A83126F v_cmp_lt_f32_e32 vcc, v4, v5 ; 7C020B04 v_cndmask_b32_e64 v4, 0, -1, vcc ; D2000004 01A98280 v_fract_f32_e32 v5, v0 ; 7E0A4100 v_cmp_eq_i32_e64 s[30:31], v4, 0 ; D104001E 00010104 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E v_rcp_f32_e32 v4, s1 ; 7E085401 v_mul_f32_e32 v4, v4, v5 ; 10080B04 s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E v_rcp_f32_e32 v4, s1 ; 7E085401 v_subrev_f32_e32 v5, 1.0, v5 ; 0A0A0AF2 v_mad_f32 v4, v5, v4, 2.0 ; D2820004 03D20905 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E v_floor_f32_e32 v5, v1 ; 7E0A4901 v_mul_f32_e64 v6, 0.5, |v5| ; D2100206 00020AF0 v_floor_f32_e32 v6, v6 ; 7E0C4906 v_mad_f32 v5, 2.0, v6, -|v5| ; D2820405 84160CF4 v_add_f32_e32 v5, 1.0, v5 ; 060A0AF2 v_mov_b32_e32 v6, 0x3a83126f ; 7E0C02FF 3A83126F v_cmp_lt_f32_e32 vcc, v5, v6 ; 7C020D05 v_cndmask_b32_e64 v5, 0, -1, vcc ; D2000805 01A98280 v_fract_f32_e32 v6, v1 ; 7E0C4101 v_cmp_eq_i32_e64 s[30:31], v5, 0 ; D104001E 00010105 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E v_rcp_f32_e32 v5, s4 ; 7E0A5404 v_mul_f32_e32 v5, v5, v6 ; 100A0D05 s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E v_rcp_f32_e32 v5, s4 ; 7E0A5404 v_subrev_f32_e32 v6, 1.0, v6 ; 0A0C0CF2 v_mad_f32 v5, v6, v5, 2.0 ; D2820005 03D20B06 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E s_or_b64 exec, exec, s[28:29] ; 88FE1C7E s_or_saveexec_b64 s[10:11], s[10:11] ; BE8A250A s_xor_b64 exec, exec, s[10:11] ; 89FE0A7E s_cbranch_execz BB0_19 ; BF880000 v_cmp_ge_f32_e64 s[28:29], v0, 1.0 ; D00C001C 0001E500 v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_eq_i32_e64 s[28:29], v4, 0 ; D104001C 00010104 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_cmp_lt_f32_e64 s[30:31], v0, 0 ; D002001E 00010100 v_cndmask_b32_e64 v4, 0, -1, s[30:31] ; D2000004 00798280 v_cmp_ne_i32_e64 s[30:31], v4, 0 ; D10A001E 00010104 v_cndmask_b32_e64 v4, v0, 0, s[30:31] ; D2000004 00790100 s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E s_buffer_load_dword s5, s[24:27], 0xe ; C202990E s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s5 ; 7E080205 v_mul_f32_e32 v4, s1, v4 ; 10080801 v_mad_f32 v4, -0.5, v4, 1.0 ; D2820004 03CA08F1 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_cmp_ge_f32_e64 s[28:29], v1, 1.0 ; D00C001C 0001E501 v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_cmp_eq_i32_e64 s[28:29], v5, 0 ; D104001C 00010105 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_cmp_lt_f32_e64 s[30:31], v1, 0 ; D002001E 00010101 v_cndmask_b32_e64 v5, 0, -1, s[30:31] ; D2000805 00798280 v_cmp_ne_i32_e64 s[30:31], v5, 0 ; D10A001E 00010105 v_cndmask_b32_e64 v5, v1, 0, s[30:31] ; D2000805 08790101 s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E s_buffer_load_dword s5, s[24:27], 0xf ; C202990F s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v5, s5 ; 7E0A0205 v_mul_f32_e32 v5, s4, v5 ; 100A0A04 v_mad_f32 v5, -0.5, v5, 1.0 ; D2820005 03CA0AF1 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_rcp_f32_e32 v6, s1 ; 7E0C5401 v_rcp_f32_e32 v7, s4 ; 7E0E5404 v_mul_f32_e32 v4, v6, v4 ; 10080906 v_mul_f32_e32 v5, v7, v5 ; 100A0B07 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E s_or_saveexec_b64 s[8:9], s[8:9] ; BE882508 s_xor_b64 exec, exec, s[8:9] ; 89FE087E v_fract_f32_e32 v4, v0 ; 7E084100 v_fract_f32_e32 v5, v1 ; 7E0A4101 v_rcp_f32_e32 v6, s1 ; 7E0C5401 v_rcp_f32_e32 v7, s4 ; 7E0E5404 v_floor_f32_e32 v0, v0 ; 7E004900 v_floor_f32_e32 v1, v1 ; 7E024901 v_mad_f32 v4, v4, v6, v0 ; D2820004 04020D04 v_mad_f32 v5, v5, v7, v1 ; D2820005 04060F05 s_or_b64 exec, exec, s[8:9] ; 88FE087E v_mov_b32_e32 v0, v4 ; 7E000304 v_mov_b32_e32 v1, v5 ; 7E020305 s_or_b64 exec, exec, s[6:7] ; 88FE067E v_cmp_eq_i32_e64 s[6:7], s0, 10 ; D1040006 00011400 v_cndmask_b32_e64 v4, 0, -1, s[6:7] ; D2000004 00198280 v_cmp_ne_i32_e64 s[6:7], v4, 0 ; D10A0006 00010104 v_mov_b32_e32 v4, -1 ; 7E0802C1 s_and_saveexec_b64 s[6:7], s[6:7] ; BE862406 s_xor_b64 s[6:7], exec, s[6:7] ; 8986067E s_cbranch_execz BB0_36 ; BF880000 v_mov_b32_e32 v4, 0 ; 7E080280 v_cmp_ge_f32_e64 s[8:9], v0, 0 ; D00C0008 00010100 v_cmp_lt_f32_e64 s[10:11], v0, 1.0 ; D002000A 0001E500 s_and_b64 s[8:9], s[8:9], s[10:11] ; 87880A08 v_cndmask_b32_e64 v5, 0, -1, s[8:9] ; D2000805 00218280 v_cmp_ge_f32_e64 s[8:9], v1, 0 ; D00C0008 00010101 v_cndmask_b32_e64 v6, 0, -1, s[8:9] ; D2000006 00218280 v_and_b32_e32 v5, v6, v5 ; 360A0B06 v_cmp_lt_f32_e64 s[8:9], v1, 1.0 ; D0020008 0001E501 v_cndmask_b32_e64 v6, 0, -1, s[8:9] ; D2000006 00218280 v_and_b32_e32 v5, v6, v5 ; 360A0B06 v_cmp_eq_i32_e64 s[8:9], v5, -1 ; D1040008 00018305 s_and_saveexec_b64 s[8:9], s[8:9] ; BE882408 s_xor_b64 s[8:9], exec, s[8:9] ; 8988087E v_fract_f32_e32 v0, v0 ; 7E004100 v_rcp_f32_e32 v4, s1 ; 7E085401 v_rcp_f32_e32 v5, s4 ; 7E0A5404 v_fract_f32_e32 v1, v1 ; 7E024101 v_mul_f32_e32 v0, v4, v0 ; 10000104 v_mul_f32_e32 v1, v5, v1 ; 10020305 v_mov_b32_e32 v4, -1 ; 7E0802C1 s_or_b64 exec, exec, s[8:9] ; 88FE087E s_or_b64 exec, exec, s[6:7] ; 88FE067E v_cmp_ne_i32_e64 s[4:5], v4, 0 ; D10A0004 00010104 v_mov_b32_e32 v4, 0 ; 7E080280 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842404 s_xor_b64 s[4:5], exec, s[4:5] ; 8984047E image_sample v4, 8, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[12:19], s[20:23] ; F0800800 00A30400 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[4:5] ; 88FE047E s_or_saveexec_b64 s[2:3], s[2:3] ; BE822502 s_buffer_load_dword s1, s[24:27], 0x4 ; C2009904 s_buffer_load_dword s4, s[24:27], 0x5 ; C2021905 s_buffer_load_dword s5, s[24:27], 0x6 ; C2029906 s_buffer_load_dword s6, s[24:27], 0x7 ; C2031907 s_waitcnt lgkmcnt(0) ; BF8C007F s_xor_b64 exec, exec, s[2:3] ; 89FE027E image_sample v4, 8, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[20:23] ; F0800800 00A30402 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[2:3] ; 88FE027E v_mul_f32_e32 v0, s1, v4 ; 10000801 v_mul_f32_e32 v1, s4, v4 ; 10020804 v_mul_f32_e32 v2, s5, v4 ; 10040805 v_mul_f32_e32 v3, s6, v4 ; 10060806 v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyxx 1: MOV OUT[1], TEMP[0] 2: MOV OUT[0], IN[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 v_mov_b32_e32 v0, 0 ; 7E000280 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v0, v0 ; F800020F 00000605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..2] DCL TEMP[0..2], LOCAL IMM[0] INT32 {0, 3, 1, 2} IMM[1] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: USEQ TEMP[0].x, CONST[1].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: USNE TEMP[0].x, CONST[2].xxxx, IMM[0].xxxx 3: USNE TEMP[1].x, CONST[2].xxxx, IMM[0].yyyy 4: AND TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx 5: UIF TEMP[0].xxxx :0 6: MOV TEMP[0].w, IMM[1].xxxx 7: MOV TEMP[1].xy, IN[0].xyyy 8: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D 9: MOV TEMP[0].xyz, TEMP[1].zyxz 10: MOV TEMP[0], TEMP[0] 11: ELSE :0 12: MOV TEMP[1].w, IMM[1].xxxx 13: MOV TEMP[2].xy, IN[0].xyyy 14: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D 15: MOV TEMP[1].xyz, TEMP[2].xyzx 16: MOV TEMP[0], TEMP[1] 17: ENDIF 18: ELSE :0 19: USEQ TEMP[1].x, CONST[2].xxxx, IMM[0].zzzz 20: UIF TEMP[1].xxxx :0 21: MOV TEMP[1].x, IMM[1].xxxx 22: MOV TEMP[2].xy, IN[0].xyyy 23: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D 24: MOV TEMP[1].yzw, TEMP[2].yxyz 25: MOV TEMP[0], TEMP[1] 26: ELSE :0 27: USEQ TEMP[1].x, CONST[2].xxxx, IMM[0].xxxx 28: UIF TEMP[1].xxxx :0 29: MOV TEMP[1].x, IMM[1].xxxx 30: MOV TEMP[2].xy, IN[0].xyyy 31: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D 32: MOV TEMP[1].yzw, TEMP[2].yzyx 33: MOV TEMP[0], TEMP[1] 34: ELSE :0 35: USEQ TEMP[1].x, CONST[2].xxxx, IMM[0].wwww 36: UIF TEMP[1].xxxx :0 37: MOV TEMP[1].w, IMM[1].xxxx 38: MOV TEMP[2].xy, IN[0].xyyy 39: TEX TEMP[2].yzw, TEMP[2], SAMP[0], 2D 40: MOV TEMP[1].xyz, TEMP[2].yzwy 41: MOV TEMP[0], TEMP[1] 42: ELSE :0 43: USEQ TEMP[1].x, CONST[2].xxxx, IMM[0].yyyy 44: UIF TEMP[1].xxxx :0 45: MOV TEMP[1].w, IMM[1].xxxx 46: MOV TEMP[2].xy, IN[0].xyyy 47: TEX TEMP[2].yzw, TEMP[2], SAMP[0], 2D 48: MOV TEMP[1].xyz, TEMP[2].wzyw 49: MOV TEMP[0], TEMP[1] 50: ENDIF 51: ENDIF 52: ENDIF 53: ENDIF 54: ENDIF 55: MOV OUT[0], TEMP[0] 56: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %26 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %27 = load <8 x i32> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %29 = load <4 x i32> addrspace(2)* %28, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %32 = bitcast float %24 to i32 %33 = icmp eq i32 %32, 0 %34 = sext i1 %33 to i32 %35 = bitcast i32 %34 to float %36 = bitcast float %35 to i32 %37 = icmp ne i32 %36, 0 %38 = bitcast float %25 to i32 br i1 %37, label %IF, label %ELSE IF: ; preds = %main_body %39 = icmp ne i32 %38, 0 %40 = sext i1 %39 to i32 %41 = bitcast i32 %40 to float %42 = bitcast float %25 to i32 %43 = icmp ne i32 %42, 3 %44 = sext i1 %43 to i32 %45 = bitcast i32 %44 to float %46 = bitcast float %41 to i32 %47 = bitcast float %45 to i32 %48 = and i32 %46, %47 %49 = bitcast i32 %48 to float %50 = bitcast float %49 to i32 %51 = icmp ne i32 %50, 0 %52 = bitcast float %30 to i32 %53 = bitcast float %31 to i32 %54 = insertelement <2 x i32> undef, i32 %52, i32 0 %55 = insertelement <2 x i32> %54, i32 %53, i32 1 %56 = bitcast <8 x i32> %27 to <32 x i8> %57 = bitcast <4 x i32> %29 to <16 x i8> %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %55, <32 x i8> %56, <16 x i8> %57, i32 2) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %. = select i1 %51, float %61, float %59 %.27 = select i1 %51, float %59, float %61 br label %ENDIF ELSE: ; preds = %main_body %62 = icmp eq i32 %38, 1 %63 = sext i1 %62 to i32 %64 = bitcast i32 %63 to float %65 = bitcast float %64 to i32 %66 = icmp ne i32 %65, 0 br i1 %66, label %IF16, label %ELSE17 ENDIF: ; preds = %IF25, %ELSE23, %IF22, %IF19, %IF16, %IF %temp.0 = phi float [ %., %IF ], [ 1.000000e+00, %IF16 ], [ 1.000000e+00, %IF19 ], [ %110, %IF22 ], [ %128, %IF25 ], [ %35, %ELSE23 ] %temp1.0 = phi float [ %60, %IF ], [ %78, %IF16 ], [ %96, %IF19 ], [ %111, %IF22 ], [ %127, %IF25 ], [ 0.000000e+00, %ELSE23 ] %temp2.0 = phi float [ %.27, %IF ], [ %79, %IF16 ], [ %95, %IF19 ], [ %112, %IF22 ], [ %126, %IF25 ], [ 0.000000e+00, %ELSE23 ] %temp3.0 = phi float [ 1.000000e+00, %IF ], [ %80, %IF16 ], [ %94, %IF19 ], [ 1.000000e+00, %IF22 ], [ 1.000000e+00, %IF25 ], [ 0.000000e+00, %ELSE23 ] %67 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0) %68 = bitcast i32 %67 to float %69 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0) %70 = bitcast i32 %69 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %68, float %70, float %68, float %70) ret void IF16: ; preds = %ELSE %71 = bitcast float %30 to i32 %72 = bitcast float %31 to i32 %73 = insertelement <2 x i32> undef, i32 %71, i32 0 %74 = insertelement <2 x i32> %73, i32 %72, i32 1 %75 = bitcast <8 x i32> %27 to <32 x i8> %76 = bitcast <4 x i32> %29 to <16 x i8> %77 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %75, <16 x i8> %76, i32 2) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = extractelement <4 x float> %77, i32 2 br label %ENDIF ELSE17: ; preds = %ELSE %81 = bitcast float %25 to i32 %82 = icmp eq i32 %81, 0 %83 = sext i1 %82 to i32 %84 = bitcast i32 %83 to float %85 = bitcast float %84 to i32 %86 = icmp ne i32 %85, 0 br i1 %86, label %IF19, label %ELSE20 IF19: ; preds = %ELSE17 %87 = bitcast float %30 to i32 %88 = bitcast float %31 to i32 %89 = insertelement <2 x i32> undef, i32 %87, i32 0 %90 = insertelement <2 x i32> %89, i32 %88, i32 1 %91 = bitcast <8 x i32> %27 to <32 x i8> %92 = bitcast <4 x i32> %29 to <16 x i8> %93 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %90, <32 x i8> %91, <16 x i8> %92, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = extractelement <4 x float> %93, i32 1 %96 = extractelement <4 x float> %93, i32 2 br label %ENDIF ELSE20: ; preds = %ELSE17 %97 = bitcast float %25 to i32 %98 = icmp eq i32 %97, 2 %99 = sext i1 %98 to i32 %100 = bitcast i32 %99 to float %101 = bitcast float %100 to i32 %102 = icmp ne i32 %101, 0 br i1 %102, label %IF22, label %ELSE23 IF22: ; preds = %ELSE20 %103 = bitcast float %30 to i32 %104 = bitcast float %31 to i32 %105 = insertelement <2 x i32> undef, i32 %103, i32 0 %106 = insertelement <2 x i32> %105, i32 %104, i32 1 %107 = bitcast <8 x i32> %27 to <32 x i8> %108 = bitcast <4 x i32> %29 to <16 x i8> %109 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %106, <32 x i8> %107, <16 x i8> %108, i32 2) %110 = extractelement <4 x float> %109, i32 1 %111 = extractelement <4 x float> %109, i32 2 %112 = extractelement <4 x float> %109, i32 3 br label %ENDIF ELSE23: ; preds = %ELSE20 %113 = bitcast float %25 to i32 %114 = icmp eq i32 %113, 3 %115 = sext i1 %114 to i32 %116 = bitcast i32 %115 to float %117 = bitcast float %116 to i32 %118 = icmp ne i32 %117, 0 br i1 %118, label %IF25, label %ENDIF IF25: ; preds = %ELSE23 %119 = bitcast float %30 to i32 %120 = bitcast float %31 to i32 %121 = insertelement <2 x i32> undef, i32 %119, i32 0 %122 = insertelement <2 x i32> %121, i32 %120, i32 1 %123 = bitcast <8 x i32> %27 to <32 x i8> %124 = bitcast <4 x i32> %29 to <16 x i8> %125 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %122, <32 x i8> %123, <16 x i8> %124, i32 2) %126 = extractelement <4 x float> %125, i32 1 %127 = extractelement <4 x float> %125, i32 2 %128 = extractelement <4 x float> %125, i32 3 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x4 ; C2040104 s_buffer_load_dword s0, s[0:3], 0x8 ; C2000108 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C0C60700 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C0820500 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_eq_i32_e64 s[2:3], s8, 0 ; D1040002 00010008 v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; D2000807 00098280 v_cmp_eq_i32_e64 s[2:3], v7, 0 ; D1040002 00010107 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 s_and_saveexec_b64 s[2:3], s[2:3] ; BE822402 s_xor_b64 s[2:3], exec, s[2:3] ; 8982027E s_cbranch_execz BB0_1 ; BF880000 v_cmp_eq_i32_e64 s[8:9], s0, 1 ; D1040008 00010200 v_cndmask_b32_e64 v0, 0, -1, s[8:9] ; D2000000 00218280 v_cmp_eq_i32_e64 s[8:9], v0, 0 ; D1040008 00010100 s_and_saveexec_b64 s[8:9], s[8:9] ; BE882408 s_xor_b64 s[8:9], exec, s[8:9] ; 8988087E s_cbranch_execz BB0_9 ; BF880000 v_cmp_eq_i32_e64 s[10:11], s0, 0 ; D104000A 00010000 v_cndmask_b32_e64 v0, 0, -1, s[10:11] ; D2000000 00298280 v_cmp_eq_i32_e64 s[10:11], v0, 0 ; D104000A 00010100 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_12 ; BF880000 v_cmp_eq_i32_e64 s[20:21], s0, 2 ; D1040014 00010400 v_cndmask_b32_e64 v0, 0, -1, s[20:21] ; D2000000 00518280 v_cmp_eq_i32_e64 s[20:21], v0, 0 ; D1040014 00010100 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E s_cbranch_execz BB0_15 ; BF880000 v_mov_b32_e32 v10, 0 ; 7E140280 v_mov_b32_e32 v9, v10 ; 7E12030A v_cmp_eq_i32_e64 s[22:23], s0, 3 ; D1040016 00010600 v_cndmask_b32_e64 v0, 0, -1, s[22:23] ; D2000000 00598280 v_cmp_ne_i32_e64 s[22:23], v0, 0 ; D10A0016 00010100 v_mov_b32_e32 v12, v10 ; 7E18030A s_and_saveexec_b64 s[22:23], s[22:23] ; BE962416 s_xor_b64 s[22:23], exec, s[22:23] ; 8996167E image_sample v[11:13], 14, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800E00 00230B02 v_mov_b32_e32 v10, 1.0 ; 7E1402F2 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v9, v11 ; 7E12030B v_mov_b32_e32 v7, v13 ; 7E0E030D s_or_b64 exec, exec, s[22:23] ; 88FE167E s_or_saveexec_b64 s[20:21], s[20:21] ; BE942514 s_xor_b64 exec, exec, s[20:21] ; 89FE147E image_sample v[7:9], 14, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800E00 00230702 v_mov_b32_e32 v10, 1.0 ; 7E1402F2 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v12, v8 ; 7E180308 s_or_b64 exec, exec, s[20:21] ; 88FE147E s_or_saveexec_b64 s[10:11], s[10:11] ; BE8A250A s_xor_b64 exec, exec, s[10:11] ; 89FE0A7E image_sample v[10:12], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800700 00230A02 v_mov_b32_e32 v7, 1.0 ; 7E0E02F2 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v9, v11 ; 7E12030B s_or_b64 exec, exec, s[10:11] ; 88FE0A7E s_or_saveexec_b64 s[8:9], s[8:9] ; BE882508 s_waitcnt expcnt(0) ; BF8C070F s_xor_b64 exec, exec, s[8:9] ; 89FE087E image_sample v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800700 00230802 v_mov_b32_e32 v7, 1.0 ; 7E0E02F2 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v12, v8 ; 7E180308 s_or_b64 exec, exec, s[8:9] ; 88FE087E s_or_saveexec_b64 s[2:3], s[2:3] ; BE822502 s_xor_b64 exec, exec, s[2:3] ; 89FE027E v_cmp_ne_i32_e64 s[8:9], s0, 0 ; D10A0008 00010000 v_cmp_ne_i32_e64 s[10:11], s0, 3 ; D10A000A 00010600 s_and_b64 s[8:9], s[8:9], s[10:11] ; 87880A08 image_sample v[11:13], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800700 00230B02 s_waitcnt vmcnt(0) ; BF8C0770 v_cndmask_b32_e64 v7, v11, v13, s[8:9] ; D2000807 18221B0B v_cndmask_b32_e64 v9, v13, v11, s[8:9] ; D2000809 0822170D v_mov_b32_e32 v10, 1.0 ; 7E1402F2 s_or_b64 exec, exec, s[2:3] ; 88FE027E v_cvt_pkrtz_f16_f32_e32 v0, v7, v12 ; 5E001907 v_cvt_pkrtz_f16_f32_e32 v1, v9, v10 ; 5E021509 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[0].zw, IN[1].yyxy 2: MOV OUT[1], TEMP[0] 3: MOV OUT[0], IN[0] 4: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0 %27 = add i32 %5, %7 %28 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %26, i32 0, i32 %27) %29 = extractelement <4 x float> %28, i32 0 %30 = extractelement <4 x float> %28, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %29, float %30, float %23, float %24) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 s_load_dwordx4 s[12:15], s[8:9], 0x8 ; C0860908 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[7:10], v0, s[12:15], 0 idxen ; E00C2000 80030700 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v7, v8, v5, v6 ; F800020F 06050807 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0..1] DCL CONST[3] DCL CONST[5] DCL TEMP[0..9], LOCAL IMM[0] INT32 {10, -10, 0, 1} IMM[1] FLT32 { 1.0000, 0.5000, 0.0000, 2.0000} IMM[2] UINT32 {4294967295, 0, 0, 0} IMM[3] INT32 {2, 3, 0, 0} IMM[4] FLT32 { 0.0010, 0.0000, 0.0000, 0.0000} 0: ISLT TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: MOV TEMP[0].w, IMM[1].xxxx 3: MOV TEMP[1].xy, IN[0].zwww 4: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D 5: MOV TEMP[0].xyz, TEMP[1].xyzx 6: MOV TEMP[0], TEMP[0] 7: ELSE :0 8: MOV TEMP[2].x, IMM[2].xxxx 9: UADD TEMP[3].x, CONST[0].xxxx, IMM[0].yyyy 10: MUL TEMP[4].xy, IN[0].zwww, CONST[3].xyyy 11: USEQ TEMP[5].x, TEMP[3].xxxx, IMM[0].zzzz 12: UIF TEMP[5].xxxx :0 13: MOV TEMP[5].xy, TEMP[4].xyxx 14: ELSE :0 15: USEQ TEMP[6].x, TEMP[3].xxxx, IMM[0].wwww 16: UIF TEMP[6].xxxx :0 17: FRC TEMP[6].xy, TEMP[4].xyyy 18: RCP TEMP[7].x, CONST[3].xxxx 19: RCP TEMP[7].y, CONST[3].yyyy 20: FLR TEMP[8].xy, TEMP[4].xyyy 21: MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[8].xyyy 22: ELSE :0 23: USEQ TEMP[6].x, TEMP[3].xxxx, IMM[3].xxxx 24: UIF TEMP[6].xxxx :0 25: FSGE TEMP[6].x, TEMP[4].xxxx, IMM[1].xxxx 26: UIF TEMP[6].xxxx :0 27: MUL TEMP[6].x, CONST[3].zzzz, CONST[3].xxxx 28: MUL TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy 29: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[6].xxxx 30: ELSE :0 31: FSLT TEMP[6].x, TEMP[4].xxxx, IMM[1].zzzz 32: UIF TEMP[6].xxxx :0 33: MOV TEMP[4].x, IMM[1].zzzz 34: ENDIF 35: ENDIF 36: FSGE TEMP[6].x, TEMP[4].yyyy, IMM[1].xxxx 37: UIF TEMP[6].xxxx :0 38: MUL TEMP[6].x, CONST[3].wwww, CONST[3].yyyy 39: MUL TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy 40: ADD TEMP[6].x, IMM[1].xxxx, -TEMP[6].xxxx 41: MOV TEMP[4].y, TEMP[6].xxxx 42: ELSE :0 43: FSLT TEMP[6].x, TEMP[4].yyyy, IMM[1].zzzz 44: UIF TEMP[6].xxxx :0 45: MOV TEMP[4].y, IMM[1].zzzz 46: ENDIF 47: ENDIF 48: RCP TEMP[6].x, CONST[3].xxxx 49: RCP TEMP[6].y, CONST[3].yyyy 50: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[6].xyyy 51: ELSE :0 52: USEQ TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy 53: UIF TEMP[3].xxxx :0 54: FLR TEMP[3].x, TEMP[4].xxxx 55: ABS TEMP[3].x, TEMP[3].xxxx 56: MUL TEMP[6].x, TEMP[3].xxxx, IMM[1].yyyy 57: FLR TEMP[6].x, TEMP[6].xxxx 58: MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx 59: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[6].xxxx 60: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 61: FSLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx 62: UIF TEMP[3].xxxx :0 63: FRC TEMP[3].x, TEMP[4].xxxx 64: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 65: RCP TEMP[6].x, CONST[3].xxxx 66: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 67: ADD TEMP[4].x, IMM[1].wwww, -TEMP[3].xxxx 68: ELSE :0 69: FRC TEMP[3].x, TEMP[4].xxxx 70: RCP TEMP[6].x, CONST[3].xxxx 71: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx 72: ENDIF 73: FLR TEMP[3].x, TEMP[4].yyyy 74: ABS TEMP[3].x, TEMP[3].xxxx 75: MUL TEMP[6].x, TEMP[3].xxxx, IMM[1].yyyy 76: FLR TEMP[6].x, TEMP[6].xxxx 77: MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx 78: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[6].xxxx 79: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 80: FSLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx 81: UIF TEMP[3].xxxx :0 82: FRC TEMP[3].x, TEMP[4].yyyy 83: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 84: RCP TEMP[6].x, CONST[3].yyyy 85: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 86: ADD TEMP[3].x, IMM[1].wwww, -TEMP[3].xxxx 87: MOV TEMP[4].y, TEMP[3].xxxx 88: ELSE :0 89: FRC TEMP[3].x, TEMP[4].yyyy 90: RCP TEMP[6].x, CONST[3].yyyy 91: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 92: MOV TEMP[4].y, TEMP[3].xxxx 93: ENDIF 94: ENDIF 95: ENDIF 96: ENDIF 97: MOV TEMP[5].xy, TEMP[4].xyxx 98: ENDIF 99: MOV TEMP[1].xy, TEMP[5].xyxx 100: USEQ TEMP[3].x, CONST[0].xxxx, IMM[0].xxxx 101: UIF TEMP[3].xxxx :0 102: FSGE TEMP[3].x, TEMP[5].xxxx, IMM[1].zzzz 103: FSLT TEMP[4].x, TEMP[5].xxxx, IMM[1].xxxx 104: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 105: FSGE TEMP[4].x, TEMP[5].yyyy, IMM[1].zzzz 106: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 107: FSLT TEMP[4].x, TEMP[5].yyyy, IMM[1].xxxx 108: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 109: NOT TEMP[3].x, TEMP[3].xxxx 110: UIF TEMP[3].xxxx :0 111: MOV TEMP[3].xyz, IMM[1].zzzz 112: MOV TEMP[3].w, IMM[1].xxxx 113: MOV TEMP[3], TEMP[3] 114: MOV TEMP[2].x, IMM[2].yyyy 115: ELSE :0 116: FRC TEMP[4].xy, TEMP[5].xyyy 117: RCP TEMP[5].x, CONST[3].xxxx 118: RCP TEMP[5].y, CONST[3].yyyy 119: MUL TEMP[1].xy, TEMP[4].xyyy, TEMP[5].xyyy 120: ENDIF 121: ENDIF 122: UIF TEMP[2].xxxx :0 123: MOV TEMP[2].w, IMM[1].xxxx 124: MOV TEMP[1].xy, TEMP[1].xyyy 125: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D 126: MOV TEMP[2].xyz, TEMP[1].xyzx 127: MOV TEMP[3], TEMP[2] 128: ENDIF 129: MOV TEMP[0], TEMP[3] 130: ENDIF 131: ISLT TEMP[1].x, CONST[1].xxxx, IMM[0].xxxx 132: UIF TEMP[1].xxxx :0 133: MOV TEMP[1].xy, IN[0].xyyy 134: TEX TEMP[1], TEMP[1], SAMP[1], 2D 135: MOV TEMP[1].w, TEMP[1] 136: ELSE :0 137: MOV TEMP[3].x, IMM[2].xxxx 138: UADD TEMP[4].x, CONST[1].xxxx, IMM[0].yyyy 139: MUL TEMP[5].xy, IN[0].xyyy, CONST[5].xyyy 140: USEQ TEMP[6].x, TEMP[4].xxxx, IMM[0].zzzz 141: UIF TEMP[6].xxxx :0 142: MOV TEMP[6].xy, TEMP[5].xyxx 143: ELSE :0 144: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[0].wwww 145: UIF TEMP[7].xxxx :0 146: FRC TEMP[7].xy, TEMP[5].xyyy 147: RCP TEMP[8].x, CONST[5].xxxx 148: RCP TEMP[8].y, CONST[5].yyyy 149: FLR TEMP[9].xy, TEMP[5].xyyy 150: MAD TEMP[5].xy, TEMP[7].xyyy, TEMP[8].xyyy, TEMP[9].xyyy 151: ELSE :0 152: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[3].xxxx 153: UIF TEMP[7].xxxx :0 154: FSGE TEMP[7].x, TEMP[5].xxxx, IMM[1].xxxx 155: UIF TEMP[7].xxxx :0 156: MUL TEMP[7].x, CONST[5].zzzz, CONST[5].xxxx 157: MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 158: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[7].xxxx 159: ELSE :0 160: FSLT TEMP[7].x, TEMP[5].xxxx, IMM[1].zzzz 161: UIF TEMP[7].xxxx :0 162: MOV TEMP[5].x, IMM[1].zzzz 163: ENDIF 164: ENDIF 165: FSGE TEMP[7].x, TEMP[5].yyyy, IMM[1].xxxx 166: UIF TEMP[7].xxxx :0 167: MUL TEMP[7].x, CONST[5].wwww, CONST[5].yyyy 168: MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 169: ADD TEMP[7].x, IMM[1].xxxx, -TEMP[7].xxxx 170: MOV TEMP[5].y, TEMP[7].xxxx 171: ELSE :0 172: FSLT TEMP[7].x, TEMP[5].yyyy, IMM[1].zzzz 173: UIF TEMP[7].xxxx :0 174: MOV TEMP[5].y, IMM[1].zzzz 175: ENDIF 176: ENDIF 177: RCP TEMP[7].x, CONST[5].xxxx 178: RCP TEMP[7].y, CONST[5].yyyy 179: MUL TEMP[5].xy, TEMP[5].xyyy, TEMP[7].xyyy 180: ELSE :0 181: USEQ TEMP[4].x, TEMP[4].xxxx, IMM[3].yyyy 182: UIF TEMP[4].xxxx :0 183: FLR TEMP[4].x, TEMP[5].xxxx 184: ABS TEMP[4].x, TEMP[4].xxxx 185: MUL TEMP[7].x, TEMP[4].xxxx, IMM[1].yyyy 186: FLR TEMP[7].x, TEMP[7].xxxx 187: MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx 188: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 189: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 190: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 191: UIF TEMP[4].xxxx :0 192: FRC TEMP[4].x, TEMP[5].xxxx 193: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 194: RCP TEMP[7].x, CONST[5].xxxx 195: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 196: ADD TEMP[5].x, IMM[1].wwww, -TEMP[4].xxxx 197: ELSE :0 198: FRC TEMP[4].x, TEMP[5].xxxx 199: RCP TEMP[7].x, CONST[5].xxxx 200: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[7].xxxx 201: ENDIF 202: FLR TEMP[4].x, TEMP[5].yyyy 203: ABS TEMP[4].x, TEMP[4].xxxx 204: MUL TEMP[7].x, TEMP[4].xxxx, IMM[1].yyyy 205: FLR TEMP[7].x, TEMP[7].xxxx 206: MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx 207: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 208: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 209: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 210: UIF TEMP[4].xxxx :0 211: FRC TEMP[4].x, TEMP[5].yyyy 212: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 213: RCP TEMP[7].x, CONST[5].yyyy 214: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 215: ADD TEMP[4].x, IMM[1].wwww, -TEMP[4].xxxx 216: MOV TEMP[5].y, TEMP[4].xxxx 217: ELSE :0 218: FRC TEMP[4].x, TEMP[5].yyyy 219: RCP TEMP[7].x, CONST[5].yyyy 220: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 221: MOV TEMP[5].y, TEMP[4].xxxx 222: ENDIF 223: ENDIF 224: ENDIF 225: ENDIF 226: MOV TEMP[6].xy, TEMP[5].xyxx 227: ENDIF 228: MOV TEMP[2].xy, TEMP[6].xyxx 229: USEQ TEMP[4].x, CONST[1].xxxx, IMM[0].xxxx 230: UIF TEMP[4].xxxx :0 231: FSGE TEMP[4].x, TEMP[6].xxxx, IMM[1].zzzz 232: FSLT TEMP[5].x, TEMP[6].xxxx, IMM[1].xxxx 233: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 234: FSGE TEMP[5].x, TEMP[6].yyyy, IMM[1].zzzz 235: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 236: FSLT TEMP[5].x, TEMP[6].yyyy, IMM[1].xxxx 237: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 238: NOT TEMP[4].x, TEMP[4].xxxx 239: UIF TEMP[4].xxxx :0 240: MOV TEMP[4].xyz, IMM[1].zzzz 241: MOV TEMP[4].w, IMM[1].zzzz 242: MOV TEMP[4], TEMP[4] 243: MOV TEMP[3].x, IMM[2].yyyy 244: ELSE :0 245: FRC TEMP[5].xy, TEMP[6].xyyy 246: RCP TEMP[6].x, CONST[5].xxxx 247: RCP TEMP[6].y, CONST[5].yyyy 248: MUL TEMP[2].xy, TEMP[5].xyyy, TEMP[6].xyyy 249: ENDIF 250: ENDIF 251: UIF TEMP[3].xxxx :0 252: MOV TEMP[2].xy, TEMP[2].xyyy 253: TEX TEMP[2], TEMP[2], SAMP[1], 2D 254: MOV TEMP[4], TEMP[2] 255: ENDIF 256: MOV TEMP[1].w, TEMP[4] 257: ENDIF 258: MUL TEMP[0], TEMP[0], TEMP[1].wwww 259: MOV OUT[0], TEMP[0] 260: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 80) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 84) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 88) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 92) %34 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %35 = load <8 x i32> addrspace(2)* %34, !tbaa !0 %36 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %37 = load <4 x i32> addrspace(2)* %36, !tbaa !0 %38 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 1 %39 = load <8 x i32> addrspace(2)* %38, !tbaa !0 %40 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 1 %41 = load <4 x i32> addrspace(2)* %40, !tbaa !0 %42 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %43 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %44 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %45 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %46 = bitcast float %24 to i32 %47 = icmp slt i32 %46, 10 %48 = sext i1 %47 to i32 %49 = bitcast i32 %48 to float %50 = bitcast float %49 to i32 %51 = icmp ne i32 %50, 0 br i1 %51, label %IF, label %ELSE IF: ; preds = %main_body %52 = bitcast float %44 to i32 %53 = bitcast float %45 to i32 %54 = insertelement <2 x i32> undef, i32 %52, i32 0 %55 = insertelement <2 x i32> %54, i32 %53, i32 1 %56 = bitcast <8 x i32> %35 to <32 x i8> %57 = bitcast <4 x i32> %37 to <16 x i8> %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %55, <32 x i8> %56, <16 x i8> %57, i32 2) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 br label %ENDIF ELSE: ; preds = %main_body %62 = bitcast float %24 to i32 %63 = add i32 %62, -10 %64 = bitcast i32 %63 to float %65 = fmul float %44, %26 %66 = fmul float %45, %27 %67 = bitcast float %64 to i32 %68 = icmp eq i32 %67, 0 %69 = sext i1 %68 to i32 %70 = bitcast i32 %69 to float %71 = bitcast float %70 to i32 %72 = icmp ne i32 %71, 0 br i1 %72, label %ENDIF40, label %ELSE42 ENDIF: ; preds = %IF77, %ENDIF70, %IF %temp3.0 = phi float [ 1.000000e+00, %IF ], [ 1.000000e+00, %IF77 ], [ %temp15.0, %ENDIF70 ] %temp2.0 = phi float [ %61, %IF ], [ %237, %IF77 ], [ 0.000000e+00, %ENDIF70 ] %temp1.0 = phi float [ %60, %IF ], [ %236, %IF77 ], [ 0.000000e+00, %ENDIF70 ] %temp.0 = phi float [ %59, %IF ], [ %235, %IF77 ], [ %temp12.0, %ENDIF70 ] %73 = bitcast float %25 to i32 %74 = icmp slt i32 %73, 10 %75 = sext i1 %74 to i32 %76 = bitcast i32 %75 to float %77 = bitcast float %76 to i32 %78 = icmp ne i32 %77, 0 br i1 %78, label %IF80, label %ELSE81 ELSE42: ; preds = %ELSE %79 = bitcast float %64 to i32 %80 = icmp eq i32 %79, 1 %81 = sext i1 %80 to i32 %82 = bitcast i32 %81 to float %83 = bitcast float %82 to i32 %84 = icmp ne i32 %83, 0 br i1 %84, label %IF44, label %ELSE45 ENDIF40: ; preds = %IF68, %ELSE69, %ELSE48, %ENDIF55, %IF44, %ELSE %temp20.0 = phi float [ %65, %ELSE ], [ %98, %IF44 ], [ %143, %ENDIF55 ], [ %65, %ELSE48 ], [ %temp16.5, %ELSE69 ], [ %temp16.5, %IF68 ] %temp21.0 = phi float [ %66, %ELSE ], [ %100, %IF44 ], [ %144, %ENDIF55 ], [ %66, %ELSE48 ], [ %188, %IF68 ], [ %190, %ELSE69 ] %85 = bitcast float %24 to i32 %86 = icmp eq i32 %85, 10 %87 = sext i1 %86 to i32 %88 = bitcast i32 %87 to float %89 = bitcast float %88 to i32 %90 = icmp ne i32 %89, 0 br i1 %90, label %IF71, label %ENDIF70 IF44: ; preds = %ELSE42 %91 = call float @llvm.AMDIL.fraction.(float %65) %92 = call float @llvm.AMDIL.fraction.(float %66) %93 = fdiv float 1.000000e+00, %26 %94 = fdiv float 1.000000e+00, %27 %95 = call float @floor(float %65) %96 = call float @floor(float %66) %97 = fmul float %91, %93 %98 = fadd float %97, %95 %99 = fmul float %92, %94 %100 = fadd float %99, %96 br label %ENDIF40 ELSE45: ; preds = %ELSE42 %101 = bitcast float %64 to i32 %102 = icmp eq i32 %101, 2 %103 = sext i1 %102 to i32 %104 = bitcast i32 %103 to float %105 = bitcast float %104 to i32 %106 = icmp ne i32 %105, 0 br i1 %106, label %IF47, label %ELSE48 IF47: ; preds = %ELSE45 %107 = fcmp oge float %65, 1.000000e+00 %108 = sext i1 %107 to i32 %109 = bitcast i32 %108 to float %110 = bitcast float %109 to i32 %111 = icmp ne i32 %110, 0 br i1 %111, label %IF50, label %ELSE51 ELSE48: ; preds = %ELSE45 %112 = bitcast float %64 to i32 %113 = icmp eq i32 %112, 3 %114 = sext i1 %113 to i32 %115 = bitcast i32 %114 to float %116 = bitcast float %115 to i32 %117 = icmp ne i32 %116, 0 br i1 %117, label %IF62, label %ENDIF40 IF50: ; preds = %IF47 %118 = fmul float %28, %26 %119 = fmul float %118, 5.000000e-01 %120 = fsub float -0.000000e+00, %119 %121 = fadd float 1.000000e+00, %120 br label %ENDIF49 ELSE51: ; preds = %IF47 %122 = fcmp olt float %65, 0.000000e+00 %123 = sext i1 %122 to i32 %124 = bitcast i32 %123 to float %125 = bitcast float %124 to i32 %126 = icmp ne i32 %125, 0 %. = select i1 %126, float 0.000000e+00, float %65 br label %ENDIF49 ENDIF49: ; preds = %ELSE51, %IF50 %temp16.2 = phi float [ %121, %IF50 ], [ %., %ELSE51 ] %127 = fcmp oge float %66, 1.000000e+00 %128 = sext i1 %127 to i32 %129 = bitcast i32 %128 to float %130 = bitcast float %129 to i32 %131 = icmp ne i32 %130, 0 br i1 %131, label %IF56, label %ELSE57 IF56: ; preds = %ENDIF49 %132 = fmul float %29, %27 %133 = fmul float %132, 5.000000e-01 %134 = fsub float -0.000000e+00, %133 %135 = fadd float 1.000000e+00, %134 br label %ENDIF55 ELSE57: ; preds = %ENDIF49 %136 = fcmp olt float %66, 0.000000e+00 %137 = sext i1 %136 to i32 %138 = bitcast i32 %137 to float %139 = bitcast float %138 to i32 %140 = icmp ne i32 %139, 0 %.121 = select i1 %140, float 0.000000e+00, float %66 br label %ENDIF55 ENDIF55: ; preds = %ELSE57, %IF56 %temp17.2 = phi float [ %135, %IF56 ], [ %.121, %ELSE57 ] %141 = fdiv float 1.000000e+00, %26 %142 = fdiv float 1.000000e+00, %27 %143 = fmul float %temp16.2, %141 %144 = fmul float %temp17.2, %142 br label %ENDIF40 IF62: ; preds = %ELSE48 %145 = call float @floor(float %65) %146 = call float @fabs(float %145) %147 = fmul float %146, 5.000000e-01 %148 = call float @floor(float %147) %149 = fmul float 2.000000e+00, %148 %150 = fsub float -0.000000e+00, %149 %151 = fadd float %146, %150 %152 = fsub float -0.000000e+00, %151 %153 = fadd float 1.000000e+00, %152 %154 = fcmp olt float %153, 0x3F50624DE0000000 %155 = sext i1 %154 to i32 %156 = bitcast i32 %155 to float %157 = bitcast float %156 to i32 %158 = icmp ne i32 %157, 0 %159 = call float @llvm.AMDIL.fraction.(float %65) br i1 %158, label %IF65, label %ELSE66 IF65: ; preds = %IF62 %160 = fsub float -0.000000e+00, %159 %161 = fadd float 1.000000e+00, %160 %162 = fdiv float 1.000000e+00, %26 %163 = fmul float %161, %162 %164 = fsub float -0.000000e+00, %163 %165 = fadd float 2.000000e+00, %164 br label %ENDIF64 ELSE66: ; preds = %IF62 %166 = fdiv float 1.000000e+00, %26 %167 = fmul float %159, %166 br label %ENDIF64 ENDIF64: ; preds = %ELSE66, %IF65 %temp16.5 = phi float [ %165, %IF65 ], [ %167, %ELSE66 ] %168 = call float @floor(float %66) %169 = call float @fabs(float %168) %170 = fmul float %169, 5.000000e-01 %171 = call float @floor(float %170) %172 = fmul float 2.000000e+00, %171 %173 = fsub float -0.000000e+00, %172 %174 = fadd float %169, %173 %175 = fsub float -0.000000e+00, %174 %176 = fadd float 1.000000e+00, %175 %177 = fcmp olt float %176, 0x3F50624DE0000000 %178 = sext i1 %177 to i32 %179 = bitcast i32 %178 to float %180 = bitcast float %179 to i32 %181 = icmp ne i32 %180, 0 %182 = call float @llvm.AMDIL.fraction.(float %66) br i1 %181, label %IF68, label %ELSE69 IF68: ; preds = %ENDIF64 %183 = fsub float -0.000000e+00, %182 %184 = fadd float 1.000000e+00, %183 %185 = fdiv float 1.000000e+00, %27 %186 = fmul float %184, %185 %187 = fsub float -0.000000e+00, %186 %188 = fadd float 2.000000e+00, %187 br label %ENDIF40 ELSE69: ; preds = %ENDIF64 %189 = fdiv float 1.000000e+00, %27 %190 = fmul float %182, %189 br label %ENDIF40 IF71: ; preds = %ENDIF40 %191 = fcmp oge float %temp20.0, 0.000000e+00 %192 = sext i1 %191 to i32 %193 = bitcast i32 %192 to float %194 = fcmp olt float %temp20.0, 1.000000e+00 %195 = sext i1 %194 to i32 %196 = bitcast i32 %195 to float %197 = bitcast float %193 to i32 %198 = bitcast float %196 to i32 %199 = and i32 %197, %198 %200 = bitcast i32 %199 to float %201 = fcmp oge float %temp21.0, 0.000000e+00 %202 = sext i1 %201 to i32 %203 = bitcast i32 %202 to float %204 = bitcast float %200 to i32 %205 = bitcast float %203 to i32 %206 = and i32 %204, %205 %207 = bitcast i32 %206 to float %208 = fcmp olt float %temp21.0, 1.000000e+00 %209 = sext i1 %208 to i32 %210 = bitcast i32 %209 to float %211 = bitcast float %207 to i32 %212 = bitcast float %210 to i32 %213 = and i32 %211, %212 %214 = bitcast i32 %213 to float %215 = bitcast float %214 to i32 %216 = xor i32 %215, -1 %217 = bitcast i32 %216 to float %218 = bitcast float %217 to i32 %219 = icmp ne i32 %218, 0 br i1 %219, label %ENDIF70, label %ELSE75 ENDIF70: ; preds = %ELSE75, %IF71, %ENDIF40 %temp8.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF40 ], [ 0xFFFFFFFFE0000000, %ELSE75 ], [ 0.000000e+00, %IF71 ] %temp12.0 = phi float [ %88, %ENDIF40 ], [ %217, %ELSE75 ], [ 0.000000e+00, %IF71 ] %temp15.0 = phi float [ 0.000000e+00, %ENDIF40 ], [ 0.000000e+00, %ELSE75 ], [ 1.000000e+00, %IF71 ] %temp5.0 = phi float [ %temp21.0, %ENDIF40 ], [ %227, %ELSE75 ], [ %temp21.0, %IF71 ] %temp4.0 = phi float [ %temp20.0, %ENDIF40 ], [ %226, %ELSE75 ], [ %temp20.0, %IF71 ] %220 = bitcast float %temp8.0 to i32 %221 = icmp ne i32 %220, 0 br i1 %221, label %IF77, label %ENDIF ELSE75: ; preds = %IF71 %222 = call float @llvm.AMDIL.fraction.(float %temp20.0) %223 = call float @llvm.AMDIL.fraction.(float %temp21.0) %224 = fdiv float 1.000000e+00, %26 %225 = fdiv float 1.000000e+00, %27 %226 = fmul float %222, %224 %227 = fmul float %223, %225 br label %ENDIF70 IF77: ; preds = %ENDIF70 %228 = bitcast float %temp4.0 to i32 %229 = bitcast float %temp5.0 to i32 %230 = insertelement <2 x i32> undef, i32 %228, i32 0 %231 = insertelement <2 x i32> %230, i32 %229, i32 1 %232 = bitcast <8 x i32> %35 to <32 x i8> %233 = bitcast <4 x i32> %37 to <16 x i8> %234 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %231, <32 x i8> %232, <16 x i8> %233, i32 2) %235 = extractelement <4 x float> %234, i32 0 %236 = extractelement <4 x float> %234, i32 1 %237 = extractelement <4 x float> %234, i32 2 br label %ENDIF IF80: ; preds = %ENDIF %238 = bitcast float %42 to i32 %239 = bitcast float %43 to i32 %240 = insertelement <2 x i32> undef, i32 %238, i32 0 %241 = insertelement <2 x i32> %240, i32 %239, i32 1 %242 = bitcast <8 x i32> %39 to <32 x i8> %243 = bitcast <4 x i32> %41 to <16 x i8> %244 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %241, <32 x i8> %242, <16 x i8> %243, i32 2) %245 = extractelement <4 x float> %244, i32 3 br label %ENDIF79 ELSE81: ; preds = %ENDIF %246 = bitcast float %25 to i32 %247 = add i32 %246, -10 %248 = bitcast i32 %247 to float %249 = fmul float %42, %30 %250 = fmul float %43, %31 %251 = bitcast float %248 to i32 %252 = icmp eq i32 %251, 0 %253 = sext i1 %252 to i32 %254 = bitcast i32 %253 to float %255 = bitcast float %254 to i32 %256 = icmp ne i32 %255, 0 br i1 %256, label %ENDIF82, label %ELSE84 ENDIF79: ; preds = %IF119, %ENDIF112, %IF80 %temp7.0 = phi float [ %245, %IF80 ], [ %421, %IF119 ], [ 0.000000e+00, %ENDIF112 ] %257 = fmul float %temp.0, %temp7.0 %258 = fmul float %temp1.0, %temp7.0 %259 = fmul float %temp2.0, %temp7.0 %260 = fmul float %temp3.0, %temp7.0 %261 = call i32 @llvm.SI.packf16(float %257, float %258) %262 = bitcast i32 %261 to float %263 = call i32 @llvm.SI.packf16(float %259, float %260) %264 = bitcast i32 %263 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %262, float %264, float %262, float %264) ret void ELSE84: ; preds = %ELSE81 %265 = bitcast float %248 to i32 %266 = icmp eq i32 %265, 1 %267 = sext i1 %266 to i32 %268 = bitcast i32 %267 to float %269 = bitcast float %268 to i32 %270 = icmp ne i32 %269, 0 br i1 %270, label %IF86, label %ELSE87 ENDIF82: ; preds = %IF110, %ELSE111, %ELSE90, %ENDIF97, %IF86, %ELSE81 %temp24.0 = phi float [ %249, %ELSE81 ], [ %284, %IF86 ], [ %329, %ENDIF97 ], [ %249, %ELSE90 ], [ %temp20.6, %ELSE111 ], [ %temp20.6, %IF110 ] %temp25.0 = phi float [ %250, %ELSE81 ], [ %286, %IF86 ], [ %330, %ENDIF97 ], [ %250, %ELSE90 ], [ %374, %IF110 ], [ %376, %ELSE111 ] %271 = bitcast float %25 to i32 %272 = icmp eq i32 %271, 10 %273 = sext i1 %272 to i32 %274 = bitcast i32 %273 to float %275 = bitcast float %274 to i32 %276 = icmp ne i32 %275, 0 br i1 %276, label %IF113, label %ENDIF112 IF86: ; preds = %ELSE84 %277 = call float @llvm.AMDIL.fraction.(float %249) %278 = call float @llvm.AMDIL.fraction.(float %250) %279 = fdiv float 1.000000e+00, %30 %280 = fdiv float 1.000000e+00, %31 %281 = call float @floor(float %249) %282 = call float @floor(float %250) %283 = fmul float %277, %279 %284 = fadd float %283, %281 %285 = fmul float %278, %280 %286 = fadd float %285, %282 br label %ENDIF82 ELSE87: ; preds = %ELSE84 %287 = bitcast float %248 to i32 %288 = icmp eq i32 %287, 2 %289 = sext i1 %288 to i32 %290 = bitcast i32 %289 to float %291 = bitcast float %290 to i32 %292 = icmp ne i32 %291, 0 br i1 %292, label %IF89, label %ELSE90 IF89: ; preds = %ELSE87 %293 = fcmp oge float %249, 1.000000e+00 %294 = sext i1 %293 to i32 %295 = bitcast i32 %294 to float %296 = bitcast float %295 to i32 %297 = icmp ne i32 %296, 0 br i1 %297, label %IF92, label %ELSE93 ELSE90: ; preds = %ELSE87 %298 = bitcast float %248 to i32 %299 = icmp eq i32 %298, 3 %300 = sext i1 %299 to i32 %301 = bitcast i32 %300 to float %302 = bitcast float %301 to i32 %303 = icmp ne i32 %302, 0 br i1 %303, label %IF104, label %ENDIF82 IF92: ; preds = %IF89 %304 = fmul float %32, %30 %305 = fmul float %304, 5.000000e-01 %306 = fsub float -0.000000e+00, %305 %307 = fadd float 1.000000e+00, %306 br label %ENDIF91 ELSE93: ; preds = %IF89 %308 = fcmp olt float %249, 0.000000e+00 %309 = sext i1 %308 to i32 %310 = bitcast i32 %309 to float %311 = bitcast float %310 to i32 %312 = icmp ne i32 %311, 0 %.122 = select i1 %312, float 0.000000e+00, float %249 br label %ENDIF91 ENDIF91: ; preds = %ELSE93, %IF92 %temp20.3 = phi float [ %307, %IF92 ], [ %.122, %ELSE93 ] %313 = fcmp oge float %250, 1.000000e+00 %314 = sext i1 %313 to i32 %315 = bitcast i32 %314 to float %316 = bitcast float %315 to i32 %317 = icmp ne i32 %316, 0 br i1 %317, label %IF98, label %ELSE99 IF98: ; preds = %ENDIF91 %318 = fmul float %33, %31 %319 = fmul float %318, 5.000000e-01 %320 = fsub float -0.000000e+00, %319 %321 = fadd float 1.000000e+00, %320 br label %ENDIF97 ELSE99: ; preds = %ENDIF91 %322 = fcmp olt float %250, 0.000000e+00 %323 = sext i1 %322 to i32 %324 = bitcast i32 %323 to float %325 = bitcast float %324 to i32 %326 = icmp ne i32 %325, 0 %.123 = select i1 %326, float 0.000000e+00, float %250 br label %ENDIF97 ENDIF97: ; preds = %ELSE99, %IF98 %temp21.3 = phi float [ %321, %IF98 ], [ %.123, %ELSE99 ] %327 = fdiv float 1.000000e+00, %30 %328 = fdiv float 1.000000e+00, %31 %329 = fmul float %temp20.3, %327 %330 = fmul float %temp21.3, %328 br label %ENDIF82 IF104: ; preds = %ELSE90 %331 = call float @floor(float %249) %332 = call float @fabs(float %331) %333 = fmul float %332, 5.000000e-01 %334 = call float @floor(float %333) %335 = fmul float 2.000000e+00, %334 %336 = fsub float -0.000000e+00, %335 %337 = fadd float %332, %336 %338 = fsub float -0.000000e+00, %337 %339 = fadd float 1.000000e+00, %338 %340 = fcmp olt float %339, 0x3F50624DE0000000 %341 = sext i1 %340 to i32 %342 = bitcast i32 %341 to float %343 = bitcast float %342 to i32 %344 = icmp ne i32 %343, 0 %345 = call float @llvm.AMDIL.fraction.(float %249) br i1 %344, label %IF107, label %ELSE108 IF107: ; preds = %IF104 %346 = fsub float -0.000000e+00, %345 %347 = fadd float 1.000000e+00, %346 %348 = fdiv float 1.000000e+00, %30 %349 = fmul float %347, %348 %350 = fsub float -0.000000e+00, %349 %351 = fadd float 2.000000e+00, %350 br label %ENDIF106 ELSE108: ; preds = %IF104 %352 = fdiv float 1.000000e+00, %30 %353 = fmul float %345, %352 br label %ENDIF106 ENDIF106: ; preds = %ELSE108, %IF107 %temp20.6 = phi float [ %351, %IF107 ], [ %353, %ELSE108 ] %354 = call float @floor(float %250) %355 = call float @fabs(float %354) %356 = fmul float %355, 5.000000e-01 %357 = call float @floor(float %356) %358 = fmul float 2.000000e+00, %357 %359 = fsub float -0.000000e+00, %358 %360 = fadd float %355, %359 %361 = fsub float -0.000000e+00, %360 %362 = fadd float 1.000000e+00, %361 %363 = fcmp olt float %362, 0x3F50624DE0000000 %364 = sext i1 %363 to i32 %365 = bitcast i32 %364 to float %366 = bitcast float %365 to i32 %367 = icmp ne i32 %366, 0 %368 = call float @llvm.AMDIL.fraction.(float %250) br i1 %367, label %IF110, label %ELSE111 IF110: ; preds = %ENDIF106 %369 = fsub float -0.000000e+00, %368 %370 = fadd float 1.000000e+00, %369 %371 = fdiv float 1.000000e+00, %31 %372 = fmul float %370, %371 %373 = fsub float -0.000000e+00, %372 %374 = fadd float 2.000000e+00, %373 br label %ENDIF82 ELSE111: ; preds = %ENDIF106 %375 = fdiv float 1.000000e+00, %31 %376 = fmul float %368, %375 br label %ENDIF82 IF113: ; preds = %ENDIF82 %377 = fcmp oge float %temp24.0, 0.000000e+00 %378 = sext i1 %377 to i32 %379 = bitcast i32 %378 to float %380 = fcmp olt float %temp24.0, 1.000000e+00 %381 = sext i1 %380 to i32 %382 = bitcast i32 %381 to float %383 = bitcast float %379 to i32 %384 = bitcast float %382 to i32 %385 = and i32 %383, %384 %386 = bitcast i32 %385 to float %387 = fcmp oge float %temp25.0, 0.000000e+00 %388 = sext i1 %387 to i32 %389 = bitcast i32 %388 to float %390 = bitcast float %386 to i32 %391 = bitcast float %389 to i32 %392 = and i32 %390, %391 %393 = bitcast i32 %392 to float %394 = fcmp olt float %temp25.0, 1.000000e+00 %395 = sext i1 %394 to i32 %396 = bitcast i32 %395 to float %397 = bitcast float %393 to i32 %398 = bitcast float %396 to i32 %399 = and i32 %397, %398 %400 = bitcast i32 %399 to float %401 = bitcast float %400 to i32 %402 = xor i32 %401, -1 %403 = bitcast i32 %402 to float %404 = bitcast float %403 to i32 %405 = icmp ne i32 %404, 0 br i1 %405, label %ENDIF112, label %ELSE117 ENDIF112: ; preds = %ELSE117, %IF113, %ENDIF82 %temp8.2 = phi float [ %temp24.0, %ENDIF82 ], [ %412, %ELSE117 ], [ %temp24.0, %IF113 ] %temp9.0 = phi float [ %temp25.0, %ENDIF82 ], [ %413, %ELSE117 ], [ %temp25.0, %IF113 ] %temp12.3 = phi float [ 0xFFFFFFFFE0000000, %ENDIF82 ], [ 0xFFFFFFFFE0000000, %ELSE117 ], [ 0.000000e+00, %IF113 ] %406 = bitcast float %temp12.3 to i32 %407 = icmp ne i32 %406, 0 br i1 %407, label %IF119, label %ENDIF79 ELSE117: ; preds = %IF113 %408 = call float @llvm.AMDIL.fraction.(float %temp24.0) %409 = call float @llvm.AMDIL.fraction.(float %temp25.0) %410 = fdiv float 1.000000e+00, %30 %411 = fdiv float 1.000000e+00, %31 %412 = fmul float %408, %410 %413 = fmul float %409, %411 br label %ENDIF112 IF119: ; preds = %ENDIF112 %414 = bitcast float %temp8.2 to i32 %415 = bitcast float %temp9.0 to i32 %416 = insertelement <2 x i32> undef, i32 %414, i32 0 %417 = insertelement <2 x i32> %416, i32 %415, i32 1 %418 = bitcast <8 x i32> %39 to <32 x i8> %419 = bitcast <4 x i32> %41 to <16 x i8> %420 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %417, <32 x i8> %418, <16 x i8> %419, i32 2) %421 = extractelement <4 x float> %420, i32 3 br label %ENDIF79 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_load_dwordx4 s[12:15], s[4:5], 0x0 ; C0860500 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x0 ; C2040100 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 s_load_dwordx8 s[16:23], s[6:7], 0x0 ; C0C80700 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 v_interp_p1_f32 v7, v0, 2, 0, [m0] ; C81C0200 v_interp_p2_f32 v7, [v7], v1, 2, 0, [m0] ; C81D0201 v_interp_p1_f32 v8, v0, 3, 0, [m0] ; C8200300 v_interp_p2_f32 v8, [v8], v1, 3, 0, [m0] ; C8210301 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_lt_i32_e64 s[10:11], s8, 10 ; D102000A 00011408 v_cndmask_b32_e64 v0, 0, -1, s[10:11] ; D2000000 00298280 v_cmp_eq_i32_e64 s[10:11], v0, 0 ; D104000A 00010100 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_8 ; BF880000 v_mov_b32_e32 v0, s8 ; 7E000208 s_buffer_load_dword s9, s[0:3], 0xc ; C204810C s_buffer_load_dword s24, s[0:3], 0xd ; C20C010D v_add_i32_e32 v4, -10, v0 ; 4A0800CA v_cmp_eq_i32_e64 s[26:27], v4, 0 ; D104001A 00010104 v_cndmask_b32_e64 v0, 0, -1, s[26:27] ; D2000000 00698280 v_cmp_eq_i32_e64 s[26:27], v0, 0 ; D104001A 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v9, s9, v7 ; 10120E09 v_mul_f32_e32 v10, s24, v8 ; 10141018 s_and_saveexec_b64 s[26:27], s[26:27] ; BE9A241A s_xor_b64 s[26:27], exec, s[26:27] ; 899A1A7E s_cbranch_execz BB0_9 ; BF880000 v_cmp_eq_i32_e64 s[28:29], v4, 1 ; D104001C 00010304 v_cndmask_b32_e64 v0, 0, -1, s[28:29] ; D2000000 00718280 v_cmp_eq_i32_e64 s[28:29], v0, 0 ; D104001C 00010100 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E s_cbranch_execz BB0_10 ; BF880000 v_cmp_eq_i32_e64 s[30:31], v4, 2 ; D104001E 00010504 v_cndmask_b32_e64 v0, 0, -1, s[30:31] ; D2000000 00798280 v_cmp_eq_i32_e64 s[30:31], v0, 0 ; D104001E 00010100 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E s_cbranch_execz BB0_13 ; BF880000 v_cmp_eq_i32_e64 s[32:33], v4, 3 ; D1040020 00010704 v_cndmask_b32_e64 v0, 0, -1, s[32:33] ; D2000000 00818280 v_cmp_ne_i32_e64 s[32:33], v0, 0 ; D10A0020 00010100 v_mov_b32_e32 v1, v10 ; 7E02030A v_mov_b32_e32 v0, v9 ; 7E000309 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E s_cbranch_execz BB0_29 ; BF880000 v_floor_f32_e32 v0, v9 ; 7E004909 v_mul_f32_e64 v1, 0.5, |v0| ; D2100201 000200F0 v_floor_f32_e32 v1, v1 ; 7E024901 v_mad_f32 v0, 2.0, v1, -|v0| ; D2820400 840202F4 v_add_f32_e32 v0, 1.0, v0 ; 060000F2 v_mov_b32_e32 v1, 0x3a83126f ; 7E0202FF 3A83126F v_cmp_lt_f32_e32 vcc, v0, v1 ; 7C020300 v_cndmask_b32_e64 v0, 0, -1, vcc ; D2000000 01A98280 v_fract_f32_e32 v1, v9 ; 7E024109 v_cmp_eq_i32_e64 s[34:35], v0, 0 ; D1040022 00010100 s_and_saveexec_b64 s[34:35], s[34:35] ; BEA22422 s_xor_b64 s[34:35], exec, s[34:35] ; 89A2227E v_rcp_f32_e32 v0, s9 ; 7E005409 v_mul_f32_e32 v0, v0, v1 ; 10000300 s_or_saveexec_b64 s[34:35], s[34:35] ; BEA22522 s_xor_b64 exec, exec, s[34:35] ; 89FE227E v_rcp_f32_e32 v0, s9 ; 7E005409 v_subrev_f32_e32 v1, 1.0, v1 ; 0A0202F2 v_mad_f32 v0, v1, v0, 2.0 ; D2820000 03D20101 s_or_b64 exec, exec, s[34:35] ; 88FE227E v_floor_f32_e32 v1, v10 ; 7E02490A v_mul_f32_e64 v4, 0.5, |v1| ; D2100204 000202F0 v_floor_f32_e32 v4, v4 ; 7E084904 v_mad_f32 v1, 2.0, v4, -|v1| ; D2820401 840608F4 v_add_f32_e32 v1, 1.0, v1 ; 060202F2 v_mov_b32_e32 v4, 0x3a83126f ; 7E0802FF 3A83126F v_cmp_lt_f32_e32 vcc, v1, v4 ; 7C020901 v_cndmask_b32_e64 v1, 0, -1, vcc ; D2000801 01A98280 v_fract_f32_e32 v4, v10 ; 7E08410A v_cmp_eq_i32_e64 s[34:35], v1, 0 ; D1040022 00010101 s_and_saveexec_b64 s[34:35], s[34:35] ; BEA22422 s_xor_b64 s[34:35], exec, s[34:35] ; 89A2227E v_rcp_f32_e32 v1, s24 ; 7E025418 v_mul_f32_e32 v1, v1, v4 ; 10020901 s_or_saveexec_b64 s[34:35], s[34:35] ; BEA22522 s_xor_b64 exec, exec, s[34:35] ; 89FE227E v_rcp_f32_e32 v1, s24 ; 7E025418 v_subrev_f32_e32 v4, 1.0, v4 ; 0A0808F2 v_mad_f32 v1, v4, v1, 2.0 ; D2820001 03D20304 s_or_b64 exec, exec, s[34:35] ; 88FE227E s_or_b64 exec, exec, s[32:33] ; 88FE207E s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E s_cbranch_execz BB0_19 ; BF880000 v_cmp_ge_f32_e64 s[32:33], v9, 1.0 ; D00C0020 0001E509 v_cndmask_b32_e64 v0, 0, -1, s[32:33] ; D2000000 00818280 v_cmp_eq_i32_e64 s[32:33], v0, 0 ; D1040020 00010100 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E v_cmp_lt_f32_e64 s[34:35], v9, 0 ; D0020022 00010109 v_cndmask_b32_e64 v0, 0, -1, s[34:35] ; D2000000 00898280 v_cmp_ne_i32_e64 s[34:35], v0, 0 ; D10A0022 00010100 v_cndmask_b32_e64 v0, v9, 0, s[34:35] ; D2000000 08890109 s_or_saveexec_b64 s[32:33], s[32:33] ; BEA02520 s_xor_b64 exec, exec, s[32:33] ; 89FE207E s_buffer_load_dword s25, s[0:3], 0xe ; C20C810E s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s25 ; 7E000219 v_mul_f32_e32 v0, s9, v0 ; 10000009 v_mad_f32 v0, -0.5, v0, 1.0 ; D2820000 03CA00F1 s_or_b64 exec, exec, s[32:33] ; 88FE207E v_cmp_ge_f32_e64 s[32:33], v10, 1.0 ; D00C0020 0001E50A v_cndmask_b32_e64 v1, 0, -1, s[32:33] ; D2000801 00818280 v_cmp_eq_i32_e64 s[32:33], v1, 0 ; D1040020 00010101 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E v_cmp_lt_f32_e64 s[34:35], v10, 0 ; D0020022 0001010A v_cndmask_b32_e64 v1, 0, -1, s[34:35] ; D2000801 00898280 v_cmp_ne_i32_e64 s[34:35], v1, 0 ; D10A0022 00010101 v_cndmask_b32_e64 v1, v10, 0, s[34:35] ; D2000801 1089010A s_or_saveexec_b64 s[32:33], s[32:33] ; BEA02520 s_xor_b64 exec, exec, s[32:33] ; 89FE207E s_buffer_load_dword s25, s[0:3], 0xf ; C20C810F s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v1, s25 ; 7E020219 v_mul_f32_e32 v1, s24, v1 ; 10020218 v_mad_f32 v1, -0.5, v1, 1.0 ; D2820001 03CA02F1 s_or_b64 exec, exec, s[32:33] ; 88FE207E v_rcp_f32_e32 v4, s9 ; 7E085409 v_rcp_f32_e32 v5, s24 ; 7E0A5418 v_mul_f32_e32 v0, v4, v0 ; 10000104 v_mul_f32_e32 v1, v5, v1 ; 10020305 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E v_fract_f32_e32 v0, v9 ; 7E004109 v_fract_f32_e32 v1, v10 ; 7E02410A v_rcp_f32_e32 v4, s9 ; 7E085409 v_rcp_f32_e32 v5, s24 ; 7E0A5418 v_floor_f32_e32 v6, v9 ; 7E0C4909 v_floor_f32_e32 v9, v10 ; 7E12490A v_mad_f32 v0, v0, v4, v6 ; D2820000 041A0900 v_mad_f32 v1, v1, v5, v9 ; D2820001 04260B01 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_mov_b32_e32 v9, v0 ; 7E120300 v_mov_b32_e32 v10, v1 ; 7E140301 s_or_b64 exec, exec, s[26:27] ; 88FE1A7E v_cmp_eq_i32_e64 s[26:27], s8, 10 ; D104001A 00011408 v_cndmask_b32_e64 v4, 0, -1, s[26:27] ; D2000004 00698280 v_cmp_ne_i32_e64 s[26:27], v4, 0 ; D10A001A 00010104 v_mov_b32_e32 v0, 0 ; 7E000280 v_mov_b32_e32 v1, -1 ; 7E0202C1 s_and_saveexec_b64 s[26:27], s[26:27] ; BE9A241A s_xor_b64 s[26:27], exec, s[26:27] ; 899A1A7E s_cbranch_execz BB0_36 ; BF880000 v_mov_b32_e32 v4, 0 ; 7E080280 v_cmp_ge_f32_e64 s[28:29], v9, 0 ; D00C001C 00010109 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 v_cmp_lt_f32_e64 s[30:31], v9, 1.0 ; D002001E 0001E509 s_and_b64 s[28:29], s[28:29], s[30:31] ; 879C1E1C v_cndmask_b32_e64 v1, 0, -1, s[28:29] ; D2000801 00718280 v_cmp_ge_f32_e64 s[28:29], v10, 0 ; D00C001C 0001010A v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_and_b32_e32 v1, v5, v1 ; 36020305 v_cmp_lt_f32_e64 s[28:29], v10, 1.0 ; D002001C 0001E50A v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_and_b32_e32 v1, v5, v1 ; 36020305 v_not_b32_e32 v5, v1 ; 7E0A6F01 v_cmp_eq_i32_e64 s[28:29], v1, -1 ; D104001C 00018301 v_mov_b32_e32 v1, v4 ; 7E020304 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_fract_f32_e32 v0, v9 ; 7E004109 v_fract_f32_e32 v1, v10 ; 7E02410A v_rcp_f32_e32 v4, s9 ; 7E085409 v_rcp_f32_e32 v6, s24 ; 7E0C5418 v_mul_f32_e32 v9, v4, v0 ; 10120104 v_mul_f32_e32 v10, v6, v1 ; 10140306 v_mov_b32_e32 v1, -1 ; 7E0202C1 v_mov_b32_e32 v0, 0 ; 7E000280 v_mov_b32_e32 v4, v5 ; 7E080305 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E s_or_b64 exec, exec, s[26:27] ; 88FE1A7E v_mov_b32_e32 v5, 0 ; 7E0A0280 v_cmp_ne_i32_e64 s[24:25], v1, 0 ; D10A0018 00010101 v_mov_b32_e32 v6, v5 ; 7E0C0305 s_and_saveexec_b64 s[24:25], s[24:25] ; BE982418 s_xor_b64 s[24:25], exec, s[24:25] ; 8998187E image_sample v[4:6], 7, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[16:23], s[12:15] ; F0800700 00640409 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[24:25] ; 88FE187E s_or_saveexec_b64 s[10:11], s[10:11] ; BE8A250A s_buffer_load_dword s9, s[0:3], 0x4 ; C2048104 s_waitcnt lgkmcnt(0) ; BF8C007F s_xor_b64 exec, exec, s[10:11] ; 89FE0A7E image_sample v[4:6], 7, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[16:23], s[12:15] ; F0800700 00640407 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E s_load_dwordx4 s[12:15], s[4:5], 0x4 ; C0860504 s_load_dwordx8 s[24:31], s[6:7], 0x8 ; C0CC0708 v_cmp_lt_i32_e64 s[4:5], s9, 10 ; D1020004 00011409 v_cndmask_b32_e64 v1, 0, -1, s[4:5] ; D2000801 00118280 v_cmp_eq_i32_e64 s[4:5], v1, 0 ; D1040004 00010101 s_waitcnt lgkmcnt(0) ; BF8C007F s_and_saveexec_b64 s[4:5], s[4:5] ; BE842404 s_xor_b64 s[4:5], exec, s[4:5] ; 8984047E s_cbranch_execz BB0_46 ; BF880000 v_mov_b32_e32 v1, s9 ; 7E020209 s_buffer_load_dword s6, s[0:3], 0x14 ; C2030114 s_buffer_load_dword s7, s[0:3], 0x15 ; C2038115 v_add_i32_e32 v10, -10, v1 ; 4A1402CA v_cmp_eq_i32_e64 s[10:11], v10, 0 ; D104000A 0001010A v_cndmask_b32_e64 v1, 0, -1, s[10:11] ; D2000801 00298280 v_cmp_eq_i32_e64 s[10:11], v1, 0 ; D104000A 00010101 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v7, s6, v2 ; 100E0406 v_mul_f32_e32 v8, s7, v3 ; 10100607 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_47 ; BF880000 v_cmp_eq_i32_e64 s[16:17], v10, 1 ; D1040010 0001030A s_waitcnt expcnt(0) ; BF8C070F v_cndmask_b32_e64 v1, 0, -1, s[16:17] ; D2000801 00418280 v_cmp_eq_i32_e64 s[16:17], v1, 0 ; D1040010 00010101 s_and_saveexec_b64 s[16:17], s[16:17] ; BE902410 s_xor_b64 s[16:17], exec, s[16:17] ; 8990107E s_cbranch_execz BB0_48 ; BF880000 v_cmp_eq_i32_e64 s[18:19], v10, 2 ; D1040012 0001050A v_cndmask_b32_e64 v1, 0, -1, s[18:19] ; D2000801 00498280 v_cmp_eq_i32_e64 s[18:19], v1, 0 ; D1040012 00010101 s_and_saveexec_b64 s[18:19], s[18:19] ; BE922412 s_xor_b64 s[18:19], exec, s[18:19] ; 8992127E s_cbranch_execz BB0_51 ; BF880000 v_cmp_eq_i32_e64 s[20:21], v10, 3 ; D1040014 0001070A v_cndmask_b32_e64 v1, 0, -1, s[20:21] ; D2000801 00518280 v_cmp_ne_i32_e64 s[20:21], v1, 0 ; D10A0014 00010101 v_mov_b32_e32 v9, v8 ; 7E120308 v_mov_b32_e32 v1, v7 ; 7E020307 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E s_cbranch_execz BB0_67 ; BF880000 v_floor_f32_e32 v1, v7 ; 7E024907 v_mul_f32_e64 v9, 0.5, |v1| ; D2100209 000202F0 v_floor_f32_e32 v9, v9 ; 7E124909 v_mad_f32 v1, 2.0, v9, -|v1| ; D2820401 840612F4 v_add_f32_e32 v1, 1.0, v1 ; 060202F2 v_mov_b32_e32 v9, 0x3a83126f ; 7E1202FF 3A83126F v_cmp_lt_f32_e32 vcc, v1, v9 ; 7C021301 v_cndmask_b32_e64 v1, 0, -1, vcc ; D2000801 01A98280 v_fract_f32_e32 v9, v7 ; 7E124107 v_cmp_eq_i32_e64 s[22:23], v1, 0 ; D1040016 00010101 s_and_saveexec_b64 s[22:23], s[22:23] ; BE962416 s_xor_b64 s[22:23], exec, s[22:23] ; 8996167E v_rcp_f32_e32 v1, s6 ; 7E025406 v_mul_f32_e32 v1, v1, v9 ; 10021301 s_or_saveexec_b64 s[22:23], s[22:23] ; BE962516 s_xor_b64 exec, exec, s[22:23] ; 89FE167E v_rcp_f32_e32 v1, s6 ; 7E025406 v_subrev_f32_e32 v9, 1.0, v9 ; 0A1212F2 v_mad_f32 v1, v9, v1, 2.0 ; D2820001 03D20309 s_or_b64 exec, exec, s[22:23] ; 88FE167E v_floor_f32_e32 v9, v8 ; 7E124908 v_mul_f32_e64 v10, 0.5, |v9| ; D210020A 000212F0 v_floor_f32_e32 v10, v10 ; 7E14490A v_mad_f32 v9, 2.0, v10, -|v9| ; D2820409 842614F4 v_add_f32_e32 v9, 1.0, v9 ; 061212F2 v_mov_b32_e32 v10, 0x3a83126f ; 7E1402FF 3A83126F v_cmp_lt_f32_e32 vcc, v9, v10 ; 7C021509 v_cndmask_b32_e64 v9, 0, -1, vcc ; D2000809 01A98280 v_fract_f32_e32 v10, v8 ; 7E144108 v_cmp_eq_i32_e64 s[22:23], v9, 0 ; D1040016 00010109 s_and_saveexec_b64 s[22:23], s[22:23] ; BE962416 s_xor_b64 s[22:23], exec, s[22:23] ; 8996167E v_rcp_f32_e32 v9, s7 ; 7E125407 v_mul_f32_e32 v9, v9, v10 ; 10121509 s_or_saveexec_b64 s[22:23], s[22:23] ; BE962516 s_xor_b64 exec, exec, s[22:23] ; 89FE167E v_rcp_f32_e32 v9, s7 ; 7E125407 v_subrev_f32_e32 v10, 1.0, v10 ; 0A1414F2 v_mad_f32 v9, v10, v9, 2.0 ; D2820009 03D2130A s_or_b64 exec, exec, s[22:23] ; 88FE167E s_or_b64 exec, exec, s[20:21] ; 88FE147E s_or_saveexec_b64 s[18:19], s[18:19] ; BE922512 s_xor_b64 exec, exec, s[18:19] ; 89FE127E s_cbranch_execz BB0_57 ; BF880000 v_cmp_ge_f32_e64 s[20:21], v7, 1.0 ; D00C0014 0001E507 v_cndmask_b32_e64 v1, 0, -1, s[20:21] ; D2000801 00518280 v_cmp_eq_i32_e64 s[20:21], v1, 0 ; D1040014 00010101 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E v_cmp_lt_f32_e64 s[22:23], v7, 0 ; D0020016 00010107 v_cndmask_b32_e64 v1, 0, -1, s[22:23] ; D2000801 00598280 v_cmp_ne_i32_e64 s[22:23], v1, 0 ; D10A0016 00010101 v_cndmask_b32_e64 v1, v7, 0, s[22:23] ; D2000801 18590107 s_or_saveexec_b64 s[20:21], s[20:21] ; BE942514 s_xor_b64 exec, exec, s[20:21] ; 89FE147E s_buffer_load_dword s8, s[0:3], 0x16 ; C2040116 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v1, s8 ; 7E020208 v_mul_f32_e32 v1, s6, v1 ; 10020206 v_mad_f32 v1, -0.5, v1, 1.0 ; D2820001 03CA02F1 s_or_b64 exec, exec, s[20:21] ; 88FE147E v_cmp_ge_f32_e64 s[20:21], v8, 1.0 ; D00C0014 0001E508 v_cndmask_b32_e64 v9, 0, -1, s[20:21] ; D2000809 00518280 v_cmp_eq_i32_e64 s[20:21], v9, 0 ; D1040014 00010109 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E v_cmp_lt_f32_e64 s[22:23], v8, 0 ; D0020016 00010108 v_cndmask_b32_e64 v9, 0, -1, s[22:23] ; D2000809 00598280 v_cmp_ne_i32_e64 s[22:23], v9, 0 ; D10A0016 00010109 v_cndmask_b32_e64 v9, v8, 0, s[22:23] ; D2000809 00590108 s_or_saveexec_b64 s[20:21], s[20:21] ; BE942514 s_xor_b64 exec, exec, s[20:21] ; 89FE147E s_buffer_load_dword s8, s[0:3], 0x17 ; C2040117 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v9, s8 ; 7E120208 v_mul_f32_e32 v9, s7, v9 ; 10121207 v_mad_f32 v9, -0.5, v9, 1.0 ; D2820009 03CA12F1 s_or_b64 exec, exec, s[20:21] ; 88FE147E v_rcp_f32_e32 v10, s6 ; 7E145406 v_rcp_f32_e32 v11, s7 ; 7E165407 v_mul_f32_e32 v1, v10, v1 ; 1002030A v_mul_f32_e32 v9, v11, v9 ; 1012130B s_or_b64 exec, exec, s[18:19] ; 88FE127E s_or_saveexec_b64 s[16:17], s[16:17] ; BE902510 s_xor_b64 exec, exec, s[16:17] ; 89FE107E v_fract_f32_e32 v1, v7 ; 7E024107 v_fract_f32_e32 v9, v8 ; 7E124108 v_rcp_f32_e32 v10, s6 ; 7E145406 v_rcp_f32_e32 v11, s7 ; 7E165407 v_floor_f32_e32 v7, v7 ; 7E0E4907 v_floor_f32_e32 v8, v8 ; 7E104908 v_mad_f32 v1, v1, v10, v7 ; D2820001 041E1501 v_mad_f32 v9, v9, v11, v8 ; D2820009 04221709 s_or_b64 exec, exec, s[16:17] ; 88FE107E v_mov_b32_e32 v7, v1 ; 7E0E0301 v_mov_b32_e32 v8, v9 ; 7E100309 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_cmp_eq_i32_e64 s[10:11], s9, 10 ; D104000A 00011409 v_cndmask_b32_e64 v1, 0, -1, s[10:11] ; D2000801 00298280 v_cmp_ne_i32_e64 s[10:11], v1, 0 ; D10A000A 00010101 v_mov_b32_e32 v1, -1 ; 7E0202C1 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_74 ; BF880000 v_mov_b32_e32 v1, 0 ; 7E020280 v_cmp_ge_f32_e64 s[16:17], v7, 0 ; D00C0010 00010107 v_cmp_lt_f32_e64 s[18:19], v7, 1.0 ; D0020012 0001E507 s_and_b64 s[16:17], s[16:17], s[18:19] ; 87901210 v_cndmask_b32_e64 v9, 0, -1, s[16:17] ; D2000809 00418280 v_cmp_ge_f32_e64 s[16:17], v8, 0 ; D00C0010 00010108 v_cndmask_b32_e64 v10, 0, -1, s[16:17] ; D200000A 00418280 v_and_b32_e32 v9, v10, v9 ; 3612130A v_cmp_lt_f32_e64 s[16:17], v8, 1.0 ; D0020010 0001E508 v_cndmask_b32_e64 v10, 0, -1, s[16:17] ; D200000A 00418280 v_and_b32_e32 v9, v10, v9 ; 3612130A v_cmp_eq_i32_e64 s[16:17], v9, -1 ; D1040010 00018309 s_and_saveexec_b64 s[16:17], s[16:17] ; BE902410 s_xor_b64 s[16:17], exec, s[16:17] ; 8990107E v_fract_f32_e32 v1, v7 ; 7E024107 v_rcp_f32_e32 v7, s6 ; 7E0E5406 v_rcp_f32_e32 v9, s7 ; 7E125407 v_fract_f32_e32 v8, v8 ; 7E104108 v_mul_f32_e32 v7, v7, v1 ; 100E0307 v_mul_f32_e32 v8, v9, v8 ; 10101109 v_mov_b32_e32 v1, -1 ; 7E0202C1 s_or_b64 exec, exec, s[16:17] ; 88FE107E s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_cmp_ne_i32_e64 s[6:7], v1, 0 ; D10A0006 00010101 v_mov_b32_e32 v1, 0 ; 7E020280 s_and_saveexec_b64 s[6:7], s[6:7] ; BE862406 s_xor_b64 s[6:7], exec, s[6:7] ; 8986067E image_sample v1, 8, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[24:31], s[12:15] ; F0800800 00660107 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[6:7] ; 88FE067E s_or_saveexec_b64 s[4:5], s[4:5] ; BE842504 s_xor_b64 exec, exec, s[4:5] ; 89FE047E image_sample v1, 8, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[24:31], s[12:15] ; F0800800 00660102 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[4:5] ; 88FE047E v_mul_f32_e32 v2, v1, v4 ; 10040901 v_mul_f32_e32 v3, v1, v5 ; 10060B01 v_mul_f32_e32 v4, v1, v6 ; 10080D01 v_mul_f32_e32 v0, v1, v0 ; 10000101 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 v_cvt_pkrtz_f16_f32_e32 v0, v4, v0 ; 5E000104 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 s_endpgm ; BF810000 The XKEYBOARD keymap compiler (xkbcomp) reports: > Warning: Type "ONE_LEVEL" has 1 levels, but has 2 symbols > Ignoring extra symbols Errors from xkbcomp are not fatal to the X server VERT DCL IN[0] DCL OUT[0], POSITION DCL CONST[0] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MAD TEMP[0].xy, IN[0].xyyy, CONST[0].xzzz, CONST[0].ywww 1: MOV TEMP[0].zw, IMM[0].yyxy 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = add i32 %5, %7 %20 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %19) %21 = extractelement <4 x float> %20, i32 0 %22 = extractelement <4 x float> %20, i32 1 %23 = fmul float %21, %13 %24 = fadd float %23, %14 %25 = fmul float %22, %15 %26 = fadd float %25, %16 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %24, float %26, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v2, s5 ; 7E040205 v_mov_b32_e32 v3, s0 ; 7E060200 v_mad_f32 v0, s4, v0, v2 ; D2820000 040A0004 v_mad_f32 v1, s6, v1, v3 ; D2820001 040E0206 v_mov_b32_e32 v2, 1.0 ; 7E0402F2 v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v0, v1, v3, v2 ; F80008CF 02030100 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float %30 = call i32 @llvm.SI.packf16(float %26, float %27) %31 = bitcast i32 %30 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e32 v0, s4, v0 ; 5E000004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e32 v1, s6, v1 ; 5E020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 (II) AIGLX: Suspending AIGLX clients for VT switch VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[0].zw, IN[1].yyxy 2: MOV OUT[1], TEMP[0] 3: MOV OUT[0], IN[0] 4: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0 %27 = add i32 %5, %7 %28 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %26, i32 0, i32 %27) %29 = extractelement <4 x float> %28, i32 0 %30 = extractelement <4 x float> %28, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %29, float %30, float %23, float %24) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 s_load_dwordx4 s[12:15], s[8:9], 0x8 ; C0860908 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[7:10], v0, s[12:15], 0 idxen ; E00C2000 80030700 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v7, v8, v5, v6 ; F800020F 06050807 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0..1] DCL CONST[3] DCL CONST[5] DCL TEMP[0..9], LOCAL IMM[0] INT32 {10, -10, 0, 1} IMM[1] UINT32 {4294967295, 0, 0, 0} IMM[2] INT32 {2, 3, 0, 0} IMM[3] FLT32 { 1.0000, 0.5000, 0.0000, 2.0000} IMM[4] FLT32 { 0.0010, 0.0000, 0.0000, 0.0000} 0: ISLT TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: MOV TEMP[0].xy, IN[0].zwww 3: TEX TEMP[0], TEMP[0], SAMP[0], 2D 4: MOV TEMP[0], TEMP[0] 5: ELSE :0 6: MOV TEMP[1].x, IMM[1].xxxx 7: UADD TEMP[2].x, CONST[0].xxxx, IMM[0].yyyy 8: MUL TEMP[3].xy, IN[0].zwww, CONST[3].xyyy 9: USEQ TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz 10: UIF TEMP[4].xxxx :0 11: MOV TEMP[4].xy, TEMP[3].xyxx 12: ELSE :0 13: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].wwww 14: UIF TEMP[5].xxxx :0 15: FRC TEMP[5].xy, TEMP[3].xyyy 16: RCP TEMP[6].x, CONST[3].xxxx 17: RCP TEMP[6].y, CONST[3].yyyy 18: FLR TEMP[7].xy, TEMP[3].xyyy 19: MAD TEMP[3].xy, TEMP[5].xyyy, TEMP[6].xyyy, TEMP[7].xyyy 20: ELSE :0 21: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx 22: UIF TEMP[5].xxxx :0 23: FSGE TEMP[5].x, TEMP[3].xxxx, IMM[3].xxxx 24: UIF TEMP[5].xxxx :0 25: MUL TEMP[5].x, CONST[3].zzzz, CONST[3].xxxx 26: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 27: ADD TEMP[3].x, IMM[3].xxxx, -TEMP[5].xxxx 28: ELSE :0 29: FSLT TEMP[5].x, TEMP[3].xxxx, IMM[3].zzzz 30: UIF TEMP[5].xxxx :0 31: MOV TEMP[3].x, IMM[3].zzzz 32: ENDIF 33: ENDIF 34: FSGE TEMP[5].x, TEMP[3].yyyy, IMM[3].xxxx 35: UIF TEMP[5].xxxx :0 36: MUL TEMP[5].x, CONST[3].wwww, CONST[3].yyyy 37: MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy 38: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 39: MOV TEMP[3].y, TEMP[5].xxxx 40: ELSE :0 41: FSLT TEMP[5].x, TEMP[3].yyyy, IMM[3].zzzz 42: UIF TEMP[5].xxxx :0 43: MOV TEMP[3].y, IMM[3].zzzz 44: ENDIF 45: ENDIF 46: RCP TEMP[5].x, CONST[3].xxxx 47: RCP TEMP[5].y, CONST[3].yyyy 48: MUL TEMP[3].xy, TEMP[3].xyyy, TEMP[5].xyyy 49: ELSE :0 50: USEQ TEMP[5].x, TEMP[2].xxxx, IMM[2].yyyy 51: UIF TEMP[5].xxxx :0 52: FLR TEMP[5].x, TEMP[3].xxxx 53: ABS TEMP[5].x, TEMP[5].xxxx 54: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 55: FLR TEMP[6].x, TEMP[6].xxxx 56: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 57: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 58: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 59: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 60: UIF TEMP[5].xxxx :0 61: FRC TEMP[5].x, TEMP[3].xxxx 62: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 63: RCP TEMP[6].x, CONST[3].xxxx 64: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 65: ADD TEMP[3].x, IMM[3].wwww, -TEMP[5].xxxx 66: ELSE :0 67: FRC TEMP[5].x, TEMP[3].xxxx 68: RCP TEMP[6].x, CONST[3].xxxx 69: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[6].xxxx 70: ENDIF 71: FLR TEMP[5].x, TEMP[3].yyyy 72: ABS TEMP[5].x, TEMP[5].xxxx 73: MUL TEMP[6].x, TEMP[5].xxxx, IMM[3].yyyy 74: FLR TEMP[6].x, TEMP[6].xxxx 75: MUL TEMP[6].x, IMM[3].wwww, TEMP[6].xxxx 76: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx 77: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 78: FSLT TEMP[5].x, TEMP[5].xxxx, IMM[4].xxxx 79: UIF TEMP[5].xxxx :0 80: FRC TEMP[5].x, TEMP[3].yyyy 81: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx 82: RCP TEMP[6].x, CONST[3].yyyy 83: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 84: ADD TEMP[5].x, IMM[3].wwww, -TEMP[5].xxxx 85: MOV TEMP[3].y, TEMP[5].xxxx 86: ELSE :0 87: FRC TEMP[5].x, TEMP[3].yyyy 88: RCP TEMP[6].x, CONST[3].yyyy 89: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 90: MOV TEMP[3].y, TEMP[5].xxxx 91: ENDIF 92: ENDIF 93: ENDIF 94: ENDIF 95: MOV TEMP[4].xy, TEMP[3].xyxx 96: ENDIF 97: MOV TEMP[2].xy, TEMP[4].xyxx 98: USEQ TEMP[3].x, CONST[0].xxxx, IMM[0].xxxx 99: UIF TEMP[3].xxxx :0 100: FSGE TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz 101: FSLT TEMP[5].x, TEMP[4].xxxx, IMM[3].xxxx 102: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 103: FSGE TEMP[5].x, TEMP[4].yyyy, IMM[3].zzzz 104: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 105: FSLT TEMP[5].x, TEMP[4].yyyy, IMM[3].xxxx 106: AND TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 107: NOT TEMP[3].x, TEMP[3].xxxx 108: UIF TEMP[3].xxxx :0 109: MOV TEMP[3].xyz, IMM[3].zzzz 110: MOV TEMP[3].w, IMM[3].zzzz 111: MOV TEMP[3], TEMP[3] 112: MOV TEMP[1].x, IMM[1].yyyy 113: ELSE :0 114: FRC TEMP[4].xy, TEMP[4].xyyy 115: RCP TEMP[5].x, CONST[3].xxxx 116: RCP TEMP[5].y, CONST[3].yyyy 117: MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy 118: ENDIF 119: ENDIF 120: UIF TEMP[1].xxxx :0 121: MOV TEMP[2].xy, TEMP[2].xyyy 122: TEX TEMP[2], TEMP[2], SAMP[0], 2D 123: MOV TEMP[3], TEMP[2] 124: ENDIF 125: MOV TEMP[0], TEMP[3] 126: ENDIF 127: ISLT TEMP[2].x, CONST[1].xxxx, IMM[0].xxxx 128: UIF TEMP[2].xxxx :0 129: MOV TEMP[2].xy, IN[0].xyyy 130: TEX TEMP[2], TEMP[2], SAMP[1], 2D 131: MOV TEMP[2].w, TEMP[2] 132: ELSE :0 133: MOV TEMP[3].x, IMM[1].xxxx 134: UADD TEMP[4].x, CONST[1].xxxx, IMM[0].yyyy 135: MUL TEMP[5].xy, IN[0].xyyy, CONST[5].xyyy 136: USEQ TEMP[6].x, TEMP[4].xxxx, IMM[0].zzzz 137: UIF TEMP[6].xxxx :0 138: MOV TEMP[6].xy, TEMP[5].xyxx 139: ELSE :0 140: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[0].wwww 141: UIF TEMP[7].xxxx :0 142: FRC TEMP[7].xy, TEMP[5].xyyy 143: RCP TEMP[8].x, CONST[5].xxxx 144: RCP TEMP[8].y, CONST[5].yyyy 145: FLR TEMP[9].xy, TEMP[5].xyyy 146: MAD TEMP[5].xy, TEMP[7].xyyy, TEMP[8].xyyy, TEMP[9].xyyy 147: ELSE :0 148: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[2].xxxx 149: UIF TEMP[7].xxxx :0 150: FSGE TEMP[7].x, TEMP[5].xxxx, IMM[3].xxxx 151: UIF TEMP[7].xxxx :0 152: MUL TEMP[7].x, CONST[5].zzzz, CONST[5].xxxx 153: MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].yyyy 154: ADD TEMP[5].x, IMM[3].xxxx, -TEMP[7].xxxx 155: ELSE :0 156: FSLT TEMP[7].x, TEMP[5].xxxx, IMM[3].zzzz 157: UIF TEMP[7].xxxx :0 158: MOV TEMP[5].x, IMM[3].zzzz 159: ENDIF 160: ENDIF 161: FSGE TEMP[7].x, TEMP[5].yyyy, IMM[3].xxxx 162: UIF TEMP[7].xxxx :0 163: MUL TEMP[7].x, CONST[5].wwww, CONST[5].yyyy 164: MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].yyyy 165: ADD TEMP[7].x, IMM[3].xxxx, -TEMP[7].xxxx 166: MOV TEMP[5].y, TEMP[7].xxxx 167: ELSE :0 168: FSLT TEMP[7].x, TEMP[5].yyyy, IMM[3].zzzz 169: UIF TEMP[7].xxxx :0 170: MOV TEMP[5].y, IMM[3].zzzz 171: ENDIF 172: ENDIF 173: RCP TEMP[7].x, CONST[5].xxxx 174: RCP TEMP[7].y, CONST[5].yyyy 175: MUL TEMP[5].xy, TEMP[5].xyyy, TEMP[7].xyyy 176: ELSE :0 177: USEQ TEMP[4].x, TEMP[4].xxxx, IMM[2].yyyy 178: UIF TEMP[4].xxxx :0 179: FLR TEMP[4].x, TEMP[5].xxxx 180: ABS TEMP[4].x, TEMP[4].xxxx 181: MUL TEMP[7].x, TEMP[4].xxxx, IMM[3].yyyy 182: FLR TEMP[7].x, TEMP[7].xxxx 183: MUL TEMP[7].x, IMM[3].wwww, TEMP[7].xxxx 184: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 185: ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx 186: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 187: UIF TEMP[4].xxxx :0 188: FRC TEMP[4].x, TEMP[5].xxxx 189: ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx 190: RCP TEMP[7].x, CONST[5].xxxx 191: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 192: ADD TEMP[5].x, IMM[3].wwww, -TEMP[4].xxxx 193: ELSE :0 194: FRC TEMP[4].x, TEMP[5].xxxx 195: RCP TEMP[7].x, CONST[5].xxxx 196: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[7].xxxx 197: ENDIF 198: FLR TEMP[4].x, TEMP[5].yyyy 199: ABS TEMP[4].x, TEMP[4].xxxx 200: MUL TEMP[7].x, TEMP[4].xxxx, IMM[3].yyyy 201: FLR TEMP[7].x, TEMP[7].xxxx 202: MUL TEMP[7].x, IMM[3].wwww, TEMP[7].xxxx 203: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 204: ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx 205: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 206: UIF TEMP[4].xxxx :0 207: FRC TEMP[4].x, TEMP[5].yyyy 208: ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx 209: RCP TEMP[7].x, CONST[5].yyyy 210: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 211: ADD TEMP[4].x, IMM[3].wwww, -TEMP[4].xxxx 212: MOV TEMP[5].y, TEMP[4].xxxx 213: ELSE :0 214: FRC TEMP[4].x, TEMP[5].yyyy 215: RCP TEMP[7].x, CONST[5].yyyy 216: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 217: MOV TEMP[5].y, TEMP[4].xxxx 218: ENDIF 219: ENDIF 220: ENDIF 221: ENDIF 222: MOV TEMP[6].xy, TEMP[5].xyxx 223: ENDIF 224: MOV TEMP[1].xy, TEMP[6].xyxx 225: USEQ TEMP[4].x, CONST[1].xxxx, IMM[0].xxxx 226: UIF TEMP[4].xxxx :0 227: FSGE TEMP[4].x, TEMP[6].xxxx, IMM[3].zzzz 228: FSLT TEMP[5].x, TEMP[6].xxxx, IMM[3].xxxx 229: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 230: FSGE TEMP[5].x, TEMP[6].yyyy, IMM[3].zzzz 231: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 232: FSLT TEMP[5].x, TEMP[6].yyyy, IMM[3].xxxx 233: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 234: NOT TEMP[4].x, TEMP[4].xxxx 235: UIF TEMP[4].xxxx :0 236: MOV TEMP[4].xyz, IMM[3].zzzz 237: MOV TEMP[4].w, IMM[3].zzzz 238: MOV TEMP[4], TEMP[4] 239: MOV TEMP[3].x, IMM[1].yyyy 240: ELSE :0 241: FRC TEMP[5].xy, TEMP[6].xyyy 242: RCP TEMP[6].x, CONST[5].xxxx 243: RCP TEMP[6].y, CONST[5].yyyy 244: MUL TEMP[1].xy, TEMP[5].xyyy, TEMP[6].xyyy 245: ENDIF 246: ENDIF 247: UIF TEMP[3].xxxx :0 248: MOV TEMP[1].xy, TEMP[1].xyyy 249: TEX TEMP[1], TEMP[1], SAMP[1], 2D 250: MOV TEMP[4], TEMP[1] 251: ENDIF 252: MOV TEMP[2].w, TEMP[4] 253: ENDIF 254: MUL TEMP[0], TEMP[0], TEMP[2].wwww 255: MOV OUT[0], TEMP[0] 256: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 80) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 84) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 88) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 92) %34 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 0 %35 = load <8 x i32> addrspace(2)* %34, !tbaa !0 %36 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 0 %37 = load <4 x i32> addrspace(2)* %36, !tbaa !0 %38 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 1 %39 = load <8 x i32> addrspace(2)* %38, !tbaa !0 %40 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 1 %41 = load <4 x i32> addrspace(2)* %40, !tbaa !0 %42 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %43 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %44 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %45 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %46 = bitcast float %24 to i32 %47 = icmp slt i32 %46, 10 %48 = sext i1 %47 to i32 %49 = bitcast i32 %48 to float %50 = bitcast float %49 to i32 %51 = icmp ne i32 %50, 0 br i1 %51, label %IF, label %ELSE IF: ; preds = %main_body %52 = bitcast float %44 to i32 %53 = bitcast float %45 to i32 %54 = insertelement <2 x i32> undef, i32 %52, i32 0 %55 = insertelement <2 x i32> %54, i32 %53, i32 1 %56 = bitcast <8 x i32> %35 to <32 x i8> %57 = bitcast <4 x i32> %37 to <16 x i8> %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %55, <32 x i8> %56, <16 x i8> %57, i32 2) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = extractelement <4 x float> %58, i32 3 br label %ENDIF ELSE: ; preds = %main_body %63 = bitcast float %24 to i32 %64 = add i32 %63, -10 %65 = bitcast i32 %64 to float %66 = fmul float %44, %26 %67 = fmul float %45, %27 %68 = bitcast float %65 to i32 %69 = icmp eq i32 %68, 0 %70 = sext i1 %69 to i32 %71 = bitcast i32 %70 to float %72 = bitcast float %71 to i32 %73 = icmp ne i32 %72, 0 br i1 %73, label %ENDIF40, label %ELSE42 ENDIF: ; preds = %IF77, %ENDIF70, %IF %temp3.0 = phi float [ %62, %IF ], [ %239, %IF77 ], [ 0.000000e+00, %ENDIF70 ] %temp2.0 = phi float [ %61, %IF ], [ %238, %IF77 ], [ 0.000000e+00, %ENDIF70 ] %temp1.0 = phi float [ %60, %IF ], [ %237, %IF77 ], [ %temp13.7, %ENDIF70 ] %temp.0 = phi float [ %59, %IF ], [ %236, %IF77 ], [ %temp12.6, %ENDIF70 ] %74 = bitcast float %25 to i32 %75 = icmp slt i32 %74, 10 %76 = sext i1 %75 to i32 %77 = bitcast i32 %76 to float %78 = bitcast float %77 to i32 %79 = icmp ne i32 %78, 0 br i1 %79, label %IF80, label %ELSE81 ELSE42: ; preds = %ELSE %80 = bitcast float %65 to i32 %81 = icmp eq i32 %80, 1 %82 = sext i1 %81 to i32 %83 = bitcast i32 %82 to float %84 = bitcast float %83 to i32 %85 = icmp ne i32 %84, 0 br i1 %85, label %IF44, label %ELSE45 ENDIF40: ; preds = %IF68, %ELSE69, %ELSE48, %ENDIF55, %IF44, %ELSE %temp13.0 = phi float [ %67, %ELSE ], [ %101, %IF44 ], [ %145, %ENDIF55 ], [ %67, %ELSE48 ], [ %189, %IF68 ], [ %191, %ELSE69 ] %temp16.0 = phi float [ %66, %ELSE ], [ %99, %IF44 ], [ %144, %ENDIF55 ], [ %66, %ELSE48 ], [ %temp12.5, %ELSE69 ], [ %temp12.5, %IF68 ] %86 = bitcast float %24 to i32 %87 = icmp eq i32 %86, 10 %88 = sext i1 %87 to i32 %89 = bitcast i32 %88 to float %90 = bitcast float %89 to i32 %91 = icmp ne i32 %90, 0 br i1 %91, label %IF71, label %ENDIF70 IF44: ; preds = %ELSE42 %92 = call float @llvm.AMDIL.fraction.(float %66) %93 = call float @llvm.AMDIL.fraction.(float %67) %94 = fdiv float 1.000000e+00, %26 %95 = fdiv float 1.000000e+00, %27 %96 = call float @floor(float %66) %97 = call float @floor(float %67) %98 = fmul float %92, %94 %99 = fadd float %98, %96 %100 = fmul float %93, %95 %101 = fadd float %100, %97 br label %ENDIF40 ELSE45: ; preds = %ELSE42 %102 = bitcast float %65 to i32 %103 = icmp eq i32 %102, 2 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to float %106 = bitcast float %105 to i32 %107 = icmp ne i32 %106, 0 br i1 %107, label %IF47, label %ELSE48 IF47: ; preds = %ELSE45 %108 = fcmp oge float %66, 1.000000e+00 %109 = sext i1 %108 to i32 %110 = bitcast i32 %109 to float %111 = bitcast float %110 to i32 %112 = icmp ne i32 %111, 0 br i1 %112, label %IF50, label %ELSE51 ELSE48: ; preds = %ELSE45 %113 = bitcast float %65 to i32 %114 = icmp eq i32 %113, 3 %115 = sext i1 %114 to i32 %116 = bitcast i32 %115 to float %117 = bitcast float %116 to i32 %118 = icmp ne i32 %117, 0 br i1 %118, label %IF62, label %ENDIF40 IF50: ; preds = %IF47 %119 = fmul float %28, %26 %120 = fmul float %119, 5.000000e-01 %121 = fsub float -0.000000e+00, %120 %122 = fadd float 1.000000e+00, %121 br label %ENDIF49 ELSE51: ; preds = %IF47 %123 = fcmp olt float %66, 0.000000e+00 %124 = sext i1 %123 to i32 %125 = bitcast i32 %124 to float %126 = bitcast float %125 to i32 %127 = icmp ne i32 %126, 0 %. = select i1 %127, float 0.000000e+00, float %66 br label %ENDIF49 ENDIF49: ; preds = %ELSE51, %IF50 %temp12.2 = phi float [ %122, %IF50 ], [ %., %ELSE51 ] %128 = fcmp oge float %67, 1.000000e+00 %129 = sext i1 %128 to i32 %130 = bitcast i32 %129 to float %131 = bitcast float %130 to i32 %132 = icmp ne i32 %131, 0 br i1 %132, label %IF56, label %ELSE57 IF56: ; preds = %ENDIF49 %133 = fmul float %29, %27 %134 = fmul float %133, 5.000000e-01 %135 = fsub float -0.000000e+00, %134 %136 = fadd float 1.000000e+00, %135 br label %ENDIF55 ELSE57: ; preds = %ENDIF49 %137 = fcmp olt float %67, 0.000000e+00 %138 = sext i1 %137 to i32 %139 = bitcast i32 %138 to float %140 = bitcast float %139 to i32 %141 = icmp ne i32 %140, 0 %.121 = select i1 %141, float 0.000000e+00, float %67 br label %ENDIF55 ENDIF55: ; preds = %ELSE57, %IF56 %temp13.3 = phi float [ %136, %IF56 ], [ %.121, %ELSE57 ] %142 = fdiv float 1.000000e+00, %26 %143 = fdiv float 1.000000e+00, %27 %144 = fmul float %temp12.2, %142 %145 = fmul float %temp13.3, %143 br label %ENDIF40 IF62: ; preds = %ELSE48 %146 = call float @floor(float %66) %147 = call float @fabs(float %146) %148 = fmul float %147, 5.000000e-01 %149 = call float @floor(float %148) %150 = fmul float 2.000000e+00, %149 %151 = fsub float -0.000000e+00, %150 %152 = fadd float %147, %151 %153 = fsub float -0.000000e+00, %152 %154 = fadd float 1.000000e+00, %153 %155 = fcmp olt float %154, 0x3F50624DE0000000 %156 = sext i1 %155 to i32 %157 = bitcast i32 %156 to float %158 = bitcast float %157 to i32 %159 = icmp ne i32 %158, 0 %160 = call float @llvm.AMDIL.fraction.(float %66) br i1 %159, label %IF65, label %ELSE66 IF65: ; preds = %IF62 %161 = fsub float -0.000000e+00, %160 %162 = fadd float 1.000000e+00, %161 %163 = fdiv float 1.000000e+00, %26 %164 = fmul float %162, %163 %165 = fsub float -0.000000e+00, %164 %166 = fadd float 2.000000e+00, %165 br label %ENDIF64 ELSE66: ; preds = %IF62 %167 = fdiv float 1.000000e+00, %26 %168 = fmul float %160, %167 br label %ENDIF64 ENDIF64: ; preds = %ELSE66, %IF65 %temp12.5 = phi float [ %166, %IF65 ], [ %168, %ELSE66 ] %169 = call float @floor(float %67) %170 = call float @fabs(float %169) %171 = fmul float %170, 5.000000e-01 %172 = call float @floor(float %171) %173 = fmul float 2.000000e+00, %172 %174 = fsub float -0.000000e+00, %173 %175 = fadd float %170, %174 %176 = fsub float -0.000000e+00, %175 %177 = fadd float 1.000000e+00, %176 %178 = fcmp olt float %177, 0x3F50624DE0000000 %179 = sext i1 %178 to i32 %180 = bitcast i32 %179 to float %181 = bitcast float %180 to i32 %182 = icmp ne i32 %181, 0 %183 = call float @llvm.AMDIL.fraction.(float %67) br i1 %182, label %IF68, label %ELSE69 IF68: ; preds = %ENDIF64 %184 = fsub float -0.000000e+00, %183 %185 = fadd float 1.000000e+00, %184 %186 = fdiv float 1.000000e+00, %27 %187 = fmul float %185, %186 %188 = fsub float -0.000000e+00, %187 %189 = fadd float 2.000000e+00, %188 br label %ENDIF40 ELSE69: ; preds = %ENDIF64 %190 = fdiv float 1.000000e+00, %27 %191 = fmul float %183, %190 br label %ENDIF40 IF71: ; preds = %ENDIF40 %192 = fcmp oge float %temp16.0, 0.000000e+00 %193 = sext i1 %192 to i32 %194 = bitcast i32 %193 to float %195 = fcmp olt float %temp16.0, 1.000000e+00 %196 = sext i1 %195 to i32 %197 = bitcast i32 %196 to float %198 = bitcast float %194 to i32 %199 = bitcast float %197 to i32 %200 = and i32 %198, %199 %201 = bitcast i32 %200 to float %202 = fcmp oge float %temp13.0, 0.000000e+00 %203 = sext i1 %202 to i32 %204 = bitcast i32 %203 to float %205 = bitcast float %201 to i32 %206 = bitcast float %204 to i32 %207 = and i32 %205, %206 %208 = bitcast i32 %207 to float %209 = fcmp olt float %temp13.0, 1.000000e+00 %210 = sext i1 %209 to i32 %211 = bitcast i32 %210 to float %212 = bitcast float %208 to i32 %213 = bitcast float %211 to i32 %214 = and i32 %212, %213 %215 = bitcast i32 %214 to float %216 = bitcast float %215 to i32 %217 = xor i32 %216, -1 %218 = bitcast i32 %217 to float %219 = bitcast float %218 to i32 %220 = icmp ne i32 %219, 0 br i1 %220, label %ENDIF70, label %ELSE75 ENDIF70: ; preds = %ELSE75, %IF71, %ENDIF40 %temp8.0 = phi float [ %temp16.0, %ENDIF40 ], [ %227, %ELSE75 ], [ %temp16.0, %IF71 ] %temp9.0 = phi float [ %temp13.0, %ENDIF40 ], [ %228, %ELSE75 ], [ %temp13.0, %IF71 ] %temp12.6 = phi float [ %89, %ENDIF40 ], [ %218, %ELSE75 ], [ 0.000000e+00, %IF71 ] %temp13.7 = phi float [ %temp13.0, %ENDIF40 ], [ %temp13.0, %ELSE75 ], [ 0.000000e+00, %IF71 ] %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF40 ], [ 0xFFFFFFFFE0000000, %ELSE75 ], [ 0.000000e+00, %IF71 ] %221 = bitcast float %temp4.0 to i32 %222 = icmp ne i32 %221, 0 br i1 %222, label %IF77, label %ENDIF ELSE75: ; preds = %IF71 %223 = call float @llvm.AMDIL.fraction.(float %temp16.0) %224 = call float @llvm.AMDIL.fraction.(float %temp13.0) %225 = fdiv float 1.000000e+00, %26 %226 = fdiv float 1.000000e+00, %27 %227 = fmul float %223, %225 %228 = fmul float %224, %226 br label %ENDIF70 IF77: ; preds = %ENDIF70 %229 = bitcast float %temp8.0 to i32 %230 = bitcast float %temp9.0 to i32 %231 = insertelement <2 x i32> undef, i32 %229, i32 0 %232 = insertelement <2 x i32> %231, i32 %230, i32 1 %233 = bitcast <8 x i32> %35 to <32 x i8> %234 = bitcast <4 x i32> %37 to <16 x i8> %235 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %232, <32 x i8> %233, <16 x i8> %234, i32 2) %236 = extractelement <4 x float> %235, i32 0 %237 = extractelement <4 x float> %235, i32 1 %238 = extractelement <4 x float> %235, i32 2 %239 = extractelement <4 x float> %235, i32 3 br label %ENDIF IF80: ; preds = %ENDIF %240 = bitcast float %42 to i32 %241 = bitcast float %43 to i32 %242 = insertelement <2 x i32> undef, i32 %240, i32 0 %243 = insertelement <2 x i32> %242, i32 %241, i32 1 %244 = bitcast <8 x i32> %39 to <32 x i8> %245 = bitcast <4 x i32> %41 to <16 x i8> %246 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %243, <32 x i8> %244, <16 x i8> %245, i32 2) %247 = extractelement <4 x float> %246, i32 3 br label %ENDIF79 ELSE81: ; preds = %ENDIF %248 = bitcast float %25 to i32 %249 = add i32 %248, -10 %250 = bitcast i32 %249 to float %251 = fmul float %42, %30 %252 = fmul float %43, %31 %253 = bitcast float %250 to i32 %254 = icmp eq i32 %253, 0 %255 = sext i1 %254 to i32 %256 = bitcast i32 %255 to float %257 = bitcast float %256 to i32 %258 = icmp ne i32 %257, 0 br i1 %258, label %ENDIF82, label %ELSE84 ENDIF79: ; preds = %IF119, %ENDIF112, %IF80 %temp11.2 = phi float [ %247, %IF80 ], [ %423, %IF119 ], [ 0.000000e+00, %ENDIF112 ] %259 = fmul float %temp.0, %temp11.2 %260 = fmul float %temp1.0, %temp11.2 %261 = fmul float %temp2.0, %temp11.2 %262 = fmul float %temp3.0, %temp11.2 %263 = call i32 @llvm.SI.packf16(float %259, float %260) %264 = bitcast i32 %263 to float %265 = call i32 @llvm.SI.packf16(float %261, float %262) %266 = bitcast i32 %265 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %264, float %266, float %264, float %266) ret void ELSE84: ; preds = %ELSE81 %267 = bitcast float %250 to i32 %268 = icmp eq i32 %267, 1 %269 = sext i1 %268 to i32 %270 = bitcast i32 %269 to float %271 = bitcast float %270 to i32 %272 = icmp ne i32 %271, 0 br i1 %272, label %IF86, label %ELSE87 ENDIF82: ; preds = %IF110, %ELSE111, %ELSE90, %ENDIF97, %IF86, %ELSE81 %temp24.0 = phi float [ %251, %ELSE81 ], [ %286, %IF86 ], [ %331, %ENDIF97 ], [ %251, %ELSE90 ], [ %temp20.5, %ELSE111 ], [ %temp20.5, %IF110 ] %temp25.0 = phi float [ %252, %ELSE81 ], [ %288, %IF86 ], [ %332, %ENDIF97 ], [ %252, %ELSE90 ], [ %376, %IF110 ], [ %378, %ELSE111 ] %273 = bitcast float %25 to i32 %274 = icmp eq i32 %273, 10 %275 = sext i1 %274 to i32 %276 = bitcast i32 %275 to float %277 = bitcast float %276 to i32 %278 = icmp ne i32 %277, 0 br i1 %278, label %IF113, label %ENDIF112 IF86: ; preds = %ELSE84 %279 = call float @llvm.AMDIL.fraction.(float %251) %280 = call float @llvm.AMDIL.fraction.(float %252) %281 = fdiv float 1.000000e+00, %30 %282 = fdiv float 1.000000e+00, %31 %283 = call float @floor(float %251) %284 = call float @floor(float %252) %285 = fmul float %279, %281 %286 = fadd float %285, %283 %287 = fmul float %280, %282 %288 = fadd float %287, %284 br label %ENDIF82 ELSE87: ; preds = %ELSE84 %289 = bitcast float %250 to i32 %290 = icmp eq i32 %289, 2 %291 = sext i1 %290 to i32 %292 = bitcast i32 %291 to float %293 = bitcast float %292 to i32 %294 = icmp ne i32 %293, 0 br i1 %294, label %IF89, label %ELSE90 IF89: ; preds = %ELSE87 %295 = fcmp oge float %251, 1.000000e+00 %296 = sext i1 %295 to i32 %297 = bitcast i32 %296 to float %298 = bitcast float %297 to i32 %299 = icmp ne i32 %298, 0 br i1 %299, label %IF92, label %ELSE93 ELSE90: ; preds = %ELSE87 %300 = bitcast float %250 to i32 %301 = icmp eq i32 %300, 3 %302 = sext i1 %301 to i32 %303 = bitcast i32 %302 to float %304 = bitcast float %303 to i32 %305 = icmp ne i32 %304, 0 br i1 %305, label %IF104, label %ENDIF82 IF92: ; preds = %IF89 %306 = fmul float %32, %30 %307 = fmul float %306, 5.000000e-01 %308 = fsub float -0.000000e+00, %307 %309 = fadd float 1.000000e+00, %308 br label %ENDIF91 ELSE93: ; preds = %IF89 %310 = fcmp olt float %251, 0.000000e+00 %311 = sext i1 %310 to i32 %312 = bitcast i32 %311 to float %313 = bitcast float %312 to i32 %314 = icmp ne i32 %313, 0 %.122 = select i1 %314, float 0.000000e+00, float %251 br label %ENDIF91 ENDIF91: ; preds = %ELSE93, %IF92 %temp20.2 = phi float [ %309, %IF92 ], [ %.122, %ELSE93 ] %315 = fcmp oge float %252, 1.000000e+00 %316 = sext i1 %315 to i32 %317 = bitcast i32 %316 to float %318 = bitcast float %317 to i32 %319 = icmp ne i32 %318, 0 br i1 %319, label %IF98, label %ELSE99 IF98: ; preds = %ENDIF91 %320 = fmul float %33, %31 %321 = fmul float %320, 5.000000e-01 %322 = fsub float -0.000000e+00, %321 %323 = fadd float 1.000000e+00, %322 br label %ENDIF97 ELSE99: ; preds = %ENDIF91 %324 = fcmp olt float %252, 0.000000e+00 %325 = sext i1 %324 to i32 %326 = bitcast i32 %325 to float %327 = bitcast float %326 to i32 %328 = icmp ne i32 %327, 0 %.123 = select i1 %328, float 0.000000e+00, float %252 br label %ENDIF97 ENDIF97: ; preds = %ELSE99, %IF98 %temp21.2 = phi float [ %323, %IF98 ], [ %.123, %ELSE99 ] %329 = fdiv float 1.000000e+00, %30 %330 = fdiv float 1.000000e+00, %31 %331 = fmul float %temp20.2, %329 %332 = fmul float %temp21.2, %330 br label %ENDIF82 IF104: ; preds = %ELSE90 %333 = call float @floor(float %251) %334 = call float @fabs(float %333) %335 = fmul float %334, 5.000000e-01 %336 = call float @floor(float %335) %337 = fmul float 2.000000e+00, %336 %338 = fsub float -0.000000e+00, %337 %339 = fadd float %334, %338 %340 = fsub float -0.000000e+00, %339 %341 = fadd float 1.000000e+00, %340 %342 = fcmp olt float %341, 0x3F50624DE0000000 %343 = sext i1 %342 to i32 %344 = bitcast i32 %343 to float %345 = bitcast float %344 to i32 %346 = icmp ne i32 %345, 0 %347 = call float @llvm.AMDIL.fraction.(float %251) br i1 %346, label %IF107, label %ELSE108 IF107: ; preds = %IF104 %348 = fsub float -0.000000e+00, %347 %349 = fadd float 1.000000e+00, %348 %350 = fdiv float 1.000000e+00, %30 %351 = fmul float %349, %350 %352 = fsub float -0.000000e+00, %351 %353 = fadd float 2.000000e+00, %352 br label %ENDIF106 ELSE108: ; preds = %IF104 %354 = fdiv float 1.000000e+00, %30 %355 = fmul float %347, %354 br label %ENDIF106 ENDIF106: ; preds = %ELSE108, %IF107 %temp20.5 = phi float [ %353, %IF107 ], [ %355, %ELSE108 ] %356 = call float @floor(float %252) %357 = call float @fabs(float %356) %358 = fmul float %357, 5.000000e-01 %359 = call float @floor(float %358) %360 = fmul float 2.000000e+00, %359 %361 = fsub float -0.000000e+00, %360 %362 = fadd float %357, %361 %363 = fsub float -0.000000e+00, %362 %364 = fadd float 1.000000e+00, %363 %365 = fcmp olt float %364, 0x3F50624DE0000000 %366 = sext i1 %365 to i32 %367 = bitcast i32 %366 to float %368 = bitcast float %367 to i32 %369 = icmp ne i32 %368, 0 %370 = call float @llvm.AMDIL.fraction.(float %252) br i1 %369, label %IF110, label %ELSE111 IF110: ; preds = %ENDIF106 %371 = fsub float -0.000000e+00, %370 %372 = fadd float 1.000000e+00, %371 %373 = fdiv float 1.000000e+00, %31 %374 = fmul float %372, %373 %375 = fsub float -0.000000e+00, %374 %376 = fadd float 2.000000e+00, %375 br label %ENDIF82 ELSE111: ; preds = %ENDIF106 %377 = fdiv float 1.000000e+00, %31 %378 = fmul float %370, %377 br label %ENDIF82 IF113: ; preds = %ENDIF82 %379 = fcmp oge float %temp24.0, 0.000000e+00 %380 = sext i1 %379 to i32 %381 = bitcast i32 %380 to float %382 = fcmp olt float %temp24.0, 1.000000e+00 %383 = sext i1 %382 to i32 %384 = bitcast i32 %383 to float %385 = bitcast float %381 to i32 %386 = bitcast float %384 to i32 %387 = and i32 %385, %386 %388 = bitcast i32 %387 to float %389 = fcmp oge float %temp25.0, 0.000000e+00 %390 = sext i1 %389 to i32 %391 = bitcast i32 %390 to float %392 = bitcast float %388 to i32 %393 = bitcast float %391 to i32 %394 = and i32 %392, %393 %395 = bitcast i32 %394 to float %396 = fcmp olt float %temp25.0, 1.000000e+00 %397 = sext i1 %396 to i32 %398 = bitcast i32 %397 to float %399 = bitcast float %395 to i32 %400 = bitcast float %398 to i32 %401 = and i32 %399, %400 %402 = bitcast i32 %401 to float %403 = bitcast float %402 to i32 %404 = xor i32 %403, -1 %405 = bitcast i32 %404 to float %406 = bitcast float %405 to i32 %407 = icmp ne i32 %406, 0 br i1 %407, label %ENDIF112, label %ELSE117 ENDIF112: ; preds = %ELSE117, %IF113, %ENDIF82 %temp12.9 = phi float [ 0xFFFFFFFFE0000000, %ENDIF82 ], [ 0xFFFFFFFFE0000000, %ELSE117 ], [ 0.000000e+00, %IF113 ] %temp5.0 = phi float [ %temp25.0, %ENDIF82 ], [ %415, %ELSE117 ], [ %temp25.0, %IF113 ] %temp4.2 = phi float [ %temp24.0, %ENDIF82 ], [ %414, %ELSE117 ], [ %temp24.0, %IF113 ] %408 = bitcast float %temp12.9 to i32 %409 = icmp ne i32 %408, 0 br i1 %409, label %IF119, label %ENDIF79 ELSE117: ; preds = %IF113 %410 = call float @llvm.AMDIL.fraction.(float %temp24.0) %411 = call float @llvm.AMDIL.fraction.(float %temp25.0) %412 = fdiv float 1.000000e+00, %30 %413 = fdiv float 1.000000e+00, %31 %414 = fmul float %410, %412 %415 = fmul float %411, %413 br label %ENDIF112 IF119: ; preds = %ENDIF112 %416 = bitcast float %temp4.2 to i32 %417 = bitcast float %temp5.0 to i32 %418 = insertelement <2 x i32> undef, i32 %416, i32 0 %419 = insertelement <2 x i32> %418, i32 %417, i32 1 %420 = bitcast <8 x i32> %39 to <32 x i8> %421 = bitcast <4 x i32> %41 to <16 x i8> %422 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %419, <32 x i8> %420, <16 x i8> %421, i32 2) %423 = extractelement <4 x float> %422, i32 3 br label %ENDIF79 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE0A7E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_load_dwordx4 s[12:15], s[4:5], 0x0 ; C0860500 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x0 ; C2040100 s_mov_b32 m0, s9 ; BEFC0309 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; C8080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001 s_load_dwordx8 s[16:23], s[6:7], 0x0 ; C0C80700 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; C80C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 v_interp_p1_f32 v8, v0, 2, 0, [m0] ; C8200200 v_interp_p2_f32 v8, [v8], v1, 2, 0, [m0] ; C8210201 v_interp_p1_f32 v9, v0, 3, 0, [m0] ; C8240300 v_interp_p2_f32 v9, [v9], v1, 3, 0, [m0] ; C8250301 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_lt_i32_e64 s[10:11], s8, 10 ; D102000A 00011408 v_cndmask_b32_e64 v0, 0, -1, s[10:11] ; D2000000 00298280 v_cmp_eq_i32_e64 s[10:11], v0, 0 ; D104000A 00010100 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_8 ; BF880000 v_mov_b32_e32 v0, s8 ; 7E000208 s_buffer_load_dword s9, s[0:3], 0xc ; C204810C s_buffer_load_dword s24, s[0:3], 0xd ; C20C010D v_add_i32_e32 v6, -10, v0 ; 4A0C00CA v_cmp_eq_i32_e64 s[26:27], v6, 0 ; D104001A 00010106 v_cndmask_b32_e64 v0, 0, -1, s[26:27] ; D2000000 00698280 v_cmp_eq_i32_e64 s[26:27], v0, 0 ; D104001A 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s9, v8 ; 10001009 v_mul_f32_e32 v1, s24, v9 ; 10021218 s_and_saveexec_b64 s[26:27], s[26:27] ; BE9A241A s_xor_b64 s[26:27], exec, s[26:27] ; 899A1A7E s_cbranch_execz BB0_9 ; BF880000 v_cmp_eq_i32_e64 s[28:29], v6, 1 ; D104001C 00010306 v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_eq_i32_e64 s[28:29], v4, 0 ; D104001C 00010104 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E s_cbranch_execz BB0_10 ; BF880000 v_cmp_eq_i32_e64 s[30:31], v6, 2 ; D104001E 00010506 v_cndmask_b32_e64 v4, 0, -1, s[30:31] ; D2000004 00798280 v_cmp_eq_i32_e64 s[30:31], v4, 0 ; D104001E 00010104 s_and_saveexec_b64 s[30:31], s[30:31] ; BE9E241E s_xor_b64 s[30:31], exec, s[30:31] ; 899E1E7E s_cbranch_execz BB0_13 ; BF880000 v_cmp_eq_i32_e64 s[32:33], v6, 3 ; D1040020 00010706 v_cndmask_b32_e64 v4, 0, -1, s[32:33] ; D2000004 00818280 v_cmp_ne_i32_e64 s[32:33], v4, 0 ; D10A0020 00010104 v_mov_b32_e32 v4, v0 ; 7E080300 v_mov_b32_e32 v5, v1 ; 7E0A0301 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E s_cbranch_execz BB0_29 ; BF880000 v_floor_f32_e32 v4, v0 ; 7E084900 v_mul_f32_e64 v5, 0.5, |v4| ; D2100205 000208F0 v_floor_f32_e32 v5, v5 ; 7E0A4905 v_mad_f32 v4, 2.0, v5, -|v4| ; D2820404 84120AF4 v_add_f32_e32 v4, 1.0, v4 ; 060808F2 v_mov_b32_e32 v5, 0x3a83126f ; 7E0A02FF 3A83126F v_cmp_lt_f32_e32 vcc, v4, v5 ; 7C020B04 v_cndmask_b32_e64 v4, 0, -1, vcc ; D2000004 01A98280 v_fract_f32_e32 v5, v0 ; 7E0A4100 v_cmp_eq_i32_e64 s[34:35], v4, 0 ; D1040022 00010104 s_and_saveexec_b64 s[34:35], s[34:35] ; BEA22422 s_xor_b64 s[34:35], exec, s[34:35] ; 89A2227E v_rcp_f32_e32 v4, s9 ; 7E085409 v_mul_f32_e32 v4, v4, v5 ; 10080B04 s_or_saveexec_b64 s[34:35], s[34:35] ; BEA22522 s_xor_b64 exec, exec, s[34:35] ; 89FE227E v_rcp_f32_e32 v4, s9 ; 7E085409 v_subrev_f32_e32 v5, 1.0, v5 ; 0A0A0AF2 v_mad_f32 v4, v5, v4, 2.0 ; D2820004 03D20905 s_or_b64 exec, exec, s[34:35] ; 88FE227E v_floor_f32_e32 v5, v1 ; 7E0A4901 v_mul_f32_e64 v6, 0.5, |v5| ; D2100206 00020AF0 v_floor_f32_e32 v6, v6 ; 7E0C4906 v_mad_f32 v5, 2.0, v6, -|v5| ; D2820405 84160CF4 v_add_f32_e32 v5, 1.0, v5 ; 060A0AF2 v_mov_b32_e32 v6, 0x3a83126f ; 7E0C02FF 3A83126F v_cmp_lt_f32_e32 vcc, v5, v6 ; 7C020D05 v_cndmask_b32_e64 v5, 0, -1, vcc ; D2000805 01A98280 v_fract_f32_e32 v6, v1 ; 7E0C4101 v_cmp_eq_i32_e64 s[34:35], v5, 0 ; D1040022 00010105 s_and_saveexec_b64 s[34:35], s[34:35] ; BEA22422 s_xor_b64 s[34:35], exec, s[34:35] ; 89A2227E v_rcp_f32_e32 v5, s24 ; 7E0A5418 v_mul_f32_e32 v5, v5, v6 ; 100A0D05 s_or_saveexec_b64 s[34:35], s[34:35] ; BEA22522 s_xor_b64 exec, exec, s[34:35] ; 89FE227E v_rcp_f32_e32 v5, s24 ; 7E0A5418 v_subrev_f32_e32 v6, 1.0, v6 ; 0A0C0CF2 v_mad_f32 v5, v6, v5, 2.0 ; D2820005 03D20B06 s_or_b64 exec, exec, s[34:35] ; 88FE227E s_or_b64 exec, exec, s[32:33] ; 88FE207E s_or_saveexec_b64 s[30:31], s[30:31] ; BE9E251E s_xor_b64 exec, exec, s[30:31] ; 89FE1E7E s_cbranch_execz BB0_19 ; BF880000 v_cmp_ge_f32_e64 s[32:33], v0, 1.0 ; D00C0020 0001E500 v_cndmask_b32_e64 v4, 0, -1, s[32:33] ; D2000004 00818280 v_cmp_eq_i32_e64 s[32:33], v4, 0 ; D1040020 00010104 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E v_cmp_lt_f32_e64 s[34:35], v0, 0 ; D0020022 00010100 v_cndmask_b32_e64 v4, 0, -1, s[34:35] ; D2000004 00898280 v_cmp_ne_i32_e64 s[34:35], v4, 0 ; D10A0022 00010104 v_cndmask_b32_e64 v4, v0, 0, s[34:35] ; D2000004 00890100 s_or_saveexec_b64 s[32:33], s[32:33] ; BEA02520 s_xor_b64 exec, exec, s[32:33] ; 89FE207E s_buffer_load_dword s25, s[0:3], 0xe ; C20C810E s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s25 ; 7E080219 v_mul_f32_e32 v4, s9, v4 ; 10080809 v_mad_f32 v4, -0.5, v4, 1.0 ; D2820004 03CA08F1 s_or_b64 exec, exec, s[32:33] ; 88FE207E v_cmp_ge_f32_e64 s[32:33], v1, 1.0 ; D00C0020 0001E501 v_cndmask_b32_e64 v5, 0, -1, s[32:33] ; D2000805 00818280 v_cmp_eq_i32_e64 s[32:33], v5, 0 ; D1040020 00010105 s_and_saveexec_b64 s[32:33], s[32:33] ; BEA02420 s_xor_b64 s[32:33], exec, s[32:33] ; 89A0207E v_cmp_lt_f32_e64 s[34:35], v1, 0 ; D0020022 00010101 v_cndmask_b32_e64 v5, 0, -1, s[34:35] ; D2000805 00898280 v_cmp_ne_i32_e64 s[34:35], v5, 0 ; D10A0022 00010105 v_cndmask_b32_e64 v5, v1, 0, s[34:35] ; D2000805 08890101 s_or_saveexec_b64 s[32:33], s[32:33] ; BEA02520 s_xor_b64 exec, exec, s[32:33] ; 89FE207E s_buffer_load_dword s25, s[0:3], 0xf ; C20C810F s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v5, s25 ; 7E0A0219 v_mul_f32_e32 v5, s24, v5 ; 100A0A18 v_mad_f32 v5, -0.5, v5, 1.0 ; D2820005 03CA0AF1 s_or_b64 exec, exec, s[32:33] ; 88FE207E v_rcp_f32_e32 v6, s9 ; 7E0C5409 v_rcp_f32_e32 v7, s24 ; 7E0E5418 v_mul_f32_e32 v4, v6, v4 ; 10080906 v_mul_f32_e32 v5, v7, v5 ; 100A0B07 s_or_b64 exec, exec, s[30:31] ; 88FE1E7E s_or_saveexec_b64 s[28:29], s[28:29] ; BE9C251C s_xor_b64 exec, exec, s[28:29] ; 89FE1C7E v_fract_f32_e32 v4, v0 ; 7E084100 v_fract_f32_e32 v5, v1 ; 7E0A4101 v_rcp_f32_e32 v6, s9 ; 7E0C5409 v_rcp_f32_e32 v7, s24 ; 7E0E5418 v_floor_f32_e32 v0, v0 ; 7E004900 v_floor_f32_e32 v1, v1 ; 7E024901 v_mad_f32 v4, v4, v6, v0 ; D2820004 04020D04 v_mad_f32 v5, v5, v7, v1 ; D2820005 04060F05 s_or_b64 exec, exec, s[28:29] ; 88FE1C7E v_mov_b32_e32 v1, v5 ; 7E020305 v_mov_b32_e32 v0, v4 ; 7E000304 s_or_b64 exec, exec, s[26:27] ; 88FE1A7E v_cmp_eq_i32_e64 s[26:27], s8, 10 ; D104001A 00011408 v_cndmask_b32_e64 v4, 0, -1, s[26:27] ; D2000004 00698280 v_cmp_ne_i32_e64 s[26:27], v4, 0 ; D10A001A 00010104 v_mov_b32_e32 v7, -1 ; 7E0E02C1 v_mov_b32_e32 v5, v1 ; 7E0A0301 s_and_saveexec_b64 s[26:27], s[26:27] ; BE9A241A s_xor_b64 s[26:27], exec, s[26:27] ; 899A1A7E s_cbranch_execz BB0_36 ; BF880000 v_mov_b32_e32 v7, 0 ; 7E0E0280 v_cmp_ge_f32_e64 s[28:29], v0, 0 ; D00C001C 00010100 v_cmp_lt_f32_e64 s[30:31], v0, 1.0 ; D002001E 0001E500 s_and_b64 s[28:29], s[28:29], s[30:31] ; 879C1E1C v_cndmask_b32_e64 v4, 0, -1, s[28:29] ; D2000004 00718280 v_cmp_ge_f32_e64 s[28:29], v1, 0 ; D00C001C 00010101 v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_and_b32_e32 v4, v5, v4 ; 36080905 v_cmp_lt_f32_e64 s[28:29], v1, 1.0 ; D002001C 0001E501 v_cndmask_b32_e64 v5, 0, -1, s[28:29] ; D2000805 00718280 v_and_b32_e32 v4, v5, v4 ; 36080905 v_cmp_eq_i32_e64 s[28:29], v4, -1 ; D104001C 00018304 v_mov_b32_e32 v5, v7 ; 7E0A0307 v_not_b32_e32 v6, v4 ; 7E0C6F04 v_mov_b32_e32 v4, v7 ; 7E080307 s_and_saveexec_b64 s[28:29], s[28:29] ; BE9C241C s_xor_b64 s[28:29], exec, s[28:29] ; 899C1C7E v_rcp_f32_e32 v4, s9 ; 7E085409 v_rcp_f32_e32 v5, s24 ; 7E0A5418 v_fract_f32_e32 v0, v0 ; 7E004100 v_fract_f32_e32 v7, v1 ; 7E0E4101 v_mul_f32_e32 v0, v4, v0 ; 10000104 v_mul_f32_e32 v10, v5, v7 ; 10140F05 v_mov_b32_e32 v5, v1 ; 7E0A0301 v_mov_b32_e32 v7, -1 ; 7E0E02C1 v_mov_b32_e32 v4, v6 ; 7E080306 v_mov_b32_e32 v1, v10 ; 7E02030A s_or_b64 exec, exec, s[28:29] ; 88FE1C7E s_or_b64 exec, exec, s[26:27] ; 88FE1A7E v_mov_b32_e32 v6, 0 ; 7E0C0280 v_cmp_ne_i32_e64 s[24:25], v7, 0 ; D10A0018 00010107 v_mov_b32_e32 v7, v6 ; 7E0E0306 s_and_saveexec_b64 s[24:25], s[24:25] ; BE982418 s_xor_b64 s[24:25], exec, s[24:25] ; 8998187E image_sample v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[16:23], s[12:15] ; F0800F00 00640400 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[24:25] ; 88FE187E s_or_saveexec_b64 s[10:11], s[10:11] ; BE8A250A s_buffer_load_dword s9, s[0:3], 0x4 ; C2048104 s_waitcnt lgkmcnt(0) ; BF8C007F s_xor_b64 exec, exec, s[10:11] ; 89FE0A7E image_sample v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[16:23], s[12:15] ; F0800F00 00640408 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E s_load_dwordx4 s[12:15], s[4:5], 0x4 ; C0860504 s_load_dwordx8 s[24:31], s[6:7], 0x8 ; C0CC0708 v_cmp_lt_i32_e64 s[4:5], s9, 10 ; D1020004 00011409 v_cndmask_b32_e64 v0, 0, -1, s[4:5] ; D2000000 00118280 v_cmp_eq_i32_e64 s[4:5], v0, 0 ; D1040004 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F s_and_saveexec_b64 s[4:5], s[4:5] ; BE842404 s_xor_b64 s[4:5], exec, s[4:5] ; 8984047E s_cbranch_execz BB0_46 ; BF880000 v_mov_b32_e32 v0, s9 ; 7E000209 s_buffer_load_dword s6, s[0:3], 0x14 ; C2030114 s_buffer_load_dword s7, s[0:3], 0x15 ; C2038115 v_add_i32_e32 v10, -10, v0 ; 4A1400CA v_cmp_eq_i32_e64 s[10:11], v10, 0 ; D104000A 0001010A v_cndmask_b32_e64 v0, 0, -1, s[10:11] ; D2000000 00298280 v_cmp_eq_i32_e64 s[10:11], v0, 0 ; D104000A 00010100 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s6, v2 ; 10000406 v_mul_f32_e32 v1, s7, v3 ; 10020607 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_47 ; BF880000 v_cmp_eq_i32_e64 s[16:17], v10, 1 ; D1040010 0001030A v_cndmask_b32_e64 v8, 0, -1, s[16:17] ; D2000008 00418280 v_cmp_eq_i32_e64 s[16:17], v8, 0 ; D1040010 00010108 s_waitcnt expcnt(0) ; BF8C070F s_and_saveexec_b64 s[16:17], s[16:17] ; BE902410 s_xor_b64 s[16:17], exec, s[16:17] ; 8990107E s_cbranch_execz BB0_48 ; BF880000 v_cmp_eq_i32_e64 s[18:19], v10, 2 ; D1040012 0001050A v_cndmask_b32_e64 v8, 0, -1, s[18:19] ; D2000008 00498280 v_cmp_eq_i32_e64 s[18:19], v8, 0 ; D1040012 00010108 s_and_saveexec_b64 s[18:19], s[18:19] ; BE922412 s_xor_b64 s[18:19], exec, s[18:19] ; 8992127E s_cbranch_execz BB0_51 ; BF880000 v_cmp_eq_i32_e64 s[20:21], v10, 3 ; D1040014 0001070A v_cndmask_b32_e64 v8, 0, -1, s[20:21] ; D2000008 00518280 v_cmp_ne_i32_e64 s[20:21], v8, 0 ; D10A0014 00010108 v_mov_b32_e32 v9, v1 ; 7E120301 v_mov_b32_e32 v8, v0 ; 7E100300 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E s_cbranch_execz BB0_67 ; BF880000 v_floor_f32_e32 v8, v0 ; 7E104900 v_mul_f32_e64 v9, 0.5, |v8| ; D2100209 000210F0 v_floor_f32_e32 v9, v9 ; 7E124909 v_mad_f32 v8, 2.0, v9, -|v8| ; D2820408 842212F4 v_add_f32_e32 v8, 1.0, v8 ; 061010F2 v_mov_b32_e32 v9, 0x3a83126f ; 7E1202FF 3A83126F v_cmp_lt_f32_e32 vcc, v8, v9 ; 7C021308 v_cndmask_b32_e64 v8, 0, -1, vcc ; D2000008 01A98280 v_fract_f32_e32 v9, v0 ; 7E124100 v_cmp_eq_i32_e64 s[22:23], v8, 0 ; D1040016 00010108 s_and_saveexec_b64 s[22:23], s[22:23] ; BE962416 s_xor_b64 s[22:23], exec, s[22:23] ; 8996167E v_rcp_f32_e32 v8, s6 ; 7E105406 v_mul_f32_e32 v8, v8, v9 ; 10101308 s_or_saveexec_b64 s[22:23], s[22:23] ; BE962516 s_xor_b64 exec, exec, s[22:23] ; 89FE167E v_rcp_f32_e32 v8, s6 ; 7E105406 v_subrev_f32_e32 v9, 1.0, v9 ; 0A1212F2 v_mad_f32 v8, v9, v8, 2.0 ; D2820008 03D21109 s_or_b64 exec, exec, s[22:23] ; 88FE167E v_floor_f32_e32 v9, v1 ; 7E124901 v_mul_f32_e64 v10, 0.5, |v9| ; D210020A 000212F0 v_floor_f32_e32 v10, v10 ; 7E14490A v_mad_f32 v9, 2.0, v10, -|v9| ; D2820409 842614F4 v_add_f32_e32 v9, 1.0, v9 ; 061212F2 v_mov_b32_e32 v10, 0x3a83126f ; 7E1402FF 3A83126F v_cmp_lt_f32_e32 vcc, v9, v10 ; 7C021509 v_cndmask_b32_e64 v9, 0, -1, vcc ; D2000809 01A98280 v_fract_f32_e32 v10, v1 ; 7E144101 v_cmp_eq_i32_e64 s[22:23], v9, 0 ; D1040016 00010109 s_and_saveexec_b64 s[22:23], s[22:23] ; BE962416 s_xor_b64 s[22:23], exec, s[22:23] ; 8996167E v_rcp_f32_e32 v9, s7 ; 7E125407 v_mul_f32_e32 v9, v9, v10 ; 10121509 s_or_saveexec_b64 s[22:23], s[22:23] ; BE962516 s_xor_b64 exec, exec, s[22:23] ; 89FE167E v_rcp_f32_e32 v9, s7 ; 7E125407 v_subrev_f32_e32 v10, 1.0, v10 ; 0A1414F2 v_mad_f32 v9, v10, v9, 2.0 ; D2820009 03D2130A s_or_b64 exec, exec, s[22:23] ; 88FE167E s_or_b64 exec, exec, s[20:21] ; 88FE147E s_or_saveexec_b64 s[18:19], s[18:19] ; BE922512 s_xor_b64 exec, exec, s[18:19] ; 89FE127E s_cbranch_execz BB0_57 ; BF880000 v_cmp_ge_f32_e64 s[20:21], v0, 1.0 ; D00C0014 0001E500 v_cndmask_b32_e64 v8, 0, -1, s[20:21] ; D2000008 00518280 v_cmp_eq_i32_e64 s[20:21], v8, 0 ; D1040014 00010108 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E v_cmp_lt_f32_e64 s[22:23], v0, 0 ; D0020016 00010100 v_cndmask_b32_e64 v8, 0, -1, s[22:23] ; D2000008 00598280 v_cmp_ne_i32_e64 s[22:23], v8, 0 ; D10A0016 00010108 v_cndmask_b32_e64 v8, v0, 0, s[22:23] ; D2000008 00590100 s_or_saveexec_b64 s[20:21], s[20:21] ; BE942514 s_xor_b64 exec, exec, s[20:21] ; 89FE147E s_buffer_load_dword s8, s[0:3], 0x16 ; C2040116 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v8, s8 ; 7E100208 v_mul_f32_e32 v8, s6, v8 ; 10101006 v_mad_f32 v8, -0.5, v8, 1.0 ; D2820008 03CA10F1 s_or_b64 exec, exec, s[20:21] ; 88FE147E v_cmp_ge_f32_e64 s[20:21], v1, 1.0 ; D00C0014 0001E501 v_cndmask_b32_e64 v9, 0, -1, s[20:21] ; D2000809 00518280 v_cmp_eq_i32_e64 s[20:21], v9, 0 ; D1040014 00010109 s_and_saveexec_b64 s[20:21], s[20:21] ; BE942414 s_xor_b64 s[20:21], exec, s[20:21] ; 8994147E v_cmp_lt_f32_e64 s[22:23], v1, 0 ; D0020016 00010101 v_cndmask_b32_e64 v9, 0, -1, s[22:23] ; D2000809 00598280 v_cmp_ne_i32_e64 s[22:23], v9, 0 ; D10A0016 00010109 v_cndmask_b32_e64 v9, v1, 0, s[22:23] ; D2000809 08590101 s_or_saveexec_b64 s[20:21], s[20:21] ; BE942514 s_xor_b64 exec, exec, s[20:21] ; 89FE147E s_buffer_load_dword s8, s[0:3], 0x17 ; C2040117 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v9, s8 ; 7E120208 v_mul_f32_e32 v9, s7, v9 ; 10121207 v_mad_f32 v9, -0.5, v9, 1.0 ; D2820009 03CA12F1 s_or_b64 exec, exec, s[20:21] ; 88FE147E v_rcp_f32_e32 v10, s6 ; 7E145406 v_rcp_f32_e32 v11, s7 ; 7E165407 v_mul_f32_e32 v8, v10, v8 ; 1010110A v_mul_f32_e32 v9, v11, v9 ; 1012130B s_or_b64 exec, exec, s[18:19] ; 88FE127E s_or_saveexec_b64 s[16:17], s[16:17] ; BE902510 s_xor_b64 exec, exec, s[16:17] ; 89FE107E v_fract_f32_e32 v8, v0 ; 7E104100 v_fract_f32_e32 v9, v1 ; 7E124101 v_rcp_f32_e32 v10, s6 ; 7E145406 v_rcp_f32_e32 v11, s7 ; 7E165407 v_floor_f32_e32 v0, v0 ; 7E004900 v_floor_f32_e32 v1, v1 ; 7E024901 v_mad_f32 v8, v8, v10, v0 ; D2820008 04021508 v_mad_f32 v9, v9, v11, v1 ; D2820009 04061709 s_or_b64 exec, exec, s[16:17] ; 88FE107E v_mov_b32_e32 v0, v8 ; 7E000308 v_mov_b32_e32 v1, v9 ; 7E020309 s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_cmp_eq_i32_e64 s[10:11], s9, 10 ; D104000A 00011409 v_cndmask_b32_e64 v8, 0, -1, s[10:11] ; D2000008 00298280 v_cmp_ne_i32_e64 s[10:11], v8, 0 ; D10A000A 00010108 v_mov_b32_e32 v8, -1 ; 7E1002C1 s_and_saveexec_b64 s[10:11], s[10:11] ; BE8A240A s_xor_b64 s[10:11], exec, s[10:11] ; 898A0A7E s_cbranch_execz BB0_74 ; BF880000 v_mov_b32_e32 v8, 0 ; 7E100280 v_cmp_ge_f32_e64 s[16:17], v0, 0 ; D00C0010 00010100 v_cmp_lt_f32_e64 s[18:19], v0, 1.0 ; D0020012 0001E500 s_and_b64 s[16:17], s[16:17], s[18:19] ; 87901210 v_cndmask_b32_e64 v9, 0, -1, s[16:17] ; D2000809 00418280 v_cmp_ge_f32_e64 s[16:17], v1, 0 ; D00C0010 00010101 v_cndmask_b32_e64 v10, 0, -1, s[16:17] ; D200000A 00418280 v_and_b32_e32 v9, v10, v9 ; 3612130A v_cmp_lt_f32_e64 s[16:17], v1, 1.0 ; D0020010 0001E501 v_cndmask_b32_e64 v10, 0, -1, s[16:17] ; D200000A 00418280 v_and_b32_e32 v9, v10, v9 ; 3612130A v_cmp_eq_i32_e64 s[16:17], v9, -1 ; D1040010 00018309 s_and_saveexec_b64 s[16:17], s[16:17] ; BE902410 s_xor_b64 s[16:17], exec, s[16:17] ; 8990107E v_fract_f32_e32 v0, v0 ; 7E004100 v_rcp_f32_e32 v8, s6 ; 7E105406 v_rcp_f32_e32 v9, s7 ; 7E125407 v_fract_f32_e32 v1, v1 ; 7E024101 v_mul_f32_e32 v0, v8, v0 ; 10000108 v_mul_f32_e32 v1, v9, v1 ; 10020309 v_mov_b32_e32 v8, -1 ; 7E1002C1 s_or_b64 exec, exec, s[16:17] ; 88FE107E s_or_b64 exec, exec, s[10:11] ; 88FE0A7E v_cmp_ne_i32_e64 s[6:7], v8, 0 ; D10A0006 00010108 v_mov_b32_e32 v8, 0 ; 7E100280 s_and_saveexec_b64 s[6:7], s[6:7] ; BE862406 s_xor_b64 s[6:7], exec, s[6:7] ; 8986067E image_sample v8, 8, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[24:31], s[12:15] ; F0800800 00660800 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[6:7] ; 88FE067E s_or_saveexec_b64 s[4:5], s[4:5] ; BE842504 s_xor_b64 exec, exec, s[4:5] ; 89FE047E image_sample v8, 8, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[24:31], s[12:15] ; F0800800 00660802 s_waitcnt vmcnt(0) ; BF8C0770 s_or_b64 exec, exec, s[4:5] ; 88FE047E v_mul_f32_e32 v0, v8, v4 ; 10000908 v_mul_f32_e32 v1, v8, v5 ; 10020B08 v_mul_f32_e32 v2, v8, v6 ; 10040D08 v_mul_f32_e32 v3, v8, v7 ; 10060F08 v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300 v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL CONST[0] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MAD TEMP[0].xy, IN[0].xyyy, CONST[0].xzzz, CONST[0].ywww 1: MOV TEMP[0].zw, IMM[0].yyxy 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = add i32 %5, %7 %20 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %19) %21 = extractelement <4 x float> %20, i32 0 %22 = extractelement <4 x float> %20, i32 1 %23 = fmul float %21, %13 %24 = fadd float %23, %14 %25 = fmul float %22, %15 %26 = fadd float %25, %16 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %24, float %26, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v2, s5 ; 7E040205 v_mov_b32_e32 v3, s0 ; 7E060200 v_mad_f32 v0, s4, v0, v2 ; D2820000 040A0004 v_mad_f32 v1, s6, v1, v3 ; D2820001 040E0206 v_mov_b32_e32 v2, 1.0 ; 7E0402F2 v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v0, v1, v3, v2 ; F80008CF 02030100 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float %30 = call i32 @llvm.SI.packf16(float %26, float %27) %31 = bitcast i32 %30 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e32 v0, s4, v0 ; 5E000004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e32 v1, s6, v1 ; 5E020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ; E00C2000 80000000 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 8) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 12) %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float %30 = call i32 @llvm.SI.packf16(float %26, float %27) %31 = bitcast i32 %30 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C0800300 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C2020100 s_buffer_load_dword s5, s[0:3], 0x1 ; C2028101 s_buffer_load_dword s6, s[0:3], 0x2 ; C2030102 s_buffer_load_dword s0, s[0:3], 0x3 ; C2000103 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e32 v0, s4, v0 ; 5E000004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e32 v1, s6, v1 ; 5E020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 s_endpgm ; BF810000 (II) AIGLX: Suspending AIGLX clients for VT switch VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[0].zw, IN[1].yyxy 2: MOV OUT[1], TEMP[0] 3: MOV OUT[0], IN[0] 4: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %11 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 0 %12 = load <16 x i8> addrspace(2)* %11, !tbaa !0 %13 = add i32 %5, %7 %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 1 %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0 %21 = add i32 %5, %7 %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21) %23 = extractelement <4 x float> %22, i32 0 %24 = extractelement <4 x float> %22, i32 1 %25 = getelementptr [16 x <16 x i8>] addrspace(2)* %4, i32 0, i32 2 %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0 %27 = add i32 %5, %7 %28 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %26, i32 0, i32 %27) %29 = extractelement <4 x float> %28, i32 0 %30 = extractelement <4 x float> %28, i32 1 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %29, float %30, float %23, float %24) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C0800900 s_load_dwordx4 s[4:7], s[8:9], 0x4 ; C0820904 s_load_dwordx4 s[12:15], s[8:9], 0x8 ; C0860908 v_add_i32_e32 v0, s10, v0 ; 4A00000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[7:10], v0, s[12:15], 0 idxen ; E00C2000 80030700 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v7, v8, v5, v6 ; F800020F 06050807 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; F80008CF 04030201 s_endpgm ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[9], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[0..1] DCL CONST[3] DCL CONST[5] DCL TEMP[0..9], LOCAL IMM[0] INT32 {10, -10, 0, 1} IMM[1] FLT32 { 1.0000, 0.5000, 0.0000, 2.0000} IMM[2] UINT32 {4294967295, 0, 0, 0} IMM[3] INT32 {2, 3, 0, 0} IMM[4] FLT32 { 0.0010, 0.0000, 0.0000, 0.0000} 0: ISLT TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx 1: UIF TEMP[0].xxxx :0 2: MOV TEMP[0].w, IMM[1].xxxx 3: MOV TEMP[1].xy, IN[0].zwww 4: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D 5: MOV TEMP[0].xyz, TEMP[1].xyzx 6: MOV TEMP[0].w, TEMP[0] 7: ELSE :0 8: MOV TEMP[2].x, IMM[2].xxxx 9: UADD TEMP[3].x, CONST[0].xxxx, IMM[0].yyyy 10: MUL TEMP[4].xy, IN[0].zwww, CONST[3].xyyy 11: USEQ TEMP[5].x, TEMP[3].xxxx, IMM[0].zzzz 12: UIF TEMP[5].xxxx :0 13: MOV TEMP[5].xy, TEMP[4].xyxx 14: ELSE :0 15: USEQ TEMP[6].x, TEMP[3].xxxx, IMM[0].wwww 16: UIF TEMP[6].xxxx :0 17: FRC TEMP[6].xy, TEMP[4].xyyy 18: RCP TEMP[7].x, CONST[3].xxxx 19: RCP TEMP[7].y, CONST[3].yyyy 20: FLR TEMP[8].xy, TEMP[4].xyyy 21: MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[8].xyyy 22: ELSE :0 23: USEQ TEMP[6].x, TEMP[3].xxxx, IMM[3].xxxx 24: UIF TEMP[6].xxxx :0 25: FSGE TEMP[6].x, TEMP[4].xxxx, IMM[1].xxxx 26: UIF TEMP[6].xxxx :0 27: MUL TEMP[6].x, CONST[3].zzzz, CONST[3].xxxx 28: MUL TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy 29: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[6].xxxx 30: ELSE :0 31: FSLT TEMP[6].x, TEMP[4].xxxx, IMM[1].zzzz 32: UIF TEMP[6].xxxx :0 33: MOV TEMP[4].x, IMM[1].zzzz 34: ENDIF 35: ENDIF 36: FSGE TEMP[6].x, TEMP[4].yyyy, IMM[1].xxxx 37: UIF TEMP[6].xxxx :0 38: MUL TEMP[6].x, CONST[3].wwww, CONST[3].yyyy 39: MUL TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy 40: ADD TEMP[6].x, IMM[1].xxxx, -TEMP[6].xxxx 41: MOV TEMP[4].y, TEMP[6].xxxx 42: ELSE :0 43: FSLT TEMP[6].x, TEMP[4].yyyy, IMM[1].zzzz 44: UIF TEMP[6].xxxx :0 45: MOV TEMP[4].y, IMM[1].zzzz 46: ENDIF 47: ENDIF 48: RCP TEMP[6].x, CONST[3].xxxx 49: RCP TEMP[6].y, CONST[3].yyyy 50: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[6].xyyy 51: ELSE :0 52: USEQ TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy 53: UIF TEMP[3].xxxx :0 54: FLR TEMP[3].x, TEMP[4].xxxx 55: ABS TEMP[3].x, TEMP[3].xxxx 56: MUL TEMP[6].x, TEMP[3].xxxx, IMM[1].yyyy 57: FLR TEMP[6].x, TEMP[6].xxxx 58: MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx 59: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[6].xxxx 60: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 61: FSLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx 62: UIF TEMP[3].xxxx :0 63: FRC TEMP[3].x, TEMP[4].xxxx 64: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 65: RCP TEMP[6].x, CONST[3].xxxx 66: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 67: ADD TEMP[4].x, IMM[1].wwww, -TEMP[3].xxxx 68: ELSE :0 69: FRC TEMP[3].x, TEMP[4].xxxx 70: RCP TEMP[6].x, CONST[3].xxxx 71: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx 72: ENDIF 73: FLR TEMP[3].x, TEMP[4].yyyy 74: ABS TEMP[3].x, TEMP[3].xxxx 75: MUL TEMP[6].x, TEMP[3].xxxx, IMM[1].yyyy 76: FLR TEMP[6].x, TEMP[6].xxxx 77: MUL TEMP[6].x, IMM[1].wwww, TEMP[6].xxxx 78: ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[6].xxxx 79: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 80: FSLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx 81: UIF TEMP[3].xxxx :0 82: FRC TEMP[3].x, TEMP[4].yyyy 83: ADD TEMP[3].x, IMM[1].xxxx, -TEMP[3].xxxx 84: RCP TEMP[6].x, CONST[3].yyyy 85: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 86: ADD TEMP[3].x, IMM[1].wwww, -TEMP[3].xxxx 87: MOV TEMP[4].y, TEMP[3].xxxx 88: ELSE :0 89: FRC TEMP[3].x, TEMP[4].yyyy 90: RCP TEMP[6].x, CONST[3].yyyy 91: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx 92: MOV TEMP[4].y, TEMP[3].xxxx 93: ENDIF 94: ENDIF 95: ENDIF 96: ENDIF 97: MOV TEMP[5].xy, TEMP[4].xyxx 98: ENDIF 99: MOV TEMP[1].xy, TEMP[5].xyxx 100: USEQ TEMP[3].x, CONST[0].xxxx, IMM[0].xxxx 101: UIF TEMP[3].xxxx :0 102: FSGE TEMP[3].x, TEMP[5].xxxx, IMM[1].zzzz 103: FSLT TEMP[4].x, TEMP[5].xxxx, IMM[1].xxxx 104: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 105: FSGE TEMP[4].x, TEMP[5].yyyy, IMM[1].zzzz 106: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 107: FSLT TEMP[4].x, TEMP[5].yyyy, IMM[1].xxxx 108: AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 109: NOT TEMP[3].x, TEMP[3].xxxx 110: UIF TEMP[3].xxxx :0 111: MOV TEMP[3].xyz, IMM[1].zzzz 112: MOV TEMP[3].w, IMM[1].xxxx 113: MOV TEMP[3], TEMP[3] 114: MOV TEMP[2].x, IMM[2].yyyy 115: ELSE :0 116: FRC TEMP[4].xy, TEMP[5].xyyy 117: RCP TEMP[5].x, CONST[3].xxxx 118: RCP TEMP[5].y, CONST[3].yyyy 119: MUL TEMP[1].xy, TEMP[4].xyyy, TEMP[5].xyyy 120: ENDIF 121: ENDIF 122: UIF TEMP[2].xxxx :0 123: MOV TEMP[2].w, IMM[1].xxxx 124: MOV TEMP[1].xy, TEMP[1].xyyy 125: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D 126: MOV TEMP[2].xyz, TEMP[1].xyzx 127: MOV TEMP[3], TEMP[2] 128: ENDIF 129: MOV TEMP[0].w, TEMP[3] 130: ENDIF 131: ISLT TEMP[1].x, CONST[1].xxxx, IMM[0].xxxx 132: UIF TEMP[1].xxxx :0 133: MOV TEMP[1].xy, IN[0].xyyy 134: TEX TEMP[1], TEMP[1], SAMP[1], 2D 135: MOV TEMP[1], TEMP[1] 136: ELSE :0 137: MOV TEMP[3].x, IMM[2].xxxx 138: UADD TEMP[4].x, CONST[1].xxxx, IMM[0].yyyy 139: MUL TEMP[5].xy, IN[0].xyyy, CONST[5].xyyy 140: USEQ TEMP[6].x, TEMP[4].xxxx, IMM[0].zzzz 141: UIF TEMP[6].xxxx :0 142: MOV TEMP[6].xy, TEMP[5].xyxx 143: ELSE :0 144: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[0].wwww 145: UIF TEMP[7].xxxx :0 146: FRC TEMP[7].xy, TEMP[5].xyyy 147: RCP TEMP[8].x, CONST[5].xxxx 148: RCP TEMP[8].y, CONST[5].yyyy 149: FLR TEMP[9].xy, TEMP[5].xyyy 150: MAD TEMP[5].xy, TEMP[7].xyyy, TEMP[8].xyyy, TEMP[9].xyyy 151: ELSE :0 152: USEQ TEMP[7].x, TEMP[4].xxxx, IMM[3].xxxx 153: UIF TEMP[7].xxxx :0 154: FSGE TEMP[7].x, TEMP[5].xxxx, IMM[1].xxxx 155: UIF TEMP[7].xxxx :0 156: MUL TEMP[7].x, CONST[5].zzzz, CONST[5].xxxx 157: MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 158: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[7].xxxx 159: ELSE :0 160: FSLT TEMP[7].x, TEMP[5].xxxx, IMM[1].zzzz 161: UIF TEMP[7].xxxx :0 162: MOV TEMP[5].x, IMM[1].zzzz 163: ENDIF 164: ENDIF 165: FSGE TEMP[7].x, TEMP[5].yyyy, IMM[1].xxxx 166: UIF TEMP[7].xxxx :0 167: MUL TEMP[7].x, CONST[5].wwww, CONST[5].yyyy 168: MUL TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 169: ADD TEMP[7].x, IMM[1].xxxx, -TEMP[7].xxxx 170: MOV TEMP[5].y, TEMP[7].xxxx 171: ELSE :0 172: FSLT TEMP[7].x, TEMP[5].yyyy, IMM[1].zzzz 173: UIF TEMP[7].xxxx :0 174: MOV TEMP[5].y, IMM[1].zzzz 175: ENDIF 176: ENDIF 177: RCP TEMP[7].x, CONST[5].xxxx 178: RCP TEMP[7].y, CONST[5].yyyy 179: MUL TEMP[5].xy, TEMP[5].xyyy, TEMP[7].xyyy 180: ELSE :0 181: USEQ TEMP[4].x, TEMP[4].xxxx, IMM[3].yyyy 182: UIF TEMP[4].xxxx :0 183: FLR TEMP[4].x, TEMP[5].xxxx 184: ABS TEMP[4].x, TEMP[4].xxxx 185: MUL TEMP[7].x, TEMP[4].xxxx, IMM[1].yyyy 186: FLR TEMP[7].x, TEMP[7].xxxx 187: MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx 188: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 189: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 190: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 191: UIF TEMP[4].xxxx :0 192: FRC TEMP[4].x, TEMP[5].xxxx 193: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 194: RCP TEMP[7].x, CONST[5].xxxx 195: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 196: ADD TEMP[5].x, IMM[1].wwww, -TEMP[4].xxxx 197: ELSE :0 198: FRC TEMP[4].x, TEMP[5].xxxx 199: RCP TEMP[7].x, CONST[5].xxxx 200: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[7].xxxx 201: ENDIF 202: FLR TEMP[4].x, TEMP[5].yyyy 203: ABS TEMP[4].x, TEMP[4].xxxx 204: MUL TEMP[7].x, TEMP[4].xxxx, IMM[1].yyyy 205: FLR TEMP[7].x, TEMP[7].xxxx 206: MUL TEMP[7].x, IMM[1].wwww, TEMP[7].xxxx 207: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx 208: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 209: FSLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx 210: UIF TEMP[4].xxxx :0 211: FRC TEMP[4].x, TEMP[5].yyyy 212: ADD TEMP[4].x, IMM[1].xxxx, -TEMP[4].xxxx 213: RCP TEMP[7].x, CONST[5].yyyy 214: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 215: ADD TEMP[4].x, IMM[1].wwww, -TEMP[4].xxxx 216: MOV TEMP[5].y, TEMP[4].xxxx 217: ELSE :0 218: FRC TEMP[4].x, TEMP[5].yyyy 219: RCP TEMP[7].x, CONST[5].yyyy 220: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[7].xxxx 221: MOV TEMP[5].y, TEMP[4].xxxx 222: ENDIF 223: ENDIF 224: ENDIF 225: ENDIF 226: MOV TEMP[6].xy, TEMP[5].xyxx 227: ENDIF 228: MOV TEMP[2].xy, TEMP[6].xyxx 229: USEQ TEMP[4].x, CONST[1].xxxx, IMM[0].xxxx 230: UIF TEMP[4].xxxx :0 231: FSGE TEMP[4].x, TEMP[6].xxxx, IMM[1].zzzz 232: FSLT TEMP[5].x, TEMP[6].xxxx, IMM[1].xxxx 233: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 234: FSGE TEMP[5].x, TEMP[6].yyyy, IMM[1].zzzz 235: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 236: FSLT TEMP[5].x, TEMP[6].yyyy, IMM[1].xxxx 237: AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 238: NOT TEMP[4].x, TEMP[4].xxxx 239: UIF TEMP[4].xxxx :0 240: MOV TEMP[4].xyz, IMM[1].zzzz 241: MOV TEMP[4].w, IMM[1].zzzz 242: MOV TEMP[4], TEMP[4] 243: MOV TEMP[3].x, IMM[2].yyyy 244: ELSE :0 245: FRC TEMP[5].xy, TEMP[6].xyyy 246: RCP TEMP[6].x, CONST[5].xxxx 247: RCP TEMP[6].y, CONST[5].yyyy 248: MUL TEMP[2].xy, TEMP[5].xyyy, TEMP[6].xyyy 249: ENDIF 250: ENDIF 251: UIF TEMP[3].xxxx :0 252: MOV TEMP[2].xy, TEMP[2].xyyy 253: TEX TEMP[2], TEMP[2], SAMP[1], 2D 254: MOV TEMP[4], TEMP[2] 255: ENDIF 256: MOV TEMP[1], TEMP[4] 257: ENDIF 258: MUL TEMP[0], TEMP[0].wwww, TEMP[1] 259: MOV OUT[0], TEMP[0] 260: END ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %1, i32 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 80) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 84) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 88) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 92) %34 = getelementptr [34 x <8 x i32>] addrspace(2)* %3, i32 0, i32 1 %35 = load <8 x i32> addrspace(2)* %34, !tbaa !0 %36 = getelementptr [17 x <4 x i32>] addrspace(2)* %2, i32 0, i32 1 %37 = load <4 x i32> addrspace(2)* %36, !tbaa !0 %38 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %39 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %40 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %41 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %42 = bitcast float %24 to i32 %43 = icmp slt i32 %42, 10 %44 = sext i1 %43 to i32 %45 = bitcast i32 %44 to float %46 = bitcast float %45 to i32 %47 = icmp ne i32 %46, 0 br i1 %47, label %ENDIF, label %ELSE ELSE: ; preds = %main_body %48 = bitcast float %24 to i32 %49 = add i32 %48, -10 %50 = bitcast i32 %49 to float %51 = fmul float %40, %26 %52 = fmul float %41, %27 %53 = bitcast float %50 to i32 %54 = icmp eq i32 %53, 0 %55 = sext i1 %54 to i32 %56 = bitcast i32 %55 to float %57 = bitcast float %56 to i32 %58 = icmp ne i32 %57, 0 br i1 %58, label %ENDIF40, label %ELSE42 ENDIF: ; preds = %main_body, %ENDIF70 %temp17.0 = phi float [ %temp17.8, %ENDIF70 ], [ 0.000000e+00, %main_body ] %temp3.0 = phi float [ %.temp15.0, %ENDIF70 ], [ 1.000000e+00, %main_body ] %59 = bitcast float %25 to i32 %60 = icmp slt i32 %59, 10 %61 = sext i1 %60 to i32 %62 = bitcast i32 %61 to float %63 = bitcast float %62 to i32 %64 = icmp ne i32 %63, 0 br i1 %64, label %IF80, label %ELSE81 ELSE42: ; preds = %ELSE %65 = bitcast float %50 to i32 %66 = icmp eq i32 %65, 1 %67 = sext i1 %66 to i32 %68 = bitcast i32 %67 to float %69 = bitcast float %68 to i32 %70 = icmp ne i32 %69, 0 br i1 %70, label %IF44, label %ELSE45 ENDIF40: ; preds = %IF68, %ELSE69, %ELSE48, %ENDIF55, %IF44, %ELSE %temp17.1 = phi float [ %52, %ELSE ], [ %86, %IF44 ], [ %130, %ENDIF55 ], [ %52, %ELSE48 ], [ %174, %IF68 ], [ %176, %ELSE69 ] %temp20.0 = phi float [ %51, %ELSE ], [ %84, %IF44 ], [ %129, %ENDIF55 ], [ %51, %ELSE48 ], [ %temp16.5, %ELSE69 ], [ %temp16.5, %IF68 ] %71 = bitcast float %24 to i32 %72 = icmp eq i32 %71, 10 %73 = sext i1 %72 to i32 %74 = bitcast i32 %73 to float %75 = bitcast float %74 to i32 %76 = icmp ne i32 %75, 0 br i1 %76, label %IF71, label %ENDIF70 IF44: ; preds = %ELSE42 %77 = call float @llvm.AMDIL.fraction.(float %51) %78 = call float @llvm.AMDIL.fraction.(float %52) %79 = fdiv float 1.000000e+00, %26 %80 = fdiv float 1.000000e+00, %27 %81 = call float @floor(float %51) %82 = call float @floor(float %52) %83 = fmul float %77, %79 %84 = fadd float %83, %81 %85 = fmul float %78, %80 %86 = fadd float %85, %82 br label %ENDIF40 ELSE45: ; preds = %ELSE42 %87 = bitcast float %50 to i32 %88 = icmp eq i32 %87, 2 %89 = sext i1 %88 to i32 %90 = bitcast i32 %89 to float %91 = bitcast float %90 to i32 %92 = icmp ne i32 %91, 0 br i1 %92, label %IF47, label %ELSE48 IF47: ; preds = %ELSE45 %93 = fcmp oge float %51, 1.000000e+00 %94 = sext i1 %93 to i32 %95 = bitcast i32 %94 to float %96 = bitcast float %95 to i32 %97 = icmp ne i32 %96, 0 br i1 %97, label %IF50, label %ELSE51 ELSE48: ; preds = %ELSE45 %98 = bitcast float %50 to i32 %99 = icmp eq i32 %98, 3 %100 = sext i1 %99 to i32 %101 = bitcast i32 %100 to float %102 = bitcast float %101 to i32 %103 = icmp ne i32 %102, 0 br i1 %103, label %IF62, label %ENDIF40 IF50: ; preds = %IF47 %104 = fmul float %28, %26 %105 = fmul float %104, 5.000000e-01 %106 = fsub float -0.000000e+00, %105 %107 = fadd float 1.000000e+00, %106 br label %ENDIF49 ELSE51: ; preds = %IF47 %108 = fcmp olt float %51, 0.000000e+00 %109 = sext i1 %108 to i32 %110 = bitcast i32 %109 to float %111 = bitcast float %110 to i32 %112 = icmp ne i32 %111, 0 %. = select i1 %112, float 0.000000e+00, float %51 br label %ENDIF49 ENDIF49: ; preds = %ELSE51, %IF50 %temp16.2 = phi float [ %107, %IF50 ], [ %., %ELSE51 ] %113 = fcmp oge float %52, 1.000000e+00 %114 = sext i1 %113 to i32 %115 = bitcast i32 %114 to float %116 = bitcast float %115 to i32 %117 = icmp ne i32 %116, 0 br i1 %117, label %IF56, label %ELSE57 IF56: ; preds = %ENDIF49 %118 = fmul float %29, %27 %119 = fmul float %118, 5.000000e-01 %120 = fsub float -0.000000e+00, %119 %121 = fadd float 1.000000e+00, %120 br label %ENDIF55 ELSE57: ; preds = %ENDIF49 %122 = fcmp olt float %52, 0.000000e+00 %123 = sext i1 %122 to i32 %124 = bitcast i32 %123 to float %125 = bitcast float %124 to i32 %126 = icmp ne i32 %125, 0 %.121 = select i1 %126, float 0.000000e+00, float %52 br label %ENDIF55 ENDIF55: ; preds = %ELSE57, %IF56 %temp17.4 = phi float [ %121, %IF56 ], [ %.121, %ELSE57 ] %127 = fdiv float 1.000000e+00, %26 %128 = fdiv float 1.000000e+00, %27 %129 = fmul float %temp16.2, %127 %130 = fmul float %temp17.4, %128 br label %ENDIF40 IF62: ; preds = %ELSE48 %131 = call float @floor(float %51) %132 = call float @fabs(float %131) %133 = fmul float %132, 5.000000e-01 %134 = call float @floor(float %133) %135 = fmul float 2.000000e+00, %134 %136 = fsub float -0.000000e+00, %135 %137 = fadd float %132, %136 %138 = fsub float -0.000000e+00, %137 %139 = fadd float 1.000000e+00, %138 %140 = fcmp olt float %139, 0x3F50624DE0000000 %141 = sext i1 %140 to i32 %142 = bitcast i32 %141 to float %143 = bitcast float %142 to i32 %144 = icmp ne i32 %143, 0 %145 = call float @llvm.AMDIL.fraction.(float %51) br i1 %144, label %IF65, label %ELSE66 IF65: ; preds = %IF62 %146 = fsub float -0.000000e+00, %145 %147 = fadd float 1.000000e+00, %146 %148 = fdiv float 1.000000e+00, %26 %149 = fmul float %147, %148 %150 = fsub float -0.000000e+00, %149 %151 = fadd float 2.000000e+00, %150 br label %ENDIF64 ELSE66: ; preds = %IF62 %152 = fdiv float 1.000000e+00, %26 %153 = fmul float %145, %152 br label %ENDIF64 ENDIF64: ; preds = %ELSE66, %IF65 %temp16.5 = phi float [ %151, %IF65 ], [ %153, %ELSE66 ] %154 = call float @floor(float %52) %155 = call float @fabs(float %154) %156 = fmul float %155, 5.000000e-01 %157 = call float @floor(float %156) %158 = fmul float 2.000000e+00, %157 %159 = fsub float -0.000000e+00, %158 %160 = fadd float %155, %159 %161 = fsub float -0.000000e+00, %160 %162 = fadd float 1.000000e+00, %161 %163 = fcmp olt float %162, 0x3F50624DE0000000 %164 = sext i1 %163 to i32 %165 = bitcast i32 %164 to float %166 = bitcast float %165 to i32 %167 = icmp ne i32 %166, 0 %168 = call float @llvm.AMDIL.fraction.(float %52) br i1 %167, label %IF68, label %ELSE69 IF68: ; preds = %ENDIF64 %169 = fsub float -0.000000e+00, %168 %170 = fadd float 1.000000e+00, %169 %171 = fdiv float 1.000000e+00, %27 %172 = fmul float %170, %171 %173 = fsub float -0.000000e+00, %172 %174 = fadd float 2.000000e+00, %173 br label %ENDIF40 ELSE69: ; preds = %ENDIF64 %175 = fdiv float 1.000000e+00, %27 %176 = fmul float %168, %175 br label %ENDIF40 IF71: ; preds = %ENDIF40 %177 = fcmp oge float %temp20.0, 0.000000e+00 %178 = sext i1 %177 to i32 %179 = bitcast i32 %178 to float %180 = fcmp olt float %temp20.0, 1.000000e+00 %181 = sext i1 %180 to i32 %182 = bitcast i32 %181 to float %183 = bitcast float %179 to i32 %184 = bitcast float %182 to i32 %185 = and i32 %183, %184 %186 = bitcast i32 %185 to float %187 = fcmp oge float %temp17.1, 0.000000e+00 %188 = sext i1 %187 to i32 %189 = bitcast i32 %188 to float %190 = bitcast float %186 to i32 %191 = bitcast float %189 to i32 %192 = and i32 %190, %191 %193 = bitcast i32 %192 to float %194 = fcmp olt float %temp17.1, 1.000000e+00 %195 = sext i1 %194 to i32 %196 = bitcast i32 %195 to float %197 = bitcast float %193 to i32 %198 = bitcast float %196 to i32 %199 = and i32 %197, %198 %200 = bitcast i32 %199 to float %201 = bitcast float %200 to i32 %202 = xor i32 %201, -1 %203 = bitcast i32 %202 to float %204 = bitcast float %203 to i32 %205 = icmp ne i32 %204, 0 br i1 %205, label %ENDIF70, label %ELSE75 ENDIF70: ; preds = %ELSE75, %IF71, %ENDIF40 %temp8.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF40 ], [ 0xFFFFFFFFE0000000, %ELSE75 ], [ 0.000000e+00, %IF71 ] %temp15.0 = phi float [ 0.000000e+00, %ENDIF40 ], [ 0.000000e+00, %ELSE75 ], [ 1.000000e+00, %IF71 ] %temp17.8 = phi float [ %temp17.1, %ENDIF40 ], [ %209, %ELSE75 ], [ %temp17.1, %IF71 ] %206 = bitcast float %temp8.0 to i32 %207 = icmp ne i32 %206, 0 %.temp15.0 = select i1 %207, float 1.000000e+00, float %temp15.0 br label %ENDIF ELSE75: ; preds = %IF71 %208 = call float @llvm.AMDIL.fraction.(float %temp20.0) %209 = call float @llvm.AMDIL.fraction.(float %temp17.1) br label %ENDIF70 IF80: ; preds = %ENDIF %210 = bitcast float %38 to i32 %211 = bitcast float %39 to i32 %212 = insertelement <2 x i32> undef, i32 %210, i32 0 %213 = insertelement <2 x i32> %212, i32 %211, i32 1 %214 = bitcast <8 x i32> %35 to <32 x i8> %215 = bitcast <4 x i32> %37 to <16 x i8> %216 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %213, <32 x i8> %214, <16 x i8> %215, i32 2) %217 = extractelement <4 x float> %216, i32 0 %218 = extractelement <4 x float> %216, i32 1 %219 = extractelement <4 x float> %216, i32 2 %220 = extractelement <4 x float> %216, i32 3 br label %ENDIF79 ELSE81: ; preds = %ENDIF %221 = bitcast float %25 to i32 %222 = add i32 %221, -10 %223 = bitcast i32 %222 to float %224 = fmul float %38, %30 %225 = fmul float %39, %31 %226 = bitcast float %223 to i32 %227 = icmp eq i32 %226, 0 %228 = sext i1 %227 to i32 %229 = bitcast i32 %228 to float %230 = bitcast float %229 to i32 %231 = icmp ne i32 %230, 0 br i1 %231, label %ENDIF82, label %ELSE84 ENDIF79: ; preds = %IF119, %ENDIF112, %IF80 %temp6.2 = phi float [ %219, %IF80 ], [ %398, %IF119 ], [ 0.000000e+00, %ENDIF112 ] %temp7.0 = phi float [ %220, %IF80 ], [ %399, %IF119 ], [ 0.000000e+00, %ENDIF112 ] %temp5.2 = phi float [ %218, %IF80 ], [ %397, %IF119 ], [ %temp17.10, %ENDIF112 ] %temp4.2 = phi float [ %217, %IF80 ], [ %396, %IF119 ], [ %temp16.6, %ENDIF112 ] %232 = fmul float %temp3.0, %temp4.2 %233 = fmul float %temp3.0, %temp5.2 %234 = fmul float %temp3.0, %temp6.2 %235 = fmul float %temp3.0, %temp7.0 %236 = call i32 @llvm.SI.packf16(float %232, float %233) %237 = bitcast i32 %236 to float %238 = call i32 @llvm.SI.packf16(float %234, float %235) %239 = bitcast i32 %238 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %237, float %239, float %237, float %239) ret void ELSE84: ; preds = %ELSE81 %240 = bitcast float %223 to i32 %241 = icmp eq i32 %240, 1 %242 = sext i1 %241 to i32 %243 = bitcast i32 %242 to float %244 = bitcast float %243 to i32 %245 = icmp ne i32 %244, 0 br i1 %245, label %IF86, label %ELSE87 ENDIF82: ; preds = %IF110, %ELSE111, %ELSE90, %ENDIF97, %IF86, %ELSE81 %temp24.0 = phi float [ %224, %ELSE81 ], [ %259, %IF86 ], [ %304, %ENDIF97 ], [ %224, %ELSE90 ], [ %temp20.6, %ELSE111 ], [ %temp20.6, %IF110 ] %temp25.0 = phi float [ %225, %ELSE81 ], [ %261, %IF86 ], [ %305, %ENDIF97 ], [ %225, %ELSE90 ], [ %349, %IF110 ], [ %351, %ELSE111 ] %246 = bitcast float %25 to i32 %247 = icmp eq i32 %246, 10 %248 = sext i1 %247 to i32 %249 = bitcast i32 %248 to float %250 = bitcast float %249 to i32 %251 = icmp ne i32 %250, 0 br i1 %251, label %IF113, label %ENDIF112 IF86: ; preds = %ELSE84 %252 = call float @llvm.AMDIL.fraction.(float %224) %253 = call float @llvm.AMDIL.fraction.(float %225) %254 = fdiv float 1.000000e+00, %30 %255 = fdiv float 1.000000e+00, %31 %256 = call float @floor(float %224) %257 = call float @floor(float %225) %258 = fmul float %252, %254 %259 = fadd float %258, %256 %260 = fmul float %253, %255 %261 = fadd float %260, %257 br label %ENDIF82 ELSE87: ; preds = %ELSE84 %262 = bitcast float %223 to i32 %263 = icmp eq i32 %262, 2 %264 = sext i1 %263 to i32 %265 = bitcast i32 %264 to float %266 = bitcast float %265 to i32 %267 = icmp ne i32 %266, 0 br i1 %267, label %IF89, label %ELSE90 IF89: ; preds = %ELSE87 %268 = fcmp oge float %224, 1.000000e+00 %269 = sext i1 %268 to i32 %270 = bitcast i32 %269 to float %271 = bitcast float %270 to i32 %272 = icmp ne i32 %271, 0 br i1 %272, label %IF92, label %ELSE93 ELSE90: ; preds = %ELSE87 %273 = bitcast float %223 to i32 %274 = icmp eq i32 %273, 3 %275 = sext i1 %274 to i32 %276 = bitcast i32 %275 to float %277 = bitcast float %276 to i32 %278 = icmp ne i32 %277, 0 br i1 %278, label %IF104, label %ENDIF82 IF92: ; preds = %IF89 %279 = fmul float %32, %30 %280 = fmul float %279, 5.000000e-01 %281 = fsub float -0.000000e+00, %280 %282 = fadd float 1.000000e+00, %281 br label %ENDIF91 ELSE93: ; preds = %IF89 %283 = fcmp olt float %224, 0.000000e+00 %284 = sext i1 %283 to i32 %285 = bitcast i32 %284 to float %286 = bitcast float %285 to i32 %287 = icmp ne i32 %286, 0 %.122 = select i1 %287, float 0.000000e+00, float %224 br label %ENDIF91 ENDIF91: ; preds = %ELSE93, %IF92 %temp20.3 = phi float [ %282, %IF92 ], [ %.122, %ELSE93 ] %288 = fcmp oge float %225, 1.000000e+00 %289 = sext i1 %288 to i32 %290 = bitcast i32 %289 to float %291 = bitcast float %290 to i32 %292 = icmp ne i32 %291, 0 br i1 %292, label %IF98, label %ELSE99 IF98: ; preds = %ENDIF91 %293 = fmul float %33, %31 %294 = fmul float %293, 5.000000e-01 %295 = fsub float -0.000000e+00, %294 %296 = fadd float 1.000000e+00, %295 br label %ENDIF97 ELSE99: ; preds = %ENDIF91 %297 = fcmp olt float %225, 0.000000e+00 %298 = sext i1 %297 to i32 %299 = bitcast i32 %298 to float %300 = bitcast float %299 to i32 %301 = icmp ne i32 %300, 0 %.123 = select i1 %301, float 0.000000e+00, float %225 br label %ENDIF97 ENDIF97: ; preds = %ELSE99, %IF98 %temp21.3 = phi float [ %296, %IF98 ], [ %.123, %ELSE99 ] %302 = fdiv float 1.000000e+00, %30 %303 = fdiv float 1.000000e+00, %31 %304 = fmul float %temp20.3, %302 %305 = fmul float %temp21.3, %303 br label %ENDIF82 IF104: ; preds = %ELSE90 %306 = call float @floor(float %224) %307 = call float @fabs(float %306) %308 = fmul float %307, 5.000000e-01 %309 = call float @floor(float %308) %310 = fmul float 2.000000e+00, %309 %311 = fsub float -0.000000e+00, %310 %312 = fadd float %307, %311 %313 = fsub float -0.000000e+00, %312 %314 = fadd float 1.000000e+00, %313 %315 = fcmp olt float %314, 0x3F50624DE0000000 %316 = sext i1 %315 to i32 %317 = bitcast i32 %316 to float %318 = bitcast float %317 to i32 %319 = icmp ne i32 %318, 0 %320 = call float @llvm.AMDIL.fraction.(float %224) br i1 %319, label %IF107, label %ELSE108 IF107: ; preds = %IF104 %321 = fsub float -0.000000e+00, %320 %322 = fadd float 1.000000e+00, %321 %323 = fdiv float 1.000000e+00, %30 %324 = fmul float %322, %323 %325 = fsub float -0.000000e+00, %324 %326 = fadd float 2.000000e+00, %325 br label %ENDIF106 ELSE108: ; preds = %IF104 %327 = fdiv float 1.000000e+00, %30 %328 = fmul float %320, %327 br label %ENDIF106 ENDIF106: ; preds = %ELSE108, %IF107 %temp20.6 = phi float [ %326, %IF107 ], [ %328, %ELSE108 ] %329 = call float @floor(float %225) %330 = call float @fabs(float %329) %331 = fmul float %330, 5.000000e-01 %332 = call float @floor(float %331) %333 = fmul float 2.000000e+00, %332 %334 = fsub float -0.000000e+00, %333 %335 = fadd float %330, %334 %336 = fsub float -0.000000e+00, %335 %337 = fadd float 1.000000e+00, %336 %338 = fcmp olt float %337, 0x3F50624DE0000000 %339 = sext i1 %338 to i32 %340 = bitcast i32 %339 to float %341 = bitcast float %340 to i32 %342 = icmp ne i32 %341, 0 %343 = call float @llvm.AMDIL.fraction.(float %225) br i1 %342, label %IF110, label %ELSE111 IF110: ; preds = %ENDIF106 %344 = fsub float -0.000000e+00, %343 %345 = fadd float 1.000000e+00, %344 %346 = fdiv float 1.000000e+00, %31 %347 = fmul float %345, %346 %348 = fsub float -0.000000e+00, %347 %349 = fadd float 2.000000e+00, %348 br label %ENDIF82 ELSE111: ; preds = %ENDIF106 %350 = fdiv float 1.000000e+00, %31 %351 = fmul float %343, %350 br label %ENDIF82 IF113: ; preds = %ENDIF82 %352 = fcmp oge float %temp24.0, 0.000000e+00 %353 = sext i1 %352 to i32 %354 = bitcast i32 %353 to float %355 = fcmp olt float %temp24.0, 1.000000e+00 %356 = sext i1 %355 to i32 %357 = bitcast i32 %356 to float %358 = bitcast float %354 to i32 %359 = bitcast float %357 to i32 %360 = and i32 %358, %359 %361 = bitcast i32 %360 to float %362 = fcmp oge float %temp25.0, 0.000000e+00 %363 = sext i1 %362 to i32 %364 = bitcast i32 %363 to float %365 = bitcast float %361 to i32 %366 = bitcast float %364 to i32 %367 = and i32 %365, %366 %368 = bitcast i32 %367 to float %369 = fcmp olt float %temp25.0, 1.000000e+00 %370 = sext i1 %369 to i32 %371 = bitcast i32 %370 to float %372 = bitcast float %368 to i32 %373 = bitcast float %371 to i32 %374 = and i32 %372, %373 %375 = bitcast i32 %374 to float %376 = bitcast float %375 to i32 %377 = xor i32 %376, -1 %378 = bitcast i32 %377 to float %379 = bitcast float %378 to i32 %380 = icmp ne i32 %379, 0 br i1 %380, label %ENDIF112, label %ELSE117 ENDIF112: ; preds = %ELSE117, %IF113, %ENDIF82 %temp8.2 = phi float [ %temp24.0, %ENDIF82 ], [ %387, %ELSE117 ], [ %temp24.0, %IF113 ] %temp9.0 = phi float [ %temp25.0, %ENDIF82 ], [ %388, %ELSE117 ], [ %temp25.0, %IF113 ] %temp12.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF82 ], [ 0xFFFFFFFFE0000000, %ELSE117 ], [ 0.000000e+00, %IF113 ] %temp16.6 = phi float [ %249, %ENDIF82 ], [ %378, %ELSE117 ], [ 0.000000e+00, %IF113 ] %temp17.10 = phi float [ %temp17.0, %ENDIF82 ], [ %temp17.0, %ELSE117 ], [ 0.000000e+00, %IF113 ] %381 = bitcast float %temp12.0 to i32 %382 = icmp ne i32 %381, 0 br i1 %382, label %IF119, label %ENDIF79 ELSE117: ; preds = %IF113 %383 = call float @llvm.AMDIL.fraction.(float %temp24.0) %384 = call float @llvm.AMDIL.fraction.(float %temp25.0) %385 = fdiv float 1.000000e+00, %30 %386 = fdiv float 1.000000e+00, %31 %387 = fmul float %383, %385 %388 = fmul float %384, %386 br label %ENDIF112 IF119: ; preds = %ENDIF112 %389 = bitcast float %temp8.2 to i32 %390 = bitcast float %temp9.0 to i32 %391 = insertelement <2 x i32> undef, i32 %389, i32 0 %392 = insertelement <2 x i32> %391, i32 %390, i32 1 %393 = bitcast <8 x i32> %35 to <32 x i8> %394 = bitcast <4 x i32> %37 to <16 x i8> %395 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %392, <32 x i8> %393, <16 x i8> %394, i32 2) %396 = extractelement <4 x float> %395, i32 0 %397 = extractelement <4 x float> %395, i32 1 %398 = extractelement <4 x float> %395, i32 2 %399 = extractelement <4 x float> %395, i32 3 br label %ENDIF79 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @floor(float) #3 ; Function Attrs: readonly declare float @fabs(float) #3 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { readonly } !0 = !{!"const", null, i32 1} X: TargetRegisterInfo.cpp:189: virtual const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMatchingSuperRegClass(const llvm::TargetRegisterClass*, const llvm::TargetRegisterClass*, unsigned int) const: Assertion `A && B && "Missing register class"' failed. xinit: connection to X server lost waiting for X server to shut down