diff --git a/include/llvm/IR/IntrinsicsR600.td b/include/llvm/IR/IntrinsicsR600.td
index 5055667..a126f23 100644
--- a/include/llvm/IR/IntrinsicsR600.td
+++ b/include/llvm/IR/IntrinsicsR600.td
@@ -82,4 +82,6 @@ def int_AMDGPU_class : GCCBuiltin<"__builtin_amdgpu_class">,
 def int_AMDGPU_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
                                        "__builtin_amdgpu_read_workdim">;
 
+defm int_AMDGPU_read_global_offset : R600ReadPreloadRegisterIntrinsic_xyz <
+                                       "__builtin_amdgpu_read_global_offset">;
 } // End TargetPrefix = "AMDGPU"
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index d4f3145..8ee0f70 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -815,6 +815,12 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
 
     case Intrinsic::AMDGPU_read_workdim:
       return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4);
+    case Intrinsic::AMDGPU_read_global_offset_x:
+      return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4 + 1);
+    case Intrinsic::AMDGPU_read_global_offset_y:
+      return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4 + 2);
+    case Intrinsic::AMDGPU_read_global_offset_z:
+      return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4 + 3);
 
     case Intrinsic::r600_read_tgid_x:
       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index af38c94..6212b5f 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -883,6 +883,18 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
                           MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
                           false);
+  case Intrinsic::AMDGPU_read_global_offset_x:
+    return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
+                          MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset + 4,
+                          false);
+  case Intrinsic::AMDGPU_read_global_offset_y:
+    return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
+                          MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset + 8,
+                          false);
+  case Intrinsic::AMDGPU_read_global_offset_z:
+    return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
+                          MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset + 12,
+                          false);
 
   case Intrinsic::r600_read_tgid_x:
     return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h
index 3a0d63b..1be01ed 100644
--- a/lib/Target/R600/SIInstrInfo.h
+++ b/lib/Target/R600/SIInstrInfo.h
@@ -371,7 +371,7 @@ enum Offsets {
   GLOBAL_SIZE_Z = 20,
   LOCAL_SIZE_X = 24,
   LOCAL_SIZE_Y = 28,
-  LOCAL_SIZE_Z = 32
+  LOCAL_SIZE_Z = 32,
 };
 
 } // End namespace KernelInputOffsets