diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index f45aa76..fdff032 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -226,8 +226,16 @@ Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
 	r = drmPrimeFDToHandle(info->dri2.drm_fd, fd, &priv->handle);
 	close(fd);
 	if (r == 0) {
+	    struct drm_radeon_gem_set_tiling args = { .handle = priv->handle };
+
 	    priv->handle_valid = TRUE;
 	    *handle = priv->handle;
+
+	    if (drmCommandWriteRead(info->dri2.drm_fd,
+				    DRM_RADEON_GEM_GET_TILING, &args,
+				    sizeof(args)) == 0)
+		priv->tiling_flags = args.tiling_flags;
+
 	    return TRUE;
 	}
     }
@@ -236,6 +244,31 @@ Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
     return FALSE;
 }
 
+uint32_t radeon_get_pixmap_tiling_flags(PixmapPtr pPix)
+{
+#ifdef USE_GLAMOR
+    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
+
+    if (info->use_glamor) {
+	struct radeon_pixmap *priv = radeon_get_pixmap_private(pPix);
+
+	if (!priv || (!priv->bo && !priv->handle_valid)) {
+	    uint32_t handle;
+
+	    radeon_get_pixmap_handle(pPix, &handle);
+	    priv = radeon_get_pixmap_private(pPix);
+	}
+
+	return priv ? priv->tiling_flags : 0;
+    } else
+#endif
+    {
+	struct radeon_exa_pixmap_priv *driver_priv;
+	driver_priv = exaGetPixmapDriverPrivate(pPix);
+	return driver_priv ? driver_priv->tiling_flags : 0;
+    }
+}
+
 #ifdef RADEON_PIXMAP_SHARING
 
 Bool radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p)
diff --git a/src/radeon_bo_helper.h b/src/radeon_bo_helper.h
index 89ad4be..d4a4ee0 100644
--- a/src/radeon_bo_helper.h
+++ b/src/radeon_bo_helper.h
@@ -31,6 +31,9 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
 extern Bool
 radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle);
 
+extern uint32_t
+radeon_get_pixmap_tiling_flags(PixmapPtr pPix);
+
 extern Bool
 radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p);
 
diff --git a/src/radeon_present.c b/src/radeon_present.c
index b402110..52ca03e 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -218,6 +218,21 @@ get_drmmode_crtc(ScrnInfoPtr scrn, RRCrtcPtr crtc)
     return NULL;
 }
 
+static uint32_t
+radeon_present_get_pixmap_tiling_flags(RADEONInfoPtr info, PixmapPtr pixmap)
+{
+    uint32_t tiling_flags = radeon_get_pixmap_tiling_flags(pixmap);
+
+    /* Micro tiling is always enabled with macro tiling on >= R600, so we
+     * can ignore the micro tiling bit in that case
+     */
+    if ((tiling_flags & RADEON_TILING_MACRO) &&
+	info->ChipFamily >= CHIP_FAMILY_R600)
+	tiling_flags &= ~RADEON_TILING_MICRO;
+
+    return tiling_flags;
+}
+
 /*
  * Test to see if page flipping is possible on the target crtc
  */
@@ -228,6 +243,7 @@ radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
     ScreenPtr screen = window->drawable.pScreen;
     ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
     RADEONInfoPtr info = RADEONPTR(scrn);
+    PixmapPtr screen_pixmap;
 
     if (!scrn->vtSema)
 	return FALSE;
@@ -235,6 +251,14 @@ radeon_present_check_flip(RRCrtcPtr crtc, WindowPtr window, PixmapPtr pixmap,
     if (!info->allowPageFlip)
 	return FALSE;
 
+    /* The kernel driver doesn't handle flipping between BOs with different
+     * tiling parameters correctly yet
+     */
+    screen_pixmap = screen->GetScreenPixmap(screen);
+    if (radeon_present_get_pixmap_tiling_flags(info, pixmap) !=
+	radeon_present_get_pixmap_tiling_flags(info, screen_pixmap))
+	return FALSE;
+
     if (crtc) {
 	drmmode_crtc_private_ptr drmmode_crtc = get_drmmode_crtc(scrn, crtc);