I: unknown keys defined in configuration file: use_lib64 NIR (SSA form) for vertex shader: decl_var uniform int i (4294967295, 0) decl_var shader_in vec4 gl_Vertex (0, 0) decl_var shader_out vec4 gl_Position (0, 0) decl_var shader_out vec4 packed:var000[0],var000[1],var000[2],var000[3] (24, 4) decl_var shader_out vec4 packed:var000[4],var000[5],var000[6],var000[7] (25, 8) decl_var shader_out vec4 packed:var000[8],var000[9],var000[10],var000[11] (26, 12) decl_var shader_out vec4 packed:var000[12],var000[13],var000[14],var000[15] (27, 16) decl_var shader_out vec4 packed:var000[16],var000[17],var000[18],var000[19] (28, 20) decl_var shader_out vec4 packed:var000[20],var000[21],var000[22],var000[23] (29, 24) decl_var shader_out vec4 packed:var000[24],var000[25],var000[26],var000[27] (30, 28) decl_var shader_out vec4 packed:var000[28],var000[29],var000[30],var000[31] (31, 32) decl_var shader_out vec4 packed:var000[32],var000[33],var000[34],var000[35] (32, 36) decl_var shader_out vec4 packed:var000[36],var000[37],var000[38],var000[39] (33, 40) decl_var shader_out vec4 packed:var000[40],var000[41],var000[42],var000[43] (34, 44) decl_var shader_out vec4 packed:var000[44],var000[45],var000[46],var000[47] (35, 48) decl_var shader_out vec4 packed:var000[48],var000[49],var000[50],var000[51] (36, 52) decl_var shader_out vec4 packed:var000[52],var000[53],var000[54],var000[55] (37, 56) decl_var shader_out vec4 packed:var000[56],var000[57],var000[58],var000[59] (38, 60) decl_var shader_out vec4 packed:var000[60],var000[61],var000[62],var000[63] (39, 64) decl_var shader_out vec4 packed:var000[64],var000[65],var000[66],var000[67] (40, 68) decl_var shader_out vec4 packed:var000[68],var000[69],var000[70],var000[71] (41, 72) decl_var shader_out vec4 packed:var000[72],var000[73],var000[74],var000[75] (42, 76) decl_var shader_out vec4 packed:var000[76],var000[77],var000[78],var000[79] (43, 80) decl_var shader_out vec4 packed:var000[80],var000[81],var000[82],var000[83] (44, 84) decl_var shader_out vec4 packed:var000[84],var000[85],var000[86],var000[87] (45, 88) decl_var shader_out vec4 packed:var000[88],var000[89],var000[90],var000[91] (46, 92) decl_var shader_out vec4 packed:var000[92],var000[93],var000[94],var000[95] (47, 96) decl_var shader_out vec4 packed:var000[96],var000[97],var000[98],var000[99] (48, 100) decl_var shader_out vec4 packed:var000[100],var000[101],var000[102],var000[103] (49, 104) decl_var shader_out vec4 packed:var000[104],var000[105],var000[106],var000[107] (50, 108) decl_var shader_out vec4 packed:var000[108],var000[109],var000[110],var000[111] (51, 112) decl_var shader_out vec4 packed:var000[112],var000[113],var000[114],var000[115] (52, 116) decl_var shader_out vec4 packed:var000[116],var000[117],var000[118],var000[119] (53, 120) decl_var shader_out vec4 packed:var000[120],var000[121],var000[122],var000[123] (54, 124) decl_var shader_out vec4 packed:var000[124],var000[125],var000[126],var000[127] (55, 128) decl_overload main returning void impl main { block block_0: /* preds: */ vec1 ssa_926 = load_const (0x0000007f /* 0.000000 */) vec1 ssa_925 = load_const (0x0000007e /* 0.000000 */) vec1 ssa_924 = load_const (0x0000007d /* 0.000000 */) vec1 ssa_922 = load_const (0x0000007c /* 0.000000 */) vec1 ssa_921 = load_const (0x0000007b /* 0.000000 */) vec1 ssa_920 = load_const (0x0000007a /* 0.000000 */) vec1 ssa_919 = load_const (0x00000079 /* 0.000000 */) vec1 ssa_917 = load_const (0x00000078 /* 0.000000 */) vec1 ssa_916 = load_const (0x00000077 /* 0.000000 */) vec1 ssa_915 = load_const (0x00000076 /* 0.000000 */) vec1 ssa_914 = load_const (0x00000075 /* 0.000000 */) vec1 ssa_912 = load_const (0x00000074 /* 0.000000 */) vec1 ssa_911 = load_const (0x00000073 /* 0.000000 */) vec1 ssa_910 = load_const (0x00000072 /* 0.000000 */) vec1 ssa_909 = load_const (0x00000071 /* 0.000000 */) vec1 ssa_907 = load_const (0x00000070 /* 0.000000 */) vec1 ssa_906 = load_const (0x0000006f /* 0.000000 */) vec1 ssa_905 = load_const (0x0000006e /* 0.000000 */) vec1 ssa_904 = load_const (0x0000006d /* 0.000000 */) vec1 ssa_902 = load_const (0x0000006c /* 0.000000 */) vec1 ssa_901 = load_const (0x0000006b /* 0.000000 */) vec1 ssa_900 = load_const (0x0000006a /* 0.000000 */) vec1 ssa_899 = load_const (0x00000069 /* 0.000000 */) vec1 ssa_897 = load_const (0x00000068 /* 0.000000 */) vec1 ssa_896 = load_const (0x00000067 /* 0.000000 */) vec1 ssa_895 = load_const (0x00000066 /* 0.000000 */) vec1 ssa_894 = load_const (0x00000065 /* 0.000000 */) vec1 ssa_892 = load_const (0x00000064 /* 0.000000 */) vec1 ssa_891 = load_const (0x00000063 /* 0.000000 */) vec1 ssa_890 = load_const (0x00000062 /* 0.000000 */) vec1 ssa_889 = load_const (0x00000061 /* 0.000000 */) vec1 ssa_887 = load_const (0x00000060 /* 0.000000 */) vec1 ssa_886 = load_const (0x0000005f /* 0.000000 */) vec1 ssa_885 = load_const (0x0000005e /* 0.000000 */) vec1 ssa_884 = load_const (0x0000005d /* 0.000000 */) vec1 ssa_882 = load_const (0x0000005c /* 0.000000 */) vec1 ssa_881 = load_const (0x0000005b /* 0.000000 */) vec1 ssa_880 = load_const (0x0000005a /* 0.000000 */) vec1 ssa_879 = load_const (0x00000059 /* 0.000000 */) vec1 ssa_877 = load_const (0x00000058 /* 0.000000 */) vec1 ssa_876 = load_const (0x00000057 /* 0.000000 */) vec1 ssa_875 = load_const (0x00000056 /* 0.000000 */) vec1 ssa_874 = load_const (0x00000055 /* 0.000000 */) vec1 ssa_872 = load_const (0x00000054 /* 0.000000 */) vec1 ssa_871 = load_const (0x00000053 /* 0.000000 */) vec1 ssa_870 = load_const (0x00000052 /* 0.000000 */) vec1 ssa_869 = load_const (0x00000051 /* 0.000000 */) vec1 ssa_867 = load_const (0x00000050 /* 0.000000 */) vec1 ssa_866 = load_const (0x0000004f /* 0.000000 */) vec1 ssa_865 = load_const (0x0000004e /* 0.000000 */) vec1 ssa_864 = load_const (0x0000004d /* 0.000000 */) vec1 ssa_862 = load_const (0x0000004c /* 0.000000 */) vec1 ssa_861 = load_const (0x0000004b /* 0.000000 */) vec1 ssa_860 = load_const (0x0000004a /* 0.000000 */) vec1 ssa_859 = load_const (0x00000049 /* 0.000000 */) vec1 ssa_857 = load_const (0x00000048 /* 0.000000 */) vec1 ssa_856 = load_const (0x00000047 /* 0.000000 */) vec1 ssa_855 = load_const (0x00000046 /* 0.000000 */) vec1 ssa_854 = load_const (0x00000045 /* 0.000000 */) vec1 ssa_852 = load_const (0x00000044 /* 0.000000 */) vec1 ssa_851 = load_const (0x00000043 /* 0.000000 */) vec1 ssa_850 = load_const (0x00000042 /* 0.000000 */) vec1 ssa_849 = load_const (0x00000041 /* 0.000000 */) vec1 ssa_847 = load_const (0x00000040 /* 0.000000 */) vec1 ssa_846 = load_const (0x0000003f /* 0.000000 */) vec1 ssa_845 = load_const (0x0000003e /* 0.000000 */) vec1 ssa_844 = load_const (0x0000003d /* 0.000000 */) vec1 ssa_842 = load_const (0x0000003c /* 0.000000 */) vec1 ssa_841 = load_const (0x0000003b /* 0.000000 */) vec1 ssa_840 = load_const (0x0000003a /* 0.000000 */) vec1 ssa_839 = load_const (0x00000039 /* 0.000000 */) vec1 ssa_837 = load_const (0x00000038 /* 0.000000 */) vec1 ssa_836 = load_const (0x00000037 /* 0.000000 */) vec1 ssa_835 = load_const (0x00000036 /* 0.000000 */) vec1 ssa_834 = load_const (0x00000035 /* 0.000000 */) vec1 ssa_832 = load_const (0x00000034 /* 0.000000 */) vec1 ssa_831 = load_const (0x00000033 /* 0.000000 */) vec1 ssa_830 = load_const (0x00000032 /* 0.000000 */) vec1 ssa_829 = load_const (0x00000031 /* 0.000000 */) vec1 ssa_827 = load_const (0x00000030 /* 0.000000 */) vec1 ssa_826 = load_const (0x0000002f /* 0.000000 */) vec1 ssa_825 = load_const (0x0000002e /* 0.000000 */) vec1 ssa_824 = load_const (0x0000002d /* 0.000000 */) vec1 ssa_822 = load_const (0x0000002c /* 0.000000 */) vec1 ssa_821 = load_const (0x0000002b /* 0.000000 */) vec1 ssa_820 = load_const (0x0000002a /* 0.000000 */) vec1 ssa_819 = load_const (0x00000029 /* 0.000000 */) vec1 ssa_817 = load_const (0x00000028 /* 0.000000 */) vec1 ssa_816 = load_const (0x00000027 /* 0.000000 */) vec1 ssa_815 = load_const (0x00000026 /* 0.000000 */) vec1 ssa_814 = load_const (0x00000025 /* 0.000000 */) vec1 ssa_812 = load_const (0x00000024 /* 0.000000 */) vec1 ssa_811 = load_const (0x00000023 /* 0.000000 */) vec1 ssa_810 = load_const (0x00000022 /* 0.000000 */) vec1 ssa_809 = load_const (0x00000021 /* 0.000000 */) vec1 ssa_807 = load_const (0x00000020 /* 0.000000 */) vec1 ssa_806 = load_const (0x0000001f /* 0.000000 */) vec1 ssa_805 = load_const (0x0000001e /* 0.000000 */) vec1 ssa_804 = load_const (0x0000001d /* 0.000000 */) vec1 ssa_802 = load_const (0x0000001c /* 0.000000 */) vec1 ssa_801 = load_const (0x0000001b /* 0.000000 */) vec1 ssa_800 = load_const (0x0000001a /* 0.000000 */) vec1 ssa_799 = load_const (0x00000019 /* 0.000000 */) vec1 ssa_797 = load_const (0x00000018 /* 0.000000 */) vec1 ssa_796 = load_const (0x00000017 /* 0.000000 */) vec1 ssa_795 = load_const (0x00000016 /* 0.000000 */) vec1 ssa_794 = load_const (0x00000015 /* 0.000000 */) vec1 ssa_792 = load_const (0x00000014 /* 0.000000 */) vec1 ssa_791 = load_const (0x00000013 /* 0.000000 */) vec1 ssa_790 = load_const (0x00000012 /* 0.000000 */) vec1 ssa_789 = load_const (0x00000011 /* 0.000000 */) vec1 ssa_787 = load_const (0x00000010 /* 0.000000 */) vec1 ssa_786 = load_const (0x0000000f /* 0.000000 */) vec1 ssa_785 = load_const (0x0000000e /* 0.000000 */) vec1 ssa_784 = load_const (0x0000000d /* 0.000000 */) vec1 ssa_782 = load_const (0x0000000c /* 0.000000 */) vec1 ssa_781 = load_const (0x0000000b /* 0.000000 */) vec1 ssa_780 = load_const (0x0000000a /* 0.000000 */) vec1 ssa_779 = load_const (0x00000009 /* 0.000000 */) vec1 ssa_777 = load_const (0x00000008 /* 0.000000 */) vec1 ssa_776 = load_const (0x00000007 /* 0.000000 */) vec1 ssa_775 = load_const (0x00000006 /* 0.000000 */) vec1 ssa_774 = load_const (0x00000005 /* 0.000000 */) vec1 ssa_772 = load_const (0x00000004 /* 0.000000 */) vec1 ssa_771 = load_const (0x00000003 /* 0.000000 */) vec1 ssa_770 = load_const (0x00000002 /* 0.000000 */) vec1 ssa_769 = load_const (0x00000001 /* 0.000000 */) vec4 ssa_2826 = intrinsic load_input () () (0, 1) vec1 ssa_2827 = intrinsic load_uniform () () (0, 1) vec1 ssa_1 = i2f ssa_2827 vec1 ssa_6 = iadd ssa_2827, ssa_769 vec1 ssa_7 = i2f ssa_6 vec1 ssa_12 = iadd ssa_2827, ssa_770 vec1 ssa_13 = i2f ssa_12 vec1 ssa_18 = iadd ssa_2827, ssa_771 vec1 ssa_19 = i2f ssa_18 vec1 ssa_24 = iadd ssa_2827, ssa_772 vec1 ssa_25 = i2f ssa_24 vec1 ssa_30 = iadd ssa_2827, ssa_774 vec1 ssa_31 = i2f ssa_30 vec1 ssa_36 = iadd ssa_2827, ssa_775 vec1 ssa_37 = i2f ssa_36 vec1 ssa_42 = iadd ssa_2827, ssa_776 vec1 ssa_43 = i2f ssa_42 vec1 ssa_48 = iadd ssa_2827, ssa_777 vec1 ssa_49 = i2f ssa_48 vec1 ssa_54 = iadd ssa_2827, ssa_779 vec1 ssa_55 = i2f ssa_54 vec1 ssa_60 = iadd ssa_2827, ssa_780 vec1 ssa_61 = i2f ssa_60 vec1 ssa_66 = iadd ssa_2827, ssa_781 vec1 ssa_67 = i2f ssa_66 vec1 ssa_72 = iadd ssa_2827, ssa_782 vec1 ssa_73 = i2f ssa_72 vec1 ssa_78 = iadd ssa_2827, ssa_784 vec1 ssa_79 = i2f ssa_78 vec1 ssa_84 = iadd ssa_2827, ssa_785 vec1 ssa_85 = i2f ssa_84 vec1 ssa_90 = iadd ssa_2827, ssa_786 vec1 ssa_91 = i2f ssa_90 vec1 ssa_96 = iadd ssa_2827, ssa_787 vec1 ssa_97 = i2f ssa_96 vec1 ssa_102 = iadd ssa_2827, ssa_789 vec1 ssa_103 = i2f ssa_102 vec1 ssa_108 = iadd ssa_2827, ssa_790 vec1 ssa_109 = i2f ssa_108 vec1 ssa_114 = iadd ssa_2827, ssa_791 vec1 ssa_115 = i2f ssa_114 vec1 ssa_120 = iadd ssa_2827, ssa_792 vec1 ssa_121 = i2f ssa_120 vec1 ssa_126 = iadd ssa_2827, ssa_794 vec1 ssa_127 = i2f ssa_126 vec1 ssa_132 = iadd ssa_2827, ssa_795 vec1 ssa_133 = i2f ssa_132 vec1 ssa_138 = iadd ssa_2827, ssa_796 vec1 ssa_139 = i2f ssa_138 vec1 ssa_144 = iadd ssa_2827, ssa_797 vec1 ssa_145 = i2f ssa_144 vec1 ssa_150 = iadd ssa_2827, ssa_799 vec1 ssa_151 = i2f ssa_150 vec1 ssa_156 = iadd ssa_2827, ssa_800 vec1 ssa_157 = i2f ssa_156 vec1 ssa_162 = iadd ssa_2827, ssa_801 vec1 ssa_163 = i2f ssa_162 vec1 ssa_168 = iadd ssa_2827, ssa_802 vec1 ssa_169 = i2f ssa_168 vec1 ssa_174 = iadd ssa_2827, ssa_804 vec1 ssa_175 = i2f ssa_174 vec1 ssa_180 = iadd ssa_2827, ssa_805 vec1 ssa_181 = i2f ssa_180 vec1 ssa_186 = iadd ssa_2827, ssa_806 vec1 ssa_187 = i2f ssa_186 vec1 ssa_192 = iadd ssa_2827, ssa_807 vec1 ssa_193 = i2f ssa_192 vec1 ssa_198 = iadd ssa_2827, ssa_809 vec1 ssa_199 = i2f ssa_198 vec1 ssa_204 = iadd ssa_2827, ssa_810 vec1 ssa_205 = i2f ssa_204 vec1 ssa_210 = iadd ssa_2827, ssa_811 vec1 ssa_211 = i2f ssa_210 vec1 ssa_216 = iadd ssa_2827, ssa_812 vec1 ssa_217 = i2f ssa_216 vec1 ssa_222 = iadd ssa_2827, ssa_814 vec1 ssa_223 = i2f ssa_222 vec1 ssa_228 = iadd ssa_2827, ssa_815 vec1 ssa_229 = i2f ssa_228 vec1 ssa_234 = iadd ssa_2827, ssa_816 vec1 ssa_235 = i2f ssa_234 vec1 ssa_240 = iadd ssa_2827, ssa_817 vec1 ssa_241 = i2f ssa_240 vec1 ssa_246 = iadd ssa_2827, ssa_819 vec1 ssa_247 = i2f ssa_246 vec1 ssa_252 = iadd ssa_2827, ssa_820 vec1 ssa_253 = i2f ssa_252 vec1 ssa_258 = iadd ssa_2827, ssa_821 vec1 ssa_259 = i2f ssa_258 vec1 ssa_264 = iadd ssa_2827, ssa_822 vec1 ssa_265 = i2f ssa_264 vec1 ssa_270 = iadd ssa_2827, ssa_824 vec1 ssa_271 = i2f ssa_270 vec1 ssa_276 = iadd ssa_2827, ssa_825 vec1 ssa_277 = i2f ssa_276 vec1 ssa_282 = iadd ssa_2827, ssa_826 vec1 ssa_283 = i2f ssa_282 vec1 ssa_288 = iadd ssa_2827, ssa_827 vec1 ssa_289 = i2f ssa_288 vec1 ssa_294 = iadd ssa_2827, ssa_829 vec1 ssa_295 = i2f ssa_294 vec1 ssa_300 = iadd ssa_2827, ssa_830 vec1 ssa_301 = i2f ssa_300 vec1 ssa_306 = iadd ssa_2827, ssa_831 vec1 ssa_307 = i2f ssa_306 vec1 ssa_312 = iadd ssa_2827, ssa_832 vec1 ssa_313 = i2f ssa_312 vec1 ssa_318 = iadd ssa_2827, ssa_834 vec1 ssa_319 = i2f ssa_318 vec1 ssa_324 = iadd ssa_2827, ssa_835 vec1 ssa_325 = i2f ssa_324 vec1 ssa_330 = iadd ssa_2827, ssa_836 vec1 ssa_331 = i2f ssa_330 vec1 ssa_336 = iadd ssa_2827, ssa_837 vec1 ssa_337 = i2f ssa_336 vec1 ssa_342 = iadd ssa_2827, ssa_839 vec1 ssa_343 = i2f ssa_342 vec1 ssa_348 = iadd ssa_2827, ssa_840 vec1 ssa_349 = i2f ssa_348 vec1 ssa_354 = iadd ssa_2827, ssa_841 vec1 ssa_355 = i2f ssa_354 vec1 ssa_360 = iadd ssa_2827, ssa_842 vec1 ssa_361 = i2f ssa_360 vec1 ssa_366 = iadd ssa_2827, ssa_844 vec1 ssa_367 = i2f ssa_366 vec1 ssa_372 = iadd ssa_2827, ssa_845 vec1 ssa_373 = i2f ssa_372 vec1 ssa_378 = iadd ssa_2827, ssa_846 vec1 ssa_379 = i2f ssa_378 vec1 ssa_384 = iadd ssa_2827, ssa_847 vec1 ssa_385 = i2f ssa_384 vec1 ssa_390 = iadd ssa_2827, ssa_849 vec1 ssa_391 = i2f ssa_390 vec1 ssa_396 = iadd ssa_2827, ssa_850 vec1 ssa_397 = i2f ssa_396 vec1 ssa_402 = iadd ssa_2827, ssa_851 vec1 ssa_403 = i2f ssa_402 vec1 ssa_408 = iadd ssa_2827, ssa_852 vec1 ssa_409 = i2f ssa_408 vec1 ssa_414 = iadd ssa_2827, ssa_854 vec1 ssa_415 = i2f ssa_414 vec1 ssa_420 = iadd ssa_2827, ssa_855 vec1 ssa_421 = i2f ssa_420 vec1 ssa_426 = iadd ssa_2827, ssa_856 vec1 ssa_427 = i2f ssa_426 vec1 ssa_432 = iadd ssa_2827, ssa_857 vec1 ssa_433 = i2f ssa_432 vec1 ssa_438 = iadd ssa_2827, ssa_859 vec1 ssa_439 = i2f ssa_438 vec1 ssa_444 = iadd ssa_2827, ssa_860 vec1 ssa_445 = i2f ssa_444 vec1 ssa_450 = iadd ssa_2827, ssa_861 vec1 ssa_451 = i2f ssa_450 vec1 ssa_456 = iadd ssa_2827, ssa_862 vec1 ssa_457 = i2f ssa_456 vec1 ssa_462 = iadd ssa_2827, ssa_864 vec1 ssa_463 = i2f ssa_462 vec1 ssa_468 = iadd ssa_2827, ssa_865 vec1 ssa_469 = i2f ssa_468 vec1 ssa_474 = iadd ssa_2827, ssa_866 vec1 ssa_475 = i2f ssa_474 vec1 ssa_480 = iadd ssa_2827, ssa_867 vec1 ssa_481 = i2f ssa_480 vec1 ssa_486 = iadd ssa_2827, ssa_869 vec1 ssa_487 = i2f ssa_486 vec1 ssa_492 = iadd ssa_2827, ssa_870 vec1 ssa_493 = i2f ssa_492 vec1 ssa_498 = iadd ssa_2827, ssa_871 vec1 ssa_499 = i2f ssa_498 vec1 ssa_504 = iadd ssa_2827, ssa_872 vec1 ssa_505 = i2f ssa_504 vec1 ssa_510 = iadd ssa_2827, ssa_874 vec1 ssa_511 = i2f ssa_510 vec1 ssa_516 = iadd ssa_2827, ssa_875 vec1 ssa_517 = i2f ssa_516 vec1 ssa_522 = iadd ssa_2827, ssa_876 vec1 ssa_523 = i2f ssa_522 vec1 ssa_528 = iadd ssa_2827, ssa_877 vec1 ssa_529 = i2f ssa_528 vec1 ssa_534 = iadd ssa_2827, ssa_879 vec1 ssa_535 = i2f ssa_534 vec1 ssa_540 = iadd ssa_2827, ssa_880 vec1 ssa_541 = i2f ssa_540 vec1 ssa_546 = iadd ssa_2827, ssa_881 vec1 ssa_547 = i2f ssa_546 vec1 ssa_552 = iadd ssa_2827, ssa_882 vec1 ssa_553 = i2f ssa_552 vec1 ssa_558 = iadd ssa_2827, ssa_884 vec1 ssa_559 = i2f ssa_558 vec1 ssa_564 = iadd ssa_2827, ssa_885 vec1 ssa_565 = i2f ssa_564 vec1 ssa_570 = iadd ssa_2827, ssa_886 vec1 ssa_571 = i2f ssa_570 vec1 ssa_576 = iadd ssa_2827, ssa_887 vec1 ssa_577 = i2f ssa_576 vec1 ssa_582 = iadd ssa_2827, ssa_889 vec1 ssa_583 = i2f ssa_582 vec1 ssa_588 = iadd ssa_2827, ssa_890 vec1 ssa_589 = i2f ssa_588 vec1 ssa_594 = iadd ssa_2827, ssa_891 vec1 ssa_595 = i2f ssa_594 vec1 ssa_600 = iadd ssa_2827, ssa_892 vec1 ssa_601 = i2f ssa_600 vec1 ssa_606 = iadd ssa_2827, ssa_894 vec1 ssa_607 = i2f ssa_606 vec1 ssa_612 = iadd ssa_2827, ssa_895 vec1 ssa_613 = i2f ssa_612 vec1 ssa_618 = iadd ssa_2827, ssa_896 vec1 ssa_619 = i2f ssa_618 vec1 ssa_624 = iadd ssa_2827, ssa_897 vec1 ssa_625 = i2f ssa_624 vec1 ssa_630 = iadd ssa_2827, ssa_899 vec1 ssa_631 = i2f ssa_630 vec1 ssa_636 = iadd ssa_2827, ssa_900 vec1 ssa_637 = i2f ssa_636 vec1 ssa_642 = iadd ssa_2827, ssa_901 vec1 ssa_643 = i2f ssa_642 vec1 ssa_648 = iadd ssa_2827, ssa_902 vec1 ssa_649 = i2f ssa_648 vec1 ssa_654 = iadd ssa_2827, ssa_904 vec1 ssa_655 = i2f ssa_654 vec1 ssa_660 = iadd ssa_2827, ssa_905 vec1 ssa_661 = i2f ssa_660 vec1 ssa_666 = iadd ssa_2827, ssa_906 vec1 ssa_667 = i2f ssa_666 vec1 ssa_672 = iadd ssa_2827, ssa_907 vec1 ssa_673 = i2f ssa_672 vec1 ssa_678 = iadd ssa_2827, ssa_909 vec1 ssa_679 = i2f ssa_678 vec1 ssa_684 = iadd ssa_2827, ssa_910 vec1 ssa_685 = i2f ssa_684 vec1 ssa_690 = iadd ssa_2827, ssa_911 vec1 ssa_691 = i2f ssa_690 vec1 ssa_696 = iadd ssa_2827, ssa_912 vec1 ssa_697 = i2f ssa_696 vec1 ssa_702 = iadd ssa_2827, ssa_914 vec1 ssa_703 = i2f ssa_702 vec1 ssa_708 = iadd ssa_2827, ssa_915 vec1 ssa_709 = i2f ssa_708 vec1 ssa_714 = iadd ssa_2827, ssa_916 vec1 ssa_715 = i2f ssa_714 vec1 ssa_720 = iadd ssa_2827, ssa_917 vec1 ssa_721 = i2f ssa_720 vec1 ssa_726 = iadd ssa_2827, ssa_919 vec1 ssa_727 = i2f ssa_726 vec1 ssa_732 = iadd ssa_2827, ssa_920 vec1 ssa_733 = i2f ssa_732 vec1 ssa_738 = iadd ssa_2827, ssa_921 vec1 ssa_739 = i2f ssa_738 vec1 ssa_744 = iadd ssa_2827, ssa_922 vec1 ssa_745 = i2f ssa_744 vec1 ssa_750 = iadd ssa_2827, ssa_924 vec1 ssa_751 = i2f ssa_750 vec1 ssa_756 = iadd ssa_2827, ssa_925 vec1 ssa_757 = i2f ssa_756 vec1 ssa_762 = iadd ssa_2827, ssa_926 vec1 ssa_763 = i2f ssa_762 vec4 ssa_2665 = vec4 ssa_745, ssa_751, ssa_757, ssa_763 intrinsic store_output (ssa_2665) () (128, 1) vec4 ssa_2670 = vec4 ssa_721, ssa_727, ssa_733, ssa_739 intrinsic store_output (ssa_2670) () (124, 1) vec4 ssa_2675 = vec4 ssa_577, ssa_583, ssa_589, ssa_595 intrinsic store_output (ssa_2675) () (100, 1) vec4 ssa_2680 = vec4 ssa_553, ssa_559, ssa_565, ssa_571 intrinsic store_output (ssa_2680) () (96, 1) vec4 ssa_2685 = vec4 ssa_337, ssa_343, ssa_349, ssa_355 intrinsic store_output (ssa_2685) () (60, 1) vec4 ssa_2690 = vec4 ssa_313, ssa_319, ssa_325, ssa_331 intrinsic store_output (ssa_2690) () (56, 1) vec4 ssa_2695 = vec4 ssa_97, ssa_103, ssa_109, ssa_115 intrinsic store_output (ssa_2695) () (20, 1) vec4 ssa_2700 = vec4 ssa_73, ssa_79, ssa_85, ssa_91 intrinsic store_output (ssa_2700) () (16, 1) vec4 ssa_2705 = vec4 ssa_529, ssa_535, ssa_541, ssa_547 intrinsic store_output (ssa_2705) () (92, 1) vec4 ssa_2710 = vec4 ssa_289, ssa_295, ssa_301, ssa_307 intrinsic store_output (ssa_2710) () (52, 1) vec4 ssa_2715 = vec4 ssa_49, ssa_55, ssa_61, ssa_67 intrinsic store_output (ssa_2715) () (12, 1) vec4 ssa_2720 = vec4 ssa_697, ssa_703, ssa_709, ssa_715 intrinsic store_output (ssa_2720) () (120, 1) vec4 ssa_2725 = vec4 ssa_673, ssa_679, ssa_685, ssa_691 intrinsic store_output (ssa_2725) () (116, 1) vec4 ssa_2730 = vec4 ssa_505, ssa_511, ssa_517, ssa_523 intrinsic store_output (ssa_2730) () (88, 1) vec4 ssa_2735 = vec4 ssa_481, ssa_487, ssa_493, ssa_499 intrinsic store_output (ssa_2735) () (84, 1) vec4 ssa_2740 = vec4 ssa_265, ssa_271, ssa_277, ssa_283 intrinsic store_output (ssa_2740) () (48, 1) vec4 ssa_2745 = vec4 ssa_241, ssa_247, ssa_253, ssa_259 intrinsic store_output (ssa_2745) () (44, 1) vec4 ssa_2750 = vec4 ssa_25, ssa_31, ssa_37, ssa_43 intrinsic store_output (ssa_2750) () (8, 1) vec4 ssa_2755 = vec4 ssa_1, ssa_7, ssa_13, ssa_19 intrinsic store_output (ssa_2755) () (4, 1) vec4 ssa_2760 = vec4 ssa_649, ssa_655, ssa_661, ssa_667 intrinsic store_output (ssa_2760) () (112, 1) vec4 ssa_2765 = vec4 ssa_625, ssa_631, ssa_637, ssa_643 intrinsic store_output (ssa_2765) () (108, 1) vec4 ssa_2770 = vec4 ssa_601, ssa_607, ssa_613, ssa_619 intrinsic store_output (ssa_2770) () (104, 1) vec4 ssa_2775 = vec4 ssa_457, ssa_463, ssa_469, ssa_475 intrinsic store_output (ssa_2775) () (80, 1) vec4 ssa_2780 = vec4 ssa_433, ssa_439, ssa_445, ssa_451 intrinsic store_output (ssa_2780) () (76, 1) vec4 ssa_2785 = vec4 ssa_217, ssa_223, ssa_229, ssa_235 intrinsic store_output (ssa_2785) () (40, 1) vec4 ssa_2790 = vec4 ssa_193, ssa_199, ssa_205, ssa_211 intrinsic store_output (ssa_2790) () (36, 1) vec4 ssa_2795 = vec4 ssa_409, ssa_415, ssa_421, ssa_427 intrinsic store_output (ssa_2795) () (72, 1) vec4 ssa_2800 = vec4 ssa_169, ssa_175, ssa_181, ssa_187 intrinsic store_output (ssa_2800) () (32, 1) intrinsic store_output (ssa_2826) () (0, 1) vec4 ssa_2810 = vec4 ssa_385, ssa_391, ssa_397, ssa_403 intrinsic store_output (ssa_2810) () (68, 1) vec4 ssa_2815 = vec4 ssa_361, ssa_367, ssa_373, ssa_379 intrinsic store_output (ssa_2815) () (64, 1) vec4 ssa_2820 = vec4 ssa_145, ssa_151, ssa_157, ssa_163 intrinsic store_output (ssa_2820) () (28, 1) vec4 ssa_2825 = vec4 ssa_121, ssa_127, ssa_133, ssa_139 intrinsic store_output (ssa_2825) () (24, 1) /* succs: block_1 */ block block_1: } NIR (final form) for vertex shader: decl_var uniform int i (4294967295, 0) decl_var shader_in vec4 gl_Vertex (0, 0) decl_var shader_out vec4 gl_Position (0, 0) decl_var shader_out vec4 packed:var000[0],var000[1],var000[2],var000[3] (24, 4) decl_var shader_out vec4 packed:var000[4],var000[5],var000[6],var000[7] (25, 8) decl_var shader_out vec4 packed:var000[8],var000[9],var000[10],var000[11] (26, 12) decl_var shader_out vec4 packed:var000[12],var000[13],var000[14],var000[15] (27, 16) decl_var shader_out vec4 packed:var000[16],var000[17],var000[18],var000[19] (28, 20) decl_var shader_out vec4 packed:var000[20],var000[21],var000[22],var000[23] (29, 24) decl_var shader_out vec4 packed:var000[24],var000[25],var000[26],var000[27] (30, 28) decl_var shader_out vec4 packed:var000[28],var000[29],var000[30],var000[31] (31, 32) decl_var shader_out vec4 packed:var000[32],var000[33],var000[34],var000[35] (32, 36) decl_var shader_out vec4 packed:var000[36],var000[37],var000[38],var000[39] (33, 40) decl_var shader_out vec4 packed:var000[40],var000[41],var000[42],var000[43] (34, 44) decl_var shader_out vec4 packed:var000[44],var000[45],var000[46],var000[47] (35, 48) decl_var shader_out vec4 packed:var000[48],var000[49],var000[50],var000[51] (36, 52) decl_var shader_out vec4 packed:var000[52],var000[53],var000[54],var000[55] (37, 56) decl_var shader_out vec4 packed:var000[56],var000[57],var000[58],var000[59] (38, 60) decl_var shader_out vec4 packed:var000[60],var000[61],var000[62],var000[63] (39, 64) decl_var shader_out vec4 packed:var000[64],var000[65],var000[66],var000[67] (40, 68) decl_var shader_out vec4 packed:var000[68],var000[69],var000[70],var000[71] (41, 72) decl_var shader_out vec4 packed:var000[72],var000[73],var000[74],var000[75] (42, 76) decl_var shader_out vec4 packed:var000[76],var000[77],var000[78],var000[79] (43, 80) decl_var shader_out vec4 packed:var000[80],var000[81],var000[82],var000[83] (44, 84) decl_var shader_out vec4 packed:var000[84],var000[85],var000[86],var000[87] (45, 88) decl_var shader_out vec4 packed:var000[88],var000[89],var000[90],var000[91] (46, 92) decl_var shader_out vec4 packed:var000[92],var000[93],var000[94],var000[95] (47, 96) decl_var shader_out vec4 packed:var000[96],var000[97],var000[98],var000[99] (48, 100) decl_var shader_out vec4 packed:var000[100],var000[101],var000[102],var000[103] (49, 104) decl_var shader_out vec4 packed:var000[104],var000[105],var000[106],var000[107] (50, 108) decl_var shader_out vec4 packed:var000[108],var000[109],var000[110],var000[111] (51, 112) decl_var shader_out vec4 packed:var000[112],var000[113],var000[114],var000[115] (52, 116) decl_var shader_out vec4 packed:var000[116],var000[117],var000[118],var000[119] (53, 120) decl_var shader_out vec4 packed:var000[120],var000[121],var000[122],var000[123] (54, 124) decl_var shader_out vec4 packed:var000[124],var000[125],var000[126],var000[127] (55, 128) decl_overload main returning void impl main { decl_reg vec4 r0 decl_reg vec1 r1 decl_reg vec1 r2 decl_reg vec1 r3 decl_reg vec1 r4 decl_reg vec1 r5 decl_reg vec1 r6 decl_reg vec1 r7 decl_reg vec1 r8 decl_reg vec1 r9 decl_reg vec1 r10 decl_reg vec1 r11 decl_reg vec1 r12 decl_reg vec1 r13 decl_reg vec1 r14 decl_reg vec1 r15 decl_reg vec1 r16 decl_reg vec1 r17 decl_reg vec1 r18 decl_reg vec1 r19 decl_reg vec1 r20 decl_reg vec1 r21 decl_reg vec1 r22 decl_reg vec1 r23 decl_reg vec1 r24 decl_reg vec1 r25 decl_reg vec1 r26 decl_reg vec1 r27 decl_reg vec1 r28 decl_reg vec1 r29 decl_reg vec1 r30 decl_reg vec1 r31 decl_reg vec1 r32 decl_reg vec1 r33 decl_reg vec1 r34 decl_reg vec1 r35 decl_reg vec1 r36 decl_reg vec1 r37 decl_reg vec1 r38 decl_reg vec1 r39 decl_reg vec1 r40 decl_reg vec1 r41 decl_reg vec1 r42 decl_reg vec1 r43 decl_reg vec1 r44 decl_reg vec1 r45 decl_reg vec1 r46 decl_reg vec1 r47 decl_reg vec1 r48 decl_reg vec1 r49 decl_reg vec1 r50 decl_reg vec1 r51 decl_reg vec1 r52 decl_reg vec1 r53 decl_reg vec1 r54 decl_reg vec1 r55 decl_reg vec1 r56 decl_reg vec1 r57 decl_reg vec1 r58 decl_reg vec1 r59 decl_reg vec1 r60 decl_reg vec1 r61 decl_reg vec1 r62 decl_reg vec1 r63 decl_reg vec1 r64 decl_reg vec1 r65 decl_reg vec1 r66 decl_reg vec1 r67 decl_reg vec1 r68 decl_reg vec1 r69 decl_reg vec1 r70 decl_reg vec1 r71 decl_reg vec1 r72 decl_reg vec1 r73 decl_reg vec1 r74 decl_reg vec1 r75 decl_reg vec1 r76 decl_reg vec1 r77 decl_reg vec1 r78 decl_reg vec1 r79 decl_reg vec1 r80 decl_reg vec1 r81 decl_reg vec1 r82 decl_reg vec1 r83 decl_reg vec1 r84 decl_reg vec1 r85 decl_reg vec1 r86 decl_reg vec1 r87 decl_reg vec1 r88 decl_reg vec1 r89 decl_reg vec1 r90 decl_reg vec1 r91 decl_reg vec1 r92 decl_reg vec1 r93 decl_reg vec1 r94 decl_reg vec1 r95 decl_reg vec1 r96 decl_reg vec1 r97 decl_reg vec1 r98 decl_reg vec1 r99 decl_reg vec1 r100 decl_reg vec1 r101 decl_reg vec1 r102 decl_reg vec1 r103 decl_reg vec1 r104 decl_reg vec1 r105 decl_reg vec1 r106 decl_reg vec1 r107 decl_reg vec1 r108 decl_reg vec1 r109 decl_reg vec1 r110 decl_reg vec1 r111 decl_reg vec1 r112 decl_reg vec1 r113 decl_reg vec1 r114 decl_reg vec1 r115 decl_reg vec1 r116 decl_reg vec1 r117 decl_reg vec1 r118 decl_reg vec1 r119 decl_reg vec1 r120 decl_reg vec1 r121 decl_reg vec1 r122 decl_reg vec1 r123 decl_reg vec1 r124 decl_reg vec1 r125 decl_reg vec1 r126 decl_reg vec1 r127 decl_reg vec1 r128 decl_reg vec1 r129 decl_reg vec1 r130 decl_reg vec1 r131 decl_reg vec1 r132 decl_reg vec1 r133 decl_reg vec1 r134 decl_reg vec1 r135 decl_reg vec1 r136 decl_reg vec1 r137 decl_reg vec1 r138 decl_reg vec1 r139 decl_reg vec1 r140 decl_reg vec1 r141 decl_reg vec1 r142 decl_reg vec1 r143 decl_reg vec1 r144 decl_reg vec1 r145 decl_reg vec1 r146 decl_reg vec1 r147 decl_reg vec1 r148 decl_reg vec1 r149 decl_reg vec1 r150 decl_reg vec1 r151 decl_reg vec1 r152 decl_reg vec1 r153 decl_reg vec1 r154 decl_reg vec1 r155 decl_reg vec1 r156 decl_reg vec1 r157 decl_reg vec1 r158 decl_reg vec1 r159 decl_reg vec1 r160 decl_reg vec1 r161 decl_reg vec1 r162 decl_reg vec1 r163 decl_reg vec1 r164 decl_reg vec1 r165 decl_reg vec1 r166 decl_reg vec1 r167 decl_reg vec1 r168 decl_reg vec1 r169 decl_reg vec1 r170 decl_reg vec1 r171 decl_reg vec1 r172 decl_reg vec1 r173 decl_reg vec1 r174 decl_reg vec1 r175 decl_reg vec1 r176 decl_reg vec1 r177 decl_reg vec1 r178 decl_reg vec1 r179 decl_reg vec1 r180 decl_reg vec1 r181 decl_reg vec1 r182 decl_reg vec1 r183 decl_reg vec1 r184 decl_reg vec1 r185 decl_reg vec1 r186 decl_reg vec1 r187 decl_reg vec1 r188 decl_reg vec1 r189 decl_reg vec1 r190 decl_reg vec1 r191 decl_reg vec1 r192 decl_reg vec1 r193 decl_reg vec1 r194 decl_reg vec1 r195 decl_reg vec1 r196 decl_reg vec1 r197 decl_reg vec1 r198 decl_reg vec1 r199 decl_reg vec1 r200 decl_reg vec1 r201 decl_reg vec1 r202 decl_reg vec1 r203 decl_reg vec1 r204 decl_reg vec1 r205 decl_reg vec1 r206 decl_reg vec1 r207 decl_reg vec1 r208 decl_reg vec1 r209 decl_reg vec1 r210 decl_reg vec1 r211 decl_reg vec1 r212 decl_reg vec1 r213 decl_reg vec1 r214 decl_reg vec1 r215 decl_reg vec1 r216 decl_reg vec1 r217 decl_reg vec1 r218 decl_reg vec1 r219 decl_reg vec1 r220 decl_reg vec1 r221 decl_reg vec1 r222 decl_reg vec1 r223 decl_reg vec1 r224 decl_reg vec1 r225 decl_reg vec1 r226 decl_reg vec1 r227 decl_reg vec1 r228 decl_reg vec1 r229 decl_reg vec1 r230 decl_reg vec1 r231 decl_reg vec1 r232 decl_reg vec1 r233 decl_reg vec1 r234 decl_reg vec1 r235 decl_reg vec1 r236 decl_reg vec1 r237 decl_reg vec1 r238 decl_reg vec1 r239 decl_reg vec1 r240 decl_reg vec1 r241 decl_reg vec1 r242 decl_reg vec1 r243 decl_reg vec1 r244 decl_reg vec1 r245 decl_reg vec1 r246 decl_reg vec1 r247 decl_reg vec1 r248 decl_reg vec1 r249 decl_reg vec1 r250 decl_reg vec1 r251 decl_reg vec1 r252 decl_reg vec1 r253 decl_reg vec1 r254 decl_reg vec1 r255 decl_reg vec1 r256 decl_reg vec4 r257 decl_reg vec4 r258 decl_reg vec4 r259 decl_reg vec4 r260 decl_reg vec4 r261 decl_reg vec4 r262 decl_reg vec4 r263 decl_reg vec4 r264 decl_reg vec4 r265 decl_reg vec4 r266 decl_reg vec4 r267 decl_reg vec4 r268 decl_reg vec4 r269 decl_reg vec4 r270 decl_reg vec4 r271 decl_reg vec4 r272 decl_reg vec4 r273 decl_reg vec4 r274 decl_reg vec4 r275 decl_reg vec4 r276 decl_reg vec4 r277 decl_reg vec4 r278 decl_reg vec4 r279 decl_reg vec4 r280 decl_reg vec4 r281 decl_reg vec4 r282 decl_reg vec4 r283 decl_reg vec4 r284 decl_reg vec4 r285 decl_reg vec4 r286 decl_reg vec4 r287 decl_reg vec4 r288 block block_0: /* preds: */ vec1 ssa_926 = load_const (0x0000007f /* 0.000000 */) vec1 ssa_925 = load_const (0x0000007e /* 0.000000 */) vec1 ssa_924 = load_const (0x0000007d /* 0.000000 */) vec1 ssa_922 = load_const (0x0000007c /* 0.000000 */) vec1 ssa_921 = load_const (0x0000007b /* 0.000000 */) vec1 ssa_920 = load_const (0x0000007a /* 0.000000 */) vec1 ssa_919 = load_const (0x00000079 /* 0.000000 */) vec1 ssa_917 = load_const (0x00000078 /* 0.000000 */) vec1 ssa_916 = load_const (0x00000077 /* 0.000000 */) vec1 ssa_915 = load_const (0x00000076 /* 0.000000 */) vec1 ssa_914 = load_const (0x00000075 /* 0.000000 */) vec1 ssa_912 = load_const (0x00000074 /* 0.000000 */) vec1 ssa_911 = load_const (0x00000073 /* 0.000000 */) vec1 ssa_910 = load_const (0x00000072 /* 0.000000 */) vec1 ssa_909 = load_const (0x00000071 /* 0.000000 */) vec1 ssa_907 = load_const (0x00000070 /* 0.000000 */) vec1 ssa_906 = load_const (0x0000006f /* 0.000000 */) vec1 ssa_905 = load_const (0x0000006e /* 0.000000 */) vec1 ssa_904 = load_const (0x0000006d /* 0.000000 */) vec1 ssa_902 = load_const (0x0000006c /* 0.000000 */) vec1 ssa_901 = load_const (0x0000006b /* 0.000000 */) vec1 ssa_900 = load_const (0x0000006a /* 0.000000 */) vec1 ssa_899 = load_const (0x00000069 /* 0.000000 */) vec1 ssa_897 = load_const (0x00000068 /* 0.000000 */) vec1 ssa_896 = load_const (0x00000067 /* 0.000000 */) vec1 ssa_895 = load_const (0x00000066 /* 0.000000 */) vec1 ssa_894 = load_const (0x00000065 /* 0.000000 */) vec1 ssa_892 = load_const (0x00000064 /* 0.000000 */) vec1 ssa_891 = load_const (0x00000063 /* 0.000000 */) vec1 ssa_890 = load_const (0x00000062 /* 0.000000 */) vec1 ssa_889 = load_const (0x00000061 /* 0.000000 */) vec1 ssa_887 = load_const (0x00000060 /* 0.000000 */) vec1 ssa_886 = load_const (0x0000005f /* 0.000000 */) vec1 ssa_885 = load_const (0x0000005e /* 0.000000 */) vec1 ssa_884 = load_const (0x0000005d /* 0.000000 */) vec1 ssa_882 = load_const (0x0000005c /* 0.000000 */) vec1 ssa_881 = load_const (0x0000005b /* 0.000000 */) vec1 ssa_880 = load_const (0x0000005a /* 0.000000 */) vec1 ssa_879 = load_const (0x00000059 /* 0.000000 */) vec1 ssa_877 = load_const (0x00000058 /* 0.000000 */) vec1 ssa_876 = load_const (0x00000057 /* 0.000000 */) vec1 ssa_875 = load_const (0x00000056 /* 0.000000 */) vec1 ssa_874 = load_const (0x00000055 /* 0.000000 */) vec1 ssa_872 = load_const (0x00000054 /* 0.000000 */) vec1 ssa_871 = load_const (0x00000053 /* 0.000000 */) vec1 ssa_870 = load_const (0x00000052 /* 0.000000 */) vec1 ssa_869 = load_const (0x00000051 /* 0.000000 */) vec1 ssa_867 = load_const (0x00000050 /* 0.000000 */) vec1 ssa_866 = load_const (0x0000004f /* 0.000000 */) vec1 ssa_865 = load_const (0x0000004e /* 0.000000 */) vec1 ssa_864 = load_const (0x0000004d /* 0.000000 */) vec1 ssa_862 = load_const (0x0000004c /* 0.000000 */) vec1 ssa_861 = load_const (0x0000004b /* 0.000000 */) vec1 ssa_860 = load_const (0x0000004a /* 0.000000 */) vec1 ssa_859 = load_const (0x00000049 /* 0.000000 */) vec1 ssa_857 = load_const (0x00000048 /* 0.000000 */) vec1 ssa_856 = load_const (0x00000047 /* 0.000000 */) vec1 ssa_855 = load_const (0x00000046 /* 0.000000 */) vec1 ssa_854 = load_const (0x00000045 /* 0.000000 */) vec1 ssa_852 = load_const (0x00000044 /* 0.000000 */) vec1 ssa_851 = load_const (0x00000043 /* 0.000000 */) vec1 ssa_850 = load_const (0x00000042 /* 0.000000 */) vec1 ssa_849 = load_const (0x00000041 /* 0.000000 */) vec1 ssa_847 = load_const (0x00000040 /* 0.000000 */) vec1 ssa_846 = load_const (0x0000003f /* 0.000000 */) vec1 ssa_845 = load_const (0x0000003e /* 0.000000 */) vec1 ssa_844 = load_const (0x0000003d /* 0.000000 */) vec1 ssa_842 = load_const (0x0000003c /* 0.000000 */) vec1 ssa_841 = load_const (0x0000003b /* 0.000000 */) vec1 ssa_840 = load_const (0x0000003a /* 0.000000 */) vec1 ssa_839 = load_const (0x00000039 /* 0.000000 */) vec1 ssa_837 = load_const (0x00000038 /* 0.000000 */) vec1 ssa_836 = load_const (0x00000037 /* 0.000000 */) vec1 ssa_835 = load_const (0x00000036 /* 0.000000 */) vec1 ssa_834 = load_const (0x00000035 /* 0.000000 */) vec1 ssa_832 = load_const (0x00000034 /* 0.000000 */) vec1 ssa_831 = load_const (0x00000033 /* 0.000000 */) vec1 ssa_830 = load_const (0x00000032 /* 0.000000 */) vec1 ssa_829 = load_const (0x00000031 /* 0.000000 */) vec1 ssa_827 = load_const (0x00000030 /* 0.000000 */) vec1 ssa_826 = load_const (0x0000002f /* 0.000000 */) vec1 ssa_825 = load_const (0x0000002e /* 0.000000 */) vec1 ssa_824 = load_const (0x0000002d /* 0.000000 */) vec1 ssa_822 = load_const (0x0000002c /* 0.000000 */) vec1 ssa_821 = load_const (0x0000002b /* 0.000000 */) vec1 ssa_820 = load_const (0x0000002a /* 0.000000 */) vec1 ssa_819 = load_const (0x00000029 /* 0.000000 */) vec1 ssa_817 = load_const (0x00000028 /* 0.000000 */) vec1 ssa_816 = load_const (0x00000027 /* 0.000000 */) vec1 ssa_815 = load_const (0x00000026 /* 0.000000 */) vec1 ssa_814 = load_const (0x00000025 /* 0.000000 */) vec1 ssa_812 = load_const (0x00000024 /* 0.000000 */) vec1 ssa_811 = load_const (0x00000023 /* 0.000000 */) vec1 ssa_810 = load_const (0x00000022 /* 0.000000 */) vec1 ssa_809 = load_const (0x00000021 /* 0.000000 */) vec1 ssa_807 = load_const (0x00000020 /* 0.000000 */) vec1 ssa_806 = load_const (0x0000001f /* 0.000000 */) vec1 ssa_805 = load_const (0x0000001e /* 0.000000 */) vec1 ssa_804 = load_const (0x0000001d /* 0.000000 */) vec1 ssa_802 = load_const (0x0000001c /* 0.000000 */) vec1 ssa_801 = load_const (0x0000001b /* 0.000000 */) vec1 ssa_800 = load_const (0x0000001a /* 0.000000 */) vec1 ssa_799 = load_const (0x00000019 /* 0.000000 */) vec1 ssa_797 = load_const (0x00000018 /* 0.000000 */) vec1 ssa_796 = load_const (0x00000017 /* 0.000000 */) vec1 ssa_795 = load_const (0x00000016 /* 0.000000 */) vec1 ssa_794 = load_const (0x00000015 /* 0.000000 */) vec1 ssa_792 = load_const (0x00000014 /* 0.000000 */) vec1 ssa_791 = load_const (0x00000013 /* 0.000000 */) vec1 ssa_790 = load_const (0x00000012 /* 0.000000 */) vec1 ssa_789 = load_const (0x00000011 /* 0.000000 */) vec1 ssa_787 = load_const (0x00000010 /* 0.000000 */) vec1 ssa_786 = load_const (0x0000000f /* 0.000000 */) vec1 ssa_785 = load_const (0x0000000e /* 0.000000 */) vec1 ssa_784 = load_const (0x0000000d /* 0.000000 */) vec1 ssa_782 = load_const (0x0000000c /* 0.000000 */) vec1 ssa_781 = load_const (0x0000000b /* 0.000000 */) vec1 ssa_780 = load_const (0x0000000a /* 0.000000 */) vec1 ssa_779 = load_const (0x00000009 /* 0.000000 */) vec1 ssa_777 = load_const (0x00000008 /* 0.000000 */) vec1 ssa_776 = load_const (0x00000007 /* 0.000000 */) vec1 ssa_775 = load_const (0x00000006 /* 0.000000 */) vec1 ssa_774 = load_const (0x00000005 /* 0.000000 */) vec1 ssa_772 = load_const (0x00000004 /* 0.000000 */) vec1 ssa_771 = load_const (0x00000003 /* 0.000000 */) vec1 ssa_770 = load_const (0x00000002 /* 0.000000 */) vec1 ssa_769 = load_const (0x00000001 /* 0.000000 */) r0 = intrinsic load_input () () (0, 1) r1 = intrinsic load_uniform () () (0, 1) r2 = i2f r1 r3 = iadd r1, ssa_769 r4 = i2f r3 r5 = iadd r1, ssa_770 r6 = i2f r5 r7 = iadd r1, ssa_771 r8 = i2f r7 r9 = iadd r1, ssa_772 r10 = i2f r9 r11 = iadd r1, ssa_774 r12 = i2f r11 r13 = iadd r1, ssa_775 r14 = i2f r13 r15 = iadd r1, ssa_776 r16 = i2f r15 r17 = iadd r1, ssa_777 r18 = i2f r17 r19 = iadd r1, ssa_779 r20 = i2f r19 r21 = iadd r1, ssa_780 r22 = i2f r21 r23 = iadd r1, ssa_781 r24 = i2f r23 r25 = iadd r1, ssa_782 r26 = i2f r25 r27 = iadd r1, ssa_784 r28 = i2f r27 r29 = iadd r1, ssa_785 r30 = i2f r29 r31 = iadd r1, ssa_786 r32 = i2f r31 r33 = iadd r1, ssa_787 r34 = i2f r33 r35 = iadd r1, ssa_789 r36 = i2f r35 r37 = iadd r1, ssa_790 r38 = i2f r37 r39 = iadd r1, ssa_791 r40 = i2f r39 r41 = iadd r1, ssa_792 r42 = i2f r41 r43 = iadd r1, ssa_794 r44 = i2f r43 r45 = iadd r1, ssa_795 r46 = i2f r45 r47 = iadd r1, ssa_796 r48 = i2f r47 r49 = iadd r1, ssa_797 r50 = i2f r49 r51 = iadd r1, ssa_799 r52 = i2f r51 r53 = iadd r1, ssa_800 r54 = i2f r53 r55 = iadd r1, ssa_801 r56 = i2f r55 r57 = iadd r1, ssa_802 r58 = i2f r57 r59 = iadd r1, ssa_804 r60 = i2f r59 r61 = iadd r1, ssa_805 r62 = i2f r61 r63 = iadd r1, ssa_806 r64 = i2f r63 r65 = iadd r1, ssa_807 r66 = i2f r65 r67 = iadd r1, ssa_809 r68 = i2f r67 r69 = iadd r1, ssa_810 r70 = i2f r69 r71 = iadd r1, ssa_811 r72 = i2f r71 r73 = iadd r1, ssa_812 r74 = i2f r73 r75 = iadd r1, ssa_814 r76 = i2f r75 r77 = iadd r1, ssa_815 r78 = i2f r77 r79 = iadd r1, ssa_816 r80 = i2f r79 r81 = iadd r1, ssa_817 r82 = i2f r81 r83 = iadd r1, ssa_819 r84 = i2f r83 r85 = iadd r1, ssa_820 r86 = i2f r85 r87 = iadd r1, ssa_821 r88 = i2f r87 r89 = iadd r1, ssa_822 r90 = i2f r89 r91 = iadd r1, ssa_824 r92 = i2f r91 r93 = iadd r1, ssa_825 r94 = i2f r93 r95 = iadd r1, ssa_826 r96 = i2f r95 r97 = iadd r1, ssa_827 r98 = i2f r97 r99 = iadd r1, ssa_829 r100 = i2f r99 r101 = iadd r1, ssa_830 r102 = i2f r101 r103 = iadd r1, ssa_831 r104 = i2f r103 r105 = iadd r1, ssa_832 r106 = i2f r105 r107 = iadd r1, ssa_834 r108 = i2f r107 r109 = iadd r1, ssa_835 r110 = i2f r109 r111 = iadd r1, ssa_836 r112 = i2f r111 r113 = iadd r1, ssa_837 r114 = i2f r113 r115 = iadd r1, ssa_839 r116 = i2f r115 r117 = iadd r1, ssa_840 r118 = i2f r117 r119 = iadd r1, ssa_841 r120 = i2f r119 r121 = iadd r1, ssa_842 r122 = i2f r121 r123 = iadd r1, ssa_844 r124 = i2f r123 r125 = iadd r1, ssa_845 r126 = i2f r125 r127 = iadd r1, ssa_846 r128 = i2f r127 r129 = iadd r1, ssa_847 r130 = i2f r129 r131 = iadd r1, ssa_849 r132 = i2f r131 r133 = iadd r1, ssa_850 r134 = i2f r133 r135 = iadd r1, ssa_851 r136 = i2f r135 r137 = iadd r1, ssa_852 r138 = i2f r137 r139 = iadd r1, ssa_854 r140 = i2f r139 r141 = iadd r1, ssa_855 r142 = i2f r141 r143 = iadd r1, ssa_856 r144 = i2f r143 r145 = iadd r1, ssa_857 r146 = i2f r145 r147 = iadd r1, ssa_859 r148 = i2f r147 r149 = iadd r1, ssa_860 r150 = i2f r149 r151 = iadd r1, ssa_861 r152 = i2f r151 r153 = iadd r1, ssa_862 r154 = i2f r153 r155 = iadd r1, ssa_864 r156 = i2f r155 r157 = iadd r1, ssa_865 r158 = i2f r157 r159 = iadd r1, ssa_866 r160 = i2f r159 r161 = iadd r1, ssa_867 r162 = i2f r161 r163 = iadd r1, ssa_869 r164 = i2f r163 r165 = iadd r1, ssa_870 r166 = i2f r165 r167 = iadd r1, ssa_871 r168 = i2f r167 r169 = iadd r1, ssa_872 r170 = i2f r169 r171 = iadd r1, ssa_874 r172 = i2f r171 r173 = iadd r1, ssa_875 r174 = i2f r173 r175 = iadd r1, ssa_876 r176 = i2f r175 r177 = iadd r1, ssa_877 r178 = i2f r177 r179 = iadd r1, ssa_879 r180 = i2f r179 r181 = iadd r1, ssa_880 r182 = i2f r181 r183 = iadd r1, ssa_881 r184 = i2f r183 r185 = iadd r1, ssa_882 r186 = i2f r185 r187 = iadd r1, ssa_884 r188 = i2f r187 r189 = iadd r1, ssa_885 r190 = i2f r189 r191 = iadd r1, ssa_886 r192 = i2f r191 r193 = iadd r1, ssa_887 r194 = i2f r193 r195 = iadd r1, ssa_889 r196 = i2f r195 r197 = iadd r1, ssa_890 r198 = i2f r197 r199 = iadd r1, ssa_891 r200 = i2f r199 r201 = iadd r1, ssa_892 r202 = i2f r201 r203 = iadd r1, ssa_894 r204 = i2f r203 r205 = iadd r1, ssa_895 r206 = i2f r205 r207 = iadd r1, ssa_896 r208 = i2f r207 r209 = iadd r1, ssa_897 r210 = i2f r209 r211 = iadd r1, ssa_899 r212 = i2f r211 r213 = iadd r1, ssa_900 r214 = i2f r213 r215 = iadd r1, ssa_901 r216 = i2f r215 r217 = iadd r1, ssa_902 r218 = i2f r217 r219 = iadd r1, ssa_904 r220 = i2f r219 r221 = iadd r1, ssa_905 r222 = i2f r221 r223 = iadd r1, ssa_906 r224 = i2f r223 r225 = iadd r1, ssa_907 r226 = i2f r225 r227 = iadd r1, ssa_909 r228 = i2f r227 r229 = iadd r1, ssa_910 r230 = i2f r229 r231 = iadd r1, ssa_911 r232 = i2f r231 r233 = iadd r1, ssa_912 r234 = i2f r233 r235 = iadd r1, ssa_914 r236 = i2f r235 r237 = iadd r1, ssa_915 r238 = i2f r237 r239 = iadd r1, ssa_916 r240 = i2f r239 r241 = iadd r1, ssa_917 r242 = i2f r241 r243 = iadd r1, ssa_919 r244 = i2f r243 r245 = iadd r1, ssa_920 r246 = i2f r245 r247 = iadd r1, ssa_921 r248 = i2f r247 r249 = iadd r1, ssa_922 r250 = i2f r249 r251 = iadd r1, ssa_924 r252 = i2f r251 r253 = iadd r1, ssa_925 r254 = i2f r253 r255 = iadd r1, ssa_926 r256 = i2f r255 r257 = vec4 r250, r252, r254, r256 intrinsic store_output (r257) () (128, 1) r258 = vec4 r242, r244, r246, r248 intrinsic store_output (r258) () (124, 1) r259 = vec4 r194, r196, r198, r200 intrinsic store_output (r259) () (100, 1) r260 = vec4 r186, r188, r190, r192 intrinsic store_output (r260) () (96, 1) r261 = vec4 r114, r116, r118, r120 intrinsic store_output (r261) () (60, 1) r262 = vec4 r106, r108, r110, r112 intrinsic store_output (r262) () (56, 1) r263 = vec4 r34, r36, r38, r40 intrinsic store_output (r263) () (20, 1) r264 = vec4 r26, r28, r30, r32 intrinsic store_output (r264) () (16, 1) r265 = vec4 r178, r180, r182, r184 intrinsic store_output (r265) () (92, 1) r266 = vec4 r98, r100, r102, r104 intrinsic store_output (r266) () (52, 1) r267 = vec4 r18, r20, r22, r24 intrinsic store_output (r267) () (12, 1) r268 = vec4 r234, r236, r238, r240 intrinsic store_output (r268) () (120, 1) r269 = vec4 r226, r228, r230, r232 intrinsic store_output (r269) () (116, 1) r270 = vec4 r170, r172, r174, r176 intrinsic store_output (r270) () (88, 1) r271 = vec4 r162, r164, r166, r168 intrinsic store_output (r271) () (84, 1) r272 = vec4 r90, r92, r94, r96 intrinsic store_output (r272) () (48, 1) r273 = vec4 r82, r84, r86, r88 intrinsic store_output (r273) () (44, 1) r274 = vec4 r10, r12, r14, r16 intrinsic store_output (r274) () (8, 1) r275 = vec4 r2, r4, r6, r8 intrinsic store_output (r275) () (4, 1) r276 = vec4 r218, r220, r222, r224 intrinsic store_output (r276) () (112, 1) r277 = vec4 r210, r212, r214, r216 intrinsic store_output (r277) () (108, 1) r278 = vec4 r202, r204, r206, r208 intrinsic store_output (r278) () (104, 1) r279 = vec4 r154, r156, r158, r160 intrinsic store_output (r279) () (80, 1) r280 = vec4 r146, r148, r150, r152 intrinsic store_output (r280) () (76, 1) r281 = vec4 r74, r76, r78, r80 intrinsic store_output (r281) () (40, 1) r282 = vec4 r66, r68, r70, r72 intrinsic store_output (r282) () (36, 1) r283 = vec4 r138, r140, r142, r144 intrinsic store_output (r283) () (72, 1) r284 = vec4 r58, r60, r62, r64 intrinsic store_output (r284) () (32, 1) intrinsic store_output (r0) () (0, 1) r285 = vec4 r130, r132, r134, r136 intrinsic store_output (r285) () (68, 1) r286 = vec4 r122, r124, r126, r128 intrinsic store_output (r286) () (64, 1) r287 = vec4 r50, r52, r54, r56 intrinsic store_output (r287) () (28, 1) r288 = vec4 r42, r44, r46, r48 intrinsic store_output (r288) () (24, 1) /* succs: block_1 */ block block_1: } GLSL IR for native vertex shader 3: ( (declare (shader_out ) vec4 gl_Position) (declare (temporary ) vec4 gl_Position) (declare (shader_out ) vec4 packed:var000[0],var000[1],var000[2],var000[3]) (declare (temporary ) vec4 packed:var000[0],var000[1],var000[2],var000[3]) (declare (shader_out ) vec4 packed:var000[4],var000[5],var000[6],var000[7]) (declare (temporary ) vec4 packed:var000[4],var000[5],var000[6],var000[7]) (declare (shader_out ) vec4 packed:var000[8],var000[9],var000[10],var000[11]) (declare (temporary ) vec4 packed:var000[8],var000[9],var000[10],var000[11]) (declare (shader_out ) vec4 packed:var000[12],var000[13],var000[14],var000[15]) (declare (temporary ) vec4 packed:var000[12],var000[13],var000[14],var000[15]) (declare (shader_out ) vec4 packed:var000[16],var000[17],var000[18],var000[19]) (declare (temporary ) vec4 packed:var000[16],var000[17],var000[18],var000[19]) (declare (shader_out ) vec4 packed:var000[20],var000[21],var000[22],var000[23]) (declare (temporary ) vec4 packed:var000[20],var000[21],var000[22],var000[23]) (declare (shader_out ) vec4 packed:var000[24],var000[25],var000[26],var000[27]) (declare (temporary ) vec4 packed:var000[24],var000[25],var000[26],var000[27]) (declare (shader_out ) vec4 packed:var000[28],var000[29],var000[30],var000[31]) (declare (temporary ) vec4 packed:var000[28],var000[29],var000[30],var000[31]) (declare (shader_out ) vec4 packed:var000[32],var000[33],var000[34],var000[35]) (declare (temporary ) vec4 packed:var000[32],var000[33],var000[34],var000[35]) (declare (shader_out ) vec4 packed:var000[36],var000[37],var000[38],var000[39]) (declare (temporary ) vec4 packed:var000[36],var000[37],var000[38],var000[39]) (declare (shader_out ) vec4 packed:var000[40],var000[41],var000[42],var000[43]) (declare (temporary ) vec4 packed:var000[40],var000[41],var000[42],var000[43]) (declare (shader_out ) vec4 packed:var000[44],var000[45],var000[46],var000[47]) (declare (temporary ) vec4 packed:var000[44],var000[45],var000[46],var000[47]) (declare (shader_out ) vec4 packed:var000[48],var000[49],var000[50],var000[51]) (declare (temporary ) vec4 packed:var000[48],var000[49],var000[50],var000[51]) (declare (shader_out ) vec4 packed:var000[52],var000[53],var000[54],var000[55]) (declare (temporary ) vec4 packed:var000[52],var000[53],var000[54],var000[55]) (declare (shader_out ) vec4 packed:var000[56],var000[57],var000[58],var000[59]) (declare (temporary ) vec4 packed:var000[56],var000[57],var000[58],var000[59]) (declare (shader_out ) vec4 packed:var000[60],var000[61],var000[62],var000[63]) (declare (temporary ) vec4 packed:var000[60],var000[61],var000[62],var000[63]) (declare (shader_out ) vec4 packed:var000[64],var000[65],var000[66],var000[67]) (declare (temporary ) vec4 packed:var000[64],var000[65],var000[66],var000[67]) (declare (shader_out ) vec4 packed:var000[68],var000[69],var000[70],var000[71]) (declare (temporary ) vec4 packed:var000[68],var000[69],var000[70],var000[71]) (declare (shader_out ) vec4 packed:var000[72],var000[73],var000[74],var000[75]) (declare (temporary ) vec4 packed:var000[72],var000[73],var000[74],var000[75]) (declare (shader_out ) vec4 packed:var000[76],var000[77],var000[78],var000[79]) (declare (temporary ) vec4 packed:var000[76],var000[77],var000[78],var000[79]) (declare (shader_out ) vec4 packed:var000[80],var000[81],var000[82],var000[83]) (declare (temporary ) vec4 packed:var000[80],var000[81],var000[82],var000[83]) (declare (shader_out ) vec4 packed:var000[84],var000[85],var000[86],var000[87]) (declare (temporary ) vec4 packed:var000[84],var000[85],var000[86],var000[87]) (declare (shader_out ) vec4 packed:var000[88],var000[89],var000[90],var000[91]) (declare (temporary ) vec4 packed:var000[88],var000[89],var000[90],var000[91]) (declare (shader_out ) vec4 packed:var000[92],var000[93],var000[94],var000[95]) (declare (temporary ) vec4 packed:var000[92],var000[93],var000[94],var000[95]) (declare (shader_out ) vec4 packed:var000[96],var000[97],var000[98],var000[99]) (declare (temporary ) vec4 packed:var000[96],var000[97],var000[98],var000[99]) (declare (shader_out ) vec4 packed:var000[100],var000[101],var000[102],var000[103]) (declare (temporary ) vec4 packed:var000[100],var000[101],var000[102],var000[103]) (declare (shader_out ) vec4 packed:var000[104],var000[105],var000[106],var000[107]) (declare (temporary ) vec4 packed:var000[104],var000[105],var000[106],var000[107]) (declare (shader_out ) vec4 packed:var000[108],var000[109],var000[110],var000[111]) (declare (temporary ) vec4 packed:var000[108],var000[109],var000[110],var000[111]) (declare (shader_out ) vec4 packed:var000[112],var000[113],var000[114],var000[115]) (declare (temporary ) vec4 packed:var000[112],var000[113],var000[114],var000[115]) (declare (shader_out ) vec4 packed:var000[116],var000[117],var000[118],var000[119]) (declare (temporary ) vec4 packed:var000[116],var000[117],var000[118],var000[119]) (declare (shader_out ) vec4 packed:var000[120],var000[121],var000[122],var000[123]) (declare (temporary ) vec4 packed:var000[120],var000[121],var000[122],var000[123]) (declare (shader_out ) vec4 packed:var000[124],var000[125],var000[126],var000[127]) (declare (temporary ) vec4 packed:var000[124],var000[125],var000[126],var000[127]) (declare (shader_in ) vec4 gl_Vertex) (declare (uniform ) int i) (function main (signature void (parameters ) ( (assign (xyzw) (var_ref gl_Position) (var_ref gl_Vertex) ) (assign (x) (var_ref packed:var000[0],var000[1],var000[2],var000[3]) (expression float i2f (var_ref i) ) ) (assign (y) (var_ref packed:var000[0],var000[1],var000[2],var000[3]) (expression float i2f (expression int + (var_ref i) (constant int (1)) ) ) ) (assign (z) (var_ref packed:var000[0],var000[1],var000[2],var000[3]) (expression float i2f (expression int + (var_ref i) (constant int (2)) ) ) ) (assign (w) (var_ref packed:var000[0],var000[1],var000[2],var000[3]) (expression float i2f (expression int + (var_ref i) (constant int (3)) ) ) ) (assign (x) (var_ref packed:var000[4],var000[5],var000[6],var000[7]) (expression float i2f (expression int + (var_ref i) (constant int (4)) ) ) ) (assign (y) (var_ref packed:var000[4],var000[5],var000[6],var000[7]) (expression float i2f (expression int + (var_ref i) (constant int (5)) ) ) ) (assign (z) (var_ref packed:var000[4],var000[5],var000[6],var000[7]) (expression float i2f (expression int + (var_ref i) (constant int (6)) ) ) ) (assign (w) (var_ref packed:var000[4],var000[5],var000[6],var000[7]) (expression float i2f (expression int + (var_ref i) (constant int (7)) ) ) ) (assign (x) (var_ref packed:var000[8],var000[9],var000[10],var000[11]) (expression float i2f (expression int + (var_ref i) (constant int (8)) ) ) ) (assign (y) (var_ref packed:var000[8],var000[9],var000[10],var000[11]) (expression float i2f (expression int + (var_ref i) (constant int (9)) ) ) ) (assign (z) (var_ref packed:var000[8],var000[9],var000[10],var000[11]) (expression float i2f (expression int + (var_ref i) (constant int (10)) ) ) ) (assign (w) (var_ref packed:var000[8],var000[9],var000[10],var000[11]) (expression float i2f (expression int + (var_ref i) (constant int (11)) ) ) ) (assign (x) (var_ref packed:var000[12],var000[13],var000[14],var000[15]) (expression float i2f (expression int + (var_ref i) (constant int (12)) ) ) ) (assign (y) (var_ref packed:var000[12],var000[13],var000[14],var000[15]) (expression float i2f (expression int + (var_ref i) (constant int (13)) ) ) ) (assign (z) (var_ref packed:var000[12],var000[13],var000[14],var000[15]) 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(expression float i2f (expression int + (var_ref i) (constant int (124)) ) ) ) (assign (y) (var_ref packed:var000[124],var000[125],var000[126],var000[127]) (expression float i2f (expression int + (var_ref i) (constant int (125)) ) ) ) (assign (z) (var_ref packed:var000[124],var000[125],var000[126],var000[127]) (expression float i2f (expression int + (var_ref i) (constant int (126)) ) ) ) (assign (w) (var_ref packed:var000[124],var000[125],var000[126],var000[127]) (expression float i2f (expression int + (var_ref i) (constant int (127)) ) ) ) (assign (xyzw) (var_ref packed:var000[124],var000[125],var000[126],var000[127]@2) (var_ref packed:var000[124],var000[125],var000[126],var000[127]) ) (assign (xyzw) (var_ref packed:var000[120],var000[121],var000[122],var000[123]@3) (var_ref packed:var000[120],var000[121],var000[122],var000[123]) ) (assign (xyzw) (var_ref packed:var000[96],var000[97],var000[98],var000[99]@4) (var_ref packed:var000[96],var000[97],var000[98],var000[99]) ) (assign (xyzw) (var_ref packed:var000[92],var000[93],var000[94],var000[95]@5) (var_ref packed:var000[92],var000[93],var000[94],var000[95]) ) (assign (xyzw) (var_ref packed:var000[56],var000[57],var000[58],var000[59]@6) (var_ref packed:var000[56],var000[57],var000[58],var000[59]) ) (assign (xyzw) (var_ref packed:var000[52],var000[53],var000[54],var000[55]@7) (var_ref packed:var000[52],var000[53],var000[54],var000[55]) ) (assign (xyzw) (var_ref packed:var000[16],var000[17],var000[18],var000[19]@8) (var_ref packed:var000[16],var000[17],var000[18],var000[19]) ) (assign (xyzw) (var_ref packed:var000[12],var000[13],var000[14],var000[15]@9) (var_ref packed:var000[12],var000[13],var000[14],var000[15]) ) (assign (xyzw) (var_ref packed:var000[88],var000[89],var000[90],var000[91]@10) (var_ref packed:var000[88],var000[89],var000[90],var000[91]) ) (assign (xyzw) (var_ref packed:var000[48],var000[49],var000[50],var000[51]@11) (var_ref packed:var000[48],var000[49],var000[50],var000[51]) ) (assign (xyzw) (var_ref packed:var000[8],var000[9],var000[10],var000[11]@12) (var_ref packed:var000[8],var000[9],var000[10],var000[11]) ) (assign (xyzw) (var_ref packed:var000[116],var000[117],var000[118],var000[119]@13) (var_ref packed:var000[116],var000[117],var000[118],var000[119]) ) (assign (xyzw) (var_ref packed:var000[112],var000[113],var000[114],var000[115]@14) (var_ref packed:var000[112],var000[113],var000[114],var000[115]) ) (assign (xyzw) (var_ref packed:var000[84],var000[85],var000[86],var000[87]@15) (var_ref packed:var000[84],var000[85],var000[86],var000[87]) ) (assign (xyzw) (var_ref packed:var000[80],var000[81],var000[82],var000[83]@16) (var_ref packed:var000[80],var000[81],var000[82],var000[83]) ) (assign (xyzw) (var_ref packed:var000[44],var000[45],var000[46],var000[47]@17) (var_ref packed:var000[44],var000[45],var000[46],var000[47]) ) (assign (xyzw) (var_ref packed:var000[40],var000[41],var000[42],var000[43]@18) (var_ref packed:var000[40],var000[41],var000[42],var000[43]) ) (assign (xyzw) (var_ref packed:var000[4],var000[5],var000[6],var000[7]@19) (var_ref packed:var000[4],var000[5],var000[6],var000[7]) ) (assign (xyzw) (var_ref packed:var000[0],var000[1],var000[2],var000[3]@20) (var_ref packed:var000[0],var000[1],var000[2],var000[3]) ) (assign (xyzw) (var_ref packed:var000[108],var000[109],var000[110],var000[111]@21) (var_ref packed:var000[108],var000[109],var000[110],var000[111]) ) (assign (xyzw) (var_ref packed:var000[104],var000[105],var000[106],var000[107]@22) (var_ref packed:var000[104],var000[105],var000[106],var000[107]) ) (assign (xyzw) (var_ref packed:var000[100],var000[101],var000[102],var000[103]@23) (var_ref packed:var000[100],var000[101],var000[102],var000[103]) ) (assign (xyzw) (var_ref packed:var000[76],var000[77],var000[78],var000[79]@24) (var_ref packed:var000[76],var000[77],var000[78],var000[79]) ) (assign (xyzw) (var_ref packed:var000[72],var000[73],var000[74],var000[75]@25) (var_ref packed:var000[72],var000[73],var000[74],var000[75]) ) (assign (xyzw) (var_ref packed:var000[36],var000[37],var000[38],var000[39]@26) (var_ref packed:var000[36],var000[37],var000[38],var000[39]) ) (assign (xyzw) (var_ref packed:var000[32],var000[33],var000[34],var000[35]@27) (var_ref packed:var000[32],var000[33],var000[34],var000[35]) ) (assign (xyzw) (var_ref packed:var000[68],var000[69],var000[70],var000[71]@28) (var_ref packed:var000[68],var000[69],var000[70],var000[71]) ) (assign (xyzw) (var_ref packed:var000[28],var000[29],var000[30],var000[31]@29) (var_ref packed:var000[28],var000[29],var000[30],var000[31]) ) (assign (xyzw) (var_ref gl_Position@30) (var_ref gl_Position) ) (assign (xyzw) (var_ref packed:var000[64],var000[65],var000[66],var000[67]@31) (var_ref packed:var000[64],var000[65],var000[66],var000[67]) ) (assign (xyzw) (var_ref packed:var000[60],var000[61],var000[62],var000[63]@32) (var_ref packed:var000[60],var000[61],var000[62],var000[63]) ) (assign (xyzw) (var_ref packed:var000[24],var000[25],var000[26],var000[27]@33) (var_ref packed:var000[24],var000[25],var000[26],var000[27]) ) (assign (xyzw) (var_ref packed:var000[20],var000[21],var000[22],var000[23]@34) (var_ref packed:var000[20],var000[21],var000[22],var000[23]) ) )) ) ) VS8 estimated execution time: 2130 cycles Native code for unnamed vertex shader 3 SIMD8 shader: 518 instructions. 0 loops. 45:45 spills:fills. Promoted 0 constants. Compacted 8288 to 5008 bytes (40%) START B0 add(8) g7<1>D g2<0,1,0>D 1D { align1 1Q compacted }; mov(8) g13<1>F g7<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g13<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000000cUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g9<1>D g2<0,1,0>D 2D { align1 1Q compacted }; mov(8) g14<1>F g9<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g14<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000000eUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g11<1>D g2<0,1,0>D 3D { align1 1Q compacted }; mov(8) g15<1>F g11<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g15<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000010UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g13<1>D g2<0,1,0>D 4D { align1 1Q compacted }; mov(8) g112<1>F g13<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g112<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000014UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g15<1>D g2<0,1,0>D 5D { align1 1Q compacted }; mov(8) g113<1>F g15<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g113<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000016UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g17<1>D g2<0,1,0>D 6D { align1 1Q compacted }; mov(8) g114<1>F g17<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g114<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000018UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g19<1>D g2<0,1,0>D 7D { align1 1Q compacted }; mov(8) g115<1>F g19<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g115<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000001aUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g21<1>D g2<0,1,0>D 8D { align1 1Q compacted }; mov(8) g116<1>F g21<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g116<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000001cUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g23<1>D g2<0,1,0>D 9D { align1 1Q compacted }; mov(8) g117<1>F g23<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g117<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000001eUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g25<1>D g2<0,1,0>D 10D { align1 1Q compacted }; mov(8) g118<1>F g25<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g118<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000020UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g27<1>D g2<0,1,0>D 11D { align1 1Q compacted }; mov(8) g119<1>F g27<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g119<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000022UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g29<1>D g2<0,1,0>D 12D { align1 1Q compacted }; mov(8) g121<1>F g29<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g121<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000026UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g31<1>D g2<0,1,0>D 13D { align1 1Q compacted }; mov(8) g122<1>F g31<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g122<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000028UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g33<1>D g2<0,1,0>D 14D { align1 1Q compacted }; mov(8) g123<1>F g33<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g123<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000002aUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g35<1>D g2<0,1,0>D 15D { align1 1Q compacted }; mov(8) g124<1>F g35<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g124<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000002cUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g37<1>D g2<0,1,0>D 16D { align1 1Q compacted }; mov(8) g125<1>F g37<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g125<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000002eUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g39<1>D g2<0,1,0>D 17D { align1 1Q compacted }; mov(8) g7<1>F g39<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g7<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000030UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g41<1>D g2<0,1,0>D 18D { align1 1Q compacted }; mov(8) g8<1>F g41<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g8<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000032UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g43<1>D g2<0,1,0>D 19D { align1 1Q compacted }; mov(8) g9<1>F g43<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g9<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000034UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g45<1>D g2<0,1,0>D 20D { align1 1Q compacted }; mov(8) g107<1>F g45<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g107<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000038UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g47<1>D g2<0,1,0>D 21D { align1 1Q compacted }; mov(8) g108<1>F g47<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g108<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000003aUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g49<1>D g2<0,1,0>D 22D { align1 1Q compacted }; mov(8) g109<1>F g49<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g109<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000003cUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g51<1>D g2<0,1,0>D 23D { align1 1Q compacted }; mov(8) g110<1>F g51<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g110<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000003eUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g53<1>D g2<0,1,0>D 24D { align1 1Q compacted }; mov(8) g111<1>F g53<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g111<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000040UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g55<1>D g2<0,1,0>D 25D { align1 1Q compacted }; mov(8) g112<1>F g55<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g112<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000042UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g57<1>D g2<0,1,0>D 26D { align1 1Q compacted }; mov(8) g113<1>F g57<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g113<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000044UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g59<1>D g2<0,1,0>D 27D { align1 1Q compacted }; mov(8) g114<1>F g59<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g114<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000046UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g61<1>D g2<0,1,0>D 28D { align1 1Q compacted }; mov(8) g116<1>F g61<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g116<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000004aUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g63<1>D g2<0,1,0>D 29D { align1 1Q compacted }; mov(8) g117<1>F g63<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g117<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000004cUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g65<1>D g2<0,1,0>D 30D { align1 1Q compacted }; mov(8) g118<1>F g65<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g118<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000004eUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g67<1>D g2<0,1,0>D 31D { align1 1Q compacted }; mov(8) g119<1>F g67<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g119<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000050UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g69<1>D g2<0,1,0>D 32D { align1 1Q compacted }; mov(8) g120<1>F g69<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g120<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000052UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g71<1>D g2<0,1,0>D 33D { align1 1Q compacted }; mov(8) g121<1>F g71<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g121<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000054UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g73<1>D g2<0,1,0>D 34D { align1 1Q compacted }; mov(8) g122<1>F g73<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g122<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000056UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g75<1>D g2<0,1,0>D 35D { align1 1Q compacted }; mov(8) g123<1>F g75<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>UD g123<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000058UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; add(8) g77<1>D g2<0,1,0>D 36D { align1 1Q compacted }; add(8) g79<1>D g2<0,1,0>D 37D { align1 1Q compacted }; add(8) g81<1>D g2<0,1,0>D 38D { align1 1Q compacted }; add(8) g83<1>D g2<0,1,0>D 39D { align1 1Q compacted }; add(8) g85<1>D g2<0,1,0>D 40D { align1 1Q compacted }; add(8) g87<1>D g2<0,1,0>D 41D { align1 1Q compacted }; add(8) g89<1>D g2<0,1,0>D 42D { align1 1Q compacted }; add(8) g91<1>D g2<0,1,0>D 43D { align1 1Q compacted }; add(8) g93<1>D g2<0,1,0>D 44D { align1 1Q compacted }; add(8) g95<1>D g2<0,1,0>D 45D { align1 1Q compacted }; add(8) g97<1>D g2<0,1,0>D 46D { align1 1Q compacted }; add(8) g99<1>D g2<0,1,0>D 47D { align1 1Q compacted }; add(8) g101<1>D g2<0,1,0>D 48D { align1 1Q compacted }; add(8) g103<1>D g2<0,1,0>D 49D { align1 1Q compacted }; add(8) g105<1>D g2<0,1,0>D 50D { align1 1Q compacted }; add(8) g107<1>D g2<0,1,0>D 51D { align1 1Q compacted }; add(8) g109<1>D g2<0,1,0>D 52D { align1 1Q compacted }; add(8) g111<1>D g2<0,1,0>D 53D { align1 1Q compacted }; add(8) g113<1>D g2<0,1,0>D 54D { align1 1Q compacted }; add(8) g115<1>D g2<0,1,0>D 55D { align1 1Q compacted }; add(8) g117<1>D g2<0,1,0>D 56D { align1 1Q compacted }; add(8) g119<1>D g2<0,1,0>D 57D { align1 1Q compacted }; add(8) g121<1>D g2<0,1,0>D 58D { align1 1Q compacted }; add(8) g125<1>D g2<0,1,0>D 60D { align1 1Q compacted }; add(8) g43<1>D g2<0,1,0>D 61D { align1 1Q compacted }; add(8) g45<1>D g2<0,1,0>D 62D { align1 1Q compacted }; add(8) g47<1>D g2<0,1,0>D 63D { align1 1Q compacted }; add(8) g49<1>D g2<0,1,0>D 64D { align1 1Q compacted }; add(8) g51<1>D g2<0,1,0>D 65D { align1 1Q compacted }; add(8) g53<1>D g2<0,1,0>D 66D { align1 1Q compacted }; add(8) g55<1>D g2<0,1,0>D 67D { align1 1Q compacted }; add(8) g57<1>D g2<0,1,0>D 68D { align1 1Q compacted }; add(8) g59<1>D g2<0,1,0>D 69D { align1 1Q compacted }; add(8) g61<1>D g2<0,1,0>D 70D { align1 1Q compacted }; add(8) g63<1>D g2<0,1,0>D 71D { align1 1Q compacted }; add(8) g65<1>D g2<0,1,0>D 72D { align1 1Q compacted }; add(8) g67<1>D g2<0,1,0>D 73D { align1 1Q compacted }; add(8) g69<1>D g2<0,1,0>D 74D { align1 1Q compacted }; add(8) g71<1>D g2<0,1,0>D 75D { align1 1Q compacted }; add(8) g73<1>D g2<0,1,0>D 76D { align1 1Q compacted }; add(8) g75<1>D g2<0,1,0>D 77D { align1 1Q compacted }; add(8) g88<1>D g2<0,1,0>D 103D { align1 1Q compacted }; add(8) g90<1>D g2<0,1,0>D 104D { align1 1Q compacted }; add(8) g92<1>D g2<0,1,0>D 105D { align1 1Q compacted }; add(8) g94<1>D g2<0,1,0>D 106D { align1 1Q compacted }; add(8) g96<1>D g2<0,1,0>D 107D { align1 1Q compacted }; add(8) g98<1>D g2<0,1,0>D 108D { align1 1Q compacted }; add(8) g100<1>D g2<0,1,0>D 109D { align1 1Q compacted }; add(8) g102<1>D g2<0,1,0>D 110D { align1 1Q compacted }; add(8) g104<1>D g2<0,1,0>D 111D { align1 1Q compacted }; add(8) g106<1>D g2<0,1,0>D 112D { align1 1Q compacted }; add(8) g108<1>D g2<0,1,0>D 113D { align1 1Q compacted }; add(8) g110<1>D g2<0,1,0>D 114D { align1 1Q compacted }; add(8) g112<1>D g2<0,1,0>D 115D { align1 1Q compacted }; add(8) g114<1>D g2<0,1,0>D 116D { align1 1Q compacted }; add(8) g116<1>D g2<0,1,0>D 117D { align1 1Q compacted }; add(8) g118<1>D g2<0,1,0>D 118D { align1 1Q compacted }; add(8) g120<1>D g2<0,1,0>D 119D { align1 1Q compacted }; add(8) g122<1>D g2<0,1,0>D 120D { align1 1Q compacted }; add(8) g124<1>D g2<0,1,0>D 121D { align1 1Q compacted }; add(8) g123<1>D g2<0,1,0>D 59D { align1 1Q compacted }; mov(8) g8<1>F g77<8,8,1>D { align1 1Q compacted }; mov(8) g9<1>F g79<8,8,1>D { align1 1Q compacted }; mov(8) g10<1>F g81<8,8,1>D { align1 1Q compacted }; mov(8) g11<1>F g83<8,8,1>D { align1 1Q compacted }; mov(8) g12<1>F g85<8,8,1>D { align1 1Q compacted }; mov(8) g13<1>F g87<8,8,1>D { align1 1Q compacted }; mov(8) g14<1>F g89<8,8,1>D { align1 1Q compacted }; mov(8) g15<1>F g91<8,8,1>D { align1 1Q compacted }; mov(8) g17<1>F g93<8,8,1>D { align1 1Q compacted }; mov(8) g18<1>F g95<8,8,1>D { align1 1Q compacted }; mov(8) g19<1>F g97<8,8,1>D { align1 1Q compacted }; mov(8) g20<1>F g99<8,8,1>D { align1 1Q compacted }; mov(8) g21<1>F g101<8,8,1>D { align1 1Q compacted }; mov(8) g22<1>F g103<8,8,1>D { align1 1Q compacted }; mov(8) g23<1>F g105<8,8,1>D { align1 1Q compacted }; mov(8) g24<1>F g107<8,8,1>D { align1 1Q compacted }; mov(8) g26<1>F g109<8,8,1>D { align1 1Q compacted }; mov(8) g27<1>F g111<8,8,1>D { align1 1Q compacted }; mov(8) g28<1>F g113<8,8,1>D { align1 1Q compacted }; mov(8) g29<1>F g115<8,8,1>D { align1 1Q compacted }; mov(8) g30<1>F g117<8,8,1>D { align1 1Q compacted }; mov(8) g31<1>F g119<8,8,1>D { align1 1Q compacted }; mov(8) g32<1>F g121<8,8,1>D { align1 1Q compacted }; mov(8) g35<1>F g125<8,8,1>D { align1 1Q compacted }; mov(8) g36<1>F g43<8,8,1>D { align1 1Q compacted }; mov(8) g37<1>F g45<8,8,1>D { align1 1Q compacted }; mov(8) g38<1>F g47<8,8,1>D { align1 1Q compacted }; mov(8) g39<1>F g49<8,8,1>D { align1 1Q compacted }; mov(8) g40<1>F g51<8,8,1>D { align1 1Q compacted }; mov(8) g41<1>F g53<8,8,1>D { align1 1Q compacted }; mov(8) g42<1>F g55<8,8,1>D { align1 1Q compacted }; mov(8) g44<1>F g57<8,8,1>D { align1 1Q compacted }; mov(8) g46<1>F g61<8,8,1>D { align1 1Q compacted }; mov(8) g48<1>F g65<8,8,1>D { align1 1Q compacted }; mov(8) g50<1>F g69<8,8,1>D { align1 1Q compacted }; mov(8) g54<1>F g75<8,8,1>D { align1 1Q compacted }; mov(8) g84<1>F g90<8,8,1>D { align1 1Q compacted }; mov(8) g86<1>F g94<8,8,1>D { align1 1Q compacted }; mov(8) g33<1>F g123<8,8,1>D { align1 1Q compacted }; add(8) g77<1>D g2<0,1,0>D 78D { align1 1Q compacted }; add(8) g79<1>D g2<0,1,0>D 79D { align1 1Q compacted }; add(8) g81<1>D g2<0,1,0>D 80D { align1 1Q compacted }; add(8) g83<1>D g2<0,1,0>D 81D { align1 1Q compacted }; add(8) g85<1>D g2<0,1,0>D 82D { align1 1Q compacted }; add(8) g87<1>D g2<0,1,0>D 83D { align1 1Q compacted }; add(8) g89<1>D g2<0,1,0>D 84D { align1 1Q compacted }; add(8) g91<1>D g2<0,1,0>D 85D { align1 1Q compacted }; add(8) g93<1>D g2<0,1,0>D 86D { align1 1Q compacted }; add(8) g95<1>D g2<0,1,0>D 87D { align1 1Q compacted }; add(8) g97<1>D g2<0,1,0>D 88D { align1 1Q compacted }; add(8) g99<1>D g2<0,1,0>D 89D { align1 1Q compacted }; add(8) g101<1>D g2<0,1,0>D 90D { align1 1Q compacted }; add(8) g103<1>D g2<0,1,0>D 91D { align1 1Q compacted }; add(8) g105<1>D g2<0,1,0>D 92D { align1 1Q compacted }; add(8) g107<1>D g2<0,1,0>D 93D { align1 1Q compacted }; add(8) g109<1>D g2<0,1,0>D 94D { align1 1Q compacted }; add(8) g111<1>D g2<0,1,0>D 95D { align1 1Q compacted }; add(8) g113<1>D g2<0,1,0>D 96D { align1 1Q compacted }; add(8) g115<1>D g2<0,1,0>D 97D { align1 1Q compacted }; add(8) g117<1>D g2<0,1,0>D 98D { align1 1Q compacted }; add(8) g119<1>D g2<0,1,0>D 99D { align1 1Q compacted }; add(8) g121<1>D g2<0,1,0>D 100D { align1 1Q compacted }; add(8) g125<1>D g2<0,1,0>D 102D { align1 1Q compacted }; mov(8) g45<1>F g59<8,8,1>D { align1 1Q compacted }; mov(8) g47<1>F g63<8,8,1>D { align1 1Q compacted }; mov(8) g49<1>F g67<8,8,1>D { align1 1Q compacted }; mov(8) g51<1>F g71<8,8,1>D { align1 1Q compacted }; mov(8) g53<1>F g73<8,8,1>D { align1 1Q compacted }; mov(8) g90<1>F g100<8,8,1>D { align1 1Q compacted }; mov(8) g94<1>F g108<8,8,1>D { align1 1Q compacted }; add(8) g123<1>D g2<0,1,0>D 101D { align1 1Q compacted }; mov(8) g55<1>F g77<8,8,1>D { align1 1Q compacted }; mov(8) g56<1>F g79<8,8,1>D { align1 1Q compacted }; mov(8) g57<1>F g81<8,8,1>D { align1 1Q compacted }; mov(8) g58<1>F g83<8,8,1>D { align1 1Q compacted }; mov(8) g60<1>F g87<8,8,1>D { align1 1Q compacted }; mov(8) g62<1>F g89<8,8,1>D { align1 1Q compacted }; mov(8) g64<1>F g93<8,8,1>D { align1 1Q compacted }; mov(8) g65<1>F g95<8,8,1>D { align1 1Q compacted }; mov(8) g66<1>F g97<8,8,1>D { align1 1Q compacted }; mov(8) g68<1>F g101<8,8,1>D { align1 1Q compacted }; mov(8) g69<1>F g103<8,8,1>D { align1 1Q compacted }; mov(8) g72<1>F g107<8,8,1>D { align1 1Q compacted }; mov(8) g74<1>F g111<8,8,1>D { align1 1Q compacted }; mov(8) g75<1>F g113<8,8,1>D { align1 1Q compacted }; mov(8) g76<1>F g115<8,8,1>D { align1 1Q compacted }; mov(8) g78<1>F g119<8,8,1>D { align1 1Q compacted }; mov(8) g80<1>F g121<8,8,1>D { align1 1Q compacted }; mov(8) g82<1>F g125<8,8,1>D { align1 1Q compacted }; mov(8) g59<1>F g85<8,8,1>D { align1 1Q compacted }; mov(8) g63<1>F g91<8,8,1>D { align1 1Q compacted }; mov(8) g67<1>F g99<8,8,1>D { align1 1Q compacted }; mov(8) g71<1>F g105<8,8,1>D { align1 1Q compacted }; mov(8) g73<1>F g109<8,8,1>D { align1 1Q compacted }; mov(8) g100<1>F g118<8,8,1>D { align1 1Q compacted }; add(8) g108<1>D g2<0,1,0>D 123D { align1 1Q compacted }; mov(8) g77<1>F g117<8,8,1>D { align1 1Q compacted }; mov(8) g81<1>F g123<8,8,1>D { align1 1Q compacted }; mov(8) g83<1>F g88<8,8,1>D { align1 1Q compacted }; mov(8) g87<1>F g96<8,8,1>D { align1 1Q compacted }; mov(8) g89<1>F g98<8,8,1>D { align1 1Q compacted }; mov(8) g93<1>F g106<8,8,1>D { align1 1Q compacted }; mov(8) g95<1>F g110<8,8,1>D { align1 1Q compacted }; mov(8) g101<1>F g120<8,8,1>D { align1 1Q compacted }; mov(8) g103<1>F g124<8,8,1>D { align1 1Q compacted }; mov(8) g85<1>F g92<8,8,1>D { align1 1Q compacted }; mov(8) g91<1>F g102<8,8,1>D { align1 1Q compacted }; mov(8) g99<1>F g116<8,8,1>D { align1 1Q compacted }; mov(8) g105<1>F g108<8,8,1>D { align1 1Q compacted }; mov(8) g96<1>F g112<8,8,1>D { align1 1Q compacted }; mov(8) g98<1>F g114<8,8,1>D { align1 1Q compacted }; add(8) g106<1>D g2<0,1,0>D 122D { align1 1Q compacted }; add(8) g110<1>D g2<0,1,0>D 124D { align1 1Q compacted }; mov(8) g92<1>F g104<8,8,1>D { align1 1Q compacted }; mov(8) g102<1>F g122<8,8,1>D { align1 1Q compacted }; add(8) g116<1>D g2<0,1,0>D 127D { align1 1Q compacted }; add(8) g112<1>D g2<0,1,0>D 125D { align1 1Q compacted }; add(8) g114<1>D g2<0,1,0>D 126D { align1 1Q compacted }; mov(8) g124<1>F g110<8,8,1>D { align1 1Q compacted }; mov(8) g104<1>F g106<8,8,1>D { align1 1Q compacted }; mov(8) g127<1>F g116<8,8,1>D { align1 1Q compacted }; mov(8) g125<1>F g112<8,8,1>D { align1 1Q compacted }; mov(8) g126<1>F g114<8,8,1>D { align1 1Q compacted }; mov(8) g106<1>F g2<0,1,0>D { align1 1Q compacted }; mov(8) g127<1>UD g106<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x0000000aUD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; mov(8) g107<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g127<1>UD g107<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000000UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; mov(8) g108<1>F g3<8,8,1>F { align1 1Q compacted }; mov(8) g127<1>UD g108<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000002UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; mov(8) g109<1>F g4<8,8,1>F { align1 1Q compacted }; mov(8) g127<1>UD g109<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000004UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; mov(8) g110<1>F g5<8,8,1>F { align1 1Q compacted }; mov(8) g127<1>UD g110<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000006UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; mov(8) g111<1>F g6<8,8,1>F { align1 1Q compacted }; mov(8) g127<1>UD g111<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000008UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g106<1>UW g0<8,8,1>F data ( DC OWORD block read, 0, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g107<1>UW g0<8,8,1>F data ( DC OWORD block read, 1, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g108<1>UW g0<8,8,1>F data ( DC OWORD block read, 2, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g109<1>UW g0<8,8,1>F data ( DC OWORD block read, 3, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g110<1>UW g0<8,8,1>F data ( DC OWORD block read, 4, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g112<1>UW g0<8,8,1>F data ( DC OWORD block read, 6, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g113<1>UW g0<8,8,1>F data ( DC OWORD block read, 7, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g114<1>UW g0<8,8,1>F data ( DC OWORD block read, 8, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g111<1>UW g0<8,8,1>F data ( DC OWORD block read, 5, 0) mlen 1 rlen 1 { align1 1Q }; send(8) null g106<8,8,1>F urb 1 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g120<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g127<1>UD g120<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000012UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g106<1>UW g0<8,8,1>F data ( DC OWORD block read, 9, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g107<1>UW g0<8,8,1>F data ( DC OWORD block read, 10, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g108<1>UW g0<8,8,1>F data ( DC OWORD block read, 11, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g109<1>UW g0<8,8,1>F data ( DC OWORD block read, 12, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g110<1>UW g0<8,8,1>F data ( DC OWORD block read, 13, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g111<1>UW g0<8,8,1>F data ( DC OWORD block read, 14, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g112<1>UW g0<8,8,1>F data ( DC OWORD block read, 15, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g113<1>UW g0<8,8,1>F data ( DC OWORD block read, 16, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g114<1>UW g0<8,8,1>F data ( DC OWORD block read, 17, 0) mlen 1 rlen 1 { align1 1Q }; send(8) null g106<8,8,1>F urb 3 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g106<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g127<1>UD g106<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000024UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g107<1>UW g0<8,8,1>F data ( DC OWORD block read, 19, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g108<1>UW g0<8,8,1>F data ( DC OWORD block read, 20, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g109<1>UW g0<8,8,1>F data ( DC OWORD block read, 21, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g110<1>UW g0<8,8,1>F data ( DC OWORD block read, 22, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g111<1>UW g0<8,8,1>F data ( DC OWORD block read, 23, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g112<1>UW g0<8,8,1>F data ( DC OWORD block read, 24, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g113<1>UW g0<8,8,1>F data ( DC OWORD block read, 25, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g114<1>UW g0<8,8,1>F data ( DC OWORD block read, 26, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g106<1>UW g0<8,8,1>F data ( DC OWORD block read, 18, 0) mlen 1 rlen 1 { align1 1Q }; send(8) null g106<8,8,1>F urb 5 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g115<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g127<1>UD g115<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000036UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g106<1>UW g0<8,8,1>F data ( DC OWORD block read, 27, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g107<1>UW g0<8,8,1>F data ( DC OWORD block read, 28, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g108<1>UW g0<8,8,1>F data ( DC OWORD block read, 29, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g109<1>UW g0<8,8,1>F data ( DC OWORD block read, 30, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g110<1>UW g0<8,8,1>F data ( DC OWORD block read, 31, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g111<1>UW g0<8,8,1>F data ( DC OWORD block read, 32, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g112<1>UW g0<8,8,1>F data ( DC OWORD block read, 33, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g113<1>UW g0<8,8,1>F data ( DC OWORD block read, 34, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g114<1>UW g0<8,8,1>F data ( DC OWORD block read, 35, 0) mlen 1 rlen 1 { align1 1Q }; send(8) null g106<8,8,1>F urb 7 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g2<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g127<1>UD g2<8,8,1>UD { align1 1Q compacted }; mov(8) g126<1>UD g0<8,8,1>UD { align1 WE_all 1Q compacted }; mov(1) g126.2<1>UD 0x00000048UD { align1 WE_all compacted }; send(8) null g126<8,8,1>UD data ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g107<1>UW g0<8,8,1>F data ( DC OWORD block read, 36, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g108<1>UW g0<8,8,1>F data ( DC OWORD block read, 37, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g109<1>UW g0<8,8,1>F data ( DC OWORD block read, 38, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g110<1>UW g0<8,8,1>F data ( DC OWORD block read, 39, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g111<1>UW g0<8,8,1>F data ( DC OWORD block read, 40, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g112<1>UW g0<8,8,1>F data ( DC OWORD block read, 41, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g113<1>UW g0<8,8,1>F data ( DC OWORD block read, 42, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g114<1>UW g0<8,8,1>F data ( DC OWORD block read, 43, 0) mlen 1 rlen 1 { align1 1Q }; send(8) g115<1>UW g0<8,8,1>F data ( DC OWORD block read, 44, 0) mlen 1 rlen 1 { align1 1Q }; send(8) null g107<8,8,1>F urb 9 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g7<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g7<8,8,1>F urb 11 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g16<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g16<8,8,1>F urb 13 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g25<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g25<8,8,1>F urb 15 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g34<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g34<8,8,1>F urb 17 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g43<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g43<8,8,1>F urb 19 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g52<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g52<8,8,1>F urb 21 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g61<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g61<8,8,1>F urb 23 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g70<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g70<8,8,1>F urb 25 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g79<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g79<8,8,1>F urb 27 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g88<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g88<8,8,1>F urb 29 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g97<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g97<8,8,1>F urb 31 SIMD8 write mlen 9 rlen 0 { align1 1Q }; mov(8) g123<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; send(8) null g123<8,8,1>F urb 33 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; nop ; END B0 NIR (SSA form) for vertex shader: decl_var shader_in vec4 position (17, 0) decl_var shader_out vec4 gl_Position (0, 0) decl_var shader_out int gl_Layer (20, 4) decl_overload main returning void impl main { block block_0: /* preds: */ vec1 ssa_19 = intrinsic load_instance_id () () () vec4 ssa_18 = intrinsic load_input () () (0, 1) intrinsic store_output (ssa_19) () (4, 1) intrinsic store_output (ssa_18) () (0, 1) /* succs: block_1 */ block block_1: } NIR (final form) for vertex shader: decl_var shader_in vec4 position (17, 0) decl_var shader_out vec4 gl_Position (0, 0) decl_var shader_out int gl_Layer (20, 4) decl_overload main returning void impl main { decl_reg vec1 r0 decl_reg vec4 r1 block block_0: /* preds: */ r0 = intrinsic load_instance_id () () () r1 = intrinsic load_input () () (0, 1) intrinsic store_output (r0) () (4, 1) intrinsic store_output (r1) () (0, 1) /* succs: block_1 */ block block_1: } GLSL IR for native vertex shader 6: ( (declare (shader_out ) vec4 gl_Position) (declare (temporary ) vec4 gl_Position) (declare (shader_out ) int gl_Layer) (declare (temporary ) int gl_Layer) (declare (sys ) int gl_InstanceID) (declare (shader_in ) vec4 position) (function main (signature void (parameters ) ( (assign (x) (var_ref gl_Layer) (var_ref gl_InstanceID) ) (assign (xyzw) (var_ref gl_Position) (var_ref position) ) (assign (x) (var_ref gl_Layer@35) (var_ref gl_Layer) ) (assign (xyzw) (var_ref gl_Position@36) (var_ref gl_Position) ) )) ) ) Native code for meta clear vertex shader 6 SIMD8 shader: 10 instructions. 0 loops. 0:0 spills:fills. Promoted 0 constants. Compacted 160 to 96 bytes (40%) START B0 mov(8) g119<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g120<1>UD 0x00000000UD { align1 1Q compacted }; mov(8) g121<1>F g9<8,8,1>F { align1 1Q compacted }; mov(8) g122<1>UD 0x00000000UD { align1 1Q compacted }; mov(8) g123<1>UD 0x00000000UD { align1 1Q compacted }; mov(8) g124<1>F g2<8,8,1>F { align1 1Q compacted }; mov(8) g125<1>F g3<8,8,1>F { align1 1Q compacted }; mov(8) g126<1>F g4<8,8,1>F { align1 1Q compacted }; mov(8) g127<1>F g5<8,8,1>F { align1 1Q compacted }; send(8) null g119<8,8,1>F urb 0 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; nop ; END B0 Probe color at (0,0) Expected: 0.000000 1.000000 0.000000 1.000000 Observed: 0.000000 0.000000 0.000000 0.000000 PIGLIT: {"result": "fail" }