SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[9]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyxx
  1: MOV TEMP[0].zw, -IN[0].yyxy
  2: MOV OUT[1], TEMP[0]
  3: MOV OUT[0], IN[0]
  4: END
; ModuleID = 'tgsi'

define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0
  %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0
  %13 = add i32 %5, %7
  %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13)
  %15 = extractelement <4 x float> %14, i32 0
  %16 = extractelement <4 x float> %14, i32 1
  %17 = extractelement <4 x float> %14, i32 2
  %18 = extractelement <4 x float> %14, i32 3
  %19 = fsub float -0.000000e+00, %15
  %20 = fsub float -0.000000e+00, %16
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %15, float %16, float %19, float %20)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" }
attributes #1 = { nounwind readnone }

!0 = !{!"const", null, i32 1}

Shader Disassembly:

	s_load_dwordx4 s[0:3], s[8:9], 0x0                  ; C0800900
	v_add_i32_e32 v0, s10, v0                           ; 4A00000A
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ; E00C2000 80000000
	v_mov_b32_e32 v4, 0x80000000                        ; 7E0802FF 80000000
	s_waitcnt vmcnt(0)                                  ; BF8C0770
	v_xor_b32_e32 v5, v0, v4                            ; 3A0A0900
	v_xor_b32_e32 v4, v1, v4                            ; 3A080901
	exp 15, 32, 0, 0, 0, v0, v1, v5, v4                 ; F800020F 04050100
	exp 15, 12, 0, 1, 0, v0, v1, v2, v3                 ; F80008CF 03020100
	s_endpgm                                            ; BF810000

*** SHADER STATS ***
SGPRS: 16
VGPRS: 8
Code Size: 60 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
********************
SHADER KEY
  export_16bpc = 0x3
  last_cbuf = 0
  color_two_side = 0
  alpha_func = 7
  alpha_to_one = 0
  poly_stipple = 0
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[9], PERSPECTIVE
DCL OUT[0], COLOR
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: ABS TEMP[0].xyz, IN[0].xyzz
  2: MOV OUT[0], TEMP[0]
  3: END
; ModuleID = 'tgsi'

define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
main_body:
  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
  %25 = call float @fabs(float %22)
  %26 = call float @fabs(float %23)
  %27 = call float @fabs(float %24)
  %28 = call i32 @llvm.SI.packf16(float %25, float %26)
  %29 = bitcast i32 %28 to float
  %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
  %31 = bitcast i32 %30 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

Shader Disassembly:

	s_mov_b32 m0, s9                         ; BEFC0309
	v_interp_p1_f32 v2, v0, 0, 0, [m0]       ; C8080000
	v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; C8090001
	v_interp_p1_f32 v3, v0, 1, 0, [m0]       ; C80C0100
	v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; C80D0101
	v_interp_p1_f32 v0, v0, 2, 0, [m0]       ; C8000200
	v_interp_p2_f32 v0, [v0], v1, 2, 0, [m0] ; C8010201
	v_cvt_pkrtz_f16_f32_e64 v1, |v2|, |v3|   ; D25E0301 00020702
	v_cvt_pkrtz_f16_f32_e64 v0, |v0|, 1.0    ; D25E0100 0001E500
	exp 15, 0, 1, 1, 1, v1, v0, v1, v0       ; F8001C0F 00010001
	s_endpgm                                 ; BF810000

*** SHADER STATS ***
SGPRS: 16
VGPRS: 4
Code Size: 56 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
********************
SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0
  %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0
  %13 = add i32 %5, %7
  %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13)
  %15 = extractelement <4 x float> %14, i32 0
  %16 = extractelement <4 x float> %14, i32 1
  %17 = extractelement <4 x float> %14, i32 2
  %18 = extractelement <4 x float> %14, i32 3
  %19 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1
  %20 = load <16 x i8>, <16 x i8> addrspace(2)* %19, align 16, !tbaa !0
  %21 = add i32 %5, %7
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" }
attributes #1 = { nounwind readnone }

!0 = !{!"const", null, i32 1}

Shader Disassembly:

	s_load_dwordx4 s[0:3], s[8:9], 0x0                  ; C0800900
	s_load_dwordx4 s[4:7], s[8:9], 0x4                  ; C0820904
	v_add_i32_e32 v0, s10, v0                           ; 4A00000A
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100
	buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500
	s_waitcnt vmcnt(0)                                  ; BF8C0770
	exp 15, 32, 0, 0, 0, v5, v6, v7, v8                 ; F800020F 08070605
	exp 15, 12, 0, 1, 0, v1, v2, v3, v4                 ; F80008CF 04030201
	s_endpgm                                            ; BF810000

*** SHADER STATS ***
SGPRS: 16
VGPRS: 12
Code Size: 56 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
********************
SHADER KEY
  export_16bpc = 0x3
  last_cbuf = 0
  color_two_side = 0
  alpha_func = 7
  alpha_to_one = 0
  poly_stipple = 0
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
main_body:
  %22 = bitcast [34 x <8 x i32>] addrspace(2)* %3 to <32 x i8> addrspace(2)*
  %23 = load <32 x i8>, <32 x i8> addrspace(2)* %22, align 32, !tbaa !0
  %24 = bitcast [17 x <4 x i32>] addrspace(2)* %2 to <16 x i8> addrspace(2)*
  %25 = load <16 x i8>, <16 x i8> addrspace(2)* %24, align 16, !tbaa !0
  %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
  %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
  %28 = bitcast float %26 to i32
  %29 = bitcast float %27 to i32
  %30 = insertelement <2 x i32> undef, i32 %28, i32 0
  %31 = insertelement <2 x i32> %30, i32 %29, i32 1
  %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
attributes #1 = { nounwind readnone }

!0 = !{!"const", null, i32 1}

Shader Disassembly:

	s_wqm_b64 exec, exec                                                   ; BEFE0A7E
	s_load_dwordx8 s[12:19], s[6:7], 0x0                                   ; C0C60700
	s_load_dwordx4 s[0:3], s[4:5], 0x0                                     ; C0800500
	s_mov_b32 m0, s9                                                       ; BEFC0309
	v_interp_p1_f32 v2, v0, 0, 0, [m0]                                     ; C8080000
	v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
	v_interp_p1_f32 v3, v0, 1, 0, [m0]                                     ; C80C0100
	v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0]                               ; C80D0101
	s_waitcnt lgkmcnt(0)                                                   ; BF8C007F
	image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002
	s_waitcnt vmcnt(0)                                                     ; BF8C0770
	v_cvt_pkrtz_f16_f32_e32 v4, v0, v1                                     ; 5E080300
	v_cvt_pkrtz_f16_f32_e32 v0, v2, v3                                     ; 5E000702
	exp 15, 0, 1, 1, 1, v4, v0, v4, v0                                     ; F8001C0F 00040004
	s_endpgm                                                               ; BF810000

*** SHADER STATS ***
SGPRS: 24
VGPRS: 8
Code Size: 68 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
********************