diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index b43c802..dec7334 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1436,6 +1436,7 @@ defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
 let Uses = [M0] in {
 
 // FIXME: Specify SchedRW for VINTRP insturctions.
+let Constraints = "@earlyclobber $dst" in {
 defm V_INTERP_P1_F32 : VINTRP_m <
   0x00000000, "v_interp_p1_f32",
   (outs VGPR_32:$dst),
@@ -1443,6 +1444,7 @@ defm V_INTERP_P1_F32 : VINTRP_m <
   "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
   [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
                                            (i32 imm:$attr)))]>;
+}
 
 defm V_INTERP_P2_F32 : VINTRP_m <
   0x00000001, "v_interp_p2_f32",