VERT VERT DCL IN[0] DCL IN[0] DCL IN[1] DCL IN[1] DCL IN[2] DCL IN[2] DCL IN[3] DCL IN[3] DCL IN[4] DCL IN[4] DCL IN[5] DCL IN[5] DCL IN[6] DCL IN[6] DCL IN[7] DCL IN[7] DCL IN[8] DCL IN[8] DCL IN[9] DCL IN[9] DCL OUT[0], POSITION DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] DCL OUT[4], GENERIC[2] DCL OUT[5], GENERIC[3] DCL OUT[5], GENERIC[3] DCL OUT[6], GENERIC[4] DCL OUT[6], GENERIC[4] DCL OUT[7], GENERIC[5] DCL OUT[7], GENERIC[5] DCL OUT[8], GENERIC[6] DCL OUT[8], GENERIC[6] DCL OUT[9], GENERIC[7] DCL OUT[9], GENERIC[7] DCL CONST[0..239] DCL CONST[0..239] DCL TEMP[0..5], LOCAL DCL TEMP[0..5], LOCAL DCL TEMP[6..8], ARRAY(1), LOCAL DCL TEMP[6..8], ARRAY(1), LOCAL DCL TEMP[9..11], ARRAY(2), LOCAL DCL TEMP[9..11], ARRAY(2), LOCAL DCL TEMP[12..16], LOCAL DCL TEMP[12..16], LOCAL DCL TEMP[17..19], ARRAY(3), LOCAL DCL TEMP[17..19], ARRAY(3), LOCAL DCL TEMP[20..22], ARRAY(4), LOCAL DCL TEMP[20..22], ARRAY(4), LOCAL DCL TEMP[23], LOCAL DCL TEMP[23], LOCAL DCL TEMP[24..26], ARRAY(5), LOCAL DCL TEMP[24..26], ARRAY(5), LOCAL DCL TEMP[27..29], LOCAL DCL TEMP[27..29], LOCAL IMM[0] FLT32 { 0.0010, 1.0000, 0.0000, 0.5000} IMM[0] FLT32 { 0.0010, 1.0000, 0.0000, 0.5000} IMM[1] FLT32 { 3.0000, -1.0000, 1.0000, 2.0000} IMM[1] FLT32 { 3.0000, -1.0000, 1.0000, 2.0000} 0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx 0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx 1: ADD TEMP[1].x, TEMP[0].yyyy, IMM[0].xxxx 1: ADD TEMP[1].x, TEMP[0].yyyy, IMM[0].xxxx 2: MOV TEMP[0].y, TEMP[1].xxxx 2: MOV TEMP[0].y, TEMP[1].xxxx 3: MAD TEMP[2], IN[8], CONST[37].zzzz, CONST[37].xyyx 3: MAD TEMP[2], IN[8], CONST[37].zzzz, CONST[37].xyyx 4: ADD TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx 4: ADD TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx 5: DP4 TEMP[3].x, IN[0], CONST[0] 5: DP4 TEMP[3].x, IN[0], CONST[0] 6: DP4 TEMP[4].x, IN[0], CONST[1] 6: DP4 TEMP[4].x, IN[0], CONST[1] 7: MOV TEMP[3].y, TEMP[4].xxxx 7: MOV TEMP[3].y, TEMP[4].xxxx 8: DP4 TEMP[4].x, IN[0], CONST[2] 8: DP4 TEMP[4].x, IN[0], CONST[2] 9: MOV TEMP[3].z, TEMP[4].xxxx 9: MOV TEMP[3].z, TEMP[4].xxxx 10: DP4 TEMP[4].x, IN[0], CONST[3] 10: DP4 TEMP[4].x, IN[0], CONST[3] 11: MOV TEMP[3].w, TEMP[4].xxxx 11: MOV TEMP[3].w, TEMP[4].xxxx 12: DP4 TEMP[4].x, IN[0], CONST[4] 12: DP4 TEMP[4].x, IN[0], CONST[4] 13: DP4 TEMP[5].x, IN[0], CONST[5] 13: DP4 TEMP[5].x, IN[0], CONST[5] 14: MOV TEMP[4].y, TEMP[5].xxxx 14: MOV TEMP[4].y, TEMP[5].xxxx 15: DP4 TEMP[5].x, IN[0], CONST[6] 15: DP4 TEMP[5].x, IN[0], CONST[6] 16: MOV TEMP[4].z, TEMP[5].xxxx 16: MOV TEMP[4].z, TEMP[5].xxxx 17: MOV TEMP[5].xyz, TEMP[4].xyzx 17: MOV TEMP[5].xyz, TEMP[4].xyzx 18: MOV TEMP[5].w, IMM[0].yyyy 18: MOV TEMP[5].w, IMM[0].yyyy 19: MOV TEMP[6].xyz, CONST[4].xyzx 19: MOV TEMP[6].xyz, CONST[4].xyzx 20: MOV TEMP[7].xyz, CONST[5].xyzx 20: MOV TEMP[7].xyz, CONST[5].xyzx 21: MOV TEMP[8].xyz, CONST[6].xyzx 21: MOV TEMP[8].xyz, CONST[6].xyzx 22: MOV TEMP[9], TEMP[6].xyzz 22: MOV TEMP[9], TEMP[6].xyzz 23: MOV TEMP[10], TEMP[7].xyzz 23: MOV TEMP[10], TEMP[7].xyzz 24: MOV TEMP[11], TEMP[8].xyzz 24: MOV TEMP[11], TEMP[8].xyzz 25: DP3 TEMP[12].x, TEMP[6].xyzz, TEMP[6].xyzz 25: DP3 TEMP[12].x, TEMP[6].xyzz, TEMP[6].xyzz 26: DP3 TEMP[13].x, TEMP[7].xyzz, TEMP[7].xyzz 26: DP3 TEMP[13].x, TEMP[7].xyzz, TEMP[7].xyzz 27: DP3 TEMP[14].x, TEMP[8].xyzz, TEMP[8].xyzz 27: DP3 TEMP[14].x, TEMP[8].xyzz, TEMP[8].xyzz 28: RCP TEMP[12].x, TEMP[12].xxxx 28: RCP TEMP[12].x, TEMP[12].xxxx 29: RCP TEMP[12].y, TEMP[13].xxxx 29: RCP TEMP[12].y, TEMP[13].xxxx 30: RCP TEMP[12].z, TEMP[14].xxxx 30: RCP TEMP[12].z, TEMP[14].xxxx 31: MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[12].xxxx 31: MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[12].xxxx 32: MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[12].yyyy 32: MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[12].yyyy 33: MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].zzzz 33: MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].zzzz 34: DP3 TEMP[12].x, TEMP[0].xyzz, TEMP[9].xyzz 34: DP3 TEMP[12].x, TEMP[0].xyzz, TEMP[9].xyzz 35: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[10].xyzz 35: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[10].xyzz 36: MOV TEMP[12].y, TEMP[13].xxxx 36: MOV TEMP[12].y, TEMP[13].xxxx 37: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[11].xyzz 37: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[11].xyzz 38: MOV TEMP[12].z, TEMP[13].xxxx 38: MOV TEMP[12].z, TEMP[13].xxxx 39: DP3 TEMP[13].x, TEMP[12].xyzz, TEMP[12].xyzz 39: DP3 TEMP[13].x, TEMP[12].xyzz, TEMP[12].xyzz 40: RSQ TEMP[13].x, TEMP[13].xxxx 40: RSQ TEMP[13].x, TEMP[13].xxxx 41: MUL TEMP[12].xyz, TEMP[12].xyzz, TEMP[13].xxxx 41: MUL TEMP[12].xyz, TEMP[12].xyzz, TEMP[13].xxxx 42: FSLT TEMP[13].x, IMM[0].zzzz, CONST[34].zzzz 42: FSLT TEMP[13].x, IMM[0].zzzz, CONST[34].zzzz 43: UIF TEMP[13].xxxx :0 43: UIF TEMP[13].xxxx :0 44: DP3 TEMP[13].x, TEMP[12].xyzz, TEMP[12].xyzz 44: DP3 TEMP[13].x, TEMP[12].xyzz, TEMP[12].xyzz 45: RSQ TEMP[13].x, TEMP[13].xxxx 45: RSQ TEMP[13].x, TEMP[13].xxxx 46: MUL TEMP[13].xyz, TEMP[12].xyzz, TEMP[13].xxxx 46: MUL TEMP[13].xyz, TEMP[12].xyzz, TEMP[13].xxxx 47: MUL TEMP[14].xyz, TEMP[13].xyzz, CONST[34].xxxx 47: MUL TEMP[14].xyz, TEMP[13].xyzz, CONST[34].xxxx 48: MAD TEMP[15].x, CONST[34].xxxx, IMM[0].wwww, IMM[0].wwww 48: MAD TEMP[15].x, CONST[34].xxxx, IMM[0].wwww, IMM[0].wwww 49: MOV TEMP[16].z, IMM[0].zzzz 49: MOV TEMP[16].z, IMM[0].zzzz 50: ADD TEMP[16].x, IMM[0].yyyy, -TEMP[15].xxxx 50: ADD TEMP[16].x, IMM[0].yyyy, -TEMP[15].xxxx 51: MOV TEMP[16].y, TEMP[15].xxxx 51: MOV TEMP[16].y, TEMP[15].xxxx 52: MUL TEMP[15].xyz, TEMP[14].zxyy, TEMP[16].yzxx 52: MUL TEMP[15].xyz, TEMP[14].zxyy, TEMP[16].yzxx 53: MAD TEMP[15].xyz, TEMP[14].yzxx, TEMP[16].zxyy, -TEMP[15].xyzz 53: MAD TEMP[15].xyz, TEMP[14].yzxx, TEMP[16].zxyy, -TEMP[15].xyzz 54: MUL TEMP[16].xyz, TEMP[15].zxyy, TEMP[14].yzxx 54: MUL TEMP[16].xyz, TEMP[15].zxyy, TEMP[14].yzxx 55: MAD TEMP[14].xyz, TEMP[15].yzxx, TEMP[14].zxyy, -TEMP[16].xyzz 55: MAD TEMP[14].xyz, TEMP[15].yzxx, TEMP[14].zxyy, -TEMP[16].xyzz 56: MUL TEMP[16].xyz, TEMP[14].xyzz, CONST[23].xxxx 56: MUL TEMP[16].xyz, TEMP[14].xyzz, CONST[23].xxxx 57: MAD TEMP[16].xyz, TEMP[15].xyzz, CONST[23].yyyy, TEMP[16].xyzz 57: MAD TEMP[16].xyz, TEMP[15].xyzz, CONST[23].yyyy, TEMP[16].xyzz 58: MAD TEMP[17].xyz, TEMP[13].xyzz, CONST[23].zzzz, TEMP[16].xyzz 58: MAD TEMP[17].xyz, TEMP[13].xyzz, CONST[23].zzzz, TEMP[16].xyzz 59: MUL TEMP[14].xyz, TEMP[14].xyzz, CONST[24].xxxx 59: MUL TEMP[14].xyz, TEMP[14].xyzz, CONST[24].xxxx 60: MAD TEMP[14].xyz, TEMP[15].xyzz, CONST[24].yyyy, TEMP[14].xyzz 60: MAD TEMP[14].xyz, TEMP[15].xyzz, CONST[24].yyyy, TEMP[14].xyzz 61: MAD TEMP[18].xyz, TEMP[13].xyzz, CONST[24].zzzz, TEMP[14].xyzz 61: MAD TEMP[18].xyz, TEMP[13].xyzz, CONST[24].zzzz, TEMP[14].xyzz 62: MOV TEMP[19].xyz, TEMP[13].xyzx 62: MOV TEMP[19].xyz, TEMP[13].xyzx 63: MOV TEMP[20], TEMP[17].xyzz 63: MOV TEMP[20], TEMP[17].xyzz 64: MOV TEMP[21], TEMP[18].xyzz 64: MOV TEMP[21], TEMP[18].xyzz 65: MOV TEMP[22], TEMP[19].xyzz 65: MOV TEMP[22], TEMP[19].xyzz 66: ELSE :0 66: ELSE :0 67: MUL TEMP[13].xyz, TEMP[0].xyzz, TEMP[2].wwww 67: MUL TEMP[13].xyz, TEMP[0].xyzz, TEMP[2].wwww 68: MUL TEMP[14].xyz, TEMP[13].zxyy, TEMP[2].yzxx 68: MUL TEMP[14].xyz, TEMP[13].zxyy, TEMP[2].yzxx 69: MAD TEMP[13].xyz, TEMP[13].yzxx, TEMP[2].zxyy, -TEMP[14].xyzz 69: MAD TEMP[13].xyz, TEMP[13].yzxx, TEMP[2].zxyy, -TEMP[14].xyzz 70: MOV TEMP[14].x, TEMP[9].xxxx 70: MOV TEMP[14].x, TEMP[9].xxxx 71: MOV TEMP[15].x, TEMP[9].yyyy 71: MOV TEMP[15].x, TEMP[9].yyyy 72: MOV TEMP[16].x, TEMP[9].zzzz 72: MOV TEMP[16].x, TEMP[9].zzzz 73: MOV TEMP[14].y, TEMP[10].xxxx 73: MOV TEMP[14].y, TEMP[10].xxxx 74: MOV TEMP[15].y, TEMP[10].yyyy 74: MOV TEMP[15].y, TEMP[10].yyyy 75: MOV TEMP[16].y, TEMP[10].zzzz 75: MOV TEMP[16].y, TEMP[10].zzzz 76: MOV TEMP[14].z, TEMP[11].xxxx 76: MOV TEMP[14].z, TEMP[11].xxxx 77: MOV TEMP[15].z, TEMP[11].yyyy 77: MOV TEMP[15].z, TEMP[11].yyyy 78: MOV TEMP[16].z, TEMP[11].zzzz 78: MOV TEMP[16].z, TEMP[11].zzzz 79: MUL TEMP[23].xyz, TEMP[2].xyzz, CONST[23].xxxx 79: MUL TEMP[23].xyz, TEMP[2].xyzz, CONST[23].xxxx 80: MAD TEMP[23].xyz, TEMP[13].xyzz, CONST[23].yyyy, TEMP[23].xyzz 80: MAD TEMP[23].xyz, TEMP[13].xyzz, CONST[23].yyyy, TEMP[23].xyzz 81: MAD TEMP[23].xyz, TEMP[0].xyzz, CONST[23].zzzz, TEMP[23].xyzz 81: MAD TEMP[23].xyz, TEMP[0].xyzz, CONST[23].zzzz, TEMP[23].xyzz 82: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[24].xxxx 82: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[24].xxxx 83: MAD TEMP[2].xyz, TEMP[13].xyzz, CONST[24].yyyy, TEMP[2].xyzz 83: MAD TEMP[2].xyz, TEMP[13].xyzz, CONST[24].yyyy, TEMP[2].xyzz 84: MAD TEMP[2].xyz, TEMP[0].xyzz, CONST[24].zzzz, TEMP[2].xyzz 84: MAD TEMP[2].xyz, TEMP[0].xyzz, CONST[24].zzzz, TEMP[2].xyzz 85: MUL TEMP[13].xyz, TEMP[14].xyzz, TEMP[23].xxxx 85: MUL TEMP[13].xyz, TEMP[14].xyzz, TEMP[23].xxxx 86: MAD TEMP[13].xyz, TEMP[15].xyzz, TEMP[23].yyyy, TEMP[13].xyzz 86: MAD TEMP[13].xyz, TEMP[15].xyzz, TEMP[23].yyyy, TEMP[13].xyzz 87: MAD TEMP[24].xyz, TEMP[16].xyzz, TEMP[23].zzzz, TEMP[13].xyzz 87: MAD TEMP[24].xyz, TEMP[16].xyzz, TEMP[23].zzzz, TEMP[13].xyzz 88: MUL TEMP[13].xyz, TEMP[14].xyzz, TEMP[2].xxxx 88: MUL TEMP[13].xyz, TEMP[14].xyzz, TEMP[2].xxxx 89: MAD TEMP[13].xyz, TEMP[15].xyzz, TEMP[2].yyyy, TEMP[13].xyzz 89: MAD TEMP[13].xyz, TEMP[15].xyzz, TEMP[2].yyyy, TEMP[13].xyzz 90: MAD TEMP[25].xyz, TEMP[16].xyzz, TEMP[2].zzzz, TEMP[13].xyzz 90: MAD TEMP[25].xyz, TEMP[16].xyzz, TEMP[2].zzzz, TEMP[13].xyzz 91: MUL TEMP[2].xyz, TEMP[14].xyzz, TEMP[0].xxxx 91: MUL TEMP[2].xyz, TEMP[14].xyzz, TEMP[0].xxxx 92: MAD TEMP[1].xyz, TEMP[15].xyzz, TEMP[1].xxxx, TEMP[2].xyzz 92: MAD TEMP[1].xyz, TEMP[15].xyzz, TEMP[1].xxxx, TEMP[2].xyzz 93: MAD TEMP[26].xyz, TEMP[16].xyzz, TEMP[0].zzzz, TEMP[1].xyzz 93: MAD TEMP[26].xyz, TEMP[16].xyzz, TEMP[0].zzzz, TEMP[1].xyzz 94: MOV TEMP[20], TEMP[24].xyzz 94: MOV TEMP[20], TEMP[24].xyzz 95: MOV TEMP[21], TEMP[25].xyzz 95: MOV TEMP[21], TEMP[25].xyzz 96: MOV TEMP[22], TEMP[26].xyzz 96: MOV TEMP[22], TEMP[26].xyzz 97: ENDIF 97: ENDIF 98: MOV TEMP[0].xyz, TEMP[20].xyzx 98: MOV TEMP[0].xyz, TEMP[20].xyzx 99: MOV TEMP[1].xyz, TEMP[21].xyzx 99: MOV TEMP[1].xyz, TEMP[21].xyzx 100: MOV TEMP[2].xyz, TEMP[22].xyzx 100: MOV TEMP[2].xyz, TEMP[22].xyzx 101: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[0].xyzz 101: DP3 TEMP[13].x, TEMP[0].xyzz, TEMP[0].xyzz 102: RSQ TEMP[13].x, TEMP[13].xxxx 102: RSQ TEMP[13].x, TEMP[13].xxxx 103: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[13].xxxx 103: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[13].xxxx 104: DP3 TEMP[13].x, TEMP[1].xyzz, TEMP[1].xyzz 104: DP3 TEMP[13].x, TEMP[1].xyzz, TEMP[1].xyzz 105: RSQ TEMP[13].x, TEMP[13].xxxx 105: RSQ TEMP[13].x, TEMP[13].xxxx 106: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[13].xxxx 106: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[13].xxxx 107: DP3 TEMP[13].x, TEMP[2].xyzz, TEMP[2].xyzz 107: DP3 TEMP[13].x, TEMP[2].xyzz, TEMP[2].xyzz 108: RSQ TEMP[13].x, TEMP[13].xxxx 108: RSQ TEMP[13].x, TEMP[13].xxxx 109: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[13].xxxx 109: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[13].xxxx 110: MUL TEMP[13].xyz, TEMP[12].xyzz, TEMP[12].xyzz 110: MUL TEMP[13].xyz, TEMP[12].xyzz, TEMP[12].xyzz 111: MUL TEMP[14].xyz, TEMP[12].xzyy, TEMP[12].zyxx 111: MUL TEMP[14].xyz, TEMP[12].xzyy, TEMP[12].zyxx 112: MAD TEMP[15].xyz, CONST[15].xyzz, TEMP[12].xxxx, CONST[14].xyzz 112: MAD TEMP[15].xyz, CONST[15].xyzz, TEMP[12].xxxx, CONST[14].xyzz 113: MAD TEMP[15].xyz, CONST[16].xyzz, TEMP[12].yyyy, TEMP[15].xyzz 113: MAD TEMP[15].xyz, CONST[16].xyzz, TEMP[12].yyyy, TEMP[15].xyzz 114: MAD TEMP[15].xyz, CONST[17].xyzz, TEMP[12].zzzz, TEMP[15].xyzz 114: MAD TEMP[15].xyz, CONST[17].xyzz, TEMP[12].zzzz, TEMP[15].xyzz 115: MAD TEMP[15].xyz, CONST[18].xyzz, TEMP[14].xxxx, TEMP[15].xyzz 115: MAD TEMP[15].xyz, CONST[18].xyzz, TEMP[14].xxxx, TEMP[15].xyzz 116: MAD TEMP[15].xyz, CONST[19].xyzz, TEMP[14].yyyy, TEMP[15].xyzz 116: MAD TEMP[15].xyz, CONST[19].xyzz, TEMP[14].yyyy, TEMP[15].xyzz 117: MAD TEMP[15].xyz, CONST[20].xyzz, TEMP[14].zzzz, TEMP[15].xyzz 117: MAD TEMP[15].xyz, CONST[20].xyzz, TEMP[14].zzzz, TEMP[15].xyzz 118: MAD TEMP[12].x, TEMP[13].zzzz, IMM[1].xxxx, IMM[1].yyyy 118: MAD TEMP[12].x, TEMP[13].zzzz, IMM[1].xxxx, IMM[1].yyyy 119: MAD TEMP[15].xyz, CONST[21].xyzz, TEMP[12].xxxx, TEMP[15].xyzz 119: MAD TEMP[15].xyz, CONST[21].xyzz, TEMP[12].xxxx, TEMP[15].xyzz 120: ADD TEMP[12].x, TEMP[13].xxxx, -TEMP[13].yyyy 120: ADD TEMP[12].x, TEMP[13].xxxx, -TEMP[13].yyyy 121: MAD TEMP[15].xyz, CONST[22].xyzz, TEMP[12].xxxx, TEMP[15].xyzz 121: MAD TEMP[15].xyz, CONST[22].xyzz, TEMP[12].xxxx, TEMP[15].xyzz 122: MAX TEMP[12].xyz, TEMP[15].xyzz, IMM[0].zzzz 122: MAX TEMP[12].xyz, TEMP[15].xyzz, IMM[0].zzzz 123: MAD TEMP[14], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 123: MAD TEMP[14], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 124: FSGE TEMP[15].x, CONST[31].zzzz, IMM[0].zzzz 124: FSGE TEMP[15].x, CONST[31].zzzz, IMM[0].zzzz 125: UIF TEMP[15].xxxx :0 125: UIF TEMP[15].xxxx :0 126: MOV TEMP[15].x, TEMP[14].xxxx 126: MOV TEMP[15].x, TEMP[14].xxxx 127: ELSE :0 127: ELSE :0 128: MOV TEMP[15].x, IN[5].xxxx 128: MOV TEMP[15].x, IN[5].xxxx 129: ENDIF 129: ENDIF 130: FSGE TEMP[16].x, CONST[31].zzzz, IMM[0].zzzz 130: FSGE TEMP[16].x, CONST[31].zzzz, IMM[0].zzzz 131: UIF TEMP[16].xxxx :0 131: UIF TEMP[16].xxxx :0 132: MOV TEMP[16].x, TEMP[14].yyyy 132: MOV TEMP[16].x, TEMP[14].yyyy 133: ELSE :0 133: ELSE :0 134: MOV TEMP[16].x, IN[5].yyyy 134: MOV TEMP[16].x, IN[5].yyyy 135: ENDIF 135: ENDIF 136: FSGE TEMP[23].x, CONST[31].xxxx, IMM[0].zzzz 136: FSGE TEMP[23].x, CONST[31].xxxx, IMM[0].zzzz 137: UIF TEMP[23].xxxx :0 137: UIF TEMP[23].xxxx :0 138: MOV TEMP[23].x, TEMP[14].zzzz 138: MOV TEMP[23].x, TEMP[14].zzzz 139: ELSE :0 139: ELSE :0 140: MOV TEMP[23].x, TEMP[15].xxxx 140: MOV TEMP[23].x, TEMP[15].xxxx 141: ENDIF 141: ENDIF 142: MOV TEMP[13].x, TEMP[23].xxxx 142: MOV TEMP[13].x, TEMP[23].xxxx 143: FSGE TEMP[15].x, CONST[31].yyyy, IMM[0].zzzz 143: FSGE TEMP[15].x, CONST[31].yyyy, IMM[0].zzzz 144: UIF TEMP[15].xxxx :0 144: UIF TEMP[15].xxxx :0 145: MOV TEMP[14].x, TEMP[14].wwww 145: MOV TEMP[14].x, TEMP[14].wwww 146: ELSE :0 146: ELSE :0 147: MOV TEMP[14].x, TEMP[16].xxxx 147: MOV TEMP[14].x, TEMP[16].xxxx 148: ENDIF 148: ENDIF 149: MOV TEMP[13].y, TEMP[14].xxxx 149: MOV TEMP[13].y, TEMP[14].xxxx 150: MOV TEMP[14].zw, IMM[0].yyzy 150: MOV TEMP[14].zw, IMM[0].yyzy 151: MOV TEMP[14].xy, TEMP[13].xyxx 151: MOV TEMP[14].xy, TEMP[13].xyxx 152: MAD TEMP[15], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 152: MAD TEMP[15], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 153: FSGE TEMP[16].x, CONST[32].zzzz, IMM[0].zzzz 153: FSGE TEMP[16].x, CONST[32].zzzz, IMM[0].zzzz 154: UIF TEMP[16].xxxx :0 154: UIF TEMP[16].xxxx :0 155: MOV TEMP[16].x, TEMP[15].xxxx 155: MOV TEMP[16].x, TEMP[15].xxxx 156: ELSE :0 156: ELSE :0 157: MOV TEMP[16].x, IN[2].xxxx 157: MOV TEMP[16].x, IN[2].xxxx 158: ENDIF 158: ENDIF 159: FSGE TEMP[23].x, CONST[32].zzzz, IMM[0].zzzz 159: FSGE TEMP[23].x, CONST[32].zzzz, IMM[0].zzzz 160: UIF TEMP[23].xxxx :0 160: UIF TEMP[23].xxxx :0 161: MOV TEMP[23].x, TEMP[15].yyyy 161: MOV TEMP[23].x, TEMP[15].yyyy 162: ELSE :0 162: ELSE :0 163: MOV TEMP[23].x, IN[2].yyyy 163: MOV TEMP[23].x, IN[2].yyyy 164: ENDIF 164: ENDIF 165: FSGE TEMP[27].x, CONST[32].xxxx, IMM[0].zzzz 165: FSGE TEMP[27].x, CONST[32].xxxx, IMM[0].zzzz 166: UIF TEMP[27].xxxx :0 166: UIF TEMP[27].xxxx :0 167: MOV TEMP[27].x, TEMP[15].zzzz 167: MOV TEMP[27].x, TEMP[15].zzzz 168: ELSE :0 168: ELSE :0 169: MOV TEMP[27].x, TEMP[16].xxxx 169: MOV TEMP[27].x, TEMP[16].xxxx 170: ENDIF 170: ENDIF 171: MOV TEMP[13].x, TEMP[27].xxxx 171: MOV TEMP[13].x, TEMP[27].xxxx 172: FSGE TEMP[16].x, CONST[32].yyyy, IMM[0].zzzz 172: FSGE TEMP[16].x, CONST[32].yyyy, IMM[0].zzzz 173: UIF TEMP[16].xxxx :0 173: UIF TEMP[16].xxxx :0 174: MOV TEMP[15].x, TEMP[15].wwww 174: MOV TEMP[15].x, TEMP[15].wwww 175: ELSE :0 175: ELSE :0 176: MOV TEMP[15].x, TEMP[23].xxxx 176: MOV TEMP[15].x, TEMP[23].xxxx 177: ENDIF 177: ENDIF 178: MOV TEMP[13].y, TEMP[15].xxxx 178: MOV TEMP[13].y, TEMP[15].xxxx 179: MOV TEMP[15].zw, IMM[0].yyzy 179: MOV TEMP[15].zw, IMM[0].yyzy 180: MOV TEMP[15].xy, TEMP[13].xyxx 180: MOV TEMP[15].xy, TEMP[13].xyxx 181: MAD TEMP[16], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 181: MAD TEMP[16], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 182: FSGE TEMP[23].x, CONST[33].zzzz, IMM[0].zzzz 182: FSGE TEMP[23].x, CONST[33].zzzz, IMM[0].zzzz 183: UIF TEMP[23].xxxx :0 183: UIF TEMP[23].xxxx :0 184: MOV TEMP[23].x, TEMP[16].xxxx 184: MOV TEMP[23].x, TEMP[16].xxxx 185: ELSE :0 185: ELSE :0 186: MOV TEMP[23].x, IN[6].xxxx 186: MOV TEMP[23].x, IN[6].xxxx 187: ENDIF 187: ENDIF 188: FSGE TEMP[27].x, CONST[33].zzzz, IMM[0].zzzz 188: FSGE TEMP[27].x, CONST[33].zzzz, IMM[0].zzzz 189: UIF TEMP[27].xxxx :0 189: UIF TEMP[27].xxxx :0 190: MOV TEMP[27].x, TEMP[16].yyyy 190: MOV TEMP[27].x, TEMP[16].yyyy 191: ELSE :0 191: ELSE :0 192: MOV TEMP[27].x, IN[6].yyyy 192: MOV TEMP[27].x, IN[6].yyyy 193: ENDIF 193: ENDIF 194: FSGE TEMP[28].x, CONST[33].xxxx, IMM[0].zzzz 194: FSGE TEMP[28].x, CONST[33].xxxx, IMM[0].zzzz 195: UIF TEMP[28].xxxx :0 195: UIF TEMP[28].xxxx :0 196: MOV TEMP[28].x, TEMP[16].zzzz 196: MOV TEMP[28].x, TEMP[16].zzzz 197: ELSE :0 197: ELSE :0 198: MOV TEMP[28].x, TEMP[23].xxxx 198: MOV TEMP[28].x, TEMP[23].xxxx 199: ENDIF 199: ENDIF 200: MOV TEMP[13].x, TEMP[28].xxxx 200: MOV TEMP[13].x, TEMP[28].xxxx 201: FSGE TEMP[23].x, CONST[33].yyyy, IMM[0].zzzz 201: FSGE TEMP[23].x, CONST[33].yyyy, IMM[0].zzzz 202: UIF TEMP[23].xxxx :0 202: UIF TEMP[23].xxxx :0 203: MOV TEMP[16].x, TEMP[16].wwww 203: MOV TEMP[16].x, TEMP[16].wwww 204: ELSE :0 204: ELSE :0 205: MOV TEMP[16].x, TEMP[27].xxxx 205: MOV TEMP[16].x, TEMP[27].xxxx 206: ENDIF 206: ENDIF 207: MOV TEMP[13].y, TEMP[16].xxxx 207: MOV TEMP[13].y, TEMP[16].xxxx 208: MOV TEMP[16].zw, IMM[0].yyzy 208: MOV TEMP[16].zw, IMM[0].yyzy 209: MOV TEMP[16].xy, TEMP[13].xyxx 209: MOV TEMP[16].xy, TEMP[13].xyxx 210: MAD TEMP[23], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 210: MAD TEMP[23], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 211: FSGE TEMP[27].x, CONST[34].zzzz, IMM[0].zzzz 211: FSGE TEMP[27].x, CONST[34].zzzz, IMM[0].zzzz 212: UIF TEMP[27].xxxx :0 212: UIF TEMP[27].xxxx :0 213: MOV TEMP[27].x, TEMP[23].xxxx 213: MOV TEMP[27].x, TEMP[23].xxxx 214: ELSE :0 214: ELSE :0 215: MOV TEMP[27].x, IN[3].xxxx 215: MOV TEMP[27].x, IN[3].xxxx 216: ENDIF 216: ENDIF 217: FSGE TEMP[28].x, CONST[34].zzzz, IMM[0].zzzz 217: FSGE TEMP[28].x, CONST[34].zzzz, IMM[0].zzzz 218: UIF TEMP[28].xxxx :0 218: UIF TEMP[28].xxxx :0 219: MOV TEMP[28].x, TEMP[23].yyyy 219: MOV TEMP[28].x, TEMP[23].yyyy 220: ELSE :0 220: ELSE :0 221: MOV TEMP[28].x, IN[3].yyyy 221: MOV TEMP[28].x, IN[3].yyyy 222: ENDIF 222: ENDIF 223: FSGE TEMP[29].x, CONST[34].xxxx, IMM[0].zzzz 223: FSGE TEMP[29].x, CONST[34].xxxx, IMM[0].zzzz 224: UIF TEMP[29].xxxx :0 224: UIF TEMP[29].xxxx :0 225: MOV TEMP[29].x, TEMP[23].zzzz 225: MOV TEMP[29].x, TEMP[23].zzzz 226: ELSE :0 226: ELSE :0 227: MOV TEMP[29].x, TEMP[27].xxxx 227: MOV TEMP[29].x, TEMP[27].xxxx 228: ENDIF 228: ENDIF 229: MOV TEMP[13].x, TEMP[29].xxxx 229: MOV TEMP[13].x, TEMP[29].xxxx 230: FSGE TEMP[27].x, CONST[34].yyyy, IMM[0].zzzz 230: FSGE TEMP[27].x, CONST[34].yyyy, IMM[0].zzzz 231: UIF TEMP[27].xxxx :0 231: UIF TEMP[27].xxxx :0 232: MOV TEMP[23].x, TEMP[23].wwww 232: MOV TEMP[23].x, TEMP[23].wwww 233: ELSE :0 233: ELSE :0 234: MOV TEMP[23].x, TEMP[28].xxxx 234: MOV TEMP[23].x, TEMP[28].xxxx 235: ENDIF 235: ENDIF 236: MOV TEMP[13].y, TEMP[23].xxxx 236: MOV TEMP[13].y, TEMP[23].xxxx 237: MOV TEMP[23].zw, IMM[0].yyzy 237: MOV TEMP[23].zw, IMM[0].yyzy 238: MOV TEMP[23].xy, TEMP[13].xyxx 238: MOV TEMP[23].xy, TEMP[13].xyxx 239: MAD TEMP[13], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 239: MAD TEMP[13], TEMP[4].xyzz, IMM[1].zyyz, IMM[0].wwww 240: FSGE TEMP[27].x, CONST[35].zzzz, IMM[0].zzzz 240: FSGE TEMP[27].x, CONST[35].zzzz, IMM[0].zzzz 241: UIF TEMP[27].xxxx :0 241: UIF TEMP[27].xxxx :0 242: MOV TEMP[27].x, TEMP[13].xxxx 242: MOV TEMP[27].x, TEMP[13].xxxx 243: ELSE :0 243: ELSE :0 244: MOV TEMP[27].x, IN[9].xxxx 244: MOV TEMP[27].x, IN[9].xxxx 245: ENDIF 245: ENDIF 246: FSGE TEMP[28].x, CONST[35].zzzz, IMM[0].zzzz 246: FSGE TEMP[28].x, CONST[35].zzzz, IMM[0].zzzz 247: UIF TEMP[28].xxxx :0 247: UIF TEMP[28].xxxx :0 248: MOV TEMP[28].x, TEMP[13].yyyy 248: MOV TEMP[28].x, TEMP[13].yyyy 249: ELSE :0 249: ELSE :0 250: MOV TEMP[28].x, IN[9].yyyy 250: MOV TEMP[28].x, IN[9].yyyy 251: ENDIF 251: ENDIF 252: FSGE TEMP[29].x, CONST[35].xxxx, IMM[0].zzzz 252: FSGE TEMP[29].x, CONST[35].xxxx, IMM[0].zzzz 253: UIF TEMP[29].xxxx :0 253: UIF TEMP[29].xxxx :0 254: MOV TEMP[29].x, TEMP[13].zzzz 254: MOV TEMP[29].x, TEMP[13].zzzz 255: ELSE :0 255: ELSE :0 256: MOV TEMP[29].x, TEMP[27].xxxx 256: MOV TEMP[29].x, TEMP[27].xxxx 257: ENDIF 257: ENDIF 258: MOV TEMP[4].x, TEMP[29].xxxx 258: MOV TEMP[4].x, TEMP[29].xxxx 259: FSGE TEMP[27].x, CONST[35].yyyy, IMM[0].zzzz 259: FSGE TEMP[27].x, CONST[35].yyyy, IMM[0].zzzz 260: UIF TEMP[27].xxxx :0 260: UIF TEMP[27].xxxx :0 261: MOV TEMP[13].x, TEMP[13].wwww 261: MOV TEMP[13].x, TEMP[13].wwww 262: ELSE :0 262: ELSE :0 263: MOV TEMP[13].x, TEMP[28].xxxx 263: MOV TEMP[13].x, TEMP[28].xxxx 264: ENDIF 264: ENDIF 265: MOV TEMP[4].y, TEMP[13].xxxx 265: MOV TEMP[4].y, TEMP[13].xxxx 266: MAD TEMP[13].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww 266: MAD TEMP[13].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww 267: DP4 TEMP[27].x, TEMP[14], CONST[27] 267: DP4 TEMP[27].x, TEMP[14], CONST[27] 268: DP4 TEMP[14].x, TEMP[14], CONST[28] 268: DP4 TEMP[14].x, TEMP[14], CONST[28] 269: MOV TEMP[27].y, TEMP[14].xxxx 269: MOV TEMP[27].y, TEMP[14].xxxx 270: MOV TEMP[13].zw, TEMP[27].yyxy 270: MOV TEMP[13].zw, TEMP[27].yyxy 271: DP4 TEMP[14].x, TEMP[15], CONST[7] 271: DP4 TEMP[14].x, TEMP[15], CONST[7] 272: DP4 TEMP[15].x, TEMP[15], CONST[8] 272: DP4 TEMP[15].x, TEMP[15], CONST[8] 273: MOV TEMP[14].y, TEMP[15].xxxx 273: MOV TEMP[14].y, TEMP[15].xxxx 274: MOV TEMP[14].xy, TEMP[14].xyxx 274: MOV TEMP[14].xy, TEMP[14].xyxx 275: DP4 TEMP[15].x, TEMP[16], CONST[25] 275: DP4 TEMP[15].x, TEMP[16], CONST[25] 276: DP4 TEMP[16].x, TEMP[16], CONST[26] 276: DP4 TEMP[16].x, TEMP[16], CONST[26] 277: MOV TEMP[15].y, TEMP[16].xxxx 277: MOV TEMP[15].y, TEMP[16].xxxx 278: MOV TEMP[14].zw, TEMP[15].yyxy 278: MOV TEMP[14].zw, TEMP[15].yyxy 279: DP4 TEMP[15].x, TEMP[23], CONST[23] 279: DP4 TEMP[15].x, TEMP[23], CONST[23] 280: DP4 TEMP[16].x, TEMP[23], CONST[24] 280: DP4 TEMP[16].x, TEMP[23], CONST[24] 281: MOV TEMP[15].y, TEMP[16].xxxx 281: MOV TEMP[15].y, TEMP[16].xxxx 282: MOV TEMP[15].xy, TEMP[15].xyxx 282: MOV TEMP[15].xy, TEMP[15].xyxx 283: MAD TEMP[4].xy, TEMP[4].xyyy, CONST[9].xyyy, CONST[9].zwww 283: MAD TEMP[4].xy, TEMP[4].xyyy, CONST[9].xyyy, CONST[9].zwww 284: MOV TEMP[15].zw, TEMP[4].yyxy 284: MOV TEMP[15].zw, TEMP[4].yyxy 285: MOV TEMP[4].w, IN[7].wwww 285: MOV TEMP[4].w, IN[7].wwww 286: MUL TEMP[4].xyz, IN[7].zyxx, IMM[1].wwww 286: MUL TEMP[4].xyz, IN[7].zyxx, IMM[1].wwww 287: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[4].xyzz 287: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[4].xyzz 288: MAD TEMP[4], TEMP[4], CONST[30].xxxx, CONST[30].yyyy 288: MAD TEMP[4], TEMP[4], CONST[30].xxxx, CONST[30].yyyy 289: MOV TEMP[0].xyz, TEMP[0].xyzx 289: MOV TEMP[0].xyz, TEMP[0].xyzx 290: MOV TEMP[0].w, TEMP[1].xxxx 290: MOV TEMP[0].w, TEMP[1].xxxx 291: MOV TEMP[1].xy, TEMP[1].yzyy 291: MOV TEMP[1].xy, TEMP[1].yzyy 292: MOV TEMP[1].zw, TEMP[2].yyxy 292: MOV TEMP[1].zw, TEMP[2].yyxy 293: MOV TEMP[2].x, TEMP[2].zzzz 293: MOV TEMP[2].x, TEMP[2].zzzz 294: MOV TEMP[2].yzw, TEMP[12].yxyz 294: MOV TEMP[2].yzw, TEMP[12].yxyz 295: MOV OUT[2], TEMP[14] 295: MOV OUT[2], TEMP[14] 296: MOV OUT[9], TEMP[2] 296: MOV OUT[9], TEMP[2] 297: MOV OUT[6], TEMP[5] 297: MOV OUT[6], TEMP[5] 298: MOV OUT[8], TEMP[1] 298: MOV OUT[8], TEMP[1] 299: MOV OUT[3], TEMP[13] 299: MOV OUT[3], TEMP[13] 300: MOV OUT[7], TEMP[0] 300: MOV OUT[7], TEMP[0] 301: MOV OUT[0], TEMP[3] 301: MOV OUT[0], TEMP[3] 302: MOV OUT[5], TEMP[4] 302: MOV OUT[5], TEMP[4] 303: MOV OUT[1], TEMP[3] 303: MOV OUT[1], TEMP[3] 304: MOV OUT[4], TEMP[15] 304: MOV OUT[4], TEMP[15] 305: END 305: END ; ModuleID = 'tgsi' ; ModuleID = 'tgsi' define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 main_body: main_body: %11 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %11 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0 %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0 %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %12, i32 0) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %12, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %12, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %12, i32 12) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %12, i32 16) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %12, i32 20) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %12, i32 24) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %12, i32 28) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %12, i32 32) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %12, i32 36) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %12, i32 40) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %12, i32 44) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %12, i32 48) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %12, i32 52) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %12, i32 56) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %12, i32 60) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 64) %29 = call float @llvm.SI.load.const(<16 x i8> %12, i32 64) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 68) %30 = call float @llvm.SI.load.const(<16 x i8> %12, i32 68) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 72) %31 = call float @llvm.SI.load.const(<16 x i8> %12, i32 72) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 76) %32 = call float @llvm.SI.load.const(<16 x i8> %12, i32 76) %33 = call float @llvm.SI.load.const(<16 x i8> %12, i32 80) %33 = call float @llvm.SI.load.const(<16 x i8> %12, i32 80) %34 = call float @llvm.SI.load.const(<16 x i8> %12, i32 84) %34 = call float @llvm.SI.load.const(<16 x i8> %12, i32 84) %35 = call float @llvm.SI.load.const(<16 x i8> %12, i32 88) %35 = call float @llvm.SI.load.const(<16 x i8> %12, i32 88) %36 = call float @llvm.SI.load.const(<16 x i8> %12, i32 92) %36 = call float @llvm.SI.load.const(<16 x i8> %12, i32 92) %37 = call float @llvm.SI.load.const(<16 x i8> %12, i32 96) %37 = call float @llvm.SI.load.const(<16 x i8> %12, i32 96) %38 = call float @llvm.SI.load.const(<16 x i8> %12, i32 100) %38 = call float @llvm.SI.load.const(<16 x i8> %12, i32 100) %39 = call float @llvm.SI.load.const(<16 x i8> %12, i32 104) %39 = call float @llvm.SI.load.const(<16 x i8> %12, i32 104) %40 = call float @llvm.SI.load.const(<16 x i8> %12, i32 108) %40 = call float @llvm.SI.load.const(<16 x i8> %12, i32 108) %41 = call float @llvm.SI.load.const(<16 x i8> %12, i32 112) %41 = call float @llvm.SI.load.const(<16 x i8> %12, i32 112) %42 = call float @llvm.SI.load.const(<16 x i8> %12, i32 116) %42 = call float @llvm.SI.load.const(<16 x i8> %12, i32 116) %43 = call float @llvm.SI.load.const(<16 x i8> %12, i32 120) %43 = call float @llvm.SI.load.const(<16 x i8> %12, i32 120) %44 = call float @llvm.SI.load.const(<16 x i8> %12, i32 124) %44 = call float @llvm.SI.load.const(<16 x i8> %12, i32 124) %45 = call float @llvm.SI.load.const(<16 x i8> %12, i32 128) %45 = call float @llvm.SI.load.const(<16 x i8> %12, i32 128) %46 = call float @llvm.SI.load.const(<16 x i8> %12, i32 132) %46 = call float @llvm.SI.load.const(<16 x i8> %12, i32 132) %47 = call float @llvm.SI.load.const(<16 x i8> %12, i32 136) %47 = call float @llvm.SI.load.const(<16 x i8> %12, i32 136) %48 = call float @llvm.SI.load.const(<16 x i8> %12, i32 140) %48 = call float @llvm.SI.load.const(<16 x i8> %12, i32 140) %49 = call float @llvm.SI.load.const(<16 x i8> %12, i32 144) %49 = call float @llvm.SI.load.const(<16 x i8> %12, i32 144) %50 = call float @llvm.SI.load.const(<16 x i8> %12, i32 148) %50 = call float @llvm.SI.load.const(<16 x i8> %12, i32 148) %51 = call float @llvm.SI.load.const(<16 x i8> %12, i32 152) %51 = call float @llvm.SI.load.const(<16 x i8> %12, i32 152) %52 = call float @llvm.SI.load.const(<16 x i8> %12, i32 156) %52 = call float @llvm.SI.load.const(<16 x i8> %12, i32 156) %53 = call float @llvm.SI.load.const(<16 x i8> %12, i32 224) %53 = call float @llvm.SI.load.const(<16 x i8> %12, i32 224) %54 = call float @llvm.SI.load.const(<16 x i8> %12, i32 228) %54 = call float @llvm.SI.load.const(<16 x i8> %12, i32 228) %55 = call float @llvm.SI.load.const(<16 x i8> %12, i32 232) %55 = call float @llvm.SI.load.const(<16 x i8> %12, i32 232) %56 = call float @llvm.SI.load.const(<16 x i8> %12, i32 240) %56 = call float @llvm.SI.load.const(<16 x i8> %12, i32 240) %57 = call float @llvm.SI.load.const(<16 x i8> %12, i32 244) %57 = call float @llvm.SI.load.const(<16 x i8> %12, i32 244) %58 = call float @llvm.SI.load.const(<16 x i8> %12, i32 248) %58 = call float @llvm.SI.load.const(<16 x i8> %12, i32 248) %59 = call float @llvm.SI.load.const(<16 x i8> %12, i32 256) %59 = call float @llvm.SI.load.const(<16 x i8> %12, i32 256) %60 = call float @llvm.SI.load.const(<16 x i8> %12, i32 260) %60 = call float @llvm.SI.load.const(<16 x i8> %12, i32 260) %61 = call float @llvm.SI.load.const(<16 x i8> %12, i32 264) %61 = call float @llvm.SI.load.const(<16 x i8> %12, i32 264) %62 = call float @llvm.SI.load.const(<16 x i8> %12, i32 272) %62 = call float @llvm.SI.load.const(<16 x i8> %12, i32 272) %63 = call float @llvm.SI.load.const(<16 x i8> %12, i32 276) %63 = call float @llvm.SI.load.const(<16 x i8> %12, i32 276) %64 = call float @llvm.SI.load.const(<16 x i8> %12, i32 280) %64 = call float @llvm.SI.load.const(<16 x i8> %12, i32 280) %65 = call float @llvm.SI.load.const(<16 x i8> %12, i32 288) %65 = call float @llvm.SI.load.const(<16 x i8> %12, i32 288) %66 = call float @llvm.SI.load.const(<16 x i8> %12, i32 292) %66 = call float @llvm.SI.load.const(<16 x i8> %12, i32 292) %67 = call float @llvm.SI.load.const(<16 x i8> %12, i32 296) %67 = call float @llvm.SI.load.const(<16 x i8> %12, i32 296) %68 = call float @llvm.SI.load.const(<16 x i8> %12, i32 304) %68 = call float @llvm.SI.load.const(<16 x i8> %12, i32 304) %69 = call float @llvm.SI.load.const(<16 x i8> %12, i32 308) %69 = call float @llvm.SI.load.const(<16 x i8> %12, i32 308) %70 = call float @llvm.SI.load.const(<16 x i8> %12, i32 312) %70 = call float @llvm.SI.load.const(<16 x i8> %12, i32 312) %71 = call float @llvm.SI.load.const(<16 x i8> %12, i32 320) %71 = call float @llvm.SI.load.const(<16 x i8> %12, i32 320) %72 = call float @llvm.SI.load.const(<16 x i8> %12, i32 324) %72 = call float @llvm.SI.load.const(<16 x i8> %12, i32 324) %73 = call float @llvm.SI.load.const(<16 x i8> %12, i32 328) %73 = call float @llvm.SI.load.const(<16 x i8> %12, i32 328) %74 = call float @llvm.SI.load.const(<16 x i8> %12, i32 336) %74 = call float @llvm.SI.load.const(<16 x i8> %12, i32 336) %75 = call float @llvm.SI.load.const(<16 x i8> %12, i32 340) %75 = call float @llvm.SI.load.const(<16 x i8> %12, i32 340) %76 = call float @llvm.SI.load.const(<16 x i8> %12, i32 344) %76 = call float @llvm.SI.load.const(<16 x i8> %12, i32 344) %77 = call float @llvm.SI.load.const(<16 x i8> %12, i32 352) %77 = call float @llvm.SI.load.const(<16 x i8> %12, i32 352) %78 = call float @llvm.SI.load.const(<16 x i8> %12, i32 356) %78 = call float @llvm.SI.load.const(<16 x i8> %12, i32 356) %79 = call float @llvm.SI.load.const(<16 x i8> %12, i32 360) %79 = call float @llvm.SI.load.const(<16 x i8> %12, i32 360) %80 = call float @llvm.SI.load.const(<16 x i8> %12, i32 368) %80 = call float @llvm.SI.load.const(<16 x i8> %12, i32 368) %81 = call float @llvm.SI.load.const(<16 x i8> %12, i32 372) %81 = call float @llvm.SI.load.const(<16 x i8> %12, i32 372) %82 = call float @llvm.SI.load.const(<16 x i8> %12, i32 376) %82 = call float @llvm.SI.load.const(<16 x i8> %12, i32 376) %83 = call float @llvm.SI.load.const(<16 x i8> %12, i32 380) %83 = call float @llvm.SI.load.const(<16 x i8> %12, i32 380) %84 = call float @llvm.SI.load.const(<16 x i8> %12, i32 384) %84 = call float @llvm.SI.load.const(<16 x i8> %12, i32 384) %85 = call float @llvm.SI.load.const(<16 x i8> %12, i32 388) %85 = call float @llvm.SI.load.const(<16 x i8> %12, i32 388) %86 = call float @llvm.SI.load.const(<16 x i8> %12, i32 392) %86 = call float @llvm.SI.load.const(<16 x i8> %12, i32 392) %87 = call float @llvm.SI.load.const(<16 x i8> %12, i32 396) %87 = call float @llvm.SI.load.const(<16 x i8> %12, i32 396) %88 = call float @llvm.SI.load.const(<16 x i8> %12, i32 400) %88 = call float @llvm.SI.load.const(<16 x i8> %12, i32 400) %89 = call float @llvm.SI.load.const(<16 x i8> %12, i32 404) %89 = call float @llvm.SI.load.const(<16 x i8> %12, i32 404) %90 = call float @llvm.SI.load.const(<16 x i8> %12, i32 408) %90 = call float @llvm.SI.load.const(<16 x i8> %12, i32 408) %91 = call float @llvm.SI.load.const(<16 x i8> %12, i32 412) %91 = call float @llvm.SI.load.const(<16 x i8> %12, i32 412) %92 = call float @llvm.SI.load.const(<16 x i8> %12, i32 416) %92 = call float @llvm.SI.load.const(<16 x i8> %12, i32 416) %93 = call float @llvm.SI.load.const(<16 x i8> %12, i32 420) %93 = call float @llvm.SI.load.const(<16 x i8> %12, i32 420) %94 = call float @llvm.SI.load.const(<16 x i8> %12, i32 424) %94 = call float @llvm.SI.load.const(<16 x i8> %12, i32 424) %95 = call float @llvm.SI.load.const(<16 x i8> %12, i32 428) %95 = call float @llvm.SI.load.const(<16 x i8> %12, i32 428) %96 = call float @llvm.SI.load.const(<16 x i8> %12, i32 432) %96 = call float @llvm.SI.load.const(<16 x i8> %12, i32 432) %97 = call float @llvm.SI.load.const(<16 x i8> %12, i32 436) %97 = call float @llvm.SI.load.const(<16 x i8> %12, i32 436) %98 = call float @llvm.SI.load.const(<16 x i8> %12, i32 440) %98 = call float @llvm.SI.load.const(<16 x i8> %12, i32 440) %99 = call float @llvm.SI.load.const(<16 x i8> %12, i32 444) %99 = call float @llvm.SI.load.const(<16 x i8> %12, i32 444) %100 = call float @llvm.SI.load.const(<16 x i8> %12, i32 448) %100 = call float @llvm.SI.load.const(<16 x i8> %12, i32 448) %101 = call float @llvm.SI.load.const(<16 x i8> %12, i32 452) %101 = call float @llvm.SI.load.const(<16 x i8> %12, i32 452) %102 = call float @llvm.SI.load.const(<16 x i8> %12, i32 456) %102 = call float @llvm.SI.load.const(<16 x i8> %12, i32 456) %103 = call float @llvm.SI.load.const(<16 x i8> %12, i32 460) %103 = call float @llvm.SI.load.const(<16 x i8> %12, i32 460) %104 = call float @llvm.SI.load.const(<16 x i8> %12, i32 464) %104 = call float @llvm.SI.load.const(<16 x i8> %12, i32 464) %105 = call float @llvm.SI.load.const(<16 x i8> %12, i32 468) %105 = call float @llvm.SI.load.const(<16 x i8> %12, i32 468) %106 = call float @llvm.SI.load.const(<16 x i8> %12, i32 472) %106 = call float @llvm.SI.load.const(<16 x i8> %12, i32 472) %107 = call float @llvm.SI.load.const(<16 x i8> %12, i32 476) %107 = call float @llvm.SI.load.const(<16 x i8> %12, i32 476) %108 = call float @llvm.SI.load.const(<16 x i8> %12, i32 480) %108 = call float @llvm.SI.load.const(<16 x i8> %12, i32 480) %109 = call float @llvm.SI.load.const(<16 x i8> %12, i32 484) %109 = call float @llvm.SI.load.const(<16 x i8> %12, i32 484) %110 = call float @llvm.SI.load.const(<16 x i8> %12, i32 496) %110 = call float @llvm.SI.load.const(<16 x i8> %12, i32 496) %111 = call float @llvm.SI.load.const(<16 x i8> %12, i32 500) %111 = call float @llvm.SI.load.const(<16 x i8> %12, i32 500) %112 = call float @llvm.SI.load.const(<16 x i8> %12, i32 504) %112 = call float @llvm.SI.load.const(<16 x i8> %12, i32 504) %113 = call float @llvm.SI.load.const(<16 x i8> %12, i32 512) %113 = call float @llvm.SI.load.const(<16 x i8> %12, i32 512) %114 = call float @llvm.SI.load.const(<16 x i8> %12, i32 516) %114 = call float @llvm.SI.load.const(<16 x i8> %12, i32 516) %115 = call float @llvm.SI.load.const(<16 x i8> %12, i32 520) %115 = call float @llvm.SI.load.const(<16 x i8> %12, i32 520) %116 = call float @llvm.SI.load.const(<16 x i8> %12, i32 528) %116 = call float @llvm.SI.load.const(<16 x i8> %12, i32 528) %117 = call float @llvm.SI.load.const(<16 x i8> %12, i32 532) %117 = call float @llvm.SI.load.const(<16 x i8> %12, i32 532) %118 = call float @llvm.SI.load.const(<16 x i8> %12, i32 536) %118 = call float @llvm.SI.load.const(<16 x i8> %12, i32 536) %119 = call float @llvm.SI.load.const(<16 x i8> %12, i32 544) %119 = call float @llvm.SI.load.const(<16 x i8> %12, i32 544) %120 = call float @llvm.SI.load.const(<16 x i8> %12, i32 548) %120 = call float @llvm.SI.load.const(<16 x i8> %12, i32 548) %121 = call float @llvm.SI.load.const(<16 x i8> %12, i32 552) %121 = call float @llvm.SI.load.const(<16 x i8> %12, i32 552) %122 = call float @llvm.SI.load.const(<16 x i8> %12, i32 560) %122 = call float @llvm.SI.load.const(<16 x i8> %12, i32 560) %123 = call float @llvm.SI.load.const(<16 x i8> %12, i32 564) %123 = call float @llvm.SI.load.const(<16 x i8> %12, i32 564) %124 = call float @llvm.SI.load.const(<16 x i8> %12, i32 568) %124 = call float @llvm.SI.load.const(<16 x i8> %12, i32 568) %125 = call float @llvm.SI.load.const(<16 x i8> %12, i32 576) %125 = call float @llvm.SI.load.const(<16 x i8> %12, i32 576) %126 = call float @llvm.SI.load.const(<16 x i8> %12, i32 580) %126 = call float @llvm.SI.load.const(<16 x i8> %12, i32 580) %127 = call float @llvm.SI.load.const(<16 x i8> %12, i32 584) %127 = call float @llvm.SI.load.const(<16 x i8> %12, i32 584) %128 = call float @llvm.SI.load.const(<16 x i8> %12, i32 592) %128 = call float @llvm.SI.load.const(<16 x i8> %12, i32 592) %129 = call float @llvm.SI.load.const(<16 x i8> %12, i32 596) %129 = call float @llvm.SI.load.const(<16 x i8> %12, i32 596) %130 = call float @llvm.SI.load.const(<16 x i8> %12, i32 600) %130 = call float @llvm.SI.load.const(<16 x i8> %12, i32 600) %131 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %131 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %132 = load <16 x i8>, <16 x i8> addrspace(2)* %131, align 16, !tbaa !0 %132 = load <16 x i8>, <16 x i8> addrspace(2)* %131, align 16, !tbaa !0 %133 = add i32 %5, %7 %133 = add i32 %5, %7 %134 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %133) %134 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %132, i32 0, i32 %133) %135 = extractelement <4 x float> %134, i32 0 %135 = extractelement <4 x float> %134, i32 0 %136 = extractelement <4 x float> %134, i32 1 %136 = extractelement <4 x float> %134, i32 1 %137 = extractelement <4 x float> %134, i32 2 %137 = extractelement <4 x float> %134, i32 2 %138 = extractelement <4 x float> %134, i32 3 %138 = extractelement <4 x float> %134, i32 3 %139 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %139 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %140 = load <16 x i8>, <16 x i8> addrspace(2)* %139, align 16, !tbaa !0 %140 = load <16 x i8>, <16 x i8> addrspace(2)* %139, align 16, !tbaa !0 %141 = add i32 %5, %7 %141 = add i32 %5, %7 %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %140, i32 0, i32 %141) %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %140, i32 0, i32 %141) %143 = extractelement <4 x float> %142, i32 0 %143 = extractelement <4 x float> %142, i32 0 %144 = extractelement <4 x float> %142, i32 1 %144 = extractelement <4 x float> %142, i32 1 %145 = extractelement <4 x float> %142, i32 2 %145 = extractelement <4 x float> %142, i32 2 %146 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %146 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %147 = load <16 x i8>, <16 x i8> addrspace(2)* %146, align 16, !tbaa !0 %147 = load <16 x i8>, <16 x i8> addrspace(2)* %146, align 16, !tbaa !0 %148 = add i32 %5, %7 %148 = add i32 %5, %7 %149 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %147, i32 0, i32 %148) %149 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %147, i32 0, i32 %148) %150 = extractelement <4 x float> %149, i32 0 %150 = extractelement <4 x float> %149, i32 0 %151 = extractelement <4 x float> %149, i32 1 %151 = extractelement <4 x float> %149, i32 1 %152 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %152 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %153 = load <16 x i8>, <16 x i8> addrspace(2)* %152, align 16, !tbaa !0 %153 = load <16 x i8>, <16 x i8> addrspace(2)* %152, align 16, !tbaa !0 %154 = add i32 %5, %7 %154 = add i32 %5, %7 %155 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %153, i32 0, i32 %154) %155 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %153, i32 0, i32 %154) %156 = extractelement <4 x float> %155, i32 0 %156 = extractelement <4 x float> %155, i32 0 %157 = extractelement <4 x float> %155, i32 1 %157 = extractelement <4 x float> %155, i32 1 %158 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %158 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %159 = load <16 x i8>, <16 x i8> addrspace(2)* %158, align 16, !tbaa !0 %159 = load <16 x i8>, <16 x i8> addrspace(2)* %158, align 16, !tbaa !0 %160 = add i32 %5, %7 %160 = add i32 %5, %7 %161 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %159, i32 0, i32 %160) %161 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %159, i32 0, i32 %160) %162 = extractelement <4 x float> %161, i32 0 %162 = extractelement <4 x float> %161, i32 0 %163 = extractelement <4 x float> %161, i32 1 %163 = extractelement <4 x float> %161, i32 1 %164 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 5 %164 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 5 %165 = load <16 x i8>, <16 x i8> addrspace(2)* %164, align 16, !tbaa !0 %165 = load <16 x i8>, <16 x i8> addrspace(2)* %164, align 16, !tbaa !0 %166 = add i32 %5, %7 %166 = add i32 %5, %7 %167 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %165, i32 0, i32 %166) %167 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %165, i32 0, i32 %166) %168 = extractelement <4 x float> %167, i32 0 %168 = extractelement <4 x float> %167, i32 0 %169 = extractelement <4 x float> %167, i32 1 %169 = extractelement <4 x float> %167, i32 1 %170 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 6 %170 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 6 %171 = load <16 x i8>, <16 x i8> addrspace(2)* %170, align 16, !tbaa !0 %171 = load <16 x i8>, <16 x i8> addrspace(2)* %170, align 16, !tbaa !0 %172 = add i32 %5, %7 %172 = add i32 %5, %7 %173 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %171, i32 0, i32 %172) %173 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %171, i32 0, i32 %172) %174 = extractelement <4 x float> %173, i32 0 %174 = extractelement <4 x float> %173, i32 0 %175 = extractelement <4 x float> %173, i32 1 %175 = extractelement <4 x float> %173, i32 1 %176 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 7 %176 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 7 %177 = load <16 x i8>, <16 x i8> addrspace(2)* %176, align 16, !tbaa !0 %177 = load <16 x i8>, <16 x i8> addrspace(2)* %176, align 16, !tbaa !0 %178 = add i32 %5, %7 %178 = add i32 %5, %7 %179 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %177, i32 0, i32 %178) %179 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %177, i32 0, i32 %178) %180 = extractelement <4 x float> %179, i32 0 %180 = extractelement <4 x float> %179, i32 0 %181 = extractelement <4 x float> %179, i32 1 %181 = extractelement <4 x float> %179, i32 1 %182 = extractelement <4 x float> %179, i32 2 %182 = extractelement <4 x float> %179, i32 2 %183 = extractelement <4 x float> %179, i32 3 %183 = extractelement <4 x float> %179, i32 3 %184 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 8 %184 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 8 %185 = load <16 x i8>, <16 x i8> addrspace(2)* %184, align 16, !tbaa !0 %185 = load <16 x i8>, <16 x i8> addrspace(2)* %184, align 16, !tbaa !0 %186 = add i32 %5, %7 %186 = add i32 %5, %7 %187 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %185, i32 0, i32 %186) %187 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %185, i32 0, i32 %186) %188 = extractelement <4 x float> %187, i32 0 %188 = extractelement <4 x float> %187, i32 0 %189 = extractelement <4 x float> %187, i32 1 %189 = extractelement <4 x float> %187, i32 1 %190 = extractelement <4 x float> %187, i32 2 %190 = extractelement <4 x float> %187, i32 2 %191 = extractelement <4 x float> %187, i32 3 %191 = extractelement <4 x float> %187, i32 3 %192 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 9 %192 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 9 %193 = load <16 x i8>, <16 x i8> addrspace(2)* %192, align 16, !tbaa !0 %193 = load <16 x i8>, <16 x i8> addrspace(2)* %192, align 16, !tbaa !0 %194 = add i32 %5, %7 %194 = add i32 %5, %7 %195 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %193, i32 0, i32 %194) %195 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %193, i32 0, i32 %194) %196 = extractelement <4 x float> %195, i32 0 %196 = extractelement <4 x float> %195, i32 0 %197 = extractelement <4 x float> %195, i32 1 %197 = extractelement <4 x float> %195, i32 1 %198 = fmul float %143, %127 %198 = fmul float %143, %127 %199 = fadd float %198, %125 %199 = fadd float %198, %125 %200 = fmul float %144, %127 %200 = fmul float %144, %127 %201 = fadd float %200, %126 %201 = fadd float %200, %126 %202 = fmul float %145, %127 %202 = fmul float %145, %127 %203 = fadd float %202, %125 %203 = fadd float %202, %125 %204 = fadd float %201, 0x3F50624DE0000000 %204 = fadd float %201, 0x3F50624DE0000000 %205 = fmul float %188, %130 %205 = fmul float %188, %130 %206 = fadd float %205, %128 %206 = fadd float %205, %128 %207 = fmul float %189, %130 %207 = fmul float %189, %130 %208 = fadd float %207, %129 %208 = fadd float %207, %129 %209 = fmul float %190, %130 %209 = fmul float %190, %130 %210 = fadd float %209, %129 %210 = fadd float %209, %129 %211 = fmul float %191, %130 %211 = fmul float %191, %130 %212 = fadd float %211, %128 %212 = fadd float %211, %128 %213 = fadd float %206, 0x3F50624DE0000000 %213 = fadd float %206, 0x3F50624DE0000000 %214 = fmul float %135, %13 %214 = fmul float %135, %13 %215 = fmul float %136, %14 %215 = fmul float %136, %14 %216 = fadd float %214, %215 %216 = fadd float %214, %215 %217 = fmul float %137, %15 %217 = fmul float %137, %15 %218 = fadd float %216, %217 %218 = fadd float %216, %217 %219 = fmul float %138, %16 %219 = fmul float %138, %16 %220 = fadd float %218, %219 %220 = fadd float %218, %219 %221 = fmul float %135, %17 %221 = fmul float %135, %17 %222 = fmul float %136, %18 %222 = fmul float %136, %18 %223 = fadd float %221, %222 %223 = fadd float %221, %222 %224 = fmul float %137, %19 %224 = fmul float %137, %19 %225 = fadd float %223, %224 %225 = fadd float %223, %224 %226 = fmul float %138, %20 %226 = fmul float %138, %20 %227 = fadd float %225, %226 %227 = fadd float %225, %226 %228 = fmul float %135, %21 %228 = fmul float %135, %21 %229 = fmul float %136, %22 %229 = fmul float %136, %22 %230 = fadd float %228, %229 %230 = fadd float %228, %229 %231 = fmul float %137, %23 %231 = fmul float %137, %23 %232 = fadd float %230, %231 %232 = fadd float %230, %231 %233 = fmul float %138, %24 %233 = fmul float %138, %24 %234 = fadd float %232, %233 %234 = fadd float %232, %233 %235 = fmul float %135, %25 %235 = fmul float %135, %25 %236 = fmul float %136, %26 %236 = fmul float %136, %26 %237 = fadd float %235, %236 %237 = fadd float %235, %236 %238 = fmul float %137, %27 %238 = fmul float %137, %27 %239 = fadd float %237, %238 %239 = fadd float %237, %238 %240 = fmul float %138, %28 %240 = fmul float %138, %28 %241 = fadd float %239, %240 %241 = fadd float %239, %240 %242 = fmul float %135, %29 %242 = fmul float %135, %29 %243 = fmul float %136, %30 %243 = fmul float %136, %30 %244 = fadd float %242, %243 %244 = fadd float %242, %243 %245 = fmul float %137, %31 %245 = fmul float %137, %31 %246 = fadd float %244, %245 %246 = fadd float %244, %245 %247 = fmul float %138, %32 %247 = fmul float %138, %32 %248 = fadd float %246, %247 %248 = fadd float %246, %247 %249 = fmul float %135, %33 %249 = fmul float %135, %33 %250 = fmul float %136, %34 %250 = fmul float %136, %34 %251 = fadd float %249, %250 %251 = fadd float %249, %250 %252 = fmul float %137, %35 %252 = fmul float %137, %35 %253 = fadd float %251, %252 %253 = fadd float %251, %252 %254 = fmul float %138, %36 %254 = fmul float %138, %36 %255 = fadd float %253, %254 %255 = fadd float %253, %254 %256 = fmul float %135, %37 %256 = fmul float %135, %37 %257 = fmul float %136, %38 %257 = fmul float %136, %38 %258 = fadd float %256, %257 %258 = fadd float %256, %257 %259 = fmul float %137, %39 %259 = fmul float %137, %39 %260 = fadd float %258, %259 %260 = fadd float %258, %259 %261 = fmul float %138, %40 %261 = fmul float %138, %40 %262 = fadd float %260, %261 %262 = fadd float %260, %261 %263 = fmul float %29, %29 %263 = fmul float %29, %29 %264 = fmul float %30, %30 %264 = fmul float %30, %30 %265 = fadd float %264, %263 %265 = fadd float %264, %263 %266 = fmul float %31, %31 %266 = fmul float %31, %31 %267 = fadd float %265, %266 %267 = fadd float %265, %266 %268 = fmul float %33, %33 %268 = fmul float %33, %33 %269 = fmul float %34, %34 %269 = fmul float %34, %34 %270 = fadd float %269, %268 %270 = fadd float %269, %268 %271 = fmul float %35, %35 %271 = fmul float %35, %35 %272 = fadd float %270, %271 %272 = fadd float %270, %271 %273 = fmul float %37, %37 %273 = fmul float %37, %37 %274 = fmul float %38, %38 %274 = fmul float %38, %38 %275 = fadd float %274, %273 %275 = fadd float %274, %273 %276 = fmul float %39, %39 %276 = fmul float %39, %39 %277 = fadd float %275, %276 %277 = fadd float %275, %276 %278 = fdiv float 1.000000e+00, %267 %278 = fdiv float 1.000000e+00, %267 %279 = fdiv float 1.000000e+00, %272 %279 = fdiv float 1.000000e+00, %272 %280 = fdiv float 1.000000e+00, %277 %280 = fdiv float 1.000000e+00, %277 %281 = fmul float %29, %278 %281 = fmul float %29, %278 %282 = fmul float %30, %278 %282 = fmul float %30, %278 %283 = fmul float %31, %278 %283 = fmul float %31, %278 %284 = fmul float %33, %279 %284 = fmul float %33, %279 %285 = fmul float %34, %279 %285 = fmul float %34, %279 %286 = fmul float %35, %279 %286 = fmul float %35, %279 %287 = fmul float %37, %280 %287 = fmul float %37, %280 %288 = fmul float %38, %280 %288 = fmul float %38, %280 %289 = fmul float %39, %280 %289 = fmul float %39, %280 %290 = fmul float %199, %281 %290 = fmul float %199, %281 %291 = fmul float %204, %282 %291 = fmul float %204, %282 %292 = fadd float %291, %290 %292 = fadd float %291, %290 %293 = fmul float %203, %283 %293 = fmul float %203, %283 %294 = fadd float %292, %293 %294 = fadd float %292, %293 %295 = fmul float %199, %284 %295 = fmul float %199, %284 %296 = fmul float %204, %285 %296 = fmul float %204, %285 %297 = fadd float %296, %295 %297 = fadd float %296, %295 %298 = fmul float %203, %286 %298 = fmul float %203, %286 %299 = fadd float %297, %298 %299 = fadd float %297, %298 %300 = fmul float %199, %287 %300 = fmul float %199, %287 %301 = fmul float %204, %288 %301 = fmul float %204, %288 %302 = fadd float %301, %300 %302 = fadd float %301, %300 %303 = fmul float %203, %289 %303 = fmul float %203, %289 %304 = fadd float %302, %303 %304 = fadd float %302, %303 %305 = fmul float %294, %294 %305 = fmul float %294, %294 %306 = fmul float %299, %299 %306 = fmul float %299, %299 %307 = fadd float %306, %305 %307 = fadd float %306, %305 %308 = fmul float %304, %304 %308 = fmul float %304, %304 %309 = fadd float %307, %308 %309 = fadd float %307, %308 %310 = call float @llvm.AMDGPU.rsq.clamped.f32(float %309) %310 = call float @llvm.AMDGPU.rsq.clamped.f32(float %309) %311 = fmul float %294, %310 %311 = fmul float %294, %310 %312 = fmul float %299, %310 %312 = fmul float %299, %310 %313 = fmul float %304, %310 %313 = fmul float %304, %310 %314 = fcmp ogt float %121, 0.000000e+00 %314 = fcmp ogt float %121, 0.000000e+00 br i1 %314, label %IF, label %ELSE br i1 %314, label %IF, label %ELSE IF: ; preds = %main_body IF: ; preds = %main_body %315 = fmul float %311, %311 %315 = fmul float %311, %311 %316 = fmul float %312, %312 %316 = fmul float %312, %312 %317 = fadd float %316, %315 %317 = fadd float %316, %315 %318 = fmul float %313, %313 %318 = fmul float %313, %313 %319 = fadd float %317, %318 %319 = fadd float %317, %318 %320 = call float @llvm.AMDGPU.rsq.clamped.f32(float %319) %320 = call float @llvm.AMDGPU.rsq.clamped.f32(float %319) %321 = fmul float %311, %320 %321 = fmul float %311, %320 %322 = fmul float %312, %320 %322 = fmul float %312, %320 %323 = fmul float %313, %320 %323 = fmul float %313, %320 %324 = fmul float %321, %119 %324 = fmul float %321, %119 %325 = fmul float %322, %119 %325 = fmul float %322, %119 %326 = fmul float %323, %119 %326 = fmul float %323, %119 %327 = fmul float %119, 5.000000e-01 %327 = fmul float %119, 5.000000e-01 %328 = fadd float %327, 5.000000e-01 %328 = fadd float %327, 5.000000e-01 %329 = fsub float 1.000000e+00, %328 %329 = fsub float 1.000000e+00, %328 %330 = fmul float %326, %328 %330 = fmul float %326, %328 %331 = fmul float %324, 0.000000e+00 %331 = fmul float %324, 0.000000e+00 %332 = fmul float %325, %329 %332 = fmul float %325, %329 %333 = fmul float %325, 0.000000e+00 %333 = fmul float %325, 0.000000e+00 %334 = fsub float %333, %330 %334 = fsub float %333, %330 %335 = fmul float %326, %329 %335 = fmul float %326, %329 %336 = fsub float %335, %331 %336 = fsub float %335, %331 %337 = fmul float %324, %328 %337 = fmul float %324, %328 %338 = fsub float %337, %332 %338 = fsub float %337, %332 %339 = fmul float %338, %325 %339 = fmul float %338, %325 %340 = fmul float %334, %326 %340 = fmul float %334, %326 %341 = fmul float %336, %324 %341 = fmul float %336, %324 %342 = fmul float %336, %326 %342 = fmul float %336, %326 %343 = fsub float %342, %339 %343 = fsub float %342, %339 %344 = fmul float %338, %324 %344 = fmul float %338, %324 %345 = fsub float %344, %340 %345 = fsub float %344, %340 %346 = fmul float %334, %325 %346 = fmul float %334, %325 %347 = fsub float %346, %341 %347 = fsub float %346, %341 %348 = fmul float %343, %80 %348 = fmul float %343, %80 %349 = fmul float %345, %80 %349 = fmul float %345, %80 %350 = fmul float %347, %80 %350 = fmul float %347, %80 %351 = fmul float %334, %81 %351 = fmul float %334, %81 %352 = fadd float %351, %348 %352 = fadd float %351, %348 %353 = fmul float %336, %81 %353 = fmul float %336, %81 %354 = fadd float %353, %349 %354 = fadd float %353, %349 %355 = fmul float %338, %81 %355 = fmul float %338, %81 %356 = fadd float %355, %350 %356 = fadd float %355, %350 %357 = fmul float %321, %82 %357 = fmul float %321, %82 %358 = fadd float %357, %352 %358 = fadd float %357, %352 %359 = fmul float %322, %82 %359 = fmul float %322, %82 %360 = fadd float %359, %354 %360 = fadd float %359, %354 %361 = fmul float %323, %82 %361 = fmul float %323, %82 %362 = fadd float %361, %356 %362 = fadd float %361, %356 %363 = fmul float %343, %84 %363 = fmul float %343, %84 %364 = fmul float %345, %84 %364 = fmul float %345, %84 %365 = fmul float %347, %84 %365 = fmul float %347, %84 %366 = fmul float %334, %85 %366 = fmul float %334, %85 %367 = fadd float %366, %363 %367 = fadd float %366, %363 %368 = fmul float %336, %85 %368 = fmul float %336, %85 %369 = fadd float %368, %364 %369 = fadd float %368, %364 %370 = fmul float %338, %85 %370 = fmul float %338, %85 %371 = fadd float %370, %365 %371 = fadd float %370, %365 %372 = fmul float %321, %86 %372 = fmul float %321, %86 %373 = fadd float %372, %367 %373 = fadd float %372, %367 %374 = fmul float %322, %86 %374 = fmul float %322, %86 %375 = fadd float %374, %369 %375 = fadd float %374, %369 %376 = fmul float %323, %86 %376 = fmul float %323, %86 %377 = fadd float %376, %371 %377 = fadd float %376, %371 br label %ENDIF br label %ENDIF ELSE: ; preds = %main_body ELSE: ; preds = %main_body %378 = fmul float %199, %212 %378 = fmul float %199, %212 %379 = fmul float %204, %212 %379 = fmul float %204, %212 %380 = fmul float %203, %212 %380 = fmul float %203, %212 %381 = fmul float %380, %208 %381 = fmul float %380, %208 %382 = fmul float %378, %210 %382 = fmul float %378, %210 %383 = fmul float %379, %213 %383 = fmul float %379, %213 %384 = fmul float %379, %210 %384 = fmul float %379, %210 %385 = fsub float %384, %381 %385 = fsub float %384, %381 %386 = fmul float %380, %213 %386 = fmul float %380, %213 %387 = fsub float %386, %382 %387 = fsub float %386, %382 %388 = fmul float %378, %208 %388 = fmul float %378, %208 %389 = fsub float %388, %383 %389 = fsub float %388, %383 %390 = fmul float %213, %80 %390 = fmul float %213, %80 %391 = fmul float %208, %80 %391 = fmul float %208, %80 %392 = fmul float %210, %80 %392 = fmul float %210, %80 %393 = fmul float %385, %81 %393 = fmul float %385, %81 %394 = fadd float %393, %390 %394 = fadd float %393, %390 %395 = fmul float %387, %81 %395 = fmul float %387, %81 %396 = fadd float %395, %391 %396 = fadd float %395, %391 %397 = fmul float %389, %81 %397 = fmul float %389, %81 %398 = fadd float %397, %392 %398 = fadd float %397, %392 %399 = fmul float %199, %82 %399 = fmul float %199, %82 %400 = fadd float %399, %394 %400 = fadd float %399, %394 %401 = fmul float %204, %82 %401 = fmul float %204, %82 %402 = fadd float %401, %396 %402 = fadd float %401, %396 %403 = fmul float %203, %82 %403 = fmul float %203, %82 %404 = fadd float %403, %398 %404 = fadd float %403, %398 %405 = fmul float %213, %84 %405 = fmul float %213, %84 %406 = fmul float %208, %84 %406 = fmul float %208, %84 %407 = fmul float %210, %84 %407 = fmul float %210, %84 %408 = fmul float %385, %85 %408 = fmul float %385, %85 %409 = fadd float %408, %405 %409 = fadd float %408, %405 %410 = fmul float %387, %85 %410 = fmul float %387, %85 %411 = fadd float %410, %406 %411 = fadd float %410, %406 %412 = fmul float %389, %85 %412 = fmul float %389, %85 %413 = fadd float %412, %407 %413 = fadd float %412, %407 %414 = fmul float %199, %86 %414 = fmul float %199, %86 %415 = fadd float %414, %409 %415 = fadd float %414, %409 %416 = fmul float %204, %86 %416 = fmul float %204, %86 %417 = fadd float %416, %411 %417 = fadd float %416, %411 %418 = fmul float %203, %86 %418 = fmul float %203, %86 %419 = fadd float %418, %413 %419 = fadd float %418, %413 %420 = fmul float %281, %400 %420 = fmul float %281, %400 %421 = fmul float %284, %400 %421 = fmul float %284, %400 %422 = fmul float %287, %400 %422 = fmul float %287, %400 %423 = fmul float %282, %402 %423 = fmul float %282, %402 %424 = fadd float %423, %420 %424 = fadd float %423, %420 %425 = fmul float %285, %402 %425 = fmul float %285, %402 %426 = fadd float %425, %421 %426 = fadd float %425, %421 %427 = fmul float %288, %402 %427 = fmul float %288, %402 %428 = fadd float %427, %422 %428 = fadd float %427, %422 %429 = fmul float %283, %404 %429 = fmul float %283, %404 %430 = fadd float %429, %424 %430 = fadd float %429, %424 %431 = fmul float %286, %404 %431 = fmul float %286, %404 %432 = fadd float %431, %426 %432 = fadd float %431, %426 %433 = fmul float %289, %404 %433 = fmul float %289, %404 %434 = fadd float %433, %428 %434 = fadd float %433, %428 %435 = fmul float %281, %415 %435 = fmul float %281, %415 %436 = fmul float %284, %415 %436 = fmul float %284, %415 %437 = fmul float %287, %415 %437 = fmul float %287, %415 %438 = fmul float %282, %417 %438 = fmul float %282, %417 %439 = fadd float %438, %435 %439 = fadd float %438, %435 %440 = fmul float %285, %417 %440 = fmul float %285, %417 %441 = fadd float %440, %436 %441 = fadd float %440, %436 %442 = fmul float %288, %417 %442 = fmul float %288, %417 %443 = fadd float %442, %437 %443 = fadd float %442, %437 %444 = fmul float %283, %419 %444 = fmul float %283, %419 %445 = fadd float %444, %439 %445 = fadd float %444, %439 %446 = fmul float %286, %419 %446 = fmul float %286, %419 %447 = fadd float %446, %441 %447 = fadd float %446, %441 %448 = fmul float %289, %419 %448 = fmul float %289, %419 %449 = fadd float %448, %443 %449 = fadd float %448, %443 %450 = fmul float %281, %199 %450 = fmul float %281, %199 %451 = fmul float %284, %199 %451 = fmul float %284, %199 %452 = fmul float %287, %199 %452 = fmul float %287, %199 %453 = fmul float %282, %204 %453 = fmul float %282, %204 %454 = fadd float %453, %450 %454 = fadd float %453, %450 %455 = fmul float %285, %204 %455 = fmul float %285, %204 %456 = fadd float %455, %451 %456 = fadd float %455, %451 %457 = fmul float %288, %204 %457 = fmul float %288, %204 %458 = fadd float %457, %452 %458 = fadd float %457, %452 %459 = fmul float %283, %203 %459 = fmul float %283, %203 %460 = fadd float %459, %454 %460 = fadd float %459, %454 %461 = fmul float %286, %203 %461 = fmul float %286, %203 %462 = fadd float %461, %456 %462 = fadd float %461, %456 %463 = fmul float %289, %203 %463 = fmul float %289, %203 %464 = fadd float %463, %458 %464 = fadd float %463, %458 br label %ENDIF br label %ENDIF ENDIF: ; preds = %ELSE, %IF ENDIF: ; preds = %ELSE, %IF %temp80.0 = phi float [ %358, %IF ], [ %430, %ELSE ] %temp80.0 = phi float [ %358, %IF ], [ %430, %ELSE ] %temp81.0 = phi float [ %360, %IF ], [ %432, %ELSE ] %temp81.0 = phi float [ %360, %IF ], [ %432, %ELSE ] %temp82.0 = phi float [ %362, %IF ], [ %434, %ELSE ] %temp82.0 = phi float [ %362, %IF ], [ %434, %ELSE ] %temp84.0 = phi float [ %373, %IF ], [ %445, %ELSE ] %temp84.0 = phi float [ %373, %IF ], [ %445, %ELSE ] %temp85.0 = phi float [ %375, %IF ], [ %447, %ELSE ] %temp85.0 = phi float [ %375, %IF ], [ %447, %ELSE ] %temp86.0 = phi float [ %377, %IF ], [ %449, %ELSE ] %temp86.0 = phi float [ %377, %IF ], [ %449, %ELSE ] %temp88.0 = phi float [ %321, %IF ], [ %460, %ELSE ] %temp88.0 = phi float [ %321, %IF ], [ %460, %ELSE ] %temp89.0 = phi float [ %322, %IF ], [ %462, %ELSE ] %temp89.0 = phi float [ %322, %IF ], [ %462, %ELSE ] %temp90.0 = phi float [ %323, %IF ], [ %464, %ELSE ] %temp90.0 = phi float [ %323, %IF ], [ %464, %ELSE ] %465 = fmul float %temp80.0, %temp80.0 %465 = fmul float %temp80.0, %temp80.0 %466 = fmul float %temp81.0, %temp81.0 %466 = fmul float %temp81.0, %temp81.0 %467 = fadd float %466, %465 %467 = fadd float %466, %465 %468 = fmul float %temp82.0, %temp82.0 %468 = fmul float %temp82.0, %temp82.0 %469 = fadd float %467, %468 %469 = fadd float %467, %468 %470 = call float @llvm.AMDGPU.rsq.clamped.f32(float %469) %470 = call float @llvm.AMDGPU.rsq.clamped.f32(float %469) %471 = fmul float %temp80.0, %470 %471 = fmul float %temp80.0, %470 %472 = fmul float %temp81.0, %470 %472 = fmul float %temp81.0, %470 %473 = fmul float %temp82.0, %470 %473 = fmul float %temp82.0, %470 %474 = fmul float %temp84.0, %temp84.0 %474 = fmul float %temp84.0, %temp84.0 %475 = fmul float %temp85.0, %temp85.0 %475 = fmul float %temp85.0, %temp85.0 %476 = fadd float %475, %474 %476 = fadd float %475, %474 %477 = fmul float %temp86.0, %temp86.0 %477 = fmul float %temp86.0, %temp86.0 %478 = fadd float %476, %477 %478 = fadd float %476, %477 %479 = call float @llvm.AMDGPU.rsq.clamped.f32(float %478) %479 = call float @llvm.AMDGPU.rsq.clamped.f32(float %478) %480 = fmul float %temp84.0, %479 %480 = fmul float %temp84.0, %479 %481 = fmul float %temp85.0, %479 %481 = fmul float %temp85.0, %479 %482 = fmul float %temp86.0, %479 %482 = fmul float %temp86.0, %479 %483 = fmul float %temp88.0, %temp88.0 %483 = fmul float %temp88.0, %temp88.0 %484 = fmul float %temp89.0, %temp89.0 %484 = fmul float %temp89.0, %temp89.0 %485 = fadd float %484, %483 %485 = fadd float %484, %483 %486 = fmul float %temp90.0, %temp90.0 %486 = fmul float %temp90.0, %temp90.0 %487 = fadd float %485, %486 %487 = fadd float %485, %486 %488 = call float @llvm.AMDGPU.rsq.clamped.f32(float %487) %488 = call float @llvm.AMDGPU.rsq.clamped.f32(float %487) %489 = fmul float %temp88.0, %488 %489 = fmul float %temp88.0, %488 %490 = fmul float %temp89.0, %488 %490 = fmul float %temp89.0, %488 %491 = fmul float %temp90.0, %488 %491 = fmul float %temp90.0, %488 %492 = fmul float %311, %311 %492 = fmul float %311, %311 %493 = fmul float %312, %312 %493 = fmul float %312, %312 %494 = fmul float %313, %313 %494 = fmul float %313, %313 %495 = fmul float %311, %313 %495 = fmul float %311, %313 %496 = fmul float %313, %312 %496 = fmul float %313, %312 %497 = fmul float %312, %311 %497 = fmul float %312, %311 %498 = fmul float %56, %311 %498 = fmul float %56, %311 %499 = fadd float %498, %53 %499 = fadd float %498, %53 %500 = fmul float %57, %311 %500 = fmul float %57, %311 %501 = fadd float %500, %54 %501 = fadd float %500, %54 %502 = fmul float %58, %311 %502 = fmul float %58, %311 %503 = fadd float %502, %55 %503 = fadd float %502, %55 %504 = fmul float %59, %312 %504 = fmul float %59, %312 %505 = fadd float %504, %499 %505 = fadd float %504, %499 %506 = fmul float %60, %312 %506 = fmul float %60, %312 %507 = fadd float %506, %501 %507 = fadd float %506, %501 %508 = fmul float %61, %312 %508 = fmul float %61, %312 %509 = fadd float %508, %503 %509 = fadd float %508, %503 %510 = fmul float %62, %313 %510 = fmul float %62, %313 %511 = fadd float %510, %505 %511 = fadd float %510, %505 %512 = fmul float %63, %313 %512 = fmul float %63, %313 %513 = fadd float %512, %507 %513 = fadd float %512, %507 %514 = fmul float %64, %313 %514 = fmul float %64, %313 %515 = fadd float %514, %509 %515 = fadd float %514, %509 %516 = fmul float %65, %495 %516 = fmul float %65, %495 Shader Disassembly: Shader Disassembly: v_writelane_b32 v105, s2, 0 ; 04D30002 v_writelane_b32 v105, s2, 0 ; 04D30002 v_writelane_b32 v105, s3, 1 ; 04D30203 v_writelane_b32 v105, s3, 1 ; 04D30203 s_load_dwordx4 s[24:27], s[2:3], 0x0 ; C08C0300 s_load_dwordx4 s[24:27], s[2:3], 0x0 ; C08C0300 v_add_i32_e32 v39, s10, v0 ; 4A4E000A v_add_i32_e32 v39, s10, v0 ; 4A4E000A s_movk_i32 s2, 0x290 ; B0020290 s_movk_i32 s2, 0x290 ; B0020290 s_movk_i32 s3, 0x2a0 ; B00302A0 s_movk_i32 s3, 0x2a0 ; B00302A0 s_movk_i32 s32, 0x2b0 ; B02002B0 s_movk_i32 s32, 0x2b0 ; B02002B0 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C0820900 s_load_dwordx4 s[20:23], s[8:9], 0x4 ; C08A0904 s_load_dwordx4 s[20:23], s[8:9], 0x4 ; C08A0904 s_load_dwordx4 s[28:31], s[8:9], 0x8 ; C08E0908 s_load_dwordx4 s[28:31], s[8:9], 0x8 ; C08E0908 s_load_dwordx4 s[36:39], s[8:9], 0xc ; C092090C s_load_dwordx4 s[36:39], s[8:9], 0xc ; C092090C s_load_dwordx4 s[40:43], s[8:9], 0x10 ; C0940910 s_load_dwordx4 s[40:43], s[8:9], 0x10 ; C0940910 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F s_mov_b32 s13, 0 ; BE8D0380 s_mov_b32 s13, 0 ; BE8D0380 s_mov_b32 s19, 0 ; BE930380 s_mov_b32 s19, 0 ; BE930380 s_mov_b32 s15, 0 ; BE8F0380 s_mov_b32 s15, 0 ; BE8F0380 s_mov_b32 s11, 0 ; BE8B0380 s_mov_b32 s11, 0 ; BE8B0380 s_mov_b32 s16, 0 ; BE900380 s_mov_b32 s16, 0 ; BE900380 buffer_load_format_xyzw v[12:15], v39, s[4:7], 0 idxen ; E00C2000 80010C27 buffer_load_format_xyzw v[12:15], v39, s[4:7], 0 idxen ; E00C2000 80010C27 buffer_load_format_xyzw v[47:50], v39, s[20:23], 0 idxen ; E00C2000 80052F27 buffer_load_format_xyzw v[47:50], v39, s[20:23], 0 idxen ; E00C2000 80052F27 buffer_load_format_xyzw v[4:7], v39, s[28:31], 0 idxen ; E00C2000 80070427 buffer_load_format_xyzw v[4:7], v39, s[28:31], 0 idxen ; E00C2000 80070427 s_mov_b32 s17, 0 ; BE910380 s_mov_b32 s17, 0 ; BE910380 s_mov_b32 s12, 0 ; BE8C0380 s_mov_b32 s12, 0 ; BE8C0380 s_mov_b32 s18, 0 ; BE920380 s_mov_b32 s18, 0 ; BE920380 s_mov_b32 s14, 0 ; BE8E0380 s_mov_b32 s14, 0 ; BE8E0380 s_mov_b32 s31, 0 ; BE9F0380 s_mov_b32 s31, 0 ; BE9F0380 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s21, 0 ; BE950380 s_mov_b32 s21, 0 ; BE950380 s_mov_b32 s96, 0 ; BEE00380 s_mov_b32 s96, 0 ; BEE00380 s_mov_b32 s20, 0 ; BE940380 s_mov_b32 s20, 0 ; BE940380 s_mov_b32 s6, 0 ; BE860380 s_mov_b32 s6, 0 ; BE860380 s_mov_b32 s4, 0 ; BE840380 s_mov_b32 s4, 0 ; BE840380 s_mov_b32 s33, 0 ; BEA10380 s_mov_b32 s33, 0 ; BEA10380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e64 v8, s13, s13 ; D2100008 00001A0D v_mul_f32_e64 v8, s13, s13 ; D2100008 00001A0D v_mad_f32 v8, s19, s19, v8 ; D2820008 04202613 v_mad_f32 v8, s19, s19, v8 ; D2820008 04202613 v_mad_f32 v8, s15, s15, v8 ; D2820008 04201E0F v_mad_f32 v8, s15, s15, v8 ; D2820008 04201E0F v_rcp_f32_e32 v8, v8 ; 7E105508 v_rcp_f32_e32 v8, v8 ; 7E105508 v_mul_f32_e64 v9, s11, s11 ; D2100009 0000160B v_mul_f32_e64 v9, s11, s11 ; D2100009 0000160B v_mad_f32 v9, s16, s16, v9 ; D2820009 04242010 v_mad_f32 v9, s16, s16, v9 ; D2820009 04242010 s_waitcnt vmcnt(0) ; BF8C0770 s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v9, s17, s17, v9 ; D2820009 04242211 v_mad_f32 v9, s17, s17, v9 ; D2820009 04242211 v_rcp_f32_e32 v9, v9 ; 7E125509 v_rcp_f32_e32 v9, v9 ; 7E125509 s_mov_b32 s30, 0 ; BE9E0380 s_mov_b32 s30, 0 ; BE9E0380 s_mov_b32 s23, 0 ; BE970380 s_mov_b32 s23, 0 ; BE970380 s_mov_b32 s28, 0 ; BE9C0380 s_mov_b32 s28, 0 ; BE9C0380 s_mov_b32 s29, 0 ; BE9D0380 s_mov_b32 s29, 0 ; BE9D0380 s_mov_b32 s0, 0 ; BE800380 s_mov_b32 s0, 0 ; BE800380 s_mov_b32 s5, 0 ; BE850380 s_mov_b32 s5, 0 ; BE850380 s_mov_b32 s1, 0 ; BE810380 s_mov_b32 s1, 0 ; BE810380 v_mul_f32_e64 v10, s12, s12 ; D210000A 0000180C v_mul_f32_e64 v10, s12, s12 ; D210000A 0000180C v_mad_f32 v10, s18, s18, v10 ; D282000A 04282412 v_mad_f32 v10, s18, s18, v10 ; D282000A 04282412 v_mad_f32 v10, s14, s14, v10 ; D282000A 04281C0E v_mad_f32 v10, s14, s14, v10 ; D282000A 04281C0E v_rcp_f32_e32 v10, v10 ; 7E14550A v_rcp_f32_e32 v10, v10 ; 7E14550A v_mov_b32_e32 v43, s4 ; 7E560204 v_mov_b32_e32 v43, s4 ; 7E560204 s_mov_b32 s4, 0 ; BE840380 s_mov_b32 s4, 0 ; BE840380 v_mov_b32_e32 v44, s6 ; 7E580206 v_mov_b32_e32 v44, s6 ; 7E580206 v_mov_b32_e32 v45, s6 ; 7E5A0206 v_mov_b32_e32 v45, s6 ; 7E5A0206 s_mov_b32 s6, 0 ; BE860380 s_mov_b32 s6, 0 ; BE860380 v_mul_f32_e32 v74, s13, v8 ; 1094100D v_mul_f32_e32 v74, s13, v8 ; 1094100D v_mul_f32_e32 v54, s19, v8 ; 106C1013 v_mul_f32_e32 v54, s19, v8 ; 106C1013 v_mul_f32_e32 v46, s15, v8 ; 105C100F v_mul_f32_e32 v46, s15, v8 ; 105C100F v_mul_f32_e32 v75, s11, v9 ; 1096120B v_mul_f32_e32 v75, s11, v9 ; 1096120B v_mul_f32_e32 v55, s16, v9 ; 106E1210 v_mul_f32_e32 v55, s16, v9 ; 106E1210 v_mul_f32_e32 v52, s17, v9 ; 10681211 v_mul_f32_e32 v52, s17, v9 ; 10681211 v_mul_f32_e32 v76, s12, v10 ; 1098140C v_mul_f32_e32 v76, s12, v10 ; 1098140C v_mul_f32_e32 v73, s18, v10 ; 10921412 v_mul_f32_e32 v73, s18, v10 ; 10921412 v_mul_f32_e32 v53, s14, v10 ; 106A140E v_mul_f32_e32 v53, s14, v10 ; 106A140E buffer_load_format_xyzw v[8:11], v39, s[36:39], 0 idxen ; E00C2000 80090827 buffer_load_format_xyzw v[8:11], v39, s[36:39], 0 idxen ; E00C2000 80090827 s_mov_b32 s7, 0 ; BE870380 s_mov_b32 s7, 0 ; BE870380 buffer_load_format_xyzw v[35:38], v39, s[40:43], 0 idxen ; E00C2000 800A2327 buffer_load_format_xyzw v[35:38], v39, s[40:43], 0 idxen ; E00C2000 800A2327 s_load_dwordx4 s[36:39], s[8:9], 0x14 ; C0920914 s_load_dwordx4 s[36:39], s[8:9], 0x14 ; C0920914 s_load_dwordx4 s[40:43], s[8:9], 0x18 ; C0940918 s_load_dwordx4 s[40:43], s[8:9], 0x18 ; C0940918 s_load_dwordx4 s[44:47], s[8:9], 0x1c ; C096091C s_load_dwordx4 s[44:47], s[8:9], 0x1c ; C096091C s_load_dwordx4 s[48:51], s[8:9], 0x24 ; C0980924 s_load_dwordx4 s[48:51], s[8:9], 0x24 ; C0980924 s_load_dwordx4 s[52:55], s[8:9], 0x28 ; C09A0928 s_load_dwordx4 s[52:55], s[8:9], 0x28 ; C09A0928 s_load_dwordx4 s[56:59], s[8:9], 0x2c ; C09C092C s_load_dwordx4 s[56:59], s[8:9], 0x2c ; C09C092C s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 buffer_load_format_xyzw v[28:31], v39, s[36:39], 0 idxen ; E00C2000 80091C27 buffer_load_format_xyzw v[28:31], v39, s[36:39], 0 idxen ; E00C2000 80091C27 buffer_load_format_xyzw v[24:27], v39, s[40:43], 0 idxen ; E00C2000 800A1827 buffer_load_format_xyzw v[24:27], v39, s[40:43], 0 idxen ; E00C2000 800A1827 buffer_load_format_xyzw v[16:19], v39, s[44:47], 0 idxen ; E00C2000 800B1027 buffer_load_format_xyzw v[16:19], v39, s[44:47], 0 idxen ; E00C2000 800B1027 buffer_load_format_xyzw v[20:23], v39, s[48:51], 0 idxen ; E00C2000 800C1427 buffer_load_format_xyzw v[20:23], v39, s[48:51], 0 idxen ; E00C2000 800C1427 buffer_load_format_xyzw v[56:59], v39, s[52:55], 0 idxen ; E00C2000 800D3827 buffer_load_format_xyzw v[56:59], v39, s[52:55], 0 idxen ; E00C2000 800D3827 buffer_load_format_xyzw v[39:42], v39, s[56:59], 0 idxen ; E00C2000 800E2727 buffer_load_format_xyzw v[39:42], v39, s[56:59], 0 idxen ; E00C2000 800E2727 v_mad_f32 v45, s33, v47, v45 ; D282002D 04B65E21 v_mad_f32 v45, s33, v47, v45 ; D282002D 04B65E21 v_mad_f32 v43, s33, v48, v43 ; D282002B 04AE6021 v_mad_f32 v43, s33, v48, v43 ; D282002B 04AE6021 v_mad_f32 v44, s33, v49, v44 ; D282002C 04B26221 v_mad_f32 v44, s33, v49, v44 ; D282002C 04B26221 v_add_f32_e32 v43, 0x3a83126f, v43 ; 065656FF 3A83126F v_add_f32_e32 v43, 0x3a83126f, v43 ; 065656FF 3A83126F s_waitcnt vmcnt(1) ; BF8C0771 s_waitcnt vmcnt(1) ; BF8C0771 v_mul_f32_e32 v47, 0x437f028f, v56 ; 105E70FF 437F028F v_mul_f32_e32 v47, 0x437f028f, v56 ; 105E70FF 437F028F v_cvt_i32_f32_e32 v47, v47 ; 7E5E112F v_cvt_i32_f32_e32 v47, v47 ; 7E5E112F v_mul_f32_e32 v48, 0x437f028f, v57 ; 106072FF 437F028F v_mul_f32_e32 v48, 0x437f028f, v57 ; 106072FF 437F028F v_cvt_i32_f32_e32 v48, v48 ; 7E601130 v_cvt_i32_f32_e32 v48, v48 ; 7E601130 v_mul_f32_e32 v49, 0x437f028f, v58 ; 106274FF 437F028F v_mul_f32_e32 v49, 0x437f028f, v58 ; 106274FF 437F028F v_mul_f32_e32 v50, 0x437f028f, v59 ; 106476FF 437F028F v_mul_f32_e32 v50, 0x437f028f, v59 ; 106476FF 437F028F v_cvt_i32_f32_e32 v49, v49 ; 7E621131 v_cvt_i32_f32_e32 v49, v49 ; 7E621131 v_cvt_i32_f32_e32 v50, v50 ; 7E641132 v_cvt_i32_f32_e32 v50, v50 ; 7E641132 v_mul_lo_i32 v47, 3, v47 ; D2D6002F 00025E83 v_mul_lo_i32 v47, 3, v47 ; D2D6002F 00025E83 v_mul_lo_i32 v48, 3, v48 ; D2D60030 00026083 v_mul_lo_i32 v48, 3, v48 ; D2D60030 00026083 v_mul_lo_i32 v49, 3, v49 ; D2D60031 00026283 v_mul_lo_i32 v49, 3, v49 ; D2D60031 00026283 v_mul_lo_i32 v50, 3, v50 ; D2D60032 00026483 v_mul_lo_i32 v50, 3, v50 ; D2D60032 00026483 v_lshlrev_b32_e32 v47, 4, v47 ; 345E5E84 v_lshlrev_b32_e32 v47, 4, v47 ; 345E5E84 v_lshlrev_b32_e32 v48, 4, v48 ; 34606084 v_lshlrev_b32_e32 v48, 4, v48 ; 34606084 v_lshlrev_b32_e32 v51, 4, v49 ; 34666284 v_lshlrev_b32_e32 v51, 4, v49 ; 34666284 v_lshlrev_b32_e32 v56, 4, v50 ; 34706484 v_lshlrev_b32_e32 v56, 4, v50 ; 34706484 v_add_i32_e32 v49, s2, v47 ; 4A625E02 v_add_i32_e32 v49, s2, v47 ; 4A625E02 buffer_load_dword v63, v49, s[24:27], 0 offen ; E0301000 80063F31 buffer_load_dword v63, v49, s[24:27], 0 offen ; E0301000 80063F31 v_or_b32_e32 v50, 4, v49 ; 38646284 v_or_b32_e32 v50, 4, v49 ; 38646284 buffer_load_dword v64, v50, s[24:27], 0 offen ; E0301000 80064032 buffer_load_dword v64, v50, s[24:27], 0 offen ; E0301000 80064032 v_add_i32_e32 v50, s2, v48 ; 4A646002 v_add_i32_e32 v50, s2, v48 ; 4A646002 v_add_i32_e32 v57, s3, v47 ; 4A725E03 v_add_i32_e32 v57, s3, v47 ; 4A725E03 v_add_i32_e32 v58, s32, v47 ; 4A745E20 v_add_i32_e32 v58, s32, v47 ; 4A745E20 v_or_b32_e32 v47, 8, v49 ; 385E6288 v_or_b32_e32 v47, 8, v49 ; 385E6288 buffer_load_dword v65, v47, s[24:27], 0 offen ; E0301000 8006412F buffer_load_dword v65, v47, s[24:27], 0 offen ; E0301000 8006412F v_or_b32_e32 v47, 12, v49 ; 385E628C v_or_b32_e32 v47, 12, v49 ; 385E628C buffer_load_dword v47, v47, s[24:27], 0 offen ; E0301000 80062F2F buffer_load_dword v47, v47, s[24:27], 0 offen ; E0301000 80062F2F buffer_load_dword v66, v50, s[24:27], 0 offen ; E0301000 80064232 buffer_load_dword v66, v50, s[24:27], 0 offen ; E0301000 80064232 v_or_b32_e32 v49, 4, v50 ; 38626484 v_or_b32_e32 v49, 4, v50 ; 38626484 buffer_load_dword v67, v49, s[24:27], 0 offen ; E0301000 80064331 buffer_load_dword v67, v49, s[24:27], 0 offen ; E0301000 80064331 v_add_i32_e32 v59, s2, v51 ; 4A766602 v_add_i32_e32 v59, s2, v51 ; 4A766602 buffer_load_dword v68, v57, s[24:27], 0 offen ; E0301000 80064439 buffer_load_dword v68, v57, s[24:27], 0 offen ; E0301000 80064439 v_or_b32_e32 v49, 4, v57 ; 38627284 v_or_b32_e32 v49, 4, v57 ; 38627284 buffer_load_dword v69, v49, s[24:27], 0 offen ; E0301000 80064531 buffer_load_dword v69, v49, s[24:27], 0 offen ; E0301000 80064531 v_add_i32_e32 v60, s3, v48 ; 4A786003 v_add_i32_e32 v60, s3, v48 ; 4A786003 v_add_i32_e32 v61, s32, v48 ; 4A7A6020 v_add_i32_e32 v61, s32, v48 ; 4A7A6020 v_or_b32_e32 v48, 8, v50 ; 38606488 v_or_b32_e32 v48, 8, v50 ; 38606488 buffer_load_dword v70, v48, s[24:27], 0 offen ; E0301000 80064630 buffer_load_dword v70, v48, s[24:27], 0 offen ; E0301000 80064630 v_or_b32_e32 v48, 12, v50 ; 3860648C v_or_b32_e32 v48, 12, v50 ; 3860648C buffer_load_dword v48, v48, s[24:27], 0 offen ; E0301000 80063030 buffer_load_dword v48, v48, s[24:27], 0 offen ; E0301000 80063030 buffer_load_dword v71, v59, s[24:27], 0 offen ; E0301000 8006473B buffer_load_dword v71, v59, s[24:27], 0 offen ; E0301000 8006473B v_or_b32_e32 v49, 4, v59 ; 38627684 v_or_b32_e32 v49, 4, v59 ; 38627684 buffer_load_dword v72, v49, s[24:27], 0 offen ; E0301000 80064831 buffer_load_dword v72, v49, s[24:27], 0 offen ; E0301000 80064831 v_add_i32_e32 v62, s2, v56 ; 4A7C7002 v_add_i32_e32 v62, s2, v56 ; 4A7C7002 v_or_b32_e32 v49, 8, v57 ; 38627288 v_or_b32_e32 v49, 8, v57 ; 38627288 buffer_load_dword v77, v49, s[24:27], 0 offen ; E0301000 80064D31 buffer_load_dword v77, v49, s[24:27], 0 offen ; E0301000 80064D31 v_or_b32_e32 v49, 12, v57 ; 3862728C v_or_b32_e32 v49, 12, v57 ; 3862728C buffer_load_dword v49, v49, s[24:27], 0 offen ; E0301000 80063131 buffer_load_dword v49, v49, s[24:27], 0 offen ; E0301000 80063131 buffer_load_dword v78, v60, s[24:27], 0 offen ; E0301000 80064E3C buffer_load_dword v78, v60, s[24:27], 0 offen ; E0301000 80064E3C v_or_b32_e32 v50, 4, v60 ; 38647884 v_or_b32_e32 v50, 4, v60 ; 38647884 buffer_load_dword v79, v50, s[24:27], 0 offen ; E0301000 80064F32 buffer_load_dword v79, v50, s[24:27], 0 offen ; E0301000 80064F32 v_add_i32_e32 v57, s3, v51 ; 4A726603 v_add_i32_e32 v57, s3, v51 ; 4A726603 v_add_i32_e32 v80, s32, v51 ; 4AA06620 v_add_i32_e32 v80, s32, v51 ; 4AA06620 buffer_load_dword v81, v58, s[24:27], 0 offen ; E0301000 8006513A buffer_load_dword v81, v58, s[24:27], 0 offen ; E0301000 8006513A v_or_b32_e32 v50, 4, v58 ; 38647484 v_or_b32_e32 v50, 4, v58 ; 38647484 buffer_load_dword v82, v50, s[24:27], 0 offen ; E0301000 80065232 buffer_load_dword v82, v50, s[24:27], 0 offen ; E0301000 80065232 v_or_b32_e32 v50, 8, v59 ; 38647688 v_or_b32_e32 v50, 8, v59 ; 38647688 buffer_load_dword v83, v50, s[24:27], 0 offen ; E0301000 80065332 buffer_load_dword v83, v50, s[24:27], 0 offen ; E0301000 80065332 v_or_b32_e32 v50, 12, v59 ; 3864768C v_or_b32_e32 v50, 12, v59 ; 3864768C buffer_load_dword v51, v50, s[24:27], 0 offen ; E0301000 80063332 buffer_load_dword v51, v50, s[24:27], 0 offen ; E0301000 80063332 buffer_load_dword v84, v62, s[24:27], 0 offen ; E0301000 8006543E buffer_load_dword v84, v62, s[24:27], 0 offen ; E0301000 8006543E v_or_b32_e32 v50, 4, v62 ; 38647C84 v_or_b32_e32 v50, 4, v62 ; 38647C84 buffer_load_dword v85, v50, s[24:27], 0 offen ; E0301000 80065532 buffer_load_dword v85, v50, s[24:27], 0 offen ; E0301000 80065532 v_or_b32_e32 v50, 8, v60 ; 38647888 v_or_b32_e32 v50, 8, v60 ; 38647888 buffer_load_dword v86, v50, s[24:27], 0 offen ; E0301000 80065632 buffer_load_dword v86, v50, s[24:27], 0 offen ; E0301000 80065632 v_or_b32_e32 v50, 12, v60 ; 3864788C v_or_b32_e32 v50, 12, v60 ; 3864788C buffer_load_dword v50, v50, s[24:27], 0 offen ; E0301000 80063232 buffer_load_dword v50, v50, s[24:27], 0 offen ; E0301000 80063232 buffer_load_dword v87, v57, s[24:27], 0 offen ; E0301000 80065739 buffer_load_dword v87, v57, s[24:27], 0 offen ; E0301000 80065739 v_or_b32_e32 v59, 4, v57 ; 38767284 v_or_b32_e32 v59, 4, v57 ; 38767284 buffer_load_dword v88, v59, s[24:27], 0 offen ; E0301000 8006583B buffer_load_dword v88, v59, s[24:27], 0 offen ; E0301000 8006583B v_add_i32_e32 v59, s3, v56 ; 4A767003 v_add_i32_e32 v59, s3, v56 ; 4A767003 v_add_i32_e32 v56, s32, v56 ; 4A707020 v_add_i32_e32 v56, s32, v56 ; 4A707020 v_or_b32_e32 v60, 8, v58 ; 38787488 v_or_b32_e32 v60, 8, v58 ; 38787488 buffer_load_dword v89, v60, s[24:27], 0 offen ; E0301000 8006593C buffer_load_dword v89, v60, s[24:27], 0 offen ; E0301000 8006593C v_or_b32_e32 v58, 12, v58 ; 3874748C v_or_b32_e32 v58, 12, v58 ; 3874748C buffer_load_dword v90, v61, s[24:27], 0 offen ; E0301000 80065A3D buffer_load_dword v90, v61, s[24:27], 0 offen ; E0301000 80065A3D v_or_b32_e32 v60, 4, v61 ; 38787A84 v_or_b32_e32 v60, 4, v61 ; 38787A84 buffer_load_dword v91, v60, s[24:27], 0 offen ; E0301000 80065B3C buffer_load_dword v91, v60, s[24:27], 0 offen ; E0301000 80065B3C v_or_b32_e32 v60, 8, v62 ; 38787C88 v_or_b32_e32 v60, 8, v62 ; 38787C88 buffer_load_dword v92, v60, s[24:27], 0 offen ; E0301000 80065C3C buffer_load_dword v92, v60, s[24:27], 0 offen ; E0301000 80065C3C v_or_b32_e32 v60, 12, v62 ; 38787C8C v_or_b32_e32 v60, 12, v62 ; 38787C8C v_or_b32_e32 v62, 8, v57 ; 387C7288 v_or_b32_e32 v62, 8, v57 ; 387C7288 buffer_load_dword v93, v62, s[24:27], 0 offen ; E0301000 80065D3E buffer_load_dword v93, v62, s[24:27], 0 offen ; E0301000 80065D3E v_or_b32_e32 v57, 12, v57 ; 3872728C v_or_b32_e32 v57, 12, v57 ; 3872728C buffer_load_dword v94, v59, s[24:27], 0 offen ; E0301000 80065E3B buffer_load_dword v94, v59, s[24:27], 0 offen ; E0301000 80065E3B v_or_b32_e32 v62, 4, v59 ; 387C7684 v_or_b32_e32 v62, 4, v59 ; 387C7684 buffer_load_dword v95, v62, s[24:27], 0 offen ; E0301000 80065F3E buffer_load_dword v95, v62, s[24:27], 0 offen ; E0301000 80065F3E v_or_b32_e32 v62, 8, v61 ; 387C7A88 v_or_b32_e32 v62, 8, v61 ; 387C7A88 buffer_load_dword v96, v62, s[24:27], 0 offen ; E0301000 8006603E buffer_load_dword v96, v62, s[24:27], 0 offen ; E0301000 8006603E v_or_b32_e32 v97, 12, v61 ; 38C27A8C v_or_b32_e32 v97, 12, v61 ; 38C27A8C buffer_load_dword v98, v80, s[24:27], 0 offen ; E0301000 80066250 buffer_load_dword v98, v80, s[24:27], 0 offen ; E0301000 80066250 v_or_b32_e32 v61, 4, v80 ; 387AA084 v_or_b32_e32 v61, 4, v80 ; 387AA084 buffer_load_dword v99, v61, s[24:27], 0 offen ; E0301000 8006633D buffer_load_dword v99, v61, s[24:27], 0 offen ; E0301000 8006633D v_or_b32_e32 v61, 8, v80 ; 387AA088 v_or_b32_e32 v61, 8, v80 ; 387AA088 buffer_load_dword v100, v61, s[24:27], 0 offen ; E0301000 8006643D buffer_load_dword v100, v61, s[24:27], 0 offen ; E0301000 8006643D buffer_load_dword v101, v56, s[24:27], 0 offen ; E0301000 80066538 buffer_load_dword v101, v56, s[24:27], 0 offen ; E0301000 80066538 v_or_b32_e32 v61, 8, v59 ; 387A7688 v_or_b32_e32 v61, 8, v59 ; 387A7688 buffer_load_dword v102, v61, s[24:27], 0 offen ; E0301000 8006663D buffer_load_dword v102, v61, s[24:27], 0 offen ; E0301000 8006663D v_or_b32_e32 v61, 4, v56 ; 387A7084 v_or_b32_e32 v61, 4, v56 ; 387A7084 buffer_load_dword v103, v61, s[24:27], 0 offen ; E0301000 8006673D buffer_load_dword v103, v61, s[24:27], 0 offen ; E0301000 8006673D v_or_b32_e32 v61, 8, v56 ; 387A7088 v_or_b32_e32 v61, 8, v56 ; 387A7088 buffer_load_dword v104, v61, s[24:27], 0 offen ; E0301000 8006683D buffer_load_dword v104, v61, s[24:27], 0 offen ; E0301000 8006683D v_or_b32_e32 v59, 12, v59 ; 3876768C v_or_b32_e32 v59, 12, v59 ; 3876768C v_or_b32_e32 v80, 12, v80 ; 38A0A08C v_or_b32_e32 v80, 12, v80 ; 38A0A08C v_or_b32_e32 v56, 12, v56 ; 3870708C v_or_b32_e32 v56, 12, v56 ; 3870708C buffer_load_dword v62, v60, s[24:27], 0 offen ; E0301000 80063E3C buffer_load_dword v62, v60, s[24:27], 0 offen ; E0301000 80063E3C buffer_load_dword v61, v57, s[24:27], 0 offen ; E0301000 80063D39 buffer_load_dword v61, v57, s[24:27], 0 offen ; E0301000 80063D39 buffer_load_dword v60, v59, s[24:27], 0 offen ; E0301000 80063C3B buffer_load_dword v60, v59, s[24:27], 0 offen ; E0301000 80063C3B buffer_load_dword v59, v58, s[24:27], 0 offen ; E0301000 80063B3A buffer_load_dword v59, v58, s[24:27], 0 offen ; E0301000 80063B3A buffer_load_dword v58, v97, s[24:27], 0 offen ; E0301000 80063A61 buffer_load_dword v58, v97, s[24:27], 0 offen ; E0301000 80063A61 buffer_load_dword v57, v80, s[24:27], 0 offen ; E0301000 80063950 buffer_load_dword v57, v80, s[24:27], 0 offen ; E0301000 80063950 buffer_load_dword v56, v56, s[24:27], 0 offen ; E0301000 80063838 buffer_load_dword v56, v56, s[24:27], 0 offen ; E0301000 80063838 s_waitcnt ; BF8C077F s_waitcnt ; BF8C077F v_mul_f32_e32 v63, v39, v63 ; 107E7F27 v_mul_f32_e32 v63, v39, v63 ; 107E7F27 v_mad_f32 v63, v66, v40, v63 ; D282003F 04FE5142 v_mad_f32 v63, v66, v40, v63 ; D282003F 04FE5142 v_mul_f32_e32 v66, v39, v68 ; 10848927 v_mul_f32_e32 v66, v39, v68 ; 10848927 v_mad_f32 v66, v78, v40, v66 ; D2820042 050A514E v_mad_f32 v66, v78, v40, v66 ; D2820042 050A514E v_mul_f32_e32 v68, v39, v81 ; 1088A327 v_mul_f32_e32 v68, v39, v81 ; 1088A327 v_mad_f32 v68, v90, v40, v68 ; D2820044 0512515A v_mad_f32 v68, v90, v40, v68 ; D2820044 0512515A v_mul_f32_e32 v64, v39, v64 ; 10808127 v_mul_f32_e32 v64, v39, v64 ; 10808127 v_mad_f32 v64, v67, v40, v64 ; D2820040 05025143 v_mad_f32 v64, v67, v40, v64 ; D2820040 05025143 v_mul_f32_e32 v65, v39, v65 ; 10828327 v_mul_f32_e32 v65, v39, v65 ; 10828327 v_mad_f32 v65, v70, v40, v65 ; D2820041 05065146 v_mad_f32 v65, v70, v40, v65 ; D2820041 05065146 v_mad_f32 v63, v71, v41, v63 ; D282003F 04FE5347 v_mad_f32 v63, v71, v41, v63 ; D282003F 04FE5347 v_mul_f32_e32 v67, v39, v69 ; 10868B27 v_mul_f32_e32 v67, v39, v69 ; 10868B27 v_mad_f32 v70, v79, v40, v67 ; D2820046 050E514F v_mad_f32 v70, v79, v40, v67 ; D2820046 050E514F v_mul_f32_e32 v67, v39, v77 ; 10869B27 v_mul_f32_e32 v67, v39, v77 ; 10869B27 v_mad_f32 v71, v86, v40, v67 ; D2820047 050E5156 v_mad_f32 v71, v86, v40, v67 ; D2820047 050E5156 v_mad_f32 v66, v87, v41, v66 ; D2820042 050A5357 v_mad_f32 v66, v87, v41, v66 ; D2820042 050A5357 v_mul_f32_e32 v67, v39, v82 ; 1086A527 v_mul_f32_e32 v67, v39, v82 ; 1086A527 v_mad_f32 v77, v91, v40, v67 ; D282004D 050E515B v_mad_f32 v77, v91, v40, v67 ; D282004D 050E515B v_mul_f32_e32 v67, v39, v89 ; 1086B327 v_mul_f32_e32 v67, v39, v89 ; 1086B327 s_waitcnt vmcnt(14) ; BF8C077E s_waitcnt vmcnt(14) ; BF8C077E v_mad_f32 v78, v96, v40, v67 ; D282004E 050E5160 v_mad_f32 v78, v96, v40, v67 ; D282004E 050E5160 s_waitcnt vmcnt(13) ; BF8C077D s_waitcnt vmcnt(13) ; BF8C077D v_mad_f32 v68, v98, v41, v68 ; D2820044 05125362 v_mad_f32 v68, v98, v41, v68 ; D2820044 05125362 v_mad_f32 v64, v72, v41, v64 ; D2820040 05025348 v_mad_f32 v64, v72, v41, v64 ; D2820040 05025348 v_mad_f32 v65, v83, v41, v65 ; D2820041 05065353 v_mad_f32 v65, v83, v41, v65 ; D2820041 05065353 v_add_f32_e32 v67, v39, v40 ; 06865127 v_add_f32_e32 v67, v39, v40 ; 06865127 v_add_f32_e32 v67, v41, v67 ; 06868729 v_add_f32_e32 v67, v41, v67 ; 06868729 v_sub_f32_e32 v69, 1.0, v67 ; 088A86F2 v_sub_f32_e32 v69, 1.0, v67 ; 088A86F2 v_mad_f32 v67, v84, v69, v63 ; D2820043 04FE8B54 v_mad_f32 v67, v84, v69, v63 ; D2820043 04FE8B54 v_mad_f32 v70, v88, v41, v70 ; D2820046 051A5358 v_mad_f32 v70, v88, v41, v70 ; D2820046 051A5358 v_mad_f32 v79, v93, v41, v71 ; D282004F 051E535D v_mad_f32 v79, v93, v41, v71 ; D282004F 051E535D v_mad_f32 v66, v94, v69, v66 ; D2820042 050A8B5E v_mad_f32 v66, v94, v69, v66 ; D2820042 050A8B5E s_waitcnt vmcnt(12) ; BF8C077C s_waitcnt vmcnt(12) ; BF8C077C v_mad_f32 v77, v99, v41, v77 ; D282004D 05365363 v_mad_f32 v77, v99, v41, v77 ; D282004D 05365363 s_waitcnt vmcnt(11) ; BF8C077B s_waitcnt vmcnt(11) ; BF8C077B v_mad_f32 v78, v100, v41, v78 ; D282004E 053A5364 v_mad_f32 v78, v100, v41, v78 ; D282004E 053A5364 s_waitcnt vmcnt(10) ; BF8C077A s_waitcnt vmcnt(10) ; BF8C077A v_mad_f32 v63, v101, v69, v68 ; D282003F 05128B65 v_mad_f32 v63, v101, v69, v68 ; D282003F 05128B65 v_mad_f32 v72, v85, v69, v64 ; D2820048 05028B55 v_mad_f32 v72, v85, v69, v64 ; D2820048 05028B55 v_mad_f32 v71, v92, v69, v65 ; D2820047 05068B5C v_mad_f32 v71, v92, v69, v65 ; D2820047 05068B5C v_mad_f32 v70, v95, v69, v70 ; D2820046 051A8B5F v_mad_f32 v70, v95, v69, v70 ; D2820046 051A8B5F s_waitcnt vmcnt(9) ; BF8C0779 s_waitcnt vmcnt(9) ; BF8C0779 v_mad_f32 v68, v102, v69, v79 ; D2820044 053E8B66 v_mad_f32 v68, v102, v69, v79 ; D2820044 053E8B66 s_waitcnt vmcnt(8) ; BF8C0778 s_waitcnt vmcnt(8) ; BF8C0778 v_mad_f32 v65, v103, v69, v77 ; D2820041 05368B67 v_mad_f32 v65, v103, v69, v77 ; D2820041 05368B67 s_waitcnt vmcnt(7) ; BF8C0777 s_waitcnt vmcnt(7) ; BF8C0777 v_mad_f32 v64, v104, v69, v78 ; D2820040 053A8B68 v_mad_f32 v64, v104, v69, v78 ; D2820040 053A8B68 v_mul_f32_e32 v77, v67, v45 ; 109A5B43 v_mul_f32_e32 v77, v67, v45 ; 109A5B43 v_mul_f32_e32 v78, v66, v45 ; 109C5B42 v_mul_f32_e32 v78, v66, v45 ; 109C5B42 v_mul_f32_e32 v45, v63, v45 ; 105A5B3F v_mul_f32_e32 v45, v63, v45 ; 105A5B3F v_mad_f32 v77, v43, v72, v77 ; D282004D 0536912B v_mad_f32 v77, v43, v72, v77 ; D282004D 0536912B v_mad_f32 v78, v43, v70, v78 ; D282004E 053A8D2B v_mad_f32 v78, v43, v70, v78 ; D282004E 053A8D2B v_mad_f32 v43, v43, v65, v45 ; D282002B 04B6832B v_mad_f32 v43, v43, v65, v45 ; D282002B 04B6832B v_mad_f32 v83, v44, v71, v77 ; D2820053 05368F2C v_mad_f32 v83, v44, v71, v77 ; D2820053 05368F2C v_mad_f32 v82, v44, v68, v78 ; D2820052 053A892C v_mad_f32 v82, v44, v68, v78 ; D2820052 053A892C v_mad_f32 v81, v44, v64, v43 ; D2820051 04AE812C v_mad_f32 v81, v44, v64, v43 ; D2820051 04AE812C v_mul_f32_e32 v43, v74, v83 ; 1056A74A v_mul_f32_e32 v43, v74, v83 ; 1056A74A v_mad_f32 v43, v82, v54, v43 ; D282002B 04AE6D52 v_mad_f32 v43, v82, v54, v43 ; D282002B 04AE6D52 v_mul_f32_e32 v44, v75, v83 ; 1058A74B v_mul_f32_e32 v44, v75, v83 ; 1058A74B v_mad_f32 v44, v82, v55, v44 ; D282002C 04B26F52 v_mad_f32 v44, v82, v55, v44 ; D282002C 04B26F52 v_mul_f32_e32 v45, v76, v83 ; 105AA74C v_mul_f32_e32 v45, v76, v83 ; 105AA74C v_mad_f32 v45, v82, v73, v45 ; D282002D 04B69352 v_mad_f32 v45, v82, v73, v45 ; D282002D 04B69352 v_mad_f32 v79, v81, v46, v43 ; D282004F 04AE5D51 v_mad_f32 v79, v81, v46, v43 ; D282004F 04AE5D51 v_mad_f32 v78, v81, v52, v44 ; D282004E 04B26951 v_mad_f32 v78, v81, v52, v44 ; D282004E 04B26951 v_mad_f32 v77, v81, v53, v45 ; D282004D 04B66B51 v_mad_f32 v77, v81, v53, v45 ; D282004D 04B66B51 v_mul_f32_e32 v43, v79, v79 ; 10569F4F v_mul_f32_e32 v43, v79, v79 ; 10569F4F v_mad_f32 v43, v78, v78, v43 ; D282002B 04AE9D4E v_mad_f32 v43, v78, v78, v43 ; D282002B 04AE9D4E v_mad_f32 v43, v77, v77, v43 ; D282002B 04AE9B4D v_mad_f32 v43, v77, v77, v43 ; D282002B 04AE9B4D v_rsq_clamp_f32_e32 v80, v43 ; 7EA0592B v_rsq_clamp_f32_e32 v80, v43 ; 7EA0592B v_cmp_nlt_f32_e64 s[2:3], 0, s20 ; D01C0002 00002880 v_cmp_nlt_f32_e64 s[2:3], 0, s20 ; D01C0002 00002880 s_waitcnt vmcnt(0) ; BF8C0770 s_waitcnt vmcnt(0) ; BF8C0770 s_and_saveexec_b64 s[82:83], s[2:3] ; BED22402 s_and_saveexec_b64 s[82:83], s[2:3] ; BED22402 s_xor_b64 s[82:83], exec, s[82:83] ; 89D2527E s_xor_b64 s[82:83], exec, s[82:83] ; 89D2527E s_cbranch_execz BB0_1 ; BF880000 s_cbranch_execz BB0_1 ; BF880000 s_mov_b32 s2, 0 ; BE820380 s_mov_b32 s2, 0 ; BE820380 s_mov_b32 s3, 0 ; BE830380 s_mov_b32 s3, 0 ; BE830380 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 v_add_i32_e32 v0, s10, v0 ; 4A00000A v_add_i32_e32 v0, s10, v0 ; 4A00000A v_mul_f32_e32 v1, v74, v83 ; 1002A74A v_mul_f32_e32 v1, v74, v83 ; 1002A74A v_mad_f32 v1, v54, v82, v1 ; D2820001 0406A536 v_mad_f32 v1, v54, v82, v1 ; D2820001 0406A536 v_mad_f32 v2, v46, v81, v1 ; D2820002 0406A32E v_mad_f32 v2, v46, v81, v1 ; D2820002 0406A32E v_mul_f32_e32 v1, v75, v83 ; 1002A74B v_mul_f32_e32 v1, v75, v83 ; 1002A74B v_mad_f32 v1, v55, v82, v1 ; D2820001 0406A537 v_mad_f32 v1, v55, v82, v1 ; D2820001 0406A537 v_mad_f32 v3, v52, v81, v1 ; D2820003 0406A334 v_mad_f32 v3, v52, v81, v1 ; D2820003 0406A334 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v32, s2 ; 7E400202 v_mov_b32_e32 v32, s2 ; 7E400202 v_mov_b32_e32 v33, s2 ; 7E420202 v_mov_b32_e32 v33, s2 ; 7E420202 v_mul_f32_e32 v1, v76, v83 ; 1002A74C v_mul_f32_e32 v1, v76, v83 ; 1002A74C v_mad_f32 v1, v73, v82, v1 ; D2820001 0406A549 v_mad_f32 v1, v73, v82, v1 ; D2820001 0406A549 v_mad_f32 v1, v53, v81, v1 ; D2820001 0406A335 v_mad_f32 v1, v53, v81, v1 ; D2820001 0406A335 v_mov_b32_e32 v34, s3 ; 7E440203 v_mov_b32_e32 v34, s3 ; 7E440203 v_mov_b32_e32 v43, s3 ; 7E560203 v_mov_b32_e32 v43, s3 ; 7E560203 s_load_dwordx4 s[36:39], s[8:9], 0x20 ; C0920920 s_load_dwordx4 s[36:39], s[8:9], 0x20 ; C0920920 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[84:87], v0, s[36:39], 0 idxen ; E00C2000 80095400 buffer_load_format_xyzw v[84:87], v0, s[36:39], 0 idxen ; E00C2000 80095400 s_waitcnt vmcnt(0) ; BF8C0770 s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v0, s32, v84, v33 ; D2820000 0486A820 v_mad_f32 v0, s32, v84, v33 ; D2820000 0486A820 v_mad_f32 v33, s32, v85, v43 ; D2820021 04AEAA20 v_mad_f32 v33, s32, v85, v43 ; D2820021 04AEAA20 v_mad_f32 v34, s32, v86, v34 ; D2820022 048AAC20 v_mad_f32 v34, s32, v86, v34 ; D2820022 048AAC20 v_mad_f32 v32, s32, v87, v32 ; D2820020 0482AE20 v_mad_f32 v32, s32, v87, v32 ; D2820020 0482AE20 v_add_f32_e32 v0, 0x3a83126f, v0 ; 060000FF 3A83126F v_add_f32_e32 v0, 0x3a83126f, v0 ; 060000FF 3A83126F v_mul_f32_e32 v43, v67, v0 ; 10560143 v_mul_f32_e32 v43, v67, v0 ; 10560143 v_mul_f32_e32 v44, v66, v0 ; 10580142 v_mul_f32_e32 v44, v66, v0 ; 10580142 v_mul_f32_e32 v0, v63, v0 ; 1000013F v_mul_f32_e32 v0, v63, v0 ; 1000013F v_mad_f32 v43, v33, v72, v43 ; D282002B 04AE9121 v_mad_f32 v43, v33, v72, v43 ; D282002B 04AE9121 v_mad_f32 v44, v33, v70, v44 ; D282002C 04B28D21 v_mad_f32 v44, v33, v70, v44 ; D282002C 04B28D21 v_mad_f32 v0, v33, v65, v0 ; D2820000 04028321 v_mad_f32 v0, v33, v65, v0 ; D2820000 04028321 v_mad_f32 v33, v34, v71, v43 ; D2820021 04AE8F22 v_mad_f32 v33, v34, v71, v43 ; D2820021 04AE8F22 v_mad_f32 v43, v34, v68, v44 ; D282002B 04B28922 v_mad_f32 v43, v34, v68, v44 ; D282002B 04B28922 v_mad_f32 v0, v34, v64, v0 ; D2820000 04028122 v_mad_f32 v0, v34, v64, v0 ; D2820000 04028122 v_mul_f32_e32 v34, v32, v83 ; 1044A720 v_mul_f32_e32 v34, v32, v83 ; 1044A720 v_mul_f32_e32 v44, v32, v82 ; 1058A520 v_mul_f32_e32 v44, v32, v82 ; 1058A520 v_mul_f32_e32 v32, v32, v81 ; 1040A320 v_mul_f32_e32 v32, v32, v81 ; 1040A320 v_mul_f32_e32 v45, v0, v34 ; 105A4500 v_mul_f32_e32 v45, v0, v34 ; 105A4500 v_mad_f32 v45, v32, v33, -v45 ; D282002D 84B64320 v_mad_f32 v45, v32, v33, -v45 ; D282002D 84B64320 v_mul_f32_e32 v32, v43, v32 ; 1040412B v_mul_f32_e32 v32, v43, v32 ; 1040412B v_mad_f32 v32, v44, v0, -v32 ; D2820020 8482012C v_mad_f32 v32, v44, v0, -v32 ; D2820020 8482012C v_mul_f32_e32 v44, v33, v44 ; 10585921 v_mul_f32_e32 v44, v33, v44 ; 10585921 v_mad_f32 v34, v34, v43, -v44 ; D2820022 84B25722 v_mad_f32 v34, v34, v43, -v44 ; D2820022 84B25722 v_mul_f32_e32 v44, s0, v33 ; 10584200 v_mul_f32_e32 v44, s0, v33 ; 10584200 v_mul_f32_e32 v33, s4, v33 ; 10424204 v_mul_f32_e32 v33, s4, v33 ; 10424204 v_mad_f32 v44, v32, s5, v44 ; D282002C 04B00B20 v_mad_f32 v44, v32, s5, v44 ; D282002C 04B00B20 v_mad_f32 v32, v32, s6, v33 ; D2820020 04840D20 v_mad_f32 v32, v32, s6, v33 ; D2820020 04840D20 v_mul_f32_e32 v33, s0, v43 ; 10425600 v_mul_f32_e32 v33, s0, v43 ; 10425600 v_mul_f32_e32 v43, s4, v43 ; 10565604 v_mul_f32_e32 v43, s4, v43 ; 10565604 v_mad_f32 v33, v45, s5, v33 ; D2820021 04840B2D v_mad_f32 v33, v45, s5, v33 ; D2820021 04840B2D v_mad_f32 v43, v45, s6, v43 ; D282002B 04AC0D2D v_mad_f32 v43, v45, s6, v43 ; D282002B 04AC0D2D v_mul_f32_e32 v45, s0, v0 ; 105A0000 v_mul_f32_e32 v45, s0, v0 ; 105A0000 v_mul_f32_e32 v0, s4, v0 ; 10000004 v_mul_f32_e32 v0, s4, v0 ; 10000004 v_mad_f32 v45, v34, s5, v45 ; D282002D 04B40B22 v_mad_f32 v45, v34, s5, v45 ; D282002D 04B40B22 v_mad_f32 v0, v34, s6, v0 ; D2820000 04000D22 v_mad_f32 v0, v34, s6, v0 ; D2820000 04000D22 v_mad_f32 v34, v83, s1, v44 ; D2820022 04B00353 v_mad_f32 v34, v83, s1, v44 ; D2820022 04B00353 v_mad_f32 v32, v83, s7, v32 ; D2820020 04800F53 v_mad_f32 v32, v83, s7, v32 ; D2820020 04800F53 v_mad_f32 v33, v82, s1, v33 ; D2820021 04840352 v_mad_f32 v33, v82, s1, v33 ; D2820021 04840352 v_mad_f32 v43, v82, s7, v43 ; D282002B 04AC0F52 v_mad_f32 v43, v82, s7, v43 ; D282002B 04AC0F52 v_mad_f32 v82, v81, s1, v45 ; D2820052 04B40351 v_mad_f32 v82, v81, s1, v45 ; D2820052 04B40351 v_mad_f32 v0, v81, s7, v0 ; D2820000 04000F51 v_mad_f32 v0, v81, s7, v0 ; D2820000 04000F51 v_mul_f32_e32 v44, v34, v74 ; 10589522 v_mul_f32_e32 v44, v34, v74 ; 10589522 v_mul_f32_e32 v45, v34, v75 ; 105A9722 v_mul_f32_e32 v45, v34, v75 ; 105A9722 v_mul_f32_e32 v34, v34, v76 ; 10449922 v_mul_f32_e32 v34, v34, v76 ; 10449922 v_mul_f32_e32 v74, v32, v74 ; 10949520 v_mul_f32_e32 v74, v32, v74 ; 10949520 v_mul_f32_e32 v75, v32, v75 ; 10969720 v_mul_f32_e32 v75, v32, v75 ; 10969720 v_mul_f32_e32 v32, v32, v76 ; 10409920 v_mul_f32_e32 v32, v32, v76 ; 10409920 v_mad_f32 v44, v54, v33, v44 ; D282002C 04B24336 v_mad_f32 v44, v54, v33, v44 ; D282002C 04B24336 v_mad_f32 v76, v55, v33, v45 ; D282004C 04B64337 v_mad_f32 v76, v55, v33, v45 ; D282004C 04B64337 v_mad_f32 v33, v73, v33, v34 ; D2820021 048A4349 v_mad_f32 v33, v73, v33, v34 ; D2820021 048A4349 v_mad_f32 v34, v54, v43, v74 ; D2820022 052A5736 v_mad_f32 v34, v54, v43, v74 ; D2820022 052A5736 v_mad_f32 v54, v55, v43, v75 ; D2820036 052E5737 v_mad_f32 v54, v55, v43, v75 ; D2820036 052E5737 v_mad_f32 v55, v73, v43, v32 ; D2820037 04825749 v_mad_f32 v55, v73, v43, v32 ; D2820037 04825749 v_mad_f32 v45, v46, v82, v44 ; D282002D 04B2A52E v_mad_f32 v45, v46, v82, v44 ; D282002D 04B2A52E v_mad_f32 v44, v52, v82, v76 ; D282002C 0532A534 v_mad_f32 v44, v52, v82, v76 ; D282002C 0532A534 v_mad_f32 v43, v53, v82, v33 ; D282002B 0486A535 v_mad_f32 v43, v53, v82, v33 ; D282002B 0486A535 v_mad_f32 v34, v46, v0, v34 ; D2820022 048A012E v_mad_f32 v34, v46, v0, v34 ; D2820022 048A012E v_mad_f32 v32, v52, v0, v54 ; D2820020 04DA0134 v_mad_f32 v32, v52, v0, v54 ; D2820020 04DA0134 v_mad_f32 v33, v53, v0, v55 ; D2820021 04DE0135 v_mad_f32 v33, v53, v0, v55 ; D2820021 04DE0135 s_or_saveexec_b64 s[82:83], s[82:83] ; BED22552 s_or_saveexec_b64 s[82:83], s[82:83] ; BED22552 v_mov_b32_e32 v0, s31 ; 7E00021F v_mov_b32_e32 v0, s31 ; 7E00021F s_buffer_load_dword s3, s[24:27], 0x0 ; C2019900 s_buffer_load_dword s3, s[24:27], 0x0 ; C2019900 v_mov_b32_e32 v46, s30 ; 7E5C021E v_mov_b32_e32 v46, s30 ; 7E5C021E s_buffer_load_dword s30, s[24:27], 0x1 ; C20F1901 s_buffer_load_dword s30, s[24:27], 0x1 ; C20F1901 v_mov_b32_e32 v75, s23 ; 7E960217 v_mov_b32_e32 v75, s23 ; 7E960217 v_mov_b32_e32 v76, s28 ; 7E98021C v_mov_b32_e32 v76, s28 ; 7E98021C v_mov_b32_e32 v81, s29 ; 7EA2021D v_mov_b32_e32 v81, s29 ; 7EA2021D v_mov_b32_e32 v74, s22 ; 7E940216 v_mov_b32_e32 v74, s22 ; 7E940216 v_mov_b32_e32 v73, s21 ; 7E920215 v_mov_b32_e32 v73, s21 ; 7E920215 s_buffer_load_dword s2, s[24:27], 0x2 ; C2011902 s_buffer_load_dword s2, s[24:27], 0x2 ; C2011902 s_buffer_load_dword s21, s[24:27], 0x3 ; C20A9903 s_buffer_load_dword s21, s[24:27], 0x3 ; C20A9903 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s21, 24 ; 04D33015 v_writelane_b32 v105, s21, 24 ; 04D33015 s_buffer_load_dword s28, s[24:27], 0x4 ; C20E1904 s_buffer_load_dword s28, s[24:27], 0x4 ; C20E1904 s_buffer_load_dword s29, s[24:27], 0x5 ; C20E9905 s_buffer_load_dword s29, s[24:27], 0x5 ; C20E9905 s_buffer_load_dword s21, s[24:27], 0x6 ; C20A9906 s_buffer_load_dword s21, s[24:27], 0x6 ; C20A9906 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s21, 25 ; 04D33215 v_writelane_b32 v105, s21, 25 ; 04D33215 s_buffer_load_dword s21, s[24:27], 0x7 ; C20A9907 s_buffer_load_dword s21, s[24:27], 0x7 ; C20A9907 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s21, 26 ; 04D33415 v_writelane_b32 v105, s21, 26 ; 04D33415 s_buffer_load_dword s21, s[24:27], 0x8 ; C20A9908 s_buffer_load_dword s21, s[24:27], 0x8 ; C20A9908 s_buffer_load_dword s31, s[24:27], 0x9 ; C20F9909 s_buffer_load_dword s31, s[24:27], 0x9 ; C20F9909 s_buffer_load_dword s22, s[24:27], 0xa ; C20B190A s_buffer_load_dword s22, s[24:27], 0xa ; C20B190A s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 28 ; 04D33816 v_writelane_b32 v105, s22, 28 ; 04D33816 s_buffer_load_dword s22, s[24:27], 0xb ; C20B190B s_buffer_load_dword s22, s[24:27], 0xb ; C20B190B s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 29 ; 04D33A16 v_writelane_b32 v105, s22, 29 ; 04D33A16 s_mov_b32 s22, 0 ; BE960380 | s_buffer_load_dword s22, s[24:27], 0xc ; C20B190C s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 30 ; 04D33C16 v_writelane_b32 v105, s22, 30 ; 04D33C16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 33 ; 04D34216 v_writelane_b32 v105, s22, 33 ; 04D34216 s_mov_b32 s58, 0 ; BEBA0380 s_mov_b32 s58, 0 ; BEBA0380 s_mov_b32 s59, 0 ; BEBB0380 s_mov_b32 s59, 0 ; BEBB0380 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 32 ; 04D34016 v_writelane_b32 v105, s22, 32 ; 04D34016 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 31 ; 04D33E16 v_writelane_b32 v105, s22, 31 ; 04D33E16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 27 ; 04D33616 v_writelane_b32 v105, s22, 27 ; 04D33616 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 16 ; 04D32016 v_writelane_b32 v105, s22, 16 ; 04D32016 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 20 ; 04D32816 v_writelane_b32 v105, s22, 20 ; 04D32816 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 17 ; 04D32216 v_writelane_b32 v105, s22, 17 ; 04D32216 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 18 ; 04D32416 v_writelane_b32 v105, s22, 18 ; 04D32416 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 19 ; 04D32616 v_writelane_b32 v105, s22, 19 ; 04D32616 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 21 ; 04D32A16 v_writelane_b32 v105, s22, 21 ; 04D32A16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 22 ; 04D32C16 v_writelane_b32 v105, s22, 22 ; 04D32C16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 23 ; 04D32E16 v_writelane_b32 v105, s22, 23 ; 04D32E16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 10 ; 04D31416 v_writelane_b32 v105, s22, 10 ; 04D31416 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s22, 14 ; 04D31C16 v_writelane_b32 v105, s22, 14 ; 04D31C16 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s22, 0 ; BE960380 s_mov_b32 s23, 0 ; BE970380 s_mov_b32 s23, 0 ; BE970380 s_mov_b32 s84, 0 ; BED40380 s_mov_b32 s84, 0 ; BED40380 s_mov_b32 s85, 0 ; BED50380 s_mov_b32 s85, 0 ; BED50380 s_mov_b32 s86, 0 ; BED60380 s_mov_b32 s86, 0 ; BED60380 s_mov_b32 s87, 0 ; BED70380 s_mov_b32 s87, 0 ; BED70380 s_mov_b32 s88, 0 ; BED80380 s_mov_b32 s88, 0 ; BED80380 s_mov_b32 s89, 0 ; BED90380 s_mov_b32 s89, 0 ; BED90380 s_mov_b32 s90, 0 ; BEDA0380 s_mov_b32 s90, 0 ; BEDA0380 s_mov_b32 s63, 0 ; BEBF0380 s_mov_b32 s63, 0 ; BEBF0380 s_mov_b32 s64, 0 ; BEC00380 s_mov_b32 s64, 0 ; BEC00380 s_mov_b32 s66, 0 ; BEC20380 s_mov_b32 s66, 0 ; BEC20380 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 2 ; 04D30420 v_writelane_b32 v105, s32, 2 ; 04D30420 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 3 ; 04D30620 v_writelane_b32 v105, s32, 3 ; 04D30620 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 4 ; 04D30820 v_writelane_b32 v105, s32, 4 ; 04D30820 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 5 ; 04D30A20 v_writelane_b32 v105, s32, 5 ; 04D30A20 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 7 ; 04D30E20 v_writelane_b32 v105, s32, 7 ; 04D30E20 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 11 ; 04D31620 v_writelane_b32 v105, s32, 11 ; 04D31620 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 6 ; 04D30C20 v_writelane_b32 v105, s32, 6 ; 04D30C20 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 8 ; 04D31020 v_writelane_b32 v105, s32, 8 ; 04D31020 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 12 ; 04D31820 v_writelane_b32 v105, s32, 12 ; 04D31820 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 9 ; 04D31220 v_writelane_b32 v105, s32, 9 ; 04D31220 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 13 ; 04D31A20 v_writelane_b32 v105, s32, 13 ; 04D31A20 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F v_writelane_b32 v105, s32, 15 ; 04D31E20 v_writelane_b32 v105, s32, 15 ; 04D31E20 s_mov_b32 s61, 0 ; BEBD0380 s_mov_b32 s61, 0 ; BEBD0380 s_mov_b32 s60, 0 ; BEBC0380 s_mov_b32 s60, 0 ; BEBC0380 s_mov_b32 s62, 0 ; BEBE0380 s_mov_b32 s62, 0 ; BEBE0380 s_mov_b32 s69, 0 ; BEC50380 s_mov_b32 s69, 0 ; BEC50380 s_mov_b32 s65, 0 ; BEC10380 s_mov_b32 s65, 0 ; BEC10380 s_mov_b32 s67, 0 ; BEC30380 s_mov_b32 s67, 0 ; BEC30380 s_mov_b32 s68, 0 ; BEC40380 s_mov_b32 s68, 0 ; BEC40380 s_mov_b32 s71, 0 ; BEC70380 s_mov_b32 s71, 0 ; BEC70380 s_mov_b32 s72, 0 ; BEC80380 s_mov_b32 s72, 0 ; BEC80380 s_mov_b32 s73, 0 ; BEC90380 s_mov_b32 s73, 0 ; BEC90380 s_mov_b32 s74, 0 ; BECA0380 s_mov_b32 s74, 0 ; BECA0380 s_mov_b32 s78, 0 ; BECE0380 s_mov_b32 s78, 0 ; BECE0380 s_mov_b32 s75, 0 ; BECB0380 s_mov_b32 s75, 0 ; BECB0380 s_mov_b32 s76, 0 ; BECC0380 s_mov_b32 s76, 0 ; BECC0380 s_mov_b32 s77, 0 ; BECD0380 s_mov_b32 s77, 0 ; BECD0380 s_mov_b32 s79, 0 ; BECF0380 s_mov_b32 s79, 0 ; BECF0380 s_mov_b32 s80, 0 ; BED00380 s_mov_b32 s80, 0 ; BED00380 s_mov_b32 s81, 0 ; BED10380 s_mov_b32 s81, 0 ; BED10380 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s32, 0 ; BEA00380 s_mov_b32 s33, 0 ; BEA10380 s_mov_b32 s33, 0 ; BEA10380 s_mov_b32 s70, 0 ; BEC60380 s_mov_b32 s70, 0 ; BEC60380 s_mov_b32 s91, 0 ; BEDB0380 s_mov_b32 s91, 0 ; BEDB0380 s_mov_b32 s92, 0 ; BEDC0380 s_mov_b32 s92, 0 ; BEDC0380 s_mov_b32 s94, 0 ; BEDE0380 s_mov_b32 s94, 0 ; BEDE0380 s_mov_b32 s93, 0 ; BEDD0380 s_mov_b32 s93, 0 ; BEDD0380 s_mov_b32 s98, 0 ; BEE20380 s_mov_b32 s98, 0 ; BEE20380 s_mov_b32 s95, 0 ; BEDF0380 s_mov_b32 s95, 0 ; BEDF0380 s_mov_b32 s34, 0 ; BEA20380 s_mov_b32 s34, 0 ; BEA20380 s_mov_b32 s35, 0 ; BEA30380 s_mov_b32 s35, 0 ; BEA30380 s_mov_b32 s37, 0 ; BEA50380 s_mov_b32 s37, 0 ; BEA50380 s_mov_b32 s36, 0 ; BEA40380 s_mov_b32 s36, 0 ; BEA40380 s_mov_b32 s38, 0 ; BEA60380 s_mov_b32 s38, 0 ; BEA60380 s_mov_b32 s39, 0 ; BEA70380 s_mov_b32 s39, 0 ; BEA70380 s_mov_b32 s40, 0 ; BEA80380 s_mov_b32 s40, 0 ; BEA80380 s_mov_b32 s24, 0 ; BE980380 s_mov_b32 s24, 0 ; BE980380 v_mov_b32_e32 v55, s96 ; 7E6E0260 v_mov_b32_e32 v55, s96 ; 7E6E0260 v_mul_f32_e32 v52, v80, v79 ; 10689F50 v_mul_f32_e32 v52, v80, v79 ; 10689F50 v_mul_f32_e32 v53, v80, v78 ; 106A9D50 v_mul_f32_e32 v53, v80, v78 ; 106A9D50 v_mul_f32_e32 v54, v80, v77 ; 106C9B50 v_mul_f32_e32 v54, v80, v77 ; 106C9B50 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F s_xor_b64 exec, exec, s[82:83] ; 89FE527E s_xor_b64 exec, exec, s[82:83] ; 89FE527E s_cbranch_execz BB0_4 ; BF880000 s_cbranch_execz BB0_4 ; BF880000 v_mul_f32_e32 v1, v52, v52 ; 10026934 v_mul_f32_e32 v1, v52, v52 ; 10026934 v_mad_f32 v1, v53, v53, v1 ; D2820001 04066B35 v_mad_f32 v1, v53, v53, v1 ; D2820001 04066B35 v_mad_f32 v1, v54, v54, v1 ; D2820001 04066D36 v_mad_f32 v1, v54, v54, v1 ; D2820001 04066D36 v_rsq_clamp_f32_e32 v1, v1 ; 7E025901 v_rsq_clamp_f32_e32 v1, v1 ; 7E025901 v_mul_f32_e32 v2, v1, v52 ; 10046901 v_mul_f32_e32 v2, v1, v52 ; 10046901 v_mul_f32_e32 v3, v1, v53 ; 10066B01 v_mul_f32_e32 v3, v1, v53 ; 10066B01 v_mul_f32_e32 v1, v1, v54 ; 10026D01 v_mul_f32_e32 v1, v1, v54 ; 10026D01 v_mul_f32_e32 v32, s36, v2 ; 10400424 v_mul_f32_e32 v32, s36, v2 ; 10400424 v_mul_f32_e32 v33, s36, v3 ; 10420624 v_mul_f32_e32 v33, s36, v3 ; 10420624 v_mul_f32_e32 v34, s36, v1 ; 10440224 v_mul_f32_e32 v34, s36, v1 ; 10440224 v_mad_f32 v43, 0.5, s36, 0.5 ; D282002B 03C048F0 v_mad_f32 v43, 0.5, s36, 0.5 ; D282002B 03C048F0 v_sub_f32_e32 v44, 1.0, v43 ; 085856F2 v_sub_f32_e32 v44, 1.0, v43 ; 085856F2 v_mul_f32_e32 v45, v43, v34 ; 105A452B v_mul_f32_e32 v45, v43, v34 ; 105A452B v_mov_b32_e32 v77, 0x80000000 ; 7E9A02FF 80000000 v_mov_b32_e32 v77, 0x80000000 ; 7E9A02FF 80000000 v_mul_f32_e32 v77, v32, v77 ; 109A9B20 v_mul_f32_e32 v77, v32, v77 ; 109A9B20 v_mad_f32 v77, v34, v44, v77 ; D282004D 05365922 v_mad_f32 v77, v34, v44, v77 ; D282004D 05365922 v_mul_f32_e32 v44, v44, v33 ; 1058432C v_mul_f32_e32 v44, v44, v33 ; 1058432C v_mad_f32 v45, 0, v33, -v45 ; D282002D 84B64280 v_mad_f32 v45, 0, v33, -v45 ; D282002D 84B64280 v_mad_f32 v43, v32, v43, -v44 ; D282002B 84B25720 v_mad_f32 v43, v32, v43, -v44 ; D282002B 84B25720 v_mul_f32_e32 v44, v33, v43 ; 10585721 v_mul_f32_e32 v44, v33, v43 ; 10585721 v_mad_f32 v44, v77, v34, -v44 ; D282002C 84B2454D v_mad_f32 v44, v77, v34, -v44 ; D282002C 84B2454D v_mul_f32_e32 v34, v34, v45 ; 10445B22 v_mul_f32_e32 v34, v34, v45 ; 10445B22 v_mad_f32 v34, v43, v32, -v34 ; D2820022 848A412B v_mad_f32 v34, v43, v32, -v34 ; D2820022 848A412B v_mul_f32_e32 v32, v32, v77 ; 10409B20 v_mul_f32_e32 v32, v32, v77 ; 10409B20 v_mad_f32 v32, v45, v33, -v32 ; D2820020 8482432D v_mad_f32 v32, v45, v33, -v32 ; D2820020 8482432D v_mul_f32_e32 v33, s0, v44 ; 10425800 v_mul_f32_e32 v33, s0, v44 ; 10425800 v_mad_f32 v33, v45, s5, v33 ; D2820021 04840B2D v_mad_f32 v33, v45, s5, v33 ; D2820021 04840B2D v_mul_f32_e32 v44, s4, v44 ; 10585804 v_mul_f32_e32 v44, s4, v44 ; 10585804 v_mad_f32 v78, v45, s6, v44 ; D282004E 04B00D2D v_mad_f32 v78, v45, s6, v44 ; D282004E 04B00D2D v_mul_f32_e32 v44, s0, v34 ; 10584400 v_mul_f32_e32 v44, s0, v34 ; 10584400 v_mad_f32 v44, v77, s5, v44 ; D282002C 04B00B4D v_mad_f32 v44, v77, s5, v44 ; D282002C 04B00B4D v_mul_f32_e32 v34, s4, v34 ; 10444404 v_mul_f32_e32 v34, s4, v34 ; 10444404 v_mad_f32 v77, v77, s6, v34 ; D282004D 04880D4D v_mad_f32 v77, v77, s6, v34 ; D282004D 04880D4D v_mul_f32_e32 v34, s0, v32 ; 10444000 v_mul_f32_e32 v34, s0, v32 ; 10444000 v_mad_f32 v34, v43, s5, v34 ; D2820022 04880B2B v_mad_f32 v34, v43, s5, v34 ; D2820022 04880B2B v_mul_f32_e32 v32, s4, v32 ; 10404004 v_mul_f32_e32 v32, s4, v32 ; 10404004 v_mad_f32 v79, v43, s6, v32 ; D282004F 04800D2B v_mad_f32 v79, v43, s6, v32 ; D282004F 04800D2B v_mad_f32 v45, v2, s1, v33 ; D282002D 04840302 v_mad_f32 v45, v2, s1, v33 ; D282002D 04840302 v_mad_f32 v44, v3, s1, v44 ; D282002C 04B00303 v_mad_f32 v44, v3, s1, v44 ; D282002C 04B00303 v_mad_f32 v43, v1, s1, v34 ; D282002B 04880301 v_mad_f32 v43, v1, s1, v34 ; D282002B 04880301 v_mad_f32 v34, v2, s7, v78 ; D2820022 05380F02 v_mad_f32 v34, v2, s7, v78 ; D2820022 05380F02 v_mad_f32 v32, v3, s7, v77 ; D2820020 05340F03 v_mad_f32 v32, v3, s7, v77 ; D2820020 05340F03 v_mad_f32 v33, v1, s7, v79 ; D2820021 053C0F01 v_mad_f32 v33, v1, s7, v79 ; D2820021 053C0F01 s_or_b64 exec, exec, s[82:83] ; 88FE527E s_or_b64 exec, exec, s[82:83] ; 88FE527E v_mad_f32 v75, v52, v75, s22 ; D282004B 005A9734 v_mad_f32 v75, v52, v75, s22 ; D282004B 005A9734 v_mad_f32 v76, v52, v76, s23 ; D282004C 005E9934 v_mad_f32 v76, v52, v76, s23 ; D282004C 005E9934 v_mad_f32 v77, v52, v81, s84 ; D282004D 0152A334 v_mad_f32 v77, v52, v81, s84 ; D282004D 0152A334 v_mad_f32 v75, s85, v53, v75 ; D282004B 052E6A55 v_mad_f32 v75, s85, v53, v75 ; D282004B 052E6A55 v_mad_f32 v76, s86, v53, v76 ; D282004C 05326A56 v_mad_f32 v76, s86, v53, v76 ; D282004C 05326A56 v_mad_f32 v77, s87, v53, v77 ; D282004D 05366A57 v_mad_f32 v77, s87, v53, v77 ; D282004D 05366A57 v_mad_f32 v75, s88, v54, v75 ; D282004B 052E6C58 v_mad_f32 v75, s88, v54, v75 ; D282004B 052E6C58 v_mad_f32 v76, s89, v54, v76 ; D282004C 05326C59 v_mad_f32 v76, s89, v54, v76 ; D282004C 05326C59 v_mad_f32 v77, s90, v54, v77 ; D282004D 05366C5A v_mad_f32 v77, s90, v54, v77 ; D282004D 05366C5A v_cmp_le_f32_e64 vcc, 0, s94 ; D006006A 0000BC80 v_cmp_le_f32_e64 vcc, 0, s94 ; D006006A 0000BC80 v_cmp_le_f32_e64 s[100:101], 0, s91 ; D0060064 0000B680 v_cmp_le_f32_e64 s[100:101], 0, s91 ; D0060064 0000B680 v_cmp_le_f32_e64 s[22:23], 0, s92 ; D0060016 0000B880 v_cmp_le_f32_e64 s[22:23], 0, s92 ; D0060016 0000B880 v_cmp_le_f32_e64 s[96:97], 0, s95 ; D0060060 0000BE80 v_cmp_le_f32_e64 s[96:97], 0, s95 ; D0060060 0000BE80 v_cmp_le_f32_e64 s[94:95], 0, s93 ; D006005E 0000BA80 v_cmp_le_f32_e64 s[94:95], 0, s93 ; D006005E 0000BA80 v_cmp_le_f32_e64 s[98:99], 0, s98 ; D0060062 0000C480 v_cmp_le_f32_e64 s[98:99], 0, s98 ; D0060062 0000C480 v_cmp_le_f32_e64 s[88:89], 0, s37 ; D0060058 00004A80 v_cmp_le_f32_e64 s[88:89], 0, s37 ; D0060058 00004A80 v_cmp_le_f32_e64 s[90:91], 0, s34 ; D006005A 00004480 v_cmp_le_f32_e64 s[90:91], 0, s34 ; D006005A 00004480 v_cmp_le_f32_e64 s[92:93], 0, s35 ; D006005C 00004680 v_cmp_le_f32_e64 s[92:93], 0, s35 ; D006005C 00004680 v_cmp_le_f32_e64 s[84:85], 0, s20 ; D0060054 00002880 v_cmp_le_f32_e64 s[84:85], 0, s20 ; D0060054 00002880 v_cmp_le_f32_e64 s[82:83], 0, s36 ; D0060052 00004880 v_cmp_le_f32_e64 s[82:83], 0, s36 ; D0060052 00004880 v_cmp_le_f32_e64 s[86:87], 0, s38 ; D0060056 00004C80 v_cmp_le_f32_e64 s[86:87], 0, s38 ; D0060056 00004C80 v_cmp_le_f32_e64 s[8:9], 0, s24 ; D0060008 00003080 v_cmp_le_f32_e64 s[8:9], 0, s24 ; D0060008 00003080 v_cmp_le_f32_e64 s[24:25], 0, s39 ; D0060018 00004E80 v_cmp_le_f32_e64 s[24:25], 0, s39 ; D0060018 00004E80 v_mad_f32 v74, s32, v35, v74 ; D282004A 052A4620 v_mad_f32 v74, s32, v35, v74 ; D282004A 052A4620 v_cmp_le_f32_e64 s[26:27], 0, s40 ; D006001A 00005080 v_cmp_le_f32_e64 s[26:27], 0, s40 ; D006001A 00005080 v_mad_f32 v35, s33, v36, v73 ; D2820023 05264821 v_mad_f32 v35, s33, v36, v73 ; D2820023 05264821 v_mul_f32_e32 v36, v39, v47 ; 10485F27 v_mul_f32_e32 v36, v39, v47 ; 10485F27 v_mad_f32 v36, v48, v40, v36 ; D2820024 04925130 v_mad_f32 v36, v48, v40, v36 ; D2820024 04925130 v_mad_f32 v36, v51, v41, v36 ; D2820024 04925333 v_mad_f32 v36, v51, v41, v36 ; D2820024 04925333 v_mad_f32 v36, v62, v69, v36 ; D2820024 04928B3E v_mad_f32 v36, v62, v69, v36 ; D2820024 04928B3E v_mul_f32_e32 v37, v39, v49 ; 104A6327 v_mul_f32_e32 v37, v39, v49 ; 104A6327 v_mad_f32 v37, v50, v40, v37 ; D2820025 04965132 v_mad_f32 v37, v50, v40, v37 ; D2820025 04965132 v_mad_f32 v37, v61, v41, v37 ; D2820025 0496533D v_mad_f32 v37, v61, v41, v37 ; D2820025 0496533D v_mad_f32 v37, v60, v69, v37 ; D2820025 04968B3C v_mad_f32 v37, v60, v69, v37 ; D2820025 04968B3C v_mul_f32_e32 v38, v39, v59 ; 104C7727 v_mul_f32_e32 v38, v39, v59 ; 104C7727 v_mad_f32 v38, v58, v40, v38 ; D2820026 049A513A v_mad_f32 v38, v58, v40, v38 ; D2820026 049A513A v_mad_f32 v38, v57, v41, v38 ; D2820026 049A5339 v_mad_f32 v38, v57, v41, v38 ; D2820026 049A5339 v_mad_f32 v38, v56, v69, v38 ; D2820026 049A8B38 v_mad_f32 v38, v56, v69, v38 ; D2820026 049A8B38 v_mul_f32_e32 v39, v72, v13 ; 104E1B48 v_mul_f32_e32 v39, v72, v13 ; 104E1B48 v_mad_f32 v39, v12, v67, v39 ; D2820027 049E870C v_mad_f32 v39, v12, v67, v39 ; D2820027 049E870C v_mad_f32 v39, v14, v71, v39 ; D2820027 049E8F0E v_mad_f32 v39, v14, v71, v39 ; D2820027 049E8F0E v_mad_f32 v36, v15, v36, v39 ; D2820024 049E490F v_mad_f32 v36, v15, v36, v39 ; D2820024 049E490F v_mul_f32_e32 v39, v70, v13 ; 104E1B46 v_mul_f32_e32 v39, v70, v13 ; 104E1B46 v_mad_f32 v39, v12, v66, v39 ; D2820027 049E850C v_mad_f32 v39, v12, v66, v39 ; D2820027 049E850C v_mad_f32 v39, v14, v68, v39 ; D2820027 049E890E v_mad_f32 v39, v14, v68, v39 ; D2820027 049E890E v_mad_f32 v37, v15, v37, v39 ; D2820025 049E4B0F v_mad_f32 v37, v15, v37, v39 ; D2820025 049E4B0F v_mul_f32_e32 v39, s30, v37 ; 104E4A1E v_mul_f32_e32 v39, s30, v37 ; 104E4A1E v_mad_f32 v39, v36, s3, v39 ; D2820027 049C0724 v_mad_f32 v39, v36, s3, v39 ; D2820027 049C0724 v_mul_f32_e32 v40, s29, v37 ; 10504A1D v_mul_f32_e32 v40, s29, v37 ; 10504A1D v_mad_f32 v40, v36, s28, v40 ; D2820028 04A03924 v_mad_f32 v40, v36, s28, v40 ; D2820028 04A03924 v_mul_f32_e32 v41, s31, v37 ; 10524A1F v_mul_f32_e32 v41, s31, v37 ; 10524A1F v_mad_f32 v41, v36, s21, v41 ; D2820029 04A42B24 v_mad_f32 v41, v36, s21, v41 ; D2820029 04A42B24 v_mul_f32_e32 v42, v65, v13 ; 10541B41 v_mul_f32_e32 v42, v65, v13 ; 10541B41 v_mad_f32 v42, v12, v63, v42 ; D282002A 04AA7F0C v_mad_f32 v42, v12, v63, v42 ; D282002A 04AA7F0C v_mad_f32 v42, v14, v64, v42 ; D282002A 04AA810E v_mad_f32 v42, v14, v64, v42 ; D282002A 04AA810E v_mad_f32 v38, v15, v38, v42 ; D2820026 04AA4D0F v_mad_f32 v38, v15, v38, v42 ; D2820026 04AA4D0F v_mad_f32 v39, v38, s2, v39 ; D2820027 049C0526 v_mad_f32 v39, v38, s2, v39 ; D2820027 049C0526 v_readlane_b32 s2, v105, 0 ; 02050169 v_readlane_b32 s2, v105, 0 ; 02050169 v_readlane_b32 s3, v105, 1 ; 02070369 v_readlane_b32 s3, v105, 1 ; 02070369 s_nop 2 ; BF800002 s_nop 2 ; BF800002 s_load_dwordx4 s[28:31], s[2:3], 0x40 ; C08E0340 s_load_dwordx4 s[28:31], s[2:3], 0x40 ; C08E0340 s_waitcnt lgkmcnt(0) ; BF8C007F s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s2, s[28:31], 0x0 ; C2011D00 s_buffer_load_dword s2, s[28:31], 0x0 ; C2011D00 s_buffer_load_dword s3, s[28:31], 0x1 ; C2019D01 s_buffer_load_dword s3, s[28:31], 0x1 ; C2019D01 s_buffer_load_dword s10, s[28:31], 0x2 ; C2051D02 s_buffer_load_dword s10, s[28:31], 0x2 ; C2051D02 s_buffer_load_dword s20, s[28:31], 0x3 ; C20A1D03 s_buffer_load_dword s20, s[28:31], 0x3 ; C20A1D03 s_buffer_load_dword s21, s[28:31], 0x4 ; C20A9D04 s_buffer_load_dword s21, s[28:31], 0x4 ; C20A9D04 s_buffer_load_dword s32, s[28:31], 0x5 ; C2101D05 s_buffer_load_dword s32, s[28:31], 0x5 ; C2101D05 s_buffer_load_dword s33, s[28:31], 0x6 ; C2109D06 s_buffer_load_dword s33, s[28:31], 0x6 ; C2109D06 s_buffer_load_dword s34, s[28:31], 0x7 ; C2111D07 s_buffer_load_dword s34, s[28:31], 0x7 ; C2111D07 s_buffer_load_dword s35, s[28:31], 0x8 ; C2119D08 s_buffer_load_dword s35, s[28:31], 0x8 ; C2119D08 s_buffer_load_dword s36, s[28:31], 0x9 ; C2121D09 s_buffer_load_dword s36, s[28:31], 0x9 ; C2121D09 s_buffer_load_dword s37, s[28:31], 0xa ; C2129D0A s_buffer_load_dword s37, s[28:31], 0xa ; C2129D0A s_buffer_load_dword s38, s[28:31], 0xb ; C2131D0B s_buffer_load_dword s38, s[28:31], 0xb ; C2131D0B s_buffer_load_dword s39, s[28:31], 0xc ; C2139D0C s_buffer_load_dword s39, s[28:31], 0xc ; C2139D0C s_mov_b32 s40, 0 ; BEA80380 s_mov_b32 s40, 0 ; BEA80380 s_mov_b32 s41, 0 ; BEA90380 s_mov_b32 s41, 0 ; BEA90380 s_mov_b32 s42, 0 ; BEAA0380 s_mov_b32 s42, 0 ; BEAA0380 s_mov_b32 s43, 0 ; BEAB0380 s_mov_b32 s43, 0 ; BEAB0380 s_mov_b32 s44, 0 ; BEAC0380 s_mov_b32 s44, 0 ; BEAC0380 s_mov_b32 s45, 0 ; BEAD0380 s_mov_b32 s45, 0 ; BEAD0380 s_mov_b32 s46, 0 ; BEAE0380 s_mov_b32 s46, 0 ; BEAE0380 s_mov_b32 s47, 0 ; BEAF0380 s_mov_b32 s47, 0 ; BEAF0380 s_mov_b32 s48, 0 ; BEB00380 s_mov_b32 s48, 0 ; BEB00380 s_mov_b32 s49, 0 ; BEB10380 s_mov_b32 s49, 0 ; BEB10380 s_mov_b32 s50, 0 ; BEB20380 s_mov_b32 s50, 0 ; BEB20380 s_mov_b32 s51, 0 ; BEB30380 s_mov_b32 s51, 0 ; BEB30380 s_mov_b32 s52, 0 ; BEB40380 s_mov_b32 s52, 0 ; BEB40380 s_mov_b32 s53, 0 ; BEB50380 s_mov_b32 s53, 0 ; BEB50380 s_mov_b32 s54, 0 ; BEB60380 s_mov_b32 s54, 0 ; BEB60380 s_mov_b32 s55, 0 ; BEB70380 s_mov_b32 s55, 0 ; BEB70380 s_mov_b32 s56, 0 ; BEB80380 s_mov_b32 s56, 0 ; BEB80380 s_mov_b32 s57, 0 ; BEB90380 s_mov_b32 s57, 0 ; BEB90380 s_mov_b32 s28, 0 ; BE9C0380 s_mov_b32 s28, 0 ; BE9C0380 v_readlane_b32 s29, v105, 24 ; 023B3169 v_readlane_b32 s29, v105, 24 ; 023B3169 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v39, v15, s29, v39 ; D2820027 049C3B0F v_mad_f32 v39, v15, s29, v39 ; D2820027 049C3B0F v_readlane_b32 s29, v105, 25 ; 023B3369 v_readlane_b32 s29, v105, 25 ; 023B3369 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v40, v38, s29, v40 ; D2820028 04A03B26 v_mad_f32 v40, v38, s29, v40 ; D2820028 04A03B26 v_readlane_b32 s29, v105, 26 ; 023B3569 v_readlane_b32 s29, v105, 26 ; 023B3569 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v40, v15, s29, v40 ; D2820028 04A03B0F v_mad_f32 v40, v15, s29, v40 ; D2820028 04A03B0F v_readlane_b32 s29, v105, 28 ; 023B3969 v_readlane_b32 s29, v105, 28 ; 023B3969 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v41, v38, s29, v41 ; D2820029 04A43B26 v_mad_f32 v41, v38, s29, v41 ; D2820029 04A43B26 v_readlane_b32 s29, v105, 29 ; 023B3B69 v_readlane_b32 s29, v105, 29 ; 023B3B69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v41, v15, s29, v41 ; D2820029 04A43B0F v_mad_f32 v41, v15, s29, v41 ; D2820029 04A43B0F v_readlane_b32 s29, v105, 33 ; 023B4369 v_readlane_b32 s29, v105, 33 ; 023B4369 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mul_f32_e32 v42, s29, v37 ; 10544A1D v_mul_f32_e32 v42, s29, v37 ; 10544A1D v_readlane_b32 s29, v105, 30 ; 023B3D69 v_readlane_b32 s29, v105, 30 ; 023B3D69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v42, v36, s29, v42 ; D282002A 04A83B24 v_mad_f32 v42, v36, s29, v42 ; D282002A 04A83B24 v_mad_f32 v42, v38, s58, v42 ; D282002A 04A87526 v_mad_f32 v42, v38, s58, v42 ; D282002A 04A87526 v_mad_f32 v42, v15, s59, v42 ; D282002A 04A8770F v_mad_f32 v42, v15, s59, v42 ; D282002A 04A8770F v_mul_f32_e32 v47, s19, v37 ; 105E4A13 v_mul_f32_e32 v47, s19, v37 ; 105E4A13 v_mad_f32 v47, v36, s13, v47 ; D282002F 04BC1B24 v_mad_f32 v47, v36, s13, v47 ; D282002F 04BC1B24 v_mad_f32 v47, v38, s15, v47 ; D282002F 04BC1F26 v_mad_f32 v47, v38, s15, v47 ; D282002F 04BC1F26 v_readlane_b32 s13, v105, 32 ; 021B4169 v_readlane_b32 s13, v105, 32 ; 021B4169 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v47, v15, s13, v47 ; D282002F 04BC1B0F v_mad_f32 v47, v15, s13, v47 ; D282002F 04BC1B0F v_mul_f32_e32 v48, s16, v37 ; 10604A10 v_mul_f32_e32 v48, s16, v37 ; 10604A10 v_mad_f32 v48, v36, s11, v48 ; D2820030 04C01724 v_mad_f32 v48, v36, s11, v48 ; D2820030 04C01724 v_mad_f32 v48, v38, s17, v48 ; D2820030 04C02326 v_mad_f32 v48, v38, s17, v48 ; D2820030 04C02326 v_readlane_b32 s11, v105, 31 ; 02173F69 v_readlane_b32 s11, v105, 31 ; 02173F69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v48, v15, s11, v48 ; D2820030 04C0170F v_mad_f32 v48, v15, s11, v48 ; D2820030 04C0170F v_mul_f32_e32 v37, s18, v37 ; 104A4A12 v_mul_f32_e32 v37, s18, v37 ; 104A4A12 v_mad_f32 v36, v36, s12, v37 ; D2820024 04941924 v_mad_f32 v36, v36, s12, v37 ; D2820024 04941924 v_mad_f32 v36, v38, s14, v36 ; D2820024 04901D26 v_mad_f32 v36, v38, s14, v36 ; D2820024 04901D26 v_readlane_b32 s11, v105, 27 ; 02173769 v_readlane_b32 s11, v105, 27 ; 02173769 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v12, v15, s11, v36 ; D282000C 0490170F v_mad_f32 v12, v15, s11, v36 ; D282000C 0490170F v_mul_f32_e32 v13, v54, v52 ; 101A6936 v_mul_f32_e32 v13, v54, v52 ; 101A6936 v_mad_f32 v14, s63, v13, v75 ; D282000E 052E1A3F v_mad_f32 v14, s63, v13, v75 ; D282000E 052E1A3F v_mad_f32 v15, s64, v13, v76 ; D282000F 05321A40 v_mad_f32 v15, s64, v13, v76 ; D282000F 05321A40 v_mad_f32 v13, s66, v13, v77 ; D282000D 05361A42 v_mad_f32 v13, s66, v13, v77 ; D282000D 05361A42 v_sub_f32_e32 v36, 0.5, v48 ; 084860F0 v_sub_f32_e32 v36, 0.5, v48 ; 084860F0 v_add_f32_e32 v37, 0.5, v12 ; 064A18F0 v_add_f32_e32 v37, 0.5, v12 ; 064A18F0 v_cndmask_b32_e64 v38, v29, v36, vcc ; D2000026 01AA491D v_cndmask_b32_e64 v38, v29, v36, vcc ; D2000026 01AA491D v_cndmask_b32_e64 v38, v38, v37, s[22:23] ; D2000026 005A4B26 v_cndmask_b32_e64 v38, v38, v37, s[22:23] ; D2000026 005A4B26 v_mul_f32_e32 v49, s78, v38 ; 10624C4E v_mul_f32_e32 v49, s78, v38 ; 10624C4E v_add_f32_e32 v50, 0.5, v47 ; 06645EF0 v_add_f32_e32 v50, 0.5, v47 ; 06645EF0 v_cndmask_b32_e64 v28, v28, v50, vcc ; D200001C 01AA651C v_cndmask_b32_e64 v28, v28, v50, vcc ; D200001C 01AA651C v_sub_f32_e32 v29, 0.5, v12 ; 083A18F0 v_sub_f32_e32 v29, 0.5, v12 ; 083A18F0 v_cndmask_b32_e64 v28, v28, v29, s[100:101] ; D200001C 01923B1C v_cndmask_b32_e64 v28, v28, v29, s[100:101] ; D200001C 01923B1C v_mad_f32 v30, v28, s74, v49 ; D282001E 04C4951C v_mad_f32 v30, v28, s74, v49 ; D282001E 04C4951C v_mad_f32 v30, 0, s75, v30 ; D282001E 04789680 v_mad_f32 v30, 0, s75, v30 ; D282001E 04789680 v_add_f32_e32 v30, s76, v30 ; 063C3C4C v_add_f32_e32 v30, s76, v30 ; 063C3C4C v_mul_f32_e32 v31, s79, v38 ; 103E4C4F v_mul_f32_e32 v31, s79, v38 ; 103E4C4F v_mad_f32 v28, v28, s77, v31 ; D282001C 047C9B1C v_mad_f32 v28, v28, s77, v31 ; D282001C 047C9B1C v_mad_f32 v28, 0, s80, v28 ; D282001C 0470A080 v_mad_f32 v28, 0, s80, v28 ; D282001C 0470A080 v_add_f32_e32 v28, s81, v28 ; 06383851 v_add_f32_e32 v28, s81, v28 ; 06383851 v_cndmask_b32_e64 v31, v5, v36, s[96:97] ; D200001F 01824905 v_cndmask_b32_e64 v31, v5, v36, s[96:97] ; D200001F 01824905 v_cndmask_b32_e64 v31, v31, v37, s[98:99] ; D200001F 018A4B1F v_cndmask_b32_e64 v31, v31, v37, s[98:99] ; D200001F 018A4B1F v_readlane_b32 s11, v105, 20 ; 02172969 v_readlane_b32 s11, v105, 20 ; 02172969 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mul_f32_e32 v38, s11, v31 ; 104C3E0B v_mul_f32_e32 v38, s11, v31 ; 104C3E0B v_cndmask_b32_e64 v4, v4, v50, s[96:97] ; D2000004 01826504 v_cndmask_b32_e64 v4, v4, v50, s[96:97] ; D2000004 01826504 v_cndmask_b32_e64 v4, v4, v29, s[94:95] ; D2000004 017A3B04 v_cndmask_b32_e64 v4, v4, v29, s[94:95] ; D2000004 017A3B04 v_readlane_b32 s11, v105, 16 ; 02172169 v_readlane_b32 s11, v105, 16 ; 02172169 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v5, v4, s11, v38 ; D2820005 04981704 v_mad_f32 v5, v4, s11, v38 ; D2820005 04981704 v_readlane_b32 s11, v105, 17 ; 02172369 v_readlane_b32 s11, v105, 17 ; 02172369 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v5, 0, s11, v5 ; D2820005 04141680 v_mad_f32 v5, 0, s11, v5 ; D2820005 04141680 v_readlane_b32 s11, v105, 18 ; 02172569 v_readlane_b32 s11, v105, 18 ; 02172569 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_add_f32_e32 v5, s11, v5 ; 060A0A0B v_add_f32_e32 v5, s11, v5 ; 060A0A0B v_readlane_b32 s11, v105, 21 ; 02172B69 v_readlane_b32 s11, v105, 21 ; 02172B69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mul_f32_e32 v6, s11, v31 ; 100C3E0B v_mul_f32_e32 v6, s11, v31 ; 100C3E0B v_readlane_b32 s11, v105, 19 ; 02172769 v_readlane_b32 s11, v105, 19 ; 02172769 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v4, v4, s11, v6 ; D2820004 04181704 v_mad_f32 v4, v4, s11, v6 ; D2820004 04181704 v_readlane_b32 s11, v105, 22 ; 02172D69 v_readlane_b32 s11, v105, 22 ; 02172D69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v4, 0, s11, v4 ; D2820004 04101680 v_mad_f32 v4, 0, s11, v4 ; D2820004 04101680 v_readlane_b32 s11, v105, 23 ; 02172F69 v_readlane_b32 s11, v105, 23 ; 02172F69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_add_f32_e32 v4, s11, v4 ; 0608080B v_add_f32_e32 v4, s11, v4 ; 0608080B v_cndmask_b32_e64 v6, v25, v36, s[88:89] ; D2000006 01624919 v_cndmask_b32_e64 v6, v25, v36, s[88:89] ; D2000006 01624919 v_cndmask_b32_e64 v6, v6, v37, s[92:93] ; D2000006 01724B06 v_cndmask_b32_e64 v6, v6, v37, s[92:93] ; D2000006 01724B06 v_mul_f32_e32 v7, s69, v6 ; 100E0C45 v_mul_f32_e32 v7, s69, v6 ; 100E0C45 v_cndmask_b32_e64 v24, v24, v50, s[88:89] ; D2000018 01626518 v_cndmask_b32_e64 v24, v24, v50, s[88:89] ; D2000018 01626518 v_cndmask_b32_e64 v24, v24, v29, s[90:91] ; D2000018 016A3B18 v_cndmask_b32_e64 v24, v24, v29, s[90:91] ; D2000018 016A3B18 v_mad_f32 v7, v24, s62, v7 ; D2820007 041C7D18 v_mad_f32 v7, v24, s62, v7 ; D2820007 041C7D18 v_mad_f32 v7, 0, s65, v7 ; D2820007 041C8280 v_mad_f32 v7, 0, s65, v7 ; D2820007 041C8280 v_add_f32_e32 v7, s67, v7 ; 060E0E43 v_add_f32_e32 v7, s67, v7 ; 060E0E43 v_mul_f32_e32 v6, s71, v6 ; 100C0C47 v_mul_f32_e32 v6, s71, v6 ; 100C0C47 v_mad_f32 v6, v24, s68, v6 ; D2820006 04188918 v_mad_f32 v6, v24, s68, v6 ; D2820006 04188918 v_mad_f32 v6, 0, s72, v6 ; D2820006 04189080 v_mad_f32 v6, 0, s72, v6 ; D2820006 04189080 v_add_f32_e32 v6, s73, v6 ; 060C0C49 v_add_f32_e32 v6, s73, v6 ; 060C0C49 v_cndmask_b32_e64 v24, v9, v36, s[84:85] ; D2000018 01524909 v_cndmask_b32_e64 v24, v9, v36, s[84:85] ; D2000018 01524909 v_cndmask_b32_e64 v24, v24, v37, s[86:87] ; D2000018 015A4B18 v_cndmask_b32_e64 v24, v24, v37, s[86:87] ; D2000018 015A4B18 v_mul_f32_e32 v25, s5, v24 ; 10323005 v_mul_f32_e32 v25, s5, v24 ; 10323005 v_cndmask_b32_e64 v8, v8, v50, s[84:85] ; D2000008 01526508 v_cndmask_b32_e64 v8, v8, v50, s[84:85] ; D2000008 01526508 v_cndmask_b32_e64 v8, v8, v29, s[82:83] ; D2000008 014A3B08 v_cndmask_b32_e64 v8, v8, v29, s[82:83] ; D2000008 014A3B08 v_mad_f32 v9, v8, s0, v25 ; D2820009 04640108 v_mad_f32 v9, v8, s0, v25 ; D2820009 04640108 v_mad_f32 v9, 0, s1, v9 ; D2820009 04240280 v_mad_f32 v9, 0, s1, v9 ; D2820009 04240280 v_add_f32_e32 v9, s61, v9 ; 0612123D v_add_f32_e32 v9, s61, v9 ; 0612123D v_mul_f32_e32 v10, s6, v24 ; 10143006 v_mul_f32_e32 v10, s6, v24 ; 10143006 v_mad_f32 v8, v8, s4, v10 ; D2820008 04280908 v_mad_f32 v8, v8, s4, v10 ; D2820008 04280908 v_mad_f32 v8, 0, s7, v8 ; D2820008 04200E80 v_mad_f32 v8, 0, s7, v8 ; D2820008 04200E80 v_cndmask_b32_e64 v10, v20, v50, s[8:9] ; D200000A 00226514 v_cndmask_b32_e64 v10, v20, v50, s[8:9] ; D200000A 00226514 v_cndmask_b32_e64 v11, v21, v36, s[8:9] ; D200000B 00224915 v_cndmask_b32_e64 v11, v21, v36, s[8:9] ; D200000B 00224915 v_cndmask_b32_e64 v10, v10, v29, s[24:25] ; D200000A 00623B0A v_cndmask_b32_e64 v10, v10, v29, s[24:25] ; D200000A 00623B0A v_cndmask_b32_e64 v11, v11, v37, s[26:27] ; D200000B 006A4B0B v_cndmask_b32_e64 v11, v11, v37, s[26:27] ; D200000B 006A4B0B v_add_f32_e32 v8, s60, v8 ; 0610103C v_add_f32_e32 v8, s60, v8 ; 0610103C v_readlane_b32 s0, v105, 10 ; 02011569 v_readlane_b32 s0, v105, 10 ; 02011569 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v0, s0, v10, v0 ; D2820000 04021400 v_mad_f32 v0, s0, v10, v0 ; D2820000 04021400 v_readlane_b32 s0, v105, 14 ; 02011D69 v_readlane_b32 s0, v105, 14 ; 02011D69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v10, s0, v11, v46 ; D282000A 04BA1600 v_mad_f32 v10, s0, v11, v46 ; D282000A 04BA1600 v_add_f32_e32 v11, v18, v18 ; 06162512 v_add_f32_e32 v11, v18, v18 ; 06162512 v_mul_f32_e32 v11, v11, v11 ; 1016170B v_mul_f32_e32 v11, v11, v11 ; 1016170B v_add_f32_e32 v20, v17, v17 ; 06282311 v_add_f32_e32 v20, v17, v17 ; 06282311 v_mul_f32_e32 v20, v20, v20 ; 10282914 v_mul_f32_e32 v20, v20, v20 ; 10282914 v_add_f32_e32 v21, v16, v16 ; 062A2110 v_add_f32_e32 v21, v16, v16 ; 062A2110 v_mul_f32_e32 v21, v21, v21 ; 102A2B15 v_mul_f32_e32 v21, v21, v21 ; 102A2B15 v_mad_f32 v11, s70, v11, v55 ; D282000B 04DE1646 v_mad_f32 v11, s70, v11, v55 ; D282000B 04DE1646 v_mad_f32 v20, s70, v20, v55 ; D2820014 04DE2846 v_mad_f32 v20, s70, v20, v55 ; D2820014 04DE2846 v_mad_f32 v21, s70, v21, v55 ; D2820015 04DE2A46 v_mad_f32 v21, s70, v21, v55 ; D2820015 04DE2A46 v_mad_f32 v16, s70, v19, v55 ; D2820010 04DE2646 v_mad_f32 v16, s70, v19, v55 ; D2820010 04DE2646 exp 15, 32, 0, 0, 0, v5, v4, v7, v6 ; F800020F 06070405 exp 15, 32, 0, 0, 0, v5, v4, v7, v6 ; F800020F 06070405 exp 15, 33, 0, 0, 0, v74, v35, v30, v28 ; F800021F 1C1E234A exp 15, 33, 0, 0, 0, v74, v35, v30, v28 ; F800021F 1C1E234A exp 15, 34, 0, 0, 0, v9, v8, v0, v10 ; F800022F 0A000809 exp 15, 34, 0, 0, 0, v9, v8, v0, v10 ; F800022F 0A000809 exp 15, 35, 0, 0, 0, v11, v20, v21, v16 ; F800023F 1015140B exp 15, 35, 0, 0, 0, v11, v20, v21, v16 ; F800023F 1015140B s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mov_b32_e32 v0, 1.0 ; 7E0002F2 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 36, 0, 0, 0, v47, v48, v12, v0 ; F800024F 000C302F exp 15, 36, 0, 0, 0, v47, v48, v12, v0 ; F800024F 000C302F s_waitcnt expcnt(0) ; BF8C070F s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, v45, v45 ; 10005B2D v_mul_f32_e32 v0, v45, v45 ; 10005B2D v_mad_f32 v0, v44, v44, v0 ; D2820000 0402592C v_mad_f32 v0, v44, v44, v0 ; D2820000 0402592C v_mad_f32 v0, v43, v43, v0 ; D2820000 0402572B v_mad_f32 v0, v43, v43, v0 ; D2820000 0402572B v_rsq_clamp_f32_e32 v0, v0 ; 7E005900 v_rsq_clamp_f32_e32 v0, v0 ; 7E005900 v_mul_f32_e32 v4, v34, v34 ; 10084522 v_mul_f32_e32 v4, v34, v34 ; 10084522 v_mad_f32 v4, v32, v32, v4 ; D2820004 04124120 v_mad_f32 v4, v32, v32, v4 ; D2820004 04124120 v_mad_f32 v4, v33, v33, v4 ; D2820004 04124321 v_mad_f32 v4, v33, v33, v4 ; D2820004 04124321 v_rsq_clamp_f32_e32 v4, v4 ; 7E085904 v_rsq_clamp_f32_e32 v4, v4 ; 7E085904 v_mul_f32_e32 v5, v0, v45 ; 100A5B00 v_mul_f32_e32 v5, v0, v45 ; 100A5B00 v_mul_f32_e32 v6, v0, v44 ; 100C5900 v_mul_f32_e32 v6, v0, v44 ; 100C5900 v_mul_f32_e32 v0, v0, v43 ; 10005700 v_mul_f32_e32 v0, v0, v43 ; 10005700 v_mul_f32_e32 v7, v4, v34 ; 100E4504 v_mul_f32_e32 v7, v4, v34 ; 100E4504 v_mul_f32_e32 v8, v2, v2 ; 10100502 v_mul_f32_e32 v8, v2, v2 ; 10100502 v_mad_f32 v8, v3, v3, v8 ; D2820008 04220703 v_mad_f32 v8, v3, v3, v8 ; D2820008 04220703 v_mad_f32 v8, v1, v1, v8 ; D2820008 04220301 v_mad_f32 v8, v1, v1, v8 ; D2820008 04220301 v_rsq_clamp_f32_e32 v8, v8 ; 7E105908 v_rsq_clamp_f32_e32 v8, v8 ; 7E105908 exp 15, 37, 0, 0, 0, v5, v6, v0, v7 ; F800025F 07000605 exp 15, 37, 0, 0, 0, v5, v6, v0, v7 ; F800025F 07000605 s_waitcnt expcnt(0) ; BF8C070F s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, v4, v32 ; 10004104 v_mul_f32_e32 v0, v4, v32 ; 10004104 v_mul_f32_e32 v4, v4, v33 ; 10084304 v_mul_f32_e32 v4, v4, v33 ; 10084304 v_mul_f32_e32 v2, v8, v2 ; 10040508 v_mul_f32_e32 v2, v8, v2 ; 10040508 v_mul_f32_e32 v3, v8, v3 ; 10060708 v_mul_f32_e32 v3, v8, v3 ; 10060708 exp 15, 38, 0, 0, 0, v0, v4, v2, v3 ; F800026F 03020400 exp 15, 38, 0, 0, 0, v0, v4, v2, v3 ; F800026F 03020400 s_waitcnt expcnt(0) ; BF8C070F s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, v53, v54 ; 10006D35 v_mul_f32_e32 v0, v53, v54 ; 10006D35 v_readlane_b32 s0, v105, 2 ; 02010569 v_readlane_b32 s0, v105, 2 ; 02010569 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v2, s0, v0, v14 ; D2820002 043A0000 v_mad_f32 v2, s0, v0, v14 ; D2820002 043A0000 v_readlane_b32 s0, v105, 3 ; 02010769 v_readlane_b32 s0, v105, 3 ; 02010769 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v3, s0, v0, v15 ; D2820003 043E0000 v_mad_f32 v3, s0, v0, v15 ; D2820003 043E0000 v_readlane_b32 s0, v105, 4 ; 02010969 v_readlane_b32 s0, v105, 4 ; 02010969 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v0, s0, v0, v13 ; D2820000 04360000 v_mad_f32 v0, s0, v0, v13 ; D2820000 04360000 v_mul_f32_e32 v4, v52, v53 ; 10086B34 v_mul_f32_e32 v4, v52, v53 ; 10086B34 v_readlane_b32 s0, v105, 5 ; 02010B69 v_readlane_b32 s0, v105, 5 ; 02010B69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_readlane_b32 s0, v105, 7 ; 02010F69 v_readlane_b32 s0, v105, 7 ; 02010F69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_readlane_b32 s0, v105, 11 ; 02011769 v_readlane_b32 s0, v105, 11 ; 02011769 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mul_f32_e32 v4, v54, v54 ; 10086D36 v_mul_f32_e32 v4, v54, v54 ; 10086D36 v_mov_b32_e32 v5, 0x40400000 ; 7E0A02FF 40400000 v_mov_b32_e32 v5, 0x40400000 ; 7E0A02FF 40400000 v_mad_f32 v4, v5, v4, -1.0 ; D2820004 03CE0905 v_mad_f32 v4, v5, v4, -1.0 ; D2820004 03CE0905 v_readlane_b32 s0, v105, 6 ; 02010D69 v_readlane_b32 s0, v105, 6 ; 02010D69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_readlane_b32 s0, v105, 8 ; 02011169 v_readlane_b32 s0, v105, 8 ; 02011169 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_readlane_b32 s0, v105, 12 ; 02011969 v_readlane_b32 s0, v105, 12 ; 02011969 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mul_f32_e32 v4, v53, v53 ; 10086B35 v_mul_f32_e32 v4, v53, v53 ; 10086B35 v_mad_f32 v4, v52, v52, -v4 ; D2820004 84126934 v_mad_f32 v4, v52, v52, -v4 ; D2820004 84126934 v_readlane_b32 s0, v105, 9 ; 02011369 v_readlane_b32 s0, v105, 9 ; 02011369 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_mad_f32 v2, s0, v4, v2 ; D2820002 040A0800 v_readlane_b32 s0, v105, 13 ; 02011B69 v_readlane_b32 s0, v105, 13 ; 02011B69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_mad_f32 v3, s0, v4, v3 ; D2820003 040E0800 v_readlane_b32 s0, v105, 15 ; 02011F69 v_readlane_b32 s0, v105, 15 ; 02011F69 s_nop 2 ; BF800002 s_nop 2 ; BF800002 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mad_f32 v0, s0, v4, v0 ; D2820000 04020800 v_mul_f32_e32 v1, v8, v1 ; 10020308 v_mul_f32_e32 v1, v8, v1 ; 10020308 v_mul_f32_e32 v4, s3, v40 ; 10085003 v_mul_f32_e32 v4, s3, v40 ; 10085003 v_mad_f32 v4, s2, v39, v4 ; D2820004 04124E02 v_mad_f32 v4, s2, v39, v4 ; D2820004 04124E02 v_mad_f32 v4, s10, v41, v4 ; D2820004 0412520A v_mad_f32 v4, s10, v41, v4 ; D2820004 0412520A v_mad_f32 v4, s20, v42, v4 ; D2820004 04125414 v_mad_f32 v4, s20, v42, v4 ; D2820004 04125414 v_mul_f32_e32 v5, s32, v40 ; 100A5020 v_mul_f32_e32 v5, s32, v40 ; 100A5020 v_mad_f32 v5, s21, v39, v5 ; D2820005 04164E15 v_mad_f32 v5, s21, v39, v5 ; D2820005 04164E15 v_mad_f32 v5, s33, v41, v5 ; D2820005 04165221 v_mad_f32 v5, s33, v41, v5 ; D2820005 04165221 v_mad_f32 v5, s34, v42, v5 ; D2820005 04165422 v_mad_f32 v5, s34, v42, v5 ; D2820005 04165422 v_mul_f32_e32 v6, s36, v40 ; 100C5024 v_mul_f32_e32 v6, s36, v40 ; 100C5024 v_mad_f32 v6, s35, v39, v6 ; D2820006 041A4E23 v_mad_f32 v6, s35, v39, v6 ; D2820006 041A4E23 v_mad_f32 v6, s37, v41, v6 ; D2820006 041A5225 v_mad_f32 v6, s37, v41, v6 ; D2820006 041A5225 v_mad_f32 v6, s38, v42, v6 ; D2820006 041A5426 v_mad_f32 v6, s38, v42, v6 ; D2820006 041A5426 v_mul_f32_e32 v7, s40, v40 ; 100E5028 v_mul_f32_e32 v7, s40, v40 ; 100E5028 v_mad_f32 v7, s39, v39, v7 ; D2820007 041E4E27 v_mad_f32 v7, s39, v39, v7 ; D2820007 041E4E27 v_mad_f32 v7, s41, v41, v7 ; D2820007 041E5229 v_mad_f32 v7, s41, v41, v7 ; D2820007 041E5229 v_mad_f32 v7, s42, v42, v7 ; D2820007 041E542A v_mad_f32 v7, s42, v42, v7 ; D2820007 041E542A v_mul_f32_e32 v8, s44, v40 ; 1010502C v_mul_f32_e32 v8, s44, v40 ; 1010502C v_mad_f32 v8, s43, v39, v8 ; D2820008 04224E2B v_mad_f32 v8, s43, v39, v8 ; D2820008 04224E2B v_mad_f32 v8, s45, v41, v8 ; D2820008 0422522D v_mad_f32 v8, s45, v41, v8 ; D2820008 0422522D v_mad_f32 v8, s46, v42, v8 ; D2820008 0422542E v_mad_f32 v8, s46, v42, v8 ; D2820008 0422542E v_mul_f32_e32 v9, s48, v40 ; 10125030 v_mul_f32_e32 v9, s48, v40 ; 10125030 v_mad_f32 v9, s47, v39, v9 ; D2820009 04264E2F v_mad_f32 v9, s47, v39, v9 ; D2820009 04264E2F v_mad_f32 v9, s49, v41, v9 ; D2820009 04265231 v_mad_f32 v9, s49, v41, v9 ; D2820009 04265231 v_mad_f32 v9, s50, v42, v9 ; D2820009 04265432 v_mad_f32 v9, s50, v42, v9 ; D2820009 04265432 v_mul_f32_e32 v10, s52, v40 ; 10145034 v_mul_f32_e32 v10, s52, v40 ; 10145034 v_mad_f32 v10, s51, v39, v10 ; D282000A 042A4E33 v_mad_f32 v10, s51, v39, v10 ; D282000A 042A4E33 v_mad_f32 v10, s53, v41, v10 ; D282000A 042A5235 v_mad_f32 v10, s53, v41, v10 ; D282000A 042A5235 v_mad_f32 v10, s54, v42, v10 ; D282000A 042A5436 v_mad_f32 v10, s54, v42, v10 ; D282000A 042A5436 v_mul_f32_e32 v11, s56, v40 ; 10165038 v_mul_f32_e32 v11, s56, v40 ; 10165038 v_mad_f32 v11, s55, v39, v11 ; D282000B 042E4E37 v_mad_f32 v11, s55, v39, v11 ; D282000B 042E4E37 v_max_f32_e32 v2, 0, v2 ; 20040480 v_max_f32_e32 v2, 0, v2 ; 20040480 v_max_f32_e32 v3, 0, v3 ; 20060680 v_max_f32_e32 v3, 0, v3 ; 20060680 v_max_f32_e32 v0, 0, v0 ; 20000080 v_max_f32_e32 v0, 0, v0 ; 20000080 v_mad_f32 v11, s57, v41, v11 ; D282000B 042E5239 v_mad_f32 v11, s57, v41, v11 ; D282000B 042E5239 v_mad_f32 v11, s28, v42, v11 ; D282000B 042E541C v_mad_f32 v11, s28, v42, v11 ; D282000B 042E541C exp 15, 39, 0, 0, 0, v1, v2, v3, v0 ; F800027F 00030201 exp 15, 39, 0, 0, 0, v1, v2, v3, v0 ; F800027F 00030201 exp 15, 12, 0, 0, 0, v39, v40, v41, v42 ; F80000CF 2A292827 exp 15, 12, 0, 0, 0, v39, v40, v41, v42 ; F80000CF 2A292827 exp 15, 13, 0, 0, 0, v4, v5, v6, v7 ; F80000DF 07060504 exp 15, 13, 0, 0, 0, v4, v5, v6, v7 ; F80000DF 07060504 exp 15, 14, 0, 1, 0, v8, v9, v10, v11 ; F80008EF 0B0A0908 exp 15, 14, 0, 1, 0, v8, v9, v10, v11 ; F80008EF 0B0A0908 s_endpgm ; BF810000 s_endpgm ; BF810000