diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d32ce48..040e391 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2207,14 +2207,23 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
 	int ret, i;
+	u8 value;
 
 	/* Should have a valid DPCD by this point */
 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 		return;
 
 	if (mode != DRM_MODE_DPMS_ON) {
-		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
-					 DP_SET_POWER_D3);
+		ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SET_POWER, &value);
+		if (ret < 0)
+			DRM_DEBUG_KMS("unable to read sink power state\n");
+
+		value &= ~DP_SET_POWER_MASK;
+		value |= DP_SET_POWER_D3;
+
+		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, value);
+		if (ret < 0)
+			DRM_DEBUG_KMS("unable to write sink power state\n");
 	} else {
 		/*
 		 * When turning on, we need to retry for 1ms to give the sink