From 8c5745c17fea4b276980ce700cabbad21c6c57a8 Mon Sep 17 00:00:00 2001 From: Gary Wang Date: Thu, 27 Aug 2015 17:39:36 +0800 Subject: [PATCH] drm/i915: force to check CDCLK during resuming from S3 Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then driver needs to force setting CDCLK to avoid display corruption. Signed-off-by: Gary Wang --- drivers/gpu/drm/i915/intel_display.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/i915/intel_display.c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c old mode 100644 new mode 100755 index f604ce1..2193da3 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5707,13 +5707,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) /* enable PG1 and Misc I/O */ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); - /* DPLL0 already enabed !? */ - if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { - DRM_DEBUG_DRIVER("DPLL0 already running\n"); - return; - } - - /* enable DPLL0 */ + /* BIOS will enable DPLL0 during S3 resume since RC 1.4, so force to set CDCLK */ required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); skl_dpll0_enable(dev_priv, required_vco); -- 1.9.1