From 8d251e3117dec00e57cf0f0b38949c52c30420c9 Mon Sep 17 00:00:00 2001 From: Gary Wang Date: Fri, 28 Aug 2015 10:33:51 +0800 Subject: [PATCH] drm/i915: set CDCLK if DPLL0 enabled during resuming from S3 Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then driver needs to set CDCLK to avoid display corruption if DPLL0 enabled. Signed-off-by: Gary Wang --- drivers/gpu/drm/i915/intel_display.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/i915/intel_display.c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c old mode 100644 new mode 100755 index f604ce1..c99b716 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5707,16 +5707,13 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) /* enable PG1 and Misc I/O */ intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); - /* DPLL0 already enabed !? */ - if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { - DRM_DEBUG_DRIVER("DPLL0 already running\n"); - return; + /* DPLL0 not enabed !? */ + if ((!I915_READ(LCPLL1_CTL)) & LCPLL_PLL_ENABLE) { + /* enable DPLL0 */ + required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); + skl_dpll0_enable(dev_priv, required_vco); } - /* enable DPLL0 */ - required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); - skl_dpll0_enable(dev_priv, required_vco); - /* set CDCLK to the frequency the BIOS chose */ skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); -- 1.9.1