From b7cc48151febca77d3e53058aeec8f2b363bd0da Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Tue, 3 Nov 2015 12:17:00 +0200 Subject: [PATCH] drm/i915: Request for resets under forcewake We have a timed release of a forcewake when using I915_READ/WRITE macros. wait_for() macro will go to a quite long sleep if the first read doesn't satisfy the condition for successful exit. With these two interacting, it is possible that we lose the forcewake during the wait_for() and the subsequent read will reaquire forcewake. Further experiments with skl shows that when we lose forcewake, we lose the reset request we submitted. So this register is not power context saved. Grab forcewakes for all engines before starting to request for resets so that all requests stay valid for the duration of reset requstion across all the engines. Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f0f97b2..5a6e7f1b 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1483,6 +1483,8 @@ static int gen8_do_reset(struct drm_device *dev) struct intel_engine_cs *engine; int i; + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + for_each_ring(engine, dev_priv, i) { I915_WRITE(RING_RESET_CTL(engine->mmio_base), _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); @@ -1497,6 +1499,8 @@ static int gen8_do_reset(struct drm_device *dev) } } + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + return gen6_do_reset(dev); not_ready: @@ -1504,6 +1508,8 @@ not_ready: I915_WRITE(RING_RESET_CTL(engine->mmio_base), _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + return -EIO; } -- 2.5.0