ernst@mammut:~$ dmesg [ 0.000000] microcode: CPU0 microcode updated early to revision 0x29, date = 2013-06-12 [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Initializing cgroup subsys cpuacct [ 0.000000] Linux version 4.3.999powerplay+ (ernst@mammut) (gcc version 5.2.1 20151010 (Ubuntu 5.2.1-22ubuntu2) ) #4 SMP Fri Nov 13 20:24:20 CET 2015 [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.3.999powerplay+ root=UUID=96de4ed3-7fc6-4ea4-a69a-d62b15398dde ro amdgpu.enable_scheduler=0 quiet splash vt.handoff=7 [ 0.000000] KERNEL supported cpus: [ 0.000000] Intel GenuineIntel [ 0.000000] AMD AuthenticAMD [ 0.000000] Centaur CentaurHauls [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 [ 0.000000] x86/fpu: Supporting XSAVE feature 0x01: 'x87 floating point registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x02: 'SSE registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x04: 'AVX registers' [ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format. [ 0.000000] x86/fpu: Using 'eager' FPU context switches. [ 0.000000] e820: BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff] usable [ 0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000bf1dffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000bf1e0000-0x00000000bf231fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bf232000-0x00000000bf5a4fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000bf5a5000-0x00000000bf5b5fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bf5b6000-0x00000000bf5ccfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000bf5cd000-0x00000000bf5cefff] usable [ 0.000000] BIOS-e820: [mem 0x00000000bf5cf000-0x00000000bf5d6fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000bf5d7000-0x00000000bf5e1fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bf5e2000-0x00000000bf63dfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000bf63e000-0x00000000bf680fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bf681000-0x00000000bf7fffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000023f7fffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] SMBIOS 2.6 present. [ 0.000000] DMI: System manufacturer System Product Name/P8P67 PRO REV 3.1, BIOS 1704 06/08/2011 [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] e820: last_pfn = 0x23f800 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-CFFFF write-protect [ 0.000000] D0000-E7FFF uncachable [ 0.000000] E8000-FFFFF write-protect [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 000000000 mask E00000000 write-back [ 0.000000] 1 base 200000000 mask FC0000000 write-back [ 0.000000] 2 base 0C0000000 mask FC0000000 uncachable [ 0.000000] 3 base 23F800000 mask FFF800000 uncachable [ 0.000000] 4 disabled [ 0.000000] 5 disabled [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] 8 disabled [ 0.000000] 9 disabled [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT [ 0.000000] original variable MTRRs [ 0.000000] reg 0, base: 0GB, range: 8GB, type WB [ 0.000000] reg 1, base: 8GB, range: 1GB, type WB [ 0.000000] reg 2, base: 3GB, range: 1GB, type UC [ 0.000000] reg 3, base: 9208MB, range: 8MB, type UC [ 0.000000] total RAM covered: 8184M [ 0.000000] Found optimal setting for mtrr clean up [ 0.000000] gran_size: 64K chunk_size: 16M num_reg: 5 lose cover RAM: 0G [ 0.000000] New variable MTRRs [ 0.000000] reg 0, base: 0GB, range: 2GB, type WB [ 0.000000] reg 1, base: 2GB, range: 1GB, type WB [ 0.000000] reg 2, base: 4GB, range: 4GB, type WB [ 0.000000] reg 3, base: 8GB, range: 1GB, type WB [ 0.000000] reg 4, base: 9208MB, range: 8MB, type UC [ 0.000000] e820: update [mem 0xc0000000-0xffffffff] usable ==> reserved [ 0.000000] e820: last_pfn = 0xbf800 max_arch_pfn = 0x400000000 [ 0.000000] found SMP MP-table at [mem 0x000fcdd0-0x000fcddf] mapped at [ffff8800000fcdd0] [ 0.000000] Scanning 1 areas for low memory corruption [ 0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576 [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] [ 0.000000] [mem 0x00000000-0x000fffff] page 4k [ 0.000000] BRK [0x01ff3000, 0x01ff3fff] PGTABLE [ 0.000000] BRK [0x01ff4000, 0x01ff4fff] PGTABLE [ 0.000000] BRK [0x01ff5000, 0x01ff5fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0x23f600000-0x23f7fffff] [ 0.000000] [mem 0x23f600000-0x23f7fffff] page 2M [ 0.000000] BRK [0x01ff6000, 0x01ff6fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0x220000000-0x23f5fffff] [ 0.000000] [mem 0x220000000-0x23f5fffff] page 2M [ 0.000000] init_memory_mapping: [mem 0x200000000-0x21fffffff] [ 0.000000] [mem 0x200000000-0x21fffffff] page 2M [ 0.000000] init_memory_mapping: [mem 0x00100000-0xbf1dffff] [ 0.000000] [mem 0x00100000-0x001fffff] page 4k [ 0.000000] [mem 0x00200000-0xbeffffff] page 2M [ 0.000000] [mem 0xbf000000-0xbf1dffff] page 4k [ 0.000000] init_memory_mapping: [mem 0xbf5cd000-0xbf5cefff] [ 0.000000] [mem 0xbf5cd000-0xbf5cefff] page 4k [ 0.000000] BRK [0x01ff7000, 0x01ff7fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0xbf681000-0xbf7fffff] [ 0.000000] [mem 0xbf681000-0xbf7fffff] page 4k [ 0.000000] BRK [0x01ff8000, 0x01ff8fff] PGTABLE [ 0.000000] init_memory_mapping: [mem 0x100000000-0x1ffffffff] [ 0.000000] [mem 0x100000000-0x1ffffffff] page 2M [ 0.000000] RAMDISK: [mem 0x33ce6000-0x35e6afff] [ 0.000000] ACPI: Early table checksum verification disabled [ 0.000000] ACPI: RSDP 0x00000000000F0420 000024 (v02 ALASKA) [ 0.000000] ACPI: XSDT 0x00000000BF229068 00004C (v01 ALASKA A M I 01072009 AMI 00010013) [ 0.000000] ACPI: FACP 0x00000000BF231A50 0000F4 (v04 ALASKA A M I 01072009 AMI 00010013) [ 0.000000] ACPI: DSDT 0x00000000BF229140 00890D (v02 ALASKA A M I 00000000 INTL 20051117) [ 0.000000] ACPI: FACS 0x00000000BF5D9F80 000040 [ 0.000000] ACPI: APIC 0x00000000BF231B48 000072 (v03 ALASKA A M I 01072009 AMI 00010013) [ 0.000000] ACPI: SSDT 0x00000000BF231BC0 000102 (v01 AMICPU PROC 00000001 MSFT 03000001) [ 0.000000] ACPI: MCFG 0x00000000BF231CC8 00003C (v01 ALASKA A M I 01072009 MSFT 00000097) [ 0.000000] ACPI: HPET 0x00000000BF231D08 000038 (v01 ALASKA A M I 01072009 AMI. 00000004) [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] No NUMA configuration found [ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000023f7fffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x23f7f5000-0x23f7f8fff] [ 0.000000] [ffffea0000000000-ffffea0008ffffff] PMD -> [ffff880236e00000-ffff88023edfffff] on node 0 [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.000000] Normal [mem 0x0000000100000000-0x000000023f7fffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000001000-0x000000000009cfff] [ 0.000000] node 0: [mem 0x0000000000100000-0x00000000bf1dffff] [ 0.000000] node 0: [mem 0x00000000bf5cd000-0x00000000bf5cefff] [ 0.000000] node 0: [mem 0x00000000bf681000-0x00000000bf7fffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023f7fffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000023f7fffff] [ 0.000000] On node 0 totalpages: 2091773 [ 0.000000] DMA zone: 64 pages used for memmap [ 0.000000] DMA zone: 21 pages reserved [ 0.000000] DMA zone: 3996 pages, LIFO batch:0 [ 0.000000] DMA32 zone: 12174 pages used for memmap [ 0.000000] DMA32 zone: 779105 pages, LIFO batch:31 [ 0.000000] Normal zone: 20448 pages used for memmap [ 0.000000] Normal zone: 1308672 pages, LIFO batch:31 [ 0.000000] ACPI: PM-Timer IO Port: 0x408 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) [ 0.000000] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000 [ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009d000-0x0009dfff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009ffff] [ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dffff] [ 0.000000] PM: Registered nosave memory: [mem 0x000e0000-0x000fffff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf1e0000-0xbf231fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf232000-0xbf5a4fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf5a5000-0xbf5b5fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf5b6000-0xbf5ccfff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf5cf000-0xbf5d6fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf5d7000-0xbf5e1fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf5e2000-0xbf63dfff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf63e000-0xbf680fff] [ 0.000000] PM: Registered nosave memory: [mem 0xbf800000-0xfed1bfff] [ 0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff] [ 0.000000] PM: Registered nosave memory: [mem 0xfed20000-0xfeffffff] [ 0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff] [ 0.000000] e820: [mem 0xbf800000-0xfed1bfff] available for PCI devices [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns [ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 33 pages/cpu @ffff88023f400000 s97496 r8192 d29480 u524288 [ 0.000000] pcpu-alloc: s97496 r8192 d29480 u524288 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 2059066 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.3.999powerplay+ root=UUID=96de4ed3-7fc6-4ea4-a69a-d62b15398dde ro amdgpu.enable_scheduler=0 quiet splash vt.handoff=7 [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! [ 0.000000] Memory: 8118380K/8367092K available (7967K kernel code, 1257K rwdata, 3904K rodata, 1452K init, 1292K bss, 248712K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] Build-time adjustment of leaf fanout to 64. [ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 [ 0.000000] NR_IRQS:16640 nr_irqs:456 16 [ 0.000000] Console: colour dummy device 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484882848 ns [ 0.000000] hpet clockevent registered [ 0.000000] tsc: Fast TSC calibration using PIT [ 0.000000] tsc: Detected 3300.067 MHz processor [ 0.000025] Calibrating delay loop (skipped), value calculated using timer frequency.. 6600.13 BogoMIPS (lpj=13200268) [ 0.000027] pid_max: default: 32768 minimum: 301 [ 0.000030] ACPI: Core revision 20150930 [ 0.003077] ACPI: 2 ACPI AML tables successfully acquired and loaded [ 0.003091] Security Framework initialized [ 0.003092] Yama: becoming mindful. [ 0.003098] AppArmor: AppArmor initialized [ 0.003469] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) [ 0.004645] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.005157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes) [ 0.005164] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes) [ 0.005307] Initializing cgroup subsys io [ 0.005310] Initializing cgroup subsys memory [ 0.005314] Initializing cgroup subsys devices [ 0.005315] Initializing cgroup subsys freezer [ 0.005318] Initializing cgroup subsys net_cls [ 0.005320] Initializing cgroup subsys perf_event [ 0.005321] Initializing cgroup subsys net_prio [ 0.005322] Initializing cgroup subsys hugetlb [ 0.005324] Initializing cgroup subsys pids [ 0.005341] CPU: Physical Processor ID: 0 [ 0.005341] CPU: Processor Core ID: 0 [ 0.005345] ENERGY_PERF_BIAS: Set to 'normal', was 'performance' [ 0.005345] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8) [ 0.005347] mce: CPU supports 9 MCE banks [ 0.005356] CPU0: Thermal monitoring enabled (TM1) [ 0.005363] process: using mwait in idle threads [ 0.005365] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8 [ 0.005366] Last level dTLB entries: 4KB 512, 2MB 32, 4MB 32, 1GB 0 [ 0.005664] Freeing SMP alternatives memory: 28K (ffffffff81ea7000 - ffffffff81eae000) [ 0.094707] ftrace: allocating 31332 entries in 123 pages [ 0.106297] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.145984] TSC deadline timer enabled [ 0.145986] smpboot: CPU0: Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz (family: 0x6, model: 0x2a, stepping: 0x7) [ 0.146002] Performance Events: PEBS fmt1+, 16-deep LBR, SandyBridge events, full-width counters, Intel PMU driver. [ 0.146017] ... version: 3 [ 0.146018] ... bit width: 48 [ 0.146018] ... generic registers: 8 [ 0.146019] ... value mask: 0000ffffffffffff [ 0.146020] ... max period: 0000ffffffffffff [ 0.146021] ... fixed-purpose events: 3 [ 0.146021] ... event mask: 00000007000000ff [ 0.146516] x86: Booting SMP configuration: [ 0.146518] .... node #0, CPUs: #1 [ 0.157682] microcode: CPU1 microcode updated early to revision 0x29, date = 2013-06-12 [ 0.159786] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. [ 0.159845] #2 [ 0.171107] microcode: CPU2 microcode updated early to revision 0x29, date = 2013-06-12 [ 0.173223] #3 [ 0.184487] microcode: CPU3 microcode updated early to revision 0x29, date = 2013-06-12 [ 0.186549] x86: Booted up 1 node, 4 CPUs [ 0.186552] smpboot: Total of 4 processors activated (26400.53 BogoMIPS) [ 0.188880] devtmpfs: initialized [ 0.190830] evm: security.selinux [ 0.190831] evm: security.SMACK64 [ 0.190832] evm: security.SMACK64EXEC [ 0.190833] evm: security.SMACK64TRANSMUTE [ 0.190833] evm: security.SMACK64MMAP [ 0.190834] evm: security.ima [ 0.190835] evm: security.capability [ 0.190887] PM: Registering ACPI NVS region [mem 0xbf1e0000-0xbf231fff] (335872 bytes) [ 0.190892] PM: Registering ACPI NVS region [mem 0xbf5a5000-0xbf5b5fff] (69632 bytes) [ 0.190893] PM: Registering ACPI NVS region [mem 0xbf5d7000-0xbf5e1fff] (45056 bytes) [ 0.190894] PM: Registering ACPI NVS region [mem 0xbf63e000-0xbf680fff] (274432 bytes) [ 0.190951] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.191006] pinctrl core: initialized pinctrl subsystem [ 0.191094] RTC time: 16:55:19, date: 11/20/15 [ 0.191173] NET: Registered protocol family 16 [ 0.202551] cpuidle: using governor ladder [ 0.214552] cpuidle: using governor menu [ 0.214557] PCCT header not found. [ 0.214656] ACPI: bus type PCI registered [ 0.214657] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.214709] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) [ 0.214711] PCI: not using MMCONFIG [ 0.214712] PCI: Using configuration type 1 for base access [ 0.214974] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. [ 0.214979] perf_event_intel: PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off [ 0.226842] ACPI: Added _OSI(Module Device) [ 0.226844] ACPI: Added _OSI(Processor Device) [ 0.226844] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.226845] ACPI: Added _OSI(Processor Aggregator Device) [ 0.228056] ACPI: Executed 1 blocks of module-level executable AML code [ 0.229478] ACPI: Dynamic OEM Table Load: [ 0.229482] ACPI: SSDT 0xFFFF880235510400 0003E0 (v01 AMI IST 00000001 MSFT 03000001) [ 0.229712] ACPI: Dynamic OEM Table Load: [ 0.229714] ACPI: SSDT 0xFFFF8802354C6400 000120 (v01 AMI CST 00000001 MSFT 03000001) [ 0.230154] ACPI : EC: EC started [ 0.230158] ACPI: Interpreter enabled [ 0.230164] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150930/hwxface-580) [ 0.230173] ACPI: (supports S0 S1 S3 S4 S5) [ 0.230174] ACPI: Using IOAPIC for interrupt routing [ 0.230192] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) [ 0.230228] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in ACPI motherboard resources [ 0.230234] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.230409] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored [ 0.234027] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.234031] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] [ 0.234119] acpi PNP0A08:00: _OSC: platform does not support [PCIeHotplug] [ 0.234199] acpi PNP0A08:00: _OSC: OS now controls [PME AER PCIeCapability] [ 0.234205] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge [ 0.234266] acpi PNP0A08:00: ignoring host bridge window [mem 0x000c8000-0x000dffff window] (conflicts with Video ROM [mem 0x000c0000-0x000cedff]) [ 0.234377] PCI host bridge to bus 0000:00 [ 0.234379] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 0.234381] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.234382] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 0.234383] pci_bus 0000:00: root bus resource [mem 0xc0000000-0xffffffff window] [ 0.234385] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.234391] pci 0000:00:00.0: [8086:0100] type 00 class 0x060000 [ 0.234452] pci 0000:00:01.0: [8086:0101] type 01 class 0x060400 [ 0.234476] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold [ 0.234501] pci 0000:00:01.0: System wakeup disabled by ACPI [ 0.234555] pci 0000:00:16.0: [8086:1c3a] type 00 class 0x078000 [ 0.234589] pci 0000:00:16.0: reg 0x10: [mem 0xfe729000-0xfe72900f 64bit] [ 0.234647] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold [ 0.234708] pci 0000:00:19.0: [8086:1503] type 00 class 0x020000 [ 0.234732] pci 0000:00:19.0: reg 0x10: [mem 0xfe700000-0xfe71ffff] [ 0.234740] pci 0000:00:19.0: reg 0x14: [mem 0xfe728000-0xfe728fff] [ 0.234748] pci 0000:00:19.0: reg 0x18: [io 0xf040-0xf05f] [ 0.234794] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold [ 0.234821] pci 0000:00:19.0: System wakeup disabled by ACPI [ 0.234852] pci 0000:00:1a.0: [8086:1c2d] type 00 class 0x0c0320 [ 0.234878] pci 0000:00:1a.0: reg 0x10: [mem 0xfe727000-0xfe7273ff] [ 0.234947] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold [ 0.234975] pci 0000:00:1a.0: System wakeup disabled by ACPI [ 0.235007] pci 0000:00:1b.0: [8086:1c20] type 00 class 0x040300 [ 0.235031] pci 0000:00:1b.0: reg 0x10: [mem 0xfe720000-0xfe723fff 64bit] [ 0.235088] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold [ 0.235145] pci 0000:00:1c.0: [8086:1c10] type 01 class 0x060400 [ 0.235215] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 0.235246] pci 0000:00:1c.0: System wakeup disabled by ACPI [ 0.235277] pci 0000:00:1c.2: [8086:1c14] type 01 class 0x060400 [ 0.235348] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold [ 0.235379] pci 0000:00:1c.2: System wakeup disabled by ACPI [ 0.235412] pci 0000:00:1c.6: [8086:244e] type 01 class 0x060401 [ 0.235482] pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold [ 0.235513] pci 0000:00:1c.6: System wakeup disabled by ACPI [ 0.235545] pci 0000:00:1d.0: [8086:1c26] type 00 class 0x0c0320 [ 0.235571] pci 0000:00:1d.0: reg 0x10: [mem 0xfe726000-0xfe7263ff] [ 0.235640] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 0.235668] pci 0000:00:1d.0: System wakeup disabled by ACPI [ 0.235700] pci 0000:00:1f.0: [8086:1c46] type 00 class 0x060100 [ 0.235844] pci 0000:00:1f.2: [8086:1c02] type 00 class 0x010601 [ 0.235866] pci 0000:00:1f.2: reg 0x10: [io 0xf090-0xf097] [ 0.235873] pci 0000:00:1f.2: reg 0x14: [io 0xf080-0xf083] [ 0.235880] pci 0000:00:1f.2: reg 0x18: [io 0xf070-0xf077] [ 0.235887] pci 0000:00:1f.2: reg 0x1c: [io 0xf060-0xf063] [ 0.235894] pci 0000:00:1f.2: reg 0x20: [io 0xf020-0xf03f] [ 0.235901] pci 0000:00:1f.2: reg 0x24: [mem 0xfe725000-0xfe7257ff] [ 0.235930] pci 0000:00:1f.2: PME# supported from D3hot [ 0.235981] pci 0000:00:1f.3: [8086:1c22] type 00 class 0x0c0500 [ 0.235996] pci 0000:00:1f.3: reg 0x10: [mem 0xfe724000-0xfe7240ff 64bit] [ 0.236016] pci 0000:00:1f.3: reg 0x20: [io 0xf000-0xf01f] [ 0.236099] pci 0000:01:00.0: [1002:7300] type 00 class 0x030000 [ 0.236118] pci 0000:01:00.0: reg 0x10: [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.236126] pci 0000:01:00.0: reg 0x18: [mem 0xd0000000-0xd01fffff 64bit pref] [ 0.236132] pci 0000:01:00.0: reg 0x20: [io 0xe000-0xe0ff] [ 0.236137] pci 0000:01:00.0: reg 0x24: [mem 0xfe600000-0xfe63ffff] [ 0.236142] pci 0000:01:00.0: reg 0x30: [mem 0xfe640000-0xfe65ffff pref] [ 0.236172] pci 0000:01:00.0: supports D1 D2 [ 0.236173] pci 0000:01:00.0: PME# supported from D1 D2 D3hot D3cold [ 0.236216] pci 0000:01:00.1: [1002:aae8] type 00 class 0x040300 [ 0.236235] pci 0000:01:00.1: reg 0x10: [mem 0xfe660000-0xfe663fff 64bit] [ 0.236278] pci 0000:01:00.1: supports D1 D2 [ 0.242581] pci 0000:00:01.0: PCI bridge to [bus 01] [ 0.242586] pci 0000:00:01.0: bridge window [io 0xe000-0xefff] [ 0.242589] pci 0000:00:01.0: bridge window [mem 0xfe600000-0xfe6fffff] [ 0.242594] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xd01fffff 64bit pref] [ 0.242666] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 0.242713] pci 0000:00:1c.2: PCI bridge to [bus 03] [ 0.242776] pci 0000:04:00.0: [1b21:1080] type 01 class 0x060401 [ 0.242888] pci 0000:04:00.0: System wakeup disabled by ACPI [ 0.242912] pci 0000:00:1c.6: PCI bridge to [bus 04-05] (subtractive decode) [ 0.242922] pci 0000:00:1c.6: bridge window [io 0x0000-0x0cf7 window] (subtractive decode) [ 0.242923] pci 0000:00:1c.6: bridge window [io 0x0d00-0xffff window] (subtractive decode) [ 0.242924] pci 0000:00:1c.6: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode) [ 0.242925] pci 0000:00:1c.6: bridge window [mem 0xc0000000-0xffffffff window] (subtractive decode) [ 0.243034] pci 0000:04:00.0: PCI bridge to [bus 05] (subtractive decode) [ 0.243056] pci 0000:04:00.0: bridge window [io 0x0000-0x0cf7 window] (subtractive decode) [ 0.243057] pci 0000:04:00.0: bridge window [io 0x0d00-0xffff window] (subtractive decode) [ 0.243058] pci 0000:04:00.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode) [ 0.243059] pci 0000:04:00.0: bridge window [mem 0xc0000000-0xffffffff window] (subtractive decode) [ 0.243407] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15) [ 0.243443] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15) [ 0.243477] ACPI: PCI Interrupt Link [LNKC] (IRQs *3 4 5 6 10 11 12 14 15) [ 0.243511] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 15) *0 [ 0.243545] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 *10 11 12 14 15) [ 0.243579] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 *5 6 7 10 11 12 14 15) [ 0.243613] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 *11 12 14 15) [ 0.243647] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 *7 10 11 12 14 15) [ 0.243706] ACPI : EC: GPE = 0x18, I/O: command/status = 0x66, data = 0x62 [ 0.243773] vgaarb: setting as boot device: PCI:0000:01:00.0 [ 0.243774] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none [ 0.243775] vgaarb: loaded [ 0.243776] vgaarb: bridge control possible 0000:01:00.0 [ 0.243941] SCSI subsystem initialized [ 0.243964] libata version 3.00 loaded. [ 0.243981] ACPI: bus type USB registered [ 0.243992] usbcore: registered new interface driver usbfs [ 0.243998] usbcore: registered new interface driver hub [ 0.244007] usbcore: registered new device driver usb [ 0.244095] PCI: Using ACPI for IRQ routing [ 0.245510] PCI: pci_cache_line_size set to 64 bytes [ 0.245546] e820: reserve RAM buffer [mem 0x0009d800-0x0009ffff] [ 0.245548] e820: reserve RAM buffer [mem 0xbf1e0000-0xbfffffff] [ 0.245549] e820: reserve RAM buffer [mem 0xbf5cf000-0xbfffffff] [ 0.245550] e820: reserve RAM buffer [mem 0xbf800000-0xbfffffff] [ 0.245551] e820: reserve RAM buffer [mem 0x23f800000-0x23fffffff] [ 0.245632] NetLabel: Initializing [ 0.245633] NetLabel: domain hash size = 128 [ 0.245634] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.245644] NetLabel: unlabeled traffic allowed by default [ 0.245698] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 0.245701] hpet0: 8 comparators, 64-bit 14.318180 MHz counter [ 0.247720] clocksource: Switched to clocksource hpet [ 0.251816] AppArmor: AppArmor Filesystem Enabled [ 0.251866] pnp: PnP ACPI init [ 0.251960] system 00:00: [mem 0xfed10000-0xfed19fff] has been reserved [ 0.251962] system 00:00: [mem 0xe0000000-0xe3ffffff] has been reserved [ 0.251963] system 00:00: [mem 0xfed90000-0xfed93fff] has been reserved [ 0.251965] system 00:00: [mem 0xfed20000-0xfed3ffff] has been reserved [ 0.251966] system 00:00: [mem 0xfee00000-0xfee0ffff] has been reserved [ 0.251969] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) [ 0.252030] system 00:01: [io 0x0290-0x029f] has been reserved [ 0.252032] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.252054] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.252084] system 00:03: [io 0x04d0-0x04d1] has been reserved [ 0.252086] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.252238] pnp 00:04: [dma 0 disabled] [ 0.252275] pnp 00:04: Plug and Play ACPI device, IDs PNP0501 (active) [ 0.252370] system 00:05: [io 0x0400-0x0453] could not be reserved [ 0.252372] system 00:05: [io 0x0458-0x047f] has been reserved [ 0.252373] system 00:05: [io 0x0500-0x057f] has been reserved [ 0.252374] system 00:05: [mem 0xfed1c000-0xfed1ffff] has been reserved [ 0.252376] system 00:05: [mem 0xfec00000-0xfecfffff] could not be reserved [ 0.252377] system 00:05: [mem 0xfed08000-0xfed08fff] has been reserved [ 0.252379] system 00:05: [mem 0xff000000-0xffffffff] has been reserved [ 0.252381] system 00:05: Plug and Play ACPI device, IDs PNP0c01 (active) [ 0.252419] system 00:06: [io 0x0454-0x0457] has been reserved [ 0.252421] system 00:06: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) [ 0.252559] pnp: PnP ACPI: found 7 devices [ 0.258437] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.258479] pci 0000:00:01.0: PCI bridge to [bus 01] [ 0.258481] pci 0000:00:01.0: bridge window [io 0xe000-0xefff] [ 0.258483] pci 0000:00:01.0: bridge window [mem 0xfe600000-0xfe6fffff] [ 0.258485] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xd01fffff 64bit pref] [ 0.258488] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 0.258498] pci 0000:00:1c.2: PCI bridge to [bus 03] [ 0.258508] pci 0000:04:00.0: PCI bridge to [bus 05] [ 0.258527] pci 0000:00:1c.6: PCI bridge to [bus 04-05] [ 0.258538] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] [ 0.258539] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] [ 0.258541] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.258542] pci_bus 0000:00: resource 7 [mem 0xc0000000-0xffffffff window] [ 0.258543] pci_bus 0000:01: resource 0 [io 0xe000-0xefff] [ 0.258545] pci_bus 0000:01: resource 1 [mem 0xfe600000-0xfe6fffff] [ 0.258546] pci_bus 0000:01: resource 2 [mem 0xc0000000-0xd01fffff 64bit pref] [ 0.258547] pci_bus 0000:04: resource 4 [io 0x0000-0x0cf7 window] [ 0.258549] pci_bus 0000:04: resource 5 [io 0x0d00-0xffff window] [ 0.258550] pci_bus 0000:04: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.258551] pci_bus 0000:04: resource 7 [mem 0xc0000000-0xffffffff window] [ 0.258552] pci_bus 0000:05: resource 4 [io 0x0000-0x0cf7 window] [ 0.258554] pci_bus 0000:05: resource 5 [io 0x0d00-0xffff window] [ 0.258555] pci_bus 0000:05: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.258556] pci_bus 0000:05: resource 7 [mem 0xc0000000-0xffffffff window] [ 0.258580] NET: Registered protocol family 2 [ 0.258695] TCP established hash table entries: 65536 (order: 7, 524288 bytes) [ 0.258805] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 0.258894] TCP: Hash tables configured (established 65536 bind 65536) [ 0.258915] UDP hash table entries: 4096 (order: 5, 131072 bytes) [ 0.258937] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes) [ 0.258976] NET: Registered protocol family 1 [ 0.511752] pci 0000:01:00.0: Video device with shadowed ROM [ 0.511761] PCI: CLS 64 bytes, default 64 [ 0.511823] Trying to unpack rootfs image as initramfs... [ 0.916713] Freeing initrd memory: 34324K (ffff880033ce6000 - ffff880035e6b000) [ 0.916733] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.916735] software IO TLB [mem 0xbb1e0000-0xbf1e0000] (64MB) mapped at [ffff8800bb1e0000-ffff8800bf1dffff] [ 0.916793] RAPL PMU detected, API unit is 2^-32 Joules, 3 fixed counters 163840 ms ovfl timer [ 0.916794] hw unit of domain pp0-core 2^-16 Joules [ 0.916795] hw unit of domain package 2^-16 Joules [ 0.916796] hw unit of domain pp1-gpu 2^-16 Joules [ 0.916909] Scanning for low memory corruption every 60 seconds [ 0.917133] futex hash table entries: 1024 (order: 4, 65536 bytes) [ 0.917153] audit: initializing netlink subsys (disabled) [ 0.917164] audit: type=2000 audit(1448038519.828:1): initialized [ 0.917450] Initialise system trusted keyring [ 0.917501] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 0.918566] zbud: loaded [ 0.918712] VFS: Disk quotas dquot_6.6.0 [ 0.918736] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.919077] fuse init (API version 7.23) [ 0.919169] Key type big_key registered [ 0.919449] Key type asymmetric registered [ 0.919451] Asymmetric key parser 'x509' registered [ 0.919477] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) [ 0.919501] io scheduler noop registered [ 0.919504] io scheduler deadline registered (default) [ 0.919526] io scheduler cfq registered [ 0.919978] pcieport 0000:00:01.0: Signaling PME through PCIe PME interrupt [ 0.919980] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt [ 0.919981] pci 0000:01:00.1: Signaling PME through PCIe PME interrupt [ 0.919983] pcie_pme 0000:00:01.0:pcie01: service driver pcie_pme loaded [ 0.920001] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt [ 0.920005] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded [ 0.920023] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt [ 0.920026] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded [ 0.920030] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 0.920035] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 [ 0.920054] vesafb: mode is 3840x2160x16, linelength=7680, pages=0 [ 0.920055] vesafb: scrolling: redraw [ 0.920056] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0 [ 0.920064] vesafb: framebuffer at 0xc0000000, mapped to 0xffffc90001000000, using 16256k, total 16256k [ 1.090979] Console: switching to colour frame buffer device 480x135 [ 1.261773] fb0: VESA VGA frame buffer device [ 1.261785] intel_idle: MWAIT substates: 0x1120 [ 1.261786] intel_idle: v0.4 model 0x2A [ 1.261787] intel_idle: lapic_timer_reliable_states 0xffffffff [ 1.261932] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 1.261935] ACPI: Power Button [PWRB] [ 1.261961] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 1.261963] ACPI: Power Button [PWRF] [ 1.262400] GHES: HEST is not enabled! [ 1.262475] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled [ 1.282878] 00:04: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A [ 1.284128] Linux agpgart interface v0.103 [ 1.286328] brd: module loaded [ 1.287218] loop: module loaded [ 1.287394] libphy: Fixed MDIO Bus: probed [ 1.287396] tun: Universal TUN/TAP device driver, 1.6 [ 1.287397] tun: (C) 1999-2004 Max Krasnyansky [ 1.287427] PPP generic driver version 2.4.2 [ 1.287468] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.287472] ehci-pci: EHCI PCI platform driver [ 1.287535] ehci-pci 0000:00:1a.0: EHCI Host Controller [ 1.287540] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1 [ 1.287550] ehci-pci 0000:00:1a.0: debug port 2 [ 1.291453] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported [ 1.291461] ehci-pci 0000:00:1a.0: irq 23, io mem 0xfe727000 [ 1.299717] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00 [ 1.299741] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.299742] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.299744] usb usb1: Product: EHCI Host Controller [ 1.299745] usb usb1: Manufacturer: Linux 4.3.999powerplay+ ehci_hcd [ 1.299746] usb usb1: SerialNumber: 0000:00:1a.0 [ 1.299904] hub 1-0:1.0: USB hub found [ 1.299910] hub 1-0:1.0: 2 ports detected [ 1.300037] ehci-pci 0000:00:1d.0: EHCI Host Controller [ 1.300040] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2 [ 1.300050] ehci-pci 0000:00:1d.0: debug port 2 [ 1.303934] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported [ 1.303938] ehci-pci 0000:00:1d.0: irq 23, io mem 0xfe726000 [ 1.315768] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00 [ 1.315826] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.315828] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.315829] usb usb2: Product: EHCI Host Controller [ 1.315830] usb usb2: Manufacturer: Linux 4.3.999powerplay+ ehci_hcd [ 1.315831] usb usb2: SerialNumber: 0000:00:1d.0 [ 1.315972] hub 2-0:1.0: USB hub found [ 1.315978] hub 2-0:1.0: 2 ports detected [ 1.316058] ehci-platform: EHCI generic platform driver [ 1.316067] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.316071] ohci-pci: OHCI PCI platform driver [ 1.316080] ohci-platform: OHCI generic platform driver [ 1.316086] uhci_hcd: USB Universal Host Controller Interface driver [ 1.316126] i8042: PNP: No PS/2 controller found. Probing ports directly. [ 1.318688] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.318693] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.318871] mousedev: PS/2 mouse device common for all mice [ 1.318978] rtc_cmos 00:02: RTC can wake from S4 [ 1.319094] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0 [ 1.319118] rtc_cmos 00:02: alarms up to one month, y3k, 114 bytes nvram, hpet irqs [ 1.319125] i2c /dev entries driver [ 1.319158] device-mapper: uevent: version 1.0.3 [ 1.319206] device-mapper: ioctl: 4.34.0-ioctl (2015-10-28) initialised: dm-devel@redhat.com [ 1.319216] Intel P-state driver initializing. [ 1.319724] ledtrig-cpu: registered to indicate activity on CPUs [ 1.320567] NET: Registered protocol family 10 [ 1.320876] NET: Registered protocol family 17 [ 1.320892] Key type dns_resolver registered [ 1.321405] registered taskstats version 1 [ 1.321435] Loading compiled-in X.509 certificates [ 1.321444] Problem loading in-kernel X.509 certificate (-74) [ 1.321801] zswap: loaded using pool lzo/zbud [ 1.324229] Key type trusted registered [ 1.326744] Key type encrypted registered [ 1.326748] AppArmor: AppArmor sha1 policy hashing enabled [ 1.326750] ima: No TPM chip found, activating TPM-bypass! [ 1.326763] evm: HMAC attrs: 0x1 [ 1.326977] Magic number: 7:123:945 [ 1.327000] tty tty2: hash matches [ 1.327026] processor cpu0: hash matches [ 1.327103] rtc_cmos 00:02: setting system clock to 2015-11-20 16:55:20 UTC (1448038520) [ 1.327292] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 1.327293] EDD information not available. [ 1.327332] PM: Hibernation image not present or could not be loaded. [ 1.328058] Freeing unused kernel memory: 1452K (ffffffff81d3c000 - ffffffff81ea7000) [ 1.328059] Write protecting the kernel read-only data: 12288k [ 1.328334] Freeing unused kernel memory: 212K (ffff8800017cb000 - ffff880001800000) [ 1.328615] Freeing unused kernel memory: 192K (ffff880001bd0000 - ffff880001c00000) [ 1.334966] random: systemd-udevd urandom read with 2 bits of entropy available [ 1.349111] fjes: module verification failed: signature and/or required key missing - tainting kernel [ 1.349237] FUJITSU Extended Socket Network Device Driver - version 1.0 - Copyright (c) 2015 FUJITSU LIMITED [ 1.352744] wmi: Mapper loaded [ 1.353319] pps_core: LinuxPPS API ver. 1 registered [ 1.353320] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti [ 1.353541] PTP clock support registered [ 1.355513] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 1.355514] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 1.355608] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode [ 1.356212] [drm] Initialized drm 1.1.0 20060810 [ 1.368950] [drm] amdgpu kernel modesetting enabled. [ 1.369703] AMD IOMMUv2 driver by Joerg Roedel [ 1.369705] AMD IOMMUv2 functionality not available on this system [ 1.370956] CRAT table not found [ 1.370957] Finished initializing topology ret=0 [ 1.370984] kfd kfd: Initialized module [ 1.371115] checking generic (c0000000 fe0000) vs hw (c0000000 10000000) [ 1.371116] fb: switching to amdgpudrmfb from VESA VGA [ 1.371132] Console: switching to colour dummy device 80x25 [ 1.371271] [drm] initializing kernel modesetting (FIJI 0x1002:0x7300 0x174B:0xE329 0xCB). [ 1.371276] [drm] register mmio base: 0xFE600000 [ 1.371276] [drm] register mmio size: 262144 [ 1.371278] [drm] doorbell mmio base: 0xD0000000 [ 1.371279] [drm] doorbell mmio size: 2097152 [ 1.371282] [drm] probing gen 2 caps for device 8086:101 = 2212102/0 [ 1.371284] [drm] probing mlw for device 8086:101 = 2212102 [ 1.371295] amdgpu 0000:01:00.0: Invalid ROM contents [ 1.371308] ATOM BIOS: 113 [ 1.371313] [drm] Changing default dispclk from 500Mhz to 600Mhz [ 1.371574] amdgpu 0000:01:00.0: VRAM: 4096M 0x0000000000000000 - 0x00000000FFFFFFFF (4096M used) [ 1.371576] amdgpu 0000:01:00.0: GTT: 4096M 0x0000000100000000 - 0x00000001FFFFFFFF [ 1.371577] [drm] Detected VRAM RAM=4096M, BAR=256M [ 1.371577] [drm] RAM width 512bits DDR [ 1.371654] [TTM] Zone kernel: Available graphics memory: 4077294 kiB [ 1.371655] [TTM] Zone dma32: Available graphics memory: 2097152 kiB [ 1.371656] [TTM] Initializing pool allocator [ 1.371658] [TTM] Initializing DMA pool allocator [ 1.371670] [drm] amdgpu: 4096M of VRAM memory ready [ 1.371671] [drm] amdgpu: 4096M of GTT memory ready. [ 1.371677] [drm] GART: num cpu pages 1048576, num gpu pages 1048576 [ 1.374854] [drm] PCIE GART of 4096M enabled (table at 0x0000000000040000). [ 1.374864] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.374865] [drm] Driver supports precise vblank timestamp query. [ 1.374919] amdgpu 0000:01:00.0: amdgpu: using MSI. [ 1.374942] [drm] amdgpu: irq initialized. [ 1.374946] Can't find requested voltage id in vdd_dep_on_sclk table! [ 1.382424] [drm] AMDGPU Display Connectors [ 1.382425] [drm] Connector 0: [ 1.382426] [drm] DP-1 [ 1.382427] [drm] HPD5 [ 1.382428] [drm] DDC: 0x4868 0x4868 0x4869 0x4869 0x486a 0x486a 0x486b 0x486b [ 1.382428] [drm] Encoders: [ 1.382429] [drm] DFP1: INTERNAL_UNIPHY1 [ 1.382429] [drm] Connector 1: [ 1.382430] [drm] DP-2 [ 1.382430] [drm] HPD4 [ 1.382431] [drm] DDC: 0x486c 0x486c 0x486d 0x486d 0x486e 0x486e 0x486f 0x486f [ 1.382431] [drm] Encoders: [ 1.382432] [drm] DFP2: INTERNAL_UNIPHY1 [ 1.382432] [drm] Connector 2: [ 1.382433] [drm] DP-3 [ 1.382433] [drm] HPD3 [ 1.382434] [drm] DDC: 0x4870 0x4870 0x4871 0x4871 0x4872 0x4872 0x4873 0x4873 [ 1.382435] [drm] Encoders: [ 1.382435] [drm] DFP3: INTERNAL_UNIPHY [ 1.382436] [drm] Connector 3: [ 1.382436] [drm] HDMI-A-1 [ 1.382437] [drm] HPD2 [ 1.382437] [drm] DDC: 0x487c 0x487c 0x487d 0x487d 0x487e 0x487e 0x487f 0x487f [ 1.382438] [drm] Encoders: [ 1.382438] [drm] DFP4: INTERNAL_UNIPHY2 [ 1.382590] amdgpu 0000:01:00.0: fence driver on ring 0 use gpu addr 0x0000000100000008, cpu addr 0xffff8800352c9008 [ 1.382693] amdgpu 0000:01:00.0: fence driver on ring 1 use gpu addr 0x0000000100000018, cpu addr 0xffff8800352c9018 [ 1.382796] amdgpu 0000:01:00.0: fence driver on ring 2 use gpu addr 0x0000000100000028, cpu addr 0xffff8800352c9028 [ 1.382898] amdgpu 0000:01:00.0: fence driver on ring 3 use gpu addr 0x0000000100000038, cpu addr 0xffff8800352c9038 [ 1.382998] amdgpu 0000:01:00.0: fence driver on ring 4 use gpu addr 0x0000000100000048, cpu addr 0xffff8800352c9048 [ 1.383105] amdgpu 0000:01:00.0: fence driver on ring 5 use gpu addr 0x0000000100000058, cpu addr 0xffff8800352c9058 [ 1.383209] amdgpu 0000:01:00.0: fence driver on ring 6 use gpu addr 0x0000000100000068, cpu addr 0xffff8800352c9068 [ 1.383311] amdgpu 0000:01:00.0: fence driver on ring 7 use gpu addr 0x0000000100000078, cpu addr 0xffff8800352c9078 [ 1.383417] amdgpu 0000:01:00.0: fence driver on ring 8 use gpu addr 0x0000000100000088, cpu addr 0xffff8800352c9088 [ 1.383556] amdgpu 0000:01:00.0: fence driver on ring 9 use gpu addr 0x0000000100000098, cpu addr 0xffff8800352c9098 [ 1.383587] amdgpu 0000:01:00.0: fence driver on ring 10 use gpu addr 0x00000001000000a8, cpu addr 0xffff8800352c90a8 [ 1.383679] [drm] Found UVD firmware Version: 1.52 Family ID: 10 [ 1.384155] amdgpu 0000:01:00.0: fence driver on ring 11 use gpu addr 0x000000000088f7b0, cpu addr 0xffffc90001c4e7b0 [ 1.384291] [drm] Found VCE firmware Version: 48.0 Binary ID: 3 [ 1.384338] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000001000000c8, cpu addr 0xffff8800352c90c8 [ 1.384343] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x00000001000000d8, cpu addr 0xffff8800352c90d8 [ 1.425675] [ powerplay ] Invalid Parameter! [ 1.427002] [drm] ring test on 0 succeeded in 12 usecs [ 1.427179] [drm] ring test on 1 succeeded in 21 usecs [ 1.427214] [drm] ring test on 2 succeeded in 19 usecs [ 1.427223] [drm] ring test on 3 succeeded in 4 usecs [ 1.427230] [drm] ring test on 4 succeeded in 3 usecs [ 1.427236] [drm] ring test on 5 succeeded in 3 usecs [ 1.427243] [drm] ring test on 6 succeeded in 3 usecs [ 1.427250] [drm] ring test on 7 succeeded in 3 usecs [ 1.427256] [drm] ring test on 8 succeeded in 3 usecs [ 1.427281] [drm] ring test on 9 succeeded in 6 usecs [ 1.427293] [drm] ring test on 10 succeeded in 6 usecs [ 1.453108] [drm] ring test on 11 succeeded in 2 usecs [ 1.453109] [drm] UVD initialized successfully. [ 1.562294] [drm] ring test on 12 succeeded in 21 usecs [ 1.562306] [drm] ring test on 13 succeeded in 4 usecs [ 1.562306] [drm] VCE initialized successfully. [ 1.613569] usb 1-1: new high-speed USB device number 2 using ehci-pci [ 1.614772] [drm] fb mappable at 0xC0BAA000 [ 1.614773] [drm] vram apper at 0xC0000000 [ 1.614774] [drm] size 33177600 [ 1.614774] [drm] fb depth is 24 [ 1.614775] [drm] pitch is 15360 [ 1.614866] fbcon: amdgpudrmfb (fb0) is primary device [ 1.616163] e1000e 0000:00:19.0 eth0: registered PHC clock [ 1.616164] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 14:da:e9:be:0b:a6 [ 1.616165] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection [ 1.616208] e1000e 0000:00:19.0 eth0: MAC: 10, PHY: 11, PBA No: FFFFFF-0FF [ 1.616294] ahci 0000:00:1f.2: version 3.0 [ 1.616707] e1000e 0000:00:19.0 eth2: renamed from eth0 [ 1.627739] usb 2-1: new high-speed USB device number 2 using ehci-pci [ 1.631824] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x1d impl SATA mode [ 1.631825] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst [ 1.656185] scsi host0: ahci [ 1.656308] scsi host1: ahci [ 1.656450] scsi host2: ahci [ 1.656541] scsi host3: ahci [ 1.656668] scsi host4: ahci [ 1.656791] scsi host5: ahci [ 1.656817] ata1: SATA max UDMA/133 abar m2048@0xfe725000 port 0xfe725100 irq 29 [ 1.656817] ata2: DUMMY [ 1.656819] ata3: SATA max UDMA/133 abar m2048@0xfe725000 port 0xfe725200 irq 29 [ 1.656821] ata4: SATA max UDMA/133 abar m2048@0xfe725000 port 0xfe725280 irq 29 [ 1.656822] ata5: SATA max UDMA/133 abar m2048@0xfe725000 port 0xfe725300 irq 29 [ 1.656822] ata6: DUMMY [ 1.744048] usb 1-1: New USB device found, idVendor=8087, idProduct=0024 [ 1.744049] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 1.744325] hub 1-1:1.0: USB hub found [ 1.744400] hub 1-1:1.0: 6 ports detected [ 1.760173] usb 2-1: New USB device found, idVendor=8087, idProduct=0024 [ 1.760174] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 1.760422] hub 2-1:1.0: USB hub found [ 1.760532] hub 2-1:1.0: 8 ports detected [ 1.772510] Console: switching to colour frame buffer device 480x135 [ 1.784812] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device [ 1.800090] [drm] ib test on ring 0 succeeded in 0 usecs [ 1.801006] [drm] ib test on ring 1 succeeded in 0 usecs [ 1.801511] [drm] ib test on ring 2 succeeded in 0 usecs [ 1.802172] [drm] ib test on ring 3 succeeded in 0 usecs [ 1.803033] [drm] ib test on ring 4 succeeded in 0 usecs [ 1.803538] [drm] ib test on ring 5 succeeded in 0 usecs [ 1.804199] [drm] ib test on ring 6 succeeded in 0 usecs [ 1.804861] [drm] ib test on ring 7 succeeded in 0 usecs [ 1.805685] [drm] ib test on ring 8 succeeded in 0 usecs [ 1.805755] [drm] ib test on ring 9 succeeded in 0 usecs [ 1.805838] [drm] ib test on ring 10 succeeded in 0 usecs [ 1.807021] [drm] ib test on ring 11 succeeded [ 1.807231] [drm] ib test on ring 12 succeeded [ 1.807676] [drm] Initialized amdgpu 3.1.0 20150101 for 0000:01:00.0 on minor 0 [ 1.915768] tsc: Refined TSC clocksource calibration: 3300.023 MHz [ 1.915774] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x2f91626a655, max_idle_ns: 440795305688 ns [ 1.975761] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 1.975787] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 1.975811] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 1.975834] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [ 1.976246] ata4.00: ATA-7: SAMSUNG HD753LJ, 1AA01104, max UDMA7 [ 1.976250] ata4.00: 1465149168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA [ 1.976427] ata5.00: ATAPI: TSSTcorp CDDVDW SH-S223B, SB02, max UDMA/100 [ 1.976734] ata4.00: configured for UDMA/133 [ 1.977081] ata5.00: configured for UDMA/100 [ 1.977527] ata1.00: ATA-9: INTEL SSDSC2CT180A3, 300i, max UDMA/133 [ 1.977528] ata1.00: 351651888 sectors, multi 16: LBA48 NCQ (depth 31/32), AA [ 1.982332] ata3.00: ATA-7: SAMSUNG HD753LJ, 1AA01118, max UDMA7 [ 1.982336] ata3.00: 1465149168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA [ 1.987444] ata1.00: configured for UDMA/133 [ 1.987778] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2CT18 300i PQ: 0 ANSI: 5 [ 1.988017] sd 0:0:0:0: [sda] 351651888 512-byte logical blocks: (180 GB/167 GiB) [ 1.988049] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 1.988227] sd 0:0:0:0: [sda] Write Protect is off [ 1.988229] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 1.988257] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.988706] sda: sda1 sda2 sda3 sda4 [ 1.988799] ata3.00: configured for UDMA/133 [ 1.988935] sd 0:0:0:0: [sda] Attached SCSI disk [ 1.989065] scsi 2:0:0:0: Direct-Access ATA SAMSUNG HD753LJ 1118 PQ: 0 ANSI: 5 [ 1.989153] sd 2:0:0:0: [sdb] 1465149168 512-byte logical blocks: (750 GB/698 GiB) [ 1.989176] sd 2:0:0:0: Attached scsi generic sg1 type 0 [ 1.989202] sd 2:0:0:0: [sdb] Write Protect is off [ 1.989204] sd 2:0:0:0: [sdb] Mode Sense: 00 3a 00 00 [ 1.989228] sd 2:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.989263] scsi 3:0:0:0: Direct-Access ATA SAMSUNG HD753LJ 1104 PQ: 0 ANSI: 5 [ 1.989359] sd 3:0:0:0: [sdc] 1465149168 512-byte logical blocks: (750 GB/698 GiB) [ 1.989370] sd 3:0:0:0: Attached scsi generic sg2 type 0 [ 1.989387] sd 3:0:0:0: [sdc] Write Protect is off [ 1.989389] sd 3:0:0:0: [sdc] Mode Sense: 00 3a 00 00 [ 1.989408] sd 3:0:0:0: [sdc] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.989921] scsi 4:0:0:0: CD-ROM TSSTcorp CDDVDW SH-S223B SB02 PQ: 0 ANSI: 5 [ 1.998575] sdb: sdb1 [ 1.998760] sd 2:0:0:0: [sdb] Attached SCSI disk [ 2.009711] sdc: sdc3 < sdc5 > [ 2.009828] sr 4:0:0:0: [sr0] scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray [ 2.009830] cdrom: Uniform CD-ROM driver Revision: 3.20 [ 2.009970] sr 4:0:0:0: Attached scsi CD-ROM sr0 [ 2.010007] sr 4:0:0:0: Attached scsi generic sg3 type 5 [ 2.010010] sd 3:0:0:0: [sdc] Attached SCSI disk [ 2.031715] usb 2-1.1: new full-speed USB device number 3 using ehci-pci [ 2.125873] usb 2-1.1: New USB device found, idVendor=046d, idProduct=c223 [ 2.125878] usb 2-1.1: New USB device strings: Mfr=0, Product=2, SerialNumber=0 [ 2.125881] usb 2-1.1: Product: G15 Keyboard Hub [ 2.126255] hub 2-1.1:1.0: USB hub found [ 2.126606] hub 2-1.1:1.0: 4 ports detected [ 2.203725] usb 2-1.2: new high-speed USB device number 4 using ehci-pci [ 2.399725] usb 2-1.1.1: new low-speed USB device number 5 using ehci-pci [ 2.498629] usb 2-1.1.1: New USB device found, idVendor=046d, idProduct=c226 [ 2.498632] usb 2-1.1.1: New USB device strings: Mfr=0, Product=2, SerialNumber=0 [ 2.498633] usb 2-1.1.1: Product: G15 Gaming Keyboard [ 2.500906] hidraw: raw HID events driver (C) Jiri Kosina [ 2.508190] usbcore: registered new interface driver usbhid [ 2.508192] usbhid: USB HID core driver [ 2.508786] input: G15 Gaming Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1.1/2-1.1.1:1.0/0003:046D:C226.0001/input/input5 [ 2.519694] raid6: sse2x1 gen() 11177 MB/s [ 2.563889] hid-generic 0003:046D:C226.0001: input,hidraw0: USB HID v1.10 Keyboard [G15 Gaming Keyboard] on usb-0000:00:1d.0-1.1.1/input0 [ 2.566154] input: G15 Gaming Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1.1/2-1.1.1:1.1/0003:046D:C226.0002/input/input6 [ 2.571726] usb 2-1.1.4: new full-speed USB device number 6 using ehci-pci [ 2.587691] raid6: sse2x1 xor() 8746 MB/s [ 2.619987] hid-generic 0003:046D:C226.0002: input,hiddev0,hidraw1: USB HID v1.10 Device [G15 Gaming Keyboard] on usb-0000:00:1d.0-1.1.1/input1 [ 2.655692] raid6: sse2x2 gen() 13920 MB/s [ 2.667248] usb 2-1.1.4: New USB device found, idVendor=046d, idProduct=c227 [ 2.667250] usb 2-1.1.4: New USB device strings: Mfr=0, Product=2, SerialNumber=0 [ 2.667251] usb 2-1.1.4: Product: G15 GamePanel LCD [ 2.685914] input: G15 GamePanel LCD as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1.4/2-1.1.4:1.0/0003:046D:C227.0003/input/input7 [ 2.723691] raid6: sse2x2 xor() 10170 MB/s [ 2.739953] hid-generic 0003:046D:C227.0003: input,hiddev0,hidraw2: USB HID v1.11 Keypad [G15 GamePanel LCD] on usb-0000:00:1d.0-1.1.4/input0 [ 2.791692] raid6: sse2x4 gen() 16153 MB/s [ 2.859689] raid6: sse2x4 xor() 11958 MB/s [ 2.859690] raid6: using algorithm sse2x4 gen() 16153 MB/s [ 2.859691] raid6: .... xor() 11958 MB/s, rmw enabled [ 2.859692] raid6: using ssse3x2 recovery algorithm [ 2.860056] xor: automatically using best checksumming function: [ 2.864244] usb 2-1.2: New USB device found, idVendor=046d, idProduct=0808 [ 2.864246] usb 2-1.2: New USB device strings: Mfr=0, Product=0, SerialNumber=2 [ 2.864247] usb 2-1.2: SerialNumber: 267DCB60 [ 2.899713] avx : 31564.000 MB/sec [ 2.908596] Btrfs loaded [ 2.915795] clocksource: Switched to clocksource tsc [ 2.935691] usb 2-1.7: new full-speed USB device number 7 using ehci-pci [ 2.977715] EXT4-fs (sda4): mounted filesystem with ordered data mode. Opts: (null) [ 3.028091] usb 2-1.7: New USB device found, idVendor=0cf3, idProduct=3000 [ 3.028093] usb 2-1.7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 3.052173] systemd[1]: RTC configured in localtime, applying delta of 60 minutes to system time. [ 3.075143] systemd[1]: Failed to insert module 'kdbus': Function not implemented [ 3.080963] systemd[1]: systemd 225 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID -ELFUTILS +KMOD -IDN) [ 3.081044] systemd[1]: Detected architecture x86-64. [ 3.081254] systemd[1]: Set hostname to . [ 3.099727] usb 2-1.1.3: new full-speed USB device number 8 using ehci-pci [ 3.196112] usb 2-1.1.3: New USB device found, idVendor=1532, idProduct=0016 [ 3.196114] usb 2-1.1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 3.196115] usb 2-1.1.3: Product: Razer DeathAdder [ 3.196116] usb 2-1.1.3: Manufacturer: Razer [ 3.205724] input: Razer Razer DeathAdder as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1.3/2-1.1.3:1.0/0003:1532:0016.0004/input/input8 [ 3.205916] hid-generic 0003:1532:0016.0004: input,hidraw3: USB HID v1.11 Mouse [Razer Razer DeathAdder] on usb-0000:00:1d.0-1.1.3/input0 [ 3.218402] systemd[1]: Reached target Swap. [ 3.218442] systemd[1]: Created slice Root Slice. [ 3.218490] systemd[1]: Created slice System Slice. [ 3.218515] systemd[1]: Listening on udev Control Socket. [ 3.218531] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe. [ 3.218537] systemd[1]: Reached target User and Group Name Lookups. [ 3.218548] systemd[1]: Listening on fsck to fsckd communication Socket. [ 3.218553] systemd[1]: Reached target Remote File Systems (Pre). [ 3.218592] systemd[1]: Listening on Journal Audit Socket. [ 3.218605] systemd[1]: Listening on LVM2 poll daemon socket. [ 3.218610] systemd[1]: Reached target Encrypted Volumes. [ 3.218648] systemd[1]: Created slice User and Session Slice. [ 3.218661] systemd[1]: Listening on LVM2 metadata daemon socket. [ 3.218704] systemd[1]: Created slice system-getty.slice. [ 3.218717] systemd[1]: Listening on udev Kernel Socket. [ 3.218737] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ 3.218758] systemd[1]: Listening on Journal Socket. [ 3.227843] systemd[1]: Started Braille Device Support. [ 3.228242] systemd[1]: Mounting POSIX Message Queue File System... [ 3.228589] systemd[1]: Mounting Huge Pages File System... [ 3.228885] systemd[1]: Mounting Debug File System... [ 3.229203] systemd[1]: Starting Create list of required static device nodes for the current kernel... [ 3.229496] systemd[1]: Starting udev Coldplug all Devices... [ 3.229792] systemd[1]: Starting Uncomplicated firewall... [ 3.229815] systemd[1]: Reached target Slices. [ 3.229892] systemd[1]: Created slice system-systemd\x2dfsck.slice. [ 3.230188] systemd[1]: Started Read required files in advance. [ 3.233510] systemd[1]: Starting Load Kernel Modules... [ 3.233607] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ 3.237004] systemd[1]: Starting Increase datagram queue length... [ 3.237039] systemd[1]: Listening on Device-mapper event daemon FIFOs. [ 3.237314] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling... [ 3.237594] systemd[1]: Starting Setup Virtual Console... [ 3.237877] systemd[1]: Starting Remount Root and Kernel File Systems... [ 3.237906] systemd[1]: Listening on Journal Socket (/dev/log). [ 3.238464] systemd[1]: Started Create list of required static device nodes for the current kernel. [ 3.238607] systemd[1]: Started Uncomplicated firewall. [ 3.240396] systemd[1]: Mounted Debug File System. [ 3.240441] systemd[1]: Mounted POSIX Message Queue File System. [ 3.240892] systemd[1]: Mounted Huge Pages File System. [ 3.241251] systemd[1]: Started Increase datagram queue length. [ 3.242475] EXT4-fs (sda4): re-mounted. Opts: errors=remount-ro,barrier=0 [ 3.243184] systemd[1]: Started Setup Virtual Console. [ 3.243323] systemd[1]: Started Remount Root and Kernel File Systems. [ 3.247711] lp: driver loaded but no devices found [ 3.252216] ppdev: user-space parallel port driver [ 3.255487] systemd[1]: ureadahead.service: Main process exited, code=exited, status=5/NOTINSTALLED [ 3.255658] systemd[1]: ureadahead.service: Unit entered failed state. [ 3.255672] systemd[1]: ureadahead.service: Failed with result 'exit-code'. [ 3.260256] systemd[1]: Started Load Kernel Modules. [ 3.262906] systemd[1]: Mounting FUSE Control File System... [ 3.263226] systemd[1]: Starting Apply Kernel Variables... [ 3.263490] systemd[1]: Started LVM2 metadata daemon. [ 3.265105] systemd[1]: Starting Load/Save Random Seed... [ 3.265135] systemd[1]: Listening on Syslog Socket. [ 3.265438] systemd[1]: Starting Journal Service... [ 3.265775] systemd[1]: Starting Create Static Device Nodes in /dev... [ 3.266484] systemd[1]: Mounted FUSE Control File System. [ 3.267192] systemd[1]: Started udev Coldplug all Devices. [ 3.272074] random: nonblocking pool is initialized [ 3.274310] systemd[1]: Started Load/Save Random Seed. [ 3.276352] systemd[1]: Started Apply Kernel Variables. [ 3.280366] systemd[1]: Started Create Static Device Nodes in /dev. [ 3.295871] systemd[1]: Starting udev Kernel Device Manager... [ 3.295885] systemd[1]: Reached target Local File Systems (Pre). [ 3.296507] systemd[1]: Started Journal Service. [ 3.301204] systemd-journald[363]: Received request to flush runtime journal from PID 1 [ 3.373258] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 3.373474] ACPI Warning: SystemIO range 0x0000000000000540-0x000000000000054F conflicts with OpRegion 0x0000000000000500-0x000000000000057F (\_SB_.PCI0.SBRG.GPBX) (20150930/utaddress-254) [ 3.373477] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.373478] ACPI Warning: SystemIO range 0x0000000000000530-0x000000000000053F conflicts with OpRegion 0x0000000000000500-0x000000000000057F (\_SB_.PCI0.SBRG.GPBX) (20150930/utaddress-254) [ 3.373480] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.373481] ACPI Warning: SystemIO range 0x0000000000000500-0x000000000000052F conflicts with OpRegion 0x0000000000000500-0x000000000000057F (\_SB_.PCI0.SBRG.GPBX) (20150930/utaddress-254) [ 3.373483] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.373483] lpc_ich: Resource conflict(s) found affecting gpio_ich [ 3.406575] media: Linux media interface: v0.10 [ 3.408794] snd_hda_intel 0000:01:00.1: Handle vga_switcheroo audio client [ 3.408796] snd_hda_intel 0000:01:00.1: Force to non-snoop mode [ 3.410104] Linux video capture interface: v2.00 [ 3.417329] uvcvideo: Found UVC 1.00 device (046d:0808) [ 3.418714] input: HDA ATI HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input9 [ 3.418749] input: HDA ATI HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input10 [ 3.418783] input: HDA ATI HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input11 [ 3.418818] input: HDA ATI HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input12 [ 3.418849] input: HDA ATI HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input13 [ 3.418892] input: HDA ATI HDMI HDMI/DP,pcm=11 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input14 [ 3.422556] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC892: line_outs=4 (0x14/0x15/0x16/0x17/0x0) type:line [ 3.422558] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 3.422559] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x1b/0x0/0x0/0x0/0x0) [ 3.422560] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 3.422561] snd_hda_codec_realtek hdaudioC0D0: dig-out=0x11/0x1e [ 3.422562] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 3.422563] snd_hda_codec_realtek hdaudioC0D0: Front Mic=0x19 [ 3.422564] snd_hda_codec_realtek hdaudioC0D0: Rear Mic=0x18 [ 3.422565] snd_hda_codec_realtek hdaudioC0D0: Line=0x1a [ 3.423049] AVX version of gcm_enc/dec engaged. [ 3.423050] AES CTR mode by8 optimization enabled [ 3.451145] input: UVC Camera (046d:0808) as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.2/2-1.2:1.0/input/input15 [ 3.451183] usbcore: registered new interface driver uvcvideo [ 3.451184] USB Video Class driver (1.1.1) [ 3.468081] intel_rapl: Found RAPL domain package [ 3.468084] intel_rapl: Found RAPL domain core [ 3.493782] asus_wmi: ASUS WMI generic driver loaded [ 3.496033] asus_wmi: Initialization: 0x0 [ 3.496047] asus_wmi: BIOS WMI version: 0.9 [ 3.496067] asus_wmi: SFUN value: 0x0 [ 3.496234] input: Eee PC WMI hotkeys as /devices/platform/eeepc-wmi/input/input16 [ 3.496363] asus_wmi: Number of fans: 1 [ 3.677431] EXT4-fs (sdc5): barriers disabled [ 3.700149] EXT4-fs (sdc5): mounted filesystem with writeback data mode. Opts: data=writeback,barrier=0 [ 3.972204] usb 2-1.2: set resolution quirk: cval->res = 384 [ 3.972416] usbcore: registered new interface driver snd-usb-audio [ 4.189963] audit: type=1400 audit(1448034923.357:2): apparmor="STATUS" operation="profile_load" name="docker-default" pid=683 comm="apparmor_parser" [ 4.195446] audit: type=1400 audit(1448034923.361:3): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm-guest-session" pid=683 comm="apparmor_parser" [ 4.195449] audit: type=1400 audit(1448034923.361:4): apparmor="STATUS" operation="profile_load" name="chromium" pid=683 comm="apparmor_parser" [ 4.197457] audit: type=1400 audit(1448034923.365:5): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=683 comm="apparmor_parser" [ 4.197460] audit: type=1400 audit(1448034923.365:6): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=683 comm="apparmor_parser" [ 4.197463] audit: type=1400 audit(1448034923.365:7): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-helper" pid=683 comm="apparmor_parser" [ 4.197465] audit: type=1400 audit(1448034923.365:8): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=683 comm="apparmor_parser" [ 4.208144] audit: type=1400 audit(1448034923.377:9): apparmor="STATUS" operation="profile_load" name="/usr/bin/evince" pid=683 comm="apparmor_parser" [ 4.208147] audit: type=1400 audit(1448034923.377:10): apparmor="STATUS" operation="profile_load" name="sanitized_helper" pid=683 comm="apparmor_parser" [ 4.439421] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready [ 4.441554] Bluetooth: Core ver 2.21 [ 4.441562] NET: Registered protocol family 31 [ 4.441563] Bluetooth: HCI device and connection manager initialized [ 4.441566] Bluetooth: HCI socket layer initialized [ 4.441567] Bluetooth: L2CAP socket layer initialized [ 4.441570] Bluetooth: SCO socket layer initialized [ 4.695882] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready [ 4.699835] usbcore: registered new interface driver ath3k [ 4.736032] bridge: automatic filtering via arp/ip/ip6tables has been deprecated. Update your scripts to load br_netfilter if you need this. [ 4.738261] nf_conntrack version 0.5.0 (65536 buckets, 262144 max) [ 4.740968] IPv6: ADDRCONF(NETDEV_UP): docker0: link is not ready [ 4.746209] ip_tables: (C) 2000-2006 Netfilter Core Team [ 4.889676] usb 2-1.7: USB disconnect, device number 7 [ 6.111695] usb 2-1.7: new full-speed USB device number 9 using ehci-pci [ 6.204977] usb 2-1.7: New USB device found, idVendor=0cf3, idProduct=3005 [ 6.204982] usb 2-1.7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 6.210293] usbcore: registered new interface driver btusb [ 6.567692] usb 2-1.2: reset high-speed USB device number 4 using ehci-pci [ 7.246243] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 7.246245] Bluetooth: BNEP filters: protocol multicast [ 7.246247] Bluetooth: BNEP socket layer initialized [ 7.401640] e1000e: eth2 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx [ 7.401672] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready [ 7.634693] usb 2-1.1.4: usbfs: process 1530 (g15daemon) did not claim interface 0 before use [ 7.634700] usb 2-1.1.4: usbfs: process 1530 (g15daemon) did not claim interface 0 before use [ 7.634702] usb 2-1.1.4: usbfs: process 1530 (g15daemon) did not claim interface 0 before use [ 7.634704] usb 2-1.1.4: usbfs: process 1530 (g15daemon) did not claim interface 0 before use [ 7.635375] usb 2-1.1.4: usbfs: process 1531 (g15daemon) did not claim interface 0 before use [ 7.635918] usb 2-1.1.4: usbfs: process 1530 (g15daemon) did not claim interface 0 before use [ 8.124623] input: G15 Extra Keys as /devices/virtual/input/input17 [ 14.907669] usb 2-1.2: reset high-speed USB device number 4 using ehci-pci [ 15.753224] Bluetooth: RFCOMM TTY layer initialized [ 15.753229] Bluetooth: RFCOMM socket layer initialized [ 15.753232] Bluetooth: RFCOMM ver 1.11 [ 17.152150] audit_printk_skb: 51 callbacks suppressed [ 17.152152] audit: type=1400 audit(1448034936.320:28): apparmor="DENIED" operation="open" profile="/usr/lib/telepathy/mission-control-5" name="/usr/share/dconf/profile/gdm" pid=1936 comm="mission-control" requested_mask="r" denied_mask="r" fsuid=124 ouid=0 [ 41.663370] usb 2-1.2: reset high-speed USB device number 4 using ehci-pci ernst@mammut:~$ less /var/log/Xorg.0.log ernst@mammut:~$ man modesetting ernst@mammut:~$ cat /proc/cmdline BOOT_IMAGE=/boot/vmlinuz-4.3.999powerplay+ root=UUID=96de4ed3-7fc6-4ea4-a69a-d62b15398dde ro amdgpu.enable_scheduler=0 quiet splash vt.handoff=7 ernst@mammut:~$ export R600_DEBUG=vs,gs,ps ernst@mammut:~$ steam Running Steam on ubuntu 15.10 64-bit STEAM_RUNTIME is enabled automatically Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) (steam:3083): Gtk-WARNING **: Kan inte hitta temamotorn i "module_path": "adwaita", (steam:3083): Gtk-WARNING **: Kan inte hitta temamotorn i "module_path": "adwaita", /usr/share/themes/Adwaita/gtk-2.0/gtkrc:1163: error: unexpected identifier `direction', expected character `}' Installing breakpad exception handler for appid(steam)/version(1447125378) Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number [1120/165947:ERROR:main_delegate.cc(751)] Could not load cef_extensions.pak [1120/165947:ERROR:browser_main_loop.cc(189)] Running without the SUID sandbox! See https://code.google.com/p/chromium/wiki/LinuxSUIDSandboxDevelopment for more information on developing with the sandbox on. Installing breakpad exception handler for appid(steamwebhelper)/version(20151109182310) Installing breakpad exception handler for appid(steamwebhelper)/version(1447093390) [1120/165947:ERROR:main_delegate.cc(751)] Could not load cef_extensions.pak Installing breakpad exception handler for appid(steamwebhelper)/version(20151109182310) Installing breakpad exception handler for appid(steamwebhelper)/version(1447125378) Installing breakpad exception handler for appid(steamwebhelper)/version(1447125378) [1120/165947:ERROR:nss_util.cc(746)] Error initializing NSS with a persistent database (sql:/home/ernst/.pki/nssdb): NSS error code: -8015 Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Wireless receiver firmware /home/ernst/.local/share/Steam/ubuntu12_32/../controller_base/d0ggle.bin loaded, version 1442256398. Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) FillInMachineIDInfo took a total of 0 milliseconds ** (steam:3083): WARNING **: Unknown device type 13 ** (steam:3083): WARNING **: Could not create object for /org/freedesktop/NetworkManager/Devices/2: unknown object type ** (steam:3083): WARNING **: handle_property_changed: failed to update property 'devices' of object type NMActiveConnection. ** (steam:3083): WARNING **: Unknown device type 14 ** (steam:3083): WARNING **: Could not create object for /org/freedesktop/NetworkManager/Devices/1: unknown object type ** (steam:3083): WARNING **: Unknown device type 13 ** (steam:3083): WARNING **: Could not create object for /org/freedesktop/NetworkManager/Devices/2: unknown object type Installing breakpad exception handler for appid(steam)/version(1447125378) SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 [2015-11-20 16:59:35] Startup - updater built Nov 9 2015 18:23:22 [2015-11-20 16:59:36] Verifying installation... [2015-11-20 16:59:36] Verification complete VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = add i32 %5, %8 %15 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %13, i32 0, i32 %14) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, align 16, !tbaa !0 %22 = add i32 %5, %8 %23 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %22) %24 = extractelement <4 x float> %23, i32 0 %25 = extractelement <4 x float> %23, i32 1 %26 = extractelement <4 x float> %23, i32 2 %27 = extractelement <4 x float> %23, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %24, float %25, float %26, float %27) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %16, float %17, float %18, float %19) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C00A0004 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x10 ; C00A0104 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; C400020F 08070605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; C40008CF 04030201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 72 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %28, float %30, float %28, float %30) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 48 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %28, float %30, float %28, float %30) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 48 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** ** (steam:3083): WARNING **: Ignoring invalid property 'secondaries' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Ignoring invalid property 'secondaries' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Ignoring invalid property 'secondaries' ** (steam:3083): WARNING **: Ignoring invalid property 'interface-name' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Ignoring invalid property 'route-data' ** (steam:3083): WARNING **: Ignoring invalid property 'address-data' ** (steam:3083): WARNING **: Unknown setting 'bridge' ** (steam:3083): WARNING **: replace_settings: error updating connection /org/freedesktop/NetworkManager/Settings/2 settings: (3) type SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], TEXCOORD[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %34, %14 %47 = fmul float %34, %15 %48 = fmul float %34, %16 %49 = fmul float %34, %17 %50 = fmul float %35, %18 %51 = fadd float %50, %46 %52 = fmul float %35, %19 %53 = fadd float %52, %47 %54 = fmul float %35, %20 %55 = fadd float %54, %48 %56 = fmul float %35, %21 %57 = fadd float %56, %49 %58 = fmul float %36, %22 %59 = fadd float %58, %51 %60 = fmul float %36, %23 %61 = fadd float %60, %53 %62 = fmul float %36, %24 %63 = fadd float %62, %55 %64 = fmul float %36, %25 %65 = fadd float %64, %57 %66 = fmul float %37, %26 %67 = fadd float %66, %59 %68 = fmul float %37, %27 %69 = fadd float %68, %61 %70 = fmul float %37, %28 %71 = fadd float %70, %63 %72 = fmul float %37, %29 %73 = fadd float %72, %65 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %42, float %43, float %44, float %45) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %67, float %69, float %71, float %73) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_load_dwordx4 s[8:11], s[8:9], 0x10 ; C00A0204 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[8:11], 0 idxen ; E00C2000 80020500 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt vmcnt(1) lgkmcnt(0) ; BF8C0071 v_mul_f32_e32 v0, s4, v1 ; 0A000204 v_mul_f32_e32 v9, s5, v1 ; 0A120205 v_mul_f32_e32 v10, s6, v1 ; 0A140206 v_mul_f32_e32 v1, s7, v1 ; 0A020207 v_mac_f32_e32 v0, s8, v2 ; 2C000408 v_mac_f32_e32 v9, s9, v2 ; 2C120409 v_mac_f32_e32 v10, s10, v2 ; 2C14040A v_mac_f32_e32 v1, s11, v2 ; 2C02040B v_mac_f32_e32 v0, s12, v3 ; 2C00060C v_mac_f32_e32 v9, s13, v3 ; 2C12060D v_mac_f32_e32 v10, s14, v3 ; 2C14060E v_mac_f32_e32 v1, s15, v3 ; 2C02060F v_mac_f32_e32 v0, s16, v4 ; 2C000810 v_mac_f32_e32 v9, s17, v4 ; 2C120811 v_mac_f32_e32 v10, s18, v4 ; 2C140812 v_mac_f32_e32 v1, s0, v4 ; 2C020800 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; C400020F 08070605 exp 15, 12, 0, 1, 0, v0, v9, v10, v1 ; C40008CF 010A0900 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 12 Code Size: 336 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], TEXCOORD[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 64) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 68) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 72) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 76) %29 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %30 = load <8 x i32>, <8 x i32> addrspace(2)* %29, align 32, !tbaa !0 %31 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !tbaa !0 %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %36 = fdiv float %33, %35 %37 = fdiv float %34, %35 %38 = bitcast float %36 to i32 %39 = bitcast float %37 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %41, <8 x i32> %30, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %43 = extractelement <4 x float> %42, i32 0 %44 = extractelement <4 x float> %42, i32 1 %45 = extractelement <4 x float> %42, i32 2 %46 = extractelement <4 x float> %42, i32 3 %47 = fmul float %43, %25 %48 = fmul float %44, %26 %49 = fmul float %45, %27 %50 = fmul float %46, %28 %51 = call i32 @llvm.SI.packf16(float %47, float %48) %52 = bitcast i32 %51 to float %53 = call i32 @llvm.SI.packf16(float %49, float %50) %54 = bitcast i32 %53 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %52, float %54, float %52, float %54) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v0, v0, 3, 0, [m0] ; D4000300 v_interp_p2_f32 v0, [v0], v1, 3, 0, [m0] ; D4010301 v_mov_b32_e32 v1, 0x6f800000 ; 7E0202FF 6F800000 v_cmp_gt_f32_e64 vcc, |v0|, v1 ; D044016A 00020300 v_mov_b32_e32 v1, 0x2f800000 ; 7E0202FF 2F800000 v_cndmask_b32_e32 v1, 1.0, v1 ; 000202F2 v_mul_f32_e32 v0, v1, v0 ; 0A000101 v_rcp_f32_e32 v0, v0 ; 7E004500 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x40 ; C0220200 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x44 ; C0220240 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x48 ; C0220280 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x4c ; C0220000 0000004C v_mul_f32_e32 v2, v0, v2 ; 0A040500 v_mul_f32_e32 v4, v2, v1 ; 0A080302 v_mul_f32_e32 v0, v0, v3 ; 0A000700 v_mul_f32_e32 v5, v0, v1 ; 0A0A0300 image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[4:7] ; F0800F00 00230004 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v0, s8, v0 ; 0A000008 v_mul_f32_e32 v1, s9, v1 ; 0A020209 v_mul_f32_e32 v2, s10, v2 ; 0A04040A v_mul_f32_e32 v3, s0, v3 ; 0A060600 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 216 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** Generating new string page texture 2: 48x256, total string texture memory is 49,15 KB SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], TEXCOORD[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: MOV OUT[2], IN[2] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %47 = load <16 x i8>, <16 x i8> addrspace(2)* %46, align 16, !tbaa !0 %48 = add i32 %5, %8 %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %47, i32 0, i32 %48) %50 = extractelement <4 x float> %49, i32 0 %51 = extractelement <4 x float> %49, i32 1 %52 = extractelement <4 x float> %49, i32 2 %53 = extractelement <4 x float> %49, i32 3 %54 = fmul float %34, %14 %55 = fmul float %34, %15 %56 = fmul float %34, %16 %57 = fmul float %34, %17 %58 = fmul float %35, %18 %59 = fadd float %58, %54 %60 = fmul float %35, %19 %61 = fadd float %60, %55 %62 = fmul float %35, %20 %63 = fadd float %62, %56 %64 = fmul float %35, %21 %65 = fadd float %64, %57 %66 = fmul float %36, %22 %67 = fadd float %66, %59 %68 = fmul float %36, %23 %69 = fadd float %68, %61 %70 = fmul float %36, %24 %71 = fadd float %70, %63 %72 = fmul float %36, %25 %73 = fadd float %72, %65 %74 = fmul float %37, %26 %75 = fadd float %74, %67 %76 = fmul float %37, %27 %77 = fadd float %76, %69 %78 = fmul float %37, %28 %79 = fadd float %78, %71 %80 = fmul float %37, %29 %81 = fadd float %80, %73 %82 = and i32 %7, 1 %83 = icmp eq i32 %82, 0 br i1 %83, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %84 = call float @llvm.AMDIL.clamp.(float %42, float 0,000000e+00, float 0x3FF0000000000000) %85 = call float @llvm.AMDIL.clamp.(float %43, float 0,000000e+00, float 0x3FF0000000000000) %86 = call float @llvm.AMDIL.clamp.(float %44, float 0,000000e+00, float 0x3FF0000000000000) %87 = call float @llvm.AMDIL.clamp.(float %45, float 0,000000e+00, float 0x3FF0000000000000) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.06 = phi float [ %84, %if-true-block ], [ %42, %main_body ] %.05 = phi float [ %85, %if-true-block ], [ %43, %main_body ] %.04 = phi float [ %86, %if-true-block ], [ %44, %main_body ] %.0 = phi float [ %87, %if-true-block ], [ %45, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.06, float %.05, float %.04, float %.0) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %50, float %51, float %52, float %53) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %75, float %77, float %79, float %81) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 v_add_i32_e32 v8, vcc, s10, v0 ; 3210000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[4:7], v8, s[4:7], 0 idxen ; E00C2000 80010408 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v8, s[16:19], 0 idxen ; E00C2000 80040008 s_nop 0 ; BF800000 buffer_load_format_xyzw v[8:11], v8, s[20:23], 0 idxen ; E00C2000 80050808 s_load_dwordx4 s[20:23], s[2:3], 0x0 ; C00A0501 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s16, s[20:23], 0x0 ; C022040A 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[20:23], 0x4 ; C02203CA 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[20:23], 0x8 ; C022038A 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[20:23], 0xc ; C022034A 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[20:23], 0x10 ; C02202CA 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[20:23], 0x14 ; C022028A 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[20:23], 0x18 ; C022024A 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[20:23], 0x1c ; C022020A 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s7, s[20:23], 0x20 ; C02201CA 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[20:23], 0x24 ; C022018A 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[20:23], 0x28 ; C022014A 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[20:23], 0x2c ; C022010A 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s3, s[20:23], 0x30 ; C02200CA 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[20:23], 0x34 ; C022008A 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[20:23], 0x38 ; C022004A 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[20:23], 0x3c ; C022000A 0000003C s_and_b32 s12, 1, s12 ; 860C0C81 v_cmp_eq_i32_e64 s[18:19], 1, s12 ; D0C20012 00001881 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 s_and_saveexec_b64 s[18:19], s[18:19] ; BE922012 s_xor_b64 s[18:19], exec, s[18:19] ; 8892127E v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_add_f32_e64 v1, 0, v1 clamp ; D1018001 00020280 v_add_f32_e64 v2, 0, v2 clamp ; D1018002 00020480 v_add_f32_e64 v3, 0, v3 clamp ; D1018003 00020680 s_or_b64 exec, exec, s[18:19] ; 87FE127E v_mul_f32_e32 v12, s16, v4 ; 0A180810 v_mul_f32_e32 v13, s15, v4 ; 0A1A080F v_mul_f32_e32 v14, s14, v4 ; 0A1C080E v_mul_f32_e32 v4, s13, v4 ; 0A08080D v_mac_f32_e32 v12, s11, v5 ; 2C180A0B v_mac_f32_e32 v13, s10, v5 ; 2C1A0A0A v_mac_f32_e32 v14, s9, v5 ; 2C1C0A09 v_mac_f32_e32 v4, s8, v5 ; 2C080A08 v_mac_f32_e32 v12, s7, v6 ; 2C180C07 v_mac_f32_e32 v13, s6, v6 ; 2C1A0C06 v_mac_f32_e32 v14, s5, v6 ; 2C1C0C05 v_mac_f32_e32 v4, s4, v6 ; 2C080C04 v_mac_f32_e32 v12, s3, v7 ; 2C180E03 v_mac_f32_e32 v13, s2, v7 ; 2C1A0E02 v_mac_f32_e32 v14, s1, v7 ; 2C1C0E01 v_mac_f32_e32 v4, s0, v7 ; 2C080E00 exp 15, 32, 0, 0, 0, v0, v1, v2, v3 ; C400020F 03020100 exp 15, 33, 0, 0, 0, v8, v9, v10, v11 ; C400021F 0B0A0908 exp 15, 12, 0, 1, 0, v12, v13, v14, v4 ; C40008CF 040E0D0C s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 16 Code Size: 424 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL IN[1], TEXCOORD[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], IN[0] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %34 = fdiv float %31, %33 %35 = fdiv float %32, %33 %36 = bitcast float %34 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %39, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %41, %27 %46 = fmul float %42, %28 %47 = fmul float %43, %29 %48 = fmul float %44, %30 %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float %51 = call i32 @llvm.SI.packf16(float %47, float %48) %52 = bitcast i32 %51 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 v_interp_p1_f32 v0, v0, 3, 1, [m0] ; D4000700 v_interp_p2_f32 v0, [v0], v1, 3, 1, [m0] ; D4010701 v_mov_b32_e32 v1, 0x6f800000 ; 7E0202FF 6F800000 v_cmp_gt_f32_e64 vcc, |v0|, v1 ; D044016A 00020300 v_mov_b32_e32 v1, 0x2f800000 ; 7E0202FF 2F800000 v_cndmask_b32_e32 v1, 1.0, v1 ; 000202F2 v_mul_f32_e32 v0, v1, v0 ; 0A000101 v_rcp_f32_e32 v0, v0 ; 7E004500 v_mul_f32_e32 v6, v0, v6 ; 0A0C0D00 v_mul_f32_e32 v8, v6, v1 ; 0A100306 v_mul_f32_e32 v0, v0, v7 ; 0A000F00 v_mul_f32_e32 v9, v0, v1 ; 0A120300 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[8:15], s[0:3] ; F0800F00 00020608 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v2, v6 ; 0A000D02 v_mul_f32_e32 v1, v3, v7 ; 0A020F03 v_mul_f32_e32 v2, v4, v8 ; 0A041104 v_mul_f32_e32 v3, v5, v9 ; 0A061305 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 12 Code Size: 192 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float %40 = call i32 @llvm.SI.packf16(float %36, float %37) %41 = bitcast i32 %40 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %39, float %41, float %39, float %41) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 88 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** Generating new string page texture 3: 256x256, total string texture memory is 311,30 KB Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) local (potentially out of sync) copy of roaming config loaded - 6921 bytes. Installing breakpad exception handler for appid(steam)/version(1447125378) roaming config store loaded successfully - 6921 bytes. migrating temporary roaming config store Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number ExecCommandLine: ""/home/ernst/.local/share/Steam/ubuntu12_32/steam" " Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) System startup time: 7,84 seconds [1120/165954:ERROR:renderer_main.cc(200)] Running without renderer sandbox Generating new string page texture 73: 1024x256, total string texture memory is 1,36 MB Generating new string page texture 74: 128x256, total string texture memory is 131,07 KB Generating new string page texture 75: 128x256, total string texture memory is 1,49 MB Generating new string page texture 76: 64x256, total string texture memory is 1,56 MB Generating new string page texture 77: 32x256, total string texture memory is 1,59 MB [1120/165954:ERROR:renderer_main.cc(200)] Running without renderer sandbox Generating new string page texture 81: 128x256, total string texture memory is 1,72 MB Generating new string page texture 82: 256x256, total string texture memory is 1,98 MB Generating new string page texture 83: 128x256, total string texture memory is 2,11 MB Generating new string page texture 85: 384x256, total string texture memory is 2,51 MB Generating new string page texture 86: 48x256, total string texture memory is 2,56 MB Installing breakpad exception handler for appid(steam)/version(1447125378) Generating new string page texture 87: 8x256, total string texture memory is 2,56 MB Generating new string page texture 98: 128x256, total string texture memory is 2,70 MB Generating new string page texture 99: 256x256, total string texture memory is 2,96 MB Generating new string page texture 100: 128x256, total string texture memory is 3,09 MB Generating new string page texture 101: 64x256, total string texture memory is 3,15 MB Installing breakpad exception handler for appid(steam)/version(1447125378) CAPIJobRequestUserStats - Server response failed 2 Generating new string page texture 105: 16x256, total string texture memory is 3,17 MB Running Steam on ubuntu 15.10 64-bit STEAM_RUNTIME has been set by the user to: /home/ernst/.local/share/Steam/ubuntu12_32/steam-runtime ExecCommandLine: "/home/ernst/.steam/root/ubuntu12_32/steam steam://open/driverhelperready" ExecSteamURL: "steam://open/driverhelperready" Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Generating new string page texture 109: 256x256, total string texture memory is 393,22 KB Generating new string page texture 110: 128x256, total string texture memory is 3,30 MB Generating new string page texture 111: 256x256, total string texture memory is 3,56 MB Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) ExecSteamURL: "steam://open/downloads" Generating new string page texture 115: 64x256, total string texture memory is 3,63 MB Generating new string page texture 116: 128x256, total string texture memory is 3,76 MB Generating new string page texture 117: 256x256, total string texture memory is 4,02 MB Generating new string page texture 118: 48x256, total string texture memory is 4,07 MB Generating new string page texture 119: 128x256, total string texture memory is 4,20 MB Installing breakpad exception handler for appid(steam)/version(1447125378) Generating new string page texture 123: 512x256, total string texture memory is 4,73 MB Game update: AppID 730 "Counter-Strike: Global Offensive", ProcID 3273, IP 0.0.0.0:0 ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. pid 3276 != 3275, skipping destruction (fork without exec?) ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_64/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS64): ignored. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:3083): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 SDL video target is 'x11' SDL failed to create GL compatibility profile (whichProfile=0! This system supports the OpenGL extension GL_EXT_framebuffer_object. This system supports the OpenGL extension GL_EXT_framebuffer_blit. This system supports the OpenGL extension GL_EXT_framebuffer_multisample. This system DOES NOT support the OpenGL extension GL_APPLE_fence. This system DOES NOT support the OpenGL extension GL_NV_fence. This system supports the OpenGL extension GL_ARB_sync. This system supports the OpenGL extension GL_EXT_draw_buffers2. This system DOES NOT support the OpenGL extension GL_EXT_bindable_uniform. This system DOES NOT support the OpenGL extension GL_APPLE_flush_buffer_range. This system supports the OpenGL extension GL_ARB_map_buffer_range. This system supports the OpenGL extension GL_ARB_vertex_buffer_object. This system supports the OpenGL extension GL_ARB_occlusion_query. This system DOES NOT support the OpenGL extension GL_APPLE_texture_range. This system DOES NOT support the OpenGL extension GL_APPLE_client_storage. This system DOES NOT support the OpenGL extension GL_ARB_uniform_buffer. This system supports the OpenGL extension GL_ARB_vertex_array_bgra. This system supports the OpenGL extension GL_EXT_vertex_array_bgra. This system supports the OpenGL extension GL_ARB_framebuffer_object. This system DOES NOT support the OpenGL extension GL_GREMEDY_string_marker. This system supports the OpenGL extension GL_ARB_debug_output. This system DOES NOT support the OpenGL extension GL_EXT_direct_state_access. This system DOES NOT support the OpenGL extension GL_NV_bindless_texture. This system supports the OpenGL extension GL_AMD_pinned_memory. This system supports the OpenGL extension GL_EXT_framebuffer_multisample_blit_scaled. This system supports the OpenGL extension GL_EXT_texture_sRGB_decode. This system DOES NOT support the OpenGL extension GL_NVX_gpu_memory_info. This system DOES NOT support the OpenGL extension GL_ATI_meminfo. This system supports the OpenGL extension GL_EXT_texture_compression_s3tc. This system supports the OpenGL extension GL_EXT_texture_compression_dxt1. This system supports the OpenGL extension GL_ANGLE_texture_compression_dxt3. This system supports the OpenGL extension GL_ANGLE_texture_compression_dxt5. This system supports the OpenGL extension GL_ARB_buffer_storage. This system DOES NOT support the OpenGL extension GLX_EXT_swap_control_tear. VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = add i32 %5, %8 %15 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %13, i32 0, i32 %14) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, align 16, !tbaa !0 %22 = add i32 %5, %8 %23 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %22) %24 = extractelement <4 x float> %23, i32 0 %25 = extractelement <4 x float> %23, i32 1 %26 = extractelement <4 x float> %23, i32 2 %27 = extractelement <4 x float> %23, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %24, float %25, float %26, float %27) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %16, float %17, float %18, float %19) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C00A0004 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x10 ; C00A0104 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; C400020F 08070605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; C40008CF 04030201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 72 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %28, float %30, float %28, float %30) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 48 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** Installing breakpad exception handler for appid(steam)/version(1447125378) Using breakpad crash handler Setting breakpad minidump AppID = 730 Forcing breakpad minidump interfaces to load Looking up breakpad interfaces from steamclient Calling BreakpadMiniDumpSystemInit Looking up breakpad interfaces from steamclient Calling BreakpadMiniDumpSystemInit Steam_SetMinidumpSteamID: Caching Steam ID: 76561198005671812 [API loaded yes] Steam_SetMinidumpSteamID: Setting Steam ID: 76561198005671812 Using breakpad minidump system 730/13511.238 Did not detect any valid joysticks. failed to dlopen /home/Gemensamt/Spel/Steam/steamapps/common/Counter-Strike Global Offensive/bin/stdshader_dbg_client.so error=/home/Gemensamt/Spel/Steam/steamapps/common/Counter-Strike Global Offensive/bin/stdshader_dbg_client.so: kan inte öppna delad objektfil: Filen eller katalogen finns inte failed to dlopen /home/Gemensamt/Spel/Steam/steamapps/common/Counter-Strike Global Offensive/bin/stdshader_dbg_client.so error=/home/Gemensamt/Spel/Steam/steamapps/common/Counter-Strike Global Offensive/bin/stdshader_dbg_client.so: kan inte öppna delad objektfil: Filen eller katalogen finns inte failed to dlopen stdshader_dbg_client.so error=stdshader_dbg_client.so: kan inte öppna delad objektfil: Filen eller katalogen finns inte CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_butterfly/knife_butterfly.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_bayonet/knife_bayonet.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_ct/knife_ct.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_flip/knife_flip.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_gut/knife_gut.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_karam/karam.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_m9_bay/knife_m9_bay.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_t/knife_t.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_tactical/knife_tactical.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/mach_m249para/m249.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/mach_negev/mach_negev.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_223/pist_223.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_cz_75/pist_cz_75.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_deagle/pist_deagle.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_elite/m9a1.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_fiveseven/fiveseven.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_glock18/pist_glock18.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_hkp2000/pist_hkp2000.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_p250/p250.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/pist_tec9/pist_tec9.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_ak47/ak47.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_aug/rif_aug.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_famas/rif_famas.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_galilar/rif_galilar.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_m4a1/rif_m4a1.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_m4a1_s/rif_m4a1_s.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/rif_sg556/rif_sg556.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/shot_mag7/shot_mag7.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/shot_nova/shot_nova.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/shot_sawedoff/shot_sawedoff_01.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/shot_xm1014/shot_xm1014.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/smg_bizon/bizon.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapoSHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 ns/v_models/smg_mac10/smg_mac10_1.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/smg_mp7/smg_mp7.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/smg_mp9/smg_mp9.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/smg_p90/smg_p90.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/smg_ump45/smg_ump45.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/snip_awp/awp.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/snip_g3sg1/snip_g3sg1.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/snip_scar20/snip_scar20.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/snip_ssg08/snip_ssg08.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/snip_ssg08/snip_ssg08_scope.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_falchion_advanced/knife_falchion_advanced.vmt. CustomMaterialManager: Cached KeyValues materials/models/weapons/v_models/knife_push/knife_push.vmt. Failed to read the default inventory image file (materials/vgui/inventory_default.vtf) FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float %40 = call i32 @llvm.SI.packf16(float %36, float %37) %41 = bitcast i32 %40 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %39, float %41, float %39, float %41) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 88 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0] 4: MOV OUT[1], IMM[0].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %14, %34 %39 = fmul float %15, %34 %40 = fmul float %16, %34 %41 = fmul float %17, %34 %42 = fmul float %18, %35 %43 = fadd float %42, %38 %44 = fmul float %19, %35 %45 = fadd float %44, %39 %46 = fmul float %20, %35 %47 = fadd float %46, %40 %48 = fmul float %21, %35 %49 = fadd float %48, %41 %50 = fmul float %22, %36 %51 = fadd float %50, %43 %52 = fmul float %23, %36 %53 = fadd float %52, %45 %54 = fmul float %24, %36 %55 = fadd float %54, %47 %56 = fmul float %25, %36 %57 = fadd float %56, %49 %58 = fmul float %26, %37 %59 = fadd float %58, %51 %60 = fmul float %27, %37 %61 = fadd float %60, %53 %62 = fmul float %28, %37 %63 = fadd float %62, %55 %64 = fmul float %29, %37 %65 = fadd float %64, %57 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %59, float %61, float %63, float %65) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v4, s4, v0 ; 0A080004 v_mul_f32_e32 v5, s5, v0 ; 0A0A0005 v_mul_f32_e32 v6, s6, v0 ; 0A0C0006 v_mul_f32_e32 v0, s7, v0 ; 0A000007 v_mac_f32_e32 v4, s8, v1 ; 2C080208 v_mac_f32_e32 v5, s9, v1 ; 2C0A0209 v_mac_f32_e32 v6, s10, v1 ; 2C0C020A v_mac_f32_e32 v0, s11, v1 ; 2C00020B v_mac_f32_e32 v4, s12, v2 ; 2C08040C v_mac_f32_e32 v5, s13, v2 ; 2C0A040D v_mac_f32_e32 v6, s14, v2 ; 2C0C040E v_mac_f32_e32 v0, s15, v2 ; 2C00040F v_mac_f32_e32 v4, s16, v3 ; 2C080610 v_mac_f32_e32 v5, s17, v3 ; 2C0A0611 v_mac_f32_e32 v6, s18, v3 ; 2C0C0612 v_mac_f32_e32 v0, s0, v3 ; 2C000600 v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 32, 0, 0, 0, v1, v1, v1, v1 ; C400020F 01010101 exp 15, 12, 0, 1, 0, v4, v5, v6, v0 ; C40008CF 00060504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 316 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float %40 = call i32 @llvm.SI.packf16(float %36, float %37) %41 = bitcast i32 %40 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %39, float %41, float %39, float %41) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 88 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %28, float %30, float %28, float %30) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 48 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, UINT 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %34, float %35, float %36, float %37) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 0, 0, 1, 1, v0, v1, v2, v3 ; C400180F 03020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 72 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], CUBE, FLOAT 0: TEX OUT[0], IN[0], SAMP[0], CUBE 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %12) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %12) %31 = insertelement <4 x float> undef, float %27, i32 0 %32 = insertelement <4 x float> %31, float %28, i32 1 %33 = insertelement <4 x float> %32, float %29, i32 2 %34 = insertelement <4 x float> %33, float %30, i32 3 %35 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %34) %36 = extractelement <4 x float> %35, i32 0 %37 = extractelement <4 x float> %35, i32 1 %38 = extractelement <4 x float> %35, i32 2 %39 = extractelement <4 x float> %35, i32 3 %40 = call float @llvm.fabs.f32(float %38) %41 = fdiv float 1.000000e+00, %40 %42 = fmul float %36, %41 %43 = fadd float %42, 1.500000e+00 %44 = fmul float %37, %41 %45 = fadd float %44, 1.500000e+00 %46 = bitcast float %45 to i32 %47 = bitcast float %43 to i32 %48 = bitcast float %39 to i32 %49 = insertelement <4 x i32> undef, i32 %46, i32 0 %50 = insertelement <4 x i32> %49, i32 %47, i32 1 %51 = insertelement <4 x i32> %50, i32 %48, i32 2 %52 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %51, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = extractelement <4 x float> %52, i32 2 %56 = extractelement <4 x float> %52, i32 3 %57 = call i32 @llvm.SI.packf16(float %53, float %54) %58 = bitcast i32 %57 to float %59 = call i32 @llvm.SI.packf16(float %55, float %56) %60 = bitcast i32 %59 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %58, float %60, float %58, float %60) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v0, v0, 3, 0, [m0] ; D4000300 v_interp_p2_f32 v0, [v0], v1, 3, 0, [m0] ; D4010301 v_cubeid_f32 v7, v2, v3, v4 ; D1C40007 04120702 v_cubema_f32 v0, v2, v3, v4 ; D1C70000 04120702 v_rcp_f32_e64 v0, |v0| ; D1620100 00000100 v_cubesc_f32 v1, v2, v3, v4 ; D1C50001 04120702 v_cubetc_f32 v2, v2, v3, v4 ; D1C60002 04120702 v_mov_b32_e32 v5, 0x3fc00000 ; 7E0A02FF 3FC00000 v_mad_f32 v6, v0, v2, v5 ; D1C10006 04160500 v_mac_f32_e32 v5, v0, v1 ; 2C0A0300 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[5:8], s[8:15], s[0:3] ; F0800F00 00020005 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 160 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0] 4: MOV OUT[1], IMM[0].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %14, %34 %39 = fmul float %15, %34 %40 = fmul float %16, %34 %41 = fmul float %17, %34 %42 = fmul float %18, %35 %43 = fadd float %42, %38 %44 = fmul float %19, %35 %45 = fadd float %44, %39 %46 = fmul float %20, %35 %47 = fadd float %46, %40 %48 = fmul float %21, %35 %49 = fadd float %48, %41 %50 = fmul float %22, %36 %51 = fadd float %50, %43 %52 = fmul float %23, %36 %53 = fadd float %52, %45 %54 = fmul float %24, %36 %55 = fadd float %54, %47 %56 = fmul float %25, %36 %57 = fadd float %56, %49 %58 = fmul float %26, %37 %59 = fadd float %58, %51 %60 = fmul float %27, %37 %61 = fadd float %60, %53 %62 = fmul float %28, %37 %63 = fadd float %62, %55 %64 = fmul float %29, %37 %65 = fadd float %64, %57 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %59, float %61, float %63, float %65) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v4, s4, v0 ; 0A080004 v_mul_f32_e32 v5, s5, v0 ; 0A0A0005 v_mul_f32_e32 v6, s6, v0 ; 0A0C0006 v_mul_f32_e32 v0, s7, v0 ; 0A000007 v_mac_f32_e32 v4, s8, v1 ; 2C080208 v_mac_f32_e32 v5, s9, v1 ; 2C0A0209 v_mac_f32_e32 v6, s10, v1 ; 2C0C020A v_mac_f32_e32 v0, s11, v1 ; 2C00020B v_mac_f32_e32 v4, s12, v2 ; 2C08040C v_mac_f32_e32 v5, s13, v2 ; 2C0A040D v_mac_f32_e32 v6, s14, v2 ; 2C0C040E v_mac_f32_e32 v0, s15, v2 ; 2C00040F v_mac_f32_e32 v4, s16, v3 ; 2C080610 v_mac_f32_e32 v5, s17, v3 ; 2C0A0611 v_mac_f32_e32 v6, s18, v3 ; 2C0C0612 v_mac_f32_e32 v0, s0, v3 ; 2C000600 v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 32, 0, 0, 0, v1, v1, v1, v1 ; C400020F 01010101 exp 15, 12, 0, 1, 0, v4, v5, v6, v0 ; C40008CF 00060504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 316 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], CUBE, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzz 1: TEX TEMP[0], TEMP[0], SAMP[0], CUBE 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = insertelement <4 x float> undef, float %27, i32 0 %31 = insertelement <4 x float> %30, float %28, i32 1 %32 = insertelement <4 x float> %31, float %29, i32 2 %33 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = call float @llvm.fabs.f32(float %36) %39 = fdiv float 1.000000e+00, %38 %40 = fmul float %34, %39 %41 = fadd float %40, 1.500000e+00 %42 = fmul float %35, %39 %43 = fadd float %42, 1.500000e+00 %44 = bitcast float %43 to i32 %45 = bitcast float %41 to i32 %46 = bitcast float %37 to i32 %47 = insertelement <4 x i32> undef, i32 %44, i32 0 %48 = insertelement <4 x i32> %47, i32 %45, i32 1 %49 = insertelement <4 x i32> %48, i32 %46, i32 2 %50 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %49, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = extractelement <4 x float> %50, i32 3 %55 = call i32 @llvm.SI.packf16(float %51, float %52) %56 = bitcast i32 %55 to float %57 = call i32 @llvm.SI.packf16(float %53, float %54) %58 = bitcast i32 %57 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %56, float %58, float %56, float %58) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v0, v0, 2, 0, [m0] ; D4000200 v_interp_p2_f32 v0, [v0], v1, 2, 0, [m0] ; D4010201 v_cubeid_f32 v6, v2, v3, v0 ; D1C40006 04020702 v_cubema_f32 v1, v2, v3, v0 ; D1C70001 04020702 v_rcp_f32_e64 v1, |v1| ; D1620101 00000101 v_cubesc_f32 v7, v2, v3, v0 ; D1C50007 04020702 v_cubetc_f32 v0, v2, v3, v0 ; D1C60000 04020702 v_mov_b32_e32 v4, 0x3fc00000 ; 7E0802FF 3FC00000 v_mad_f32 v5, v1, v0, v4 ; D1C10005 04120101 v_mac_f32_e32 v4, v1, v7 ; 2C080F01 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:7], s[8:15], s[0:3] ; F0800F00 00020004 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 152 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] DCL CONST[0..57] DCL TEMP[0..7], LOCAL IMM[0] FLT32 { 1.0000, 2.2000, 0.0000, 0.0000} 0: ABS TEMP[0].x, CONST[50].xxxx 1: FSLT TEMP[1].x, -TEMP[0].xxxx, TEMP[0].xxxx 2: AND TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx 3: ADD TEMP[0].xyz, IN[1].xyzz, IN[1].xyzz 4: LG2 TEMP[2].x, TEMP[0].xxxx 5: LG2 TEMP[3].x, TEMP[0].yyyy 6: MOV TEMP[2].y, TEMP[3].xxxx 7: LG2 TEMP[3].x, TEMP[0].zzzz 8: MOV TEMP[2].z, TEMP[3].xxxx 9: MUL TEMP[0].xyz, TEMP[2].xyzz, IMM[0].yyyy 10: EX2 TEMP[2].x, TEMP[0].xxxx 11: EX2 TEMP[3].x, TEMP[0].yyyy 12: MOV TEMP[2].y, TEMP[3].xxxx 13: EX2 TEMP[3].x, TEMP[0].zzzz 14: MOV TEMP[2].z, TEMP[3].xxxx 15: MUL TEMP[1].xyz, TEMP[1].xxxx, TEMP[2].xyzz 16: DP4 TEMP[3].x, IN[2], CONST[48] 17: DP4 TEMP[4].x, IN[2], CONST[49] 18: MOV TEMP[3].y, TEMP[4].xxxx 19: MOV TEMP[0].w, CONST[0].yyyy 20: MOV TEMP[2].w, IN[0].wwww 21: MAD TEMP[2].xyz, IN[3].xyzz, CONST[13].xxxx, IN[0].xyzz 22: DP4 TEMP[0].x, TEMP[2], CONST[54] 23: DP4 TEMP[4].x, TEMP[2], CONST[55] 24: MOV TEMP[0].y, TEMP[4].xxxx 25: DP4 TEMP[2].x, TEMP[2], CONST[56] 26: MOV TEMP[0].z, TEMP[2].xxxx 27: DP4 TEMP[2].x, TEMP[0], CONST[8] 28: DP4 TEMP[4].x, TEMP[0], CONST[9] 29: MOV TEMP[2].y, TEMP[4].xxxx 30: DP4 TEMP[5].x, TEMP[0], CONST[11] 31: MOV TEMP[2].w, TEMP[5].xxxx 32: DP4 TEMP[6].x, TEMP[0], CONST[10] 33: MOV TEMP[0].w, TEMP[6].xxxx 34: MOV TEMP[2].z, TEMP[6].xxxx 35: MOV TEMP[3].zw, CONST[0].xxxx 36: MOV TEMP[1].w, CONST[0].xxxx 37: MOV TEMP[7], TEMP[2] 38: MAD TEMP[6].x, TEMP[6].xxxx, CONST[0].zzzz, -TEMP[5].xxxx 39: MOV TEMP[2].z, TEMP[6].xxxx 40: MOV TEMP[2].y, -TEMP[4].xxxx 41: MAD TEMP[2].xy, CONST[57].xyyy, TEMP[5].xxxx, TEMP[2].xyyy 42: MOV OUT[2], TEMP[3] 43: MOV OUT[0], TEMP[2] 44: MOV OUT[1], TEMP[7] 45: MOV OUT[3], TEMP[1] 46: MOV OUT[4], TEMP[0] 47: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 872) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 876) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 880) %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 884) %49 = call float @llvm.SI.load.const(<16 x i8> %13, i32 888) %50 = call float @llvm.SI.load.const(<16 x i8> %13, i32 892) %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 896) %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 900) %53 = call float @llvm.SI.load.const(<16 x i8> %13, i32 904) %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 908) %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 912) %56 = call float @llvm.SI.load.const(<16 x i8> %13, i32 916) %57 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %58 = load <16 x i8>, <16 x i8> addrspace(2)* %57, align 16, !tbaa !0 %59 = add i32 %5, %8 %60 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %59) %61 = extractelement <4 x float> %60, i32 0 %62 = extractelement <4 x float> %60, i32 1 %63 = extractelement <4 x float> %60, i32 2 %64 = extractelement <4 x float> %60, i32 3 %65 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %66 = load <16 x i8>, <16 x i8> addrspace(2)* %65, align 16, !tbaa !0 %67 = add i32 %5, %8 %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %66, i32 0, i32 %67) %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = extractelement <4 x float> %68, i32 2 %72 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %73 = load <16 x i8>, <16 x i8> addrspace(2)* %72, align 16, !tbaa !0 %74 = add i32 %5, %8 %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %73, i32 0, i32 %74) %76 = extractelement <4 x float> %75, i32 0 %77 = extractelement <4 x float> %75, i32 1 %78 = extractelement <4 x float> %75, i32 2 %79 = extractelement <4 x float> %75, i32 3 %80 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %81 = load <16 x i8>, <16 x i8> addrspace(2)* %80, align 16, !tbaa !0 %82 = add i32 %5, %8 %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %82) %84 = extractelement <4 x float> %83, i32 0 %85 = extractelement <4 x float> %83, i32 1 %86 = extractelement <4 x float> %83, i32 2 %87 = call float @llvm.fabs.f32(float %42) %88 = fsub float -0.000000e+00, %87 %89 = fcmp ogt float %87, %88 %90 = select i1 %89, float 1.000000e+00, float 0.000000e+00 %91 = fadd float %69, %69 %92 = fadd float %70, %70 %93 = fadd float %71, %71 %94 = call float @llvm.log2.f32(float %91) %95 = call float @llvm.log2.f32(float %92) %96 = call float @llvm.log2.f32(float %93) %97 = fmul float %94, 0x40019999A0000000 %98 = fmul float %95, 0x40019999A0000000 %99 = fmul float %96, 0x40019999A0000000 %100 = call float @llvm.exp2.f32(float %97) %101 = call float @llvm.exp2.f32(float %98) %102 = call float @llvm.exp2.f32(float %99) %103 = fmul float %90, %100 %104 = fmul float %90, %101 %105 = fmul float %90, %102 %106 = fmul float %76, %34 %107 = fmul float %77, %35 %108 = fadd float %106, %107 %109 = fmul float %78, %36 %110 = fadd float %108, %109 %111 = fmul float %79, %37 %112 = fadd float %110, %111 %113 = fmul float %76, %38 %114 = fmul float %77, %39 %115 = fadd float %113, %114 %116 = fmul float %78, %40 %117 = fadd float %115, %116 %118 = fmul float %79, %41 %119 = fadd float %117, %118 %120 = fmul float %84, %33 %121 = fadd float %120, %61 %122 = fmul float %85, %33 %123 = fadd float %122, %62 %124 = fmul float %86, %33 %125 = fadd float %124, %63 %126 = fmul float %121, %43 %127 = fmul float %123, %44 %128 = fadd float %126, %127 %129 = fmul float %125, %45 %130 = fadd float %128, %129 %131 = fmul float %64, %46 %132 = fadd float %130, %131 %133 = fmul float %121, %47 %134 = fmul float %123, %48 %135 = fadd float %133, %134 %136 = fmul float %125, %49 %137 = fadd float %135, %136 %138 = fmul float %64, %50 %139 = fadd float %137, %138 %140 = fmul float %121, %51 %141 = fmul float %123, %52 %142 = fadd float %140, %141 %143 = fmul float %125, %53 %144 = fadd float %142, %143 %145 = fmul float %64, %54 %146 = fadd float %144, %145 %147 = fmul float %132, %17 %148 = fmul float %139, %18 %149 = fadd float %147, %148 %150 = fmul float %146, %19 %151 = fadd float %149, %150 %152 = fmul float %15, %20 %153 = fadd float %151, %152 %154 = fmul float %132, %21 %155 = fmul float %139, %22 %156 = fadd float %154, %155 %157 = fmul float %146, %23 %158 = fadd float %156, %157 %159 = fmul float %15, %24 %160 = fadd float %158, %159 %161 = fmul float %132, %29 %162 = fmul float %139, %30 %163 = fadd float %161, %162 %164 = fmul float %146, %31 %165 = fadd float %163, %164 %166 = fmul float %15, %32 %167 = fadd float %165, %166 %168 = fmul float %132, %25 %169 = fmul float %139, %26 %170 = fadd float %168, %169 %171 = fmul float %146, %27 %172 = fadd float %170, %171 %173 = fmul float %15, %28 %174 = fadd float %172, %173 %175 = fmul float %174, %16 %176 = fsub float %175, %167 %177 = fmul float %55, %167 %178 = fadd float %177, %153 %179 = fmul float %56, %167 %180 = fsub float %179, %160 %181 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %182 = load <16 x i8>, <16 x i8> addrspace(2)* %181, align 16, !tbaa !0 %183 = call float @llvm.SI.load.const(<16 x i8> %182, i32 0) %184 = fmul float %183, %153 %185 = call float @llvm.SI.load.const(<16 x i8> %182, i32 4) %186 = fmul float %185, %160 %187 = fadd float %184, %186 %188 = call float @llvm.SI.load.const(<16 x i8> %182, i32 8) %189 = fmul float %188, %174 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %182, i32 12) %192 = fmul float %191, %167 %193 = fadd float %190, %192 %194 = call float @llvm.SI.load.const(<16 x i8> %182, i32 16) %195 = fmul float %194, %153 %196 = call float @llvm.SI.load.const(<16 x i8> %182, i32 20) %197 = fmul float %196, %160 %198 = fadd float %195, %197 %199 = call float @llvm.SI.load.const(<16 x i8> %182, i32 24) %200 = fmul float %199, %174 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %182, i32 28) %203 = fmul float %202, %167 %204 = fadd float %201, %203 %205 = call float @llvm.SI.load.const(<16 x i8> %182, i32 32) %206 = fmul float %205, %153 %207 = call float @llvm.SI.load.const(<16 x i8> %182, i32 36) %208 = fmul float %207, %160 %209 = fadd float %206, %208 %210 = call float @llvm.SI.load.const(<16 x i8> %182, i32 40) %211 = fmul float %210, %174 %212 = fadd float %209, %211 %213 = call float @llvm.SI.load.const(<16 x i8> %182, i32 44) %214 = fmul float %213, %167 %215 = fadd float %212, %214 %216 = call float @llvm.SI.load.const(<16 x i8> %182, i32 48) %217 = fmul float %216, %153 %218 = call float @llvm.SI.load.const(<16 x i8> %182, i32 52) %219 = fmul float %218, %160 %220 = fadd float %217, %219 %221 = call float @llvm.SI.load.const(<16 x i8> %182, i32 56) %222 = fmul float %221, %174 %223 = fadd float %220, %222 %224 = call float @llvm.SI.load.const(<16 x i8> %182, i32 60) %225 = fmul float %224, %167 %226 = fadd float %223, %225 %227 = call float @llvm.SI.load.const(<16 x i8> %182, i32 64) %228 = fmul float %227, %153 %229 = call float @llvm.SI.load.const(<16 x i8> %182, i32 68) %230 = fmul float %229, %160 %231 = fadd float %228, %230 %232 = call float @llvm.SI.load.const(<16 x i8> %182, i32 72) %233 = fmul float %232, %174 %234 = fadd float %231, %233 %235 = call float @llvm.SI.load.const(<16 x i8> %182, i32 76) %236 = fmul float %235, %167 %237 = fadd float %234, %236 %238 = call float @llvm.SI.load.const(<16 x i8> %182, i32 80) %239 = fmul float %238, %153 %240 = call float @llvm.SI.load.const(<16 x i8> %182, i32 84) %241 = fmul float %240, %160 %242 = fadd float %239, %241 %243 = call float @llvm.SI.load.const(<16 x i8> %182, i32 88) %244 = fmul float %243, %174 %245 = fadd float %242, %244 %246 = call float @llvm.SI.load.const(<16 x i8> %182, i32 92) %247 = fmul float %246, %167 %248 = fadd float %245, %247 %249 = call float @llvm.SI.load.const(<16 x i8> %182, i32 96) %250 = fmul float %249, %153 %251 = call float @llvm.SI.load.const(<16 x i8> %182, i32 100) %252 = fmul float %251, %160 %253 = fadd float %250, %252 %254 = call float @llvm.SI.load.const(<16 x i8> %182, i32 104) %255 = fmul float %254, %174 %256 = fadd float %253, %255 %257 = call float @llvm.SI.load.const(<16 x i8> %182, i32 108) %258 = fmul float %257, %167 %259 = fadd float %256, %258 %260 = call float @llvm.SI.load.const(<16 x i8> %182, i32 112) %261 = fmul float %260, %153 %262 = call float @llvm.SI.load.const(<16 x i8> %182, i32 116) %263 = fmul float %262, %160 %264 = fadd float %261, %263 %265 = call float @llvm.SI.load.const(<16 x i8> %182, i32 120) %266 = fmul float %265, %174 %267 = fadd float %264, %266 %268 = call float @llvm.SI.load.const(<16 x i8> %182, i32 124) %269 = fmul float %268, %167 %270 = fadd float %267, %269 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %112, float %119, float %14, float %14) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %103, float %104, float %105, float %14) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %132, float %139, float %146, float %174) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %178, float %180, float %176, float %167) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %193, float %204, float %215, float %226) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %237, float %248, float %259, float %270) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.log2.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.exp2.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[2:3], 0x100 ; C00A0101 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x0 ; C00A0604 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x10 ; C00A0704 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x30 ; C00A0404 00000030 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[12:15], 0xb0 ; C0220046 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0xb4 ; C0220086 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0xb8 ; C0220006 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0xbc ; C0220206 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xd0 ; C02200C6 000000D0 buffer_load_format_xyzw v[1:4], v0, s[24:27], 0 idxen ; E00C2000 80060100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[28:31], 0 idxen ; E00C2000 80070500 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[8:11], v0, s[20:23], 0 idxen ; E00C2000 80050800 s_nop 0 ; BF800000 buffer_load_format_xyzw v[12:15], v0, s[16:19], 0 idxen ; E00C2000 80040C00 s_buffer_load_dword s11, s[12:15], 0x0 ; C02202C6 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x4 ; C0220286 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x8 ; C0220246 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x80 ; C0220406 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x84 ; C0220446 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x88 ; C0220486 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x8c ; C02204C6 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x90 ; C0220506 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x94 ; C0220546 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x98 ; C0220586 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x9c ; C02205C6 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0xa0 ; C0220606 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0xa4 ; C0220646 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0xa8 ; C0220686 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0xac ; C02206C6 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x300 ; C0220706 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x304 ; C0220746 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x308 ; C0220786 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x30c ; C02207C6 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x310 ; C0220806 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x314 ; C0220846 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x318 ; C0220886 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x31c ; C02208C6 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x320 ; C0220906 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x360 ; C0220946 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x364 ; C0220986 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x368 ; C02209C6 00000368 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x36c ; C0220A06 0000036C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x370 ; C0220A46 00000370 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x374 ; C0220A86 00000374 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x378 ; C0220AC6 00000378 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[12:15], 0x37c ; C0220B06 0000037C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[12:15], 0x380 ; C0220B46 00000380 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[12:15], 0x384 ; C0220B86 00000384 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[12:15], 0x388 ; C0220BC6 00000388 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[12:15], 0x38c ; C0220C06 0000038C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[12:15], 0x390 ; C0220C46 00000390 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x394 ; C0220306 00000394 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x0 ; C0220342 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x4 ; C0220382 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x8 ; C02203C2 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[4:7], 0xc ; C0220C82 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s51, s[4:7], 0x10 ; C0220CC2 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[4:7], 0x14 ; C0220D02 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s53, s[4:7], 0x18 ; C0220D42 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[4:7], 0x1c ; C0220D82 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s55, s[4:7], 0x20 ; C0220DC2 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[4:7], 0x24 ; C0220E02 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[4:7], 0x28 ; C0220E42 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[4:7], 0x2c ; C0220E82 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s59, s[4:7], 0x30 ; C0220EC2 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[4:7], 0x34 ; C0220F02 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[4:7], 0x38 ; C0220F42 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[4:7], 0x3c ; C0220F82 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[4:7], 0x40 ; C0220FC2 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[4:7], 0x44 ; C0221002 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[4:7], 0x48 ; C0221042 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[4:7], 0x4c ; C0221082 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[4:7], 0x50 ; C02210C2 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[4:7], 0x54 ; C0221102 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[4:7], 0x58 ; C0221142 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[4:7], 0x5c ; C0221182 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s71, s[4:7], 0x60 ; C02211C2 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s72, s[4:7], 0x64 ; C0221202 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s73, s[4:7], 0x68 ; C0221242 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s74, s[4:7], 0x6c ; C0221282 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s75, s[4:7], 0x70 ; C02212C2 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s76, s[4:7], 0x74 ; C0221302 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s77, s[4:7], 0x78 ; C0221342 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x7c ; C0220102 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s19 ; 7E000213 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v15, s23 ; 7E1E0217 v_mov_b32_e32 v16, s8 ; 7E200208 v_mov_b32_e32 v17, s27 ; 7E22021B v_mov_b32_e32 v18, s11 ; 7E24020B v_mul_f32_e32 v19, s29, v9 ; 0A26121D v_cmp_gt_f32_e64 s[6:7], |s36|, -|s36| ; D0440306 40004824 v_mad_f32 v1, s3, v12, v1 ; D1C10001 04061803 v_mad_f32 v2, s3, v13, v2 ; D1C10002 040A1A03 v_mad_f32 v3, s3, v14, v3 ; D1C10003 040E1C03 v_mul_f32_e32 v9, s33, v9 ; 0A121221 v_mac_f32_e32 v19, s28, v8 ; 2C26101C v_mac_f32_e32 v9, s32, v8 ; 2C121020 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mac_f32_e32 v19, s30, v10 ; 2C26141E v_mac_f32_e32 v9, s34, v10 ; 2C121422 v_mac_f32_e32 v19, s31, v11 ; 2C26161F v_mac_f32_e32 v9, s35, v11 ; 2C121623 v_mov_b32_e32 v10, 0x400ccccd ; 7E1402FF 400CCCCD v_add_f32_e32 v5, v5, v5 ; 020A0B05 v_add_f32_e32 v6, v6, v6 ; 020C0D06 v_add_f32_e32 v7, v7, v7 ; 020E0F07 v_cndmask_b32_e64 v11, 0, 1.0, s[6:7] ; D100000B 0019E480 v_log_f32_e32 v5, v5 ; 7E0A4305 v_log_f32_e32 v6, v6 ; 7E0C4306 v_log_f32_e32 v7, v7 ; 7E0E4307 v_mul_f32_e32 v12, s42, v2 ; 0A18042A v_mul_f32_e32 v2, s46, v2 ; 0A04042E v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v12, s41, v1 ; 2C180229 v_mac_f32_e32 v2, s45, v1 ; 2C04022D v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v12, s43, v3 ; 2C18062B v_mac_f32_e32 v2, s47, v3 ; 2C04062F v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v12, s44, v4 ; 2C18082C v_mac_f32_e32 v2, s48, v4 ; 2C040830 exp 15, 32, 0, 0, 0, v19, v9, v18, v18 ; C400020F 12120913 v_mul_f32_e32 v1, v10, v5 ; 0A020B0A v_mul_f32_e32 v3, v10, v6 ; 0A060D0A v_mul_f32_e32 v4, v10, v7 ; 0A080F0A v_mul_f32_e32 v5, s17, v12 ; 0A0A1811 v_mul_f32_e32 v6, s21, v12 ; 0A0C1815 v_mul_f32_e32 v7, s2, v12 ; 0A0E1802 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v9, s25, v12 ; 0A121819 v_exp_f32_e32 v1, v1 ; 7E024101 v_exp_f32_e32 v3, v3 ; 7E064103 v_exp_f32_e32 v4, v4 ; 7E084104 v_mac_f32_e32 v5, s16, v8 ; 2C0A1010 v_mac_f32_e32 v6, s20, v8 ; 2C0C1014 v_mac_f32_e32 v7, s1, v8 ; 2C0E1001 v_mac_f32_e32 v9, s24, v8 ; 2C121018 v_mul_f32_e32 v1, v1, v11 ; 0A021701 v_mul_f32_e32 v3, v3, v11 ; 0A061703 v_mul_f32_e32 v4, v4, v11 ; 0A081704 v_mac_f32_e32 v5, s18, v2 ; 2C0A0412 v_mac_f32_e32 v6, s22, v2 ; 2C0C0416 v_mac_f32_e32 v7, s0, v2 ; 2C0E0400 v_mac_f32_e32 v9, s26, v2 ; 2C12041A v_mac_f32_e32 v5, s10, v0 ; 2C0A000A v_mac_f32_e32 v6, s10, v15 ; 2C0C1E0A v_mac_f32_e32 v7, s10, v16 ; 2C0E200A v_mac_f32_e32 v9, s10, v17 ; 2C12220A exp 15, 33, 0, 0, 0, v1, v3, v4, v18 ; C400021F 12040301 v_mad_f32 v0, v9, s9, -v7 ; D1C10000 841C1309 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v1, s49, v7, v5 ; D1C10001 04160E31 v_mad_f32 v3, s12, v7, -v6 ; D1C10003 841A0E0C v_mul_f32_e32 v4, s14, v6 ; 0A080C0E v_mul_f32_e32 v10, s52, v6 ; 0A140C34 v_mul_f32_e32 v11, s56, v6 ; 0A160C38 v_mul_f32_e32 v13, s60, v6 ; 0A1A0C3C v_mul_f32_e32 v14, s64, v6 ; 0A1C0C40 v_mul_f32_e32 v15, s68, v6 ; 0A1E0C44 v_mul_f32_e32 v16, s72, v6 ; 0A200C48 v_mul_f32_e32 v6, s76, v6 ; 0A0C0C4C exp 15, 34, 0, 0, 0, v8, v12, v2, v9 ; C400022F 09020C08 v_mac_f32_e32 v4, s13, v5 ; 2C080A0D v_mac_f32_e32 v10, s51, v5 ; 2C140A33 v_mac_f32_e32 v11, s55, v5 ; 2C160A37 v_mac_f32_e32 v13, s59, v5 ; 2C1A0A3B v_mac_f32_e32 v14, s63, v5 ; 2C1C0A3F v_mac_f32_e32 v15, s67, v5 ; 2C1E0A43 v_mac_f32_e32 v16, s71, v5 ; 2C200A47 v_mac_f32_e32 v6, s75, v5 ; 2C0C0A4B v_mac_f32_e32 v4, s15, v9 ; 2C08120F v_mac_f32_e32 v10, s53, v9 ; 2C141235 v_mac_f32_e32 v11, s57, v9 ; 2C161239 v_mac_f32_e32 v13, s61, v9 ; 2C1A123D v_mac_f32_e32 v14, s65, v9 ; 2C1C1241 v_mac_f32_e32 v15, s69, v9 ; 2C1E1245 v_mac_f32_e32 v16, s73, v9 ; 2C201249 v_mac_f32_e32 v6, s77, v9 ; 2C0C124D v_mac_f32_e32 v4, s50, v7 ; 2C080E32 v_mac_f32_e32 v10, s54, v7 ; 2C140E36 v_mac_f32_e32 v11, s58, v7 ; 2C160E3A v_mac_f32_e32 v13, s62, v7 ; 2C1A0E3E v_mac_f32_e32 v14, s66, v7 ; 2C1C0E42 v_mac_f32_e32 v15, s70, v7 ; 2C1E0E46 v_mac_f32_e32 v16, s74, v7 ; 2C200E4A v_mac_f32_e32 v6, s4, v7 ; 2C0C0E04 exp 15, 12, 0, 0, 0, v1, v3, v0, v7 ; C40000CF 07000301 exp 15, 13, 0, 0, 0, v4, v10, v11, v13 ; C40000DF 0D0B0A04 exp 15, 14, 0, 1, 0, v14, v15, v16, v6 ; C40008EF 06100F0E s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 20 Code Size: 1504 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0..30] DCL TEMP[0..5], LOCAL IMM[0] FLT32 { -1.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: ADD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx 3: MAD TEMP[1].x, CONST[20].wwww, TEMP[1].xxxx, IMM[0].yyyy 4: MUL TEMP[1].x, TEMP[1].xxxx, CONST[1].wwww 5: MAD TEMP[2].x, TEMP[1].xxxx, IN[1].wwww, -TEMP[1].xxxx 6: MAD TEMP[1].x, CONST[12].wwww, TEMP[2].xxxx, TEMP[1].xxxx 7: ABS TEMP[3].x, CONST[12].yyyy 8: MUL TEMP[4].x, CONST[29].wwww, IN[2].wwww 9: FSGE TEMP[5].x, -TEMP[3].xxxx, IMM[0].zzzz 10: UIF TEMP[5].xxxx :0 11: MOV TEMP[5].x, TEMP[1].xxxx 12: ELSE :0 13: MOV TEMP[5].x, TEMP[4].xxxx 14: ENDIF 15: MOV TEMP[3].w, TEMP[5].xxxx 16: ADD TEMP[4].x, TEMP[0].wwww, CONST[12].xxxx 17: MOV_SAT TEMP[4].x, TEMP[4].xxxx 18: ADD TEMP[1].xyz, IMM[0].xxxx, CONST[1].xyzz 19: MAD TEMP[1].xyz, TEMP[4].xxxx, TEMP[1].xyzz, IMM[0].yyyy 20: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz 21: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[30].xxxx 22: MAD TEMP[0].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz 23: ADD TEMP[2].xyz, CONST[20].xyzz, -IN[2].xyzz 24: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 25: SQRT TEMP[2].x, TEMP[2].xxxx 26: MAD TEMP[2].x, TEMP[2].xxxx, CONST[21].wwww, CONST[21].xxxx 27: MOV_SAT TEMP[2].x, TEMP[2].xxxx 28: MIN TEMP[2].x, TEMP[2].xxxx, CONST[21].zzzz 29: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 30: MAD TEMP[3].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[1].xyzz 31: MOV OUT[0], TEMP[3] 32: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 204) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 320) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 324) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 328) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 332) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 336) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 344) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 348) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 476) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %44 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %45 = load <8 x i32>, <8 x i32> addrspace(2)* %44, align 32, !tbaa !0 %46 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %47 = load <4 x i32>, <4 x i32> addrspace(2)* %46, align 16, !tbaa !0 %48 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %49 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %50 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %51 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %52 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %53 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %54 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %55 = bitcast float %48 to i32 %56 = bitcast float %49 to i32 %57 = insertelement <2 x i32> undef, i32 %55, i32 0 %58 = insertelement <2 x i32> %57, i32 %56, i32 1 %59 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %58, <8 x i32> %45, <4 x i32> %47, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %60 = extractelement <4 x float> %59, i32 0 %61 = extractelement <4 x float> %59, i32 1 %62 = extractelement <4 x float> %59, i32 2 %63 = extractelement <4 x float> %59, i32 3 %64 = fadd float %63, -1.000000e+00 %65 = fmul float %35, %64 %66 = fadd float %65, 1.000000e+00 %67 = fmul float %66, %28 %68 = fmul float %67, %50 %69 = fsub float %68, %67 %70 = fmul float %31, %69 %71 = fadd float %70, %67 %72 = call float @llvm.fabs.f32(float %30) %73 = fmul float %42, %54 %74 = fcmp ole float %72, -0.000000e+00 %. = select i1 %74, float %71, float %73 %75 = fadd float %63, %29 %76 = call float @llvm.AMDIL.clamp.(float %75, float 0.000000e+00, float 1.000000e+00) %77 = fadd float %25, -1.000000e+00 %78 = fadd float %26, -1.000000e+00 %79 = fadd float %27, -1.000000e+00 %80 = fmul float %76, %77 %81 = fadd float %80, 1.000000e+00 %82 = fmul float %76, %78 %83 = fadd float %82, 1.000000e+00 %84 = fmul float %76, %79 %85 = fadd float %84, 1.000000e+00 %86 = fmul float %60, %81 %87 = fmul float %61, %83 %88 = fmul float %62, %85 %89 = fmul float %86, %43 %90 = fmul float %87, %43 %91 = fmul float %88, %43 %92 = fmul float %43, %86 %93 = fsub float %39, %92 %94 = fmul float %43, %87 %95 = fsub float %40, %94 %96 = fmul float %43, %88 %97 = fsub float %41, %96 %98 = fsub float %32, %51 %99 = fsub float %33, %52 %100 = fsub float %34, %53 %101 = fmul float %98, %98 %102 = fmul float %99, %99 %103 = fadd float %102, %101 %104 = fmul float %100, %100 %105 = fadd float %103, %104 %106 = call float @llvm.sqrt.f32(float %105) %107 = fmul float %106, %38 %108 = fadd float %107, %36 %109 = call float @llvm.AMDIL.clamp.(float %108, float 0.000000e+00, float 1.000000e+00) %110 = call float @llvm.minnum.f32(float %109, float %37) %111 = fmul float %110, %110 %112 = fmul float %111, %93 %113 = fadd float %112, %89 %114 = fmul float %111, %95 %115 = fadd float %114, %90 %116 = fmul float %111, %97 %117 = fadd float %116, %91 %118 = call i32 @llvm.SI.packf16(float %113, float %115) %119 = bitcast i32 %118 to float %120 = call i32 @llvm.SI.packf16(float %117, float %.) %121 = bitcast i32 %120 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %119, float %121, float %119, float %121) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x18 ; C02202C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x1c ; C0220300 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0xc0 ; C0220340 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0xc4 ; C0220380 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0xcc ; C02203C0 000000CC s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x140 ; C0220400 00000140 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x144 ; C0220440 00000144 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x148 ; C0220480 00000148 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x14c ; C02204C0 0000014C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x150 ; C0220500 00000150 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x158 ; C0220540 00000158 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x15c ; C0220580 0000015C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x1d0 ; C02205C0 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x1d4 ; C0220600 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x1d8 ; C0220640 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x1dc ; C0220680 000001DC s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x1e0 ; C0220000 000001E0 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[28:35], s[6:7], 0x0 ; C00E0703 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 3, 1, [m0] ; D4100700 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 v_interp_p2_f32 v4, [v4], v1, 3, 1, [m0] ; D4110701 v_interp_p1_f32 v5, v0, 0, 2, [m0] ; D4140800 v_interp_p2_f32 v5, [v5], v1, 0, 2, [m0] ; D4150801 v_interp_p1_f32 v6, v0, 1, 2, [m0] ; D4180900 v_interp_p2_f32 v6, [v6], v1, 1, 2, [m0] ; D4190901 v_interp_p1_f32 v7, v0, 2, 2, [m0] ; D41C0A00 v_interp_p2_f32 v7, [v7], v1, 2, 2, [m0] ; D41D0A01 v_interp_p1_f32 v0, v0, 3, 2, [m0] ; D4000B00 v_interp_p2_f32 v0, [v0], v1, 3, 2, [m0] ; D4010B01 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[8:11], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[28:35], s[4:7] ; F0800F00 00270802 s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v1, v11, s19, -s19 ; D1C10001 804C270B v_mad_f32 v1, v1, s12, s12 ; D1C10001 00301901 v_mad_f32 v2, v1, v4, -v1 ; D1C10002 84060901 v_mac_f32_e32 v1, s15, v2 ; 2C02040F v_mul_f32_e32 v0, s26, v0 ; 0A00001A v_mov_b32_e32 v2, 0x80000000 ; 7E0402FF 80000000 v_cmp_le_f32_e64 vcc, |s14|, v2 ; D043016A 0002040E v_cndmask_b32_e32 v0, v0, v1 ; 00000300 v_add_f32_e32 v1, s13, v11 ; 0202160D v_add_f32_e64 v1, 0, v1 clamp ; D1018001 00020280 v_mad_f32 v2, s8, v1, -v1 ; D1C10002 84060208 v_mad_f32 v3, s9, v1, -v1 ; D1C10003 84060209 v_mad_f32 v1, s11, v1, -v1 ; D1C10001 8406020B v_mad_f32 v2, v8, v2, v8 ; D1C10002 04220508 v_mad_f32 v3, v9, v3, v9 ; D1C10003 04260709 v_mad_f32 v1, v10, v1, v10 ; D1C10001 042A030A v_mul_f32_e32 v4, s0, v2 ; 0A080400 v_mul_f32_e32 v8, s0, v3 ; 0A100600 v_mul_f32_e32 v9, s0, v1 ; 0A120200 v_mov_b32_e32 v10, s23 ; 7E140217 v_mad_f32 v2, -v2, s0, v10 ; D1C10002 24280102 v_mov_b32_e32 v10, s24 ; 7E140218 v_mad_f32 v3, -v3, s0, v10 ; D1C10003 24280103 v_mov_b32_e32 v10, s25 ; 7E140219 v_mad_f32 v1, -v1, s0, v10 ; D1C10001 24280101 v_sub_f32_e32 v5, s16, v5 ; 040A0A10 v_sub_f32_e32 v6, s17, v6 ; 040C0C11 v_sub_f32_e32 v7, s18, v7 ; 040E0E12 v_mul_f32_e32 v5, v5, v5 ; 0A0A0B05 v_mac_f32_e32 v5, v6, v6 ; 2C0A0D06 v_mac_f32_e32 v5, v7, v7 ; 2C0A0F07 v_sqrt_f32_e32 v5, v5 ; 7E0A4F05 v_mov_b32_e32 v6, s20 ; 7E0C0214 v_mac_f32_e32 v6, s22, v5 ; 2C0C0A16 v_add_f32_e64 v5, 0, v6 clamp ; D1018005 00020C80 v_min_f32_e32 v5, s21, v5 ; 140A0A15 v_mul_f32_e32 v5, v5, v5 ; 0A0A0B05 v_mac_f32_e32 v4, v2, v5 ; 2C080B02 v_mac_f32_e32 v8, v3, v5 ; 2C100B03 v_mac_f32_e32 v9, v1, v5 ; 2C120B01 v_cvt_pkrtz_f16_f32_e64 v1, v4, v8 ; D2960001 00021104 v_cvt_pkrtz_f16_f32_e64 v0, v9, v0 ; D2960000 00020109 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 40 VGPRS: 12 Code Size: 584 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** ##### swap interval = 0 swap limit = 1 ##### SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 CClientSteamContext logged on = 1 Game.dll loaded for "Counter-Strike: Global Offensive" CGameEventManager::AddListener: event 'server_pre_shutdown' unknown. CGameEventManager::AddListener: event 'game_newmap' unknown. CGameEventManager::AddListener: event 'finale_start' unknown. CGameEventManager::AddListener: event 'round_start' unknown. CGameEventManager::AddListener: event 'round_end' unknown. CGameEventManager::AddListener: event 'difficulty_changed' unknown. CGameEventManager::AddListener: event 'player_connect' unknown. CGameEventManager::AddListener: event 'player_disconnect' unknown. GameTypes: missing mapgroupsSP entry for game type/mode (custom/custom). GameTypes: missing mapgroupsSP entry for game type/mode (cooperative/cooperative). FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %23, float %24, float %25, float %26) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 exp 15, 0, 0, 1, 1, v0, v1, v2, v3 ; C400180F 03020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 32 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL OUT[1], POSITION DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: TEX OUT[1].z, IN[0], SAMP[0], 2D 2: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 2 call void @llvm.SI.export(i32 1, i32 0, i32 0, i32 8, i32 0, float %34, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_mov_b32_e32 v0, 0 ; 7E000280 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v1, 4, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800400 00030102 s_waitcnt vmcnt(0) ; BF8C0770 exp 1, 8, 0, 0, 0, v1, v0, v0, v0 ; C4000081 00000001 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 1.0 ; 7E0202F2 exp 15, 0, 0, 1, 1, v0, v0, v0, v1 ; C400180F 01000000 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 92 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 3D, FLOAT 0: TEX OUT[0], IN[0], SAMP[0], 3D 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %12) %30 = bitcast float %27 to i32 %31 = bitcast float %28 to i32 %32 = bitcast float %29 to i32 %33 = insertelement <4 x i32> undef, i32 %30, i32 0 %34 = insertelement <4 x i32> %33, i32 %31, i32 1 %35 = insertelement <4 x i32> %34, i32 %32, i32 2 %36 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %35, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float %43 = call i32 @llvm.SI.packf16(float %39, float %40) %44 = bitcast i32 %43 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %42, float %44, float %42, float %44) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:5], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 96 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0] 4: MOV OUT[1], IMM[0].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %14, %34 %39 = fmul float %15, %34 %40 = fmul float %16, %34 %41 = fmul float %17, %34 %42 = fmul float %18, %35 %43 = fadd float %42, %38 %44 = fmul float %19, %35 %45 = fadd float %44, %39 %46 = fmul float %20, %35 %47 = fadd float %46, %40 %48 = fmul float %21, %35 %49 = fadd float %48, %41 %50 = fmul float %22, %36 %51 = fadd float %50, %43 %52 = fmul float %23, %36 %53 = fadd float %52, %45 %54 = fmul float %24, %36 %55 = fadd float %54, %47 %56 = fmul float %25, %36 %57 = fadd float %56, %49 %58 = fmul float %26, %37 %59 = fadd float %58, %51 %60 = fmul float %27, %37 %61 = fadd float %60, %53 %62 = fmul float %28, %37 %63 = fadd float %62, %55 %64 = fmul float %29, %37 %65 = fadd float %64, %57 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %59, float %61, float %63, float %65) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v4, s4, v0 ; 0A080004 v_mul_f32_e32 v5, s5, v0 ; 0A0A0005 v_mul_f32_e32 v6, s6, v0 ; 0A0C0006 v_mul_f32_e32 v0, s7, v0 ; 0A000007 v_mac_f32_e32 v4, s8, v1 ; 2C080208 v_mac_f32_e32 v5, s9, v1 ; 2C0A0209 v_mac_f32_e32 v6, s10, v1 ; 2C0C020A v_mac_f32_e32 v0, s11, v1 ; 2C00020B v_mac_f32_e32 v4, s12, v2 ; 2C08040C v_mac_f32_e32 v5, s13, v2 ; 2C0A040D v_mac_f32_e32 v6, s14, v2 ; 2C0C040E v_mac_f32_e32 v0, s15, v2 ; 2C00040F v_mac_f32_e32 v4, s16, v3 ; 2C080610 v_mac_f32_e32 v5, s17, v3 ; 2C0A0611 v_mac_f32_e32 v6, s18, v3 ; 2C0C0612 v_mac_f32_e32 v0, s0, v3 ; 2C000600 v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 32, 0, 0, 0, v1, v1, v1, v1 ; C400020F 01010101 exp 15, 12, 0, 1, 0, v4, v5, v6, v0 ; C40008CF 00060504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 316 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 3D, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzz 1: TEX TEMP[0], TEMP[0], SAMP[0], 3D 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = bitcast float %27 to i32 %31 = bitcast float %28 to i32 %32 = bitcast float %29 to i32 %33 = insertelement <4 x i32> undef, i32 %30, i32 0 %34 = insertelement <4 x i32> %33, i32 %31, i32 1 %35 = insertelement <4 x i32> %34, i32 %32, i32 2 %36 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %35, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = call i32 @llvm.SI.packf16(float %37, float %38) %42 = bitcast i32 %41 to float %43 = call i32 @llvm.SI.packf16(float %39, float %40) %44 = bitcast i32 %43 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %42, float %44, float %42, float %44) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:5], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 96 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS32): ignored. SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL CONST[0..3] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[1], CONST[0] 2: DP4 TEMP[1].x, IN[1], CONST[1] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[1], CONST[2] 5: DP4 TEMP[2].x, IN[1], CONST[3] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], IN[0] 9: MOV OUT[0], TEMP[0] 10: MOV OUT[2], TEMP[1] 11: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %14 %47 = fmul float %43, %15 %48 = fadd float %46, %47 %49 = fmul float %44, %16 %50 = fadd float %48, %49 %51 = fmul float %45, %17 %52 = fadd float %50, %51 %53 = fmul float %42, %18 %54 = fmul float %43, %19 %55 = fadd float %53, %54 %56 = fmul float %44, %20 %57 = fadd float %55, %56 %58 = fmul float %45, %21 %59 = fadd float %57, %58 %60 = fmul float %42, %22 %61 = fmul float %43, %23 %62 = fadd float %60, %61 %63 = fmul float %44, %24 %64 = fadd float %62, %63 %65 = fmul float %45, %25 %66 = fadd float %64, %65 %67 = fmul float %42, %26 %68 = fmul float %43, %27 %69 = fadd float %67, %68 %70 = fmul float %44, %28 %71 = fadd float %69, %70 %72 = fmul float %45, %29 %73 = fadd float %71, %72 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %34, float %35, float %36, float %37) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %66, float %73, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 1.0 ; 7E0202F2 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x14 ; C0220200 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x18 ; C0220240 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x1c ; C0220280 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x20 ; C02202C0 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x24 ; C0220400 00000024 buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_buffer_load_dword s4, s[0:3], 0x28 ; C0220100 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x2c ; C0220140 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x30 ; C0220180 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x34 ; C02201C0 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x38 ; C0220300 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x0 ; C0220340 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x4 ; C0220380 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x8 ; C02203C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0xc ; C0220440 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x10 ; C0220480 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt vmcnt(1) ; BF8C0771 exp 15, 32, 0, 0, 0, v2, v3, v4, v5 ; C400020F 05040302 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v0, s14, v7 ; 0A000E0E s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v2, s8, v7 ; 0A040E08 v_mul_f32_e32 v3, s16, v7 ; 0A060E10 v_mul_f32_e32 v4, s7, v7 ; 0A080E07 v_mac_f32_e32 v0, s13, v6 ; 2C000C0D v_mac_f32_e32 v2, s18, v6 ; 2C040C12 v_mac_f32_e32 v3, s11, v6 ; 2C060C0B v_mac_f32_e32 v4, s6, v6 ; 2C080C06 v_mac_f32_e32 v0, s15, v8 ; 2C00100F v_mac_f32_e32 v2, s9, v8 ; 2C041009 v_mac_f32_e32 v3, s4, v8 ; 2C061004 v_mac_f32_e32 v4, s12, v8 ; 2C08100C v_mac_f32_e32 v0, s17, v9 ; 2C001211 v_mac_f32_e32 v2, s10, v9 ; 2C04120A v_mac_f32_e32 v3, s5, v9 ; 2C061205 v_mac_f32_e32 v4, s0, v9 ; 2C081200 exp 15, 33, 0, 0, 0, v3, v4, v0, v0 ; C400021F 00000403 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v0, v2, v3, v1 ; C40008CF 01030200 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 12 Code Size: 360 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xyz, TEMP[0].xyzx 3: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww 4: MOV TEMP[1].w, TEMP[0].xxxx 5: MOV OUT[0], TEMP[1] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %30 = bitcast float %28 to i32 %31 = bitcast float %29 to i32 %32 = insertelement <2 x i32> undef, i32 %30, i32 0 %33 = insertelement <2 x i32> %32, i32 %31, i32 1 %34 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %33, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %35 = extractelement <4 x float> %34, i32 0 %36 = extractelement <4 x float> %34, i32 1 %37 = extractelement <4 x float> %34, i32 2 %38 = extractelement <4 x float> %34, i32 3 %39 = fmul float %38, %27 %40 = call i32 @llvm.SI.packf16(float %35, float %36) %41 = bitcast i32 %40 to float %42 = call i32 @llvm.SI.packf16(float %37, float %39) %43 = bitcast i32 %42 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 3, 0, [m0] ; D4080300 v_interp_p2_f32 v2, [v2], v1, 3, 0, [m0] ; D4090301 v_interp_p1_f32 v3, v0, 0, 1, [m0] ; D40C0400 v_interp_p2_f32 v3, [v3], v1, 0, 1, [m0] ; D40D0401 v_interp_p1_f32 v4, v0, 1, 1, [m0] ; D4100500 v_interp_p2_f32 v4, [v4], v1, 1, 1, [m0] ; D4110501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[3:6], 15, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[12:19], s[0:3] ; F0800F00 00030303 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v2, v6 ; 0A000D02 v_cvt_pkrtz_f16_f32_e64 v1, v3, v4 ; D2960001 00020903 v_cvt_pkrtz_f16_f32_e64 v0, v5, v0 ; D2960000 00020105 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 100 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL OUT[4], GENERIC[3] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[1], CONST[2] 2: DP4 TEMP[1].x, IN[1], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[1], CONST[4] 5: DP4 TEMP[2].x, IN[1], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], IN[0] 9: MOV OUT[2], CONST[0] 10: MOV OUT[3], CONST[1] 11: MOV OUT[0], TEMP[0] 12: MOV OUT[4], TEMP[1] 13: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %47 = load <16 x i8>, <16 x i8> addrspace(2)* %46, align 16, !tbaa !0 %48 = add i32 %5, %8 %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %47, i32 0, i32 %48) %50 = extractelement <4 x float> %49, i32 0 %51 = extractelement <4 x float> %49, i32 1 %52 = extractelement <4 x float> %49, i32 2 %53 = extractelement <4 x float> %49, i32 3 %54 = fmul float %50, %22 %55 = fmul float %51, %23 %56 = fadd float %54, %55 %57 = fmul float %52, %24 %58 = fadd float %56, %57 %59 = fmul float %53, %25 %60 = fadd float %58, %59 %61 = fmul float %50, %26 %62 = fmul float %51, %27 %63 = fadd float %61, %62 %64 = fmul float %52, %28 %65 = fadd float %63, %64 %66 = fmul float %53, %29 %67 = fadd float %65, %66 %68 = fmul float %50, %30 %69 = fmul float %51, %31 %70 = fadd float %68, %69 %71 = fmul float %52, %32 %72 = fadd float %70, %71 %73 = fmul float %53, %33 %74 = fadd float %72, %73 %75 = fmul float %50, %34 %76 = fmul float %51, %35 %77 = fadd float %75, %76 %78 = fmul float %52, %36 %79 = fadd float %77, %78 %80 = fmul float %53, %37 %81 = fadd float %79, %80 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %42, float %43, float %44, float %45) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %74, float %81, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %60, float %67, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v9, s4 ; 7E120204 v_mov_b32_e32 v10, s5 ; 7E140205 v_mov_b32_e32 v11, s6 ; 7E160206 s_waitcnt vmcnt(1) ; BF8C0771 exp 15, 32, 0, 0, 0, v1, v2, v3, v4 ; C400020F 04030201 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, s7 ; 7E020207 v_mov_b32_e32 v2, s8 ; 7E040208 v_mov_b32_e32 v3, s9 ; 7E060209 v_mov_b32_e32 v4, s10 ; 7E08020A exp 15, 33, 0, 0, 0, v9, v10, v11, v1 ; C400021F 010B0A09 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, s11 ; 7E02020B s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v9, s13, v6 ; 0A120C0D v_mul_f32_e32 v10, s17, v6 ; 0A140C11 v_mul_f32_e32 v11, s21, v6 ; 0A160C15 exp 15, 34, 0, 0, 0, v2, v3, v4, v1 ; C400022F 01040302 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v1, s23, v6 ; 0A020C17 v_mac_f32_e32 v9, s12, v5 ; 2C120A0C v_mac_f32_e32 v10, s16, v5 ; 2C140A10 v_mac_f32_e32 v11, s20, v5 ; 2C160A14 v_mac_f32_e32 v1, s22, v5 ; 2C020A16 v_mac_f32_e32 v9, s14, v7 ; 2C120E0E v_mac_f32_e32 v10, s18, v7 ; 2C140E12 v_mac_f32_e32 v11, s24, v7 ; 2C160E18 v_mac_f32_e32 v1, s26, v7 ; 2C020E1A v_mac_f32_e32 v9, s15, v8 ; 2C12100F v_mac_f32_e32 v10, s19, v8 ; 2C141013 v_mac_f32_e32 v11, s25, v8 ; 2C161019 v_mac_f32_e32 v1, s0, v8 ; 2C021000 exp 15, 35, 0, 0, 0, v11, v1, v0, v0 ; C400023F 0000010B s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v9, v10, v1, v0 ; C40008CF 00010A09 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 12 Code Size: 520 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xy, IN[3].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MAD TEMP[0], TEMP[0], IN[2], IN[1] 3: MUL TEMP[1].x, TEMP[0].wwww, IN[0].wwww 4: MOV TEMP[0].w, TEMP[1].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %38 = bitcast float %36 to i32 %39 = bitcast float %37 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %41, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %43 = extractelement <4 x float> %42, i32 0 %44 = extractelement <4 x float> %42, i32 1 %45 = extractelement <4 x float> %42, i32 2 %46 = extractelement <4 x float> %42, i32 3 %47 = fmul float %43, %32 %48 = fadd float %47, %28 %49 = fmul float %44, %33 %50 = fadd float %49, %29 %51 = fmul float %45, %34 %52 = fadd float %51, %30 %53 = fmul float %46, %35 %54 = fadd float %53, %31 %55 = fmul float %54, %27 %56 = call i32 @llvm.SI.packf16(float %48, float %50) %57 = bitcast i32 %56 to float %58 = call i32 @llvm.SI.packf16(float %52, float %55) %59 = bitcast i32 %58 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %57, float %59, float %57, float %59) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 3, 0, [m0] ; D4080300 v_interp_p2_f32 v2, [v2], v1, 3, 0, [m0] ; D4090301 v_interp_p1_f32 v3, v0, 0, 1, [m0] ; D40C0400 v_interp_p2_f32 v3, [v3], v1, 0, 1, [m0] ; D40D0401 v_interp_p1_f32 v4, v0, 1, 1, [m0] ; D4100500 v_interp_p2_f32 v4, [v4], v1, 1, 1, [m0] ; D4110501 v_interp_p1_f32 v5, v0, 2, 1, [m0] ; D4140600 v_interp_p2_f32 v5, [v5], v1, 2, 1, [m0] ; D4150601 v_interp_p1_f32 v6, v0, 3, 1, [m0] ; D4180700 v_interp_p2_f32 v6, [v6], v1, 3, 1, [m0] ; D4190701 v_interp_p1_f32 v7, v0, 0, 2, [m0] ; D41C0800 v_interp_p2_f32 v7, [v7], v1, 0, 2, [m0] ; D41D0801 v_interp_p1_f32 v8, v0, 1, 2, [m0] ; D4200900 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v8, [v8], v1, 1, 2, [m0] ; D4210901 v_interp_p1_f32 v9, v0, 2, 2, [m0] ; D4240A00 v_interp_p2_f32 v9, [v9], v1, 2, 2, [m0] ; D4250A01 v_interp_p1_f32 v10, v0, 3, 2, [m0] ; D4280B00 v_interp_p2_f32 v10, [v10], v1, 3, 2, [m0] ; D4290B01 v_interp_p1_f32 v11, v0, 0, 3, [m0] ; D42C0C00 v_interp_p2_f32 v11, [v11], v1, 0, 3, [m0] ; D42D0C01 v_interp_p1_f32 v12, v0, 1, 3, [m0] ; D4300D00 v_interp_p2_f32 v12, [v12], v1, 1, 3, [m0] ; D4310D01 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[8:15], s[0:3] ; F0800F00 00020B0B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v3, v7, v11 ; 2C061707 v_mac_f32_e32 v4, v8, v12 ; 2C081908 v_mac_f32_e32 v5, v9, v13 ; 2C0A1B09 v_mac_f32_e32 v6, v10, v14 ; 2C0C1D0A v_mul_f32_e32 v0, v2, v6 ; 0A000D02 v_cvt_pkrtz_f16_f32_e64 v1, v3, v4 ; D2960001 00020903 v_cvt_pkrtz_f16_f32_e64 v0, v5, v0 ; D2960000 00020105 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 176 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL OUT[4], GENERIC[3] DCL CONST[0..3] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[2], CONST[2] 2: DP4 TEMP[1].x, IN[2], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: MOV OUT[2], IN[1] 5: MOV OUT[3], CONST[0] 6: MOV OUT[1], IN[0] 7: MOV OUT[4], CONST[1] 8: MOV OUT[0], TEMP[0] 9: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %47 = load <16 x i8>, <16 x i8> addrspace(2)* %46, align 16, !tbaa !0 %48 = add i32 %5, %8 %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %47, i32 0, i32 %48) %50 = extractelement <4 x float> %49, i32 0 %51 = extractelement <4 x float> %49, i32 1 %52 = extractelement <4 x float> %49, i32 2 %53 = extractelement <4 x float> %49, i32 3 %54 = fmul float %50, %22 %55 = fmul float %51, %23 %56 = fadd float %54, %55 %57 = fmul float %52, %24 %58 = fadd float %56, %57 %59 = fmul float %53, %25 %60 = fadd float %58, %59 %61 = fmul float %50, %26 %62 = fmul float %51, %27 %63 = fadd float %61, %62 %64 = fmul float %52, %28 %65 = fadd float %63, %64 %66 = fmul float %53, %29 %67 = fadd float %65, %66 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %34, float %35, float %36, float %37) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %42, float %43, float %44, float %45) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %60, float %67, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 1.0 ; 7E0202F2 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x14 ; C0220200 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x18 ; C0220240 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x1c ; C0220280 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x20 ; C02202C0 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x24 ; C0220500 00000024 buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_nop 0 ; BF800000 buffer_load_format_xyzw v[10:13], v0, s[16:19], 0 idxen ; E00C2000 80040A00 s_buffer_load_dword s4, s[0:3], 0x28 ; C0220100 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x2c ; C0220140 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x30 ; C0220180 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x34 ; C02201C0 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x38 ; C0220300 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x0 ; C0220340 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x4 ; C0220380 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x8 ; C02203C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0xc ; C0220400 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x10 ; C0220440 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s8 ; 7E000208 v_mov_b32_e32 v14, s13 ; 7E1C020D v_mov_b32_e32 v15, s14 ; 7E1E020E v_mov_b32_e32 v16, s15 ; 7E20020F v_mov_b32_e32 v17, s16 ; 7E220210 v_mov_b32_e32 v18, s17 ; 7E240211 s_waitcnt vmcnt(2) ; BF8C0772 exp 15, 32, 0, 0, 0, v2, v3, v4, v5 ; C400020F 05040302 s_waitcnt vmcnt(1) ; BF8C0771 exp 15, 33, 0, 0, 0, v6, v7, v8, v9 ; C400021F 09080706 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v2, s9 ; 7E040209 v_mov_b32_e32 v3, s10 ; 7E06020A s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v4, s20, v11 ; 0A081614 exp 15, 34, 0, 0, 0, v14, v15, v16, v17 ; C400022F 11100F0E v_mul_f32_e32 v5, s7, v11 ; 0A0A1607 v_mac_f32_e32 v4, s11, v10 ; 2C08140B v_mac_f32_e32 v5, s6, v10 ; 2C0A1406 v_mac_f32_e32 v4, s4, v12 ; 2C081804 v_mac_f32_e32 v5, s12, v12 ; 2C0A180C v_mac_f32_e32 v4, s5, v13 ; 2C081A05 v_mac_f32_e32 v5, s0, v13 ; 2C0A1A00 exp 15, 35, 0, 0, 0, v18, v0, v2, v3 ; C400023F 03020012 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v4, v5, v0, v1 ; C40008CF 01000504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 20 Code Size: 408 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0..1], LOCAL 0: MAD TEMP[0], IN[0], IN[3], IN[2] 1: MUL TEMP[1].x, TEMP[0].wwww, IN[1].wwww 2: MOV TEMP[0].w, TEMP[1].xxxx 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %24 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %27 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %6, <2 x i32> %8) %36 = fmul float %23, %32 %37 = fadd float %36, %28 %38 = fmul float %24, %33 %39 = fadd float %38, %29 %40 = fmul float %25, %34 %41 = fadd float %40, %30 %42 = fmul float %26, %35 %43 = fadd float %42, %31 %44 = fmul float %43, %27 %45 = call i32 @llvm.SI.packf16(float %37, float %39) %46 = bitcast i32 %45 to float %47 = call i32 @llvm.SI.packf16(float %41, float %44) %48 = bitcast i32 %47 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %46, float %48, float %46, float %48) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 3, 1, [m0] ; D4180700 v_interp_p2_f32 v6, [v6], v1, 3, 1, [m0] ; D4190701 v_interp_p1_f32 v7, v0, 0, 2, [m0] ; D41C0800 v_interp_p2_f32 v7, [v7], v1, 0, 2, [m0] ; D41D0801 v_interp_p1_f32 v8, v0, 1, 2, [m0] ; D4200900 v_interp_p2_f32 v8, [v8], v1, 1, 2, [m0] ; D4210901 v_interp_p1_f32 v9, v0, 2, 2, [m0] ; D4240A00 v_interp_p2_f32 v9, [v9], v1, 2, 2, [m0] ; D4250A01 v_interp_p1_f32 v10, v0, 3, 2, [m0] ; D4280B00 v_interp_p2_f32 v10, [v10], v1, 3, 2, [m0] ; D4290B01 v_interp_p1_f32 v11, v0, 0, 3, [m0] ; D42C0C00 v_interp_p2_f32 v11, [v11], v1, 0, 3, [m0] ; D42D0C01 v_interp_p1_f32 v12, v0, 1, 3, [m0] ; D4300D00 v_interp_p2_f32 v12, [v12], v1, 1, 3, [m0] ; D4310D01 v_interp_p1_f32 v13, v0, 2, 3, [m0] ; D4340E00 v_interp_p2_f32 v13, [v13], v1, 2, 3, [m0] ; D4350E01 v_interp_p1_f32 v0, v0, 3, 3, [m0] ; D4000F00 v_interp_p2_f32 v0, [v0], v1, 3, 3, [m0] ; D4010F01 v_mac_f32_e32 v7, v11, v2 ; 2C0E050B v_mac_f32_e32 v8, v12, v3 ; 2C10070C v_mac_f32_e32 v9, v13, v4 ; 2C12090D v_mac_f32_e32 v10, v0, v5 ; 2C140B00 v_mul_f32_e32 v0, v6, v10 ; 0A001506 v_cvt_pkrtz_f16_f32_e64 v1, v7, v8 ; D2960001 00021107 v_cvt_pkrtz_f16_f32_e64 v0, v9, v0 ; D2960000 00020109 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 156 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 ****loading serverbrowser_client.so VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL CONST[0..3] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 6.0000, 1.0000, -0.5800, 10.0000} IMM[1] FLT32 { -2.0000, 3.0000, -1.0000, -0.0000} IMM[2] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0].xw, TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[1].xyyy 3: TEX TEMP[1].y, TEMP[1], SAMP[1], 2D 4: MAD TEMP[0].x, TEMP[1].yyyy, TEMP[0].xxxx, TEMP[0].wwww 5: MAD TEMP[2].x, CONST[3].wwww, IMM[0].xxxx, IMM[0].yyyy 6: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx, IMM[0].zzzz 7: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww 8: MOV_SAT TEMP[2].x, TEMP[0].xxxx 9: MAD TEMP[3].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy 10: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[2].xxxx 11: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx 12: MOV TEMP[2].xy, IN[0].xyyy 13: TEX TEMP[2].xyz, TEMP[2], SAMP[2], 2D 14: MAD TEMP[2].xyz, CONST[3].yyyy, IMM[1].zwww, TEMP[2].xyzz 15: MUL TEMP[1].xyz, IMM[2].xyyy, CONST[3].yyyy 16: MAD TEMP[0].xyz, TEMP[0].xxxx, TEMP[2].xyzz, TEMP[1].xyzz 17: MOV TEMP[0].w, IMM[0].yyyy 18: MOV OUT[0], TEMP[0] 19: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %27 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %28 = load <8 x i32>, <8 x i32> addrspace(2)* %27, align 32, !tbaa !0 %29 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %30 = load <4 x i32>, <4 x i32> addrspace(2)* %29, align 16, !tbaa !0 %31 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %32 = load <8 x i32>, <8 x i32> addrspace(2)* %31, align 32, !tbaa !0 %33 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !tbaa !0 %35 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %36 = load <8 x i32>, <8 x i32> addrspace(2)* %35, align 32, !tbaa !0 %37 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %38 = load <4 x i32>, <4 x i32> addrspace(2)* %37, align 16, !tbaa !0 %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %41 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %42 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %43 = bitcast float %39 to i32 %44 = bitcast float %40 to i32 %45 = insertelement <2 x i32> undef, i32 %43, i32 0 %46 = insertelement <2 x i32> %45, i32 %44, i32 1 %47 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %46, <8 x i32> %28, <4 x i32> %30, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %48 = extractelement <4 x float> %47, i32 0 %49 = extractelement <4 x float> %47, i32 3 %50 = bitcast float %41 to i32 %51 = bitcast float %42 to i32 %52 = insertelement <2 x i32> undef, i32 %50, i32 0 %53 = insertelement <2 x i32> %52, i32 %51, i32 1 %54 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %53, <8 x i32> %32, <4 x i32> %34, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %55 = extractelement <4 x float> %54, i32 1 %56 = fmul float %55, %48 %57 = fadd float %56, %49 %58 = fmul float %26, 6.000000e+00 %59 = fadd float %58, 1.000000e+00 %60 = fmul float %57, %59 %61 = fadd float %60, 0xBFE28F5C20000000 %62 = fmul float %61, 1.000000e+01 %63 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00) %64 = fmul float %63, -2.000000e+00 %65 = fadd float %64, 3.000000e+00 %66 = fmul float %63, %63 %67 = fmul float %66, %65 %68 = bitcast float %39 to i32 %69 = bitcast float %40 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %71, <8 x i32> %36, <4 x i32> %38, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %73 = extractelement <4 x float> %72, i32 0 %74 = extractelement <4 x float> %72, i32 1 %75 = extractelement <4 x float> %72, i32 2 %76 = fsub float %73, %25 %77 = fmul float %25, -0.000000e+00 %78 = fadd float %77, %74 %79 = fmul float %25, -0.000000e+00 %80 = fadd float %79, %75 %81 = fmul float %25, 0.000000e+00 %82 = fmul float %25, 0.000000e+00 %83 = fmul float %67, %76 %84 = fadd float %83, %25 %85 = fmul float %67, %78 %86 = fadd float %85, %81 %87 = fmul float %67, %80 %88 = fadd float %87, %82 %89 = call i32 @llvm.SI.packf16(float %84, float %86) %90 = bitcast i32 %89 to float %91 = call i32 @llvm.SI.packf16(float %88, float 1.000000e+00) %92 = bitcast i32 %91 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %90, float %92, float %90, float %92) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[20:27], s[6:7], 0x20 ; C00E0503 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[28:35], s[6:7], 0x40 ; C00E0703 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[36:39], s[4:5], 0x0 ; C00A0902 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x10 ; C00A0A02 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x20 ; C00A0102 00000020 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x34 ; C0220200 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 0, 1, [m0] ; D4100400 v_interp_p2_f32 v4, [v4], v1, 0, 1, [m0] ; D4110401 v_interp_p1_f32 v5, v0, 1, 1, [m0] ; D4140500 v_interp_p2_f32 v5, [v5], v1, 1, 1, [m0] ; D4150501 image_sample v[0:1], 9, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[36:39] ; F0800900 01230002 s_nop 0 ; BF800000 image_sample v4, 2, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[20:27], s[40:43] ; F0800200 01450404 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v1, v0, v4 ; 2C020900 v_mov_b32_e32 v0, 0x40c00000 ; 7E0002FF 40C00000 s_waitcnt lgkmcnt(0) ; BF8C007F v_mad_f32 v0, v0, s0, 1.0 ; D1C10000 03C80100 v_madak_f32_e32 v0, v1, v0, 0xbf147ae1 ; 30000101 BF147AE1 v_mul_f32_e32 v0, 0x41200000, v0 ; 0A0000FF 41200000 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_madak_f32_e32 v1, -2.0, v0, 0x40400000 ; 300200F5 40400000 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v1, v0 ; 0A000101 image_sample v[1:3], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[28:35], s[4:7] ; F0800700 00270102 s_waitcnt vmcnt(0) ; BF8C0770 v_subrev_f32_e32 v1, s8, v1 ; 06020208 v_mov_b32_e32 v4, 0x80000000 ; 7E0802FF 80000000 v_mad_f32 v2, s8, v4, v2 ; D1C10002 040A0808 v_mac_f32_e32 v3, s8, v4 ; 2C060808 v_mul_f32_e64 v4, 0, s8 ; D1050004 00001080 v_mad_f32 v1, v0, v1, s8 ; D1C10001 00220300 v_mad_f32 v2, v2, v0, v4 ; D1C10002 04120102 v_mac_f32_e32 v4, v3, v0 ; 2C080103 v_cvt_pkrtz_f16_f32_e64 v0, v1, v2 ; D2960000 00020501 v_cvt_pkrtz_f16_f32_e64 v1, v4, 1.0 ; D2960001 0001E504 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 8 Code Size: 324 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL CONST[0..3] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 6.0000, 1.0000, -0.5800, 10.0000} IMM[1] FLT32 { -2.0000, 3.0000, -1.0000, -0.0000} IMM[2] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0].xw, TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[1].xyyy 3: TEX TEMP[1].y, TEMP[1], SAMP[1], 2D 4: MAD TEMP[0].x, TEMP[1].yyyy, TEMP[0].xxxx, TEMP[0].wwww 5: MAD TEMP[2].x, CONST[3].wwww, IMM[0].xxxx, IMM[0].yyyy 6: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx, IMM[0].zzzz 7: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww 8: MOV_SAT TEMP[2].x, TEMP[0].xxxx 9: MAD TEMP[3].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy 10: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[2].xxxx 11: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx 12: MOV TEMP[2].xy, IN[0].xyyy 13: TEX TEMP[2].xyz, TEMP[2], SAMP[2], 2D 14: MAD TEMP[2].xyz, CONST[3].yyyy, IMM[1].zwww, TEMP[2].xyzz 15: MUL TEMP[1].xyz, IMM[2].xyyy, CONST[3].yyyy 16: MAD TEMP[0].xyz, TEMP[0].xxxx, TEMP[2].xyzz, TEMP[1].xyzz 17: MOV TEMP[0].w, IMM[0].yyyy 18: MOV OUT[0], TEMP[0] 19: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %27 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %28 = load <8 x i32>, <8 x i32> addrspace(2)* %27, align 32, !tbaa !0 %29 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %30 = load <4 x i32>, <4 x i32> addrspace(2)* %29, align 16, !tbaa !0 %31 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %32 = load <8 x i32>, <8 x i32> addrspace(2)* %31, align 32, !tbaa !0 %33 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !tbaa !0 %35 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %36 = load <8 x i32>, <8 x i32> addrspace(2)* %35, align 32, !tbaa !0 %37 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %38 = load <4 x i32>, <4 x i32> addrspace(2)* %37, align 16, !tbaa !0 %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %41 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %42 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %43 = bitcast float %39 to i32 %44 = bitcast float %40 to i32 %45 = insertelement <2 x i32> undef, i32 %43, i32 0 %46 = insertelement <2 x i32> %45, i32 %44, i32 1 %47 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %46, <8 x i32> %28, <4 x i32> %30, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %48 = extractelement <4 x float> %47, i32 0 %49 = extractelement <4 x float> %47, i32 3 %50 = bitcast float %41 to i32 %51 = bitcast float %42 to i32 %52 = insertelement <2 x i32> undef, i32 %50, i32 0 %53 = insertelement <2 x i32> %52, i32 %51, i32 1 %54 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %53, <8 x i32> %32, <4 x i32> %34, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %55 = extractelement <4 x float> %54, i32 1 %56 = fmul float %55, %48 %57 = fadd float %56, %49 %58 = fmul float %26, 6.000000e+00 %59 = fadd float %58, 1.000000e+00 %60 = fmul float %57, %59 %61 = fadd float %60, 0xBFE28F5C20000000 %62 = fmul float %61, 1.000000e+01 %63 = call float @llvm.AMDIL.clamp.(float %62, float 0.000000e+00, float 1.000000e+00) %64 = fmul float %63, -2.000000e+00 %65 = fadd float %64, 3.000000e+00 %66 = fmul float %63, %63 %67 = fmul float %66, %65 %68 = bitcast float %39 to i32 %69 = bitcast float %40 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %71, <8 x i32> %36, <4 x i32> %38, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %73 = extractelement <4 x float> %72, i32 0 %74 = extractelement <4 x float> %72, i32 1 %75 = extractelement <4 x float> %72, i32 2 %76 = fsub float %73, %25 %77 = fmul float %25, -0.000000e+00 %78 = fadd float %77, %74 %79 = fmul float %25, -0.000000e+00 %80 = fadd float %79, %75 %81 = fmul float %25, 0.000000e+00 %82 = fmul float %25, 0.000000e+00 %83 = fmul float %67, %76 %84 = fadd float %83, %25 %85 = fmul float %67, %78 %86 = fadd float %85, %81 %87 = fmul float %67, %80 %88 = fadd float %87, %82 %89 = call i32 @llvm.SI.packf16(float %84, float %86) %90 = bitcast i32 %89 to float %91 = call i32 @llvm.SI.packf16(float %88, float 1.000000e+00) %92 = bitcast i32 %91 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %90, float %92, float %90, float %92) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[20:27], s[6:7], 0x20 ; C00E0503 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[28:35], s[6:7], 0x40 ; C00E0703 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[36:39], s[4:5], 0x0 ; C00A0902 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x10 ; C00A0A02 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x20 ; C00A0102 00000020 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x34 ; C0220200 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 0, 1, [m0] ; D4100400 v_interp_p2_f32 v4, [v4], v1, 0, 1, [m0] ; D4110401 v_interp_p1_f32 v5, v0, 1, 1, [m0] ; D4140500 v_interp_p2_f32 v5, [v5], v1, 1, 1, [m0] ; D4150501 image_sample v[0:1], 9, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[36:39] ; F0800900 01230002 s_nop 0 ; BF800000 image_sample v4, 2, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[20:27], s[40:43] ; F0800200 01450404 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v1, v0, v4 ; 2C020900 v_mov_b32_e32 v0, 0x40c00000 ; 7E0002FF 40C00000 s_waitcnt lgkmcnt(0) ; BF8C007F v_mad_f32 v0, v0, s0, 1.0 ; D1C10000 03C80100 v_madak_f32_e32 v0, v1, v0, 0xbf147ae1 ; 30000101 BF147AE1 v_mul_f32_e32 v0, 0x41200000, v0 ; 0A0000FF 41200000 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_madak_f32_e32 v1, -2.0, v0, 0x40400000 ; 300200F5 40400000 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v1, v0 ; 0A000101 image_sample v[1:3], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[28:35], s[4:7] ; F0800700 00270102 s_waitcnt vmcnt(0) ; BF8C0770 v_subrev_f32_e32 v1, s8, v1 ; 06020208 v_mov_b32_e32 v4, 0x80000000 ; 7E0802FF 80000000 v_mad_f32 v2, s8, v4, v2 ; D1C10002 040A0808 v_mac_f32_e32 v3, s8, v4 ; 2C060808 v_mul_f32_e64 v4, 0, s8 ; D1050004 00001080 v_mad_f32 v1, v0, v1, s8 ; D1C10001 00220300 v_mad_f32 v2, v2, v0, v4 ; D1C10002 04120102 v_mac_f32_e32 v4, v3, v0 ; 2C080103 v_cvt_pkrtz_f16_f32_e64 v0, v1, v2 ; D2960000 00020501 v_cvt_pkrtz_f16_f32_e64 v1, v4, 1.0 ; D2960001 0001E504 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 8 Code Size: 324 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], 2D, FLOAT DCL SVIEW[5], 2D, FLOAT DCL SVIEW[6], 2D, FLOAT DCL CONST[0..11] DCL TEMP[0..8], LOCAL IMM[0] FLT32 { 1.0000, -1.0000, 0.0588, 16.0000} IMM[1] FLT32 { -0.0011, 0.9960, 0.0020, 0.9966} IMM[2] FLT32 { 0.0040, 0.9989, -0.0007, 0.9973} IMM[3] FLT32 { 0.0010, 0.9983, 0.0027, 0.9993} IMM[4] FLT32 { -0.0034, 0.9980, -0.0017, 0.9990} IMM[5] FLT32 { 0.0000, 1.0000, 0.0017, 1.0010} IMM[6] FLT32 { 0.0034, 1.0020, -0.0027, 1.0007} IMM[7] FLT32 { -0.0010, 1.0017, 0.0007, 1.0027} IMM[8] FLT32 { -0.0040, 1.0011, -0.0020, 1.0034} IMM[9] FLT32 { 0.0011, 1.0040, 2.0000, 7.0000} IMM[10] FLT32 { 0.0600, 0.1200, 0.1800, 6.0000} IMM[11] FLT32 { -0.0600, -0.1200, -0.1800, -0.5800} IMM[12] FLT32 { 0.5600, -0.0200, 0.5400, 0.5200} IMM[13] FLT32 { 10.0000, -2.0000, 3.0000, 0.7500} IMM[14] FLT32 { 0.2500, 0.3000, 0.5900, 0.1100} IMM[15] FLT32 { -0.0800, 14.2857, 0.0300, 0.5000} IMM[16] FLT32 { -0.9000, -0.0100, 10.0000, -100.0000} 0: MAD TEMP[0], IN[0].xyxy, IMM[0].xyxy, IMM[1] 1: MOV TEMP[1].xy, TEMP[0].zwww 2: TEX TEMP[1], TEMP[1], SAMP[5], 2D 3: MUL TEMP[1], TEMP[1], IMM[0].zzzz 4: MOV TEMP[2].xy, TEMP[0].xyyy 5: TEX TEMP[2], TEMP[2], SAMP[5], 2D 6: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[1] 7: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[2] 8: MOV TEMP[2].xy, TEMP[1].xyyy 9: TEX TEMP[2], TEMP[2], SAMP[5], 2D 10: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 11: MOV TEMP[2].xy, TEMP[1].zwww 12: TEX TEMP[2], TEMP[2], SAMP[5], 2D 13: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 14: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[3] 15: MOV TEMP[2].xy, TEMP[1].xyyy 16: TEX TEMP[2], TEMP[2], SAMP[5], 2D 17: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 18: MOV TEMP[2].xy, TEMP[1].zwww 19: TEX TEMP[2], TEMP[2], SAMP[5], 2D 20: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 21: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[4] 22: MOV TEMP[2].xy, TEMP[1].xyyy 23: TEX TEMP[2], TEMP[2], SAMP[5], 2D 24: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 25: MOV TEMP[2].xy, TEMP[1].zwww 26: TEX TEMP[2], TEMP[2], SAMP[5], 2D 27: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 28: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[5] 29: MOV TEMP[2].xy, TEMP[1].xyyy 30: TEX TEMP[2], TEMP[2], SAMP[5], 2D 31: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 32: MOV TEMP[2].xy, TEMP[1].zwww 33: TEX TEMP[2], TEMP[2], SAMP[5], 2D 34: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 35: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[6] 36: MOV TEMP[2].xy, TEMP[1].xyyy 37: TEX TEMP[2], TEMP[2], SAMP[5], 2D 38: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 39: MOV TEMP[2].xy, TEMP[1].zwww 40: TEX TEMP[2], TEMP[2], SAMP[5], 2D 41: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 42: MAD TEMP[1], IN[0].xyxy, IMM[0].xyxy, IMM[7] 43: MOV TEMP[2].xy, TEMP[1].xyyy 44: TEX TEMP[2], TEMP[2], SAMP[5], 2D 45: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 46: MOV TEMP[2].xy, TEMP[1].zwww 47: TEX TEMP[2], TEMP[2], SAMP[5], 2D 48: MAD TEMP[0], TEMP[2], IMM[0].zzzz, TEMP[0] 49: MAD TEMP[2], IN[0].xyxy, IMM[0].xyxy, IMM[8] 50: MOV TEMP[3].xy, TEMP[2].xyyy 51: TEX TEMP[3], TEMP[3], SAMP[5], 2D 52: MAD TEMP[0], TEMP[3], IMM[0].zzzz, TEMP[0] 53: MOV TEMP[3].xy, TEMP[2].zwww 54: TEX TEMP[3], TEMP[3], SAMP[5], 2D 55: MAD TEMP[2], TEMP[3], IMM[0].zzzz, TEMP[0] 56: MAD TEMP[0].xy, IN[0].xyyy, IMM[0].xyyy, IMM[9].xyyy 57: MOV TEMP[3].xy, TEMP[0].xyyy 58: TEX TEMP[3], TEMP[3], SAMP[5], 2D 59: MAD TEMP[2], TEMP[3], IMM[0].zzzz, TEMP[2] 60: MUL TEMP[3].x, TEMP[2].wwww, IMM[0].wwww 61: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[2].xyzz 62: DP2 TEMP[3].x, TEMP[2].yzzz, CONST[10].xyyy 63: ADD TEMP[0].x, TEMP[3].xxxx, CONST[10].wwww 64: DP2 TEMP[3].x, TEMP[2].yzzz, CONST[11].xyyy 65: ADD TEMP[3].x, TEMP[3].xxxx, CONST[11].wwww 66: MOV TEMP[0].y, TEMP[3].xxxx 67: MOV TEMP[3].xy, TEMP[0].xyyy 68: TEX TEMP[3].xyz, TEMP[3], SAMP[6], 2D 69: DP2 TEMP[4].x, TEMP[2].xzzz, CONST[10].xyyy 70: ADD TEMP[1].x, TEMP[4].xxxx, CONST[10].wwww 71: DP2 TEMP[4].x, TEMP[2].xzzz, CONST[11].xyyy 72: ADD TEMP[4].x, TEMP[4].xxxx, CONST[11].wwww 73: MOV TEMP[1].y, TEMP[4].xxxx 74: MOV TEMP[4].xy, IN[0].xyyy 75: TEX TEMP[4].xyz, TEMP[4], SAMP[4], 2D 76: MAD TEMP[4].xyz, TEMP[4].xyzz, IMM[9].zzzz, IMM[0].yyyy 77: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 78: RSQ TEMP[5].x, TEMP[5].xxxx 79: MUL TEMP[5].xy, TEMP[5].xxxx, TEMP[4].yzzz 80: ABS TEMP[6].x, TEMP[5].xxxx 81: POW TEMP[6].x, TEMP[6].xxxx, IMM[9].wwww 82: MOV TEMP[7].xy, TEMP[1].xyyy 83: TEX TEMP[7].xyz, TEMP[7], SAMP[6], 2D 84: LRP TEMP[4].xyz, TEMP[6].xxxx, TEMP[7].xyzz, TEMP[3].xyzz 85: DP2 TEMP[3].x, TEMP[2].yxxx, CONST[10].xyyy 86: ADD TEMP[0].x, TEMP[3].xxxx, CONST[10].wwww 87: DP2 TEMP[3].x, TEMP[2].yxxx, CONST[11].xyyy 88: ADD TEMP[3].x, TEMP[3].xxxx, CONST[11].wwww 89: MOV TEMP[0].y, TEMP[3].xxxx 90: MOV TEMP[3].xy, TEMP[0].xyyy 91: TEX TEMP[3].xyz, TEMP[3], SAMP[6], 2D 92: ABS TEMP[5].x, TEMP[5].yyyy 93: POW TEMP[5].x, TEMP[5].xxxx, IMM[9].wwww 94: LRP TEMP[0].xyz, TEMP[5].xxxx, TEMP[3].xyzz, TEMP[4].xyzz 95: MAD TEMP[1], CONST[3].wwww, IMM[11].xxyz, IMM[12] 96: ADD TEMP[2].xy, -TEMP[1].xzzz, TEMP[1].zwww 97: RCP TEMP[2].x, TEMP[2].xxxx 98: RCP TEMP[3].x, TEMP[2].yyyy 99: MOV TEMP[2].y, TEMP[3].xxxx 100: MAD TEMP[3].x, CONST[3].wwww, IMM[10].wwww, IMM[0].xxxx 101: MOV TEMP[5].xy, IN[1].xyyy 102: TEX TEMP[5].y, TEMP[5], SAMP[1], 2D 103: MOV TEMP[6].xy, IN[0].xyyy 104: TEX TEMP[6], TEMP[6], SAMP[0], 2D 105: MAD TEMP[5].x, TEMP[5].yyyy, TEMP[6].xxxx, TEMP[6].wwww 106: MAD TEMP[7].xy, TEMP[5].xxxx, TEMP[3].xxxx, -TEMP[1].xzzz 107: MAD TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx, IMM[11].wwww 108: RCP TEMP[5].x, TEMP[1].yyyy 109: MUL TEMP[5].x, TEMP[3].xxxx, TEMP[5].xxxx 110: MOV_SAT TEMP[5].x, TEMP[5].xxxx 111: MUL TEMP[3].x, TEMP[3].xxxx, IMM[13].xxxx 112: MOV_SAT TEMP[3].x, TEMP[3].xxxx 113: MUL TEMP[2].xy, TEMP[2].xyyy, TEMP[7].xyyy 114: MOV_SAT TEMP[7].xy, TEMP[2].xyyy 115: MAD TEMP[1].x, TEMP[7].xxxx, IMM[13].yyyy, IMM[13].zzzz 116: MUL TEMP[2].x, TEMP[7].xxxx, TEMP[7].xxxx 117: MUL TEMP[8].x, TEMP[2].xxxx, TEMP[1].xxxx 118: MOV TEMP[1].y, TEMP[8].xxxx 119: MAD TEMP[2].x, TEMP[7].yyyy, IMM[13].yyyy, IMM[13].zzzz 120: MUL TEMP[7].x, TEMP[7].yyyy, TEMP[7].yyyy 121: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].xxxx 122: MOV TEMP[1].z, TEMP[7].xxxx 123: MAD TEMP[2].x, TEMP[5].xxxx, IMM[13].yyyy, IMM[13].zzzz 124: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 125: MUL TEMP[1].x, TEMP[5].xxxx, TEMP[2].xxxx 126: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz 127: ADD TEMP[1].xyz, -CONST[0].xyzz, CONST[1].xyzz 128: MAD TEMP[1].xyz, TEMP[0].xxxx, TEMP[1].xyzz, CONST[0].xyzz 129: LRP TEMP[4].xyz, TEMP[0].yyyy, CONST[2].xyzz, TEMP[1].xyzz 130: ADD TEMP[1].x, -TEMP[4].xxxx, CONST[0].wwww 131: ADD TEMP[5].x, -TEMP[4].yyyy, CONST[1].wwww 132: MOV TEMP[1].y, TEMP[5].xxxx 133: ADD TEMP[5].x, -TEMP[4].zzzz, CONST[2].wwww 134: MOV TEMP[1].z, TEMP[5].xxxx 135: MAD TEMP[0].xyz, TEMP[0].zzzz, TEMP[1].xyzz, TEMP[4].xyzz 136: MUL TEMP[2].x, CONST[3].wwww, IMM[13].wwww 137: ADD TEMP[5].x, -TEMP[6].xxxx, IMM[0].xxxx 138: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 139: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 140: MAD TEMP[2].x, TEMP[5].xxxx, IMM[14].xxxx, TEMP[2].xxxx 141: MOV TEMP[5].xy, IN[1].zwww 142: TEX TEMP[5], TEMP[5], SAMP[3], 2D 143: ADD TEMP[5], TEMP[5], IMM[0].yyyy 144: MAD TEMP[4], TEMP[2].xxxx, TEMP[5], IMM[0].xxxx 145: MUL TEMP[5].xyz, TEMP[0].xyzz, TEMP[4].xyzz 146: DP3 TEMP[7].x, TEMP[5].xyzz, IMM[14].yzww 147: ADD TEMP[0].x, TEMP[7].xxxx, IMM[15].xxxx 148: MUL TEMP[0].x, TEMP[0].xxxx, IMM[15].yyyy 149: MOV_SAT TEMP[7].x, TEMP[0].xxxx 150: MAD TEMP[8].x, TEMP[7].xxxx, IMM[13].yyyy, IMM[13].zzzz 151: MUL TEMP[0].x, TEMP[7].xxxx, TEMP[7].xxxx 152: MAD TEMP[0].x, TEMP[8].xxxx, -TEMP[0].xxxx, IMM[0].xxxx 153: MAD TEMP[0].xyz, TEMP[0].xxxx, IMM[15].zzzz, TEMP[5].xyzz 154: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[6].zzzz 155: MAD TEMP[5].xyz, TEMP[0].xyzz, IMM[15].wwww, TEMP[5].xyzz 156: MOV_SAT TEMP[5].xyz, TEMP[5].xyzz 157: MUL TEMP[0].xyz, TEMP[6].yyyy, TEMP[5].xyzz 158: MOV TEMP[7].xy, IN[0].xyyy 159: TEX TEMP[7], TEMP[7], SAMP[2], 2D 160: MAD TEMP[5].xyz, TEMP[5].xyzz, -TEMP[6].yyyy, TEMP[7].xyzz 161: MUL TEMP[6].x, TEMP[6].yyyy, CONST[3].zzzz 162: MUL TEMP[4].x, TEMP[4].wwww, TEMP[6].xxxx 163: MAD TEMP[1].x, TEMP[3].xxxx, IMM[13].yyyy, IMM[13].zzzz 164: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx 165: MUL TEMP[6].x, TEMP[3].xxxx, TEMP[1].xxxx 166: MAD TEMP[1].xy, TEMP[1].xxxx, TEMP[3].xxxx, IMM[16].xyyy 167: MUL TEMP[1].xy, TEMP[1].xyyy, IMM[16].zwww 168: MAD TEMP[0].xyz, TEMP[6].xxxx, TEMP[5].xyzz, TEMP[0].xyzz 169: MAX TEMP[3].x, TEMP[1].yyyy, IMM[5].xxxx 170: MOV_SAT TEMP[1].x, TEMP[1].xxxx 171: MAD TEMP[5].x, TEMP[3].xxxx, IMM[13].yyyy, IMM[13].zzzz 172: MUL TEMP[2].x, TEMP[3].xxxx, TEMP[3].xxxx 173: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx 174: MAD TEMP[3].x, TEMP[4].xxxx, -TEMP[2].xxxx, TEMP[7].wwww 175: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx 176: MAD TEMP[4].x, TEMP[1].xxxx, IMM[13].yyyy, IMM[13].zzzz 177: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx 178: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx 179: MAD TEMP[1].x, TEMP[1].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 180: MOV TEMP[0].w, TEMP[1].xxxx 181: MOV OUT[0], TEMP[0] 182: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 40) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 44) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 56) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 172) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 180) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %45 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %46 = load <8 x i32>, <8 x i32> addrspace(2)* %45, align 32, !tbaa !0 %47 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %48 = load <4 x i32>, <4 x i32> addrspace(2)* %47, align 16, !tbaa !0 %49 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %50 = load <8 x i32>, <8 x i32> addrspace(2)* %49, align 32, !tbaa !0 %51 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %52 = load <4 x i32>, <4 x i32> addrspace(2)* %51, align 16, !tbaa !0 %53 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %54 = load <8 x i32>, <8 x i32> addrspace(2)* %53, align 32, !tbaa !0 %55 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %56 = load <4 x i32>, <4 x i32> addrspace(2)* %55, align 16, !tbaa !0 %57 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %58 = load <8 x i32>, <8 x i32> addrspace(2)* %57, align 32, !tbaa !0 %59 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %60 = load <4 x i32>, <4 x i32> addrspace(2)* %59, align 16, !tbaa !0 %61 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %62 = load <8 x i32>, <8 x i32> addrspace(2)* %61, align 32, !tbaa !0 %63 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %64 = load <4 x i32>, <4 x i32> addrspace(2)* %63, align 16, !tbaa !0 %65 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 5 %66 = load <8 x i32>, <8 x i32> addrspace(2)* %65, align 32, !tbaa !0 %67 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 5 %68 = load <4 x i32>, <4 x i32> addrspace(2)* %67, align 16, !tbaa !0 %69 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 6 %70 = load <8 x i32>, <8 x i32> addrspace(2)* %69, align 32, !tbaa !0 %71 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 6 %72 = load <4 x i32>, <4 x i32> addrspace(2)* %71, align 16, !tbaa !0 %73 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %74 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %75 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %76 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %77 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %78 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %79 = fadd float %73, 0xBF5191B840000000 %80 = fsub float 0x3FEFDF3720000000, %74 %81 = fadd float %73, 0x3F5FFFFAA0000000 %82 = fsub float 0x3FEFE44980000000, %74 %83 = bitcast float %81 to i32 %84 = bitcast float %82 to i32 %85 = insertelement <2 x i32> undef, i32 %83, i32 0 %86 = insertelement <2 x i32> %85, i32 %84, i32 1 %87 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %86, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %88 = extractelement <4 x float> %87, i32 0 %89 = extractelement <4 x float> %87, i32 1 %90 = extractelement <4 x float> %87, i32 2 %91 = extractelement <4 x float> %87, i32 3 %92 = fmul float %88, 0x3FAE1E1E20000000 %93 = fmul float %89, 0x3FAE1E1E20000000 %94 = fmul float %90, 0x3FAE1E1E20000000 %95 = fmul float %91, 0x3FAE1E1E20000000 %96 = bitcast float %79 to i32 %97 = bitcast float %80 to i32 %98 = insertelement <2 x i32> undef, i32 %96, i32 0 %99 = insertelement <2 x i32> %98, i32 %97, i32 1 %100 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %99, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = extractelement <4 x float> %100, i32 2 %104 = extractelement <4 x float> %100, i32 3 %105 = fmul float %101, 0x3FAE1E1E20000000 %106 = fadd float %105, %92 %107 = fmul float %102, 0x3FAE1E1E20000000 %108 = fadd float %107, %93 %109 = fmul float %103, 0x3FAE1E1E20000000 %110 = fadd float %109, %94 %111 = fmul float %104, 0x3FAE1E1E20000000 %112 = fadd float %111, %95 %113 = fadd float %73, 0x3F70646EC0000000 %114 = fsub float 0x3FEFF73720000000, %74 %115 = fadd float %73, 0xBF476CFB80000000 %116 = fsub float 0x3FEFEA24C0000000, %74 %117 = bitcast float %113 to i32 %118 = bitcast float %114 to i32 %119 = insertelement <2 x i32> undef, i32 %117, i32 0 %120 = insertelement <2 x i32> %119, i32 %118, i32 1 %121 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %120, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %122 = extractelement <4 x float> %121, i32 0 %123 = extractelement <4 x float> %121, i32 1 %124 = extractelement <4 x float> %121, i32 2 %125 = extractelement <4 x float> %121, i32 3 %126 = fmul float %122, 0x3FAE1E1E20000000 %127 = fadd float %126, %106 %128 = fmul float %123, 0x3FAE1E1E20000000 %129 = fadd float %128, %108 %130 = fmul float %124, 0x3FAE1E1E20000000 %131 = fadd float %130, %110 %132 = fmul float %125, 0x3FAE1E1E20000000 %133 = fadd float %132, %112 %134 = bitcast float %115 to i32 %135 = bitcast float %116 to i32 %136 = insertelement <2 x i32> undef, i32 %134, i32 0 %137 = insertelement <2 x i32> %136, i32 %135, i32 1 %138 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %137, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %139 = extractelement <4 x float> %138, i32 0 %140 = extractelement <4 x float> %138, i32 1 %141 = extractelement <4 x float> %138, i32 2 %142 = extractelement <4 x float> %138, i32 3 %143 = fmul float %139, 0x3FAE1E1E20000000 %144 = fadd float %143, %127 %145 = fmul float %140, 0x3FAE1E1E20000000 %146 = fadd float %145, %129 %147 = fmul float %141, 0x3FAE1E1E20000000 %148 = fadd float %147, %131 %149 = fmul float %142, 0x3FAE1E1E20000000 %150 = fadd float %149, %133 %151 = fadd float %73, 0x3F500002A0000000 %152 = fsub float 0x3FEFF224C0000000, %74 %153 = fadd float %73, 0x3F65DB3E60000000 %154 = fsub float 0x3FEFFA24C0000000, %74 %155 = bitcast float %151 to i32 %156 = bitcast float %152 to i32 %157 = insertelement <2 x i32> undef, i32 %155, i32 0 %158 = insertelement <2 x i32> %157, i32 %156, i32 1 %159 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %158, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %160 = extractelement <4 x float> %159, i32 0 %161 = extractelement <4 x float> %159, i32 1 %162 = extractelement <4 x float> %159, i32 2 %163 = extractelement <4 x float> %159, i32 3 %164 = fmul float %160, 0x3FAE1E1E20000000 %165 = fadd float %164, %144 %166 = fmul float %161, 0x3FAE1E1E20000000 %167 = fadd float %166, %146 %168 = fmul float %162, 0x3FAE1E1E20000000 %169 = fadd float %168, %148 %170 = fmul float %163, 0x3FAE1E1E20000000 %171 = fadd float %170, %150 %172 = bitcast float %153 to i32 %173 = bitcast float %154 to i32 %174 = insertelement <2 x i32> undef, i32 %172, i32 0 %175 = insertelement <2 x i32> %174, i32 %173, i32 1 %176 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %175, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %177 = extractelement <4 x float> %176, i32 0 %178 = extractelement <4 x float> %176, i32 1 %179 = extractelement <4 x float> %176, i32 2 %180 = extractelement <4 x float> %176, i32 3 %181 = fmul float %177, 0x3FAE1E1E20000000 %182 = fadd float %181, %165 %183 = fmul float %178, 0x3FAE1E1E20000000 %184 = fadd float %183, %167 %185 = fmul float %179, 0x3FAE1E1E20000000 %186 = fadd float %185, %169 %187 = fmul float %180, 0x3FAE1E1E20000000 %188 = fadd float %187, %171 %189 = fadd float %73, 0xBF6BB67A00000000 %190 = fsub float 0x3FEFF00000000000, %74 %191 = fadd float %73, 0xBF5BB67F60000000 %192 = fsub float 0x3FEFF80000000000, %74 %193 = bitcast float %189 to i32 %194 = bitcast float %190 to i32 %195 = insertelement <2 x i32> undef, i32 %193, i32 0 %196 = insertelement <2 x i32> %195, i32 %194, i32 1 %197 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %196, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %198 = extractelement <4 x float> %197, i32 0 %199 = extractelement <4 x float> %197, i32 1 %200 = extractelement <4 x float> %197, i32 2 %201 = extractelement <4 x float> %197, i32 3 %202 = fmul float %198, 0x3FAE1E1E20000000 %203 = fadd float %202, %182 %204 = fmul float %199, 0x3FAE1E1E20000000 %205 = fadd float %204, %184 %206 = fmul float %200, 0x3FAE1E1E20000000 %207 = fadd float %206, %186 %208 = fmul float %201, 0x3FAE1E1E20000000 %209 = fadd float %208, %188 %210 = bitcast float %191 to i32 %211 = bitcast float %192 to i32 %212 = insertelement <2 x i32> undef, i32 %210, i32 0 %213 = insertelement <2 x i32> %212, i32 %211, i32 1 %214 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %213, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fmul float %215, 0x3FAE1E1E20000000 %220 = fadd float %219, %203 %221 = fmul float %216, 0x3FAE1E1E20000000 %222 = fadd float %221, %205 %223 = fmul float %217, 0x3FAE1E1E20000000 %224 = fadd float %223, %207 %225 = fmul float %218, 0x3FAE1E1E20000000 %226 = fadd float %225, %209 %227 = fadd float %73, 0.000000e+00 %228 = fsub float 1.000000e+00, %74 %229 = fadd float %73, 0x3F5BB67F60000000 %230 = fsub float 0x3FF0040000000000, %74 %231 = bitcast float %227 to i32 %232 = bitcast float %228 to i32 %233 = insertelement <2 x i32> undef, i32 %231, i32 0 %234 = insertelement <2 x i32> %233, i32 %232, i32 1 %235 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %234, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %236 = extractelement <4 x float> %235, i32 0 %237 = extractelement <4 x float> %235, i32 1 %238 = extractelement <4 x float> %235, i32 2 %239 = extractelement <4 x float> %235, i32 3 %240 = fmul float %236, 0x3FAE1E1E20000000 %241 = fadd float %240, %220 %242 = fmul float %237, 0x3FAE1E1E20000000 %243 = fadd float %242, %222 %244 = fmul float %238, 0x3FAE1E1E20000000 %245 = fadd float %244, %224 %246 = fmul float %239, 0x3FAE1E1E20000000 %247 = fadd float %246, %226 %248 = bitcast float %229 to i32 %249 = bitcast float %230 to i32 %250 = insertelement <2 x i32> undef, i32 %248, i32 0 %251 = insertelement <2 x i32> %250, i32 %249, i32 1 %252 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %251, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %253 = extractelement <4 x float> %252, i32 0 %254 = extractelement <4 x float> %252, i32 1 %255 = extractelement <4 x float> %252, i32 2 %256 = extractelement <4 x float> %252, i32 3 %257 = fmul float %253, 0x3FAE1E1E20000000 %258 = fadd float %257, %241 %259 = fmul float %254, 0x3FAE1E1E20000000 %260 = fadd float %259, %243 %261 = fmul float %255, 0x3FAE1E1E20000000 %262 = fadd float %261, %245 %263 = fmul float %256, 0x3FAE1E1E20000000 %264 = fadd float %263, %247 %265 = fadd float %73, 0x3F6BB67A00000000 %266 = fsub float 0x3FF0080000000000, %74 %267 = fadd float %73, 0xBF65DB3E60000000 %268 = fsub float 0x3FF002EDA0000000, %74 %269 = bitcast float %265 to i32 %270 = bitcast float %266 to i32 %271 = insertelement <2 x i32> undef, i32 %269, i32 0 %272 = insertelement <2 x i32> %271, i32 %270, i32 1 %273 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %272, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %274 = extractelement <4 x float> %273, i32 0 %275 = extractelement <4 x float> %273, i32 1 %276 = extractelement <4 x float> %273, i32 2 %277 = extractelement <4 x float> %273, i32 3 %278 = fmul float %274, 0x3FAE1E1E20000000 %279 = fadd float %278, %258 %280 = fmul float %275, 0x3FAE1E1E20000000 %281 = fadd float %280, %260 %282 = fmul float %276, 0x3FAE1E1E20000000 %283 = fadd float %282, %262 %284 = fmul float %277, 0x3FAE1E1E20000000 %285 = fadd float %284, %264 %286 = bitcast float %267 to i32 %287 = bitcast float %268 to i32 %288 = insertelement <2 x i32> undef, i32 %286, i32 0 %289 = insertelement <2 x i32> %288, i32 %287, i32 1 %290 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %289, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %291 = extractelement <4 x float> %290, i32 0 %292 = extractelement <4 x float> %290, i32 1 %293 = extractelement <4 x float> %290, i32 2 %294 = extractelement <4 x float> %290, i32 3 %295 = fmul float %291, 0x3FAE1E1E20000000 %296 = fadd float %295, %279 %297 = fmul float %292, 0x3FAE1E1E20000000 %298 = fadd float %297, %281 %299 = fmul float %293, 0x3FAE1E1E20000000 %300 = fadd float %299, %283 %301 = fmul float %294, 0x3FAE1E1E20000000 %302 = fadd float %301, %285 %303 = fadd float %73, 0xBF500002A0000000 %304 = fsub float 0x3FF006EDA0000000, %74 %305 = fadd float %73, 0x3F476CFB80000000 %306 = fsub float 0x3FF00AEDA0000000, %74 %307 = bitcast float %303 to i32 %308 = bitcast float %304 to i32 %309 = insertelement <2 x i32> undef, i32 %307, i32 0 %310 = insertelement <2 x i32> %309, i32 %308, i32 1 %311 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %310, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %312 = extractelement <4 x float> %311, i32 0 %313 = extractelement <4 x float> %311, i32 1 %314 = extractelement <4 x float> %311, i32 2 %315 = extractelement <4 x float> %311, i32 3 %316 = fmul float %312, 0x3FAE1E1E20000000 %317 = fadd float %316, %296 %318 = fmul float %313, 0x3FAE1E1E20000000 %319 = fadd float %318, %298 %320 = fmul float %314, 0x3FAE1E1E20000000 %321 = fadd float %320, %300 %322 = fmul float %315, 0x3FAE1E1E20000000 %323 = fadd float %322, %302 %324 = bitcast float %305 to i32 %325 = bitcast float %306 to i32 %326 = insertelement <2 x i32> undef, i32 %324, i32 0 %327 = insertelement <2 x i32> %326, i32 %325, i32 1 %328 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %327, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %329 = extractelement <4 x float> %328, i32 0 %330 = extractelement <4 x float> %328, i32 1 %331 = extractelement <4 x float> %328, i32 2 %332 = extractelement <4 x float> %328, i32 3 %333 = fmul float %329, 0x3FAE1E1E20000000 %334 = fadd float %333, %317 %335 = fmul float %330, 0x3FAE1E1E20000000 %336 = fadd float %335, %319 %337 = fmul float %331, 0x3FAE1E1E20000000 %338 = fadd float %337, %321 %339 = fmul float %332, 0x3FAE1E1E20000000 %340 = fadd float %339, %323 %341 = fadd float %73, 0xBF70646EC0000000 %342 = fsub float 0x3FF0046460000000, %74 %343 = fadd float %73, 0xBF5FFFFAA0000000 %344 = fsub float 0x3FF00DDB40000000, %74 %345 = bitcast float %341 to i32 %346 = bitcast float %342 to i32 %347 = insertelement <2 x i32> undef, i32 %345, i32 0 %348 = insertelement <2 x i32> %347, i32 %346, i32 1 %349 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %348, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %350 = extractelement <4 x float> %349, i32 0 %351 = extractelement <4 x float> %349, i32 1 %352 = extractelement <4 x float> %349, i32 2 %353 = extractelement <4 x float> %349, i32 3 %354 = fmul float %350, 0x3FAE1E1E20000000 %355 = fadd float %354, %334 %356 = fmul float %351, 0x3FAE1E1E20000000 %357 = fadd float %356, %336 %358 = fmul float %352, 0x3FAE1E1E20000000 %359 = fadd float %358, %338 %360 = fmul float %353, 0x3FAE1E1E20000000 %361 = fadd float %360, %340 %362 = bitcast float %343 to i32 %363 = bitcast float %344 to i32 %364 = insertelement <2 x i32> undef, i32 %362, i32 0 %365 = insertelement <2 x i32> %364, i32 %363, i32 1 %366 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %365, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %367 = extractelement <4 x float> %366, i32 0 %368 = extractelement <4 x float> %366, i32 1 %369 = extractelement <4 x float> %366, i32 2 %370 = extractelement <4 x float> %366, i32 3 %371 = fmul float %367, 0x3FAE1E1E20000000 %372 = fadd float %371, %355 %373 = fmul float %368, 0x3FAE1E1E20000000 %374 = fadd float %373, %357 %375 = fmul float %369, 0x3FAE1E1E20000000 %376 = fadd float %375, %359 %377 = fmul float %370, 0x3FAE1E1E20000000 %378 = fadd float %377, %361 %379 = fadd float %73, 0x3F5191B840000000 %380 = fsub float 0x3FF0106460000000, %74 %381 = bitcast float %379 to i32 %382 = bitcast float %380 to i32 %383 = insertelement <2 x i32> undef, i32 %381, i32 0 %384 = insertelement <2 x i32> %383, i32 %382, i32 1 %385 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %384, <8 x i32> %66, <4 x i32> %68, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %386 = extractelement <4 x float> %385, i32 0 %387 = extractelement <4 x float> %385, i32 1 %388 = extractelement <4 x float> %385, i32 2 %389 = extractelement <4 x float> %385, i32 3 %390 = fmul float %386, 0x3FAE1E1E20000000 %391 = fadd float %390, %372 %392 = fmul float %387, 0x3FAE1E1E20000000 %393 = fadd float %392, %374 %394 = fmul float %388, 0x3FAE1E1E20000000 %395 = fadd float %394, %376 %396 = fmul float %389, 0x3FAE1E1E20000000 %397 = fadd float %396, %378 %398 = fmul float %397, 1.600000e+01 %399 = fmul float %398, %391 %400 = fmul float %398, %393 %401 = fmul float %398, %395 %402 = fmul float %400, %39 %403 = fmul float %401, %40 %404 = fadd float %402, %403 %405 = fadd float %404, %41 %406 = fmul float %400, %42 %407 = fmul float %401, %43 %408 = fadd float %406, %407 %409 = fadd float %408, %44 %410 = bitcast float %405 to i32 %411 = bitcast float %409 to i32 %412 = insertelement <2 x i32> undef, i32 %410, i32 0 %413 = insertelement <2 x i32> %412, i32 %411, i32 1 %414 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %413, <8 x i32> %70, <4 x i32> %72, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %415 = extractelement <4 x float> %414, i32 0 %416 = extractelement <4 x float> %414, i32 1 %417 = extractelement <4 x float> %414, i32 2 %418 = fmul float %399, %39 %419 = fmul float %401, %40 %420 = fadd float %418, %419 %421 = fadd float %420, %41 %422 = fmul float %399, %42 %423 = fmul float %401, %43 %424 = fadd float %422, %423 %425 = fadd float %424, %44 %426 = bitcast float %73 to i32 %427 = bitcast float %74 to i32 %428 = insertelement <2 x i32> undef, i32 %426, i32 0 %429 = insertelement <2 x i32> %428, i32 %427, i32 1 %430 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %429, <8 x i32> %62, <4 x i32> %64, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %431 = extractelement <4 x float> %430, i32 0 %432 = extractelement <4 x float> %430, i32 1 %433 = extractelement <4 x float> %430, i32 2 %434 = fmul float %431, 2.000000e+00 %435 = fadd float %434, -1.000000e+00 %436 = fmul float %432, 2.000000e+00 %437 = fadd float %436, -1.000000e+00 %438 = fmul float %433, 2.000000e+00 %439 = fadd float %438, -1.000000e+00 %440 = fmul float %435, %435 %441 = fmul float %437, %437 %442 = fadd float %441, %440 %443 = fmul float %439, %439 %444 = fadd float %442, %443 %445 = call float @llvm.AMDGPU.rsq.clamped.f32(float %444) %446 = fmul float %445, %437 %447 = fmul float %445, %439 %448 = call float @llvm.fabs.f32(float %446) %449 = call float @llvm.pow.f32(float %448, float 7.000000e+00) %450 = bitcast float %421 to i32 %451 = bitcast float %425 to i32 %452 = insertelement <2 x i32> undef, i32 %450, i32 0 %453 = insertelement <2 x i32> %452, i32 %451, i32 1 %454 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %453, <8 x i32> %70, <4 x i32> %72, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %455 = extractelement <4 x float> %454, i32 0 %456 = extractelement <4 x float> %454, i32 1 %457 = extractelement <4 x float> %454, i32 2 %458 = fsub float 1.000000e+00, %449 %459 = fmul float %455, %449 %460 = fmul float %415, %458 %461 = fadd float %459, %460 %462 = fsub float 1.000000e+00, %449 %463 = fmul float %456, %449 %464 = fmul float %416, %462 %465 = fadd float %463, %464 %466 = fsub float 1.000000e+00, %449 %467 = fmul float %457, %449 %468 = fmul float %417, %466 %469 = fadd float %467, %468 %470 = fmul float %400, %39 %471 = fmul float %399, %40 %472 = fadd float %470, %471 %473 = fadd float %472, %41 %474 = fmul float %400, %42 %475 = fmul float %399, %43 %476 = fadd float %474, %475 %477 = fadd float %476, %44 %478 = bitcast float %473 to i32 %479 = bitcast float %477 to i32 %480 = insertelement <2 x i32> undef, i32 %478, i32 0 %481 = insertelement <2 x i32> %480, i32 %479, i32 1 %482 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %481, <8 x i32> %70, <4 x i32> %72, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %483 = extractelement <4 x float> %482, i32 0 %484 = extractelement <4 x float> %482, i32 1 %485 = extractelement <4 x float> %482, i32 2 %486 = call float @llvm.fabs.f32(float %447) %487 = call float @llvm.pow.f32(float %486, float 7.000000e+00) %488 = fsub float 1.000000e+00, %487 %489 = fmul float %483, %487 %490 = fmul float %461, %488 %491 = fadd float %489, %490 %492 = fsub float 1.000000e+00, %487 %493 = fmul float %484, %487 %494 = fmul float %465, %492 %495 = fadd float %493, %494 %496 = fsub float 1.000000e+00, %487 %497 = fmul float %485, %487 %498 = fmul float %469, %496 %499 = fadd float %497, %498 %500 = fmul float %38, 0xBFAEB851E0000000 %501 = fadd float %500, 0x3FE1EB8520000000 %502 = fmul float %38, 0xBFAEB851E0000000 %503 = fadd float %502, 0xBF947AE140000000 %504 = fmul float %38, 0xBFBEB851E0000000 %505 = fadd float %504, 0x3FE147AE20000000 %506 = fmul float %38, 0xBFC70A3D80000000 %507 = fadd float %506, 0x3FE0A3D700000000 %508 = fsub float %505, %501 %509 = fsub float %507, %505 %510 = fdiv float 1.000000e+00, %508 %511 = fdiv float 1.000000e+00, %509 %512 = fmul float %38, 6.000000e+00 %513 = fadd float %512, 1.000000e+00 %514 = bitcast float %75 to i32 %515 = bitcast float %76 to i32 %516 = insertelement <2 x i32> undef, i32 %514, i32 0 %517 = insertelement <2 x i32> %516, i32 %515, i32 1 %518 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %517, <8 x i32> %50, <4 x i32> %52, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %519 = extractelement <4 x float> %518, i32 1 %520 = bitcast float %73 to i32 %521 = bitcast float %74 to i32 %522 = insertelement <2 x i32> undef, i32 %520, i32 0 %523 = insertelement <2 x i32> %522, i32 %521, i32 1 %524 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %523, <8 x i32> %46, <4 x i32> %48, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %525 = extractelement <4 x float> %524, i32 0 %526 = extractelement <4 x float> %524, i32 1 %527 = extractelement <4 x float> %524, i32 2 %528 = extractelement <4 x float> %524, i32 3 %529 = fmul float %519, %525 %530 = fadd float %529, %528 %531 = fmul float %530, %513 %532 = fsub float %531, %501 %533 = fmul float %530, %513 %534 = fsub float %533, %505 %535 = fmul float %530, %513 %536 = fadd float %535, 0xBFE28F5C20000000 %537 = fdiv float 1.000000e+00, %503 %538 = fmul float %536, %537 %539 = call float @llvm.AMDIL.clamp.(float %538, float 0.000000e+00, float 1.000000e+00) %540 = fmul float %536, 1.000000e+01 %541 = call float @llvm.AMDIL.clamp.(float %540, float 0.000000e+00, float 1.000000e+00) %542 = fmul float %510, %532 %543 = fmul float %511, %534 %544 = call float @llvm.AMDIL.clamp.(float %542, float 0.000000e+00, float 1.000000e+00) %545 = call float @llvm.AMDIL.clamp.(float %543, float 0.000000e+00, float 1.000000e+00) %546 = fmul float %544, -2.000000e+00 %547 = fadd float %546, 3.000000e+00 %548 = fmul float %544, %544 %549 = fmul float %548, %547 %550 = fmul float %545, -2.000000e+00 %551 = fadd float %550, 3.000000e+00 %552 = fmul float %545, %545 %553 = fmul float %552, %551 %554 = fmul float %539, -2.000000e+00 %555 = fadd float %554, 3.000000e+00 %556 = fmul float %539, %539 %557 = fmul float %556, %555 %558 = fmul float %491, %557 %559 = fmul float %495, %549 %560 = fmul float %499, %553 %561 = fsub float %29, %25 %562 = fsub float %30, %26 %563 = fsub float %31, %27 %564 = fmul float %558, %561 %565 = fadd float %564, %25 %566 = fmul float %558, %562 %567 = fadd float %566, %26 %568 = fmul float %558, %563 %569 = fadd float %568, %27 %570 = fsub float 1.000000e+00, %559 %571 = fmul float %33, %559 %572 = fmul float %565, %570 %573 = fadd float %571, %572 %574 = fsub float 1.000000e+00, %559 %575 = fmul float %34, %559 %576 = fmul float %567, %574 %577 = fadd float %575, %576 %578 = fsub float 1.000000e+00, %559 %579 = fmul float %35, %559 %580 = fmul float %569, %578 %581 = fadd float %579, %580 %582 = fsub float %28, %573 %583 = fsub float %32, %577 %584 = fsub float %36, %581 %585 = fmul float %560, %582 %586 = fadd float %585, %573 %587 = fmul float %560, %583 %588 = fadd float %587, %577 %589 = fmul float %560, %584 %590 = fadd float %589, %581 %591 = fmul float %38, 7.500000e-01 %592 = fsub float 1.000000e+00, %525 %593 = fmul float %592, %592 %594 = fmul float %593, %593 %595 = fmul float %594, 2.500000e-01 %596 = fadd float %595, %591 %597 = bitcast float %77 to i32 %598 = bitcast float %78 to i32 %599 = insertelement <2 x i32> undef, i32 %597, i32 0 %600 = insertelement <2 x i32> %599, i32 %598, i32 1 %601 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %600, <8 x i32> %58, <4 x i32> %60, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %602 = extractelement <4 x float> %601, i32 0 %603 = extractelement <4 x float> %601, i32 1 %604 = extractelement <4 x float> %601, i32 2 %605 = extractelement <4 x float> %601, i32 3 %606 = fadd float %602, -1.000000e+00 %607 = fadd float %603, -1.000000e+00 %608 = fadd float %604, -1.000000e+00 %609 = fadd float %605, -1.000000e+00 %610 = fmul float %596, %606 %611 = fadd float %610, 1.000000e+00 %612 = fmul float %596, %607 %613 = fadd float %612, 1.000000e+00 %614 = fmul float %596, %608 %615 = fadd float %614, 1.000000e+00 %616 = fmul float %596, %609 %617 = fadd float %616, 1.000000e+00 %618 = fmul float %586, %611 %619 = fmul float %588, %613 %620 = fmul float %590, %615 %621 = fmul float %618, 0x3FD3333340000000 %622 = fmul float %619, 0x3FE2E147A0000000 %623 = fadd float %622, %621 %624 = fmul float %620, 0x3FBC28F5C0000000 %625 = fadd float %623, %624 %626 = fadd float %625, 0xBFB47AE140000000 %627 = fmul float %626, 0x402C924920000000 %628 = call float @llvm.AMDIL.clamp.(float %627, float 0.000000e+00, float 1.000000e+00) %629 = fmul float %628, -2.000000e+00 %630 = fadd float %629, 3.000000e+00 %631 = fmul float %628, %628 %632 = fmul float %631, %630 %633 = fsub float 1.000000e+00, %632 %634 = fmul float %633, 0x3F9EB851E0000000 %635 = fadd float %634, %618 %636 = fmul float %633, 0x3F9EB851E0000000 %637 = fadd float %636, %619 %638 = fmul float %633, 0x3F9EB851E0000000 %639 = fadd float %638, %620 %640 = fmul float %635, %527 %641 = fmul float %637, %527 %642 = fmul float %639, %527 %643 = fmul float %640, 5.000000e-01 %644 = fadd float %643, %618 %645 = fmul float %641, 5.000000e-01 %646 = fadd float %645, %619 %647 = fmul float %642, 5.000000e-01 %648 = fadd float %647, %620 %649 = call float @llvm.AMDIL.clamp.(float %644, float 0.000000e+00, float 1.000000e+00) %650 = call float @llvm.AMDIL.clamp.(float %646, float 0.000000e+00, float 1.000000e+00) %651 = call float @llvm.AMDIL.clamp.(float %648, float 0.000000e+00, float 1.000000e+00) %652 = fmul float %526, %649 %653 = fmul float %526, %650 %654 = fmul float %526, %651 %655 = bitcast float %73 to i32 %656 = bitcast float %74 to i32 %657 = insertelement <2 x i32> undef, i32 %655, i32 0 %658 = insertelement <2 x i32> %657, i32 %656, i32 1 %659 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %658, <8 x i32> %54, <4 x i32> %56, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %660 = extractelement <4 x float> %659, i32 0 %661 = extractelement <4 x float> %659, i32 1 %662 = extractelement <4 x float> %659, i32 2 %663 = extractelement <4 x float> %659, i32 3 %664 = fmul float %526, %649 %665 = fsub float %660, %664 %666 = fmul float %526, %650 %667 = fsub float %661, %666 %668 = fmul float %526, %651 %669 = fsub float %662, %668 %670 = fmul float %526, %37 %671 = fmul float %617, %670 %672 = fmul float %541, -2.000000e+00 %673 = fadd float %672, 3.000000e+00 %674 = fmul float %541, %541 %675 = fmul float %674, %673 %676 = fmul float %673, %674 %677 = fadd float %676, 0xBFECCCCCC0000000 %678 = fmul float %673, %674 %679 = fadd float %678, 0xBF847AE140000000 %680 = fmul float %677, 1.000000e+01 %681 = fmul float %679, -1.000000e+02 %682 = fmul float %675, %665 %683 = fadd float %682, %652 %684 = fmul float %675, %667 %685 = fadd float %684, %653 %686 = fmul float %675, %669 %687 = fadd float %686, %654 %688 = call float @llvm.maxnum.f32(float %681, float 0.000000e+00) %689 = call float @llvm.AMDIL.clamp.(float %680, float 0.000000e+00, float 1.000000e+00) %690 = fmul float %688, -2.000000e+00 %691 = fadd float %690, 3.000000e+00 %692 = fmul float %688, %688 %693 = fmul float %692, %691 %694 = fmul float %693, %671 %695 = fsub float %663, %694 %696 = fmul float %693, %671 %697 = fmul float %689, -2.000000e+00 %698 = fadd float %697, 3.000000e+00 %699 = fmul float %689, %689 %700 = fmul float %699, %698 %701 = fmul float %700, %695 %702 = fadd float %701, %696 %703 = call i32 @llvm.SI.packf16(float %683, float %685) %704 = bitcast i32 %703 to float %705 = call i32 @llvm.SI.packf16(float %687, float %702) %706 = bitcast i32 %705 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %704, float %706, float %704, float %706) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.pow.f32(float, float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 v_interp_p1_f32 v4, v0, 2, 1, [m0] ; D4100600 v_interp_p2_f32 v4, [v4], v1, 2, 1, [m0] ; D4110601 v_interp_p1_f32 v5, v0, 3, 1, [m0] ; D4140700 v_interp_p2_f32 v5, [v5], v1, 3, 1, [m0] ; D4150701 v_mov_b32_e32 v0, 0xba8c8dc2 ; 7E0002FF BA8C8DC2 v_add_f32_e32 v0, v2, v0 ; 02000102 s_load_dwordx8 s[24:31], s[6:7], 0x0 ; C00E0603 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x20 ; C00E0803 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[8:15], s[6:7], 0x40 ; C00E0203 00000040 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x60 ; C00E0403 00000060 v_sub_f32_e32 v1, 0x3f7ef9b9, v3 ; 040206FF 3F7EF9B9 v_add_f32_e32 v8, 0x3affffd5, v2 ; 021004FF 3AFFFFD5 s_load_dwordx8 s[48:55], s[6:7], 0x80 ; C00E0C03 00000080 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s40, s[0:3], 0xa4 ; C0220A00 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[0:3], 0xac ; C0220E00 000000AC v_sub_f32_e32 v9, 0x3f7f224c, v3 ; 041206FF 3F7F224C v_mov_b32_e32 v10, 0x3d70f0f1 ; 7E1402FF 3D70F0F1 v_add_f32_e32 v11, 0x3b832376, v2 ; 021604FF 3B832376 v_sub_f32_e32 v12, 0x3f7fb9b9, v3 ; 041806FF 3F7FB9B9 v_mov_b32_e32 v13, 0xba3b67dc ; 7E1A02FF BA3B67DC v_add_f32_e32 v13, v2, v13 ; 021A1B02 v_sub_f32_e32 v14, 0x3f7f5126, v3 ; 041C06FF 3F7F5126 v_add_f32_e32 v15, 0x3a800015, v2 ; 021E04FF 3A800015 s_buffer_load_dword s41, s[0:3], 0xb0 ; C0220A40 000000B0 v_sub_f32_e32 v16, 0x3f7f9126, v3 ; 042006FF 3F7F9126 v_add_f32_e32 v17, 0x3b2ed9f3, v2 ; 022204FF 3B2ED9F3 s_buffer_load_dword s42, s[0:3], 0xb4 ; C0220A80 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0xbc ; C0220AC0 000000BC v_sub_f32_e32 v18, 0x3f7fd126, v3 ; 042406FF 3F7FD126 v_mov_b32_e32 v19, 0xbb5db3d0 ; 7E2602FF BB5DB3D0 s_load_dwordx4 s[60:63], s[4:5], 0x50 ; C00A0F02 00000050 s_nop 0 ; BF800000 s_load_dwordx4 s[44:47], s[4:5], 0x60 ; C00A0B02 00000060 v_add_f32_e32 v19, v2, v19 ; 02262702 v_sub_f32_e32 v20, 0x3f7f8000, v3 ; 042806FF 3F7F8000 v_mov_b32_e32 v21, 0xbaddb3fb ; 7E2A02FF BADDB3FB v_add_f32_e32 v21, v2, v21 ; 022A2B02 v_sub_f32_e32 v22, 0x3f7fc000, v3 ; 042C06FF 3F7FC000 v_add_f32_e32 v23, 0, v2 ; 022E0480 v_sub_f32_e32 v24, 1.0, v3 ; 043006F2 v_add_f32_e32 v25, 0x3addb3fb, v2 ; 023204FF 3ADDB3FB v_sub_f32_e32 v26, 0x3f802000, v3 ; 043406FF 3F802000 v_add_f32_e32 v27, 0x3b5db3d0, v2 ; 023604FF 3B5DB3D0 v_sub_f32_e32 v28, 0x3f804000, v3 ; 043806FF 3F804000 v_mov_b32_e32 v29, 0xbb2ed9f3 ; 7E3A02FF BB2ED9F3 v_add_f32_e32 v29, v2, v29 ; 023A3B02 v_sub_f32_e32 v30, 0x3f80176d, v3 ; 043C06FF 3F80176D v_mov_b32_e32 v31, 0xba800015 ; 7E3E02FF BA800015 v_add_f32_e32 v31, v2, v31 ; 023E3F02 v_sub_f32_e32 v32, 0x3f80376d, v3 ; 044006FF 3F80376D v_add_f32_e32 v33, 0x3a3b67dc, v2 ; 024204FF 3A3B67DC v_sub_f32_e32 v34, 0x3f80576d, v3 ; 044406FF 3F80576D s_load_dwordx8 s[72:79], s[6:7], 0xa0 ; C00E1203 000000A0 v_mov_b32_e32 v35, 0xbb832376 ; 7E4602FF BB832376 v_add_f32_e32 v35, v2, v35 ; 02464702 v_sub_f32_e32 v36, 0x3f802323, v3 ; 044806FF 3F802323 v_mov_b32_e32 v37, 0xbaffffd5 ; 7E4A02FF BAFFFFD5 v_add_f32_e32 v37, v2, v37 ; 024A4B02 v_sub_f32_e32 v38, 0x3f806eda, v3 ; 044C06FF 3F806EDA v_add_f32_e32 v39, 0x3a8c8dc2, v2 ; 024E04FF 3A8C8DC2 v_sub_f32_e32 v40, 0x3f808323, v3 ; 045006FF 3F808323 s_load_dwordx8 s[64:71], s[6:7], 0xc0 ; C00E1003 000000C0 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[41:44], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[72:79], s[60:63] ; F0800F00 01F22908 s_nop 0 ; BF800000 image_sample v[45:48], 15, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[72:79], s[60:63] ; F0800F00 01F22D00 s_nop 0 ; BF800000 image_sample v[49:52], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[72:79], s[60:63] ; F0800F00 01F2310B s_nop 0 ; BF800000 image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[72:79], s[60:63] ; F0800F00 01F20B0D s_nop 0 ; BF800000 image_sample v[53:56], 15, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[72:79], s[60:63] ; F0800F00 01F2350F s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[17:18], s[72:79], s[60:63] ; F0800F00 01F20F11 s_nop 0 ; BF800000 image_sample v[57:60], 15, 0, 0, 0, 0, 0, 0, 0, v[19:20], s[72:79], s[60:63] ; F0800F00 01F23913 s_nop 0 ; BF800000 image_sample v[19:22], 15, 0, 0, 0, 0, 0, 0, 0, v[21:22], s[72:79], s[60:63] ; F0800F00 01F21315 s_nop 0 ; BF800000 image_sample v[61:64], 15, 0, 0, 0, 0, 0, 0, 0, v[23:24], s[72:79], s[60:63] ; F0800F00 01F23D17 s_nop 0 ; BF800000 image_sample v[23:26], 15, 0, 0, 0, 0, 0, 0, 0, v[25:26], s[72:79], s[60:63] ; F0800F00 01F21719 s_nop 0 ; BF800000 image_sample v[65:68], 15, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[72:79], s[60:63] ; F0800F00 01F2411B s_nop 0 ; BF800000 image_sample v[27:30], 15, 0, 0, 0, 0, 0, 0, 0, v[29:30], s[72:79], s[60:63] ; F0800F00 01F21B1D s_nop 0 ; BF800000 image_sample v[69:72], 15, 0, 0, 0, 0, 0, 0, 0, v[31:32], s[72:79], s[60:63] ; F0800F00 01F2451F s_nop 0 ; BF800000 image_sample v[31:34], 15, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[72:79], s[60:63] ; F0800F00 01F21F21 s_nop 0 ; BF800000 image_sample v[73:76], 15, 0, 0, 0, 0, 0, 0, 0, v[35:36], s[72:79], s[60:63] ; F0800F00 01F24923 s_nop 0 ; BF800000 image_sample v[35:38], 15, 0, 0, 0, 0, 0, 0, 0, v[37:38], s[72:79], s[60:63] ; F0800F00 01F22325 s_nop 0 ; BF800000 image_sample v[77:80], 15, 0, 0, 0, 0, 0, 0, 0, v[39:40], s[72:79], s[60:63] ; F0800F00 01F24D27 s_waitcnt ; BF8C077F v_mul_f32_e32 v0, v10, v41 ; 0A00530A v_mul_f32_e32 v1, v10, v42 ; 0A02550A v_mul_f32_e32 v8, v10, v43 ; 0A10570A v_mul_f32_e32 v9, v10, v44 ; 0A12590A v_mac_f32_e32 v0, v10, v45 ; 2C005B0A v_mac_f32_e32 v1, v10, v46 ; 2C025D0A v_mac_f32_e32 v8, v10, v47 ; 2C105F0A v_mac_f32_e32 v9, v10, v48 ; 2C12610A s_waitcnt vmcnt(14) ; BF8C077E v_mac_f32_e32 v0, v10, v49 ; 2C00630A v_mac_f32_e32 v1, v10, v50 ; 2C02650A v_mac_f32_e32 v8, v10, v51 ; 2C10670A v_mac_f32_e32 v9, v10, v52 ; 2C12690A s_waitcnt vmcnt(13) ; BF8C077D v_mac_f32_e32 v0, v10, v11 ; 2C00170A v_mac_f32_e32 v1, v10, v12 ; 2C02190A v_mac_f32_e32 v8, v10, v13 ; 2C101B0A v_mac_f32_e32 v9, v10, v14 ; 2C121D0A s_waitcnt vmcnt(12) ; BF8C077C v_mac_f32_e32 v0, v10, v53 ; 2C006B0A v_mac_f32_e32 v1, v10, v54 ; 2C026D0A v_mac_f32_e32 v8, v10, v55 ; 2C106F0A v_mac_f32_e32 v9, v10, v56 ; 2C12710A s_waitcnt vmcnt(11) ; BF8C077B v_mac_f32_e32 v0, v10, v15 ; 2C001F0A v_mac_f32_e32 v1, v10, v16 ; 2C02210A v_mac_f32_e32 v8, v10, v17 ; 2C10230A v_mac_f32_e32 v9, v10, v18 ; 2C12250A s_waitcnt vmcnt(10) ; BF8C077A v_mac_f32_e32 v0, v10, v57 ; 2C00730A v_mac_f32_e32 v1, v10, v58 ; 2C02750A v_mac_f32_e32 v8, v10, v59 ; 2C10770A v_mac_f32_e32 v9, v10, v60 ; 2C12790A s_waitcnt vmcnt(9) ; BF8C0779 v_mac_f32_e32 v0, v10, v19 ; 2C00270A v_mac_f32_e32 v1, v10, v20 ; 2C02290A v_mac_f32_e32 v8, v10, v21 ; 2C102B0A v_mac_f32_e32 v9, v10, v22 ; 2C122D0A s_waitcnt vmcnt(8) ; BF8C0778 v_mac_f32_e32 v0, v10, v61 ; 2C007B0A v_mac_f32_e32 v1, v10, v62 ; 2C027D0A v_mac_f32_e32 v8, v10, v63 ; 2C107F0A v_mac_f32_e32 v9, v10, v64 ; 2C12810A s_waitcnt vmcnt(7) ; BF8C0777 v_mac_f32_e32 v0, v10, v23 ; 2C002F0A v_mac_f32_e32 v1, v10, v24 ; 2C02310A v_mac_f32_e32 v8, v10, v25 ; 2C10330A v_mac_f32_e32 v9, v10, v26 ; 2C12350A s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v0, v10, v65 ; 2C00830A v_mac_f32_e32 v1, v10, v66 ; 2C02850A v_mac_f32_e32 v8, v10, v67 ; 2C10870A v_mac_f32_e32 v9, v10, v68 ; 2C12890A s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v0, v10, v27 ; 2C00370A v_mac_f32_e32 v1, v10, v28 ; 2C02390A v_mac_f32_e32 v8, v10, v29 ; 2C103B0A v_mac_f32_e32 v9, v10, v30 ; 2C123D0A s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v0, v10, v69 ; 2C008B0A v_mac_f32_e32 v1, v10, v70 ; 2C028D0A v_mac_f32_e32 v8, v10, v71 ; 2C108F0A v_mac_f32_e32 v9, v10, v72 ; 2C12910A s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v0, v10, v31 ; 2C003F0A v_mac_f32_e32 v1, v10, v32 ; 2C02410A v_mac_f32_e32 v8, v10, v33 ; 2C10430A v_mac_f32_e32 v9, v10, v34 ; 2C12450A s_buffer_load_dword s6, s[0:3], 0xa0 ; C0220180 000000A0 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v0, v10, v73 ; 2C00930A v_mac_f32_e32 v1, v10, v74 ; 2C02950A v_mac_f32_e32 v8, v10, v75 ; 2C10970A v_mac_f32_e32 v9, v10, v76 ; 2C12990A v_mov_b32_e32 v11, s56 ; 7E160238 s_load_dwordx4 s[56:59], s[4:5], 0x40 ; C00A0E02 00000040 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v8, v10, v37 ; 2C104B0A v_mac_f32_e32 v9, v10, v38 ; 2C124D0A s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v8, v10, v79 ; 2C109F0A v_mac_f32_e32 v9, v10, v80 ; 2C12A10A v_mul_f32_e32 v9, 0x41800000, v9 ; 0A1212FF 41800000 v_mul_f32_e32 v8, v8, v9 ; 0A101308 v_mad_f32 v13, s40, v8, v11 ; D1C1000D 042E1028 v_mov_b32_e32 v12, s43 ; 7E18022B v_mac_f32_e32 v0, v10, v35 ; 2C00470A v_mac_f32_e32 v1, v10, v36 ; 2C02490A v_mac_f32_e32 v1, v10, v78 ; 2C029D0A v_mul_f32_e32 v1, v1, v9 ; 0A021301 s_waitcnt lgkmcnt(0) ; BF8C007F v_mad_f32 v15, s6, v1, v13 ; D1C1000F 04360206 v_mad_f32 v14, s42, v8, v12 ; D1C1000E 0432102A v_mad_f32 v16, s41, v1, v14 ; D1C10010 043A0229 image_sample v[15:17], 7, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[64:71], s[44:47] ; F0800700 01700F0F s_nop 0 ; BF800000 image_sample v[18:20], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[48:55], s[56:59] ; F0800700 01CC1202 v_mac_f32_e32 v0, v10, v77 ; 2C009B0A v_mul_f32_e32 v0, v0, v9 ; 0A001300 v_mac_f32_e32 v13, s6, v0 ; 2C1A0006 v_mac_f32_e32 v11, s6, v1 ; 2C160206 v_mac_f32_e32 v11, s40, v0 ; 2C160028 v_mac_f32_e32 v14, s41, v0 ; 2C1C0029 v_mac_f32_e32 v12, s41, v1 ; 2C180229 v_mac_f32_e32 v12, s42, v0 ; 2C18002A s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v0, v18, v18 ; 02002512 v_mad_f32 v1, 2.0, v18, -1.0 ; D1C10001 03CE24F4 v_mad_f32 v8, 2.0, v19, -1.0 ; D1C10008 03CE26F4 v_mad_f32 v9, 2.0, v20, -1.0 ; D1C10009 03CE28F4 v_mad_f32 v0, v0, v1, -v1 ; D1C10000 84060300 v_mac_f32_e32 v0, v8, v8 ; 2C001108 v_mac_f32_e32 v0, v9, v9 ; 2C001309 v_rsq_f32_e32 v0, v0 ; 7E004900 image_sample v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[64:71], s[44:47] ; F0800700 0170080D s_nop 0 ; BF800000 image_sample v[11:13], 7, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[64:71], s[44:47] ; F0800700 01700B0B s_load_dwordx4 s[48:51], s[4:5], 0x10 ; C00A0C02 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x20 ; C00A0A02 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[44:47], s[4:5], 0x30 ; C00A0B02 00000030 v_add_f32_e32 v1, v19, v19 ; 02022713 v_min_f32_e32 v0, 0x7f7fffff, v0 ; 140000FF 7F7FFFFF v_mov_b32_e32 v14, 0xff7fffff ; 7E1C02FF FF7FFFFF v_max_f32_e32 v0, v0, v14 ; 16001D00 v_mad_f32 v1, v1, v0, -v0 ; D1C10001 84020101 v_mov_b32_e32 v14, 0x7fffffff ; 7E1C02FF 7FFFFFFF v_and_b32_e32 v1, v1, v14 ; 26021D01 v_log_f32_e32 v1, v1 ; 7E024301 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v6, 2, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[32:39], s[48:51] ; F0800200 01880606 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 v_mov_b32_e32 v7, 0x40e00000 ; 7E0E02FF 40E00000 v_mul_legacy_f32_e32 v1, v7, v1 ; 08020307 v_exp_f32_e32 v1, v1 ; 7E024101 v_mad_f32 v15, -v1, v15, v15 ; D1C1000F 243E1F01 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v15, v1, v8 ; 2C1E1101 v_mad_f32 v8, -v1, v16, v16 ; D1C10008 24422101 v_mac_f32_e32 v8, v1, v9 ; 2C101301 v_mad_f32 v9, -v1, v17, v17 ; D1C10009 24462301 v_mac_f32_e32 v9, v1, v10 ; 2C121501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[16:19], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[24:31], s[4:7] ; F0800F00 00261002 s_nop 0 ; BF800000 image_sample v[21:24], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[16:23], s[44:47] ; F0800F00 01641504 v_add_f32_e32 v1, v20, v20 ; 02022914 image_sample v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[8:15], s[40:43] ; F0800F00 01420202 s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x28 ; C02202C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x2c ; C0220300 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x38 ; C0220340 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x3c ; C0220380 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x1c ; C02203C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x20 ; C0220400 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x24 ; C0220000 00000024 v_mad_f32 v0, v1, v0, -v0 ; D1C10000 84020101 v_and_b32_e32 v0, v0, v14 ; 26001D00 v_log_f32_e32 v0, v0 ; 7E004300 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v1, s4 ; 7E020204 v_sub_f32_e32 v1, s8, v1 ; 04020208 v_mov_b32_e32 v10, s5 ; 7E140205 v_sub_f32_e32 v10, s9, v10 ; 04141409 v_mov_b32_e32 v14, s6 ; 7E1C0206 v_sub_f32_e32 v14, s10, v14 ; 041C1C0A v_mul_legacy_f32_e32 v0, v7, v0 ; 08000107 v_exp_f32_e32 v0, v0 ; 7E004100 v_mad_f32 v7, -v0, v15, v15 ; D1C10007 243E1F00 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v7, v0, v11 ; 2C0E1700 v_mad_f32 v8, -v0, v8, v8 ; D1C10008 24221100 v_mac_f32_e32 v8, v0, v12 ; 2C101900 v_mad_f32 v9, -v0, v9, v9 ; D1C10009 24261300 v_mac_f32_e32 v9, v0, v13 ; 2C121B00 v_mov_b32_e32 v0, 0xbd75c28f ; 7E0002FF BD75C28F v_mov_b32_e32 v11, 0xbca3d70a ; 7E1602FF BCA3D70A v_mac_f32_e32 v11, s14, v0 ; 2C16000E v_mov_b32_e32 v12, 0x40c00000 ; 7E1802FF 40C00000 v_rcp_f32_e32 v11, v11 ; 7E16450B v_mad_f32 v12, v12, s14, 1.0 ; D1C1000C 03C81D0C s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v19, v16, v6 ; 2C260D10 v_madak_f32_e32 v6, v19, v12, 0xbf147ae1 ; 300C1913 BF147AE1 v_mul_f32_e32 v11, v11, v6 ; 0A160D0B v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mov_b32_e32 v13, 0x40400000 ; 7E1A02FF 40400000 v_mad_f32 v15, -2.0, v11, v13 ; D1C1000F 043616F5 v_mul_f32_e32 v11, v11, v11 ; 0A16170B v_mul_f32_e32 v11, v15, v11 ; 0A16170F v_mul_f32_e32 v7, v11, v7 ; 0A0E0F0B v_mad_f32 v1, v7, v1, s4 ; D1C10001 00120307 v_mad_f32 v10, v7, v10, s5 ; D1C1000A 00161507 v_mad_f32 v7, v7, v14, s6 ; D1C10007 001A1D07 v_mov_b32_e32 v11, 0x3f0f5c29 ; 7E1602FF 3F0F5C29 v_mac_f32_e32 v11, s14, v0 ; 2C16000E v_mov_b32_e32 v0, 0x3f0a3d71 ; 7E0002FF 3F0A3D71 v_mov_b32_e32 v14, 0xbdf5c28f ; 7E1C02FF BDF5C28F v_mac_f32_e32 v0, s14, v14 ; 2C001C0E v_mov_b32_e32 v14, 0x3f051eb8 ; 7E1C02FF 3F051EB8 v_mov_b32_e32 v15, 0xbe3851ec ; 7E1E02FF BE3851EC v_mac_f32_e32 v14, s14, v15 ; 2C1C1E0E v_subrev_f32_e32 v15, v11, v0 ; 061E010B v_subrev_f32_e32 v14, v0, v14 ; 061C1D00 v_rcp_f32_e32 v15, v15 ; 7E1E450F v_rcp_f32_e32 v14, v14 ; 7E1C450E v_mad_f32 v11, v19, v12, -v11 ; D1C1000B 842E1913 v_mad_f32 v0, v19, v12, -v0 ; D1C10000 84021913 v_mul_f32_e32 v11, v11, v15 ; 0A161F0B v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mad_f32 v12, -2.0, v11, v13 ; D1C1000C 043616F5 v_mul_f32_e32 v11, v11, v11 ; 0A16170B v_mul_f32_e32 v11, v12, v11 ; 0A16170C v_mad_f32 v12, -v8, v11, 1.0 ; D1C1000C 23CA1708 v_mad_f32 v15, -v1, v12, s7 ; D1C1000F 201E1901 v_mul_f32_e32 v0, v0, v14 ; 0A001D00 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_mad_f32 v14, -2.0, v0, v13 ; D1C1000E 043600F5 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v14, v0 ; 0A00010E v_mul_f32_e32 v8, v11, v8 ; 0A10110B v_mov_b32_e32 v11, 0x41200000 ; 7E1602FF 41200000 v_mul_f32_e32 v6, v11, v6 ; 0A0C0D0B v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_mul_f32_e32 v0, v0, v9 ; 0A001300 v_mad_f32 v1, -v8, v1, v1 ; D1C10001 24060308 v_mac_f32_e32 v1, s16, v8 ; 2C021010 v_mad_f32 v9, -v8, v10, v10 ; D1C10009 242A1508 v_mac_f32_e32 v9, s0, v8 ; 2C121000 v_mad_f32 v10, -v10, v12, s15 ; D1C1000A 203E190A v_mad_f32 v12, -v7, v12, s12 ; D1C1000C 20321907 v_mad_f32 v7, -v8, v7, v7 ; D1C10007 241E0F08 v_mac_f32_e32 v7, s11, v8 ; 2C0E100B v_mad_f32 v14, -s16, v8, v15 ; D1C1000E 243E1010 v_mad_f32 v10, -s0, v8, v10 ; D1C1000A 242A1000 v_mad_f32 v8, -s11, v8, v12 ; D1C10008 2432100B v_mac_f32_e32 v1, v14, v0 ; 2C02010E v_mac_f32_e32 v9, v10, v0 ; 2C12010A v_mac_f32_e32 v7, v8, v0 ; 2C0E0108 v_mov_b32_e32 v0, 0x3f400000 ; 7E0002FF 3F400000 v_mul_f32_e32 v0, s14, v0 ; 0A00000E v_sub_f32_e32 v8, 1.0, v16 ; 041020F2 v_mad_f32 v8, -v16, v8, v8 ; D1C10008 24221110 v_mul_f32_e32 v8, v8, v8 ; 0A101108 v_madmk_f32_e32 v0, v8, v0, 0x3e800000 ; 2E000108 3E800000 s_waitcnt vmcnt(1) ; BF8C0771 v_mad_f32 v8, v21, v0, -v0 ; D1C10008 84020115 v_mad_f32 v10, v22, v0, -v0 ; D1C1000A 84020116 v_mad_f32 v12, v23, v0, -v0 ; D1C1000C 84020117 v_mad_f32 v0, v24, v0, -v0 ; D1C10000 84020118 v_mac_f32_e32 v1, v1, v8 ; 2C021101 v_mac_f32_e32 v9, v9, v10 ; 2C121509 v_mac_f32_e32 v7, v7, v12 ; 2C0E1907 v_mul_f32_e32 v8, 0x3e99999a, v1 ; 0A1002FF 3E99999A v_madmk_f32_e32 v8, v9, v8, 0x3f170a3d ; 2E101109 3F170A3D v_madmk_f32_e32 v8, v7, v8, 0x3de147ae ; 2E101107 3DE147AE v_mov_b32_e32 v10, 0xbda3d70a ; 7E1402FF BDA3D70A v_add_f32_e32 v8, v8, v10 ; 02101508 v_mul_f32_e32 v8, 0x41649249, v8 ; 0A1010FF 41649249 v_add_f32_e64 v8, 0, v8 clamp ; D1018008 00021080 v_mad_f32 v10, -2.0, v8, v13 ; D1C1000A 043610F5 v_mul_f32_e32 v8, v8, v8 ; 0A101108 v_mad_f32 v8, -v8, v10, 1.0 ; D1C10008 23CA1508 v_mov_b32_e32 v10, 0x3cf5c28f ; 7E1402FF 3CF5C28F v_mad_f32 v12, v10, v8, v1 ; D1C1000C 0406110A v_mad_f32 v14, v10, v8, v9 ; D1C1000E 0426110A v_mad_f32 v8, v10, v8, v7 ; D1C10008 041E110A v_mul_f32_e32 v10, v18, v12 ; 0A141912 v_mul_f32_e32 v12, v18, v14 ; 0A181D12 v_mul_f32_e32 v8, v18, v8 ; 0A101112 v_mac_f32_e32 v1, 0.5, v10 ; 2C0214F0 v_mac_f32_e32 v9, 0.5, v12 ; 2C1218F0 v_mac_f32_e32 v7, 0.5, v8 ; 2C0E10F0 v_add_f32_e64 v1, 0, v1 clamp ; D1018001 00020280 v_add_f32_e64 v8, 0, v9 clamp ; D1018008 00021280 v_add_f32_e64 v7, 0, v7 clamp ; D1018007 00020E80 v_mul_f32_e32 v9, v1, v17 ; 0A122301 v_mul_f32_e32 v10, v8, v17 ; 0A142308 v_mul_f32_e32 v12, v7, v17 ; 0A182307 s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v1, -v17, v1, v2 ; D1C10001 240A0311 v_mad_f32 v2, -v17, v8, v3 ; D1C10002 240E1111 v_mad_f32 v3, -v17, v7, v4 ; D1C10003 24120F11 v_mul_f32_e32 v4, s13, v17 ; 0A08220D v_mac_f32_e32 v4, v4, v0 ; 2C080104 v_mad_f32 v0, -2.0, v6, v13 ; D1C10000 04360CF5 v_mul_f32_e32 v6, v6, v6 ; 0A0C0D06 v_mul_f32_e32 v7, v0, v6 ; 0A0E0D00 v_madak_f32_e32 v8, v6, v0, 0xbf666666 ; 30100106 BF666666 v_madak_f32_e32 v0, v6, v0, 0xbc23d70a ; 30000106 BC23D70A v_mul_f32_e32 v6, v11, v8 ; 0A0C110B v_mov_b32_e32 v8, 0xc2c80000 ; 7E1002FF C2C80000 v_mul_f32_e32 v0, v0, v8 ; 0A001100 v_mac_f32_e32 v9, v1, v7 ; 2C120F01 v_mac_f32_e32 v10, v2, v7 ; 2C140F02 v_mac_f32_e32 v12, v3, v7 ; 2C180F03 v_max_f32_e32 v0, 0, v0 ; 16000080 v_add_f32_e64 v1, 0, v6 clamp ; D1018001 00020C80 v_mad_f32 v2, -2.0, v0, v13 ; D1C10002 043600F5 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v2, v0 ; 0A000102 v_mul_f32_e32 v2, v4, v0 ; 0A040104 v_mad_f32 v0, -v0, v4, v5 ; D1C10000 24160900 v_mac_f32_e32 v13, -2.0, v1 ; 2C1A02F5 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mul_f32_e32 v1, v13, v1 ; 0A02030D v_mac_f32_e32 v2, v0, v1 ; 2C040300 v_cvt_pkrtz_f16_f32_e64 v0, v9, v10 ; D2960000 00021509 v_cvt_pkrtz_f16_f32_e64 v1, v12, v2 ; D2960001 0002050C exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 84 Code Size: 2512 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], 2D, FLOAT DCL CONST[0..3] DCL TEMP[0..4], LOCAL IMM[0] FLT32 { -0.5000, -1.0000, 10.0000, -10.0000} IMM[1] FLT32 { -2.0000, 3.0000, 6.0000, 1.0000} IMM[2] FLT32 { -0.5800, -1.0000, -0.0000, 1.0000} IMM[3] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0].xw, TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[1].xyyy 3: TEX TEMP[1].y, TEMP[1], SAMP[1], 2D 4: MAD TEMP[0].x, TEMP[1].yyyy, TEMP[0].xxxx, TEMP[0].wwww 5: MOV TEMP[1].xy, IN[0].zwww 6: TEX TEMP[1].w, TEMP[1], SAMP[4], 2D 7: ADD TEMP[2].xy, TEMP[1].wwww, IMM[0].xyyy 8: ADD TEMP[3].x, TEMP[1].wwww, TEMP[1].wwww 9: MOV_SAT TEMP[3].x, TEMP[3].xxxx 10: MUL TEMP[2].xy, TEMP[2].xyyy, IMM[0].zwww 11: MOV_SAT TEMP[2].xy, TEMP[2].xyyy 12: MAD TEMP[1].xy, TEMP[2].xyyy, IMM[1].xxxx, IMM[1].yyyy 13: MUL TEMP[2].xy, TEMP[2].xyyy, TEMP[2].xyyy 14: MUL TEMP[2].xy, TEMP[2].xyyy, TEMP[1].xyyy 15: MUL TEMP[2].x, TEMP[2].yyyy, TEMP[2].xxxx 16: MAD TEMP[4].x, CONST[3].wwww, IMM[1].zzzz, IMM[1].wwww 17: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx, TEMP[2].xxxx 18: MAD TEMP[2].x, TEMP[3].xxxx, IMM[1].xxxx, IMM[1].yyyy 19: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx 20: MUL TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx 21: MOV TEMP[3].xy, IN[0].xyyy 22: TEX TEMP[3].yz, TEMP[3], SAMP[3], 2D 23: ADD TEMP[3].x, TEMP[3].zzzz, TEMP[3].yyyy 24: MOV_SAT TEMP[3].x, TEMP[3].xxxx 25: ADD TEMP[3].x, -TEMP[3].xxxx, IMM[1].wwww 26: ADD TEMP[3].x, -TEMP[3].xxxx, IMM[1].wwww 27: MAX TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx 28: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx, IMM[2].xxxx 29: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz 30: MOV_SAT TEMP[2].x, TEMP[0].xxxx 31: MAD TEMP[3].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy 32: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[2].xxxx 33: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx 34: MOV TEMP[2].xy, IN[0].xyyy 35: TEX TEMP[2].xyz, TEMP[2], SAMP[2], 2D 36: MAD TEMP[2].xyz, CONST[3].yyyy, IMM[2].yzzz, TEMP[2].xyzz 37: MUL TEMP[1].xyz, IMM[3].xyyy, CONST[3].yyyy 38: MAD TEMP[0].xyz, TEMP[0].xxxx, TEMP[2].xyzz, TEMP[1].xyzz 39: MOV TEMP[0].w, IMM[1].wwww 40: MOV OUT[0], TEMP[0] 41: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %27 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %28 = load <8 x i32>, <8 x i32> addrspace(2)* %27, align 32, !tbaa !0 %29 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %30 = load <4 x i32>, <4 x i32> addrspace(2)* %29, align 16, !tbaa !0 %31 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %32 = load <8 x i32>, <8 x i32> addrspace(2)* %31, align 32, !tbaa !0 %33 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !tbaa !0 %35 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %36 = load <8 x i32>, <8 x i32> addrspace(2)* %35, align 32, !tbaa !0 %37 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %38 = load <4 x i32>, <4 x i32> addrspace(2)* %37, align 16, !tbaa !0 %39 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %40 = load <8 x i32>, <8 x i32> addrspace(2)* %39, align 32, !tbaa !0 %41 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %42 = load <4 x i32>, <4 x i32> addrspace(2)* %41, align 16, !tbaa !0 %43 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %44 = load <8 x i32>, <8 x i32> addrspace(2)* %43, align 32, !tbaa !0 %45 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %46 = load <4 x i32>, <4 x i32> addrspace(2)* %45, align 16, !tbaa !0 %47 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %48 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %49 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %50 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %51 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %52 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %53 = bitcast float %47 to i32 %54 = bitcast float %48 to i32 %55 = insertelement <2 x i32> undef, i32 %53, i32 0 %56 = insertelement <2 x i32> %55, i32 %54, i32 1 %57 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %56, <8 x i32> %28, <4 x i32> %30, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 3 %60 = bitcast float %51 to i32 %61 = bitcast float %52 to i32 %62 = insertelement <2 x i32> undef, i32 %60, i32 0 %63 = insertelement <2 x i32> %62, i32 %61, i32 1 %64 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %63, <8 x i32> %32, <4 x i32> %34, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %65 = extractelement <4 x float> %64, i32 1 %66 = fmul float %65, %58 %67 = fadd float %66, %59 %68 = bitcast float %49 to i32 %69 = bitcast float %50 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %71, <8 x i32> %44, <4 x i32> %46, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %73 = extractelement <4 x float> %72, i32 3 %74 = fadd float %73, -5.000000e-01 %75 = fadd float %73, -1.000000e+00 %76 = fadd float %73, %73 %77 = call float @llvm.AMDIL.clamp.(float %76, float 0.000000e+00, float 1.000000e+00) %78 = fmul float %74, 1.000000e+01 %79 = fmul float %75, -1.000000e+01 %80 = call float @llvm.AMDIL.clamp.(float %78, float 0.000000e+00, float 1.000000e+00) %81 = call float @llvm.AMDIL.clamp.(float %79, float 0.000000e+00, float 1.000000e+00) %82 = fmul float %80, -2.000000e+00 %83 = fadd float %82, 3.000000e+00 %84 = fmul float %81, -2.000000e+00 %85 = fadd float %84, 3.000000e+00 %86 = fmul float %80, %80 %87 = fmul float %81, %81 %88 = fmul float %86, %83 %89 = fmul float %87, %85 %90 = fmul float %89, %88 %91 = fmul float %26, 6.000000e+00 %92 = fadd float %91, 1.000000e+00 %93 = fmul float %67, %92 %94 = fadd float %93, %90 %95 = fmul float %77, -2.000000e+00 %96 = fadd float %95, 3.000000e+00 %97 = fmul float %77, %77 %98 = fmul float %97, %96 %99 = bitcast float %47 to i32 %100 = bitcast float %48 to i32 %101 = insertelement <2 x i32> undef, i32 %99, i32 0 %102 = insertelement <2 x i32> %101, i32 %100, i32 1 %103 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %102, <8 x i32> %40, <4 x i32> %42, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %104 = extractelement <4 x float> %103, i32 1 %105 = extractelement <4 x float> %103, i32 2 %106 = fadd float %105, %104 %107 = call float @llvm.AMDIL.clamp.(float %106, float 0.000000e+00, float 1.000000e+00) %108 = fsub float 1.000000e+00, %107 %109 = fsub float 1.000000e+00, %108 %110 = call float @llvm.maxnum.f32(float %109, float %98) %111 = fmul float %94, %110 %112 = fadd float %111, 0xBFE28F5C20000000 %113 = fmul float %112, 1.000000e+01 %114 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00) %115 = fmul float %114, -2.000000e+00 %116 = fadd float %115, 3.000000e+00 %117 = fmul float %114, %114 %118 = fmul float %117, %116 %119 = bitcast float %47 to i32 %120 = bitcast float %48 to i32 %121 = insertelement <2 x i32> undef, i32 %119, i32 0 %122 = insertelement <2 x i32> %121, i32 %120, i32 1 %123 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %122, <8 x i32> %36, <4 x i32> %38, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %124 = extractelement <4 x float> %123, i32 0 %125 = extractelement <4 x float> %123, i32 1 %126 = extractelement <4 x float> %123, i32 2 %127 = fsub float %124, %25 %128 = fmul float %25, -0.000000e+00 %129 = fadd float %128, %125 %130 = fmul float %25, -0.000000e+00 %131 = fadd float %130, %126 %132 = fmul float %25, 0.000000e+00 %133 = fmul float %25, 0.000000e+00 %134 = fmul float %118, %127 %135 = fadd float %134, %25 %136 = fmul float %118, %129 %137 = fadd float %136, %132 %138 = fmul float %118, %131 %139 = fadd float %138, %133 %140 = call i32 @llvm.SI.packf16(float %135, float %137) %141 = bitcast i32 %140 to float %142 = call i32 @llvm.SI.packf16(float %139, float 1.000000e+00) %143 = bitcast i32 %142 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %141, float %143, float %141, float %143) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[32:35], s[2:3], 0x0 ; C00A0801 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[36:43], s[6:7], 0x0 ; C00E0903 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x20 ; C00E0B03 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x40 ; C00E0303 00000040 s_nop 0 ; BF800000 s_load_dwordx8 s[20:27], s[6:7], 0x60 ; C00E0503 00000060 s_nop 0 ; BF800000 s_load_dwordx8 s[52:59], s[6:7], 0x80 ; C00E0D03 00000080 s_nop 0 ; BF800000 s_load_dwordx4 s[60:63], s[4:5], 0x0 ; C00A0F02 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[64:67], s[4:5], 0x10 ; C00A1002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x20 ; C00A0002 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[4:5], 0x30 ; C00A0702 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x40 ; C00A0102 00000040 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[32:35], 0x34 ; C0220210 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[32:35], 0x3c ; C0220250 0000003C v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 image_sample v[0:1], 9, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[36:43], s[60:63] ; F0800900 01E90002 s_nop 0 ; BF800000 image_sample v6, 2, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[44:51], s[64:67] ; F0800200 020B0606 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v1, v0, v6 ; 2C020D00 image_sample v0, 8, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[52:59], s[4:7] ; F0800800 002D0004 s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v4, -0.5, v0 ; 020800F1 v_add_f32_e32 v5, v0, v0 ; 020A0100 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_mov_b32_e32 v6, 0x41200000 ; 7E0C02FF 41200000 v_mul_f32_e32 v4, v6, v4 ; 0A080906 v_madmk_f32_e32 v0, v0, v6, 0xc1200000 ; 2E000D00 C1200000 v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_mov_b32_e32 v7, 0x40400000 ; 7E0E02FF 40400000 v_mad_f32 v8, -2.0, v4, v7 ; D1C10008 041E08F5 v_mad_f32 v9, -2.0, v0, v7 ; D1C10009 041E00F5 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v4, v8, v4 ; 0A080908 v_mul_f32_e32 v0, v9, v0 ; 0A000109 v_mul_f32_e32 v0, v4, v0 ; 0A000104 v_mov_b32_e32 v4, 0x40c00000 ; 7E0802FF 40C00000 s_waitcnt lgkmcnt(0) ; BF8C007F v_mad_f32 v4, v4, s9, 1.0 ; D1C10004 03C81304 v_mac_f32_e32 v0, v4, v1 ; 2C000304 v_mad_f32 v1, -2.0, v5, v7 ; D1C10001 041E0AF5 v_mul_f32_e32 v4, v5, v5 ; 0A080B05 v_mul_f32_e32 v1, v1, v4 ; 0A020901 image_sample v[4:5], 6, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[20:27], s[28:31] ; F0800600 00E50402 s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v4, v4, v5 ; 02080B04 v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_sub_f32_e32 v4, 1.0, v4 ; 040808F2 v_sub_f32_e32 v4, 1.0, v4 ; 040808F2 v_max_f32_e32 v1, v1, v4 ; 16020901 v_madak_f32_e32 v0, v0, v1, 0xbf147ae1 ; 30000300 BF147AE1 v_mul_f32_e32 v0, v6, v0 ; 0A000106 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_mac_f32_e32 v7, -2.0, v0 ; 2C0E00F5 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v7, v0 ; 0A000107 image_sample v[1:3], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800700 00030102 s_waitcnt vmcnt(0) ; BF8C0770 v_subrev_f32_e32 v1, s8, v1 ; 06020208 v_mov_b32_e32 v4, 0x80000000 ; 7E0802FF 80000000 v_mad_f32 v2, s8, v4, v2 ; D1C10002 040A0808 v_mac_f32_e32 v3, s8, v4 ; 2C060808 v_mul_f32_e64 v4, 0, s8 ; D1050004 00001080 v_mad_f32 v1, v0, v1, s8 ; D1C10001 00220300 v_mad_f32 v2, v2, v0, v4 ; D1C10002 04120102 v_mac_f32_e32 v4, v3, v0 ; 2C080103 v_cvt_pkrtz_f16_f32_e64 v0, v1, v2 ; D2960000 00020501 v_cvt_pkrtz_f16_f32_e64 v1, v4, 1.0 ; D2960001 0001E504 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 72 VGPRS: 12 Code Size: 544 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], 2D, FLOAT DCL SVIEW[5], 2D, FLOAT DCL CONST[0..3] DCL TEMP[0..10], LOCAL IMM[0] FLT32 { 1.0000, 6.0000, 0.7500, 0.2500} IMM[1] FLT32 { -1.0000, 0.3000, 0.5900, 0.1100} IMM[2] FLT32 { -0.0800, 14.2857, -2.0000, 3.0000} IMM[3] FLT32 { 0.0300, 0.5000, -0.5000, -1.0000} IMM[4] FLT32 { 10.0000, -10.0000, -0.5800, -100.0000} IMM[5] FLT32 { -0.9000, -0.0100, 0.0000, 0.0000} 0: ADD TEMP[0].xyz, -CONST[0].xyzz, CONST[1].xyzz 1: MOV TEMP[1].xy, IN[0].zwww 2: TEX TEMP[1], TEMP[1], SAMP[5], 2D 3: MAD TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz, CONST[0].xyzz 4: LRP TEMP[2].xyz, TEMP[1].yyyy, CONST[2].xyzz, TEMP[0].xyzz 5: MOV TEMP[0].x, CONST[0].wwww 6: MOV TEMP[0].y, CONST[1].wwww 7: MOV TEMP[0].z, CONST[2].wwww 8: LRP TEMP[3].xyz, TEMP[1].zzzz, TEMP[0].xyzz, TEMP[2].xyzz 9: MOV TEMP[4].xy, IN[0].xyyy 10: TEX TEMP[5].yz, TEMP[4], SAMP[3], 2D 11: LRP TEMP[4].xyz, TEMP[5].yyyy, CONST[2].xyzz, TEMP[3].xyzz 12: LRP TEMP[3].xyz, TEMP[5].zzzz, TEMP[0].xyzz, TEMP[4].xyzz 13: ADD TEMP[0].x, TEMP[5].zzzz, TEMP[5].yyyy 14: MOV_SAT TEMP[5].x, TEMP[0].xxxx 15: ADD TEMP[0].x, -TEMP[5].xxxx, IMM[0].xxxx 16: ADD TEMP[0].x, -TEMP[0].xxxx, IMM[0].xxxx 17: MOV TEMP[5].xy, IN[1].zwww 18: TEX TEMP[5], TEMP[5], SAMP[4], 2D 19: MUL TEMP[6].x, IMM[0].zzzz, CONST[3].wwww 20: MOV TEMP[7].xy, IN[0].xyyy 21: TEX TEMP[7], TEMP[7], SAMP[0], 2D 22: ADD TEMP[8].x, -TEMP[7].xxxx, IMM[0].xxxx 23: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[8].xxxx 24: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[8].xxxx 25: MAD TEMP[6].x, TEMP[8].xxxx, IMM[0].wwww, TEMP[6].xxxx 26: ADD TEMP[5], TEMP[5], IMM[1].xxxx 27: MAD TEMP[5], TEMP[6].xxxx, TEMP[5], IMM[0].xxxx 28: MUL TEMP[6].xyz, TEMP[3].xyzz, TEMP[5].xyzz 29: DP3 TEMP[8].x, TEMP[6].xyzz, IMM[1].yzww 30: ADD TEMP[4].x, TEMP[8].xxxx, IMM[2].xxxx 31: MUL TEMP[4].x, TEMP[4].xxxx, IMM[2].yyyy 32: MOV_SAT TEMP[8].x, TEMP[4].xxxx 33: MAD TEMP[2].x, TEMP[8].xxxx, IMM[2].zzzz, IMM[2].wwww 34: MUL TEMP[4].x, TEMP[8].xxxx, TEMP[8].xxxx 35: MAD TEMP[4].x, TEMP[2].xxxx, -TEMP[4].xxxx, IMM[0].xxxx 36: MAD TEMP[2].xyz, TEMP[4].xxxx, IMM[3].xxxx, TEMP[6].xyzz 37: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[7].zzzz 38: MAD TEMP[6].xyz, TEMP[2].xyzz, IMM[3].yyyy, TEMP[6].xyzz 39: MOV_SAT TEMP[6].xyz, TEMP[6].xyzz 40: MUL TEMP[2].xyz, TEMP[7].yyyy, TEMP[6].xyzz 41: MOV TEMP[8].xy, IN[0].xyyy 42: TEX TEMP[8], TEMP[8], SAMP[2], 2D 43: MAD TEMP[6].xyz, TEMP[6].xyzz, -TEMP[7].yyyy, TEMP[8].xyzz 44: ADD TEMP[4].x, TEMP[1].wwww, TEMP[1].wwww 45: MOV_SAT TEMP[9].x, TEMP[4].xxxx 46: ADD TEMP[3].xy, TEMP[1].wwww, IMM[3].zwww 47: MUL TEMP[3].xy, TEMP[3].xyyy, IMM[4].xyyy 48: MOV_SAT TEMP[1].xy, TEMP[3].xyyy 49: MAD TEMP[10].x, TEMP[9].xxxx, IMM[2].zzzz, IMM[2].wwww 50: MUL TEMP[4].x, TEMP[9].xxxx, TEMP[9].xxxx 51: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[10].xxxx 52: MAX TEMP[9].x, TEMP[0].xxxx, TEMP[4].xxxx 53: MAD TEMP[10].xy, TEMP[1].xyyy, IMM[2].zzzz, IMM[2].wwww 54: MUL TEMP[3].xy, TEMP[1].xyyy, TEMP[1].xyyy 55: MUL TEMP[1].xy, TEMP[10].xyyy, TEMP[3].xyyy 56: MUL TEMP[0].x, TEMP[1].yyyy, TEMP[1].xxxx 57: MOV TEMP[1].xy, IN[1].xyyy 58: TEX TEMP[1].y, TEMP[1], SAMP[1], 2D 59: MAD TEMP[4].x, TEMP[1].yyyy, TEMP[7].xxxx, TEMP[7].wwww 60: MUL TEMP[1].x, TEMP[7].yyyy, CONST[3].zzzz 61: MUL TEMP[1].x, TEMP[5].wwww, TEMP[1].xxxx 62: MAD TEMP[3].x, CONST[3].wwww, IMM[0].yyyy, IMM[0].xxxx 63: MAD TEMP[0].x, TEMP[4].xxxx, TEMP[3].xxxx, TEMP[0].xxxx 64: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[9].xxxx, IMM[4].zzzz 65: MUL TEMP[0].x, TEMP[0].xxxx, IMM[4].xxxx 66: MOV_SAT TEMP[3].x, TEMP[0].xxxx 67: MAD TEMP[4].x, TEMP[3].xxxx, IMM[2].zzzz, IMM[2].wwww 68: MUL TEMP[0].x, TEMP[3].xxxx, TEMP[3].xxxx 69: MUL TEMP[3].x, TEMP[0].xxxx, TEMP[4].xxxx 70: MAD TEMP[4].xy, TEMP[4].xxxx, TEMP[0].xxxx, IMM[5].xyyy 71: MUL TEMP[4].xy, TEMP[4].xyyy, IMM[4].xwww 72: MAD TEMP[2].xyz, TEMP[3].xxxx, TEMP[6].xyzz, TEMP[2].xyzz 73: MAX TEMP[3].x, TEMP[4].yyyy, IMM[5].zzzz 74: MOV_SAT TEMP[4].x, TEMP[4].xxxx 75: MAD TEMP[5].x, TEMP[3].xxxx, IMM[2].zzzz, IMM[2].wwww 76: MUL TEMP[0].x, TEMP[3].xxxx, TEMP[3].xxxx 77: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx 78: MAD TEMP[3].x, TEMP[1].xxxx, -TEMP[0].xxxx, TEMP[8].wwww 79: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx 80: MAD TEMP[1].x, TEMP[4].xxxx, IMM[2].zzzz, IMM[2].wwww 81: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx 82: MUL TEMP[1].x, TEMP[4].xxxx, TEMP[1].xxxx 83: MAD TEMP[0].x, TEMP[1].xxxx, TEMP[3].xxxx, TEMP[0].xxxx 84: MOV TEMP[2].w, TEMP[0].xxxx 85: MOV OUT[0], TEMP[2] 86: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 40) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 44) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 56) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %39 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %40 = load <8 x i32>, <8 x i32> addrspace(2)* %39, align 32, !tbaa !0 %41 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %42 = load <4 x i32>, <4 x i32> addrspace(2)* %41, align 16, !tbaa !0 %43 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %44 = load <8 x i32>, <8 x i32> addrspace(2)* %43, align 32, !tbaa !0 %45 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %46 = load <4 x i32>, <4 x i32> addrspace(2)* %45, align 16, !tbaa !0 %47 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %48 = load <8 x i32>, <8 x i32> addrspace(2)* %47, align 32, !tbaa !0 %49 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %50 = load <4 x i32>, <4 x i32> addrspace(2)* %49, align 16, !tbaa !0 %51 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %52 = load <8 x i32>, <8 x i32> addrspace(2)* %51, align 32, !tbaa !0 %53 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %54 = load <4 x i32>, <4 x i32> addrspace(2)* %53, align 16, !tbaa !0 %55 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %56 = load <8 x i32>, <8 x i32> addrspace(2)* %55, align 32, !tbaa !0 %57 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %58 = load <4 x i32>, <4 x i32> addrspace(2)* %57, align 16, !tbaa !0 %59 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 5 %60 = load <8 x i32>, <8 x i32> addrspace(2)* %59, align 32, !tbaa !0 %61 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 5 %62 = load <4 x i32>, <4 x i32> addrspace(2)* %61, align 16, !tbaa !0 %63 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %64 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %65 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %66 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %67 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %68 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %69 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %70 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %71 = fsub float %29, %25 %72 = fsub float %30, %26 %73 = fsub float %31, %27 %74 = bitcast float %65 to i32 %75 = bitcast float %66 to i32 %76 = insertelement <2 x i32> undef, i32 %74, i32 0 %77 = insertelement <2 x i32> %76, i32 %75, i32 1 %78 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %77, <8 x i32> %60, <4 x i32> %62, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %79 = extractelement <4 x float> %78, i32 0 %80 = extractelement <4 x float> %78, i32 1 %81 = extractelement <4 x float> %78, i32 2 %82 = extractelement <4 x float> %78, i32 3 %83 = fmul float %79, %71 %84 = fadd float %83, %25 %85 = fmul float %79, %72 %86 = fadd float %85, %26 %87 = fmul float %79, %73 %88 = fadd float %87, %27 %89 = fsub float 1.000000e+00, %80 %90 = fmul float %33, %80 %91 = fmul float %84, %89 %92 = fadd float %90, %91 %93 = fsub float 1.000000e+00, %80 %94 = fmul float %34, %80 %95 = fmul float %86, %93 %96 = fadd float %94, %95 %97 = fsub float 1.000000e+00, %80 %98 = fmul float %35, %80 %99 = fmul float %88, %97 %100 = fadd float %98, %99 %101 = fsub float 1.000000e+00, %81 %102 = fmul float %28, %81 %103 = fmul float %92, %101 %104 = fadd float %102, %103 %105 = fsub float 1.000000e+00, %81 %106 = fmul float %32, %81 %107 = fmul float %96, %105 %108 = fadd float %106, %107 %109 = fsub float 1.000000e+00, %81 %110 = fmul float %36, %81 %111 = fmul float %100, %109 %112 = fadd float %110, %111 %113 = bitcast float %63 to i32 %114 = bitcast float %64 to i32 %115 = insertelement <2 x i32> undef, i32 %113, i32 0 %116 = insertelement <2 x i32> %115, i32 %114, i32 1 %117 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %116, <8 x i32> %52, <4 x i32> %54, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %118 = extractelement <4 x float> %117, i32 1 %119 = extractelement <4 x float> %117, i32 2 %120 = fsub float 1.000000e+00, %118 %121 = fmul float %33, %118 %122 = fmul float %104, %120 %123 = fadd float %121, %122 %124 = fsub float 1.000000e+00, %118 %125 = fmul float %34, %118 %126 = fmul float %108, %124 %127 = fadd float %125, %126 %128 = fsub float 1.000000e+00, %118 %129 = fmul float %35, %118 %130 = fmul float %112, %128 %131 = fadd float %129, %130 %132 = fsub float 1.000000e+00, %119 %133 = fmul float %28, %119 %134 = fmul float %123, %132 %135 = fadd float %133, %134 %136 = fsub float 1.000000e+00, %119 %137 = fmul float %32, %119 %138 = fmul float %127, %136 %139 = fadd float %137, %138 %140 = fsub float 1.000000e+00, %119 %141 = fmul float %36, %119 %142 = fmul float %131, %140 %143 = fadd float %141, %142 %144 = fadd float %119, %118 %145 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00) %146 = fsub float 1.000000e+00, %145 %147 = fsub float 1.000000e+00, %146 %148 = bitcast float %69 to i32 %149 = bitcast float %70 to i32 %150 = insertelement <2 x i32> undef, i32 %148, i32 0 %151 = insertelement <2 x i32> %150, i32 %149, i32 1 %152 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %151, <8 x i32> %56, <4 x i32> %58, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %153 = extractelement <4 x float> %152, i32 0 %154 = extractelement <4 x float> %152, i32 1 %155 = extractelement <4 x float> %152, i32 2 %156 = extractelement <4 x float> %152, i32 3 %157 = fmul float %38, 7.500000e-01 %158 = bitcast float %63 to i32 %159 = bitcast float %64 to i32 %160 = insertelement <2 x i32> undef, i32 %158, i32 0 %161 = insertelement <2 x i32> %160, i32 %159, i32 1 %162 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %161, <8 x i32> %40, <4 x i32> %42, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %163 = extractelement <4 x float> %162, i32 0 %164 = extractelement <4 x float> %162, i32 1 %165 = extractelement <4 x float> %162, i32 2 %166 = extractelement <4 x float> %162, i32 3 %167 = fsub float 1.000000e+00, %163 %168 = fmul float %167, %167 %169 = fmul float %168, %168 %170 = fmul float %169, 2.500000e-01 %171 = fadd float %170, %157 %172 = fadd float %153, -1.000000e+00 %173 = fadd float %154, -1.000000e+00 %174 = fadd float %155, -1.000000e+00 %175 = fadd float %156, -1.000000e+00 %176 = fmul float %171, %172 %177 = fadd float %176, 1.000000e+00 %178 = fmul float %171, %173 %179 = fadd float %178, 1.000000e+00 %180 = fmul float %171, %174 %181 = fadd float %180, 1.000000e+00 %182 = fmul float %171, %175 %183 = fadd float %182, 1.000000e+00 %184 = fmul float %135, %177 %185 = fmul float %139, %179 %186 = fmul float %143, %181 %187 = fmul float %184, 0x3FD3333340000000 %188 = fmul float %185, 0x3FE2E147A0000000 %189 = fadd float %188, %187 %190 = fmul float %186, 0x3FBC28F5C0000000 %191 = fadd float %189, %190 %192 = fadd float %191, 0xBFB47AE140000000 %193 = fmul float %192, 0x402C924920000000 %194 = call float @llvm.AMDIL.clamp.(float %193, float 0.000000e+00, float 1.000000e+00) %195 = fmul float %194, -2.000000e+00 %196 = fadd float %195, 3.000000e+00 %197 = fmul float %194, %194 %198 = fmul float %197, %196 %199 = fsub float 1.000000e+00, %198 %200 = fmul float %199, 0x3F9EB851E0000000 %201 = fadd float %200, %184 %202 = fmul float %199, 0x3F9EB851E0000000 %203 = fadd float %202, %185 %204 = fmul float %199, 0x3F9EB851E0000000 %205 = fadd float %204, %186 %206 = fmul float %201, %165 %207 = fmul float %203, %165 %208 = fmul float %205, %165 %209 = fmul float %206, 5.000000e-01 %210 = fadd float %209, %184 %211 = fmul float %207, 5.000000e-01 %212 = fadd float %211, %185 %213 = fmul float %208, 5.000000e-01 %214 = fadd float %213, %186 %215 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00) %216 = call float @llvm.AMDIL.clamp.(float %212, float 0.000000e+00, float 1.000000e+00) %217 = call float @llvm.AMDIL.clamp.(float %214, float 0.000000e+00, float 1.000000e+00) %218 = fmul float %164, %215 %219 = fmul float %164, %216 %220 = fmul float %164, %217 %221 = bitcast float %63 to i32 %222 = bitcast float %64 to i32 %223 = insertelement <2 x i32> undef, i32 %221, i32 0 %224 = insertelement <2 x i32> %223, i32 %222, i32 1 %225 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %224, <8 x i32> %48, <4 x i32> %50, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 %228 = extractelement <4 x float> %225, i32 2 %229 = extractelement <4 x float> %225, i32 3 %230 = fmul float %164, %215 %231 = fsub float %226, %230 %232 = fmul float %164, %216 %233 = fsub float %227, %232 %234 = fmul float %164, %217 %235 = fsub float %228, %234 %236 = fadd float %82, %82 %237 = call float @llvm.AMDIL.clamp.(float %236, float 0.000000e+00, float 1.000000e+00) %238 = fadd float %82, -5.000000e-01 %239 = fadd float %82, -1.000000e+00 %240 = fmul float %238, 1.000000e+01 %241 = fmul float %239, -1.000000e+01 %242 = call float @llvm.AMDIL.clamp.(float %240, float 0.000000e+00, float 1.000000e+00) %243 = call float @llvm.AMDIL.clamp.(float %241, float 0.000000e+00, float 1.000000e+00) %244 = fmul float %237, -2.000000e+00 %245 = fadd float %244, 3.000000e+00 %246 = fmul float %237, %237 %247 = fmul float %246, %245 %248 = call float @llvm.maxnum.f32(float %147, float %247) %249 = fmul float %242, -2.000000e+00 %250 = fadd float %249, 3.000000e+00 %251 = fmul float %243, -2.000000e+00 %252 = fadd float %251, 3.000000e+00 %253 = fmul float %242, %242 %254 = fmul float %243, %243 %255 = fmul float %250, %253 %256 = fmul float %252, %254 %257 = fmul float %256, %255 %258 = bitcast float %67 to i32 %259 = bitcast float %68 to i32 %260 = insertelement <2 x i32> undef, i32 %258, i32 0 %261 = insertelement <2 x i32> %260, i32 %259, i32 1 %262 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %261, <8 x i32> %44, <4 x i32> %46, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %263 = extractelement <4 x float> %262, i32 1 %264 = fmul float %263, %163 %265 = fadd float %264, %166 %266 = fmul float %164, %37 %267 = fmul float %183, %266 %268 = fmul float %38, 6.000000e+00 %269 = fadd float %268, 1.000000e+00 %270 = fmul float %265, %269 %271 = fadd float %270, %257 %272 = fmul float %271, %248 %273 = fadd float %272, 0xBFE28F5C20000000 %274 = fmul float %273, 1.000000e+01 %275 = call float @llvm.AMDIL.clamp.(float %274, float 0.000000e+00, float 1.000000e+00) %276 = fmul float %275, -2.000000e+00 %277 = fadd float %276, 3.000000e+00 %278 = fmul float %275, %275 %279 = fmul float %278, %277 %280 = fmul float %277, %278 %281 = fadd float %280, 0xBFECCCCCC0000000 %282 = fmul float %277, %278 %283 = fadd float %282, 0xBF847AE140000000 %284 = fmul float %281, 1.000000e+01 %285 = fmul float %283, -1.000000e+02 %286 = fmul float %279, %231 %287 = fadd float %286, %218 %288 = fmul float %279, %233 %289 = fadd float %288, %219 %290 = fmul float %279, %235 %291 = fadd float %290, %220 %292 = call float @llvm.maxnum.f32(float %285, float 0.000000e+00) %293 = call float @llvm.AMDIL.clamp.(float %284, float 0.000000e+00, float 1.000000e+00) %294 = fmul float %292, -2.000000e+00 %295 = fadd float %294, 3.000000e+00 %296 = fmul float %292, %292 %297 = fmul float %296, %295 %298 = fmul float %297, %267 %299 = fsub float %229, %298 %300 = fmul float %297, %267 %301 = fmul float %293, -2.000000e+00 %302 = fadd float %301, 3.000000e+00 %303 = fmul float %293, %293 %304 = fmul float %303, %302 %305 = fmul float %304, %299 %306 = fadd float %305, %300 %307 = call i32 @llvm.SI.packf16(float %287, float %289) %308 = bitcast i32 %307 to float %309 = call i32 @llvm.SI.packf16(float %291, float %306) %310 = bitcast i32 %309 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %308, float %310, float %308, float %310) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A v_mov_b32_e32 v2, 0x3f400000 ; 7E0402FF 3F400000 v_mov_b32_e32 v3, 0xbda3d70a ; 7E0602FF BDA3D70A v_mov_b32_e32 v4, 0x40400000 ; 7E0802FF 40400000 v_mov_b32_e32 v5, 0x3cf5c28f ; 7E0A02FF 3CF5C28F v_mov_b32_e32 v6, 0x41200000 ; 7E0C02FF 41200000 v_mov_b32_e32 v7, 0x40c00000 ; 7E0E02FF 40C00000 v_mov_b32_e32 v8, 0xc2c80000 ; 7E1002FF C2C80000 v_interp_p1_f32 v9, v0, 0, 0, [m0] ; D4240000 v_interp_p2_f32 v9, [v9], v1, 0, 0, [m0] ; D4250001 v_interp_p1_f32 v10, v0, 1, 0, [m0] ; D4280100 v_interp_p2_f32 v10, [v10], v1, 1, 0, [m0] ; D4290101 v_interp_p1_f32 v11, v0, 2, 0, [m0] ; D42C0200 v_interp_p2_f32 v11, [v11], v1, 2, 0, [m0] ; D42D0201 v_interp_p1_f32 v12, v0, 3, 0, [m0] ; D4300300 v_interp_p2_f32 v12, [v12], v1, 3, 0, [m0] ; D4310301 v_interp_p1_f32 v13, v0, 0, 1, [m0] ; D4340400 v_interp_p2_f32 v13, [v13], v1, 0, 1, [m0] ; D4350401 v_interp_p1_f32 v14, v0, 1, 1, [m0] ; D4380500 v_interp_p2_f32 v14, [v14], v1, 1, 1, [m0] ; D4390501 v_interp_p1_f32 v15, v0, 2, 1, [m0] ; D43C0600 v_interp_p2_f32 v15, [v15], v1, 2, 1, [m0] ; D43D0601 v_interp_p1_f32 v16, v0, 3, 1, [m0] ; D4400700 v_interp_p2_f32 v16, [v16], v1, 3, 1, [m0] ; D4410701 s_load_dwordx4 s[44:47], s[2:3], 0x0 ; C00A0B01 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[4:5], 0x0 ; C00A0702 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[4:5], 0x20 ; C00A0402 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x30 ; C00A0D02 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x40 ; C00A0A02 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[64:67], s[4:5], 0x50 ; C00A1002 00000050 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x0 ; C00E0803 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[8:15], s[6:7], 0x20 ; C00E0203 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[20:27], s[6:7], 0x40 ; C00E0503 00000040 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[44:47], 0x0 ; C0220116 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[44:47], 0x4 ; C0220156 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[44:47], 0x8 ; C0221116 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[44:47], 0xc ; C0221156 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s48, s[44:47], 0x10 ; C0220C16 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[44:47], 0x14 ; C0220C56 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[44:47], 0x18 ; C0220C96 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[44:47], 0x1c ; C0221196 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s71, s[44:47], 0x20 ; C02211D6 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s72, s[44:47], 0x24 ; C0221216 00000024 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s4 ; 7E000204 s_buffer_load_dword s73, s[44:47], 0x28 ; C0221256 00000028 v_mov_b32_e32 v1, s5 ; 7E020205 s_buffer_load_dword s74, s[44:47], 0x2c ; C0221296 0000002C v_mov_b32_e32 v17, s68 ; 7E220244 s_buffer_load_dword s75, s[44:47], 0x38 ; C02212D6 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s76, s[44:47], 0x3c ; C0221316 0000003C v_sub_f32_e32 v0, s48, v0 ; 04000030 v_sub_f32_e32 v1, s49, v1 ; 04020231 v_sub_f32_e32 v17, s50, v17 ; 04222232 s_load_dwordx8 s[56:63], s[6:7], 0x60 ; C00E0E03 00000060 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x80 ; C00E0B03 00000080 s_nop 0 ; BF800000 s_load_dwordx8 s[80:87], s[6:7], 0xa0 ; C00E1403 000000A0 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v2, s76, v2 ; 0A04044C image_sample v[18:21], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[80:87], s[64:67] ; F0800F00 0214120B s_nop 0 ; BF800000 image_sample v[11:12], 6, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[56:63], s[52:55] ; F0800600 01AE0B09 s_nop 0 ; BF800000 image_sample v[22:25], 15, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[44:51], s[40:43] ; F0800F00 014B160F s_nop 0 ; BF800000 image_sample v[26:29], 15, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[32:39], s[28:31] ; F0800F00 00E81A09 s_waitcnt vmcnt(0) ; BF8C0770 v_sub_f32_e32 v15, 1.0, v26 ; 041E34F2 v_mad_f32 v15, -v26, v15, v15 ; D1C1000F 243E1F1A v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_madmk_f32_e32 v2, v15, v2, 0x3e800000 ; 2E04050F 3E800000 v_mad_f32 v15, v22, v2, -v2 ; D1C1000F 840A0516 v_mad_f32 v16, v23, v2, -v2 ; D1C10010 840A0517 v_mad_f32 v22, v24, v2, -v2 ; D1C10016 840A0518 v_mad_f32 v2, v25, v2, -v2 ; D1C10002 840A0519 v_mad_f32 v0, v18, v0, s4 ; D1C10000 00120112 v_mad_f32 v0, -v19, v0, v0 ; D1C10000 24020113 v_mac_f32_e32 v0, s71, v19 ; 2C002647 v_mad_f32 v0, -v20, v0, v0 ; D1C10000 24020114 v_mac_f32_e32 v0, s69, v20 ; 2C002845 v_mad_f32 v0, -v11, v0, v0 ; D1C10000 2402010B v_mac_f32_e32 v0, s71, v11 ; 2C001647 v_mad_f32 v0, -v12, v0, v0 ; D1C10000 2402010C v_mac_f32_e32 v0, s69, v12 ; 2C001845 v_mac_f32_e32 v0, v0, v15 ; 2C001F00 v_mad_f32 v1, v18, v1, s5 ; D1C10001 00160312 v_mad_f32 v1, -v19, v1, v1 ; D1C10001 24060313 v_mac_f32_e32 v1, s72, v19 ; 2C022648 v_mad_f32 v1, -v20, v1, v1 ; D1C10001 24060314 v_mac_f32_e32 v1, s70, v20 ; 2C022846 v_mad_f32 v1, -v11, v1, v1 ; D1C10001 2406030B v_mac_f32_e32 v1, s72, v11 ; 2C021648 v_mad_f32 v1, -v12, v1, v1 ; D1C10001 2406030C v_mac_f32_e32 v1, s70, v12 ; 2C021846 v_mac_f32_e32 v1, v1, v16 ; 2C022101 v_mad_f32 v15, v18, v17, s68 ; D1C1000F 01122312 v_mad_f32 v15, -v19, v15, v15 ; D1C1000F 243E1F13 v_mac_f32_e32 v15, s73, v19 ; 2C1E2649 v_mad_f32 v15, -v20, v15, v15 ; D1C1000F 243E1F14 v_mac_f32_e32 v15, s74, v20 ; 2C1E284A v_mad_f32 v15, -v11, v15, v15 ; D1C1000F 243E1F0B v_mac_f32_e32 v15, s73, v11 ; 2C1E1649 v_mad_f32 v15, -v12, v15, v15 ; D1C1000F 243E1F0C v_mac_f32_e32 v15, s74, v12 ; 2C1E184A v_mac_f32_e32 v15, v15, v22 ; 2C1E2D0F v_mul_f32_e32 v16, 0x3e99999a, v0 ; 0A2000FF 3E99999A v_madmk_f32_e32 v16, v1, v16, 0x3f170a3d ; 2E202101 3F170A3D v_madmk_f32_e32 v16, v15, v16, 0x3de147ae ; 2E20210F 3DE147AE v_add_f32_e32 v3, v16, v3 ; 02060710 v_mul_f32_e32 v3, 0x41649249, v3 ; 0A0606FF 41649249 v_add_f32_e64 v3, 0, v3 clamp ; D1018003 00020680 v_mad_f32 v16, -2.0, v3, v4 ; D1C10010 041206F5 v_mul_f32_e32 v3, v3, v3 ; 0A060703 v_mad_f32 v3, -v3, v16, 1.0 ; D1C10003 23CA2103 v_mad_f32 v16, v5, v3, v0 ; D1C10010 04020705 v_mad_f32 v17, v5, v3, v1 ; D1C10011 04060705 v_mad_f32 v3, v5, v3, v15 ; D1C10003 043E0705 v_mul_f32_e32 v5, v28, v16 ; 0A0A211C v_mac_f32_e32 v0, 0.5, v5 ; 2C000AF0 v_mul_f32_e32 v5, v28, v17 ; 0A0A231C v_mul_f32_e32 v3, v28, v3 ; 0A06071C v_mac_f32_e32 v1, 0.5, v5 ; 2C020AF0 v_mac_f32_e32 v15, 0.5, v3 ; 2C1E06F0 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_add_f32_e64 v1, 0, v1 clamp ; D1018001 00020280 v_add_f32_e64 v3, 0, v15 clamp ; D1018003 00021E80 v_add_f32_e32 v5, v21, v21 ; 020A2B15 v_add_f32_e32 v15, -0.5, v21 ; 021E2AF1 v_madmk_f32_e32 v16, v21, v6, 0xc1200000 ; 2E200D15 C1200000 v_mul_f32_e32 v17, v0, v27 ; 0A223700 v_mul_f32_e32 v18, v1, v27 ; 0A243701 v_mul_f32_e32 v15, v6, v15 ; 0A1E1F06 v_add_f32_e64 v15, 0, v15 clamp ; D101800F 00021E80 v_add_f32_e64 v16, 0, v16 clamp ; D1018010 00022080 v_mad_f32 v19, -2.0, v15, v4 ; D1C10013 04121EF5 v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_mul_f32_e32 v15, v15, v19 ; 0A1E270F v_mad_f32 v19, -2.0, v16, v4 ; D1C10013 041220F5 v_mul_f32_e32 v16, v16, v16 ; 0A202110 v_mul_f32_e32 v16, v16, v19 ; 0A202710 v_mul_f32_e32 v15, v15, v16 ; 0A1E210F image_sample v[19:22], 15, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[20:27], s[16:19] ; F0800F00 00851309 s_nop 0 ; BF800000 image_sample v9, 2, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[8:15], s[0:3] ; F0800200 0002090D v_mul_f32_e32 v10, v3, v27 ; 0A143703 s_waitcnt vmcnt(1) ; BF8C0771 v_mad_f32 v0, -v27, v0, v19 ; D1C10000 244E011B v_mad_f32 v1, -v27, v1, v20 ; D1C10001 2452031B v_mad_f32 v3, -v27, v3, v21 ; D1C10003 2456071B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v29, v26, v9 ; 2C3A131A v_mad_f32 v7, v7, s76, 1.0 ; D1C10007 03C89907 v_mac_f32_e32 v15, v7, v29 ; 2C1E3B07 v_mul_f32_e32 v7, s75, v27 ; 0A0E364B v_add_f32_e32 v9, v11, v12 ; 0212190B v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_mad_f32 v11, -2.0, v5, v4 ; D1C1000B 04120AF5 v_mul_f32_e32 v5, v5, v5 ; 0A0A0B05 v_mul_f32_e32 v5, v11, v5 ; 0A0A0B0B v_add_f32_e64 v9, 0, v9 clamp ; D1018009 00021280 v_sub_f32_e32 v9, 1.0, v9 ; 041212F2 v_sub_f32_e32 v9, 1.0, v9 ; 041212F2 v_max_f32_e32 v5, v5, v9 ; 160A1305 v_mac_f32_e32 v7, v7, v2 ; 2C0E0507 v_madak_f32_e32 v2, v15, v5, 0xbf147ae1 ; 30040B0F BF147AE1 v_mul_f32_e32 v2, v6, v2 ; 0A040506 v_add_f32_e64 v2, 0, v2 clamp ; D1018002 00020480 v_mad_f32 v5, -2.0, v2, v4 ; D1C10005 041204F5 v_mul_f32_e32 v2, v2, v2 ; 0A040502 v_mul_f32_e32 v9, v5, v2 ; 0A120505 v_madak_f32_e32 v11, v2, v5, 0xbf666666 ; 30160B02 BF666666 v_madak_f32_e32 v2, v2, v5, 0xbc23d70a ; 30040B02 BC23D70A v_mul_f32_e32 v5, v6, v11 ; 0A0A1706 v_mul_f32_e32 v2, v2, v8 ; 0A041102 v_mac_f32_e32 v17, v0, v9 ; 2C221300 v_mac_f32_e32 v18, v1, v9 ; 2C241301 v_mac_f32_e32 v10, v3, v9 ; 2C141303 v_max_f32_e32 v0, 0, v2 ; 16000480 v_add_f32_e64 v1, 0, v5 clamp ; D1018001 00020A80 v_mad_f32 v2, -2.0, v0, v4 ; D1C10002 041200F5 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v2, v0 ; 0A000102 v_mul_f32_e32 v2, v7, v0 ; 0A040107 v_mad_f32 v0, -v0, v7, v22 ; D1C10000 245A0F00 v_mac_f32_e32 v4, -2.0, v1 ; 2C0802F5 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mul_f32_e32 v1, v4, v1 ; 0A020304 v_mac_f32_e32 v2, v0, v1 ; 2C040300 v_cvt_pkrtz_f16_f32_e64 v0, v17, v18 ; D2960000 00022511 v_cvt_pkrtz_f16_f32_e64 v1, v10, v2 ; D2960001 0002050A exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 88 VGPRS: 32 Code Size: 1252 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL CONST[0..54] DCL TEMP[0..3], LOCAL 0: MUL TEMP[0].xy, CONST[48].xyyy, IN[1].xyyy 1: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 2: ADD TEMP[1].x, TEMP[0].xxxx, CONST[48].wwww 3: MOV TEMP[1].z, TEMP[1].xxxx 4: MUL TEMP[0].xy, CONST[49].xyyy, IN[1].xyyy 5: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 6: ADD TEMP[2].x, TEMP[0].xxxx, CONST[49].wwww 7: MOV TEMP[1].w, TEMP[2].xxxx 8: MUL TEMP[0].xy, CONST[50].xyyy, IN[1].xyyy 9: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 10: ADD TEMP[2].x, TEMP[0].xxxx, CONST[50].wwww 11: MUL TEMP[0].xy, CONST[51].xyyy, IN[1].xyyy 12: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, TEMP[0].xxxx, CONST[51].wwww 14: MOV TEMP[2].y, TEMP[3].xxxx 15: MUL TEMP[0].xy, CONST[52].xyyy, IN[1].xyyy 16: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 17: ADD TEMP[3].x, TEMP[0].xxxx, CONST[52].wwww 18: MOV TEMP[2].z, TEMP[3].xxxx 19: MUL TEMP[0].xy, CONST[53].xyyy, IN[1].xyyy 20: ADD TEMP[0].x, TEMP[0].yyyy, TEMP[0].xxxx 21: ADD TEMP[0].x, TEMP[0].xxxx, CONST[53].wwww 22: MOV TEMP[2].w, TEMP[0].xxxx 23: MOV TEMP[0].xw, IN[0].xxxw 24: MOV TEMP[1].xy, IN[1].xyxx 25: MAD TEMP[3].x, IN[0].zzzz, CONST[0].zzzz, -IN[0].wwww 26: MOV TEMP[0].z, TEMP[3].xxxx 27: MOV TEMP[0].y, -IN[0].yyyy 28: MAD TEMP[0].xy, CONST[54].xyyy, IN[0].wwww, TEMP[0].xyyy 29: MOV OUT[2], TEMP[1] 30: MOV OUT[3], TEMP[2] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[1], IN[0] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = fmul float %15, %47 %50 = fmul float %16, %48 %51 = fadd float %50, %49 %52 = fadd float %51, %17 %53 = fmul float %18, %47 %54 = fmul float %19, %48 %55 = fadd float %54, %53 %56 = fadd float %55, %20 %57 = fmul float %21, %47 %58 = fmul float %22, %48 %59 = fadd float %58, %57 %60 = fadd float %59, %23 %61 = fmul float %24, %47 %62 = fmul float %25, %48 %63 = fadd float %62, %61 %64 = fadd float %63, %26 %65 = fmul float %27, %47 %66 = fmul float %28, %48 %67 = fadd float %66, %65 %68 = fadd float %67, %29 %69 = fmul float %30, %47 %70 = fmul float %31, %48 %71 = fadd float %70, %69 %72 = fadd float %71, %32 %73 = fmul float %41, %14 %74 = fsub float %73, %42 %75 = fmul float %33, %42 %76 = fadd float %75, %39 %77 = fmul float %34, %42 %78 = fsub float %77, %40 %79 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, align 16, !tbaa !0 %81 = call float @llvm.SI.load.const(<16 x i8> %80, i32 0) %82 = fmul float %81, %39 %83 = call float @llvm.SI.load.const(<16 x i8> %80, i32 4) %84 = fmul float %83, %40 %85 = fadd float %82, %84 %86 = call float @llvm.SI.load.const(<16 x i8> %80, i32 8) %87 = fmul float %86, %41 %88 = fadd float %85, %87 %89 = call float @llvm.SI.load.const(<16 x i8> %80, i32 12) %90 = fmul float %89, %42 %91 = fadd float %88, %90 %92 = call float @llvm.SI.load.const(<16 x i8> %80, i32 16) %93 = fmul float %92, %39 %94 = call float @llvm.SI.load.const(<16 x i8> %80, i32 20) %95 = fmul float %94, %40 %96 = fadd float %93, %95 %97 = call float @llvm.SI.load.const(<16 x i8> %80, i32 24) %98 = fmul float %97, %41 %99 = fadd float %96, %98 %100 = call float @llvm.SI.load.const(<16 x i8> %80, i32 28) %101 = fmul float %100, %42 %102 = fadd float %99, %101 %103 = call float @llvm.SI.load.const(<16 x i8> %80, i32 32) %104 = fmul float %103, %39 %105 = call float @llvm.SI.load.const(<16 x i8> %80, i32 36) %106 = fmul float %105, %40 %107 = fadd float %104, %106 %108 = call float @llvm.SI.load.const(<16 x i8> %80, i32 40) %109 = fmul float %108, %41 %110 = fadd float %107, %109 %111 = call float @llvm.SI.load.const(<16 x i8> %80, i32 44) %112 = fmul float %111, %42 %113 = fadd float %110, %112 %114 = call float @llvm.SI.load.const(<16 x i8> %80, i32 48) %115 = fmul float %114, %39 %116 = call float @llvm.SI.load.const(<16 x i8> %80, i32 52) %117 = fmul float %116, %40 %118 = fadd float %115, %117 %119 = call float @llvm.SI.load.const(<16 x i8> %80, i32 56) %120 = fmul float %119, %41 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %80, i32 60) %123 = fmul float %122, %42 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %80, i32 64) %126 = fmul float %125, %39 %127 = call float @llvm.SI.load.const(<16 x i8> %80, i32 68) %128 = fmul float %127, %40 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %80, i32 72) %131 = fmul float %130, %41 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %80, i32 76) %134 = fmul float %133, %42 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %80, i32 80) %137 = fmul float %136, %39 %138 = call float @llvm.SI.load.const(<16 x i8> %80, i32 84) %139 = fmul float %138, %40 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %80, i32 88) %142 = fmul float %141, %41 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %80, i32 92) %145 = fmul float %144, %42 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %80, i32 96) %148 = fmul float %147, %39 %149 = call float @llvm.SI.load.const(<16 x i8> %80, i32 100) %150 = fmul float %149, %40 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %80, i32 104) %153 = fmul float %152, %41 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %80, i32 108) %156 = fmul float %155, %42 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %80, i32 112) %159 = fmul float %158, %39 %160 = call float @llvm.SI.load.const(<16 x i8> %80, i32 116) %161 = fmul float %160, %40 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %80, i32 120) %164 = fmul float %163, %41 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %80, i32 124) %167 = fmul float %166, %42 %168 = fadd float %165, %167 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %47, float %48, float %52, float %56) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %60, float %64, float %68, float %72) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %76, float %78, float %74, float %42) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %91, float %102, float %113, float %124) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %135, float %146, float %157, float %168) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x300 ; C0220242 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x304 ; C0220282 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30c ; C02202C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x310 ; C0220302 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x314 ; C0220342 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x31c ; C0220382 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x320 ; C02203C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x324 ; C0220402 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x32c ; C0220442 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x330 ; C0220482 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x334 ; C02204C2 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x33c ; C0220502 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x340 ; C0220542 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x344 ; C0220582 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x34c ; C02205C2 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x350 ; C0220602 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x354 ; C0220642 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x35c ; C0220682 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x360 ; C02206C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x364 ; C0220102 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0xc ; C0220700 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x10 ; C0220740 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x14 ; C0220780 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x18 ; C02207C0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x1c ; C0220800 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x20 ; C0220840 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x24 ; C0220880 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x28 ; C02208C0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x2c ; C0220900 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x30 ; C0220940 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x34 ; C0220980 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x38 ; C02209C0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x3c ; C0220A00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x40 ; C0220A40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x44 ; C0220A80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x48 ; C0220AC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x4c ; C0220B00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x50 ; C0220B40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x54 ; C0220B80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x58 ; C0220BC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x5c ; C0220C00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x60 ; C0220C40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x64 ; C0220C80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x68 ; C0220CC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x6c ; C0220D00 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x70 ; C0220D40 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x74 ; C0220D80 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x78 ; C0220DC0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v7, s14 ; 7E0E020E v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s20 ; 7E120214 v_mac_f32_e32 v0, s9, v5 ; 2C000A09 v_mac_f32_e32 v7, s12, v5 ; 2C0E0A0C v_mac_f32_e32 v0, s10, v6 ; 2C000C0A v_mac_f32_e32 v7, s13, v6 ; 2C0E0C0D exp 15, 32, 0, 0, 0, v5, v6, v0, v7 ; C400020F 07000605 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, s23 ; 7E000217 v_mov_b32_e32 v7, s26 ; 7E0E021A v_mac_f32_e32 v8, s15, v5 ; 2C100A0F v_mac_f32_e32 v9, s18, v5 ; 2C120A12 v_mac_f32_e32 v0, s21, v5 ; 2C000A15 v_mac_f32_e32 v7, s24, v5 ; 2C0E0A18 v_mac_f32_e32 v8, s16, v6 ; 2C100C10 v_mac_f32_e32 v9, s19, v6 ; 2C120C13 v_mac_f32_e32 v0, s22, v6 ; 2C000C16 v_mac_f32_e32 v7, s25, v6 ; 2C0E0C19 v_mad_f32 v5, v3, s8, -v4 ; D1C10005 84101103 v_mad_f32 v6, s27, v4, v1 ; D1C10006 0406081B v_mad_f32 v10, s4, v4, -v2 ; D1C1000A 840A0804 v_mul_f32_e32 v11, s6, v2 ; 0A160406 exp 15, 33, 0, 0, 0, v8, v9, v0, v7 ; C400021F 07000908 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s30, v2 ; 0A00041E v_mul_f32_e32 v7, s34, v2 ; 0A0E0422 v_mul_f32_e32 v8, s38, v2 ; 0A100426 v_mul_f32_e32 v9, s42, v2 ; 0A12042A exp 15, 12, 0, 0, 0, v6, v10, v5, v4 ; C40000CF 04050A06 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s46, v2 ; 0A0A042E v_mul_f32_e32 v6, s50, v2 ; 0A0C0432 v_mul_f32_e32 v2, s54, v2 ; 0A040436 v_mac_f32_e32 v11, s5, v1 ; 2C160205 v_mac_f32_e32 v0, s29, v1 ; 2C00021D v_mac_f32_e32 v7, s33, v1 ; 2C0E0221 v_mac_f32_e32 v8, s37, v1 ; 2C100225 v_mac_f32_e32 v9, s41, v1 ; 2C120229 v_mac_f32_e32 v5, s45, v1 ; 2C0A022D v_mac_f32_e32 v6, s49, v1 ; 2C0C0231 v_mac_f32_e32 v2, s53, v1 ; 2C040235 v_mac_f32_e32 v11, s7, v3 ; 2C160607 v_mac_f32_e32 v0, s31, v3 ; 2C00061F v_mac_f32_e32 v7, s35, v3 ; 2C0E0623 v_mac_f32_e32 v8, s39, v3 ; 2C100627 v_mac_f32_e32 v9, s43, v3 ; 2C12062B v_mac_f32_e32 v5, s47, v3 ; 2C0A062F v_mac_f32_e32 v6, s51, v3 ; 2C0C0633 v_mac_f32_e32 v2, s55, v3 ; 2C040637 v_mac_f32_e32 v11, s28, v4 ; 2C16081C v_mac_f32_e32 v0, s32, v4 ; 2C000820 v_mac_f32_e32 v7, s36, v4 ; 2C0E0824 v_mac_f32_e32 v8, s40, v4 ; 2C100828 v_mac_f32_e32 v9, s44, v4 ; 2C12082C v_mac_f32_e32 v5, s48, v4 ; 2C0A0830 v_mac_f32_e32 v6, s52, v4 ; 2C0C0834 v_mac_f32_e32 v2, s0, v4 ; 2C040800 exp 15, 13, 0, 0, 0, v11, v0, v7, v8 ; C40000DF 0807000B exp 15, 14, 0, 1, 0, v9, v5, v6, v2 ; C40008EF 02060509 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 12 Code Size: 992 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], 2D, FLOAT DCL CONST[0..3] DCL TEMP[0..6], LOCAL IMM[0] FLT32 { 6.0000, 1.0000, 0.7500, 0.2500} IMM[1] FLT32 { -1.0000, 0.3000, 0.5900, 0.1100} IMM[2] FLT32 { -0.0800, 14.2857, -2.0000, 3.0000} IMM[3] FLT32 { 0.0300, 0.5000, -0.5800, 10.0000} IMM[4] FLT32 { -0.9000, -0.0100, 10.0000, -100.0000} IMM[5] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: ADD TEMP[0].xyz, -CONST[0].xyzz, CONST[1].xyzz 1: MOV TEMP[1].xy, IN[0].xyyy 2: TEX TEMP[1].xyz, TEMP[1], SAMP[3], 2D 3: MAD TEMP[0].xyz, TEMP[1].xxxx, TEMP[0].xyzz, CONST[0].xyzz 4: LRP TEMP[2].xyz, TEMP[1].yyyy, CONST[2].xyzz, TEMP[0].xyzz 5: ADD TEMP[0].x, -TEMP[2].xxxx, CONST[0].wwww 6: ADD TEMP[3].x, -TEMP[2].yyyy, CONST[1].wwww 7: MOV TEMP[0].y, TEMP[3].xxxx 8: ADD TEMP[3].x, -TEMP[2].zzzz, CONST[2].wwww 9: MOV TEMP[0].z, TEMP[3].xxxx 10: MAD TEMP[0].xyz, TEMP[1].zzzz, TEMP[0].xyzz, TEMP[2].xyzz 11: MOV TEMP[1].xy, IN[1].zwww 12: TEX TEMP[1], TEMP[1], SAMP[4], 2D 13: MUL TEMP[3].x, IMM[0].zzzz, CONST[3].wwww 14: MOV TEMP[4].xy, IN[0].xyyy 15: TEX TEMP[4], TEMP[4], SAMP[0], 2D 16: ADD TEMP[2].x, -TEMP[4].xxxx, IMM[0].yyyy 17: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 18: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 19: MAD TEMP[3].x, TEMP[2].xxxx, IMM[0].wwww, TEMP[3].xxxx 20: ADD TEMP[5], TEMP[1], IMM[1].xxxx 21: MAD TEMP[3], TEMP[3].xxxx, TEMP[5], IMM[0].yyyy 22: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xyzz 23: DP3 TEMP[5].x, TEMP[0].xyzz, IMM[1].yzww 24: ADD TEMP[5].x, TEMP[5].xxxx, IMM[2].xxxx 25: MUL TEMP[5].x, TEMP[5].xxxx, IMM[2].yyyy 26: MOV_SAT TEMP[5].x, TEMP[5].xxxx 27: MAD TEMP[1].x, TEMP[5].xxxx, IMM[2].zzzz, IMM[2].wwww 28: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 29: MAD TEMP[5].x, TEMP[1].xxxx, -TEMP[5].xxxx, IMM[0].yyyy 30: MAD TEMP[1].xyz, TEMP[5].xxxx, IMM[3].xxxx, TEMP[0].xyzz 31: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[4].zzzz 32: MAD TEMP[0].xyz, TEMP[1].xyzz, IMM[3].yyyy, TEMP[0].xyzz 33: MOV_SAT TEMP[5].xyz, TEMP[0].xyzz 34: MUL TEMP[1].xyz, TEMP[4].yyyy, TEMP[5].xyzz 35: MOV TEMP[6].xy, IN[0].xyyy 36: TEX TEMP[6], TEMP[6], SAMP[2], 2D 37: MAD TEMP[0].xyz, TEMP[5].xyzz, -TEMP[4].yyyy, TEMP[6].xyzz 38: MOV TEMP[5].xy, IN[1].xyyy 39: TEX TEMP[5].y, TEMP[5], SAMP[1], 2D 40: MAD TEMP[5].x, TEMP[5].yyyy, TEMP[4].xxxx, TEMP[4].wwww 41: MUL TEMP[4].x, TEMP[4].yyyy, CONST[3].zzzz 42: MUL TEMP[3].x, TEMP[3].wwww, TEMP[4].xxxx 43: MAD TEMP[2].x, CONST[3].wwww, IMM[0].xxxx, IMM[0].yyyy 44: MAD TEMP[4].x, TEMP[5].xxxx, TEMP[2].xxxx, IMM[3].zzzz 45: MUL TEMP[4].x, TEMP[4].xxxx, IMM[3].wwww 46: MOV_SAT TEMP[4].x, TEMP[4].xxxx 47: MAD TEMP[2].x, TEMP[4].xxxx, IMM[2].zzzz, IMM[2].wwww 48: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[4].xxxx 49: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[2].xxxx 50: MAD TEMP[2].xy, TEMP[2].xxxx, TEMP[4].xxxx, IMM[4].xyyy 51: MUL TEMP[2].xy, TEMP[2].xyyy, IMM[4].zwww 52: MAD TEMP[1].xyz, TEMP[5].xxxx, TEMP[0].xyzz, TEMP[1].xyzz 53: MAX TEMP[4].x, TEMP[2].yyyy, IMM[5].xxxx 54: MOV_SAT TEMP[2].x, TEMP[2].xxxx 55: MAD TEMP[5].x, TEMP[4].xxxx, IMM[2].zzzz, IMM[2].wwww 56: MUL TEMP[0].x, TEMP[4].xxxx, TEMP[4].xxxx 57: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx 58: MAD TEMP[4].x, TEMP[3].xxxx, -TEMP[0].xxxx, TEMP[6].wwww 59: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx 60: MAD TEMP[3].x, TEMP[2].xxxx, IMM[2].zzzz, IMM[2].wwww 61: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 62: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 63: MAD TEMP[0].x, TEMP[2].xxxx, TEMP[4].xxxx, TEMP[0].xxxx 64: MOV TEMP[1].w, TEMP[0].xxxx 65: MOV OUT[0], TEMP[1] 66: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 40) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 44) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 56) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 60) %39 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %40 = load <8 x i32>, <8 x i32> addrspace(2)* %39, align 32, !tbaa !0 %41 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %42 = load <4 x i32>, <4 x i32> addrspace(2)* %41, align 16, !tbaa !0 %43 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %44 = load <8 x i32>, <8 x i32> addrspace(2)* %43, align 32, !tbaa !0 %45 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %46 = load <4 x i32>, <4 x i32> addrspace(2)* %45, align 16, !tbaa !0 %47 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %48 = load <8 x i32>, <8 x i32> addrspace(2)* %47, align 32, !tbaa !0 %49 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %50 = load <4 x i32>, <4 x i32> addrspace(2)* %49, align 16, !tbaa !0 %51 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %52 = load <8 x i32>, <8 x i32> addrspace(2)* %51, align 32, !tbaa !0 %53 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %54 = load <4 x i32>, <4 x i32> addrspace(2)* %53, align 16, !tbaa !0 %55 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %56 = load <8 x i32>, <8 x i32> addrspace(2)* %55, align 32, !tbaa !0 %57 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %58 = load <4 x i32>, <4 x i32> addrspace(2)* %57, align 16, !tbaa !0 %59 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %60 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %61 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %62 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %65 = fsub float %29, %25 %66 = fsub float %30, %26 %67 = fsub float %31, %27 %68 = bitcast float %59 to i32 %69 = bitcast float %60 to i32 %70 = insertelement <2 x i32> undef, i32 %68, i32 0 %71 = insertelement <2 x i32> %70, i32 %69, i32 1 %72 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %71, <8 x i32> %52, <4 x i32> %54, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %73 = extractelement <4 x float> %72, i32 0 %74 = extractelement <4 x float> %72, i32 1 %75 = extractelement <4 x float> %72, i32 2 %76 = fmul float %73, %65 %77 = fadd float %76, %25 %78 = fmul float %73, %66 %79 = fadd float %78, %26 %80 = fmul float %73, %67 %81 = fadd float %80, %27 %82 = fsub float 1.000000e+00, %74 %83 = fmul float %33, %74 %84 = fmul float %77, %82 %85 = fadd float %83, %84 %86 = fsub float 1.000000e+00, %74 %87 = fmul float %34, %74 %88 = fmul float %79, %86 %89 = fadd float %87, %88 %90 = fsub float 1.000000e+00, %74 %91 = fmul float %35, %74 %92 = fmul float %81, %90 %93 = fadd float %91, %92 %94 = fsub float %28, %85 %95 = fsub float %32, %89 %96 = fsub float %36, %93 %97 = fmul float %75, %94 %98 = fadd float %97, %85 %99 = fmul float %75, %95 %100 = fadd float %99, %89 %101 = fmul float %75, %96 %102 = fadd float %101, %93 %103 = bitcast float %63 to i32 %104 = bitcast float %64 to i32 %105 = insertelement <2 x i32> undef, i32 %103, i32 0 %106 = insertelement <2 x i32> %105, i32 %104, i32 1 %107 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %106, <8 x i32> %56, <4 x i32> %58, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fmul float %38, 7.500000e-01 %113 = bitcast float %59 to i32 %114 = bitcast float %60 to i32 %115 = insertelement <2 x i32> undef, i32 %113, i32 0 %116 = insertelement <2 x i32> %115, i32 %114, i32 1 %117 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %116, <8 x i32> %40, <4 x i32> %42, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %118 = extractelement <4 x float> %117, i32 0 %119 = extractelement <4 x float> %117, i32 1 %120 = extractelement <4 x float> %117, i32 2 %121 = extractelement <4 x float> %117, i32 3 %122 = fsub float 1.000000e+00, %118 %123 = fmul float %122, %122 %124 = fmul float %123, %123 %125 = fmul float %124, 2.500000e-01 %126 = fadd float %125, %112 %127 = fadd float %108, -1.000000e+00 %128 = fadd float %109, -1.000000e+00 %129 = fadd float %110, -1.000000e+00 %130 = fadd float %111, -1.000000e+00 %131 = fmul float %126, %127 %132 = fadd float %131, 1.000000e+00 %133 = fmul float %126, %128 %134 = fadd float %133, 1.000000e+00 %135 = fmul float %126, %129 %136 = fadd float %135, 1.000000e+00 %137 = fmul float %126, %130 %138 = fadd float %137, 1.000000e+00 %139 = fmul float %98, %132 %140 = fmul float %100, %134 %141 = fmul float %102, %136 %142 = fmul float %139, 0x3FD3333340000000 %143 = fmul float %140, 0x3FE2E147A0000000 %144 = fadd float %143, %142 %145 = fmul float %141, 0x3FBC28F5C0000000 %146 = fadd float %144, %145 %147 = fadd float %146, 0xBFB47AE140000000 %148 = fmul float %147, 0x402C924920000000 %149 = call float @llvm.AMDIL.clamp.(float %148, float 0.000000e+00, float 1.000000e+00) %150 = fmul float %149, -2.000000e+00 %151 = fadd float %150, 3.000000e+00 %152 = fmul float %149, %149 %153 = fmul float %152, %151 %154 = fsub float 1.000000e+00, %153 %155 = fmul float %154, 0x3F9EB851E0000000 %156 = fadd float %155, %139 %157 = fmul float %154, 0x3F9EB851E0000000 %158 = fadd float %157, %140 %159 = fmul float %154, 0x3F9EB851E0000000 %160 = fadd float %159, %141 %161 = fmul float %156, %120 %162 = fmul float %158, %120 %163 = fmul float %160, %120 %164 = fmul float %161, 5.000000e-01 %165 = fadd float %164, %139 %166 = fmul float %162, 5.000000e-01 %167 = fadd float %166, %140 %168 = fmul float %163, 5.000000e-01 %169 = fadd float %168, %141 %170 = call float @llvm.AMDIL.clamp.(float %165, float 0.000000e+00, float 1.000000e+00) %171 = call float @llvm.AMDIL.clamp.(float %167, float 0.000000e+00, float 1.000000e+00) %172 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00) %173 = fmul float %119, %170 %174 = fmul float %119, %171 %175 = fmul float %119, %172 %176 = bitcast float %59 to i32 %177 = bitcast float %60 to i32 %178 = insertelement <2 x i32> undef, i32 %176, i32 0 %179 = insertelement <2 x i32> %178, i32 %177, i32 1 %180 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %179, <8 x i32> %48, <4 x i32> %50, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %181 = extractelement <4 x float> %180, i32 0 %182 = extractelement <4 x float> %180, i32 1 %183 = extractelement <4 x float> %180, i32 2 %184 = extractelement <4 x float> %180, i32 3 %185 = fmul float %119, %170 %186 = fsub float %181, %185 %187 = fmul float %119, %171 %188 = fsub float %182, %187 %189 = fmul float %119, %172 %190 = fsub float %183, %189 %191 = bitcast float %61 to i32 %192 = bitcast float %62 to i32 %193 = insertelement <2 x i32> undef, i32 %191, i32 0 %194 = insertelement <2 x i32> %193, i32 %192, i32 1 %195 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %194, <8 x i32> %44, <4 x i32> %46, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %196 = extractelement <4 x float> %195, i32 1 %197 = fmul float %196, %118 %198 = fadd float %197, %121 %199 = fmul float %119, %37 %200 = fmul float %138, %199 %201 = fmul float %38, 6.000000e+00 %202 = fadd float %201, 1.000000e+00 %203 = fmul float %198, %202 %204 = fadd float %203, 0xBFE28F5C20000000 %205 = fmul float %204, 1.000000e+01 %206 = call float @llvm.AMDIL.clamp.(float %205, float 0.000000e+00, float 1.000000e+00) %207 = fmul float %206, -2.000000e+00 %208 = fadd float %207, 3.000000e+00 %209 = fmul float %206, %206 %210 = fmul float %209, %208 %211 = fmul float %208, %209 %212 = fadd float %211, 0xBFECCCCCC0000000 %213 = fmul float %208, %209 %214 = fadd float %213, 0xBF847AE140000000 %215 = fmul float %212, 1.000000e+01 %216 = fmul float %214, -1.000000e+02 %217 = fmul float %210, %186 %218 = fadd float %217, %173 %219 = fmul float %210, %188 %220 = fadd float %219, %174 %221 = fmul float %210, %190 %222 = fadd float %221, %175 %223 = call float @llvm.maxnum.f32(float %216, float 0.000000e+00) %224 = call float @llvm.AMDIL.clamp.(float %215, float 0.000000e+00, float 1.000000e+00) %225 = fmul float %223, -2.000000e+00 %226 = fadd float %225, 3.000000e+00 %227 = fmul float %223, %223 %228 = fmul float %227, %226 %229 = fmul float %228, %200 %230 = fsub float %184, %229 %231 = fmul float %228, %200 %232 = fmul float %224, -2.000000e+00 %233 = fadd float %232, 3.000000e+00 %234 = fmul float %224, %224 %235 = fmul float %234, %233 %236 = fmul float %235, %230 %237 = fadd float %236, %231 %238 = call i32 @llvm.SI.packf16(float %218, float %220) %239 = bitcast i32 %238 to float %240 = call i32 @llvm.SI.packf16(float %222, float %237) %241 = bitcast i32 %240 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %239, float %241, float %239, float %241) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 0, 1, [m0] ; D4100400 v_interp_p2_f32 v4, [v4], v1, 0, 1, [m0] ; D4110401 v_interp_p1_f32 v5, v0, 1, 1, [m0] ; D4140500 v_interp_p2_f32 v5, [v5], v1, 1, 1, [m0] ; D4150501 v_interp_p1_f32 v6, v0, 2, 1, [m0] ; D4180600 v_interp_p2_f32 v6, [v6], v1, 2, 1, [m0] ; D4190601 v_interp_p1_f32 v7, v0, 3, 1, [m0] ; D41C0700 v_interp_p2_f32 v7, [v7], v1, 3, 1, [m0] ; D41D0701 s_load_dwordx4 s[44:47], s[2:3], 0x0 ; C00A0B01 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[4:5], 0x0 ; C00A0702 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[4:5], 0x20 ; C00A0402 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x30 ; C00A0D02 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x40 ; C00A0A02 00000040 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x0 ; C00E0803 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[8:15], s[6:7], 0x20 ; C00E0203 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[20:27], s[6:7], 0x40 ; C00E0503 00000040 s_nop 0 ; BF800000 s_load_dwordx8 s[56:63], s[6:7], 0x60 ; C00E0E03 00000060 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[44:47], 0x0 ; C0220116 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[44:47], 0x4 ; C0220156 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[44:47], 0x8 ; C0221016 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[44:47], 0xc ; C0221056 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s48, s[44:47], 0x10 ; C0220C16 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[44:47], 0x14 ; C0220C56 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[44:47], 0x18 ; C0220C96 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[44:47], 0x1c ; C0221096 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[44:47], 0x20 ; C02210D6 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[44:47], 0x24 ; C0221116 00000024 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s4 ; 7E000204 s_buffer_load_dword s69, s[44:47], 0x28 ; C0221156 00000028 v_mov_b32_e32 v1, s5 ; 7E020205 s_buffer_load_dword s70, s[44:47], 0x2c ; C0221196 0000002C v_mov_b32_e32 v8, s64 ; 7E100240 s_buffer_load_dword s71, s[44:47], 0x38 ; C02211D6 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s72, s[44:47], 0x3c ; C0221216 0000003C v_sub_f32_e32 v0, s48, v0 ; 04000030 v_sub_f32_e32 v1, s49, v1 ; 04020231 v_sub_f32_e32 v8, s50, v8 ; 04101032 s_load_dwordx8 s[44:51], s[6:7], 0x80 ; C00E0B03 00000080 image_sample v[9:11], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[56:63], s[52:55] ; F0800700 01AE0902 s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v0, v9, v0, s4 ; D1C10000 00120109 v_mad_f32 v1, v9, v1, s5 ; D1C10001 00160309 v_mad_f32 v8, v9, v8, s64 ; D1C10008 01021109 v_sub_f32_e32 v9, 1.0, v10 ; 041214F2 v_mad_f32 v12, -v10, v0, v0 ; D1C1000C 2402010A v_mac_f32_e32 v12, s67, v10 ; 2C181443 v_mad_f32 v13, -v10, v1, v1 ; D1C1000D 2406030A v_mac_f32_e32 v13, s68, v10 ; 2C1A1444 v_mad_f32 v14, -v10, v8, v8 ; D1C1000E 2422110A s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v14, s69, v10 ; 2C1C1445 v_mad_f32 v0, -v0, v9, s65 ; D1C10000 21061300 v_mad_f32 v0, -s67, v10, v0 ; D1C10000 24021443 v_mad_f32 v1, -v1, v9, s66 ; D1C10001 210A1301 v_mad_f32 v1, -s68, v10, v1 ; D1C10001 24061444 v_mad_f32 v8, -v8, v9, s70 ; D1C10008 211A1308 v_mad_f32 v8, -s69, v10, v8 ; D1C10008 24221445 v_mac_f32_e32 v12, v0, v11 ; 2C181700 v_mac_f32_e32 v13, v1, v11 ; 2C1A1701 v_mac_f32_e32 v14, v8, v11 ; 2C1C1708 image_sample v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[44:51], s[40:43] ; F0800F00 014B0606 s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[32:39], s[28:31] ; F0800F00 00E80F02 s_nop 0 ; BF800000 image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[20:27], s[16:19] ; F0800F00 00850002 s_nop 0 ; BF800000 image_sample v4, 2, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[8:15], s[0:3] ; F0800200 00020404 v_mov_b32_e32 v5, 0x3f400000 ; 7E0A02FF 3F400000 v_mul_f32_e32 v5, s72, v5 ; 0A0A0A48 s_waitcnt vmcnt(2) ; BF8C0772 v_sub_f32_e32 v10, 1.0, v15 ; 04141EF2 v_mad_f32 v10, -v15, v10, v10 ; D1C1000A 242A150F v_mul_f32_e32 v10, v10, v10 ; 0A14150A v_madmk_f32_e32 v5, v10, v5, 0x3e800000 ; 2E0A0B0A 3E800000 v_mad_f32 v6, v6, v5, -v5 ; D1C10006 84160B06 v_mad_f32 v7, v7, v5, -v5 ; D1C10007 84160B07 v_mad_f32 v8, v8, v5, -v5 ; D1C10008 84160B08 v_mad_f32 v5, v9, v5, -v5 ; D1C10005 84160B09 v_mac_f32_e32 v12, v12, v6 ; 2C180D0C v_mac_f32_e32 v13, v13, v7 ; 2C1A0F0D v_mac_f32_e32 v14, v14, v8 ; 2C1C110E v_mul_f32_e32 v6, 0x3e99999a, v12 ; 0A0C18FF 3E99999A v_madmk_f32_e32 v6, v13, v6, 0x3f170a3d ; 2E0C0D0D 3F170A3D v_madmk_f32_e32 v6, v14, v6, 0x3de147ae ; 2E0C0D0E 3DE147AE v_mov_b32_e32 v7, 0xbda3d70a ; 7E0E02FF BDA3D70A v_add_f32_e32 v6, v6, v7 ; 020C0F06 v_mul_f32_e32 v6, 0x41649249, v6 ; 0A0C0CFF 41649249 v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_mov_b32_e32 v7, 0x40400000 ; 7E0E02FF 40400000 v_mad_f32 v8, -2.0, v6, v7 ; D1C10008 041E0CF5 v_mul_f32_e32 v6, v6, v6 ; 0A0C0D06 v_mad_f32 v6, -v6, v8, 1.0 ; D1C10006 23CA1106 v_mov_b32_e32 v8, 0x3cf5c28f ; 7E1002FF 3CF5C28F v_mad_f32 v9, v8, v6, v12 ; D1C10009 04320D08 v_mad_f32 v10, v8, v6, v13 ; D1C1000A 04360D08 v_mad_f32 v6, v8, v6, v14 ; D1C10006 043A0D08 v_mul_f32_e32 v8, v17, v9 ; 0A101311 v_mul_f32_e32 v9, v17, v10 ; 0A121511 v_mul_f32_e32 v6, v17, v6 ; 0A0C0D11 v_mac_f32_e32 v12, 0.5, v8 ; 2C1810F0 v_mac_f32_e32 v13, 0.5, v9 ; 2C1A12F0 v_mac_f32_e32 v14, 0.5, v6 ; 2C1C0CF0 v_add_f32_e64 v6, 0, v12 clamp ; D1018006 00021880 v_add_f32_e64 v8, 0, v13 clamp ; D1018008 00021A80 v_add_f32_e64 v9, 0, v14 clamp ; D1018009 00021C80 v_mul_f32_e32 v10, v6, v16 ; 0A142106 v_mul_f32_e32 v11, v8, v16 ; 0A162108 v_mul_f32_e32 v12, v9, v16 ; 0A182109 s_waitcnt vmcnt(1) ; BF8C0771 v_mad_f32 v0, -v16, v6, v0 ; D1C10000 24020D10 v_mad_f32 v1, -v16, v8, v1 ; D1C10001 24061110 v_mad_f32 v2, -v16, v9, v2 ; D1C10002 240A1310 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v18, v15, v4 ; 2C24090F v_mul_f32_e32 v4, s71, v16 ; 0A082047 v_mac_f32_e32 v4, v4, v5 ; 2C080B04 v_mov_b32_e32 v5, 0x40c00000 ; 7E0A02FF 40C00000 v_mad_f32 v5, v5, s72, 1.0 ; D1C10005 03C89105 v_madak_f32_e32 v5, v18, v5, 0xbf147ae1 ; 300A0B12 BF147AE1 v_mov_b32_e32 v6, 0x41200000 ; 7E0C02FF 41200000 v_mul_f32_e32 v5, v6, v5 ; 0A0A0B06 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_mad_f32 v8, -2.0, v5, v7 ; D1C10008 041E0AF5 v_mul_f32_e32 v5, v5, v5 ; 0A0A0B05 v_mul_f32_e32 v9, v8, v5 ; 0A120B08 v_madak_f32_e32 v13, v5, v8, 0xbf666666 ; 301A1105 BF666666 v_madak_f32_e32 v5, v5, v8, 0xbc23d70a ; 300A1105 BC23D70A v_mul_f32_e32 v6, v6, v13 ; 0A0C1B06 v_mov_b32_e32 v8, 0xc2c80000 ; 7E1002FF C2C80000 v_mul_f32_e32 v5, v5, v8 ; 0A0A1105 v_mac_f32_e32 v10, v0, v9 ; 2C141300 v_mac_f32_e32 v11, v1, v9 ; 2C161301 v_mac_f32_e32 v12, v2, v9 ; 2C181302 v_max_f32_e32 v0, 0, v5 ; 16000A80 v_add_f32_e64 v1, 0, v6 clamp ; D1018001 00020C80 v_mad_f32 v2, -2.0, v0, v7 ; D1C10002 041E00F5 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mul_f32_e32 v0, v2, v0 ; 0A000102 v_mul_f32_e32 v2, v4, v0 ; 0A040104 v_mad_f32 v0, -v0, v4, v3 ; D1C10000 240E0900 v_mac_f32_e32 v7, -2.0, v1 ; 2C0E02F5 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mul_f32_e32 v1, v7, v1 ; 0A020307 v_mac_f32_e32 v2, v0, v1 ; 2C040300 v_cvt_pkrtz_f16_f32_e64 v0, v10, v11 ; D2960000 0002170A v_cvt_pkrtz_f16_f32_e64 v1, v12, v2 ; D2960001 0002050C exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 20 Code Size: 1036 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL CONST[0..47] DCL TEMP[0..1], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 510.0200, 0.1000} IMM[1] FLT32 { 1.1000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: MAD TEMP[1].x, IMM[0].zzzz, IN[1].zzzz, IMM[0].wwww 2: F2I TEMP[1].x, TEMP[1].xxxx 3: UARL ADDR[0].x, TEMP[1].xxxx 4: UARL ADDR[0].x, TEMP[1].xxxx 5: DP4 TEMP[0].x, IN[2], CONST[ADDR[0].x] 6: MAD TEMP[1].x, IMM[0].zzzz, IN[1].zzzz, IMM[1].xxxx 7: F2I TEMP[1].x, TEMP[1].xxxx 8: UARL ADDR[0].x, TEMP[1].xxxx 9: DP4 TEMP[1].x, IN[2], CONST[ADDR[0].x] 10: MOV TEMP[0].y, TEMP[1].xxxx 11: MOV OUT[2], IN[1] 12: MOV OUT[1], IN[0] 13: MOV OUT[0], TEMP[0] 14: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %15 = load <16 x i8>, <16 x i8> addrspace(2)* %14, align 16, !tbaa !0 %16 = add i32 %5, %8 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %16) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = extractelement <4 x float> %25, i32 2 %29 = extractelement <4 x float> %25, i32 3 %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %28, 0x407FE051E0000000 %39 = fadd float %38, 0x3FB99999A0000000 %40 = fptosi float %39 to i32 %41 = shl i32 %40, 4 %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %41) %43 = shl i32 %40, 4 %44 = or i32 %43, 4 %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %44) %46 = shl i32 %40, 4 %47 = or i32 %46, 8 %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %47) %49 = shl i32 %40, 4 %50 = or i32 %49, 12 %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %50) %52 = fmul float %34, %42 %53 = fmul float %35, %45 %54 = fadd float %52, %53 %55 = fmul float %36, %48 %56 = fadd float %54, %55 %57 = fmul float %37, %51 %58 = fadd float %56, %57 %59 = fmul float %28, 0x407FE051E0000000 %60 = fadd float %59, 0x3FF19999A0000000 %61 = fptosi float %60 to i32 %62 = shl i32 %61, 4 %63 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %62) %64 = shl i32 %61, 4 %65 = or i32 %64, 4 %66 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %65) %67 = shl i32 %61, 4 %68 = or i32 %67, 8 %69 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %68) %70 = shl i32 %61, 4 %71 = or i32 %70, 12 %72 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %71) %73 = fmul float %34, %63 %74 = fmul float %35, %66 %75 = fadd float %73, %74 %76 = fmul float %36, %69 %77 = fadd float %75, %76 %78 = fmul float %37, %72 %79 = fadd float %77, %78 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %26, float %27, float %28, float %29) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %58, float %79, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 v_mov_b32_e32 v1, 0x43ff028f ; 7E0202FF 43FF028F v_mov_b32_e32 v2, 1.0 ; 7E0402F2 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[3:6], v0, s[4:7], 0 idxen ; E00C2000 80010300 s_nop 0 ; BF800000 buffer_load_format_xyzw v[7:10], v0, s[12:15], 0 idxen ; E00C2000 80030700 s_nop 0 ; BF800000 buffer_load_format_xyzw v[11:14], v0, s[16:19], 0 idxen ; E00C2000 80040B00 s_waitcnt vmcnt(2) ; BF8C0772 exp 15, 32, 0, 0, 0, v3, v4, v5, v6 ; C400020F 06050403 s_waitcnt vmcnt(1) ; BF8C0771 v_madak_f32_e32 v0, v9, v1, 0x3dcccccd ; 30000309 3DCCCCCD v_madak_f32_e32 v1, v9, v1, 0x3f8ccccd ; 30020309 3F8CCCCD v_cvt_i32_f32_e32 v0, v0 ; 7E001100 v_cvt_i32_f32_e32 v1, v1 ; 7E021101 v_lshlrev_b32_e32 v0, 4, v0 ; 24000084 v_lshlrev_b32_e32 v1, 4, v1 ; 24020284 s_waitcnt expcnt(0) ; BF8C070F buffer_load_dword v3, v0, s[0:3], 0 offen ; E0501000 80000300 v_or_b32_e32 v4, 4, v0 ; 28080084 v_or_b32_e32 v5, 8, v0 ; 280A0088 v_or_b32_e32 v0, 12, v0 ; 2800008C buffer_load_dword v6, v1, s[0:3], 0 offen ; E0501000 80000601 v_or_b32_e32 v15, 4, v1 ; 281E0284 buffer_load_dword v4, v4, s[0:3], 0 offen ; E0501000 80000404 s_nop 0 ; BF800000 buffer_load_dword v15, v15, s[0:3], 0 offen ; E0501000 80000F0F v_or_b32_e32 v16, 8, v1 ; 28200288 v_or_b32_e32 v1, 12, v1 ; 2802028C buffer_load_dword v5, v5, s[0:3], 0 offen ; E0501000 80000505 s_nop 0 ; BF800000 buffer_load_dword v16, v16, s[0:3], 0 offen ; E0501000 80001010 s_nop 0 ; BF800000 buffer_load_dword v0, v0, s[0:3], 0 offen ; E0501000 80000000 s_nop 0 ; BF800000 buffer_load_dword v1, v1, s[0:3], 0 offen ; E0501000 80000101 exp 15, 33, 0, 0, 0, v7, v8, v9, v10 ; C400021F 0A090807 s_waitcnt vmcnt(5) ; BF8C0775 v_mul_f32_e32 v4, v4, v12 ; 0A081904 s_waitcnt vmcnt(4) expcnt(0) ; BF8C0704 v_mul_f32_e32 v7, v15, v12 ; 0A0E190F v_mac_f32_e32 v4, v3, v11 ; 2C081703 v_mac_f32_e32 v7, v6, v11 ; 2C0E1706 s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v4, v5, v13 ; 2C081B05 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v7, v16, v13 ; 2C0E1B10 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v4, v0, v14 ; 2C081D00 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v7, v1, v14 ; 2C0E1D01 v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v4, v7, v0, v2 ; C40008CF 02000704 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 20 Code Size: 332 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzx 1: MUL TEMP[1].x, IN[0].wwww, IN[1].wwww 2: MOV TEMP[0].w, TEMP[1].xxxx 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %24 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %27 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %28 = fmul float %26, %27 %29 = call i32 @llvm.SI.packf16(float %23, float %24) %30 = bitcast i32 %29 to float %31 = call i32 @llvm.SI.packf16(float %25, float %28) %32 = bitcast i32 %31 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %30, float %32, float %30, float %32) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v0, v0, 3, 1, [m0] ; D4000700 v_interp_p2_f32 v0, [v0], v1, 3, 1, [m0] ; D4010701 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 v_cvt_pkrtz_f16_f32_e64 v0, v4, v0 ; D2960000 00020104 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 76 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[0], CONST[2] 2: DP4 TEMP[1].x, IN[0], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[0], CONST[4] 5: DP4 TEMP[2].x, IN[0], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], CONST[0] 9: MOV OUT[2], CONST[1] 10: MOV OUT[0], TEMP[0] 11: MOV OUT[3], TEMP[1] 12: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %22 %47 = fmul float %43, %23 %48 = fadd float %46, %47 %49 = fmul float %44, %24 %50 = fadd float %48, %49 %51 = fmul float %45, %25 %52 = fadd float %50, %51 %53 = fmul float %42, %26 %54 = fmul float %43, %27 %55 = fadd float %53, %54 %56 = fmul float %44, %28 %57 = fadd float %55, %56 %58 = fmul float %45, %29 %59 = fadd float %57, %58 %60 = fmul float %42, %30 %61 = fmul float %43, %31 %62 = fadd float %60, %61 %63 = fmul float %44, %32 %64 = fadd float %62, %63 %65 = fmul float %45, %33 %66 = fadd float %64, %65 %67 = fmul float %42, %34 %68 = fmul float %43, %35 %69 = fadd float %67, %68 %70 = fmul float %44, %36 %71 = fadd float %69, %70 %72 = fmul float %45, %37 %73 = fadd float %71, %72 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %66, float %73, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s4 ; 7E080204 v_mov_b32_e32 v5, s5 ; 7E0A0205 v_mov_b32_e32 v6, s6 ; 7E0C0206 v_mov_b32_e32 v7, s7 ; 7E0E0207 exp 15, 32, 0, 0, 0, v4, v5, v6, v7 ; C400020F 07060504 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v4, s8 ; 7E080208 v_mov_b32_e32 v5, s9 ; 7E0A0209 v_mov_b32_e32 v6, s10 ; 7E0C020A v_mov_b32_e32 v7, s11 ; 7E0E020B exp 15, 33, 0, 0, 0, v4, v5, v6, v7 ; C400021F 07060504 s_waitcnt vmcnt(0) expcnt(0) ; BF8C0700 v_mul_f32_e32 v4, s13, v1 ; 0A08020D v_mul_f32_e32 v5, s17, v1 ; 0A0A0211 v_mul_f32_e32 v6, s21, v1 ; 0A0C0215 v_mul_f32_e32 v1, s23, v1 ; 0A020217 v_mac_f32_e32 v4, s12, v0 ; 2C08000C v_mac_f32_e32 v5, s16, v0 ; 2C0A0010 v_mac_f32_e32 v6, s20, v0 ; 2C0C0014 v_mac_f32_e32 v1, s22, v0 ; 2C020016 v_mac_f32_e32 v4, s14, v2 ; 2C08040E v_mac_f32_e32 v5, s18, v2 ; 2C0A0412 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s26, v2 ; 2C02041A v_mac_f32_e32 v4, s15, v3 ; 2C08060F v_mac_f32_e32 v5, s19, v3 ; 2C0A0613 v_mac_f32_e32 v6, s25, v3 ; 2C0C0619 v_mac_f32_e32 v1, s0, v3 ; 2C020600 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 34, 0, 0, 0, v6, v1, v0, v0 ; C400022F 00000106 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v4, v5, v1, v0 ; C40008CF 00010504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 8 Code Size: 476 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0] DCL CONST[2] DCL TEMP[0..7], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3].x, -CONST[0].xxxx 4: BGNLOOP :0 5: FSLT TEMP[4].x, CONST[0].xxxx, TEMP[3].xxxx 6: UIF TEMP[4].xxxx :0 7: BRK 8: ENDIF 9: MAD TEMP[5].xy, TEMP[3].xxxx, CONST[2].xyyy, TEMP[0].xyyy 10: MOV TEMP[6].xy, TEMP[5].xyyy 11: MOV TEMP[6].w, IMM[0].xxxx 12: TXB TEMP[7], TEMP[6], SAMP[0], 2D 13: ADD TEMP[2], TEMP[2], TEMP[7] 14: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy 15: ENDLOOP :0 16: MUL TEMP[1], TEMP[2], CONST[0].wwww 17: MOV TEMP[0].w, IMM[0].yyyy 18: MOV TEMP[0].xyz, IN[1].xyzx 19: MUL TEMP[0], TEMP[1], TEMP[0] 20: MUL TEMP[1], TEMP[0], IN[1].wwww 21: MAD TEMP[1], IN[0], TEMP[1].wwww, TEMP[1] 22: MOV OUT[0], TEMP[1] 23: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %29 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %30 = load <8 x i32>, <8 x i32> addrspace(2)* %29, align 32, !tbaa !0 %31 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !tbaa !0 %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %38 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %39 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %40 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %41 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %42 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %43 = fsub float -0.000000e+00, %25 br label %LOOP LOOP: ; preds = %ENDIF, %main_body %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %81, %ENDIF ] %temp9.0 = phi float [ 0.000000e+00, %main_body ], [ %82, %ENDIF ] %temp10.0 = phi float [ 0.000000e+00, %main_body ], [ %83, %ENDIF ] %temp11.0 = phi float [ 0.000000e+00, %main_body ], [ %84, %ENDIF ] %temp12.0 = phi float [ %43, %main_body ], [ %85, %ENDIF ] %44 = fcmp olt float %25, %temp12.0 br i1 %44, label %IF, label %ENDIF IF: ; preds = %LOOP %45 = fmul float %temp8.0, %26 %46 = fmul float %temp9.0, %26 %47 = fmul float %temp10.0, %26 %48 = fmul float %temp11.0, %26 %49 = fmul float %45, %37 %50 = fmul float %46, %38 %51 = fmul float %47, %39 %52 = fmul float %49, %40 %53 = fmul float %50, %40 %54 = fmul float %51, %40 %55 = fmul float %48, %40 %56 = fmul float %33, %55 %57 = fadd float %56, %52 %58 = fmul float %34, %55 %59 = fadd float %58, %53 %60 = fmul float %35, %55 %61 = fadd float %60, %54 %62 = fmul float %36, %55 %63 = fadd float %62, %55 %64 = call i32 @llvm.SI.packf16(float %57, float %59) %65 = bitcast i32 %64 to float %66 = call i32 @llvm.SI.packf16(float %61, float %63) %67 = bitcast i32 %66 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %65, float %67, float %65, float %67) ret void ENDIF: ; preds = %LOOP %68 = fmul float %temp12.0, %27 %69 = fadd float %68, %41 %70 = fmul float %temp12.0, %28 %71 = fadd float %70, %42 %72 = bitcast float %69 to i32 %73 = bitcast float %71 to i32 %74 = insertelement <4 x i32> , i32 %72, i32 1 %75 = insertelement <4 x i32> %74, i32 %73, i32 2 %76 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %75, <8 x i32> %30, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %77 = extractelement <4 x float> %76, i32 0 %78 = extractelement <4 x float> %76, i32 1 %79 = extractelement <4 x float> %76, i32 2 %80 = extractelement <4 x float> %76, i32 3 %81 = fadd float %temp8.0, %77 %82 = fadd float %temp9.0, %78 %83 = fadd float %temp10.0, %79 %84 = fadd float %temp11.0, %80 %85 = fadd float %temp12.0, 1.000000e+00 br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[16:19], s[2:3], 0x0 ; C00A0401 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[16:19], 0x0 ; C0220048 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[16:19], 0xc ; C0220008 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s2, s[16:19], 0x20 ; C0220088 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[16:19], 0x24 ; C02200C8 00000024 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 v_interp_p1_f32 v8, v0, 2, 1, [m0] ; D4200600 v_interp_p2_f32 v8, [v8], v1, 2, 1, [m0] ; D4210601 v_interp_p1_f32 v9, v0, 3, 1, [m0] ; D4240700 v_interp_p2_f32 v9, [v9], v1, 3, 1, [m0] ; D4250701 v_interp_p1_f32 v10, v0, 0, 2, [m0] ; D4280800 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 v_interp_p2_f32 v10, [v10], v1, 0, 2, [m0] ; D4290801 v_interp_p1_f32 v0, v0, 1, 2, [m0] ; D4000900 v_interp_p2_f32 v0, [v0], v1, 1, 2, [m0] ; D4010901 v_mov_b32_e32 v1, 0x80000000 ; 7E0202FF 80000000 s_waitcnt lgkmcnt(0) ; BF8C007F v_xor_b32_e32 v11, s1, v1 ; 2A160201 v_mov_b32_e32 v15, 0 ; 7E1E0280 s_mov_b64 s[16:17], 0 ; BE900180 v_mov_b32_e32 v16, 0 ; 7E200280 v_mov_b32_e32 v17, 0 ; 7E220280 v_mov_b32_e32 v18, 0 ; 7E240280 v_mov_b32_e32 v1, v18 ; 7E020312 v_mov_b32_e32 v12, v17 ; 7E180311 v_mov_b32_e32 v13, v16 ; 7E1A0310 v_mov_b32_e32 v14, v15 ; 7E1C030F v_cmp_nlt_f32_e32 vcc, s1, v11 ; 7C9C1601 s_and_saveexec_b64 s[18:19], vcc ; BE92206A s_xor_b64 s[18:19], exec, s[18:19] ; 8892127E v_mad_f32 v16, s2, v11, v10 ; D1C10010 042A1602 v_mad_f32 v17, s3, v11, v0 ; D1C10011 04021603 v_mov_b32_e32 v15, 0 ; 7E1E0280 image_sample_b v[18:21], 15, 0, 0, 0, 0, 0, 0, 0, v[15:18], s[8:15], s[4:7] ; F0940F00 0022120F s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v15, v18, v14 ; 021E1D12 v_add_f32_e32 v16, v19, v13 ; 02201B13 v_add_f32_e32 v17, v20, v12 ; 02221914 v_add_f32_e32 v18, v21, v1 ; 02240315 v_add_f32_e32 v11, 1.0, v11 ; 021616F2 s_or_b64 exec, exec, s[18:19] ; 87FE127E s_or_b64 s[16:17], s[18:19], s[16:17] ; 87901012 s_andn2_b64 exec, exec, s[16:17] ; 89FE107E s_cbranch_execnz BB0_1 ; BF890000 s_or_b64 exec, exec, s[16:17] ; 87FE107E v_mul_f32_e32 v0, s0, v14 ; 0A001C00 v_mul_f32_e32 v10, s0, v13 ; 0A141A00 v_mul_f32_e32 v11, s0, v12 ; 0A161800 v_mul_f32_e32 v1, s0, v1 ; 0A020200 v_mul_f32_e32 v0, v6, v0 ; 0A000106 v_mul_f32_e32 v6, v7, v10 ; 0A0C1507 v_mul_f32_e32 v7, v8, v11 ; 0A0E1708 v_mul_f32_e32 v0, v9, v0 ; 0A000109 v_mul_f32_e32 v6, v9, v6 ; 0A0C0D09 v_mul_f32_e32 v7, v9, v7 ; 0A0E0F09 v_mul_f32_e32 v1, v9, v1 ; 0A020309 v_mac_f32_e32 v0, v1, v2 ; 2C000501 v_mac_f32_e32 v6, v1, v3 ; 2C0C0701 v_mac_f32_e32 v7, v1, v4 ; 2C0E0901 v_mac_f32_e32 v1, v1, v5 ; 2C020B01 v_cvt_pkrtz_f16_f32_e64 v0, v0, v6 ; D2960000 00020D00 v_cvt_pkrtz_f16_f32_e64 v1, v7, v1 ; D2960001 00020307 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 24 Code Size: 384 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[0], CONST[2] 2: DP4 TEMP[1].x, IN[0], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[0], CONST[4] 5: DP4 TEMP[2].x, IN[0], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], CONST[0] 9: MOV OUT[2], CONST[1] 10: MOV OUT[0], TEMP[0] 11: MOV OUT[3], TEMP[1] 12: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %22 %47 = fmul float %43, %23 %48 = fadd float %46, %47 %49 = fmul float %44, %24 %50 = fadd float %48, %49 %51 = fmul float %45, %25 %52 = fadd float %50, %51 %53 = fmul float %42, %26 %54 = fmul float %43, %27 %55 = fadd float %53, %54 %56 = fmul float %44, %28 %57 = fadd float %55, %56 %58 = fmul float %45, %29 %59 = fadd float %57, %58 %60 = fmul float %42, %30 %61 = fmul float %43, %31 %62 = fadd float %60, %61 %63 = fmul float %44, %32 %64 = fadd float %62, %63 %65 = fmul float %45, %33 %66 = fadd float %64, %65 %67 = fmul float %42, %34 %68 = fmul float %43, %35 %69 = fadd float %67, %68 %70 = fmul float %44, %36 %71 = fadd float %69, %70 %72 = fmul float %45, %37 %73 = fadd float %71, %72 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %66, float %73, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s4 ; 7E080204 v_mov_b32_e32 v5, s5 ; 7E0A0205 v_mov_b32_e32 v6, s6 ; 7E0C0206 v_mov_b32_e32 v7, s7 ; 7E0E0207 exp 15, 32, 0, 0, 0, v4, v5, v6, v7 ; C400020F 07060504 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v4, s8 ; 7E080208 v_mov_b32_e32 v5, s9 ; 7E0A0209 v_mov_b32_e32 v6, s10 ; 7E0C020A v_mov_b32_e32 v7, s11 ; 7E0E020B exp 15, 33, 0, 0, 0, v4, v5, v6, v7 ; C400021F 07060504 s_waitcnt vmcnt(0) expcnt(0) ; BF8C0700 v_mul_f32_e32 v4, s13, v1 ; 0A08020D v_mul_f32_e32 v5, s17, v1 ; 0A0A0211 v_mul_f32_e32 v6, s21, v1 ; 0A0C0215 v_mul_f32_e32 v1, s23, v1 ; 0A020217 v_mac_f32_e32 v4, s12, v0 ; 2C08000C v_mac_f32_e32 v5, s16, v0 ; 2C0A0010 v_mac_f32_e32 v6, s20, v0 ; 2C0C0014 v_mac_f32_e32 v1, s22, v0 ; 2C020016 v_mac_f32_e32 v4, s14, v2 ; 2C08040E v_mac_f32_e32 v5, s18, v2 ; 2C0A0412 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s26, v2 ; 2C02041A v_mac_f32_e32 v4, s15, v3 ; 2C08060F v_mac_f32_e32 v5, s19, v3 ; 2C0A0613 v_mac_f32_e32 v6, s25, v3 ; 2C0C0619 v_mac_f32_e32 v1, s0, v3 ; 2C020600 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 34, 0, 0, 0, v6, v1, v0, v0 ; C400022F 00000106 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v4, v5, v1, v0 ; C40008CF 00010504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 8 Code Size: 476 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL CONST[0..2] DCL CONST[4] DCL CONST[6] DCL TEMP[0..10], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3].y, IMM[0].xxxx 4: MOV TEMP[3].x, -CONST[0].xxxx 5: BGNLOOP :0 6: FSLT TEMP[4].x, CONST[0].xxxx, TEMP[3].xxxx 7: UIF TEMP[4].xxxx :0 8: BRK 9: ENDIF 10: MOV TEMP[3].y, -CONST[0].yyyy 11: BGNLOOP :0 12: FSLT TEMP[5].x, CONST[0].yyyy, TEMP[3].yyyy 13: UIF TEMP[5].xxxx :0 14: BRK 15: ENDIF 16: ADD TEMP[6].xy, CONST[1].xyyy, TEMP[3].xyyy 17: MAD TEMP[7].xy, TEMP[6].xyyy, CONST[6].xyyy, TEMP[0].xyyy 18: MOV TEMP[8].xy, TEMP[7].xyyy 19: MOV TEMP[8].w, IMM[0].xxxx 20: TXB TEMP[9], TEMP[8], SAMP[1], 2D 21: ADD TEMP[2], TEMP[2], TEMP[9] 22: ADD TEMP[10].x, TEMP[3].yyyy, IMM[0].yyyy 23: MOV TEMP[3].y, TEMP[10].xxxx 24: ENDLOOP :0 25: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy 26: ENDLOOP :0 27: MUL TEMP[1].w, TEMP[2], CONST[0].wwww 28: MUL TEMP[0].xy, IN[2].xyyy, CONST[4].xyyy 29: MOV TEMP[0].xy, TEMP[0].xyyy 30: MOV TEMP[0].w, IMM[0].xxxx 31: TXB TEMP[0], TEMP[0], SAMP[0], 2D 32: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[0].wwww 33: MUL TEMP[2].x, TEMP[1].wwww, TEMP[2].xxxx 34: MUL TEMP[2].x, TEMP[2].xxxx, CONST[0].zzzz 35: MOV_SAT TEMP[2].x, TEMP[2].xxxx 36: MAD TEMP[1], CONST[2], TEMP[2].xxxx, TEMP[0] 37: MOV TEMP[0].w, IMM[0].yyyy 38: MOV TEMP[0].xyz, IN[1].xyzx 39: MUL TEMP[0], TEMP[1], TEMP[0] 40: MUL TEMP[1], TEMP[0], IN[1].wwww 41: MAD TEMP[1], IN[0], TEMP[1].wwww, TEMP[1] 42: MOV OUT[0], TEMP[1] 43: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 40) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 44) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 64) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 68) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 96) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 100) %39 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %40 = load <8 x i32>, <8 x i32> addrspace(2)* %39, align 32, !tbaa !0 %41 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %42 = load <4 x i32>, <4 x i32> addrspace(2)* %41, align 16, !tbaa !0 %43 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %44 = load <8 x i32>, <8 x i32> addrspace(2)* %43, align 32, !tbaa !0 %45 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %46 = load <4 x i32>, <4 x i32> addrspace(2)* %45, align 16, !tbaa !0 %47 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %48 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %49 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %50 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %51 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %52 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %53 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %54 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %55 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %56 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %57 = fsub float -0.000000e+00, %25 %58 = fsub float -0.000000e+00, %26 br label %LOOP LOOP: ; preds = %IF47, %main_body %temp11.0 = phi float [ 0.000000e+00, %main_body ], [ %temp11.1, %IF47 ] %temp12.0 = phi float [ %57, %main_body ], [ %109, %IF47 ] %59 = fcmp olt float %25, %temp12.0 br i1 %59, label %IF, label %ENDIF IF: ; preds = %LOOP %60 = fmul float %temp11.0, %28 %61 = fmul float %55, %35 %62 = fmul float %56, %36 %63 = bitcast float %61 to i32 %64 = bitcast float %62 to i32 %65 = insertelement <4 x i32> , i32 %63, i32 1 %66 = insertelement <4 x i32> %65, i32 %64, i32 2 %67 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %66, <8 x i32> %40, <4 x i32> %42, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %68 = extractelement <4 x float> %67, i32 0 %69 = extractelement <4 x float> %67, i32 1 %70 = extractelement <4 x float> %67, i32 2 %71 = extractelement <4 x float> %67, i32 3 %72 = fsub float 1.000000e+00, %71 %73 = fmul float %60, %72 %74 = fmul float %73, %27 %75 = call float @llvm.AMDIL.clamp.(float %74, float 0.000000e+00, float 1.000000e+00) %76 = fmul float %31, %75 %77 = fadd float %76, %68 %78 = fmul float %32, %75 %79 = fadd float %78, %69 %80 = fmul float %33, %75 %81 = fadd float %80, %70 %82 = fmul float %34, %75 %83 = fadd float %82, %71 %84 = fmul float %77, %51 %85 = fmul float %79, %52 %86 = fmul float %81, %53 %87 = fmul float %84, %54 %88 = fmul float %85, %54 %89 = fmul float %86, %54 %90 = fmul float %83, %54 %91 = fmul float %47, %90 %92 = fadd float %91, %87 %93 = fmul float %48, %90 %94 = fadd float %93, %88 %95 = fmul float %49, %90 %96 = fadd float %95, %89 %97 = fmul float %50, %90 %98 = fadd float %97, %90 %99 = call i32 @llvm.SI.packf16(float %92, float %94) %100 = bitcast i32 %99 to float %101 = call i32 @llvm.SI.packf16(float %96, float %98) %102 = bitcast i32 %101 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %100, float %102, float %100, float %102) ret void ENDIF: ; preds = %LOOP %103 = fadd float %29, %temp12.0 %104 = fmul float %103, %37 %105 = fadd float %104, %55 %106 = bitcast float %105 to i32 %107 = insertelement <4 x i32> , i32 %106, i32 1 br label %LOOP45 LOOP45: ; preds = %ENDIF46, %ENDIF %temp11.1 = phi float [ %temp11.0, %ENDIF ], [ %117, %ENDIF46 ] %temp13.0 = phi float [ %58, %ENDIF ], [ %118, %ENDIF46 ] %108 = fcmp olt float %26, %temp13.0 br i1 %108, label %IF47, label %ENDIF46 IF47: ; preds = %LOOP45 %109 = fadd float %temp12.0, 1.000000e+00 br label %LOOP ENDIF46: ; preds = %LOOP45 %110 = fadd float %30, %temp13.0 %111 = fmul float %110, %38 %112 = fadd float %111, %56 %113 = bitcast float %112 to i32 %114 = insertelement <4 x i32> %107, i32 %113, i32 2 %115 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %114, <8 x i32> %44, <4 x i32> %46, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %116 = extractelement <4 x float> %115, i32 3 %117 = fadd float %temp11.1, %116 %118 = fadd float %temp13.0, 1.000000e+00 br label %LOOP45 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[40:43], s[2:3], 0x0 ; C00A0A01 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x20 ; C00E0603 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[4:5], 0x0 ; C00A0502 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[4:5], 0x10 ; C00A0802 00000010 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v3, v0, 0, 0, [m0] ; D40C0000 v_interp_p2_f32 v3, [v3], v1, 0, 0, [m0] ; D40D0001 v_interp_p1_f32 v2, v0, 1, 0, [m0] ; D4080100 v_interp_p2_f32 v2, [v2], v1, 1, 0, [m0] ; D4090101 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s6, s[40:43], 0x0 ; C0220194 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[40:43], 0x4 ; C02201D4 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[40:43], 0x8 ; C02200D4 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[40:43], 0xc ; C0220154 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[40:43], 0x10 ; C0220294 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[40:43], 0x14 ; C02202D4 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[40:43], 0x20 ; C0220114 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[40:43], 0x24 ; C0220054 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[40:43], 0x28 ; C0220094 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[40:43], 0x2c ; C0220014 0000002C v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 s_buffer_load_dword s8, s[40:43], 0x40 ; C0220214 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[40:43], 0x44 ; C0220254 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[40:43], 0x60 ; C0220914 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[40:43], 0x64 ; C0220954 00000064 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 v_interp_p1_f32 v8, v0, 2, 1, [m0] ; D4200600 v_interp_p2_f32 v8, [v8], v1, 2, 1, [m0] ; D4210601 v_interp_p1_f32 v9, v0, 3, 1, [m0] ; D4240700 v_interp_p2_f32 v9, [v9], v1, 3, 1, [m0] ; D4250701 v_interp_p1_f32 v10, v0, 0, 2, [m0] ; D4280800 v_interp_p2_f32 v10, [v10], v1, 0, 2, [m0] ; D4290801 v_interp_p1_f32 v0, v0, 1, 2, [m0] ; D4000900 v_interp_p2_f32 v0, [v0], v1, 1, 2, [m0] ; D4010901 v_mov_b32_e32 v1, 0x80000000 ; 7E0202FF 80000000 s_waitcnt lgkmcnt(0) ; BF8C007F v_xor_b32_e32 v11, s6, v1 ; 2A160206 v_xor_b32_e32 v12, s7, v1 ; 2A180207 v_mov_b32_e32 v13, 0 ; 7E1A0280 s_mov_b64 s[38:39], 0 ; BEA60180 v_mov_b32_e32 v1, v13 ; 7E02030D v_cmp_nlt_f32_e32 vcc, s6, v11 ; 7C9C1606 s_and_saveexec_b64 s[40:41], vcc ; BEA8206A s_xor_b64 s[40:41], exec, s[40:41] ; 88A8287E s_cbranch_execz BB0_4 ; BF880000 v_add_f32_e32 v13, s10, v11 ; 021A160A v_mad_f32 v15, s36, v13, v10 ; D1C1000F 042A1A24 v_mov_b32_e32 v14, 0 ; 7E1C0280 s_mov_b64 s[42:43], 0 ; BEAA0180 v_mov_b32_e32 v16, v1 ; 7E200301 v_mov_b32_e32 v17, v12 ; 7E22030C v_mov_b32_e32 v13, v16 ; 7E1A0310 v_cmp_nlt_f32_e32 vcc, s7, v17 ; 7C9C2207 s_and_saveexec_b64 s[44:45], vcc ; BEAC206A s_xor_b64 s[44:45], exec, s[44:45] ; 88AC2C7E v_add_f32_e32 v16, s11, v17 ; 0220220B v_mad_f32 v16, s37, v16, v0 ; D1C10010 04022025 image_sample_b v16, 8, 0, 0, 0, 0, 0, 0, 0, v[14:17], s[24:31], s[32:35] ; F0940800 0106100E s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v16, v16, v13 ; 02201B10 v_add_f32_e32 v17, 1.0, v17 ; 022222F2 s_or_b64 exec, exec, s[44:45] ; 87FE2C7E s_or_b64 s[42:43], s[44:45], s[42:43] ; 87AA2A2C s_andn2_b64 exec, exec, s[42:43] ; 89FE2A7E s_cbranch_execnz BB0_5 ; BF890000 s_or_b64 exec, exec, s[42:43] ; 87FE2A7E v_add_f32_e32 v11, 1.0, v11 ; 021616F2 s_or_b64 exec, exec, s[40:41] ; 87FE287E s_or_b64 s[38:39], s[40:41], s[38:39] ; 87A62628 s_andn2_b64 exec, exec, s[38:39] ; 89FE267E s_cbranch_execnz BB0_1 ; BF890000 s_or_b64 exec, exec, s[38:39] ; 87FE267E v_mul_f32_e32 v1, s5, v1 ; 0A020205 v_mul_f32_e32 v11, s8, v10 ; 0A161408 v_mul_f32_e32 v12, s9, v0 ; 0A180009 v_mov_b32_e32 v10, 0 ; 7E140280 image_sample_b v[10:13], 15, 0, 0, 0, 0, 0, 0, 0, v[10:13], s[12:19], s[20:23] ; F0940F00 00A30A0A s_waitcnt vmcnt(0) ; BF8C0770 v_mad_f32 v0, -v13, v1, v1 ; D1C10000 2406030D v_mul_f32_e32 v0, s3, v0 ; 0A000003 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_mad_f32 v1, s4, v0, v10 ; D1C10001 042A0004 v_mad_f32 v10, s1, v0, v11 ; D1C1000A 042E0001 v_mad_f32 v11, s2, v0, v12 ; D1C1000B 04320002 v_mac_f32_e32 v13, s0, v0 ; 2C1A0000 v_mul_f32_e32 v0, v6, v1 ; 0A000306 v_mul_f32_e32 v1, v7, v10 ; 0A021507 v_mul_f32_e32 v6, v8, v11 ; 0A0C1708 v_mul_f32_e32 v0, v9, v0 ; 0A000109 v_mul_f32_e32 v1, v9, v1 ; 0A020309 v_mul_f32_e32 v6, v9, v6 ; 0A0C0D09 v_mul_f32_e32 v7, v9, v13 ; 0A0E1B09 v_mac_f32_e32 v0, v7, v3 ; 2C000707 v_mac_f32_e32 v1, v7, v2 ; 2C020507 v_mac_f32_e32 v6, v7, v4 ; 2C0C0907 v_mac_f32_e32 v7, v7, v5 ; 2C0E0B07 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v6, v7 ; D2960001 00020F06 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 20 Code Size: 624 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL CONST[0..47] DCL TEMP[0..1], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 2.0000, 0.1000} IMM[1] FLT32 { 1.1000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: MAD TEMP[1].x, IN[1].xxxx, IMM[0].zzzz, IMM[0].wwww 2: F2I TEMP[1].x, TEMP[1].xxxx 3: UARL ADDR[0].x, TEMP[1].xxxx 4: UARL ADDR[0].x, TEMP[1].xxxx 5: DP4 TEMP[0].x, IN[0], CONST[ADDR[0].x] 6: MAD TEMP[1].x, IN[1].xxxx, IMM[0].zzzz, IMM[1].xxxx 7: F2I TEMP[1].x, TEMP[1].xxxx 8: UARL ADDR[0].x, TEMP[1].xxxx 9: DP4 TEMP[1].x, IN[0], CONST[ADDR[0].x] 10: MOV TEMP[0].y, TEMP[1].xxxx 11: MOV OUT[0], TEMP[0] 12: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %15 = load <16 x i8>, <16 x i8> addrspace(2)* %14, align 16, !tbaa !0 %16 = add i32 %5, %8 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %16) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = fmul float %26, 2.000000e+00 %28 = fadd float %27, 0x3FB99999A0000000 %29 = fptosi float %28 to i32 %30 = shl i32 %29, 4 %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %30) %32 = shl i32 %29, 4 %33 = or i32 %32, 4 %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %33) %35 = shl i32 %29, 4 %36 = or i32 %35, 8 %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %36) %38 = shl i32 %29, 4 %39 = or i32 %38, 12 %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %39) %41 = fmul float %18, %31 %42 = fmul float %19, %34 %43 = fadd float %41, %42 %44 = fmul float %20, %37 %45 = fadd float %43, %44 %46 = fmul float %21, %40 %47 = fadd float %45, %46 %48 = fmul float %26, 2.000000e+00 %49 = fadd float %48, 0x3FF19999A0000000 %50 = fptosi float %49 to i32 %51 = shl i32 %50, 4 %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %51) %53 = shl i32 %50, 4 %54 = or i32 %53, 4 %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %54) %56 = shl i32 %50, 4 %57 = or i32 %56, 8 %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %57) %59 = shl i32 %50, 4 %60 = or i32 %59, 12 %61 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %60) %62 = fmul float %18, %52 %63 = fmul float %19, %55 %64 = fadd float %62, %63 %65 = fmul float %20, %58 %66 = fadd float %64, %65 %67 = fmul float %21, %61 %68 = fadd float %66, %67 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %47, float %68, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_waitcnt vmcnt(0) ; BF8C0770 v_madak_f32_e32 v0, 2.0, v5, 0x3dcccccd ; 30000AF4 3DCCCCCD v_madak_f32_e32 v5, 2.0, v5, 0x3f8ccccd ; 300A0AF4 3F8CCCCD v_cvt_i32_f32_e32 v0, v0 ; 7E001100 v_cvt_i32_f32_e32 v5, v5 ; 7E0A1105 v_lshlrev_b32_e32 v0, 4, v0 ; 24000084 v_lshlrev_b32_e32 v5, 4, v5 ; 240A0A84 buffer_load_dword v6, v0, s[0:3], 0 offen ; E0501000 80000600 v_or_b32_e32 v7, 4, v0 ; 280E0084 v_or_b32_e32 v8, 8, v0 ; 28100088 v_or_b32_e32 v0, 12, v0 ; 2800008C buffer_load_dword v9, v5, s[0:3], 0 offen ; E0501000 80000905 s_nop 0 ; BF800000 buffer_load_dword v7, v7, s[0:3], 0 offen ; E0501000 80000707 v_or_b32_e32 v10, 4, v5 ; 28140A84 v_or_b32_e32 v11, 8, v5 ; 28160A88 buffer_load_dword v10, v10, s[0:3], 0 offen ; E0501000 80000A0A v_or_b32_e32 v5, 12, v5 ; 280A0A8C buffer_load_dword v8, v8, s[0:3], 0 offen ; E0501000 80000808 s_nop 0 ; BF800000 buffer_load_dword v11, v11, s[0:3], 0 offen ; E0501000 80000B0B s_nop 0 ; BF800000 buffer_load_dword v0, v0, s[0:3], 0 offen ; E0501000 80000000 s_nop 0 ; BF800000 buffer_load_dword v5, v5, s[0:3], 0 offen ; E0501000 80000505 s_waitcnt vmcnt(5) ; BF8C0775 v_mul_f32_e32 v7, v7, v2 ; 0A0E0507 v_mac_f32_e32 v7, v6, v1 ; 2C0E0306 v_mov_b32_e32 v6, 1.0 ; 7E0C02F2 s_waitcnt vmcnt(4) ; BF8C0774 v_mul_f32_e32 v2, v10, v2 ; 0A04050A v_mac_f32_e32 v2, v9, v1 ; 2C040309 s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v7, v8, v3 ; 2C0E0708 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v2, v11, v3 ; 2C04070B s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v7, v0, v4 ; 2C0E0900 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v2, v5, v4 ; 2C040905 v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v7, v2, v0, v6 ; C40008CF 06000207 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 12 Code Size: 276 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float %31 = call i32 @llvm.SI.packf16(float %27, float %28) %32 = bitcast i32 %31 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %30, float %32, float %30, float %32) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0xc ; C0220000 0000000C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e64 v0, s4, v0 ; D2960000 00020004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e64 v1, s6, v1 ; D2960001 00020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 96 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL CONST[0..1] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[0], CONST[0] 2: DP4 TEMP[1].x, IN[0], CONST[1] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = extractelement <4 x float> %25, i32 2 %29 = extractelement <4 x float> %25, i32 3 %30 = fmul float %26, %14 %31 = fmul float %27, %15 %32 = fadd float %30, %31 %33 = fmul float %28, %16 %34 = fadd float %32, %33 %35 = fmul float %29, %17 %36 = fadd float %34, %35 %37 = fmul float %26, %18 %38 = fmul float %27, %19 %39 = fadd float %37, %38 %40 = fmul float %28, %20 %41 = fadd float %39, %40 %42 = fmul float %29, %21 %43 = fadd float %41, %42 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %36, float %43, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x4 ; C0220100 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x14 ; C0220140 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x0 ; C0220180 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x10 ; C02201C0 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x8 ; C0220200 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x18 ; C0220240 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0xc ; C0220280 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x1c ; C0220000 0000001C s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v4, s4, v1 ; 0A080204 v_mul_f32_e32 v1, s5, v1 ; 0A020205 v_mac_f32_e32 v4, s6, v0 ; 2C080006 v_mac_f32_e32 v1, s7, v0 ; 2C020007 v_mac_f32_e32 v4, s8, v2 ; 2C080408 v_mac_f32_e32 v1, s9, v2 ; 2C020409 v_mac_f32_e32 v4, s10, v3 ; 2C08060A v_mac_f32_e32 v1, s0, v3 ; 2C020600 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 v_mov_b32_e32 v2, 0 ; 7E040280 exp 15, 12, 0, 1, 0, v4, v1, v2, v0 ; C40008CF 00020104 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 184 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float %31 = call i32 @llvm.SI.packf16(float %27, float %28) %32 = bitcast i32 %31 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %30, float %32, float %30, float %32) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0xc ; C0220000 0000000C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s5 ; 7E000205 v_cvt_pkrtz_f16_f32_e64 v0, s4, v0 ; D2960000 00020004 v_mov_b32_e32 v1, s0 ; 7E020200 v_cvt_pkrtz_f16_f32_e64 v1, s6, v1 ; D2960001 00020206 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 96 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL CONST[0..3] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[2], CONST[2] 2: DP4 TEMP[1].x, IN[2], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: MAD TEMP[1], IN[0], CONST[1], CONST[0] 5: MOV TEMP[2].xy, IN[1].xyxx 6: MOV OUT[1], TEMP[1] 7: MOV OUT[0], TEMP[0] 8: MOV OUT[2], TEMP[2] 9: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %45 = load <16 x i8>, <16 x i8> addrspace(2)* %44, align 16, !tbaa !0 %46 = add i32 %5, %8 %47 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %46) %48 = extractelement <4 x float> %47, i32 0 %49 = extractelement <4 x float> %47, i32 1 %50 = extractelement <4 x float> %47, i32 2 %51 = extractelement <4 x float> %47, i32 3 %52 = fmul float %48, %22 %53 = fmul float %49, %23 %54 = fadd float %52, %53 %55 = fmul float %50, %24 %56 = fadd float %54, %55 %57 = fmul float %51, %25 %58 = fadd float %56, %57 %59 = fmul float %48, %26 %60 = fmul float %49, %27 %61 = fadd float %59, %60 %62 = fmul float %50, %28 %63 = fadd float %61, %62 %64 = fmul float %51, %29 %65 = fadd float %63, %64 %66 = fmul float %34, %18 %67 = fadd float %66, %14 %68 = fmul float %35, %19 %69 = fadd float %68, %15 %70 = fmul float %36, %20 %71 = fadd float %70, %16 %72 = fmul float %37, %21 %73 = fadd float %72, %17 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %67, float %69, float %71, float %73) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %42, float %43, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %58, float %65, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 1.0 ; 7E0202F2 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x0 ; C0220200 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x4 ; C0220240 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x8 ; C0220280 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0xc ; C02202C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x10 ; C0220500 00000010 buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[8:11], v0, s[16:19], 0 idxen ; E00C2000 80040800 s_buffer_load_dword s4, s[0:3], 0x14 ; C0220100 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x18 ; C0220140 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x1c ; C0220180 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x20 ; C02201C0 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x24 ; C0220300 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x28 ; C0220340 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x2c ; C0220380 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x30 ; C02203C0 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x34 ; C0220400 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x38 ; C0220440 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x3c ; C0220000 0000003C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s8 ; 7E000208 v_mov_b32_e32 v12, s9 ; 7E180209 v_mov_b32_e32 v13, s10 ; 7E1A020A v_mov_b32_e32 v14, s11 ; 7E1C020B v_mac_f32_e32 v0, s20, v2 ; 2C000414 v_mac_f32_e32 v12, s4, v3 ; 2C180604 v_mac_f32_e32 v13, s5, v4 ; 2C1A0805 v_mac_f32_e32 v14, s6, v5 ; 2C1C0A06 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v2, s12, v9 ; 0A04120C exp 15, 32, 0, 0, 0, v0, v12, v13, v14 ; C400020F 0E0D0C00 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s16, v9 ; 0A001210 v_mac_f32_e32 v2, s7, v8 ; 2C041007 v_mac_f32_e32 v0, s15, v8 ; 2C00100F v_mac_f32_e32 v2, s13, v10 ; 2C04140D v_mac_f32_e32 v0, s17, v10 ; 2C001411 exp 15, 33, 0, 0, 0, v6, v7, v0, v0 ; C400021F 00000706 v_mac_f32_e32 v2, s14, v11 ; 2C04160E s_waitcnt expcnt(0) ; BF8C070F v_mac_f32_e32 v0, s0, v11 ; 2C001600 v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v2, v0, v3, v1 ; C40008CF 01030002 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 16 Code Size: 384 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzx 1: MOV TEMP[1].xy, IN[1].xyyy 2: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D 3: MUL TEMP[1].x, IN[0].wwww, TEMP[1].wwww 4: MOV TEMP[0].w, TEMP[1].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %33 = bitcast float %31 to i32 %34 = bitcast float %32 to i32 %35 = insertelement <2 x i32> undef, i32 %33, i32 0 %36 = insertelement <2 x i32> %35, i32 %34, i32 1 %37 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %36, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %38 = extractelement <4 x float> %37, i32 3 %39 = fmul float %30, %38 %40 = call i32 @llvm.SI.packf16(float %27, float %28) %41 = bitcast i32 %40 to float %42 = call i32 @llvm.SI.packf16(float %29, float %39) %43 = bitcast i32 %42 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v0, 8, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[8:15], s[0:3] ; F0800800 00020006 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 v_cvt_pkrtz_f16_f32_e64 v0, v4, v0 ; D2960000 00020104 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 120 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL CONST[0..1] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[2], CONST[0] 2: DP4 TEMP[1].x, IN[2], CONST[1] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: MOV OUT[2], IN[1] 5: MOV OUT[1], IN[0] 6: MOV OUT[0], TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = extractelement <4 x float> %25, i32 2 %29 = extractelement <4 x float> %25, i32 3 %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %14 %47 = fmul float %43, %15 %48 = fadd float %46, %47 %49 = fmul float %44, %16 %50 = fadd float %48, %49 %51 = fmul float %45, %17 %52 = fadd float %50, %51 %53 = fmul float %42, %18 %54 = fmul float %43, %19 %55 = fadd float %53, %54 %56 = fmul float %44, %20 %57 = fadd float %55, %56 %58 = fmul float %45, %21 %59 = fadd float %57, %58 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %26, float %27, float %28, float %29) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %34, float %35, float %36, float %37) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 1.0 ; 7E0202F2 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[0:3], 0x0 ; C0220200 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x4 ; C0220240 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x8 ; C0220280 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0xc ; C02202C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x10 ; C0220500 00000010 buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_nop 0 ; BF800000 buffer_load_format_xyzw v[10:13], v0, s[16:19], 0 idxen ; E00C2000 80040A00 s_buffer_load_dword s4, s[0:3], 0x14 ; C0220100 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x18 ; C0220140 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x1c ; C0220000 0000001C s_waitcnt vmcnt(2) ; BF8C0772 exp 15, 32, 0, 0, 0, v2, v3, v4, v5 ; C400020F 05040302 s_waitcnt vmcnt(1) ; BF8C0771 exp 15, 33, 0, 0, 0, v6, v7, v8, v9 ; C400021F 09080706 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v0, s9, v11 ; 0A001609 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v2, s4, v11 ; 0A041604 v_mac_f32_e32 v0, s8, v10 ; 2C001408 v_mac_f32_e32 v2, s20, v10 ; 2C041414 v_mac_f32_e32 v0, s10, v12 ; 2C00180A v_mac_f32_e32 v2, s5, v12 ; 2C041805 v_mac_f32_e32 v0, s11, v13 ; 2C001A0B v_mac_f32_e32 v2, s0, v13 ; 2C041A00 v_mov_b32_e32 v3, 0 ; 7E060280 exp 15, 12, 0, 1, 0, v0, v2, v3, v1 ; C40008CF 01030200 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 16 Code Size: 256 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzx 1: MUL TEMP[1].x, IN[0].wwww, IN[1].wwww 2: MOV TEMP[0].w, TEMP[1].xxxx 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %24 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %27 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %28 = fmul float %26, %27 %29 = call i32 @llvm.SI.packf16(float %23, float %24) %30 = bitcast i32 %29 to float %31 = call i32 @llvm.SI.packf16(float %25, float %28) %32 = bitcast i32 %31 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %30, float %32, float %30, float %32) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v0, v0, 3, 1, [m0] ; D4000700 v_interp_p2_f32 v0, [v0], v1, 3, 1, [m0] ; D4010701 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 v_cvt_pkrtz_f16_f32_e64 v0, v4, v0 ; D2960000 00020104 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 76 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL OUT[4], GENERIC[3] DCL CONST[0..95] DCL TEMP[0..2], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 1020.0400, 2.1000} IMM[1] FLT32 { 3.1000, 0.1000, 1.1000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: MAD TEMP[1].x, IMM[0].zzzz, IN[1].zzzz, IMM[0].wwww 2: F2I TEMP[1].x, TEMP[1].xxxx 3: UARL ADDR[0].x, TEMP[1].xxxx 4: UARL ADDR[0].x, TEMP[1].xxxx 5: DP4 TEMP[0].x, IN[2], CONST[ADDR[0].x] 6: MAD TEMP[1].x, IMM[0].zzzz, IN[1].zzzz, IMM[1].xxxx 7: F2I TEMP[1].x, TEMP[1].xxxx 8: UARL ADDR[0].x, TEMP[1].xxxx 9: DP4 TEMP[1].x, IN[2], CONST[ADDR[0].x] 10: MOV TEMP[0].y, TEMP[1].xxxx 11: MAD TEMP[1].x, IMM[0].zzzz, IN[1].zzzz, IMM[1].yyyy 12: F2I TEMP[1].x, TEMP[1].xxxx 13: UARL ADDR[0].x, TEMP[1].xxxx 14: MOV TEMP[1], CONST[ADDR[0].x] 15: MAD TEMP[2].x, IMM[0].zzzz, IN[1].zzzz, IMM[1].zzzz 16: F2I TEMP[2].x, TEMP[2].xxxx 17: UARL ADDR[0].x, TEMP[2].xxxx 18: MOV TEMP[2], CONST[ADDR[0].x] 19: MOV OUT[2], IN[1] 20: MOV OUT[3], TEMP[1] 21: MOV OUT[1], IN[0] 22: MOV OUT[4], TEMP[2] 23: MOV OUT[0], TEMP[0] 24: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %15 = load <16 x i8>, <16 x i8> addrspace(2)* %14, align 16, !tbaa !0 %16 = add i32 %5, %8 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %16) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = extractelement <4 x float> %25, i32 2 %29 = extractelement <4 x float> %25, i32 3 %30 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %31 = load <16 x i8>, <16 x i8> addrspace(2)* %30, align 16, !tbaa !0 %32 = add i32 %5, %8 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %32) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %28, 0x408FE051E0000000 %39 = fadd float %38, 0x4000CCCCC0000000 %40 = fptosi float %39 to i32 %41 = shl i32 %40, 4 %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %41) %43 = shl i32 %40, 4 %44 = or i32 %43, 4 %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %44) %46 = shl i32 %40, 4 %47 = or i32 %46, 8 %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %47) %49 = shl i32 %40, 4 %50 = or i32 %49, 12 %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %50) %52 = fmul float %34, %42 %53 = fmul float %35, %45 %54 = fadd float %52, %53 %55 = fmul float %36, %48 %56 = fadd float %54, %55 %57 = fmul float %37, %51 %58 = fadd float %56, %57 %59 = fmul float %28, 0x408FE051E0000000 %60 = fadd float %59, 0x4008CCCCC0000000 %61 = fptosi float %60 to i32 %62 = shl i32 %61, 4 %63 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %62) %64 = shl i32 %61, 4 %65 = or i32 %64, 4 %66 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %65) %67 = shl i32 %61, 4 %68 = or i32 %67, 8 %69 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %68) %70 = shl i32 %61, 4 %71 = or i32 %70, 12 %72 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %71) %73 = fmul float %34, %63 %74 = fmul float %35, %66 %75 = fadd float %73, %74 %76 = fmul float %36, %69 %77 = fadd float %75, %76 %78 = fmul float %37, %72 %79 = fadd float %77, %78 %80 = fmul float %28, 0x408FE051E0000000 %81 = fadd float %80, 0x3FB99999A0000000 %82 = fptosi float %81 to i32 %83 = shl i32 %82, 4 %84 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %83) %85 = shl i32 %82, 4 %86 = or i32 %85, 4 %87 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %86) %88 = shl i32 %82, 4 %89 = or i32 %88, 8 %90 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %89) %91 = shl i32 %82, 4 %92 = or i32 %91, 12 %93 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %92) %94 = fmul float %28, 0x408FE051E0000000 %95 = fadd float %94, 0x3FF19999A0000000 %96 = fptosi float %95 to i32 %97 = shl i32 %96, 4 %98 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %97) %99 = shl i32 %96, 4 %100 = or i32 %99, 4 %101 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %100) %102 = shl i32 %96, 4 %103 = or i32 %102, 8 %104 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %103) %105 = shl i32 %96, 4 %106 = or i32 %105, 12 %107 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %106) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %26, float %27, float %28, float %29) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %84, float %87, float %90, float %93) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %98, float %101, float %104, float %107) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %58, float %79, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 v_mov_b32_e32 v1, 0x447f028f ; 7E0202FF 447F028F v_mov_b32_e32 v2, 1.0 ; 7E0402F2 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[3:6], v0, s[4:7], 0 idxen ; E00C2000 80010300 s_nop 0 ; BF800000 buffer_load_format_xyzw v[7:10], v0, s[12:15], 0 idxen ; E00C2000 80030700 s_nop 0 ; BF800000 buffer_load_format_xyzw v[11:14], v0, s[16:19], 0 idxen ; E00C2000 80040B00 s_waitcnt vmcnt(2) ; BF8C0772 exp 15, 32, 0, 0, 0, v3, v4, v5, v6 ; C400020F 06050403 s_waitcnt vmcnt(1) ; BF8C0771 v_madak_f32_e32 v0, v9, v1, 0x40066666 ; 30000309 40066666 s_waitcnt expcnt(0) ; BF8C070F v_madak_f32_e32 v3, v9, v1, 0x40466666 ; 30060309 40466666 v_cvt_i32_f32_e32 v0, v0 ; 7E001100 v_cvt_i32_f32_e32 v3, v3 ; 7E061103 v_madak_f32_e32 v4, v9, v1, 0x3dcccccd ; 30080309 3DCCCCCD v_madak_f32_e32 v1, v9, v1, 0x3f8ccccd ; 30020309 3F8CCCCD v_cvt_i32_f32_e32 v4, v4 ; 7E081104 v_cvt_i32_f32_e32 v1, v1 ; 7E021101 v_lshlrev_b32_e32 v0, 4, v0 ; 24000084 v_lshlrev_b32_e32 v3, 4, v3 ; 24060684 v_lshlrev_b32_e32 v4, 4, v4 ; 24080884 v_lshlrev_b32_e32 v1, 4, v1 ; 24020284 buffer_load_dword v5, v0, s[0:3], 0 offen ; E0501000 80000500 v_or_b32_e32 v6, 4, v0 ; 280C0084 v_or_b32_e32 v15, 8, v0 ; 281E0088 v_or_b32_e32 v0, 12, v0 ; 2800008C buffer_load_dword v16, v3, s[0:3], 0 offen ; E0501000 80001003 v_or_b32_e32 v17, 4, v3 ; 28220684 v_or_b32_e32 v18, 8, v3 ; 28240688 v_or_b32_e32 v3, 12, v3 ; 2806068C buffer_load_dword v19, v4, s[0:3], 0 offen ; E0501000 80001304 v_or_b32_e32 v20, 4, v4 ; 28280884 v_or_b32_e32 v21, 8, v4 ; 282A0888 v_or_b32_e32 v4, 12, v4 ; 2808088C buffer_load_dword v22, v1, s[0:3], 0 offen ; E0501000 80001601 v_or_b32_e32 v23, 4, v1 ; 282E0284 v_or_b32_e32 v24, 8, v1 ; 28300288 v_or_b32_e32 v1, 12, v1 ; 2802028C buffer_load_dword v20, v20, s[0:3], 0 offen ; E0501000 80001414 s_nop 0 ; BF800000 buffer_load_dword v21, v21, s[0:3], 0 offen ; E0501000 80001515 s_nop 0 ; BF800000 buffer_load_dword v4, v4, s[0:3], 0 offen ; E0501000 80000404 s_nop 0 ; BF800000 buffer_load_dword v6, v6, s[0:3], 0 offen ; E0501000 80000606 s_nop 0 ; BF800000 buffer_load_dword v17, v17, s[0:3], 0 offen ; E0501000 80001111 s_nop 0 ; BF800000 buffer_load_dword v23, v23, s[0:3], 0 offen ; E0501000 80001717 s_nop 0 ; BF800000 buffer_load_dword v24, v24, s[0:3], 0 offen ; E0501000 80001818 s_nop 0 ; BF800000 buffer_load_dword v1, v1, s[0:3], 0 offen ; E0501000 80000101 s_nop 0 ; BF800000 buffer_load_dword v15, v15, s[0:3], 0 offen ; E0501000 80000F0F s_nop 0 ; BF800000 buffer_load_dword v18, v18, s[0:3], 0 offen ; E0501000 80001212 s_nop 0 ; BF800000 buffer_load_dword v0, v0, s[0:3], 0 offen ; E0501000 80000000 s_nop 0 ; BF800000 buffer_load_dword v3, v3, s[0:3], 0 offen ; E0501000 80000303 exp 15, 33, 0, 0, 0, v7, v8, v9, v10 ; C400021F 0A090807 s_waitcnt vmcnt(9) ; BF8C0779 exp 15, 34, 0, 0, 0, v19, v20, v21, v4 ; C400022F 04151413 s_waitcnt vmcnt(8) expcnt(0) ; BF8C0708 v_mul_f32_e32 v4, v6, v12 ; 0A081906 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v6, v17, v12 ; 0A0C1911 v_mac_f32_e32 v4, v5, v11 ; 2C081705 v_mac_f32_e32 v6, v16, v11 ; 2C0C1710 s_waitcnt vmcnt(4) ; BF8C0774 exp 15, 35, 0, 0, 0, v22, v23, v24, v1 ; C400023F 01181716 s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v4, v15, v13 ; 2C081B0F s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v6, v18, v13 ; 2C0C1B12 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v4, v0, v14 ; 2C081D00 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v6, v3, v14 ; 2C0C1D03 v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v4, v6, v0, v2 ; C40008CF 02000604 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 28 Code Size: 504 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0..1], LOCAL 0: MAD TEMP[0], IN[0], IN[3], IN[2] 1: MUL TEMP[1].x, TEMP[0].wwww, IN[1].wwww 2: MOV TEMP[0].w, TEMP[1].xxxx 3: MOV OUT[0], TEMP[0] 4: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %24 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %26 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %27 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %6, <2 x i32> %8) %36 = fmul float %23, %32 %37 = fadd float %36, %28 %38 = fmul float %24, %33 %39 = fadd float %38, %29 %40 = fmul float %25, %34 %41 = fadd float %40, %30 %42 = fmul float %26, %35 %43 = fadd float %42, %31 %44 = fmul float %43, %27 %45 = call i32 @llvm.SI.packf16(float %37, float %39) %46 = bitcast i32 %45 to float %47 = call i32 @llvm.SI.packf16(float %41, float %44) %48 = bitcast i32 %47 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %46, float %48, float %46, float %48) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 3, 1, [m0] ; D4180700 v_interp_p2_f32 v6, [v6], v1, 3, 1, [m0] ; D4190701 v_interp_p1_f32 v7, v0, 0, 2, [m0] ; D41C0800 v_interp_p2_f32 v7, [v7], v1, 0, 2, [m0] ; D41D0801 v_interp_p1_f32 v8, v0, 1, 2, [m0] ; D4200900 v_interp_p2_f32 v8, [v8], v1, 1, 2, [m0] ; D4210901 v_interp_p1_f32 v9, v0, 2, 2, [m0] ; D4240A00 v_interp_p2_f32 v9, [v9], v1, 2, 2, [m0] ; D4250A01 v_interp_p1_f32 v10, v0, 3, 2, [m0] ; D4280B00 v_interp_p2_f32 v10, [v10], v1, 3, 2, [m0] ; D4290B01 v_interp_p1_f32 v11, v0, 0, 3, [m0] ; D42C0C00 v_interp_p2_f32 v11, [v11], v1, 0, 3, [m0] ; D42D0C01 v_interp_p1_f32 v12, v0, 1, 3, [m0] ; D4300D00 v_interp_p2_f32 v12, [v12], v1, 1, 3, [m0] ; D4310D01 v_interp_p1_f32 v13, v0, 2, 3, [m0] ; D4340E00 v_interp_p2_f32 v13, [v13], v1, 2, 3, [m0] ; D4350E01 v_interp_p1_f32 v0, v0, 3, 3, [m0] ; D4000F00 v_interp_p2_f32 v0, [v0], v1, 3, 3, [m0] ; D4010F01 v_mac_f32_e32 v7, v11, v2 ; 2C0E050B v_mac_f32_e32 v8, v12, v3 ; 2C10070C v_mac_f32_e32 v9, v13, v4 ; 2C12090D v_mac_f32_e32 v10, v0, v5 ; 2C140B00 v_mul_f32_e32 v0, v6, v10 ; 0A001506 v_cvt_pkrtz_f16_f32_e64 v1, v7, v8 ; D2960001 00021107 v_cvt_pkrtz_f16_f32_e64 v0, v9, v0 ; D2960000 00020109 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 156 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL OUT[4], GENERIC[3] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[1], CONST[2] 2: DP4 TEMP[1].x, IN[1], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[1], CONST[4] 5: DP4 TEMP[2].x, IN[1], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], IN[0] 9: MOV OUT[2], CONST[0] 10: MOV OUT[3], CONST[1] 11: MOV OUT[0], TEMP[0] 12: MOV OUT[4], TEMP[1] 13: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %47 = load <16 x i8>, <16 x i8> addrspace(2)* %46, align 16, !tbaa !0 %48 = add i32 %5, %8 %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %47, i32 0, i32 %48) %50 = extractelement <4 x float> %49, i32 0 %51 = extractelement <4 x float> %49, i32 1 %52 = extractelement <4 x float> %49, i32 2 %53 = extractelement <4 x float> %49, i32 3 %54 = fmul float %50, %22 %55 = fmul float %51, %23 %56 = fadd float %54, %55 %57 = fmul float %52, %24 %58 = fadd float %56, %57 %59 = fmul float %53, %25 %60 = fadd float %58, %59 %61 = fmul float %50, %26 %62 = fmul float %51, %27 %63 = fadd float %61, %62 %64 = fmul float %52, %28 %65 = fadd float %63, %64 %66 = fmul float %53, %29 %67 = fadd float %65, %66 %68 = fmul float %50, %30 %69 = fmul float %51, %31 %70 = fadd float %68, %69 %71 = fmul float %52, %32 %72 = fadd float %70, %71 %73 = fmul float %53, %33 %74 = fadd float %72, %73 %75 = fmul float %50, %34 %76 = fmul float %51, %35 %77 = fadd float %75, %76 %78 = fmul float %52, %36 %79 = fadd float %77, %78 %80 = fmul float %53, %37 %81 = fadd float %79, %80 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %42, float %43, float %44, float %45) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %74, float %81, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %60, float %67, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v9, s4 ; 7E120204 v_mov_b32_e32 v10, s5 ; 7E140205 v_mov_b32_e32 v11, s6 ; 7E160206 s_waitcnt vmcnt(1) ; BF8C0771 exp 15, 32, 0, 0, 0, v1, v2, v3, v4 ; C400020F 04030201 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, s7 ; 7E020207 v_mov_b32_e32 v2, s8 ; 7E040208 v_mov_b32_e32 v3, s9 ; 7E060209 v_mov_b32_e32 v4, s10 ; 7E08020A exp 15, 33, 0, 0, 0, v9, v10, v11, v1 ; C400021F 010B0A09 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, s11 ; 7E02020B s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v9, s13, v6 ; 0A120C0D v_mul_f32_e32 v10, s17, v6 ; 0A140C11 v_mul_f32_e32 v11, s21, v6 ; 0A160C15 exp 15, 34, 0, 0, 0, v2, v3, v4, v1 ; C400022F 01040302 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v1, s23, v6 ; 0A020C17 v_mac_f32_e32 v9, s12, v5 ; 2C120A0C v_mac_f32_e32 v10, s16, v5 ; 2C140A10 v_mac_f32_e32 v11, s20, v5 ; 2C160A14 v_mac_f32_e32 v1, s22, v5 ; 2C020A16 v_mac_f32_e32 v9, s14, v7 ; 2C120E0E v_mac_f32_e32 v10, s18, v7 ; 2C140E12 v_mac_f32_e32 v11, s24, v7 ; 2C160E18 v_mac_f32_e32 v1, s26, v7 ; 2C020E1A v_mac_f32_e32 v9, s15, v8 ; 2C12100F v_mac_f32_e32 v10, s19, v8 ; 2C141013 v_mac_f32_e32 v11, s25, v8 ; 2C161019 v_mac_f32_e32 v1, s0, v8 ; 2C021000 exp 15, 35, 0, 0, 0, v11, v1, v0, v0 ; C400023F 0000010B s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v9, v10, v1, v0 ; C40008CF 00010A09 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 12 Code Size: 520 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xy, IN[3].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MAD TEMP[0], TEMP[0], IN[2], IN[1] 3: MUL TEMP[1].x, TEMP[0].wwww, IN[0].wwww 4: MOV TEMP[0].w, TEMP[1].xxxx 5: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 6: MOV OUT[0], TEMP[0] 7: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %38 = bitcast float %36 to i32 %39 = bitcast float %37 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %41, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %43 = extractelement <4 x float> %42, i32 0 %44 = extractelement <4 x float> %42, i32 1 %45 = extractelement <4 x float> %42, i32 2 %46 = extractelement <4 x float> %42, i32 3 %47 = fmul float %43, %32 %48 = fadd float %47, %28 %49 = fmul float %44, %33 %50 = fadd float %49, %29 %51 = fmul float %45, %34 %52 = fadd float %51, %30 %53 = fmul float %46, %35 %54 = fadd float %53, %31 %55 = fmul float %54, %27 %56 = fmul float %48, %55 %57 = fmul float %50, %55 %58 = fmul float %52, %55 %59 = call i32 @llvm.SI.packf16(float %56, float %57) %60 = bitcast i32 %59 to float %61 = call i32 @llvm.SI.packf16(float %58, float %55) %62 = bitcast i32 %61 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 3, 0, [m0] ; D4080300 v_interp_p2_f32 v2, [v2], v1, 3, 0, [m0] ; D4090301 v_interp_p1_f32 v3, v0, 0, 1, [m0] ; D40C0400 v_interp_p2_f32 v3, [v3], v1, 0, 1, [m0] ; D40D0401 v_interp_p1_f32 v4, v0, 1, 1, [m0] ; D4100500 v_interp_p2_f32 v4, [v4], v1, 1, 1, [m0] ; D4110501 v_interp_p1_f32 v5, v0, 2, 1, [m0] ; D4140600 v_interp_p2_f32 v5, [v5], v1, 2, 1, [m0] ; D4150601 v_interp_p1_f32 v6, v0, 3, 1, [m0] ; D4180700 v_interp_p2_f32 v6, [v6], v1, 3, 1, [m0] ; D4190701 v_interp_p1_f32 v7, v0, 0, 2, [m0] ; D41C0800 v_interp_p2_f32 v7, [v7], v1, 0, 2, [m0] ; D41D0801 v_interp_p1_f32 v8, v0, 1, 2, [m0] ; D4200900 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v8, [v8], v1, 1, 2, [m0] ; D4210901 v_interp_p1_f32 v9, v0, 2, 2, [m0] ; D4240A00 v_interp_p2_f32 v9, [v9], v1, 2, 2, [m0] ; D4250A01 v_interp_p1_f32 v10, v0, 3, 2, [m0] ; D4280B00 v_interp_p2_f32 v10, [v10], v1, 3, 2, [m0] ; D4290B01 v_interp_p1_f32 v11, v0, 0, 3, [m0] ; D42C0C00 v_interp_p2_f32 v11, [v11], v1, 0, 3, [m0] ; D42D0C01 v_interp_p1_f32 v12, v0, 1, 3, [m0] ; D4300D00 v_interp_p2_f32 v12, [v12], v1, 1, 3, [m0] ; D4310D01 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[8:15], s[0:3] ; F0800F00 00020B0B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v3, v7, v11 ; 2C061707 v_mac_f32_e32 v4, v8, v12 ; 2C081908 v_mac_f32_e32 v5, v9, v13 ; 2C0A1B09 v_mac_f32_e32 v6, v10, v14 ; 2C0C1D0A v_mul_f32_e32 v0, v2, v6 ; 0A000D02 v_mul_f32_e32 v1, v0, v3 ; 0A020700 v_mul_f32_e32 v2, v0, v4 ; 0A040900 v_mul_f32_e32 v3, v0, v5 ; 0A060B00 v_cvt_pkrtz_f16_f32_e64 v1, v1, v2 ; D2960001 00020501 v_cvt_pkrtz_f16_f32_e64 v0, v3, v0 ; D2960000 00020103 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 188 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL CONST[0..95] DCL TEMP[0..2], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 4.0000, 2.1000} IMM[1] FLT32 { 3.1000, 1.1000, 0.1000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: MAD TEMP[1].x, IN[3].xxxx, IMM[0].zzzz, IMM[0].wwww 2: F2I TEMP[1].x, TEMP[1].xxxx 3: UARL ADDR[0].x, TEMP[1].xxxx 4: UARL ADDR[0].x, TEMP[1].xxxx 5: DP4 TEMP[0].x, IN[2], CONST[ADDR[0].x] 6: MAD TEMP[1].x, IN[3].xxxx, IMM[0].zzzz, IMM[1].xxxx 7: F2I TEMP[1].x, TEMP[1].xxxx 8: UARL ADDR[0].x, TEMP[1].xxxx 9: DP4 TEMP[1].x, IN[2], CONST[ADDR[0].x] 10: MOV TEMP[0].y, TEMP[1].xxxx 11: MAD TEMP[1].x, IN[3].xxxx, IMM[0].zzzz, IMM[1].yyyy 12: F2I TEMP[1].x, TEMP[1].xxxx 13: MAD TEMP[2].x, IN[3].xxxx, IMM[0].zzzz, IMM[1].zzzz 14: F2I TEMP[2].x, TEMP[2].xxxx 15: UARL ADDR[0].x, TEMP[2].xxxx 16: UARL ADDR[0].x, TEMP[2].xxxx 17: MOV TEMP[2], CONST[ADDR[0].x] 18: UARL ADDR[0].x, TEMP[1].xxxx 19: UARL ADDR[0].x, TEMP[1].xxxx 20: MAD TEMP[1], IN[0], CONST[ADDR[0].x], TEMP[2] 21: MOV TEMP[2].xy, IN[1].xyxx 22: MOV OUT[1], TEMP[1] 23: MOV OUT[0], TEMP[0] 24: MOV OUT[2], TEMP[2] 25: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %15 = load <16 x i8>, <16 x i8> addrspace(2)* %14, align 16, !tbaa !0 %16 = add i32 %5, %8 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %16) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %29 = load <16 x i8>, <16 x i8> addrspace(2)* %28, align 16, !tbaa !0 %30 = add i32 %5, %8 %31 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %30) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %37 = load <16 x i8>, <16 x i8> addrspace(2)* %36, align 16, !tbaa !0 %38 = add i32 %5, %8 %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %38) %40 = extractelement <4 x float> %39, i32 0 %41 = fmul float %40, 4.000000e+00 %42 = fadd float %41, 0x4000CCCCC0000000 %43 = fptosi float %42 to i32 %44 = shl i32 %43, 4 %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %44) %46 = shl i32 %43, 4 %47 = or i32 %46, 4 %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %47) %49 = shl i32 %43, 4 %50 = or i32 %49, 8 %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %50) %52 = shl i32 %43, 4 %53 = or i32 %52, 12 %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %53) %55 = fmul float %32, %45 %56 = fmul float %33, %48 %57 = fadd float %55, %56 %58 = fmul float %34, %51 %59 = fadd float %57, %58 %60 = fmul float %35, %54 %61 = fadd float %59, %60 %62 = fmul float %40, 4.000000e+00 %63 = fadd float %62, 0x4008CCCCC0000000 %64 = fptosi float %63 to i32 %65 = shl i32 %64, 4 %66 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %65) %67 = shl i32 %64, 4 %68 = or i32 %67, 4 %69 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %68) %70 = shl i32 %64, 4 %71 = or i32 %70, 8 %72 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %71) %73 = shl i32 %64, 4 %74 = or i32 %73, 12 %75 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %74) %76 = fmul float %32, %66 %77 = fmul float %33, %69 %78 = fadd float %76, %77 %79 = fmul float %34, %72 %80 = fadd float %78, %79 %81 = fmul float %35, %75 %82 = fadd float %80, %81 %83 = fmul float %40, 4.000000e+00 %84 = fadd float %83, 0x3FF19999A0000000 %85 = fptosi float %84 to i32 %86 = fmul float %40, 4.000000e+00 %87 = fadd float %86, 0x3FB99999A0000000 %88 = fptosi float %87 to i32 %89 = shl i32 %88, 4 %90 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %89) %91 = shl i32 %88, 4 %92 = or i32 %91, 4 %93 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %92) %94 = shl i32 %88, 4 %95 = or i32 %94, 8 %96 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %95) %97 = shl i32 %88, 4 %98 = or i32 %97, 12 %99 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %98) %100 = shl i32 %85, 4 %101 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %100) %102 = fmul float %18, %101 %103 = fadd float %102, %90 %104 = shl i32 %85, 4 %105 = or i32 %104, 4 %106 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %105) %107 = fmul float %19, %106 %108 = fadd float %107, %93 %109 = shl i32 %85, 4 %110 = or i32 %109, 8 %111 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %110) %112 = fmul float %20, %111 %113 = fadd float %112, %96 %114 = shl i32 %85, 4 %115 = or i32 %114, 12 %116 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %115) %117 = fmul float %21, %116 %118 = fadd float %117, %99 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %103, float %108, float %113, float %118) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %26, float %27, float %96, float %99) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %61, float %82, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x20 ; C00A0404 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x30 ; C00A0504 00000030 v_mov_b32_e32 v1, 1.0 ; 7E0202F2 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[8:11], v0, s[16:19], 0 idxen ; E00C2000 80040800 s_nop 0 ; BF800000 buffer_load_format_xyzw v[12:15], v0, s[20:23], 0 idxen ; E00C2000 80050C00 s_waitcnt vmcnt(0) ; BF8C0770 v_madak_f32_e32 v0, 4.0, v12, 0x40066666 ; 300018F6 40066666 v_madak_f32_e32 v13, 4.0, v12, 0x40466666 ; 301A18F6 40466666 v_madak_f32_e32 v14, 4.0, v12, 0x3f8ccccd ; 301C18F6 3F8CCCCD v_madak_f32_e32 v12, 4.0, v12, 0x3dcccccd ; 301818F6 3DCCCCCD v_cvt_i32_f32_e32 v0, v0 ; 7E001100 v_cvt_i32_f32_e32 v13, v13 ; 7E1A110D v_cvt_i32_f32_e32 v12, v12 ; 7E18110C v_cvt_i32_f32_e32 v14, v14 ; 7E1C110E v_lshlrev_b32_e32 v0, 4, v0 ; 24000084 v_lshlrev_b32_e32 v13, 4, v13 ; 241A1A84 v_lshlrev_b32_e32 v12, 4, v12 ; 24181884 v_lshlrev_b32_e32 v14, 4, v14 ; 241C1C84 buffer_load_dword v15, v0, s[0:3], 0 offen ; E0501000 80000F00 v_or_b32_e32 v16, 4, v0 ; 28200084 v_or_b32_e32 v17, 8, v0 ; 28220088 v_or_b32_e32 v0, 12, v0 ; 2800008C buffer_load_dword v18, v12, s[0:3], 0 offen ; E0501000 8000120C v_or_b32_e32 v19, 4, v12 ; 28261884 v_or_b32_e32 v20, 8, v12 ; 28281888 v_or_b32_e32 v12, 12, v12 ; 2818188C buffer_load_dword v21, v14, s[0:3], 0 offen ; E0501000 8000150E v_or_b32_e32 v22, 4, v14 ; 282C1C84 v_or_b32_e32 v23, 8, v14 ; 282E1C88 v_or_b32_e32 v14, 12, v14 ; 281C1C8C buffer_load_dword v19, v19, s[0:3], 0 offen ; E0501000 80001313 s_nop 0 ; BF800000 buffer_load_dword v20, v20, s[0:3], 0 offen ; E0501000 80001414 s_nop 0 ; BF800000 buffer_load_dword v12, v12, s[0:3], 0 offen ; E0501000 80000C0C s_nop 0 ; BF800000 buffer_load_dword v22, v22, s[0:3], 0 offen ; E0501000 80001616 s_nop 0 ; BF800000 buffer_load_dword v23, v23, s[0:3], 0 offen ; E0501000 80001717 s_nop 0 ; BF800000 buffer_load_dword v14, v14, s[0:3], 0 offen ; E0501000 80000E0E s_nop 0 ; BF800000 buffer_load_dword v16, v16, s[0:3], 0 offen ; E0501000 80001010 v_or_b32_e32 v24, 4, v13 ; 28301A84 buffer_load_dword v24, v24, s[0:3], 0 offen ; E0501000 80001818 s_nop 0 ; BF800000 buffer_load_dword v25, v13, s[0:3], 0 offen ; E0501000 8000190D s_nop 0 ; BF800000 buffer_load_dword v17, v17, s[0:3], 0 offen ; E0501000 80001111 v_or_b32_e32 v26, 8, v13 ; 28341A88 buffer_load_dword v26, v26, s[0:3], 0 offen ; E0501000 80001A1A v_or_b32_e32 v13, 12, v13 ; 281A1A8C buffer_load_dword v0, v0, s[0:3], 0 offen ; E0501000 80000000 s_nop 0 ; BF800000 buffer_load_dword v13, v13, s[0:3], 0 offen ; E0501000 80000D0D s_waitcnt vmcnt(13) ; BF8C077D v_mac_f32_e32 v18, v21, v2 ; 2C240515 s_waitcnt vmcnt(9) ; BF8C0779 v_mac_f32_e32 v19, v22, v3 ; 2C260716 s_waitcnt vmcnt(8) ; BF8C0778 v_mad_f32 v2, v23, v4, v20 ; D1C10002 04520917 s_waitcnt vmcnt(7) ; BF8C0777 v_mad_f32 v3, v14, v5, v12 ; D1C10003 04320B0E s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v4, v16, v9 ; 0A081310 v_mac_f32_e32 v4, v15, v8 ; 2C08110F s_waitcnt vmcnt(5) ; BF8C0775 v_mul_f32_e32 v5, v24, v9 ; 0A0A1318 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v5, v25, v8 ; 2C0A1119 exp 15, 32, 0, 0, 0, v18, v19, v2, v3 ; C400020F 03021312 s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v4, v17, v10 ; 2C081511 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v5, v26, v10 ; 2C0A151A exp 15, 33, 0, 0, 0, v6, v7, v20, v12 ; C400021F 0C140706 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v4, v0, v11 ; 2C081700 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v5, v13, v11 ; 2C0A170D v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v4, v5, v0, v1 ; C40008CF 01000504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 28 Code Size: 524 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xyz, IN[0].xyzx 1: MOV TEMP[1].xy, IN[1].xyyy 2: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D 3: MUL TEMP[1].x, IN[0].wwww, TEMP[1].wwww 4: MOV TEMP[0].w, TEMP[1].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %33 = bitcast float %31 to i32 %34 = bitcast float %32 to i32 %35 = insertelement <2 x i32> undef, i32 %33, i32 0 %36 = insertelement <2 x i32> %35, i32 %34, i32 1 %37 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %36, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %38 = extractelement <4 x float> %37, i32 3 %39 = fmul float %30, %38 %40 = call i32 @llvm.SI.packf16(float %27, float %28) %41 = bitcast i32 %40 to float %42 = call i32 @llvm.SI.packf16(float %29, float %39) %43 = bitcast i32 %42 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v0, 8, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[8:15], s[0:3] ; F0800800 00020006 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 v_cvt_pkrtz_f16_f32_e64 v0, v4, v0 ; D2960000 00020104 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 8 Code Size: 120 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** [1120/170058:ERROR:renderer_main.cc(200)] Running without renderer sandbox SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[0], CONST[2] 2: DP4 TEMP[1].x, IN[0], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[0], CONST[4] 5: DP4 TEMP[2].x, IN[0], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], CONST[0] 9: MOV OUT[2], CONST[1] 10: MOV OUT[0], TEMP[0] 11: MOV OUT[3], TEMP[1] 12: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %22 %47 = fmul float %43, %23 %48 = fadd float %46, %47 %49 = fmul float %44, %24 %50 = fadd float %48, %49 %51 = fmul float %45, %25 %52 = fadd float %50, %51 %53 = fmul float %42, %26 %54 = fmul float %43, %27 %55 = fadd float %53, %54 %56 = fmul float %44, %28 %57 = fadd float %55, %56 %58 = fmul float %45, %29 %59 = fadd float %57, %58 %60 = fmul float %42, %30 %61 = fmul float %43, %31 %62 = fadd float %60, %61 %63 = fmul float %44, %32 %64 = fadd float %62, %63 %65 = fmul float %45, %33 %66 = fadd float %64, %65 %67 = fmul float %42, %34 %68 = fmul float %43, %35 %69 = fadd float %67, %68 %70 = fmul float %44, %36 %71 = fadd float %69, %70 %72 = fmul float %45, %37 %73 = fadd float %71, %72 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %66, float %73, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s4 ; 7E080204 v_mov_b32_e32 v5, s5 ; 7E0A0205 v_mov_b32_e32 v6, s6 ; 7E0C0206 v_mov_b32_e32 v7, s7 ; 7E0E0207 exp 15, 32, 0, 0, 0, v4, v5, v6, v7 ; C400020F 07060504 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v4, s8 ; 7E080208 v_mov_b32_e32 v5, s9 ; 7E0A0209 v_mov_b32_e32 v6, s10 ; 7E0C020A v_mov_b32_e32 v7, s11 ; 7E0E020B exp 15, 33, 0, 0, 0, v4, v5, v6, v7 ; C400021F 07060504 s_waitcnt vmcnt(0) expcnt(0) ; BF8C0700 v_mul_f32_e32 v4, s13, v1 ; 0A08020D v_mul_f32_e32 v5, s17, v1 ; 0A0A0211 v_mul_f32_e32 v6, s21, v1 ; 0A0C0215 v_mul_f32_e32 v1, s23, v1 ; 0A020217 v_mac_f32_e32 v4, s12, v0 ; 2C08000C v_mac_f32_e32 v5, s16, v0 ; 2C0A0010 v_mac_f32_e32 v6, s20, v0 ; 2C0C0014 v_mac_f32_e32 v1, s22, v0 ; 2C020016 v_mac_f32_e32 v4, s14, v2 ; 2C08040E v_mac_f32_e32 v5, s18, v2 ; 2C0A0412 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s26, v2 ; 2C02041A v_mac_f32_e32 v4, s15, v3 ; 2C08060F v_mac_f32_e32 v5, s19, v3 ; 2C0A0613 v_mac_f32_e32 v6, s25, v3 ; 2C0C0619 v_mac_f32_e32 v1, s0, v3 ; 2C020600 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 34, 0, 0, 0, v6, v1, v0, v0 ; C400022F 00000106 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v4, v5, v1, v0 ; C40008CF 00010504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 8 Code Size: 476 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[1].xyzx 2: MOV TEMP[1].xy, IN[2].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MUL TEMP[0], TEMP[1], TEMP[0] 5: MUL TEMP[0], TEMP[0], IN[1].wwww 6: MAD TEMP[0], IN[0], TEMP[0].wwww, TEMP[0] 7: MOV OUT[0], TEMP[0] 8: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %37 = bitcast float %35 to i32 %38 = bitcast float %36 to i32 %39 = insertelement <2 x i32> undef, i32 %37, i32 0 %40 = insertelement <2 x i32> %39, i32 %38, i32 1 %41 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %40, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %31 %47 = fmul float %43, %32 %48 = fmul float %44, %33 %49 = fmul float %46, %34 %50 = fmul float %47, %34 %51 = fmul float %48, %34 %52 = fmul float %45, %34 %53 = fmul float %27, %52 %54 = fadd float %53, %49 %55 = fmul float %28, %52 %56 = fadd float %55, %50 %57 = fmul float %29, %52 %58 = fadd float %57, %51 %59 = fmul float %30, %52 %60 = fadd float %59, %52 %61 = call i32 @llvm.SI.packf16(float %54, float %56) %62 = bitcast i32 %61 to float %63 = call i32 @llvm.SI.packf16(float %58, float %60) %64 = bitcast i32 %63 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %62, float %64, float %62, float %64) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 v_interp_p1_f32 v8, v0, 2, 1, [m0] ; D4200600 v_interp_p2_f32 v8, [v8], v1, 2, 1, [m0] ; D4210601 v_interp_p1_f32 v9, v0, 3, 1, [m0] ; D4240700 v_interp_p2_f32 v9, [v9], v1, 3, 1, [m0] ; D4250701 v_interp_p1_f32 v10, v0, 0, 2, [m0] ; D4280800 v_interp_p2_f32 v10, [v10], v1, 0, 2, [m0] ; D4290801 v_interp_p1_f32 v11, v0, 1, 2, [m0] ; D42C0900 v_interp_p2_f32 v11, [v11], v1, 1, 2, [m0] ; D42D0901 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[10:13], 15, 0, 0, 0, 0, 0, 0, 0, v[10:11], s[8:15], s[0:3] ; F0800F00 00020A0A s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v6, v10 ; 0A001506 v_mul_f32_e32 v1, v7, v11 ; 0A021707 v_mul_f32_e32 v6, v8, v12 ; 0A0C1908 v_mul_f32_e32 v0, v9, v0 ; 0A000109 v_mul_f32_e32 v1, v9, v1 ; 0A020309 v_mul_f32_e32 v6, v9, v6 ; 0A0C0D09 v_mul_f32_e32 v7, v9, v13 ; 0A0E1B09 v_mac_f32_e32 v0, v7, v2 ; 2C000507 v_mac_f32_e32 v1, v7, v3 ; 2C020707 v_mac_f32_e32 v6, v7, v4 ; 2C0C0907 v_mac_f32_e32 v7, v7, v5 ; 2C0E0B07 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v6, v7 ; D2960001 00020F06 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 192 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL OUT[4], GENERIC[3] DCL CONST[0..143] DCL TEMP[0..3], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 1.0000, 1530.0599, 2.1000} IMM[1] FLT32 { 3.1000, 4.1000, 5.1000, 0.1000} IMM[2] FLT32 { 1.1000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: MAD TEMP[1].x, IMM[0].zzzz, IN[0].zzzz, IMM[0].wwww 2: F2I TEMP[1].x, TEMP[1].xxxx 3: UARL ADDR[0].x, TEMP[1].xxxx 4: UARL ADDR[0].x, TEMP[1].xxxx 5: DP4 TEMP[0].x, IN[1], CONST[ADDR[0].x] 6: MAD TEMP[1].x, IMM[0].zzzz, IN[0].zzzz, IMM[1].xxxx 7: F2I TEMP[1].x, TEMP[1].xxxx 8: UARL ADDR[0].x, TEMP[1].xxxx 9: DP4 TEMP[1].x, IN[1], CONST[ADDR[0].x] 10: MOV TEMP[0].y, TEMP[1].xxxx 11: MAD TEMP[1].x, IMM[0].zzzz, IN[0].zzzz, IMM[1].yyyy 12: F2I TEMP[1].x, TEMP[1].xxxx 13: UARL ADDR[0].x, TEMP[1].xxxx 14: UARL ADDR[0].x, TEMP[1].xxxx 15: DP4 TEMP[1].x, IN[1], CONST[ADDR[0].x] 16: MAD TEMP[2].x, IMM[0].zzzz, IN[0].zzzz, IMM[1].zzzz 17: F2I TEMP[2].x, TEMP[2].xxxx 18: UARL ADDR[0].x, TEMP[2].xxxx 19: DP4 TEMP[2].x, IN[1], CONST[ADDR[0].x] 20: MOV TEMP[1].y, TEMP[2].xxxx 21: MAD TEMP[2].x, IMM[0].zzzz, IN[0].zzzz, IMM[1].wwww 22: F2I TEMP[2].x, TEMP[2].xxxx 23: UARL ADDR[0].x, TEMP[2].xxxx 24: MOV TEMP[2], CONST[ADDR[0].x] 25: MAD TEMP[3].x, IMM[0].zzzz, IN[0].zzzz, IMM[2].xxxx 26: F2I TEMP[3].x, TEMP[3].xxxx 27: UARL ADDR[0].x, TEMP[3].xxxx 28: MOV TEMP[3], CONST[ADDR[0].x] 29: MOV TEMP[1].xy, TEMP[1].xyxx 30: MOV OUT[1], IN[0] 31: MOV OUT[2], TEMP[2] 32: MOV OUT[3], TEMP[3] 33: MOV OUT[0], TEMP[0] 34: MOV OUT[4], TEMP[1] 35: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %15 = load <16 x i8>, <16 x i8> addrspace(2)* %14, align 16, !tbaa !0 %16 = add i32 %5, %8 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %15, i32 0, i32 %16) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0 %24 = add i32 %5, %8 %25 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %24) %26 = extractelement <4 x float> %25, i32 0 %27 = extractelement <4 x float> %25, i32 1 %28 = extractelement <4 x float> %25, i32 2 %29 = extractelement <4 x float> %25, i32 3 %30 = fmul float %20, 0x4097E83D60000000 %31 = fadd float %30, 0x4000CCCCC0000000 %32 = fptosi float %31 to i32 %33 = shl i32 %32, 4 %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %33) %35 = shl i32 %32, 4 %36 = or i32 %35, 4 %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %36) %38 = shl i32 %32, 4 %39 = or i32 %38, 8 %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %39) %41 = shl i32 %32, 4 %42 = or i32 %41, 12 %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %42) %44 = fmul float %26, %34 %45 = fmul float %27, %37 %46 = fadd float %44, %45 %47 = fmul float %28, %40 %48 = fadd float %46, %47 %49 = fmul float %29, %43 %50 = fadd float %48, %49 %51 = fmul float %20, 0x4097E83D60000000 %52 = fadd float %51, 0x4008CCCCC0000000 %53 = fptosi float %52 to i32 %54 = shl i32 %53, 4 %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %54) %56 = shl i32 %53, 4 %57 = or i32 %56, 4 %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %57) %59 = shl i32 %53, 4 %60 = or i32 %59, 8 %61 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %60) %62 = shl i32 %53, 4 %63 = or i32 %62, 12 %64 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %63) %65 = fmul float %26, %55 %66 = fmul float %27, %58 %67 = fadd float %65, %66 %68 = fmul float %28, %61 %69 = fadd float %67, %68 %70 = fmul float %29, %64 %71 = fadd float %69, %70 %72 = fmul float %20, 0x4097E83D60000000 %73 = fadd float %72, 0x4010666660000000 %74 = fptosi float %73 to i32 %75 = shl i32 %74, 4 %76 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %75) %77 = shl i32 %74, 4 %78 = or i32 %77, 4 %79 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %78) %80 = shl i32 %74, 4 %81 = or i32 %80, 8 %82 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %81) %83 = shl i32 %74, 4 %84 = or i32 %83, 12 %85 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %84) %86 = fmul float %26, %76 %87 = fmul float %27, %79 %88 = fadd float %86, %87 %89 = fmul float %28, %82 %90 = fadd float %88, %89 %91 = fmul float %29, %85 %92 = fadd float %90, %91 %93 = fmul float %20, 0x4097E83D60000000 %94 = fadd float %93, 0x4014666660000000 %95 = fptosi float %94 to i32 %96 = shl i32 %95, 4 %97 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %96) %98 = shl i32 %95, 4 %99 = or i32 %98, 4 %100 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %99) %101 = shl i32 %95, 4 %102 = or i32 %101, 8 %103 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %102) %104 = shl i32 %95, 4 %105 = or i32 %104, 12 %106 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %105) %107 = fmul float %26, %97 %108 = fmul float %27, %100 %109 = fadd float %107, %108 %110 = fmul float %28, %103 %111 = fadd float %109, %110 %112 = fmul float %29, %106 %113 = fadd float %111, %112 %114 = fmul float %20, 0x4097E83D60000000 %115 = fadd float %114, 0x3FB99999A0000000 %116 = fptosi float %115 to i32 %117 = shl i32 %116, 4 %118 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %117) %119 = shl i32 %116, 4 %120 = or i32 %119, 4 %121 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %120) %122 = shl i32 %116, 4 %123 = or i32 %122, 8 %124 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %123) %125 = shl i32 %116, 4 %126 = or i32 %125, 12 %127 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %126) %128 = fmul float %20, 0x4097E83D60000000 %129 = fadd float %128, 0x3FF19999A0000000 %130 = fptosi float %129 to i32 %131 = shl i32 %130, 4 %132 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %131) %133 = shl i32 %130, 4 %134 = or i32 %133, 4 %135 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %134) %136 = shl i32 %130, 4 %137 = or i32 %136, 8 %138 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %137) %139 = shl i32 %130, 4 %140 = or i32 %139, 12 %141 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %140) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %118, float %121, float %124, float %127) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %132, float %135, float %138, float %141) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %92, float %113, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %50, float %71, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_mov_b32_e32 v1, 0x44bf41eb ; 7E0202FF 44BF41EB v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[12:15], 0 idxen ; E00C2000 80030600 s_waitcnt vmcnt(1) ; BF8C0771 v_madak_f32_e32 v0, v4, v1, 0x40833333 ; 30000304 40833333 v_madak_f32_e32 v10, v4, v1, 0x40a33333 ; 30140304 40A33333 v_madak_f32_e32 v11, v4, v1, 0x40066666 ; 30160304 40066666 v_madak_f32_e32 v12, v4, v1, 0x40466666 ; 30180304 40466666 v_cvt_i32_f32_e32 v0, v0 ; 7E001100 v_cvt_i32_f32_e32 v10, v10 ; 7E14110A v_madak_f32_e32 v13, v4, v1, 0x3dcccccd ; 301A0304 3DCCCCCD v_madak_f32_e32 v1, v4, v1, 0x3f8ccccd ; 30020304 3F8CCCCD v_cvt_i32_f32_e32 v11, v11 ; 7E16110B v_cvt_i32_f32_e32 v12, v12 ; 7E18110C v_cvt_i32_f32_e32 v13, v13 ; 7E1A110D v_cvt_i32_f32_e32 v1, v1 ; 7E021101 v_lshlrev_b32_e32 v11, 4, v11 ; 24161684 v_lshlrev_b32_e32 v12, 4, v12 ; 24181884 v_lshlrev_b32_e32 v0, 4, v0 ; 24000084 v_lshlrev_b32_e32 v10, 4, v10 ; 24141484 v_lshlrev_b32_e32 v13, 4, v13 ; 241A1A84 v_lshlrev_b32_e32 v1, 4, v1 ; 24020284 buffer_load_dword v14, v11, s[0:3], 0 offen ; E0501000 80000E0B v_or_b32_e32 v15, 4, v11 ; 281E1684 v_or_b32_e32 v16, 8, v11 ; 28201688 v_or_b32_e32 v11, 12, v11 ; 2816168C buffer_load_dword v17, v12, s[0:3], 0 offen ; E0501000 8000110C v_or_b32_e32 v18, 4, v12 ; 28241884 v_or_b32_e32 v19, 8, v12 ; 28261888 v_or_b32_e32 v12, 12, v12 ; 2818188C buffer_load_dword v20, v13, s[0:3], 0 offen ; E0501000 8000140D v_or_b32_e32 v21, 4, v13 ; 282A1A84 v_or_b32_e32 v22, 8, v13 ; 282C1A88 v_or_b32_e32 v13, 12, v13 ; 281A1A8C buffer_load_dword v23, v1, s[0:3], 0 offen ; E0501000 80001701 v_or_b32_e32 v24, 4, v1 ; 28300284 v_or_b32_e32 v25, 8, v1 ; 28320288 v_or_b32_e32 v1, 12, v1 ; 2802028C buffer_load_dword v15, v15, s[0:3], 0 offen ; E0501000 80000F0F s_nop 0 ; BF800000 buffer_load_dword v21, v21, s[0:3], 0 offen ; E0501000 80001515 s_nop 0 ; BF800000 buffer_load_dword v22, v22, s[0:3], 0 offen ; E0501000 80001616 s_nop 0 ; BF800000 buffer_load_dword v13, v13, s[0:3], 0 offen ; E0501000 80000D0D s_nop 0 ; BF800000 buffer_load_dword v24, v24, s[0:3], 0 offen ; E0501000 80001818 s_nop 0 ; BF800000 buffer_load_dword v25, v25, s[0:3], 0 offen ; E0501000 80001919 s_nop 0 ; BF800000 buffer_load_dword v1, v1, s[0:3], 0 offen ; E0501000 80000101 s_nop 0 ; BF800000 buffer_load_dword v26, v0, s[0:3], 0 offen ; E0501000 80001A00 v_or_b32_e32 v27, 4, v0 ; 28360084 v_or_b32_e32 v28, 8, v0 ; 28380088 v_or_b32_e32 v0, 12, v0 ; 2800008C buffer_load_dword v18, v18, s[0:3], 0 offen ; E0501000 80001212 s_nop 0 ; BF800000 buffer_load_dword v16, v16, s[0:3], 0 offen ; E0501000 80001010 s_nop 0 ; BF800000 buffer_load_dword v27, v27, s[0:3], 0 offen ; E0501000 80001B1B v_or_b32_e32 v29, 4, v10 ; 283A1484 buffer_load_dword v29, v29, s[0:3], 0 offen ; E0501000 80001D1D s_nop 0 ; BF800000 buffer_load_dword v30, v10, s[0:3], 0 offen ; E0501000 80001E0A v_or_b32_e32 v31, 8, v10 ; 283E1488 v_or_b32_e32 v10, 12, v10 ; 2814148C buffer_load_dword v19, v19, s[0:3], 0 offen ; E0501000 80001313 s_nop 0 ; BF800000 buffer_load_dword v28, v28, s[0:3], 0 offen ; E0501000 80001C1C s_nop 0 ; BF800000 buffer_load_dword v31, v31, s[0:3], 0 offen ; E0501000 80001F1F s_nop 0 ; BF800000 buffer_load_dword v11, v11, s[0:3], 0 offen ; E0501000 80000B0B s_nop 0 ; BF800000 buffer_load_dword v12, v12, s[0:3], 0 offen ; E0501000 80000C0C s_nop 0 ; BF800000 buffer_load_dword v0, v0, s[0:3], 0 offen ; E0501000 80000000 s_nop 0 ; BF800000 buffer_load_dword v10, v10, s[0:3], 0 offen ; E0501000 80000A0A exp 15, 32, 0, 0, 0, v2, v3, v4, v5 ; C400020F 05040302 s_waitcnt ; BF8C077F exp 15, 33, 0, 0, 0, v20, v21, v22, v13 ; C400021F 0D161514 s_waitcnt vmcnt(13) ; BF8C077D exp 15, 34, 0, 0, 0, v23, v24, v25, v1 ; C400022F 01191817 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v1, v15, v7 ; 0A020F0F v_mac_f32_e32 v1, v14, v6 ; 2C020D0E s_waitcnt vmcnt(11) ; BF8C077B v_mul_f32_e32 v2, v18, v7 ; 0A040F12 v_mac_f32_e32 v2, v17, v6 ; 2C040D11 s_waitcnt vmcnt(9) ; BF8C0779 v_mul_f32_e32 v3, v27, v7 ; 0A060F1B v_mac_f32_e32 v3, v26, v6 ; 2C060D1A s_waitcnt vmcnt(8) ; BF8C0778 v_mul_f32_e32 v4, v29, v7 ; 0A080F1D s_waitcnt vmcnt(7) ; BF8C0777 v_mac_f32_e32 v4, v30, v6 ; 2C080D1E v_mac_f32_e32 v1, v16, v8 ; 2C021110 v_mov_b32_e32 v5, 1.0 ; 7E0A02F2 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v2, v19, v8 ; 2C041113 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v3, v28, v8 ; 2C06111C s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v4, v31, v8 ; 2C08111F s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v1, v11, v9 ; 2C02130B s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v2, v12, v9 ; 2C04130C s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v3, v0, v9 ; 2C061300 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v4, v10, v9 ; 2C08130A exp 15, 35, 0, 0, 0, v3, v4, v0, v0 ; C400023F 00000403 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v0, 0 ; 7E000280 exp 15, 12, 0, 1, 0, v1, v2, v0, v5 ; C40008CF 05000201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 32 Code Size: 672 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0..1], LOCAL 0: MOV TEMP[0].xy, IN[3].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MAD TEMP[0], TEMP[0], IN[2], IN[1] 3: MUL TEMP[1].x, TEMP[0].wwww, IN[0].wwww 4: MOV TEMP[0].w, TEMP[1].xxxx 5: MOV OUT[0], TEMP[0] 6: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %30 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %32 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %33 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %34 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %38 = bitcast float %36 to i32 %39 = bitcast float %37 to i32 %40 = insertelement <2 x i32> undef, i32 %38, i32 0 %41 = insertelement <2 x i32> %40, i32 %39, i32 1 %42 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %41, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %43 = extractelement <4 x float> %42, i32 0 %44 = extractelement <4 x float> %42, i32 1 %45 = extractelement <4 x float> %42, i32 2 %46 = extractelement <4 x float> %42, i32 3 %47 = fmul float %43, %32 %48 = fadd float %47, %28 %49 = fmul float %44, %33 %50 = fadd float %49, %29 %51 = fmul float %45, %34 %52 = fadd float %51, %30 %53 = fmul float %46, %35 %54 = fadd float %53, %31 %55 = fmul float %54, %27 %56 = call i32 @llvm.SI.packf16(float %48, float %50) %57 = bitcast i32 %56 to float %58 = call i32 @llvm.SI.packf16(float %52, float %55) %59 = bitcast i32 %58 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %57, float %59, float %57, float %59) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 3, 0, [m0] ; D4080300 v_interp_p2_f32 v2, [v2], v1, 3, 0, [m0] ; D4090301 v_interp_p1_f32 v3, v0, 0, 1, [m0] ; D40C0400 v_interp_p2_f32 v3, [v3], v1, 0, 1, [m0] ; D40D0401 v_interp_p1_f32 v4, v0, 1, 1, [m0] ; D4100500 v_interp_p2_f32 v4, [v4], v1, 1, 1, [m0] ; D4110501 v_interp_p1_f32 v5, v0, 2, 1, [m0] ; D4140600 v_interp_p2_f32 v5, [v5], v1, 2, 1, [m0] ; D4150601 v_interp_p1_f32 v6, v0, 3, 1, [m0] ; D4180700 v_interp_p2_f32 v6, [v6], v1, 3, 1, [m0] ; D4190701 v_interp_p1_f32 v7, v0, 0, 2, [m0] ; D41C0800 v_interp_p2_f32 v7, [v7], v1, 0, 2, [m0] ; D41D0801 v_interp_p1_f32 v8, v0, 1, 2, [m0] ; D4200900 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v8, [v8], v1, 1, 2, [m0] ; D4210901 v_interp_p1_f32 v9, v0, 2, 2, [m0] ; D4240A00 v_interp_p2_f32 v9, [v9], v1, 2, 2, [m0] ; D4250A01 v_interp_p1_f32 v10, v0, 3, 2, [m0] ; D4280B00 v_interp_p2_f32 v10, [v10], v1, 3, 2, [m0] ; D4290B01 v_interp_p1_f32 v11, v0, 0, 3, [m0] ; D42C0C00 v_interp_p2_f32 v11, [v11], v1, 0, 3, [m0] ; D42D0C01 v_interp_p1_f32 v12, v0, 1, 3, [m0] ; D4300D00 v_interp_p2_f32 v12, [v12], v1, 1, 3, [m0] ; D4310D01 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[8:15], s[0:3] ; F0800F00 00020B0B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v3, v7, v11 ; 2C061707 v_mac_f32_e32 v4, v8, v12 ; 2C081908 v_mac_f32_e32 v5, v9, v13 ; 2C0A1B09 v_mac_f32_e32 v6, v10, v14 ; 2C0C1D0A v_mul_f32_e32 v0, v2, v6 ; 0A000D02 v_cvt_pkrtz_f16_f32_e64 v1, v3, v4 ; D2960001 00020903 v_cvt_pkrtz_f16_f32_e64 v0, v5, v0 ; D2960000 00020105 exp 15, 0, 1, 1, 1, v1, v0, v1, v0 ; C4001C0F 00010001 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 16 Code Size: 176 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG 0: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } Shader Disassembly: v_mov_b32_e32 v0, 0 ; 7E000280 exp 0, 0, 0, 1, 1, v0, v0, v0, v0 ; C4001800 00000000 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 16 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** Installing breakpad exception handler for appid(csgo_linux)/version(1.0) Looking up breakpad interfaces from steamclient Calling BreakpadMiniDumpSystemInit Steam_SetMinidumpSteamID: Caching Steam ID: 76561198005671812 [API loaded yes] Steam_SetMinidumpSteamID: Setting Steam ID: 76561198005671812 SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 FillInMachineIDInfo took a total of 0 milliseconds VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[1] DCL OUT[3], GENERIC[2] DCL CONST[0..5] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].yyxy 1: DP4 TEMP[0].x, IN[0], CONST[2] 2: DP4 TEMP[1].x, IN[0], CONST[3] 3: MOV TEMP[0].y, TEMP[1].xxxx 4: DP4 TEMP[1].x, IN[0], CONST[4] 5: DP4 TEMP[2].x, IN[0], CONST[5] 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyxx 8: MOV OUT[1], CONST[0] 9: MOV OUT[2], CONST[1] 10: MOV OUT[0], TEMP[0] 11: MOV OUT[3], TEMP[1] 12: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 16) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 20) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 24) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 28) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 44) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 48) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 52) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 56) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 60) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %38 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %39 = load <16 x i8>, <16 x i8> addrspace(2)* %38, align 16, !tbaa !0 %40 = add i32 %5, %8 %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %39, i32 0, i32 %40) %42 = extractelement <4 x float> %41, i32 0 %43 = extractelement <4 x float> %41, i32 1 %44 = extractelement <4 x float> %41, i32 2 %45 = extractelement <4 x float> %41, i32 3 %46 = fmul float %42, %22 %47 = fmul float %43, %23 %48 = fadd float %46, %47 %49 = fmul float %44, %24 %50 = fadd float %48, %49 %51 = fmul float %45, %25 %52 = fadd float %50, %51 %53 = fmul float %42, %26 %54 = fmul float %43, %27 %55 = fadd float %53, %54 %56 = fmul float %44, %28 %57 = fadd float %55, %56 %58 = fmul float %45, %29 %59 = fadd float %57, %58 %60 = fmul float %42, %30 %61 = fmul float %43, %31 %62 = fadd float %60, %61 %63 = fmul float %44, %32 %64 = fadd float %62, %63 %65 = fmul float %45, %33 %66 = fadd float %64, %65 %67 = fmul float %42, %34 %68 = fmul float %43, %35 %69 = fadd float %67, %68 %70 = fmul float %44, %36 %71 = fadd float %69, %70 %72 = fmul float %45, %37 %73 = fadd float %71, %72 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %14, float %15, float %16, float %17) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %18, float %19, float %20, float %21) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %66, float %73, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %52, float %59, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 idxen ; E00C2000 80010000 s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s4, s[0:3], 0x0 ; C0220100 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x4 ; C0220140 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x8 ; C0220180 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0xc ; C02201C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x10 ; C0220200 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x14 ; C0220240 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x18 ; C0220280 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x1c ; C02202C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x20 ; C0220300 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x24 ; C0220340 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x28 ; C0220380 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x2c ; C02203C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x30 ; C0220400 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x34 ; C0220440 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[0:3], 0x38 ; C0220480 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[0:3], 0x3c ; C02204C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[0:3], 0x40 ; C0220500 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[0:3], 0x44 ; C0220540 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[0:3], 0x50 ; C0220580 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[0:3], 0x54 ; C02205C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[0:3], 0x48 ; C0220600 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[0:3], 0x4c ; C0220640 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[0:3], 0x58 ; C0220680 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x5c ; C0220000 0000005C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v4, s4 ; 7E080204 v_mov_b32_e32 v5, s5 ; 7E0A0205 v_mov_b32_e32 v6, s6 ; 7E0C0206 v_mov_b32_e32 v7, s7 ; 7E0E0207 exp 15, 32, 0, 0, 0, v4, v5, v6, v7 ; C400020F 07060504 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v4, s8 ; 7E080208 v_mov_b32_e32 v5, s9 ; 7E0A0209 v_mov_b32_e32 v6, s10 ; 7E0C020A v_mov_b32_e32 v7, s11 ; 7E0E020B exp 15, 33, 0, 0, 0, v4, v5, v6, v7 ; C400021F 07060504 s_waitcnt vmcnt(0) expcnt(0) ; BF8C0700 v_mul_f32_e32 v4, s13, v1 ; 0A08020D v_mul_f32_e32 v5, s17, v1 ; 0A0A0211 v_mul_f32_e32 v6, s21, v1 ; 0A0C0215 v_mul_f32_e32 v1, s23, v1 ; 0A020217 v_mac_f32_e32 v4, s12, v0 ; 2C08000C v_mac_f32_e32 v5, s16, v0 ; 2C0A0010 v_mac_f32_e32 v6, s20, v0 ; 2C0C0014 v_mac_f32_e32 v1, s22, v0 ; 2C020016 v_mac_f32_e32 v4, s14, v2 ; 2C08040E v_mac_f32_e32 v5, s18, v2 ; 2C0A0412 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s26, v2 ; 2C02041A v_mac_f32_e32 v4, s15, v3 ; 2C08060F v_mac_f32_e32 v5, s19, v3 ; 2C0A0613 v_mac_f32_e32 v6, s25, v3 ; 2C0C0619 v_mac_f32_e32 v1, s0, v3 ; 2C020600 v_mov_b32_e32 v0, 1.0 ; 7E0002F2 exp 15, 34, 0, 0, 0, v6, v1, v0, v0 ; C400022F 00000106 s_waitcnt expcnt(0) ; BF8C070F v_mov_b32_e32 v1, 0 ; 7E020280 exp 15, 12, 0, 1, 0, v4, v5, v1, v0 ; C40008CF 00010504 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 8 Code Size: 476 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0] DCL CONST[2] DCL TEMP[0..9], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyxx 1: MOV TEMP[1], IMM[0].xxxx 2: MOV TEMP[2], IMM[0].xxxx 3: MOV TEMP[3].y, IMM[0].xxxx 4: MOV TEMP[3].x, -CONST[0].xxxx 5: BGNLOOP :0 6: FSLT TEMP[4].x, CONST[0].xxxx, TEMP[3].xxxx 7: UIF TEMP[4].xxxx :0 8: BRK 9: ENDIF 10: MOV TEMP[3].y, -CONST[0].yyyy 11: BGNLOOP :0 12: FSLT TEMP[5].x, CONST[0].yyyy, TEMP[3].yyyy 13: UIF TEMP[5].xxxx :0 14: BRK 15: ENDIF 16: MAD TEMP[6].xy, TEMP[3].xyyy, CONST[2].xyyy, TEMP[0].xyyy 17: MOV TEMP[7].xy, TEMP[6].xyyy 18: MOV TEMP[7].w, IMM[0].xxxx 19: TXB TEMP[8], TEMP[7], SAMP[0], 2D 20: ADD TEMP[2], TEMP[2], TEMP[8] 21: ADD TEMP[9].x, TEMP[3].yyyy, IMM[0].yyyy 22: MOV TEMP[3].y, TEMP[9].xxxx 23: ENDLOOP :0 24: ADD TEMP[3].x, TEMP[3].xxxx, IMM[0].yyyy 25: ENDLOOP :0 26: MUL TEMP[1], TEMP[2], CONST[0].wwww 27: MOV TEMP[0].w, IMM[0].yyyy 28: MOV TEMP[0].xyz, IN[1].xyzx 29: MUL TEMP[0], TEMP[1], TEMP[0] 30: MUL TEMP[1], TEMP[0], IN[1].wwww 31: MAD TEMP[1], IN[0], TEMP[1].wwww, TEMP[1] 32: MOV OUT[0], TEMP[1] 33: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 12) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 36) %30 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %31 = load <8 x i32>, <8 x i32> addrspace(2)* %30, align 32, !tbaa !0 %32 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %33 = load <4 x i32>, <4 x i32> addrspace(2)* %32, align 16, !tbaa !0 %34 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8) %38 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %39 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %40 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %41 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %42 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %43 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %44 = fsub float -0.000000e+00, %25 %45 = fsub float -0.000000e+00, %26 br label %LOOP LOOP: ; preds = %IF43, %main_body %temp9.0 = phi float [ 0.000000e+00, %main_body ], [ %temp9.1, %IF43 ] %temp10.0 = phi float [ 0.000000e+00, %main_body ], [ %temp10.1, %IF43 ] %temp11.0 = phi float [ 0.000000e+00, %main_body ], [ %temp11.1, %IF43 ] %temp12.0 = phi float [ %44, %main_body ], [ %75, %IF43 ] %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %temp8.1, %IF43 ] %46 = fcmp olt float %25, %temp12.0 br i1 %46, label %IF, label %ENDIF IF: ; preds = %LOOP %47 = fmul float %temp8.0, %27 %48 = fmul float %temp9.0, %27 %49 = fmul float %temp10.0, %27 %50 = fmul float %temp11.0, %27 %51 = fmul float %47, %38 %52 = fmul float %48, %39 %53 = fmul float %49, %40 %54 = fmul float %51, %41 %55 = fmul float %52, %41 %56 = fmul float %53, %41 %57 = fmul float %50, %41 %58 = fmul float %34, %57 %59 = fadd float %58, %54 %60 = fmul float %35, %57 %61 = fadd float %60, %55 %62 = fmul float %36, %57 %63 = fadd float %62, %56 %64 = fmul float %37, %57 %65 = fadd float %64, %57 %66 = call i32 @llvm.SI.packf16(float %59, float %61) %67 = bitcast i32 %66 to float %68 = call i32 @llvm.SI.packf16(float %63, float %65) %69 = bitcast i32 %68 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %67, float %69, float %67, float %69) ret void ENDIF: ; preds = %LOOP %70 = fmul float %temp12.0, %28 %71 = fadd float %70, %42 %72 = bitcast float %71 to i32 %73 = insertelement <4 x i32> , i32 %72, i32 1 br label %LOOP41 LOOP41: ; preds = %ENDIF42, %ENDIF %temp9.1 = phi float [ %temp9.0, %ENDIF ], [ %86, %ENDIF42 ] %temp10.1 = phi float [ %temp10.0, %ENDIF ], [ %87, %ENDIF42 ] %temp11.1 = phi float [ %temp11.0, %ENDIF ], [ %88, %ENDIF42 ] %temp13.0 = phi float [ %45, %ENDIF ], [ %89, %ENDIF42 ] %temp8.1 = phi float [ %temp8.0, %ENDIF ], [ %85, %ENDIF42 ] %74 = fcmp olt float %26, %temp13.0 br i1 %74, label %IF43, label %ENDIF42 IF43: ; preds = %LOOP41 %75 = fadd float %temp12.0, 1.000000e+00 br label %LOOP ENDIF42: ; preds = %LOOP41 %76 = fmul float %temp13.0, %29 %77 = fadd float %76, %43 %78 = bitcast float %77 to i32 %79 = insertelement <4 x i32> %73, i32 %78, i32 2 %80 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %79, <8 x i32> %31, <4 x i32> %33, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = extractelement <4 x float> %80, i32 2 %84 = extractelement <4 x float> %80, i32 3 %85 = fadd float %temp8.1, %81 %86 = fadd float %temp9.1, %82 %87 = fadd float %temp10.1, %83 %88 = fadd float %temp11.1, %84 %89 = fadd float %temp13.0, 1.000000e+00 br label %LOOP41 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[16:19], s[2:3], 0x0 ; C00A0401 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[16:19], 0x0 ; C0220048 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[16:19], 0x4 ; C0220088 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[16:19], 0xc ; C0220008 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s3, s[16:19], 0x20 ; C02200C8 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[16:19], 0x24 ; C0220188 00000024 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v5, v0, 3, 0, [m0] ; D4140300 v_interp_p2_f32 v5, [v5], v1, 3, 0, [m0] ; D4150301 v_interp_p1_f32 v6, v0, 0, 1, [m0] ; D4180400 v_interp_p2_f32 v6, [v6], v1, 0, 1, [m0] ; D4190401 v_interp_p1_f32 v7, v0, 1, 1, [m0] ; D41C0500 v_interp_p2_f32 v7, [v7], v1, 1, 1, [m0] ; D41D0501 v_interp_p1_f32 v8, v0, 2, 1, [m0] ; D4200600 v_interp_p2_f32 v8, [v8], v1, 2, 1, [m0] ; D4210601 v_interp_p1_f32 v9, v0, 3, 1, [m0] ; D4240700 v_interp_p2_f32 v9, [v9], v1, 3, 1, [m0] ; D4250701 v_interp_p1_f32 v10, v0, 0, 2, [m0] ; D4280800 s_load_dwordx4 s[16:19], s[4:5], 0x0 ; C00A0402 00000000 v_interp_p2_f32 v10, [v10], v1, 0, 2, [m0] ; D4290801 v_interp_p1_f32 v0, v0, 1, 2, [m0] ; D4000900 v_interp_p2_f32 v0, [v0], v1, 1, 2, [m0] ; D4010901 v_mov_b32_e32 v11, 0x80000000 ; 7E1602FF 80000000 s_waitcnt lgkmcnt(0) ; BF8C007F v_xor_b32_e32 v1, s1, v11 ; 2A021601 v_xor_b32_e32 v12, s2, v11 ; 2A181602 v_mov_b32_e32 v16, 0 ; 7E200280 s_mov_b64 s[4:5], 0 ; BE840180 v_mov_b32_e32 v17, 0 ; 7E220280 v_mov_b32_e32 v18, 0 ; 7E240280 v_mov_b32_e32 v19, 0 ; 7E260280 v_mov_b32_e32 v13, v19 ; 7E1A0313 v_mov_b32_e32 v11, v18 ; 7E160312 v_mov_b32_e32 v14, v17 ; 7E1C0311 v_mov_b32_e32 v15, v16 ; 7E1E0310 v_cmp_nlt_f32_e32 vcc, s1, v1 ; 7C9C0201 s_and_saveexec_b64 s[20:21], vcc ; BE94206A s_xor_b64 s[20:21], exec, s[20:21] ; 8894147E s_cbranch_execz BB0_4 ; BF880000 v_mad_f32 v21, s3, v1, v10 ; D1C10015 042A0203 v_mov_b32_e32 v20, 0 ; 7E280280 s_mov_b64 s[22:23], 0 ; BE960180 v_mov_b32_e32 v22, v15 ; 7E2C030F v_mov_b32_e32 v24, v14 ; 7E30030E v_mov_b32_e32 v26, v11 ; 7E34030B v_mov_b32_e32 v23, v12 ; 7E2E030C v_mov_b32_e32 v25, v13 ; 7E32030D v_mov_b32_e32 v19, v25 ; 7E260319 v_mov_b32_e32 v18, v26 ; 7E24031A v_mov_b32_e32 v17, v24 ; 7E220318 v_mov_b32_e32 v16, v22 ; 7E200316 v_cmp_nlt_f32_e32 vcc, s2, v23 ; 7C9C2E02 s_and_saveexec_b64 s[24:25], vcc ; BE98206A s_xor_b64 s[24:25], exec, s[24:25] ; 8898187E v_mad_f32 v22, s6, v23, v0 ; D1C10016 04022E06 image_sample_b v[26:29], 15, 0, 0, 0, 0, 0, 0, 0, v[20:23], s[8:15], s[16:19] ; F0940F00 00821A14 s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v25, v26, v19 ; 0232271A v_add_f32_e32 v22, v27, v16 ; 022C211B v_add_f32_e32 v24, v28, v17 ; 0230231C v_add_f32_e32 v26, v29, v18 ; 0234251D v_add_f32_e32 v23, 1.0, v23 ; 022E2EF2 s_or_b64 exec, exec, s[24:25] ; 87FE187E s_or_b64 s[22:23], s[24:25], s[22:23] ; 87961618 s_andn2_b64 exec, exec, s[22:23] ; 89FE167E s_cbranch_execnz BB0_5 ; BF890000 s_or_b64 exec, exec, s[22:23] ; 87FE167E v_add_f32_e32 v1, 1.0, v1 ; 020202F2 s_or_b64 exec, exec, s[20:21] ; 87FE147E s_or_b64 s[4:5], s[20:21], s[4:5] ; 87840414 s_andn2_b64 exec, exec, s[4:5] ; 89FE047E s_cbranch_execnz BB0_1 ; BF890000 s_or_b64 exec, exec, s[4:5] ; 87FE047E v_mul_f32_e32 v0, s0, v13 ; 0A001A00 v_mul_f32_e32 v1, s0, v15 ; 0A021E00 v_mul_f32_e32 v10, s0, v14 ; 0A141C00 v_mul_f32_e32 v11, s0, v11 ; 0A161600 v_mul_f32_e32 v0, v6, v0 ; 0A000106 v_mul_f32_e32 v1, v7, v1 ; 0A020307 v_mul_f32_e32 v6, v8, v10 ; 0A0C1508 v_mul_f32_e32 v0, v9, v0 ; 0A000109 v_mul_f32_e32 v1, v9, v1 ; 0A020309 v_mul_f32_e32 v6, v9, v6 ; 0A0C0D09 v_mul_f32_e32 v7, v9, v11 ; 0A0E1709 v_mac_f32_e32 v0, v7, v2 ; 2C000507 v_mac_f32_e32 v1, v7, v3 ; 2C020707 v_mac_f32_e32 v6, v7, v4 ; 2C0C0907 v_mac_f32_e32 v7, v7, v5 ; 2C0E0B07 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v6, v7 ; D2960001 00020F06 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 32 VGPRS: 32 Code Size: 480 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = bitcast float %27 to i32 %30 = bitcast float %28 to i32 %31 = insertelement <2 x i32> undef, i32 %29, i32 0 %32 = insertelement <2 x i32> %31, i32 %30, i32 1 %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %34, float %35, float %36, float %37) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800F00 00030002 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 0, 0, 1, 1, v0, v1, v2, v3 ; C400180F 03020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 4 Code Size: 72 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x0 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], CUBE, UINT 0: TEX OUT[0], IN[0], SAMP[0], CUBE 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !0 %25 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %12) %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %12) %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %12) %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %12) %31 = insertelement <4 x float> undef, float %27, i32 0 %32 = insertelement <4 x float> %31, float %28, i32 1 %33 = insertelement <4 x float> %32, float %29, i32 2 %34 = insertelement <4 x float> %33, float %30, i32 3 %35 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %34) %36 = extractelement <4 x float> %35, i32 0 %37 = extractelement <4 x float> %35, i32 1 %38 = extractelement <4 x float> %35, i32 2 %39 = extractelement <4 x float> %35, i32 3 %40 = call float @llvm.fabs.f32(float %38) %41 = fdiv float 1.000000e+00, %40 %42 = fmul float %36, %41 %43 = fadd float %42, 1.500000e+00 %44 = fmul float %37, %41 %45 = fadd float %44, 1.500000e+00 %46 = bitcast float %45 to i32 %47 = bitcast float %43 to i32 %48 = bitcast float %39 to i32 %49 = insertelement <4 x i32> undef, i32 %46, i32 0 %50 = insertelement <4 x i32> %49, i32 %47, i32 1 %51 = insertelement <4 x i32> %50, i32 %48, i32 2 %52 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %51, <8 x i32> %24, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = extractelement <4 x float> %52, i32 2 %56 = extractelement <4 x float> %52, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %53, float %54, float %55, float %56) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 2, 0, [m0] ; D4100200 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v4, [v4], v1, 2, 0, [m0] ; D4110201 v_interp_p1_f32 v0, v0, 3, 0, [m0] ; D4000300 v_interp_p2_f32 v0, [v0], v1, 3, 0, [m0] ; D4010301 v_cubeid_f32 v7, v2, v3, v4 ; D1C40007 04120702 v_cubema_f32 v0, v2, v3, v4 ; D1C70000 04120702 v_rcp_f32_e64 v0, |v0| ; D1620100 00000100 v_cubesc_f32 v1, v2, v3, v4 ; D1C50001 04120702 v_cubetc_f32 v2, v2, v3, v4 ; D1C60002 04120702 v_mov_b32_e32 v5, 0x3fc00000 ; 7E0A02FF 3FC00000 v_mad_f32 v6, v0, v2, v5 ; D1C10006 04160500 v_mac_f32_e32 v5, v0, v1 ; 2C0A0300 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[5:8], s[8:15], s[0:3] ; F0800F00 00020005 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 0, 0, 1, 1, v0, v1, v2, v3 ; C400180F 03020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 144 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** [1120/170159:ERROR:renderer_main.cc(200)] Running without renderer sandbox SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] DCL OUT[5], GENERIC[3] DCL OUT[6], GENERIC[4] DCL CONST[0..51] DCL TEMP[0..9], LOCAL 0: DP4 TEMP[0].x, IN[0], CONST[4] 1: DP4 TEMP[1].x, IN[0], CONST[5] 2: MOV TEMP[0].y, TEMP[1].xxxx 3: DP4 TEMP[2].x, IN[0], CONST[6] 4: MOV TEMP[0].z, TEMP[2].xxxx 5: MAD TEMP[3].xyz, IN[1].xyxx, CONST[0].yyxx, CONST[0].xxyy 6: DP4 TEMP[4].x, IN[0], CONST[7] 7: MOV TEMP[0].w, TEMP[4].xxxx 8: DP3 TEMP[5].x, TEMP[3].xyzz, CONST[49].xyww 9: DP3 TEMP[6].x, TEMP[3].xyzz, CONST[50].xyww 10: ADD TEMP[7].x, TEMP[5].xxxx, -CONST[48].xxxx 11: MOV TEMP[3].y, TEMP[7].xxxx 12: ADD TEMP[3].x, TEMP[5].xxxx, CONST[48].xxxx 13: ADD TEMP[5].x, TEMP[6].xxxx, -CONST[48].yyyy 14: MOV TEMP[3].z, TEMP[5].xxxx 15: ADD TEMP[5].x, TEMP[6].xxxx, CONST[48].yyyy 16: MOV TEMP[3].w, TEMP[5].xxxx 17: MUL TEMP[5].xy, TEMP[3].yzzz, CONST[48].zwww 18: MOV TEMP[6].xy, TEMP[3].yzyy 19: MOV TEMP[7].xy, TEMP[3].ywyy 20: MOV TEMP[8].xy, TEMP[3].xwxx 21: MOV TEMP[3].xy, TEMP[3].xzxx 22: MOV TEMP[9], TEMP[0] 23: MAD TEMP[2].x, TEMP[2].xxxx, CONST[0].zzzz, -TEMP[4].xxxx 24: MOV TEMP[0].z, TEMP[2].xxxx 25: MOV TEMP[0].y, -TEMP[1].xxxx 26: MAD TEMP[0].xy, CONST[51].xyyy, TEMP[4].xxxx, TEMP[0].xyyy 27: MOV OUT[2], TEMP[6] 28: MOV OUT[3], TEMP[7] 29: MOV OUT[4], TEMP[3] 30: MOV OUT[5], TEMP[8] 31: MOV OUT[0], TEMP[0] 32: MOV OUT[6], TEMP[5] 33: MOV OUT[1], TEMP[9] 34: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 64) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 68) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 72) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 76) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 80) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 84) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 88) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 92) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 96) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 100) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 104) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 108) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 112) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 116) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 120) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 124) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %45 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %46 = load <16 x i8>, <16 x i8> addrspace(2)* %45, align 16, !tbaa !0 %47 = add i32 %5, %8 %48 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %46, i32 0, i32 %47) %49 = extractelement <4 x float> %48, i32 0 %50 = extractelement <4 x float> %48, i32 1 %51 = extractelement <4 x float> %48, i32 2 %52 = extractelement <4 x float> %48, i32 3 %53 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %54 = load <16 x i8>, <16 x i8> addrspace(2)* %53, align 16, !tbaa !0 %55 = add i32 %5, %8 %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %54, i32 0, i32 %55) %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = fmul float %49, %17 %60 = fmul float %50, %18 %61 = fadd float %59, %60 %62 = fmul float %51, %19 %63 = fadd float %61, %62 %64 = fmul float %52, %20 %65 = fadd float %63, %64 %66 = fmul float %49, %21 %67 = fmul float %50, %22 %68 = fadd float %66, %67 %69 = fmul float %51, %23 %70 = fadd float %68, %69 %71 = fmul float %52, %24 %72 = fadd float %70, %71 %73 = fmul float %49, %25 %74 = fmul float %50, %26 %75 = fadd float %73, %74 %76 = fmul float %51, %27 %77 = fadd float %75, %76 %78 = fmul float %52, %28 %79 = fadd float %77, %78 %80 = fmul float %57, %15 %81 = fadd float %80, %14 %82 = fmul float %58, %15 %83 = fadd float %82, %14 %84 = fmul float %57, %14 %85 = fadd float %84, %15 %86 = fmul float %49, %29 %87 = fmul float %50, %30 %88 = fadd float %86, %87 %89 = fmul float %51, %31 %90 = fadd float %88, %89 %91 = fmul float %52, %32 %92 = fadd float %90, %91 %93 = fmul float %81, %37 %94 = fmul float %83, %38 %95 = fadd float %94, %93 %96 = fmul float %85, %39 %97 = fadd float %95, %96 %98 = fmul float %81, %40 %99 = fmul float %83, %41 %100 = fadd float %99, %98 %101 = fmul float %85, %42 %102 = fadd float %100, %101 %103 = fsub float %97, %33 %104 = fadd float %97, %33 %105 = fsub float %102, %34 %106 = fadd float %102, %34 %107 = fmul float %103, %35 %108 = fmul float %105, %36 %109 = fmul float %79, %16 %110 = fsub float %109, %92 %111 = fmul float %43, %92 %112 = fadd float %111, %65 %113 = fmul float %44, %92 %114 = fsub float %113, %72 %115 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %116 = load <16 x i8>, <16 x i8> addrspace(2)* %115, align 16, !tbaa !0 %117 = call float @llvm.SI.load.const(<16 x i8> %116, i32 0) %118 = fmul float %117, %65 %119 = call float @llvm.SI.load.const(<16 x i8> %116, i32 4) %120 = fmul float %119, %72 %121 = fadd float %118, %120 %122 = call float @llvm.SI.load.const(<16 x i8> %116, i32 8) %123 = fmul float %122, %79 %124 = fadd float %121, %123 %125 = call float @llvm.SI.load.const(<16 x i8> %116, i32 12) %126 = fmul float %125, %92 %127 = fadd float %124, %126 %128 = call float @llvm.SI.load.const(<16 x i8> %116, i32 16) %129 = fmul float %128, %65 %130 = call float @llvm.SI.load.const(<16 x i8> %116, i32 20) %131 = fmul float %130, %72 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %116, i32 24) %134 = fmul float %133, %79 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %116, i32 28) %137 = fmul float %136, %92 %138 = fadd float %135, %137 %139 = call float @llvm.SI.load.const(<16 x i8> %116, i32 32) %140 = fmul float %139, %65 %141 = call float @llvm.SI.load.const(<16 x i8> %116, i32 36) %142 = fmul float %141, %72 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %116, i32 40) %145 = fmul float %144, %79 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %116, i32 44) %148 = fmul float %147, %92 %149 = fadd float %146, %148 %150 = call float @llvm.SI.load.const(<16 x i8> %116, i32 48) %151 = fmul float %150, %65 %152 = call float @llvm.SI.load.const(<16 x i8> %116, i32 52) %153 = fmul float %152, %72 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %116, i32 56) %156 = fmul float %155, %79 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %116, i32 60) %159 = fmul float %158, %92 %160 = fadd float %157, %159 %161 = call float @llvm.SI.load.const(<16 x i8> %116, i32 64) %162 = fmul float %161, %65 %163 = call float @llvm.SI.load.const(<16 x i8> %116, i32 68) %164 = fmul float %163, %72 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %116, i32 72) %167 = fmul float %166, %79 %168 = fadd float %165, %167 %169 = call float @llvm.SI.load.const(<16 x i8> %116, i32 76) %170 = fmul float %169, %92 %171 = fadd float %168, %170 %172 = call float @llvm.SI.load.const(<16 x i8> %116, i32 80) %173 = fmul float %172, %65 %174 = call float @llvm.SI.load.const(<16 x i8> %116, i32 84) %175 = fmul float %174, %72 %176 = fadd float %173, %175 %177 = call float @llvm.SI.load.const(<16 x i8> %116, i32 88) %178 = fmul float %177, %79 %179 = fadd float %176, %178 %180 = call float @llvm.SI.load.const(<16 x i8> %116, i32 92) %181 = fmul float %180, %92 %182 = fadd float %179, %181 %183 = call float @llvm.SI.load.const(<16 x i8> %116, i32 96) %184 = fmul float %183, %65 %185 = call float @llvm.SI.load.const(<16 x i8> %116, i32 100) %186 = fmul float %185, %72 %187 = fadd float %184, %186 %188 = call float @llvm.SI.load.const(<16 x i8> %116, i32 104) %189 = fmul float %188, %79 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %116, i32 108) %192 = fmul float %191, %92 %193 = fadd float %190, %192 %194 = call float @llvm.SI.load.const(<16 x i8> %116, i32 112) %195 = fmul float %194, %65 %196 = call float @llvm.SI.load.const(<16 x i8> %116, i32 116) %197 = fmul float %196, %72 %198 = fadd float %195, %197 %199 = call float @llvm.SI.load.const(<16 x i8> %116, i32 120) %200 = fmul float %199, %79 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %116, i32 124) %203 = fmul float %202, %92 %204 = fadd float %201, %203 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %103, float %105, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %103, float %106, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %104, float %105, float %105, float %106) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %104, float %106, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %107, float %108, float undef, float undef) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %112, float %114, float %110, float %92) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %127, float %138, float %149, float %160) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %171, float %182, float %193, float %204) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x0 ; C0220202 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x4 ; C0220242 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x8 ; C0220282 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x40 ; C02202C2 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x44 ; C0220302 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x48 ; C0220342 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x4c ; C0220382 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x50 ; C02203C2 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x54 ; C0220402 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x58 ; C0220442 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x5c ; C0220482 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x60 ; C02204C2 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x64 ; C0220502 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x68 ; C0220542 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x6c ; C0220582 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x70 ; C02205C2 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x74 ; C0220602 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x78 ; C0220642 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x7c ; C0220682 0000007C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x300 ; C02206C2 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x304 ; C0220702 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x308 ; C0220742 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0x30c ; C0220782 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x310 ; C02207C2 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x314 ; C0220802 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x31c ; C0220842 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x320 ; C0220882 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x324 ; C02208C2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x32c ; C0220902 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x330 ; C0220942 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x334 ; C0220102 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0xc ; C0220980 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x10 ; C02209C0 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x14 ; C0220A00 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x18 ; C0220A40 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x1c ; C0220A80 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x20 ; C0220AC0 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x24 ; C0220B00 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x28 ; C0220B40 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x2c ; C0220B80 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x30 ; C0220BC0 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x34 ; C0220C00 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x38 ; C0220C40 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x3c ; C0220C80 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x40 ; C0220CC0 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x44 ; C0220D00 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x48 ; C0220D40 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x4c ; C0220D80 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x50 ; C0220DC0 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[0:3], 0x54 ; C0220E00 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[0:3], 0x58 ; C0220E40 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[0:3], 0x5c ; C0220E80 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s59, s[0:3], 0x60 ; C0220EC0 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[0:3], 0x64 ; C0220F00 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[0:3], 0x68 ; C0220F40 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[0:3], 0x6c ; C0220F80 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[0:3], 0x70 ; C0220FC0 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[0:3], 0x74 ; C0221000 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[0:3], 0x78 ; C0221040 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt vmcnt(1) lgkmcnt(0) ; BF8C0071 v_mul_f32_e32 v0, s12, v2 ; 0A00040C s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v7, s16, v2 ; 0A0E0410 v_mul_f32_e32 v8, s20, v2 ; 0A100414 v_mov_b32_e32 v9, s9 ; 7E120209 v_mac_f32_e32 v9, s8, v5 ; 2C120A08 v_mov_b32_e32 v10, s8 ; 7E140208 v_mad_f32 v5, s9, v5, v10 ; D1C10005 042A0A09 v_mad_f32 v6, s9, v6, v10 ; D1C10006 042A0C09 v_mul_f32_e32 v2, s24, v2 ; 0A040418 v_mac_f32_e32 v0, s11, v1 ; 2C00020B v_mac_f32_e32 v7, s15, v1 ; 2C0E020F v_mac_f32_e32 v8, s19, v1 ; 2C100213 v_mac_f32_e32 v2, s23, v1 ; 2C040217 v_mul_f32_e32 v1, s31, v5 ; 0A020A1F v_mul_f32_e32 v5, s34, v5 ; 0A0A0A22 v_mac_f32_e32 v0, s13, v3 ; 2C00060D v_mac_f32_e32 v7, s17, v3 ; 2C0E0611 v_mac_f32_e32 v8, s21, v3 ; 2C100615 v_mac_f32_e32 v2, s25, v3 ; 2C040619 v_mac_f32_e32 v1, s32, v6 ; 2C020C20 v_mac_f32_e32 v5, s35, v6 ; 2C0A0C23 v_mac_f32_e32 v0, s14, v4 ; 2C00080E v_mac_f32_e32 v7, s18, v4 ; 2C0E0812 v_mac_f32_e32 v8, s22, v4 ; 2C100816 v_mac_f32_e32 v2, s26, v4 ; 2C04081A v_mac_f32_e32 v1, s33, v9 ; 2C021221 v_mac_f32_e32 v5, s36, v9 ; 2C0A1224 v_subrev_f32_e32 v3, s27, v1 ; 0606021B v_add_f32_e32 v1, s27, v1 ; 0202021B v_subrev_f32_e32 v4, s28, v5 ; 06080A1C v_add_f32_e32 v5, s28, v5 ; 020A0A1C v_mad_f32 v6, v8, s10, -v2 ; D1C10006 84081508 v_mad_f32 v9, s37, v2, v0 ; D1C10009 04020425 v_mad_f32 v10, s4, v2, -v7 ; D1C1000A 841E0404 v_mul_f32_e32 v11, s6, v7 ; 0A160E06 v_mul_f32_e32 v12, s40, v7 ; 0A180E28 v_mul_f32_e32 v13, s44, v7 ; 0A1A0E2C v_mul_f32_e32 v14, s48, v7 ; 0A1C0E30 v_mul_f32_e32 v15, s52, v7 ; 0A1E0E34 v_mul_f32_e32 v16, s56, v7 ; 0A200E38 v_mul_f32_e32 v17, s60, v7 ; 0A220E3C v_mul_f32_e32 v7, s64, v7 ; 0A0E0E40 v_mul_f32_e32 v18, s29, v3 ; 0A24061D v_mul_f32_e32 v19, s30, v4 ; 0A26081E v_mac_f32_e32 v11, s5, v0 ; 2C160005 v_mac_f32_e32 v12, s39, v0 ; 2C180027 v_mac_f32_e32 v13, s43, v0 ; 2C1A002B v_mac_f32_e32 v14, s47, v0 ; 2C1C002F v_mac_f32_e32 v15, s51, v0 ; 2C1E0033 v_mac_f32_e32 v16, s55, v0 ; 2C200037 v_mac_f32_e32 v17, s59, v0 ; 2C22003B v_mac_f32_e32 v7, s63, v0 ; 2C0E003F exp 15, 32, 0, 0, 0, v3, v4, v0, v0 ; C400020F 00000403 v_mac_f32_e32 v11, s7, v8 ; 2C161007 v_mac_f32_e32 v12, s41, v8 ; 2C181029 v_mac_f32_e32 v13, s45, v8 ; 2C1A102D v_mac_f32_e32 v14, s49, v8 ; 2C1C1031 v_mac_f32_e32 v15, s53, v8 ; 2C1E1035 v_mac_f32_e32 v16, s57, v8 ; 2C201039 v_mac_f32_e32 v17, s61, v8 ; 2C22103D v_mac_f32_e32 v7, s65, v8 ; 2C0E1041 exp 15, 33, 0, 0, 0, v3, v5, v0, v0 ; C400021F 00000503 v_mac_f32_e32 v11, s38, v2 ; 2C160426 v_mac_f32_e32 v12, s42, v2 ; 2C18042A v_mac_f32_e32 v13, s46, v2 ; 2C1A042E v_mac_f32_e32 v14, s50, v2 ; 2C1C0432 v_mac_f32_e32 v15, s54, v2 ; 2C1E0436 v_mac_f32_e32 v16, s58, v2 ; 2C20043A v_mac_f32_e32 v17, s62, v2 ; 2C22043E v_mac_f32_e32 v7, s0, v2 ; 2C0E0400 exp 15, 34, 0, 0, 0, v1, v4, v4, v5 ; C400022F 05040401 exp 15, 35, 0, 0, 0, v1, v5, v0, v0 ; C400023F 00000501 exp 15, 36, 0, 0, 0, v18, v19, v0, v0 ; C400024F 00001312 exp 15, 12, 0, 0, 0, v9, v10, v6, v2 ; C40000CF 02060A09 exp 15, 13, 0, 0, 0, v11, v12, v13, v14 ; C40000DF 0E0D0C0B exp 15, 14, 0, 1, 0, v15, v16, v17, v7 ; C40008EF 0711100F s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 72 VGPRS: 20 Code Size: 1192 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL IN[4], GENERIC[4], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0..30] DCL TEMP[0..4], LOCAL IMM[0] FLT32 {100000002004087734272.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], 2D 4: MOV TEMP[2].xy, IN[3].xyyy 5: TEX TEMP[2], TEMP[2], SAMP[0], 2D 6: MOV TEMP[3].xy, IN[1].xyyy 7: TEX TEMP[3], TEMP[3], SAMP[0], 2D 8: MUL TEMP[1].xyz, TEMP[1].wwww, TEMP[1].xyzz 9: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[0].wwww, -TEMP[1].xyzz 10: FRC TEMP[4].xy, IN[4].xyyy 11: MAD TEMP[0].xyz, TEMP[4].xxxx, TEMP[0].xyzz, TEMP[1].xyzz 12: MUL TEMP[3].xyz, TEMP[3].wwww, TEMP[3].xyzz 13: MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[2].wwww, -TEMP[3].xyzz 14: MAD TEMP[3].xyz, TEMP[4].xxxx, TEMP[1].xyzz, TEMP[3].xyzz 15: LRP TEMP[1].xyz, TEMP[4].yyyy, TEMP[3].xyzz, TEMP[0].xyzz 16: MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[0].xyzz 17: MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[30].xxxx 18: MUL TEMP[0].x, CONST[29].wwww, IMM[0].xxxx 19: MOV TEMP[1].w, TEMP[0].xxxx 20: MOV OUT[0], TEMP[1] 21: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 476) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %30 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %31 = load <8 x i32>, <8 x i32> addrspace(2)* %30, align 32, !tbaa !0 %32 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %33 = load <4 x i32>, <4 x i32> addrspace(2)* %32, align 16, !tbaa !0 %34 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %35 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %36 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %37 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %38 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8) %39 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8) %40 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %41 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %42 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %8) %43 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %8) %44 = bitcast float %38 to i32 %45 = bitcast float %39 to i32 %46 = insertelement <2 x i32> undef, i32 %44, i32 0 %47 = insertelement <2 x i32> %46, i32 %45, i32 1 %48 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %47, <8 x i32> %31, <4 x i32> %33, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %49 = extractelement <4 x float> %48, i32 0 %50 = extractelement <4 x float> %48, i32 1 %51 = extractelement <4 x float> %48, i32 2 %52 = extractelement <4 x float> %48, i32 3 %53 = bitcast float %34 to i32 %54 = bitcast float %35 to i32 %55 = insertelement <2 x i32> undef, i32 %53, i32 0 %56 = insertelement <2 x i32> %55, i32 %54, i32 1 %57 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %56, <8 x i32> %31, <4 x i32> %33, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = extractelement <4 x float> %57, i32 2 %61 = extractelement <4 x float> %57, i32 3 %62 = bitcast float %40 to i32 %63 = bitcast float %41 to i32 %64 = insertelement <2 x i32> undef, i32 %62, i32 0 %65 = insertelement <2 x i32> %64, i32 %63, i32 1 %66 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %65, <8 x i32> %31, <4 x i32> %33, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %67 = extractelement <4 x float> %66, i32 0 %68 = extractelement <4 x float> %66, i32 1 %69 = extractelement <4 x float> %66, i32 2 %70 = extractelement <4 x float> %66, i32 3 %71 = bitcast float %36 to i32 %72 = bitcast float %37 to i32 %73 = insertelement <2 x i32> undef, i32 %71, i32 0 %74 = insertelement <2 x i32> %73, i32 %72, i32 1 %75 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %74, <8 x i32> %31, <4 x i32> %33, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %76 = extractelement <4 x float> %75, i32 0 %77 = extractelement <4 x float> %75, i32 1 %78 = extractelement <4 x float> %75, i32 2 %79 = extractelement <4 x float> %75, i32 3 %80 = fmul float %61, %58 %81 = fmul float %61, %59 %82 = fmul float %61, %60 %83 = fmul float %49, %52 %84 = fsub float %83, %80 %85 = fmul float %50, %52 %86 = fsub float %85, %81 %87 = fmul float %51, %52 %88 = fsub float %87, %82 %89 = call float @llvm.floor.f32(float %42) %90 = fsub float %42, %89 %91 = call float @llvm.floor.f32(float %43) %92 = fsub float %43, %91 %93 = fmul float %90, %84 %94 = fadd float %93, %80 %95 = fmul float %90, %86 %96 = fadd float %95, %81 %97 = fmul float %90, %88 %98 = fadd float %97, %82 %99 = fmul float %79, %76 %100 = fmul float %79, %77 %101 = fmul float %79, %78 %102 = fmul float %67, %70 %103 = fsub float %102, %99 %104 = fmul float %68, %70 %105 = fsub float %104, %100 %106 = fmul float %69, %70 %107 = fsub float %106, %101 %108 = fmul float %90, %103 %109 = fadd float %108, %99 %110 = fmul float %90, %105 %111 = fadd float %110, %100 %112 = fmul float %90, %107 %113 = fadd float %112, %101 %114 = fsub float 1.000000e+00, %92 %115 = fmul float %109, %92 %116 = fmul float %94, %114 %117 = fadd float %115, %116 %118 = fsub float 1.000000e+00, %92 %119 = fmul float %111, %92 %120 = fmul float %96, %118 %121 = fadd float %119, %120 %122 = fsub float 1.000000e+00, %92 %123 = fmul float %113, %92 %124 = fmul float %98, %122 %125 = fadd float %123, %124 %126 = fmul float %117, %25 %127 = fmul float %121, %26 %128 = fmul float %125, %27 %129 = fmul float %126, %29 %130 = fmul float %127, %29 %131 = fmul float %128, %29 %132 = fmul float %28, 0x4415AF1D80000000 %133 = call i32 @llvm.SI.packf16(float %129, float %130) %134 = bitcast i32 %133 to float %135 = call i32 @llvm.SI.packf16(float %131, float %132) %136 = bitcast i32 %135 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %134, float %136, float %134, float %136) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.floor.f32(float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[8:15], s[6:7], 0x0 ; C00E0203 00000000 v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s6, s[0:3], 0x0 ; C0220180 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x4 ; C02201C0 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[0:3], 0x8 ; C0220400 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[0:3], 0x1dc ; C0220440 000001DC s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x1e0 ; C0220000 000001E0 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 v_interp_p1_f32 v4, v0, 0, 1, [m0] ; D4100400 v_interp_p2_f32 v4, [v4], v1, 0, 1, [m0] ; D4110401 v_interp_p1_f32 v5, v0, 1, 1, [m0] ; D4140500 v_interp_p2_f32 v5, [v5], v1, 1, 1, [m0] ; D4150501 v_interp_p1_f32 v6, v0, 0, 2, [m0] ; D4180800 v_interp_p2_f32 v6, [v6], v1, 0, 2, [m0] ; D4190801 v_interp_p1_f32 v7, v0, 1, 2, [m0] ; D41C0900 s_load_dwordx4 s[20:23], s[4:5], 0x0 ; C00A0502 00000000 v_interp_p2_f32 v7, [v7], v1, 1, 2, [m0] ; D41D0901 v_interp_p1_f32 v8, v0, 0, 3, [m0] ; D4200C00 v_interp_p2_f32 v8, [v8], v1, 0, 3, [m0] ; D4210C01 v_interp_p1_f32 v9, v0, 1, 3, [m0] ; D4240D00 v_interp_p2_f32 v9, [v9], v1, 1, 3, [m0] ; D4250D01 v_interp_p1_f32 v10, v0, 0, 4, [m0] ; D4281000 v_interp_p2_f32 v10, [v10], v1, 0, 4, [m0] ; D4291001 v_interp_p1_f32 v0, v0, 1, 4, [m0] ; D4001100 v_interp_p2_f32 v0, [v0], v1, 1, 4, [m0] ; D4011101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[8:15], s[20:23] ; F0800F00 00A20B06 s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[8:15], s[20:23] ; F0800F00 00A20F02 s_nop 0 ; BF800000 image_sample v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[8:15], s[20:23] ; F0800F00 00A20608 s_nop 0 ; BF800000 image_sample v[1:4], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[8:15], s[20:23] ; F0800F00 00A20104 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v5, v15, v18 ; 0A0A250F v_mul_f32_e32 v15, v16, v18 ; 0A1E2510 v_mul_f32_e32 v16, v17, v18 ; 0A202511 v_mad_f32 v11, v11, v14, -v5 ; D1C1000B 84161D0B v_mad_f32 v12, v12, v14, -v15 ; D1C1000C 843E1D0C v_mad_f32 v13, v13, v14, -v16 ; D1C1000D 84421D0D v_fract_f32_e32 v10, v10 ; 7E14370A v_fract_f32_e32 v0, v0 ; 7E003700 v_mac_f32_e32 v5, v11, v10 ; 2C0A150B v_mac_f32_e32 v15, v12, v10 ; 2C1E150C v_mac_f32_e32 v16, v13, v10 ; 2C20150D s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v1, v1, v4 ; 0A020901 v_mul_f32_e32 v2, v2, v4 ; 0A040902 v_mul_f32_e32 v3, v3, v4 ; 0A060903 v_mad_f32 v4, v6, v9, -v1 ; D1C10004 84061306 v_mad_f32 v6, v7, v9, -v2 ; D1C10006 840A1307 v_mad_f32 v7, v8, v9, -v3 ; D1C10007 840E1308 v_mac_f32_e32 v1, v4, v10 ; 2C021504 v_mac_f32_e32 v2, v6, v10 ; 2C041506 v_mac_f32_e32 v3, v7, v10 ; 2C061507 v_mad_f32 v4, -v0, v5, v5 ; D1C10004 24160B00 v_mac_f32_e32 v4, v0, v1 ; 2C080300 v_mad_f32 v1, -v0, v15, v15 ; D1C10001 243E1F00 v_mac_f32_e32 v1, v0, v2 ; 2C020500 v_mad_f32 v2, -v0, v16, v16 ; D1C10002 24422100 v_mac_f32_e32 v2, v0, v3 ; 2C040700 v_mul_f32_e32 v0, s6, v4 ; 0A000806 v_mul_f32_e32 v1, s7, v1 ; 0A020207 v_mul_f32_e32 v2, s16, v2 ; 0A040410 v_mul_f32_e32 v0, s0, v0 ; 0A000000 v_mul_f32_e32 v1, s0, v1 ; 0A020200 v_mul_f32_e32 v2, s0, v2 ; 0A040400 v_mov_b32_e32 v3, 0x60ad78ec ; 7E0602FF 60AD78EC v_mul_f32_e32 v3, s17, v3 ; 0A060611 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 20 Code Size: 432 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], COLOR[1] DCL OUT[3], CLIPVERTEX DCL OUT[4], GENERIC[0] DCL OUT[5], GENERIC[1] DCL OUT[6], GENERIC[2] DCL CONST[0..51] DCL TEMP[0..7], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].yzw, IMM[0].xxxx 2: MOV TEMP[2].w, CONST[0].yyyy 3: MAD TEMP[3], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 4: DP4 TEMP[2].x, TEMP[3], CONST[48] 5: DP4 TEMP[4].x, TEMP[3], CONST[49] 6: MOV TEMP[2].y, TEMP[4].xxxx 7: DP4 TEMP[3].x, TEMP[3], CONST[50] 8: MOV TEMP[2].z, TEMP[3].xxxx 9: DP4 TEMP[3].x, TEMP[2], CONST[8] 10: DP4 TEMP[4].x, TEMP[2], CONST[9] 11: MOV TEMP[3].y, TEMP[4].xxxx 12: DP4 TEMP[5].x, TEMP[2], CONST[11] 13: MOV TEMP[3].w, TEMP[5].xxxx 14: DP4 TEMP[6].x, TEMP[2], CONST[10] 15: MOV TEMP[2].w, TEMP[6].xxxx 16: MOV TEMP[3].z, TEMP[6].xxxx 17: MOV TEMP[2], TEMP[2] 18: MOV TEMP[0].xy, IN[1].xyxx 19: MOV TEMP[1].x, IN[3].wwww 20: MOV TEMP[7], TEMP[3] 21: MAD TEMP[6].x, TEMP[6].xxxx, CONST[0].zzzz, -TEMP[5].xxxx 22: MOV TEMP[3].z, TEMP[6].xxxx 23: MOV TEMP[3].y, -TEMP[4].xxxx 24: MAD TEMP[3].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[3].xyyy 25: MUL TEMP[4], CONST[0].yyxx, IN[2].xyxx 26: MAD TEMP[5], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 27: MOV OUT[2], TEMP[1] 28: MOV OUT[4], TEMP[0] 29: MOV OUT[6], TEMP[4] 30: MOV OUT[5], TEMP[2] 31: MOV OUT[0], TEMP[3] 32: MOV OUT[3], TEMP[7] 33: MOV OUT[1], TEMP[5] 34: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, align 16, !tbaa !0 %69 = add i32 %5, %8 %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69) %71 = extractelement <4 x float> %70, i32 3 %72 = fmul float %52, %15 %73 = fadd float %72, %14 %74 = fmul float %53, %15 %75 = fadd float %74, %14 %76 = fmul float %54, %15 %77 = fadd float %76, %14 %78 = fmul float %52, %14 %79 = fadd float %78, %15 %80 = fmul float %73, %34 %81 = fmul float %75, %35 %82 = fadd float %80, %81 %83 = fmul float %77, %36 %84 = fadd float %82, %83 %85 = fmul float %79, %37 %86 = fadd float %84, %85 %87 = fmul float %73, %38 %88 = fmul float %75, %39 %89 = fadd float %87, %88 %90 = fmul float %77, %40 %91 = fadd float %89, %90 %92 = fmul float %79, %41 %93 = fadd float %91, %92 %94 = fmul float %73, %42 %95 = fmul float %75, %43 %96 = fadd float %94, %95 %97 = fmul float %77, %44 %98 = fadd float %96, %97 %99 = fmul float %79, %45 %100 = fadd float %98, %99 %101 = fmul float %86, %17 %102 = fmul float %93, %18 %103 = fadd float %101, %102 %104 = fmul float %100, %19 %105 = fadd float %103, %104 %106 = fmul float %15, %20 %107 = fadd float %105, %106 %108 = fmul float %86, %21 %109 = fmul float %93, %22 %110 = fadd float %108, %109 %111 = fmul float %100, %23 %112 = fadd float %110, %111 %113 = fmul float %15, %24 %114 = fadd float %112, %113 %115 = fmul float %86, %29 %116 = fmul float %93, %30 %117 = fadd float %115, %116 %118 = fmul float %100, %31 %119 = fadd float %117, %118 %120 = fmul float %15, %32 %121 = fadd float %119, %120 %122 = fmul float %86, %25 %123 = fmul float %93, %26 %124 = fadd float %122, %123 %125 = fmul float %100, %27 %126 = fadd float %124, %125 %127 = fmul float %15, %28 %128 = fadd float %126, %127 %129 = fmul float %128, %16 %130 = fsub float %129, %121 %131 = fmul float %46, %121 %132 = fadd float %131, %107 %133 = fmul float %47, %121 %134 = fsub float %133, %114 %135 = fmul float %15, %65 %136 = fmul float %15, %66 %137 = fmul float %14, %65 %138 = fmul float %14, %65 %139 = fmul float %33, %14 %140 = fadd float %139, %15 %141 = fmul float %33, %14 %142 = fadd float %141, %15 %143 = fmul float %33, %14 %144 = fadd float %143, %15 %145 = fmul float %33, %15 %146 = fadd float %145, %14 %147 = and i32 %7, 1 %148 = icmp eq i32 %147, 0 br i1 %148, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %149 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00) %150 = call float @llvm.AMDIL.clamp.(float %142, float 0.000000e+00, float 1.000000e+00) %151 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00) %152 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00) %153 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00) %154 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %155 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %156 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.038 = phi float [ %156, %if-true-block ], [ 0.000000e+00, %main_body ] %.037 = phi float [ %155, %if-true-block ], [ 0.000000e+00, %main_body ] %.036 = phi float [ %154, %if-true-block ], [ 0.000000e+00, %main_body ] %.035 = phi float [ %153, %if-true-block ], [ %71, %main_body ] %.034 = phi float [ %152, %if-true-block ], [ %146, %main_body ] %.033 = phi float [ %151, %if-true-block ], [ %144, %main_body ] %.032 = phi float [ %150, %if-true-block ], [ %142, %main_body ] %.0 = phi float [ %149, %if-true-block ], [ %140, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.032, float %.033, float %.034) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %.035, float %.036, float %.037, float %.038) %157 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %158 = load <16 x i8>, <16 x i8> addrspace(2)* %157, align 16, !tbaa !0 %159 = call float @llvm.SI.load.const(<16 x i8> %158, i32 0) %160 = fmul float %159, %107 %161 = call float @llvm.SI.load.const(<16 x i8> %158, i32 4) %162 = fmul float %161, %114 %163 = fadd float %160, %162 %164 = call float @llvm.SI.load.const(<16 x i8> %158, i32 8) %165 = fmul float %164, %128 %166 = fadd float %163, %165 %167 = call float @llvm.SI.load.const(<16 x i8> %158, i32 12) %168 = fmul float %167, %121 %169 = fadd float %166, %168 %170 = call float @llvm.SI.load.const(<16 x i8> %158, i32 16) %171 = fmul float %170, %107 %172 = call float @llvm.SI.load.const(<16 x i8> %158, i32 20) %173 = fmul float %172, %114 %174 = fadd float %171, %173 %175 = call float @llvm.SI.load.const(<16 x i8> %158, i32 24) %176 = fmul float %175, %128 %177 = fadd float %174, %176 %178 = call float @llvm.SI.load.const(<16 x i8> %158, i32 28) %179 = fmul float %178, %121 %180 = fadd float %177, %179 %181 = call float @llvm.SI.load.const(<16 x i8> %158, i32 32) %182 = fmul float %181, %107 %183 = call float @llvm.SI.load.const(<16 x i8> %158, i32 36) %184 = fmul float %183, %114 %185 = fadd float %182, %184 %186 = call float @llvm.SI.load.const(<16 x i8> %158, i32 40) %187 = fmul float %186, %128 %188 = fadd float %185, %187 %189 = call float @llvm.SI.load.const(<16 x i8> %158, i32 44) %190 = fmul float %189, %121 %191 = fadd float %188, %190 %192 = call float @llvm.SI.load.const(<16 x i8> %158, i32 48) %193 = fmul float %192, %107 %194 = call float @llvm.SI.load.const(<16 x i8> %158, i32 52) %195 = fmul float %194, %114 %196 = fadd float %193, %195 %197 = call float @llvm.SI.load.const(<16 x i8> %158, i32 56) %198 = fmul float %197, %128 %199 = fadd float %196, %198 %200 = call float @llvm.SI.load.const(<16 x i8> %158, i32 60) %201 = fmul float %200, %121 %202 = fadd float %199, %201 %203 = call float @llvm.SI.load.const(<16 x i8> %158, i32 64) %204 = fmul float %203, %107 %205 = call float @llvm.SI.load.const(<16 x i8> %158, i32 68) %206 = fmul float %205, %114 %207 = fadd float %204, %206 %208 = call float @llvm.SI.load.const(<16 x i8> %158, i32 72) %209 = fmul float %208, %128 %210 = fadd float %207, %209 %211 = call float @llvm.SI.load.const(<16 x i8> %158, i32 76) %212 = fmul float %211, %121 %213 = fadd float %210, %212 %214 = call float @llvm.SI.load.const(<16 x i8> %158, i32 80) %215 = fmul float %214, %107 %216 = call float @llvm.SI.load.const(<16 x i8> %158, i32 84) %217 = fmul float %216, %114 %218 = fadd float %215, %217 %219 = call float @llvm.SI.load.const(<16 x i8> %158, i32 88) %220 = fmul float %219, %128 %221 = fadd float %218, %220 %222 = call float @llvm.SI.load.const(<16 x i8> %158, i32 92) %223 = fmul float %222, %121 %224 = fadd float %221, %223 %225 = call float @llvm.SI.load.const(<16 x i8> %158, i32 96) %226 = fmul float %225, %107 %227 = call float @llvm.SI.load.const(<16 x i8> %158, i32 100) %228 = fmul float %227, %114 %229 = fadd float %226, %228 %230 = call float @llvm.SI.load.const(<16 x i8> %158, i32 104) %231 = fmul float %230, %128 %232 = fadd float %229, %231 %233 = call float @llvm.SI.load.const(<16 x i8> %158, i32 108) %234 = fmul float %233, %121 %235 = fadd float %232, %234 %236 = call float @llvm.SI.load.const(<16 x i8> %158, i32 112) %237 = fmul float %236, %107 %238 = call float @llvm.SI.load.const(<16 x i8> %158, i32 116) %239 = fmul float %238, %114 %240 = fadd float %237, %239 %241 = call float @llvm.SI.load.const(<16 x i8> %158, i32 120) %242 = fmul float %241, %128 %243 = fadd float %240, %242 %244 = call float @llvm.SI.load.const(<16 x i8> %158, i32 124) %245 = fmul float %244, %121 %246 = fadd float %243, %245 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %86, float %93, float %100, float %128) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %135, float %136, float %137, float %138) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %132, float %134, float %130, float %121) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %169, float %180, float %191, float %202) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %213, float %224, float %235, float %246) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[36:39], s[2:3], 0x0 ; C00A0901 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x10 ; C00A0604 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x20 ; C00A0704 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[8:9], 0x30 ; C00A0804 00000030 v_add_i32_e32 v4, vcc, s10, v0 ; 3208000A s_and_b32 s0, 1, s12 ; 86000C81 v_cmp_eq_i32_e64 s[40:41], 1, s0 ; D0C20028 00000081 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[36:39], 0x0 ; C0220052 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[36:39], 0x4 ; C0220A92 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[36:39], 0x8 ; C0220012 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[36:39], 0x80 ; C0220452 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[36:39], 0x84 ; C0220552 00000084 buffer_load_format_xyzw v[10:13], v4, s[4:7], 0 idxen ; E00C2000 80010A04 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v4, s[24:27], 0 idxen ; E00C2000 80060004 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v4, s[28:31], 0 idxen ; E00C2000 80070604 s_waitcnt vmcnt(1) ; BF8C0771 buffer_load_format_xyzw v[2:5], v4, s[32:35], 0 idxen ; E00C2000 80080204 s_buffer_load_dword s4, s[36:39], 0xb0 ; C0220112 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[36:39], 0xb4 ; C0220252 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[36:39], 0xb8 ; C0220212 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[36:39], 0xbc ; C0220152 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s34, s[36:39], 0x2fc ; C0220892 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s20, s[36:39], 0x88 ; C0220512 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[36:39], 0x8c ; C02204D2 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[36:39], 0x90 ; C0220412 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[36:39], 0x94 ; C0220492 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[36:39], 0x98 ; C02203D2 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[36:39], 0x9c ; C0220392 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[36:39], 0xa0 ; C0220292 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[36:39], 0xa4 ; C0220352 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[36:39], 0xa8 ; C02202D2 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[36:39], 0xac ; C0220312 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s32, s[36:39], 0x300 ; C0220812 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[36:39], 0x304 ; C0220852 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[36:39], 0x308 ; C02207D2 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[36:39], 0x30c ; C0220792 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[36:39], 0x310 ; C0220712 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[36:39], 0x314 ; C0220752 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[36:39], 0x318 ; C02206D2 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[36:39], 0x31c ; C0220692 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[36:39], 0x320 ; C0220612 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[36:39], 0x324 ; C0220652 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[36:39], 0x328 ; C02205D2 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[36:39], 0x32c ; C0220592 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s6, s[36:39], 0x330 ; C0220192 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[36:39], 0x334 ; C02201D2 00000334 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mov_b32_e32 v2, s42 ; 7E04022A v_mov_b32_e32 v3, s1 ; 7E060201 v_mad_f32 v8, s34, v3, v2 ; D1C10008 040A0622 v_mad_f32 v4, s34, v2, v3 ; D1C10004 040E0422 v_mov_b32_e32 v3, 0 ; 7E060280 v_mov_b32_e32 v13, v8 ; 7E1A0308 v_mov_b32_e32 v9, v8 ; 7E120308 s_and_saveexec_b64 s[34:35], s[40:41] ; BEA22028 s_xor_b64 s[34:35], exec, s[34:35] ; 88A2227E v_add_f32_e64 v9, 0, v8 clamp ; D1018009 00021080 v_add_f32_e64 v13, 0, v8 clamp ; D101800D 00021080 v_add_f32_e64 v8, 0, v8 clamp ; D1018008 00021080 v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_add_f32_e64 v3, 0, 0 clamp ; D1018003 00010080 s_or_b64 exec, exec, s[34:35] ; 87FE227E exp 15, 32, 0, 0, 0, v8, v9, v13, v4 ; C400020F 040D0908 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v4, v2, v10, s1 ; D1C10004 00061502 v_mad_f32 v8, v11, v2, s1 ; D1C10008 0006050B v_mad_f32 v9, v12, v2, s1 ; D1C10009 0006050C v_mad_f32 v10, s1, v10, v2 ; D1C1000A 040A1401 v_mul_f32_e32 v11, s33, v8 ; 0A161021 v_mac_f32_e32 v11, s32, v4 ; 2C160820 v_mac_f32_e32 v11, s31, v9 ; 2C16121F v_mac_f32_e32 v11, s30, v10 ; 2C16141E v_mul_f32_e32 v12, s29, v8 ; 0A18101D v_mac_f32_e32 v12, s28, v4 ; 2C18081C v_mac_f32_e32 v12, s27, v9 ; 2C18121B v_mac_f32_e32 v12, s26, v10 ; 2C18141A v_mul_f32_e32 v8, s25, v8 ; 0A101019 v_mac_f32_e32 v8, s24, v4 ; 2C100818 v_mac_f32_e32 v8, s23, v9 ; 2C101217 v_mac_f32_e32 v8, s22, v10 ; 2C101416 v_mul_f32_e32 v4, s21, v12 ; 0A081815 v_mac_f32_e32 v4, s17, v11 ; 2C081611 v_mac_f32_e32 v4, s20, v8 ; 2C081014 v_mac_f32_e32 v4, s19, v2 ; 2C080413 v_mul_f32_e32 v9, s18, v12 ; 0A121812 v_mac_f32_e32 v9, s16, v11 ; 2C121610 v_mac_f32_e32 v9, s15, v8 ; 2C12100F v_mac_f32_e32 v9, s14, v2 ; 2C12040E s_load_dwordx4 s[16:19], s[2:3], 0x100 ; C00A0401 00000100 v_mul_f32_e32 v10, s9, v12 ; 0A141809 v_mac_f32_e32 v10, s4, v11 ; 2C141604 v_mac_f32_e32 v10, s8, v8 ; 2C141008 v_mac_f32_e32 v10, s5, v2 ; 2C140405 v_mul_f32_e32 v13, s13, v12 ; 0A1A180D v_mac_f32_e32 v13, s10, v11 ; 2C1A160A v_mac_f32_e32 v13, s11, v8 ; 2C1A100B v_mac_f32_e32 v13, s12, v2 ; 2C1A040C v_mul_f32_e32 v14, v6, v2 ; 0A1C0506 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s2, s[16:19], 0x0 ; C0220088 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[16:19], 0x4 ; C02200C8 00000004 v_mul_f32_e32 v2, v7, v2 ; 0A040507 s_buffer_load_dword s4, s[16:19], 0x8 ; C0220108 00000008 v_mul_f32_e32 v6, s1, v6 ; 0A0C0C01 s_buffer_load_dword s1, s[16:19], 0xc ; C0220048 0000000C v_mad_f32 v7, v13, s0, -v10 ; D1C10007 8428010D v_mad_f32 v15, s6, v10, v4 ; D1C1000F 04121406 v_mad_f32 v16, s7, v10, -v9 ; D1C10010 84261407 exp 15, 33, 0, 0, 0, v5, v3, v3, v3 ; C400021F 03030305 s_buffer_load_dword s0, s[16:19], 0x10 ; C0220008 00000010 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v3, s3, v9 ; 0A061203 v_mac_f32_e32 v3, s2, v4 ; 2C060802 v_mac_f32_e32 v3, s4, v13 ; 2C061A04 s_buffer_load_dword s2, s[16:19], 0x14 ; C0220088 00000014 v_mac_f32_e32 v3, s1, v10 ; 2C061401 s_buffer_load_dword s1, s[16:19], 0x18 ; C0220048 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[16:19], 0x1c ; C02200C8 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[16:19], 0x20 ; C0220108 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[16:19], 0x24 ; C0220148 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[16:19], 0x28 ; C0220188 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[16:19], 0x2c ; C02201C8 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[16:19], 0x30 ; C0220208 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[16:19], 0x34 ; C0220248 00000034 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v5, s2, v9 ; 0A0A1202 s_buffer_load_dword s2, s[16:19], 0x38 ; C0220088 00000038 v_mac_f32_e32 v5, s0, v4 ; 2C0A0800 v_mac_f32_e32 v5, s1, v13 ; 2C0A1A01 v_mac_f32_e32 v5, s3, v10 ; 2C0A1403 v_mul_f32_e32 v17, s5, v9 ; 0A221205 v_mac_f32_e32 v17, s4, v4 ; 2C220804 v_mac_f32_e32 v17, s6, v13 ; 2C221A06 v_mac_f32_e32 v17, s7, v10 ; 2C221407 v_mul_f32_e32 v18, s9, v9 ; 0A241209 v_mac_f32_e32 v18, s8, v4 ; 2C240808 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v18, s2, v13 ; 2C241A02 s_buffer_load_dword s0, s[16:19], 0x3c ; C0220008 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[16:19], 0x40 ; C0220048 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[16:19], 0x44 ; C0220088 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[16:19], 0x48 ; C02200C8 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[16:19], 0x4c ; C0220108 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s5, s[16:19], 0x50 ; C0220148 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[16:19], 0x54 ; C0220188 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[16:19], 0x58 ; C02201C8 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[16:19], 0x5c ; C0220208 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s9, s[16:19], 0x60 ; C0220248 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[16:19], 0x64 ; C0220288 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[16:19], 0x68 ; C02202C8 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[16:19], 0x6c ; C0220308 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[16:19], 0x70 ; C0220348 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[16:19], 0x74 ; C0220388 00000074 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v18, s0, v10 ; 2C241400 v_mov_b32_e32 v19, 0 ; 7E260280 exp 15, 34, 0, 0, 0, v0, v1, v19, v19 ; C400022F 13130100 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s2, v9 ; 0A001202 v_mac_f32_e32 v0, s1, v4 ; 2C000801 v_mul_f32_e32 v1, s6, v9 ; 0A021206 v_mac_f32_e32 v1, s5, v4 ; 2C020805 v_mul_f32_e32 v19, s10, v9 ; 0A26120A v_mac_f32_e32 v19, s9, v4 ; 2C260809 v_mul_f32_e32 v9, s14, v9 ; 0A12120E s_buffer_load_dword s0, s[16:19], 0x78 ; C0220008 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[16:19], 0x7c ; C0220048 0000007C exp 15, 35, 0, 0, 0, v11, v12, v8, v13 ; C400023F 0D080C0B exp 15, 36, 0, 0, 0, v14, v2, v6, v6 ; C400024F 0606020E exp 15, 12, 0, 0, 0, v15, v16, v7, v10 ; C40000CF 0A07100F exp 15, 13, 0, 0, 0, v3, v5, v17, v18 ; C40000DF 12110503 v_mac_f32_e32 v9, s13, v4 ; 2C12080D v_mac_f32_e32 v0, s3, v13 ; 2C001A03 v_mac_f32_e32 v1, s7, v13 ; 2C021A07 v_mac_f32_e32 v19, s11, v13 ; 2C261A0B s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v9, s0, v13 ; 2C121A00 v_mac_f32_e32 v0, s4, v10 ; 2C001404 v_mac_f32_e32 v1, s8, v10 ; 2C021408 v_mac_f32_e32 v19, s12, v10 ; 2C26140C v_mac_f32_e32 v9, s1, v10 ; 2C121401 exp 15, 14, 0, 1, 0, v0, v1, v19, v9 ; C40008EF 09130100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 20 Code Size: 1388 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], COLOR[1], COLOR DCL IN[2], GENERIC[0], PERSPECTIVE DCL IN[3], GENERIC[1], PERSPECTIVE DCL IN[4], GENERIC[2], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..17], LOCAL IMM[0] FLT32 { 0.0000, 0.2125, 0.7154, 0.0721} IMM[1] FLT32 { 1.0000, 0.0000, 2.0000, -0.5000} IMM[2] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[3] FLT32 { 0.0005, 0.0000, -0.0005, 0.1250} IMM[4] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[5] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[2].xyyy 3: TEX TEMP[2].xyz, TEMP[1], SAMP[2], 2D 4: MOV TEMP[3].xy, IN[4].xyyy 5: TEX TEMP[3], TEMP[3], SAMP[1], 2D 6: MOV TEMP[4], TEMP[3] 7: LRP TEMP[2].xyz, IN[1].xxxx, TEMP[2].xyzz, TEMP[0].xyzz 8: MUL TEMP[1].xyz, TEMP[2].xyzz, IN[0].xyzz 9: MUL TEMP[5].x, TEMP[0].wwww, IN[0].wwww 10: MOV TEMP[5].w, TEMP[5].xxxx 11: MUL TEMP[0].xyz, TEMP[3].xyzz, CONST[12].xyzz 12: FSLT TEMP[6].x, -TEMP[3].wwww, IMM[0].xxxx 13: AND TEMP[6].x, CONST[90].xxxx, TEMP[6].xxxx 14: UIF TEMP[6].xxxx :0 15: DP3 TEMP[6].x, TEMP[3].xyzz, IMM[0].yzww 16: RCP TEMP[6].x, TEMP[6].xxxx 17: MUL TEMP[3].x, TEMP[6].xxxx, TEMP[3].wwww 18: MAD TEMP[4], IN[3].xyzx, IMM[1].xxxy, IMM[1].yyyx 19: DP4 TEMP[2].x, TEMP[4], CONST[69] 20: DP4 TEMP[6].x, TEMP[4], CONST[70] 21: MOV TEMP[2].y, TEMP[6].xxxx 22: MOV_SAT TEMP[7].xy, TEMP[2].xyyy 23: ADD TEMP[7].xy, -TEMP[2].xyyy, TEMP[7].xyyy 24: DP2 TEMP[8].x, TEMP[7].xyyy, IMM[1].xxxx 25: DP4 TEMP[7].x, TEMP[4], CONST[73] 26: DP4 TEMP[9].x, TEMP[4], CONST[74] 27: MOV TEMP[7].y, TEMP[9].xxxx 28: MOV_SAT TEMP[10].xy, TEMP[7].xyyy 29: ADD TEMP[10].xy, -TEMP[7].xyyy, TEMP[10].xyyy 30: DP2 TEMP[11].x, TEMP[10].xyyy, IMM[1].xxxx 31: MOV TEMP[2].w, TEMP[11].xxxx 32: DP4 TEMP[10].x, TEMP[4], CONST[77] 33: DP4 TEMP[12].x, TEMP[4], CONST[78] 34: MOV TEMP[7].z, IMM[1].xxxx 35: MOV TEMP[13].w, TEMP[7] 36: ABS TEMP[14].x, TEMP[11].xxxx 37: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 38: UIF TEMP[14].xxxx :0 39: MOV TEMP[14].x, TEMP[7].xxxx 40: ELSE :0 41: MOV TEMP[14].x, TEMP[10].xxxx 42: ENDIF 43: MOV TEMP[13].x, TEMP[14].xxxx 44: ABS TEMP[14].x, TEMP[11].xxxx 45: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 46: UIF TEMP[14].xxxx :0 47: MOV TEMP[9].x, TEMP[9].xxxx 48: ELSE :0 49: MOV TEMP[9].x, TEMP[12].xxxx 50: ENDIF 51: MOV TEMP[13].y, TEMP[9].xxxx 52: ABS TEMP[9].x, TEMP[11].xxxx 53: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 54: UIF TEMP[9].xxxx :0 55: MOV TEMP[9].x, IMM[1].xxxx 56: ELSE :0 57: MOV TEMP[9].x, IMM[1].zzzz 58: ENDIF 59: MOV TEMP[13].z, TEMP[9].xxxx 60: MOV TEMP[7].xyz, TEMP[13] 61: MOV TEMP[2].z, IMM[0].xxxx 62: MOV TEMP[13].w, TEMP[2] 63: ABS TEMP[9].x, TEMP[8].xxxx 64: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 65: UIF TEMP[9].xxxx :0 66: MOV TEMP[9].x, TEMP[2].xxxx 67: ELSE :0 68: MOV TEMP[9].x, TEMP[7].xxxx 69: ENDIF 70: MOV TEMP[13].x, TEMP[9].xxxx 71: ABS TEMP[9].x, TEMP[8].xxxx 72: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 73: UIF TEMP[9].xxxx :0 74: MOV TEMP[6].x, TEMP[6].xxxx 75: ELSE :0 76: MOV TEMP[6].x, TEMP[7].yyyy 77: ENDIF 78: MOV TEMP[13].y, TEMP[6].xxxx 79: ABS TEMP[6].x, TEMP[8].xxxx 80: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].xxxx 81: UIF TEMP[6].xxxx :0 82: MOV TEMP[6].x, IMM[0].xxxx 83: ELSE :0 84: MOV TEMP[6].x, TEMP[7].zzzz 85: ENDIF 86: MOV TEMP[13].z, TEMP[6].xxxx 87: MOV TEMP[2].z, TEMP[13].wwzw 88: DP4 TEMP[8].x, TEMP[4], CONST[71] 89: MOV TEMP[7].z, TEMP[8].xxxx 90: ADD TEMP[10].xy, TEMP[13].xyyy, IMM[1].wwww 91: ABS TEMP[9].xy, TEMP[10].xyyy 92: ADD TEMP[10].xy, TEMP[9].xyyy, -CONST[67].zzzz 93: MUL TEMP[10].xy, TEMP[10].xyyy, CONST[67].wwww 94: MOV_SAT TEMP[9].xy, TEMP[10].xyyy 95: ADD TEMP[10].xy, -TEMP[9].xyyy, IMM[1].xxxx 96: MUL TEMP[9].x, TEMP[10].yyyy, TEMP[10].xxxx 97: MOV_SAT TEMP[11].xy, TEMP[13].xyyy 98: ADD TEMP[10].xyz, TEMP[6].xxxx, IMM[2].xyzz 99: MOV TEMP[6].x, IMM[0].xxxx 100: ABS TEMP[14].x, TEMP[10].xxxx 101: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 102: UIF TEMP[14].xxxx :0 103: MOV TEMP[14].x, CONST[85].zzzz 104: ELSE :0 105: MOV TEMP[14].x, IMM[0].xxxx 106: ENDIF 107: ABS TEMP[15].x, TEMP[10].xxxx 108: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 109: UIF TEMP[15].xxxx :0 110: MOV TEMP[15].x, CONST[85].wwww 111: ELSE :0 112: MOV TEMP[15].x, IMM[0].xxxx 113: ENDIF 114: MOV TEMP[13].y, TEMP[15].xxxx 115: ABS TEMP[15].x, TEMP[10].xxxx 116: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 117: UIF TEMP[15].xxxx :0 118: MOV TEMP[15].x, CONST[85].xxxx 119: ELSE :0 120: MOV TEMP[15].x, IMM[0].xxxx 121: ENDIF 122: MOV TEMP[13].z, TEMP[15].xxxx 123: ABS TEMP[15].x, TEMP[10].xxxx 124: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 125: UIF TEMP[15].xxxx :0 126: MOV TEMP[15].x, CONST[85].yyyy 127: ELSE :0 128: MOV TEMP[15].x, IMM[0].xxxx 129: ENDIF 130: MOV TEMP[13].w, TEMP[15].xxxx 131: ABS TEMP[15].x, TEMP[10].yyyy 132: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 133: UIF TEMP[15].xxxx :0 134: MOV TEMP[15].x, CONST[86].zzzz 135: ELSE :0 136: MOV TEMP[15].x, TEMP[14].xxxx 137: ENDIF 138: MOV TEMP[13].x, TEMP[15].xxxx 139: ABS TEMP[14].x, TEMP[10].yyyy 140: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 141: UIF TEMP[14].xxxx :0 142: MOV TEMP[14].x, CONST[86].wwww 143: ELSE :0 144: MOV TEMP[14].x, TEMP[13].yyyy 145: ENDIF 146: MOV TEMP[13].y, TEMP[14].xxxx 147: ABS TEMP[14].x, TEMP[10].yyyy 148: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 149: UIF TEMP[14].xxxx :0 150: MOV TEMP[14].x, CONST[86].xxxx 151: ELSE :0 152: MOV TEMP[14].x, TEMP[13].zzzz 153: ENDIF 154: MOV TEMP[13].z, TEMP[14].xxxx 155: ABS TEMP[14].x, TEMP[10].yyyy 156: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 157: UIF TEMP[14].xxxx :0 158: MOV TEMP[14].x, CONST[86].yyyy 159: ELSE :0 160: MOV TEMP[14].x, TEMP[13].wwww 161: ENDIF 162: MOV TEMP[13].w, TEMP[14].xxxx 163: MOV TEMP[12], TEMP[13] 164: ABS TEMP[14].x, TEMP[10].zzzz 165: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 166: UIF TEMP[14].xxxx :0 167: MOV TEMP[14].x, CONST[87].zzzz 168: ELSE :0 169: MOV TEMP[14].x, TEMP[12].xxxx 170: ENDIF 171: MOV TEMP[13].x, TEMP[14].xxxx 172: ABS TEMP[14].x, TEMP[10].zzzz 173: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 174: UIF TEMP[14].xxxx :0 175: MOV TEMP[14].x, CONST[87].wwww 176: ELSE :0 177: MOV TEMP[14].x, TEMP[12].yyyy 178: ENDIF 179: MOV TEMP[13].y, TEMP[14].xxxx 180: ABS TEMP[14].x, TEMP[10].zzzz 181: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 182: UIF TEMP[14].xxxx :0 183: MOV TEMP[14].x, CONST[87].xxxx 184: ELSE :0 185: MOV TEMP[14].x, TEMP[12].zzzz 186: ENDIF 187: MOV TEMP[13].z, TEMP[14].xxxx 188: ABS TEMP[14].x, TEMP[10].zzzz 189: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 190: UIF TEMP[14].xxxx :0 191: MOV TEMP[14].x, CONST[87].yyyy 192: ELSE :0 193: MOV TEMP[14].x, TEMP[12].wwww 194: ENDIF 195: MOV TEMP[13].w, TEMP[14].xxxx 196: MAD TEMP[7].xy, TEMP[11].xyyy, TEMP[13].xyyy, TEMP[13].zwww 197: MOV TEMP[7].w, IMM[0].xxxx 198: ADD TEMP[10], TEMP[7], IMM[3].xxyy 199: TXL TEMP[11].x, TEMP[10], SAMP[3], SHADOW2D 200: MOV TEMP[10].x, TEMP[11].xxxx 201: ADD TEMP[12], TEMP[7], IMM[3].zxyy 202: ADD TEMP[11], TEMP[7], IMM[3].xzyy 203: ADD TEMP[14], TEMP[7], IMM[3].zzyy 204: TXL TEMP[15].x, TEMP[12], SAMP[3], SHADOW2D 205: MOV TEMP[10].y, TEMP[15].xxxx 206: TXL TEMP[15].x, TEMP[11], SAMP[3], SHADOW2D 207: MOV TEMP[10].z, TEMP[15].xxxx 208: TXL TEMP[15].x, TEMP[14], SAMP[3], SHADOW2D 209: MOV TEMP[10].w, TEMP[15].xxxx 210: DP4 TEMP[15].x, TEMP[10], IMM[2].wwww 211: ADD TEMP[10], TEMP[7], IMM[3].xyyy 212: TXL TEMP[16].x, TEMP[10], SAMP[3], SHADOW2D 213: MOV TEMP[10].x, TEMP[16].xxxx 214: ADD TEMP[12], TEMP[7], IMM[3].zyyy 215: TXL TEMP[16], TEMP[12], SAMP[3], SHADOW2D 216: MOV TEMP[12], TEMP[16] 217: ADD TEMP[11], TEMP[7], IMM[3].yzyy 218: TXL TEMP[17], TEMP[11], SAMP[3], SHADOW2D 219: MOV TEMP[11], TEMP[17] 220: ADD TEMP[14], TEMP[7], IMM[3].yxyy 221: TXL TEMP[14].x, TEMP[14], SAMP[3], SHADOW2D 222: MOV TEMP[10].y, TEMP[16].xxxx 223: MOV TEMP[10].z, TEMP[17].xxxx 224: MOV TEMP[10].w, TEMP[14].xxxx 225: DP4 TEMP[14].x, TEMP[10], IMM[3].wwww 226: MOV TEMP[16].xy, TEMP[7].xyyy 227: MOV TEMP[16].z, TEMP[8].xxxx 228: MOV TEMP[16].w, IMM[0].xxxx 229: TXL TEMP[16], TEMP[16], SAMP[3], SHADOW2D 230: MOV TEMP[10], TEMP[16] 231: ADD TEMP[2].x, TEMP[14].xxxx, TEMP[15].xxxx 232: MAD TEMP[2].x, TEMP[16].xxxx, IMM[4].xxxx, TEMP[2].xxxx 233: FSLT TEMP[14].x, TEMP[9].xxxx, IMM[1].xxxx 234: UIF TEMP[14].xxxx :0 235: ADD TEMP[14].xyz, TEMP[2].zzzz, IMM[4].yzww 236: ABS TEMP[15].x, TEMP[14].xxxx 237: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 238: UIF TEMP[15].xxxx :0 239: MOV TEMP[15].x, CONST[73].xxxx 240: ELSE :0 241: MOV TEMP[15].x, IMM[0].xxxx 242: ENDIF 243: MOV TEMP[13].x, TEMP[15].xxxx 244: ABS TEMP[15].x, TEMP[14].xxxx 245: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 246: UIF TEMP[15].xxxx :0 247: MOV TEMP[15].x, CONST[73].yyyy 248: ELSE :0 249: MOV TEMP[15].x, IMM[0].xxxx 250: ENDIF 251: MOV TEMP[13].y, TEMP[15].xxxx 252: ABS TEMP[15].x, TEMP[14].xxxx 253: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 254: UIF TEMP[15].xxxx :0 255: MOV TEMP[15].x, CONST[73].zzzz 256: ELSE :0 257: MOV TEMP[15].x, IMM[0].xxxx 258: ENDIF 259: MOV TEMP[13].z, TEMP[15].xxxx 260: ABS TEMP[15].x, TEMP[14].xxxx 261: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 262: UIF TEMP[15].xxxx :0 263: MOV TEMP[15].x, CONST[73].wwww 264: ELSE :0 265: MOV TEMP[15].x, IMM[0].xxxx 266: ENDIF 267: MOV TEMP[13].w, TEMP[15].xxxx 268: MOV TEMP[10], TEMP[13] 269: ABS TEMP[15].x, TEMP[14].xxxx 270: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 271: UIF TEMP[15].xxxx :0 272: MOV TEMP[15].x, CONST[74].xxxx 273: ELSE :0 274: MOV TEMP[15].x, IMM[0].xxxx 275: ENDIF 276: MOV TEMP[13].x, TEMP[15].xxxx 277: ABS TEMP[15].x, TEMP[14].xxxx 278: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 279: UIF TEMP[15].xxxx :0 280: MOV TEMP[15].x, CONST[74].yyyy 281: ELSE :0 282: MOV TEMP[15].x, IMM[0].xxxx 283: ENDIF 284: MOV TEMP[13].y, TEMP[15].xxxx 285: ABS TEMP[15].x, TEMP[14].xxxx 286: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 287: UIF TEMP[15].xxxx :0 288: MOV TEMP[15].x, CONST[74].zzzz 289: ELSE :0 290: MOV TEMP[15].x, IMM[0].xxxx 291: ENDIF 292: MOV TEMP[13].z, TEMP[15].xxxx 293: ABS TEMP[15].x, TEMP[14].xxxx 294: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 295: UIF TEMP[15].xxxx :0 296: MOV TEMP[15].x, CONST[74].wwww 297: ELSE :0 298: MOV TEMP[15].x, IMM[0].xxxx 299: ENDIF 300: MOV TEMP[13].w, TEMP[15].xxxx 301: MOV TEMP[12], TEMP[13] 302: ABS TEMP[15].x, TEMP[14].yyyy 303: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 304: UIF TEMP[15].xxxx :0 305: MOV TEMP[15].x, CONST[77].xxxx 306: ELSE :0 307: MOV TEMP[15].x, TEMP[10].xxxx 308: ENDIF 309: MOV TEMP[13].x, TEMP[15].xxxx 310: ABS TEMP[15].x, TEMP[14].yyyy 311: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 312: UIF TEMP[15].xxxx :0 313: MOV TEMP[15].x, CONST[77].yyyy 314: ELSE :0 315: MOV TEMP[15].x, TEMP[10].yyyy 316: ENDIF 317: MOV TEMP[13].y, TEMP[15].xxxx 318: ABS TEMP[15].x, TEMP[14].yyyy 319: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 320: UIF TEMP[15].xxxx :0 321: MOV TEMP[15].x, CONST[77].zzzz 322: ELSE :0 323: MOV TEMP[15].x, TEMP[10].zzzz 324: ENDIF 325: MOV TEMP[13].z, TEMP[15].xxxx 326: ABS TEMP[15].x, TEMP[14].yyyy 327: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 328: UIF TEMP[15].xxxx :0 329: MOV TEMP[15].x, CONST[77].wwww 330: ELSE :0 331: MOV TEMP[15].x, TEMP[10].wwww 332: ENDIF 333: MOV TEMP[13].w, TEMP[15].xxxx 334: MOV TEMP[10], TEMP[13] 335: ABS TEMP[15].x, TEMP[14].yyyy 336: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 337: UIF TEMP[15].xxxx :0 338: MOV TEMP[15].x, CONST[78].xxxx 339: ELSE :0 340: MOV TEMP[15].x, TEMP[12].xxxx 341: ENDIF 342: MOV TEMP[13].x, TEMP[15].xxxx 343: ABS TEMP[15].x, TEMP[14].yyyy 344: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 345: UIF TEMP[15].xxxx :0 346: MOV TEMP[15].x, CONST[78].yyyy 347: ELSE :0 348: MOV TEMP[15].x, TEMP[12].yyyy 349: ENDIF 350: MOV TEMP[13].y, TEMP[15].xxxx 351: ABS TEMP[15].x, TEMP[14].yyyy 352: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 353: UIF TEMP[15].xxxx :0 354: MOV TEMP[15].x, CONST[78].zzzz 355: ELSE :0 356: MOV TEMP[15].x, TEMP[12].zzzz 357: ENDIF 358: MOV TEMP[13].z, TEMP[15].xxxx 359: ABS TEMP[15].x, TEMP[14].yyyy 360: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 361: UIF TEMP[15].xxxx :0 362: MOV TEMP[15].x, CONST[78].wwww 363: ELSE :0 364: MOV TEMP[15].x, TEMP[12].wwww 365: ENDIF 366: MOV TEMP[13].w, TEMP[15].xxxx 367: MOV TEMP[12], TEMP[13] 368: ABS TEMP[15].x, TEMP[14].zzzz 369: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 370: UIF TEMP[15].xxxx :0 371: MOV TEMP[15].x, CONST[81].xxxx 372: ELSE :0 373: MOV TEMP[15].x, TEMP[10].xxxx 374: ENDIF 375: MOV TEMP[13].x, TEMP[15].xxxx 376: ABS TEMP[15].x, TEMP[14].zzzz 377: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 378: UIF TEMP[15].xxxx :0 379: MOV TEMP[15].x, CONST[81].yyyy 380: ELSE :0 381: MOV TEMP[15].x, TEMP[10].yyyy 382: ENDIF 383: MOV TEMP[13].y, TEMP[15].xxxx 384: ABS TEMP[15].x, TEMP[14].zzzz 385: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 386: UIF TEMP[15].xxxx :0 387: MOV TEMP[15].x, CONST[81].zzzz 388: ELSE :0 389: MOV TEMP[15].x, TEMP[10].zzzz 390: ENDIF 391: MOV TEMP[13].z, TEMP[15].xxxx 392: ABS TEMP[15].x, TEMP[14].zzzz 393: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 394: UIF TEMP[15].xxxx :0 395: MOV TEMP[15].x, CONST[81].wwww 396: ELSE :0 397: MOV TEMP[15].x, TEMP[10].wwww 398: ENDIF 399: MOV TEMP[13].w, TEMP[15].xxxx 400: MOV TEMP[10], TEMP[13] 401: ABS TEMP[15].x, TEMP[14].zzzz 402: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 403: UIF TEMP[15].xxxx :0 404: MOV TEMP[15].x, CONST[82].xxxx 405: ELSE :0 406: MOV TEMP[15].x, TEMP[12].xxxx 407: ENDIF 408: MOV TEMP[13].x, TEMP[15].xxxx 409: ABS TEMP[15].x, TEMP[14].zzzz 410: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 411: UIF TEMP[15].xxxx :0 412: MOV TEMP[15].x, CONST[82].yyyy 413: ELSE :0 414: MOV TEMP[15].x, TEMP[12].yyyy 415: ENDIF 416: MOV TEMP[13].y, TEMP[15].xxxx 417: ABS TEMP[15].x, TEMP[14].zzzz 418: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 419: UIF TEMP[15].xxxx :0 420: MOV TEMP[15].x, CONST[82].zzzz 421: ELSE :0 422: MOV TEMP[15].x, TEMP[12].zzzz 423: ENDIF 424: MOV TEMP[13].z, TEMP[15].xxxx 425: ABS TEMP[15].x, TEMP[14].zzzz 426: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 427: UIF TEMP[15].xxxx :0 428: MOV TEMP[15].x, CONST[82].wwww 429: ELSE :0 430: MOV TEMP[15].x, TEMP[12].wwww 431: ENDIF 432: MOV TEMP[13].w, TEMP[15].xxxx 433: DP4 TEMP[10].x, TEMP[4], TEMP[10] 434: MOV_SAT TEMP[10].x, TEMP[10].xxxx 435: DP4 TEMP[15].x, TEMP[4], TEMP[13] 436: MOV_SAT TEMP[15].x, TEMP[15].xxxx 437: MOV TEMP[10].y, TEMP[15].xxxx 438: ABS TEMP[15].x, TEMP[14].xxxx 439: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 440: UIF TEMP[15].xxxx :0 441: MOV TEMP[15].x, CONST[86].zzzz 442: ELSE :0 443: MOV TEMP[15].x, IMM[0].xxxx 444: ENDIF 445: ABS TEMP[16].x, TEMP[14].xxxx 446: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 447: UIF TEMP[16].xxxx :0 448: MOV TEMP[16].x, CONST[86].wwww 449: ELSE :0 450: MOV TEMP[16].x, IMM[0].xxxx 451: ENDIF 452: MOV TEMP[13].y, TEMP[16].xxxx 453: ABS TEMP[16].x, TEMP[14].xxxx 454: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 455: UIF TEMP[16].xxxx :0 456: MOV TEMP[16].x, CONST[86].xxxx 457: ELSE :0 458: MOV TEMP[16].x, IMM[0].xxxx 459: ENDIF 460: MOV TEMP[13].z, TEMP[16].xxxx 461: ABS TEMP[16].x, TEMP[14].xxxx 462: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 463: UIF TEMP[16].xxxx :0 464: MOV TEMP[16].x, CONST[86].yyyy 465: ELSE :0 466: MOV TEMP[16].x, IMM[0].xxxx 467: ENDIF 468: MOV TEMP[13].w, TEMP[16].xxxx 469: ABS TEMP[16].x, TEMP[14].yyyy 470: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 471: UIF TEMP[16].xxxx :0 472: MOV TEMP[16].x, CONST[87].zzzz 473: ELSE :0 474: MOV TEMP[16].x, TEMP[15].xxxx 475: ENDIF 476: ABS TEMP[15].x, TEMP[14].yyyy 477: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 478: UIF TEMP[15].xxxx :0 479: MOV TEMP[15].x, CONST[87].wwww 480: ELSE :0 481: MOV TEMP[15].x, TEMP[13].yyyy 482: ENDIF 483: MOV TEMP[13].y, TEMP[15].xxxx 484: ABS TEMP[15].x, TEMP[14].yyyy 485: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 486: UIF TEMP[15].xxxx :0 487: MOV TEMP[15].x, CONST[87].xxxx 488: ELSE :0 489: MOV TEMP[15].x, TEMP[13].zzzz 490: ENDIF 491: MOV TEMP[13].z, TEMP[15].xxxx 492: ABS TEMP[15].x, TEMP[14].yyyy 493: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 494: UIF TEMP[15].xxxx :0 495: MOV TEMP[15].x, CONST[87].yyyy 496: ELSE :0 497: MOV TEMP[15].x, TEMP[13].wwww 498: ENDIF 499: MOV TEMP[13].w, TEMP[15].xxxx 500: ABS TEMP[15].x, TEMP[14].zzzz 501: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 502: UIF TEMP[15].xxxx :0 503: MOV TEMP[15].x, CONST[88].zzzz 504: ELSE :0 505: MOV TEMP[15].x, TEMP[16].xxxx 506: ENDIF 507: MOV TEMP[13].x, TEMP[15].xxxx 508: ABS TEMP[15].x, TEMP[14].zzzz 509: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 510: UIF TEMP[15].xxxx :0 511: MOV TEMP[15].x, CONST[88].wwww 512: ELSE :0 513: MOV TEMP[15].x, TEMP[13].yyyy 514: ENDIF 515: MOV TEMP[13].y, TEMP[15].xxxx 516: ABS TEMP[15].x, TEMP[14].zzzz 517: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 518: UIF TEMP[15].xxxx :0 519: MOV TEMP[15].x, CONST[88].xxxx 520: ELSE :0 521: MOV TEMP[15].x, TEMP[13].zzzz 522: ENDIF 523: MOV TEMP[13].z, TEMP[15].xxxx 524: ABS TEMP[15].x, TEMP[14].zzzz 525: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 526: UIF TEMP[15].xxxx :0 527: MOV TEMP[15].x, CONST[88].yyyy 528: ELSE :0 529: MOV TEMP[15].x, TEMP[13].wwww 530: ENDIF 531: MOV TEMP[13].w, TEMP[15].xxxx 532: MAD TEMP[7].xy, TEMP[10].xyyy, TEMP[13].xyyy, TEMP[13].zwww 533: ADD TEMP[4], TEMP[7], IMM[3].xxyy 534: TXL TEMP[13].x, TEMP[4], SAMP[3], SHADOW2D 535: MOV TEMP[4].x, TEMP[13].xxxx 536: ADD TEMP[10], TEMP[7], IMM[3].zxyy 537: ADD TEMP[6], TEMP[7], IMM[3].xzyy 538: ADD TEMP[12], TEMP[7], IMM[3].zzyy 539: TXL TEMP[13].x, TEMP[10], SAMP[3], SHADOW2D 540: MOV TEMP[4].y, TEMP[13].xxxx 541: TXL TEMP[13].x, TEMP[6], SAMP[3], SHADOW2D 542: MOV TEMP[4].z, TEMP[13].xxxx 543: TXL TEMP[13].x, TEMP[12], SAMP[3], SHADOW2D 544: MOV TEMP[4].w, TEMP[13].xxxx 545: DP4 TEMP[13].x, TEMP[4], IMM[2].wwww 546: ADD TEMP[10], TEMP[7], IMM[3].xyyy 547: TXL TEMP[15].x, TEMP[10], SAMP[3], SHADOW2D 548: MOV TEMP[10].x, TEMP[15].xxxx 549: ADD TEMP[6], TEMP[7], IMM[3].zyyy 550: TXL TEMP[6].x, TEMP[6], SAMP[3], SHADOW2D 551: ADD TEMP[12], TEMP[7], IMM[3].yzyy 552: TXL TEMP[12].x, TEMP[12], SAMP[3], SHADOW2D 553: ADD TEMP[11], TEMP[7], IMM[3].yxyy 554: TXL TEMP[11].x, TEMP[11], SAMP[3], SHADOW2D 555: MOV TEMP[10].y, TEMP[6].xxxx 556: MOV TEMP[10].z, TEMP[12].xxxx 557: MOV TEMP[10].w, TEMP[11].xxxx 558: DP4 TEMP[6].x, TEMP[10], IMM[3].wwww 559: MOV TEMP[10].xy, TEMP[7].xyyy 560: MOV TEMP[10].z, TEMP[8].xxxx 561: MOV TEMP[10].w, IMM[0].xxxx 562: TXL TEMP[8].x, TEMP[10], SAMP[3], SHADOW2D 563: ADD TEMP[4].x, TEMP[6].xxxx, TEMP[13].xxxx 564: MAD TEMP[4].x, TEMP[8].xxxx, IMM[4].xxxx, TEMP[4].xxxx 565: FSGE TEMP[6].x, TEMP[14].zzzz, IMM[0].xxxx 566: UIF TEMP[6].xxxx :0 567: MOV TEMP[6].x, IMM[1].xxxx 568: ELSE :0 569: MOV TEMP[6].x, TEMP[4].xxxx 570: ENDIF 571: LRP TEMP[7].x, TEMP[9].xxxx, TEMP[2].xxxx, TEMP[6].xxxx 572: MOV TEMP[2].x, TEMP[7].xxxx 573: ENDIF 574: ADD TEMP[4].xyz, -CONST[89].xyzz, IN[3].xyzz 575: DP3 TEMP[6].x, TEMP[4].xyzz, TEMP[4].xyzz 576: MAD TEMP[6].x, TEMP[6].xxxx, CONST[68].yyyy, CONST[68].xxxx 577: MOV_SAT TEMP[6].x, TEMP[6].xxxx 578: LRP TEMP[4].x, TEMP[6].xxxx, IMM[1].xxxx, TEMP[2].xxxx 579: ADD TEMP[2].x, -TEMP[4].xxxx, IMM[1].xxxx 580: MAD TEMP[2].x, TEMP[3].xxxx, -TEMP[2].xxxx, IMM[1].xxxx 581: MUL TEMP[4].xyz, TEMP[2].xxxx, TEMP[0].zyxx 582: MAD TEMP[2].x, TEMP[2].xxxx, IMM[5].xxxx, IMM[5].xxxx 583: LRP TEMP[0].xyz, TEMP[2].xxxx, TEMP[4].zyxx, TEMP[4].xyzz 584: ENDIF 585: ADD TEMP[0].xyz, TEMP[0].xyzz, CONST[31].xyzz 586: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xyzz 587: ADD TEMP[0].xyz, CONST[10].xyzz, -IN[3].xyzz 588: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[0].xyzz 589: SQRT TEMP[0].x, TEMP[0].xxxx 590: MAD TEMP[0].x, TEMP[0].xxxx, CONST[11].wwww, CONST[11].xxxx 591: MOV_SAT TEMP[0].x, TEMP[0].xxxx 592: MIN TEMP[0].x, TEMP[0].xxxx, CONST[11].zzzz 593: MUL TEMP[2].xyz, TEMP[1].xyzz, CONST[30].xxxx 594: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx 595: MAD TEMP[1].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz 596: MAD TEMP[5].xyz, TEMP[0].xxxx, TEMP[1].xyzz, TEMP[2].xyzz 597: MOV OUT[0], TEMP[5] 598: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %85 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %86 = load <8 x i32>, <8 x i32> addrspace(2)* %85, align 32, !tbaa !0 %87 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %88 = load <4 x i32>, <4 x i32> addrspace(2)* %87, align 16, !tbaa !0 %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = and i32 %5, 1 %102 = icmp ne i32 %101, 0 %103 = select i1 %102, <2 x i32> %7, <2 x i32> %8 %104 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %103) %105 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %103) %106 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %103) %107 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %103) %108 = and i32 %5, 1 %109 = icmp ne i32 %108, 0 %110 = select i1 %109, <2 x i32> %7, <2 x i32> %8 %111 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %110) %112 = and i32 %5, 1 %113 = icmp ne i32 %112, 0 %114 = select i1 %113, <2 x i32> %7, <2 x i32> %8 %115 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %114) %116 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %114) %117 = and i32 %5, 1 %118 = icmp ne i32 %117, 0 %119 = select i1 %118, <2 x i32> %7, <2 x i32> %8 %120 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %119) %121 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %119) %122 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %119) %123 = and i32 %5, 1 %124 = icmp ne i32 %123, 0 %125 = select i1 %124, <2 x i32> %7, <2 x i32> %9 %126 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %125) %127 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %125) %128 = bitcast float %115 to i32 %129 = bitcast float %116 to i32 %130 = insertelement <2 x i32> undef, i32 %128, i32 0 %131 = insertelement <2 x i32> %130, i32 %129, i32 1 %132 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %131, <8 x i32> %86, <4 x i32> %88, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %133 = extractelement <4 x float> %132, i32 0 %134 = extractelement <4 x float> %132, i32 1 %135 = extractelement <4 x float> %132, i32 2 %136 = extractelement <4 x float> %132, i32 3 %137 = bitcast float %115 to i32 %138 = bitcast float %116 to i32 %139 = insertelement <2 x i32> undef, i32 %137, i32 0 %140 = insertelement <2 x i32> %139, i32 %138, i32 1 %141 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %140, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %142 = extractelement <4 x float> %141, i32 0 %143 = extractelement <4 x float> %141, i32 1 %144 = extractelement <4 x float> %141, i32 2 %145 = bitcast float %126 to i32 %146 = bitcast float %127 to i32 %147 = insertelement <2 x i32> undef, i32 %145, i32 0 %148 = insertelement <2 x i32> %147, i32 %146, i32 1 %149 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %148, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %150 = extractelement <4 x float> %149, i32 0 %151 = extractelement <4 x float> %149, i32 1 %152 = extractelement <4 x float> %149, i32 2 %153 = extractelement <4 x float> %149, i32 3 %154 = fsub float 1.000000e+00, %111 %155 = fmul float %142, %111 %156 = fmul float %133, %154 %157 = fadd float %155, %156 %158 = fsub float 1.000000e+00, %111 %159 = fmul float %143, %111 %160 = fmul float %134, %158 %161 = fadd float %159, %160 %162 = fsub float 1.000000e+00, %111 %163 = fmul float %144, %111 %164 = fmul float %135, %162 %165 = fadd float %163, %164 %166 = fmul float %157, %104 %167 = fmul float %161, %105 %168 = fmul float %165, %106 %169 = fmul float %136, %107 %170 = fmul float %150, %31 %171 = fmul float %151, %32 %172 = fmul float %152, %33 %173 = fcmp ogt float %153, -0.000000e+00 %174 = bitcast float %84 to i32 %175 = icmp ne i32 %174, 0 %176 = and i1 %173, %175 br i1 %176, label %IF, label %ENDIF IF: ; preds = %main_body %177 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %178 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %179 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %180 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %181 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %182 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %183 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %184 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %185 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %186 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %187 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %188 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %189 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %190 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %191 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %192 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %193 = fmul float %150, 0x3FCB333340000000 %194 = fmul float %151, 0x3FE6E48E80000000 %195 = fadd float %194, %193 %196 = fmul float %152, 0x3FB2752540000000 %197 = fadd float %195, %196 %198 = fdiv float 1.000000e+00, %197 %199 = fmul float %198, %153 %200 = fadd float %120, 0.000000e+00 %201 = fadd float %121, 0.000000e+00 %202 = fadd float %122, 0.000000e+00 %203 = fmul float %120, 0.000000e+00 %204 = fadd float %203, 1.000000e+00 %205 = fmul float %200, %192 %206 = fmul float %201, %191 %207 = fadd float %205, %206 %208 = fmul float %202, %190 %209 = fadd float %207, %208 %210 = fmul float %204, %189 %211 = fadd float %209, %210 %212 = fmul float %200, %188 %213 = fmul float %201, %187 %214 = fadd float %212, %213 %215 = fmul float %202, %186 %216 = fadd float %214, %215 %217 = fmul float %204, %185 %218 = fadd float %216, %217 %219 = call float @llvm.AMDIL.clamp.(float %211, float 0.000000e+00, float 1.000000e+00) %220 = call float @llvm.AMDIL.clamp.(float %218, float 0.000000e+00, float 1.000000e+00) %221 = fsub float %219, %211 %222 = fsub float %220, %218 %223 = fadd float %221, %222 %224 = fmul float %200, %45 %225 = fmul float %201, %46 %226 = fadd float %224, %225 %227 = fmul float %202, %47 %228 = fadd float %226, %227 %229 = fmul float %204, %48 %230 = fadd float %228, %229 %231 = fmul float %200, %49 %232 = fmul float %201, %50 %233 = fadd float %231, %232 %234 = fmul float %202, %51 %235 = fadd float %233, %234 %236 = fmul float %204, %52 %237 = fadd float %235, %236 %238 = call float @llvm.AMDIL.clamp.(float %230, float 0.000000e+00, float 1.000000e+00) %239 = call float @llvm.AMDIL.clamp.(float %237, float 0.000000e+00, float 1.000000e+00) %240 = fsub float %238, %230 %241 = fsub float %239, %237 %242 = fadd float %240, %241 %243 = fmul float %200, %53 %244 = fmul float %201, %54 %245 = fadd float %243, %244 %246 = fmul float %202, %55 %247 = fadd float %245, %246 %248 = fmul float %204, %56 %249 = fadd float %247, %248 %250 = fmul float %200, %57 %251 = fmul float %201, %58 %252 = fadd float %250, %251 %253 = fmul float %202, %59 %254 = fadd float %252, %253 %255 = fmul float %204, %60 %256 = fadd float %254, %255 %257 = call float @llvm.fabs.f32(float %242) %258 = fcmp ole float %257, -0.000000e+00 %. = select i1 %258, float %230, float %249 %259 = call float @llvm.fabs.f32(float %242) %260 = fcmp ole float %259, -0.000000e+00 %temp36.0 = select i1 %260, float %237, float %256 %261 = call float @llvm.fabs.f32(float %242) %262 = fcmp ole float %261, -0.000000e+00 %.240 = select i1 %262, float 1.000000e+00, float 2.000000e+00 %263 = call float @llvm.fabs.f32(float %223) %264 = fcmp ole float %263, -0.000000e+00 %temp36.2 = select i1 %264, float %211, float %. %265 = call float @llvm.fabs.f32(float %223) %266 = fcmp ole float %265, -0.000000e+00 %.temp36.0 = select i1 %266, float %218, float %temp36.0 %267 = call float @llvm.fabs.f32(float %223) %268 = fcmp ole float %267, -0.000000e+00 %temp24.1 = select i1 %268, float 0.000000e+00, float %.240 %269 = fmul float %200, %184 %270 = fmul float %201, %183 %271 = fadd float %269, %270 %272 = fmul float %202, %182 %273 = fadd float %271, %272 %274 = fmul float %204, %181 %275 = fadd float %273, %274 %276 = fadd float %temp36.2, -5.000000e-01 %277 = fadd float %.temp36.0, -5.000000e-01 %278 = call float @llvm.fabs.f32(float %276) %279 = call float @llvm.fabs.f32(float %277) %280 = fsub float %278, %41 %281 = fsub float %279, %41 %282 = fmul float %280, %42 %283 = fmul float %281, %42 %284 = call float @llvm.AMDIL.clamp.(float %282, float 0.000000e+00, float 1.000000e+00) %285 = call float @llvm.AMDIL.clamp.(float %283, float 0.000000e+00, float 1.000000e+00) %286 = fsub float 1.000000e+00, %284 %287 = fsub float 1.000000e+00, %285 %288 = fmul float %287, %286 %289 = call float @llvm.AMDIL.clamp.(float %temp36.2, float 0.000000e+00, float 1.000000e+00) %290 = call float @llvm.AMDIL.clamp.(float %.temp36.0, float 0.000000e+00, float 1.000000e+00) %291 = fadd float %temp24.1, -1.000000e+00 %292 = fadd float %temp24.1, -2.000000e+00 %293 = call float @llvm.fabs.f32(float %temp24.1) %294 = fcmp ole float %293, -0.000000e+00 %.241 = select i1 %294, float %178, float 0.000000e+00 %295 = call float @llvm.fabs.f32(float %temp24.1) %296 = fcmp ole float %295, -0.000000e+00 %temp60.0 = select i1 %296, float %177, float 0.000000e+00 %297 = call float @llvm.fabs.f32(float %temp24.1) %298 = fcmp ole float %297, -0.000000e+00 %.242 = select i1 %298, float %180, float 0.000000e+00 %299 = call float @llvm.fabs.f32(float %temp24.1) %300 = fcmp ole float %299, -0.000000e+00 %temp60.2 = select i1 %300, float %179, float 0.000000e+00 %301 = call float @llvm.fabs.f32(float %291) %302 = fcmp ole float %301, -0.000000e+00 %..241 = select i1 %302, float %71, float %.241 %303 = call float @llvm.fabs.f32(float %291) %304 = fcmp ole float %303, -0.000000e+00 %temp56.2 = select i1 %304, float %72, float %temp60.0 %305 = call float @llvm.fabs.f32(float %291) %306 = fcmp ole float %305, -0.000000e+00 %..242 = select i1 %306, float %69, float %.242 %307 = call float @llvm.fabs.f32(float %291) %308 = fcmp ole float %307, -0.000000e+00 %temp56.4 = select i1 %308, float %70, float %temp60.2 %309 = call float @llvm.fabs.f32(float %292) %310 = fcmp ole float %309, -0.000000e+00 %...241 = select i1 %310, float %75, float %..241 %311 = call float @llvm.fabs.f32(float %292) %312 = fcmp ole float %311, -0.000000e+00 %temp56.6 = select i1 %312, float %76, float %temp56.2 %313 = call float @llvm.fabs.f32(float %292) %314 = fcmp ole float %313, -0.000000e+00 %...242 = select i1 %314, float %73, float %..242 %315 = call float @llvm.fabs.f32(float %292) %316 = fcmp ole float %315, -0.000000e+00 %temp56.8 = select i1 %316, float %74, float %temp56.4 %317 = fmul float %289, %...241 %318 = fadd float %317, %...242 %319 = fmul float %290, %temp56.6 %320 = fadd float %319, %temp56.8 %321 = fadd float %318, 0x3F40000000000000 %322 = fadd float %320, 0x3F40000000000000 %323 = fadd float %275, 0.000000e+00 %324 = bitcast float %323 to i32 %325 = bitcast float %321 to i32 %326 = bitcast float %322 to i32 %327 = insertelement <4 x i32> undef, i32 %324, i32 0 %328 = insertelement <4 x i32> %327, i32 %325, i32 1 %329 = insertelement <4 x i32> %328, i32 %326, i32 2 %330 = insertelement <4 x i32> %329, i32 0, i32 3 %331 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %330, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %332 = extractelement <4 x float> %331, i32 0 %333 = fadd float %318, 0xBF40000000000000 %334 = fadd float %320, 0x3F40000000000000 %335 = fadd float %275, 0.000000e+00 %336 = fadd float %318, 0x3F40000000000000 %337 = fadd float %320, 0xBF40000000000000 %338 = fadd float %275, 0.000000e+00 %339 = fadd float %318, 0xBF40000000000000 %340 = fadd float %320, 0xBF40000000000000 %341 = fadd float %275, 0.000000e+00 %342 = bitcast float %335 to i32 %343 = bitcast float %333 to i32 %344 = bitcast float %334 to i32 %345 = insertelement <4 x i32> undef, i32 %342, i32 0 %346 = insertelement <4 x i32> %345, i32 %343, i32 1 %347 = insertelement <4 x i32> %346, i32 %344, i32 2 %348 = insertelement <4 x i32> %347, i32 0, i32 3 %349 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %348, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %350 = extractelement <4 x float> %349, i32 0 %351 = bitcast float %338 to i32 %352 = bitcast float %336 to i32 %353 = bitcast float %337 to i32 %354 = insertelement <4 x i32> undef, i32 %351, i32 0 %355 = insertelement <4 x i32> %354, i32 %352, i32 1 %356 = insertelement <4 x i32> %355, i32 %353, i32 2 %357 = insertelement <4 x i32> %356, i32 0, i32 3 %358 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %357, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %359 = extractelement <4 x float> %358, i32 0 %360 = bitcast float %341 to i32 %361 = bitcast float %339 to i32 %362 = bitcast float %340 to i32 %363 = insertelement <4 x i32> undef, i32 %360, i32 0 %364 = insertelement <4 x i32> %363, i32 %361, i32 1 %365 = insertelement <4 x i32> %364, i32 %362, i32 2 %366 = insertelement <4 x i32> %365, i32 0, i32 3 %367 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %366, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %368 = extractelement <4 x float> %367, i32 0 %369 = fmul float %332, 6.250000e-02 %370 = fmul float %350, 6.250000e-02 %371 = fadd float %369, %370 %372 = fmul float %359, 6.250000e-02 %373 = fadd float %371, %372 %374 = fmul float %368, 6.250000e-02 %375 = fadd float %373, %374 %376 = fadd float %318, 0x3F40000000000000 %377 = fadd float %320, 0.000000e+00 %378 = fadd float %275, 0.000000e+00 %379 = bitcast float %378 to i32 %380 = bitcast float %376 to i32 %381 = bitcast float %377 to i32 %382 = insertelement <4 x i32> undef, i32 %379, i32 0 %383 = insertelement <4 x i32> %382, i32 %380, i32 1 %384 = insertelement <4 x i32> %383, i32 %381, i32 2 %385 = insertelement <4 x i32> %384, i32 0, i32 3 %386 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %385, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %387 = extractelement <4 x float> %386, i32 0 %388 = fadd float %318, 0xBF40000000000000 %389 = fadd float %320, 0.000000e+00 %390 = fadd float %275, 0.000000e+00 %391 = bitcast float %390 to i32 %392 = bitcast float %388 to i32 %393 = bitcast float %389 to i32 %394 = insertelement <4 x i32> undef, i32 %391, i32 0 %395 = insertelement <4 x i32> %394, i32 %392, i32 1 %396 = insertelement <4 x i32> %395, i32 %393, i32 2 %397 = insertelement <4 x i32> %396, i32 0, i32 3 %398 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %397, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %399 = extractelement <4 x float> %398, i32 0 %400 = fadd float %318, 0.000000e+00 %401 = fadd float %320, 0xBF40000000000000 %402 = fadd float %275, 0.000000e+00 %403 = bitcast float %402 to i32 %404 = bitcast float %400 to i32 %405 = bitcast float %401 to i32 %406 = insertelement <4 x i32> undef, i32 %403, i32 0 %407 = insertelement <4 x i32> %406, i32 %404, i32 1 %408 = insertelement <4 x i32> %407, i32 %405, i32 2 %409 = insertelement <4 x i32> %408, i32 0, i32 3 %410 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %409, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %411 = extractelement <4 x float> %410, i32 0 %412 = fadd float %318, 0.000000e+00 %413 = fadd float %320, 0x3F40000000000000 %414 = fadd float %275, 0.000000e+00 %415 = bitcast float %414 to i32 %416 = bitcast float %412 to i32 %417 = bitcast float %413 to i32 %418 = insertelement <4 x i32> undef, i32 %415, i32 0 %419 = insertelement <4 x i32> %418, i32 %416, i32 1 %420 = insertelement <4 x i32> %419, i32 %417, i32 2 %421 = insertelement <4 x i32> %420, i32 0, i32 3 %422 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %421, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %423 = extractelement <4 x float> %422, i32 0 %424 = fmul float %387, 1.250000e-01 %425 = fmul float %399, 1.250000e-01 %426 = fadd float %424, %425 %427 = fmul float %411, 1.250000e-01 %428 = fadd float %426, %427 %429 = fmul float %423, 1.250000e-01 %430 = fadd float %428, %429 %431 = bitcast float %275 to i32 %432 = bitcast float %318 to i32 %433 = bitcast float %320 to i32 %434 = insertelement <4 x i32> undef, i32 %431, i32 0 %435 = insertelement <4 x i32> %434, i32 %432, i32 1 %436 = insertelement <4 x i32> %435, i32 %433, i32 2 %437 = insertelement <4 x i32> %436, i32 0, i32 3 %438 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %437, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %439 = extractelement <4 x float> %438, i32 0 %440 = fadd float %430, %375 %441 = fmul float %439, 2.500000e-01 %442 = fadd float %441, %440 %443 = fcmp olt float %288, 1.000000e+00 br i1 %443, label %IF127, label %ENDIF126 ENDIF: ; preds = %main_body, %ENDIF126 %temp2.0 = phi float [ %738, %ENDIF126 ], [ %172, %main_body ] %temp1.0 = phi float [ %734, %ENDIF126 ], [ %171, %main_body ] %temp.0 = phi float [ %730, %ENDIF126 ], [ %170, %main_body ] %444 = fadd float %temp.0, %38 %445 = fadd float %temp1.0, %39 %446 = fadd float %temp2.0, %40 %447 = fmul float %166, %444 %448 = fmul float %167, %445 %449 = fmul float %168, %446 %450 = fsub float %25, %120 %451 = fsub float %26, %121 %452 = fsub float %27, %122 %453 = fmul float %450, %450 %454 = fmul float %451, %451 %455 = fadd float %454, %453 %456 = fmul float %452, %452 %457 = fadd float %455, %456 %458 = call float @llvm.sqrt.f32(float %457) %459 = fmul float %458, %30 %460 = fadd float %459, %28 %461 = call float @llvm.AMDIL.clamp.(float %460, float 0.000000e+00, float 1.000000e+00) %462 = call float @llvm.minnum.f32(float %461, float %29) %463 = fmul float %447, %37 %464 = fmul float %448, %37 %465 = fmul float %449, %37 %466 = fmul float %462, %462 %467 = fmul float %37, %447 %468 = fsub float %34, %467 %469 = fmul float %37, %448 %470 = fsub float %35, %469 %471 = fmul float %37, %449 %472 = fsub float %36, %471 %473 = fmul float %466, %468 %474 = fadd float %473, %463 %475 = fmul float %466, %470 %476 = fadd float %475, %464 %477 = fmul float %466, %472 %478 = fadd float %477, %465 %479 = call i32 @llvm.SI.packf16(float %474, float %476) %480 = bitcast i32 %479 to float %481 = call i32 @llvm.SI.packf16(float %478, float %169) %482 = bitcast i32 %481 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %480, float %482, float %480, float %482) ret void IF127: ; preds = %IF %483 = fadd float %temp24.1, 0.000000e+00 %484 = fadd float %temp24.1, -1.000000e+00 %485 = fadd float %temp24.1, -2.000000e+00 %486 = call float @llvm.fabs.f32(float %483) %487 = fcmp ole float %486, -0.000000e+00 %.243 = select i1 %487, float %45, float 0.000000e+00 %488 = call float @llvm.fabs.f32(float %483) %489 = fcmp ole float %488, -0.000000e+00 %temp60.5 = select i1 %489, float %46, float 0.000000e+00 %490 = call float @llvm.fabs.f32(float %483) %491 = fcmp ole float %490, -0.000000e+00 %.244 = select i1 %491, float %47, float 0.000000e+00 %492 = call float @llvm.fabs.f32(float %483) %493 = fcmp ole float %492, -0.000000e+00 %temp60.7 = select i1 %493, float %48, float 0.000000e+00 %494 = call float @llvm.fabs.f32(float %483) %495 = fcmp ole float %494, -0.000000e+00 %.245 = select i1 %495, float %49, float 0.000000e+00 %496 = call float @llvm.fabs.f32(float %483) %497 = fcmp ole float %496, -0.000000e+00 %temp60.9 = select i1 %497, float %50, float 0.000000e+00 %498 = call float @llvm.fabs.f32(float %483) %499 = fcmp ole float %498, -0.000000e+00 %.246 = select i1 %499, float %51, float 0.000000e+00 %500 = call float @llvm.fabs.f32(float %483) %501 = fcmp ole float %500, -0.000000e+00 %temp60.11 = select i1 %501, float %52, float 0.000000e+00 %502 = call float @llvm.fabs.f32(float %484) %503 = fcmp ole float %502, -0.000000e+00 %..243 = select i1 %503, float %53, float %.243 %504 = call float @llvm.fabs.f32(float %484) %505 = fcmp ole float %504, -0.000000e+00 %temp60.13 = select i1 %505, float %54, float %temp60.5 %506 = call float @llvm.fabs.f32(float %484) %507 = fcmp ole float %506, -0.000000e+00 %..244 = select i1 %507, float %55, float %.244 %508 = call float @llvm.fabs.f32(float %484) %509 = fcmp ole float %508, -0.000000e+00 %temp60.15 = select i1 %509, float %56, float %temp60.7 %510 = call float @llvm.fabs.f32(float %484) %511 = fcmp ole float %510, -0.000000e+00 %..245 = select i1 %511, float %57, float %.245 %512 = call float @llvm.fabs.f32(float %484) %513 = fcmp ole float %512, -0.000000e+00 %temp60.17 = select i1 %513, float %58, float %temp60.9 %514 = call float @llvm.fabs.f32(float %484) %515 = fcmp ole float %514, -0.000000e+00 %..246 = select i1 %515, float %59, float %.246 %516 = call float @llvm.fabs.f32(float %484) %517 = fcmp ole float %516, -0.000000e+00 %temp60.19 = select i1 %517, float %60, float %temp60.11 %518 = call float @llvm.fabs.f32(float %485) %519 = fcmp ole float %518, -0.000000e+00 %...243 = select i1 %519, float %61, float %..243 %520 = call float @llvm.fabs.f32(float %485) %521 = fcmp ole float %520, -0.000000e+00 %temp60.21 = select i1 %521, float %62, float %temp60.13 %522 = call float @llvm.fabs.f32(float %485) %523 = fcmp ole float %522, -0.000000e+00 %...244 = select i1 %523, float %63, float %..244 %524 = call float @llvm.fabs.f32(float %485) %525 = fcmp ole float %524, -0.000000e+00 %temp60.23 = select i1 %525, float %64, float %temp60.15 %526 = call float @llvm.fabs.f32(float %485) %527 = fcmp ole float %526, -0.000000e+00 %...245 = select i1 %527, float %65, float %..245 %528 = call float @llvm.fabs.f32(float %485) %529 = fcmp ole float %528, -0.000000e+00 %temp60.25 = select i1 %529, float %66, float %temp60.17 %530 = call float @llvm.fabs.f32(float %485) %531 = fcmp ole float %530, -0.000000e+00 %...246 = select i1 %531, float %67, float %..246 %532 = call float @llvm.fabs.f32(float %485) %533 = fcmp ole float %532, -0.000000e+00 %temp60.27 = select i1 %533, float %68, float %temp60.19 %534 = fmul float %200, %...243 %535 = fmul float %201, %temp60.21 %536 = fadd float %534, %535 %537 = fmul float %202, %...244 %538 = fadd float %536, %537 %539 = fmul float %204, %temp60.23 %540 = fadd float %538, %539 %541 = call float @llvm.AMDIL.clamp.(float %540, float 0.000000e+00, float 1.000000e+00) %542 = fmul float %200, %...245 %543 = fmul float %201, %temp60.25 %544 = fadd float %542, %543 %545 = fmul float %202, %...246 %546 = fadd float %544, %545 %547 = fmul float %204, %temp60.27 %548 = fadd float %546, %547 %549 = call float @llvm.AMDIL.clamp.(float %548, float 0.000000e+00, float 1.000000e+00) %550 = call float @llvm.fabs.f32(float %483) %551 = fcmp ole float %550, -0.000000e+00 %.247 = select i1 %551, float %71, float 0.000000e+00 %552 = call float @llvm.fabs.f32(float %483) %553 = fcmp ole float %552, -0.000000e+00 %temp64.0 = select i1 %553, float %72, float 0.000000e+00 %554 = call float @llvm.fabs.f32(float %483) %555 = fcmp ole float %554, -0.000000e+00 %.248 = select i1 %555, float %69, float 0.000000e+00 %556 = call float @llvm.fabs.f32(float %483) %557 = fcmp ole float %556, -0.000000e+00 %temp64.2 = select i1 %557, float %70, float 0.000000e+00 %558 = call float @llvm.fabs.f32(float %484) %559 = fcmp ole float %558, -0.000000e+00 %..247 = select i1 %559, float %75, float %.247 %560 = call float @llvm.fabs.f32(float %484) %561 = fcmp ole float %560, -0.000000e+00 %temp60.29 = select i1 %561, float %76, float %temp64.0 %562 = call float @llvm.fabs.f32(float %484) %563 = fcmp ole float %562, -0.000000e+00 %..248 = select i1 %563, float %73, float %.248 %564 = call float @llvm.fabs.f32(float %484) %565 = fcmp ole float %564, -0.000000e+00 %temp60.31 = select i1 %565, float %74, float %temp64.2 %566 = call float @llvm.fabs.f32(float %485) %567 = fcmp ole float %566, -0.000000e+00 %...247 = select i1 %567, float %79, float %..247 %568 = call float @llvm.fabs.f32(float %485) %569 = fcmp ole float %568, -0.000000e+00 %temp60.33 = select i1 %569, float %80, float %temp60.29 %570 = call float @llvm.fabs.f32(float %485) %571 = fcmp ole float %570, -0.000000e+00 %...248 = select i1 %571, float %77, float %..248 %572 = call float @llvm.fabs.f32(float %485) %573 = fcmp ole float %572, -0.000000e+00 %temp60.35 = select i1 %573, float %78, float %temp60.31 %574 = fmul float %541, %...247 %575 = fadd float %574, %...248 %576 = fmul float %549, %temp60.33 %577 = fadd float %576, %temp60.35 %578 = fadd float %575, 0x3F40000000000000 %579 = fadd float %577, 0x3F40000000000000 %580 = fadd float %275, 0.000000e+00 %581 = bitcast float %580 to i32 %582 = bitcast float %578 to i32 %583 = bitcast float %579 to i32 %584 = insertelement <4 x i32> undef, i32 %581, i32 0 %585 = insertelement <4 x i32> %584, i32 %582, i32 1 %586 = insertelement <4 x i32> %585, i32 %583, i32 2 %587 = insertelement <4 x i32> %586, i32 0, i32 3 %588 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %587, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %589 = extractelement <4 x float> %588, i32 0 %590 = fadd float %575, 0xBF40000000000000 %591 = fadd float %577, 0x3F40000000000000 %592 = fadd float %275, 0.000000e+00 %593 = fadd float %575, 0x3F40000000000000 %594 = fadd float %577, 0xBF40000000000000 %595 = fadd float %275, 0.000000e+00 %596 = fadd float %575, 0xBF40000000000000 %597 = fadd float %577, 0xBF40000000000000 %598 = fadd float %275, 0.000000e+00 %599 = bitcast float %592 to i32 %600 = bitcast float %590 to i32 %601 = bitcast float %591 to i32 %602 = insertelement <4 x i32> undef, i32 %599, i32 0 %603 = insertelement <4 x i32> %602, i32 %600, i32 1 %604 = insertelement <4 x i32> %603, i32 %601, i32 2 %605 = insertelement <4 x i32> %604, i32 0, i32 3 %606 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %605, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %607 = extractelement <4 x float> %606, i32 0 %608 = bitcast float %595 to i32 %609 = bitcast float %593 to i32 %610 = bitcast float %594 to i32 %611 = insertelement <4 x i32> undef, i32 %608, i32 0 %612 = insertelement <4 x i32> %611, i32 %609, i32 1 %613 = insertelement <4 x i32> %612, i32 %610, i32 2 %614 = insertelement <4 x i32> %613, i32 0, i32 3 %615 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %614, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %616 = extractelement <4 x float> %615, i32 0 %617 = bitcast float %598 to i32 %618 = bitcast float %596 to i32 %619 = bitcast float %597 to i32 %620 = insertelement <4 x i32> undef, i32 %617, i32 0 %621 = insertelement <4 x i32> %620, i32 %618, i32 1 %622 = insertelement <4 x i32> %621, i32 %619, i32 2 %623 = insertelement <4 x i32> %622, i32 0, i32 3 %624 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %623, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %625 = extractelement <4 x float> %624, i32 0 %626 = fmul float %589, 6.250000e-02 %627 = fmul float %607, 6.250000e-02 %628 = fadd float %626, %627 %629 = fmul float %616, 6.250000e-02 %630 = fadd float %628, %629 %631 = fmul float %625, 6.250000e-02 %632 = fadd float %630, %631 %633 = fadd float %575, 0x3F40000000000000 %634 = fadd float %577, 0.000000e+00 %635 = fadd float %275, 0.000000e+00 %636 = bitcast float %635 to i32 %637 = bitcast float %633 to i32 %638 = bitcast float %634 to i32 %639 = insertelement <4 x i32> undef, i32 %636, i32 0 %640 = insertelement <4 x i32> %639, i32 %637, i32 1 %641 = insertelement <4 x i32> %640, i32 %638, i32 2 %642 = insertelement <4 x i32> %641, i32 0, i32 3 %643 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %642, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %644 = extractelement <4 x float> %643, i32 0 %645 = fadd float %575, 0xBF40000000000000 %646 = fadd float %577, 0.000000e+00 %647 = fadd float %275, 0.000000e+00 %648 = bitcast float %647 to i32 %649 = bitcast float %645 to i32 %650 = bitcast float %646 to i32 %651 = insertelement <4 x i32> undef, i32 %648, i32 0 %652 = insertelement <4 x i32> %651, i32 %649, i32 1 %653 = insertelement <4 x i32> %652, i32 %650, i32 2 %654 = insertelement <4 x i32> %653, i32 0, i32 3 %655 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %654, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %656 = extractelement <4 x float> %655, i32 0 %657 = fadd float %575, 0.000000e+00 %658 = fadd float %577, 0xBF40000000000000 %659 = fadd float %275, 0.000000e+00 %660 = bitcast float %659 to i32 %661 = bitcast float %657 to i32 %662 = bitcast float %658 to i32 %663 = insertelement <4 x i32> undef, i32 %660, i32 0 %664 = insertelement <4 x i32> %663, i32 %661, i32 1 %665 = insertelement <4 x i32> %664, i32 %662, i32 2 %666 = insertelement <4 x i32> %665, i32 0, i32 3 %667 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %666, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %668 = extractelement <4 x float> %667, i32 0 %669 = fadd float %575, 0.000000e+00 %670 = fadd float %577, 0x3F40000000000000 %671 = fadd float %275, 0.000000e+00 %672 = bitcast float %671 to i32 %673 = bitcast float %669 to i32 %674 = bitcast float %670 to i32 %675 = insertelement <4 x i32> undef, i32 %672, i32 0 %676 = insertelement <4 x i32> %675, i32 %673, i32 1 %677 = insertelement <4 x i32> %676, i32 %674, i32 2 %678 = insertelement <4 x i32> %677, i32 0, i32 3 %679 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %678, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %680 = extractelement <4 x float> %679, i32 0 %681 = fmul float %644, 1.250000e-01 %682 = fmul float %656, 1.250000e-01 %683 = fadd float %681, %682 %684 = fmul float %668, 1.250000e-01 %685 = fadd float %683, %684 %686 = fmul float %680, 1.250000e-01 %687 = fadd float %685, %686 %688 = bitcast float %275 to i32 %689 = bitcast float %575 to i32 %690 = bitcast float %577 to i32 %691 = insertelement <4 x i32> undef, i32 %688, i32 0 %692 = insertelement <4 x i32> %691, i32 %689, i32 1 %693 = insertelement <4 x i32> %692, i32 %690, i32 2 %694 = insertelement <4 x i32> %693, i32 0, i32 3 %695 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %694, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %696 = extractelement <4 x float> %695, i32 0 %697 = fadd float %687, %632 %698 = fmul float %696, 2.500000e-01 %699 = fadd float %698, %697 %700 = fcmp oge float %485, 0.000000e+00 %.249 = select i1 %700, float 1.000000e+00, float %699 %701 = fsub float 1.000000e+00, %288 %702 = fmul float %442, %288 %703 = fmul float %.249, %701 %704 = fadd float %702, %703 br label %ENDIF126 ENDIF126: ; preds = %IF, %IF127 %temp8.0 = phi float [ %704, %IF127 ], [ %442, %IF ] %705 = fsub float %120, %81 %706 = fsub float %121, %82 %707 = fsub float %122, %83 %708 = fmul float %705, %705 %709 = fmul float %706, %706 %710 = fadd float %709, %708 %711 = fmul float %707, %707 %712 = fadd float %710, %711 %713 = fmul float %712, %44 %714 = fadd float %713, %43 %715 = call float @llvm.AMDIL.clamp.(float %714, float 0.000000e+00, float 1.000000e+00) %716 = fsub float 1.000000e+00, %715 %717 = fmul float %temp8.0, %716 %718 = fadd float %715, %717 %719 = fsub float 1.000000e+00, %718 %720 = fmul float %719, %199 %721 = fsub float 1.000000e+00, %720 %722 = fmul float %721, %172 %723 = fmul float %721, %171 %724 = fmul float %721, %170 %725 = fmul float %721, 5.000000e-01 %726 = fadd float %725, 5.000000e-01 %727 = fsub float 1.000000e+00, %726 %728 = fmul float %724, %726 %729 = fmul float %722, %727 %730 = fadd float %728, %729 %731 = fsub float 1.000000e+00, %726 %732 = fmul float %723, %726 %733 = fmul float %723, %731 %734 = fadd float %732, %733 %735 = fsub float 1.000000e+00, %726 %736 = fmul float %722, %726 %737 = fmul float %724, %735 %738 = fadd float %736, %737 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x0 ; C00E0603 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x20 ; C00E0403 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x40 ; C00E0803 00000040 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s11, s[12:15], 0xbc ; C02202C6 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s48, s[12:15], 0xc0 ; C0220C06 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[12:15], 0xc4 ; C0220C46 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[12:15], 0xc8 ; C0220C86 000000C8 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x0 ; C00A0A02 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[44:47], s[4:5], 0x20 ; C00A0B02 00000020 s_and_b32 s9, 1, s9 ; 86090981 v_cmp_eq_i32_e64 vcc, 1, s9 ; D0C2006A 00001281 v_cndmask_b32_e32 v11, v2, v0 ; 00160102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v12, v3, v1 ; 00180303 v_interp_p1_f32 v2, v11, 0, 0, [m0] ; D408000B v_interp_p2_f32 v2, [v2], v12, 0, 0, [m0] ; D409000C v_interp_p1_f32 v3, v11, 1, 0, [m0] ; D40C010B v_interp_p2_f32 v3, [v3], v12, 1, 0, [m0] ; D40D010C v_interp_p1_f32 v6, v11, 2, 0, [m0] ; D418020B v_interp_p2_f32 v6, [v6], v12, 2, 0, [m0] ; D419020C v_interp_p1_f32 v7, v11, 3, 0, [m0] ; D41C030B v_interp_p2_f32 v7, [v7], v12, 3, 0, [m0] ; D41D030C v_interp_p1_f32 v9, v11, 0, 1, [m0] ; D424040B v_interp_p2_f32 v9, [v9], v12, 0, 1, [m0] ; D425040C v_interp_p1_f32 v16, v11, 0, 2, [m0] ; D440080B v_interp_p2_f32 v16, [v16], v12, 0, 2, [m0] ; D441080C v_interp_p1_f32 v17, v11, 1, 2, [m0] ; D444090B v_interp_p2_f32 v17, [v17], v12, 1, 2, [m0] ; D445090C v_interp_p1_f32 v8, v11, 0, 3, [m0] ; D4200C0B v_interp_p2_f32 v8, [v8], v12, 0, 3, [m0] ; D4210C0C v_interp_p1_f32 v10, v11, 1, 3, [m0] ; D4280D0B v_interp_p2_f32 v10, [v10], v12, 1, 3, [m0] ; D4290D0C v_interp_p1_f32 v11, v11, 2, 3, [m0] ; D42C0E0B s_buffer_load_dword s9, s[12:15], 0x5a0 ; C0220246 000005A0 v_interp_p2_f32 v11, [v11], v12, 2, 3, [m0] ; D42D0E0C v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v4, v0, 0, 4, [m0] ; D4101000 v_interp_p2_f32 v4, [v4], v1, 0, 4, [m0] ; D4111001 v_interp_p1_f32 v5, v0, 1, 4, [m0] ; D4141100 v_interp_p2_f32 v5, [v5], v1, 1, 4, [m0] ; D4151101 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[12:15], 15, 0, 0, 0, 0, 0, 0, 0, v[16:17], s[24:31], s[40:43] ; F0800F00 01460C10 s_nop 0 ; BF800000 image_sample v[16:19], 15, 0, 0, 0, 0, 0, 0, 0, v[16:17], s[32:39], s[44:47] ; F0800F00 01681010 s_waitcnt vmcnt(0) ; BF8C0770 image_sample v[19:22], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[16:23], s[0:3] ; F0800F00 00041304 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, s48, v19 ; 0A002630 v_mul_f32_e32 v1, s49, v20 ; 0A022831 v_mul_f32_e32 v4, s50, v21 ; 0A082A32 v_mov_b32_e32 v5, 0x80000000 ; 7E0A02FF 80000000 v_cmp_lt_f32_e32 vcc, v5, v22 ; 7C822D05 v_cmp_ne_i32_e64 s[0:1], 0, s9 ; D0C50000 00001280 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[16:17], s[0:1] ; BE902000 s_xor_b64 s[16:17], exec, s[16:17] ; 8890107E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x440 ; C0220246 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x4a0 ; C0220506 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4a4 ; C0220546 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a8 ; C0220586 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4ac ; C02205C6 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4d0 ; C0220606 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d4 ; C0220646 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d8 ; C02206C6 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4dc ; C0220746 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4e0 ; C02207C6 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e4 ; C0220846 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4e8 ; C0220886 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4ec ; C02208C6 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s56, s[12:15], 0x550 ; C0220E06 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[12:15], 0x554 ; C0220E46 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[12:15], 0x558 ; C0220E86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x570 ; C0220946 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x574 ; C02209C6 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x578 ; C0220A46 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x57c ; C0220AC6 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x590 ; C02204C6 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x594 ; C0220486 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x598 ; C0220286 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x60 ; C00E0B03 00000060 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x30 ; C00A0D02 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[12:15], 0x55c ; C0220EC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x560 ; C0220906 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x564 ; C0220986 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x568 ; C0220A06 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x56c ; C0220A86 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x490 ; C0220686 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x494 ; C0220706 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x498 ; C0220786 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x49c ; C0220806 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v27, 0, v10 ; 02361480 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v23, s66, v27 ; 0A2E3642 v_add_f32_e32 v29, 0, v8 ; 023A1080 v_add_f32_e32 v28, 0, v11 ; 02381680 v_mad_f32 v5, 0, v8, 1.0 ; D1C10005 03CA1080 v_mac_f32_e32 v23, s3, v29 ; 2C2E3A03 v_mac_f32_e32 v23, s67, v28 ; 2C2E3843 v_mac_f32_e32 v23, s68, v5 ; 2C2E0A44 v_mul_f32_e32 v24, s70, v27 ; 0A303646 v_mac_f32_e32 v24, s69, v29 ; 2C303A45 v_mac_f32_e32 v24, s61, v28 ; 2C30383D v_mac_f32_e32 v24, s62, v5 ; 2C300A3E v_add_f32_e64 v25, 0, v23 clamp ; D1018019 00022E80 v_add_f32_e64 v26, 0, v24 clamp ; D101801A 00023080 v_subrev_f32_e32 v25, v23, v25 ; 06323317 v_subrev_f32_e32 v26, v24, v26 ; 06343518 v_add_f32_e32 v25, v26, v25 ; 0232331A v_mul_f32_e32 v26, s28, v27 ; 0A34361C v_mac_f32_e32 v26, s26, v29 ; 2C343A1A v_mac_f32_e32 v26, s30, v28 ; 2C34381E v_mac_f32_e32 v26, s32, v5 ; 2C340A20 v_mul_f32_e32 v30, s21, v27 ; 0A3C3615 v_mac_f32_e32 v30, s20, v29 ; 2C3C3A14 v_mac_f32_e32 v30, s22, v28 ; 2C3C3816 v_mac_f32_e32 v30, s23, v5 ; 2C3C0A17 v_add_f32_e64 v31, 0, v26 clamp ; D101801F 00023480 v_add_f32_e64 v32, 0, v30 clamp ; D1018020 00023C80 v_subrev_f32_e32 v31, v26, v31 ; 063E3F1A v_subrev_f32_e32 v32, v30, v32 ; 0640411E v_add_f32_e32 v31, v32, v31 ; 023E3F20 v_mul_f32_e32 v32, s25, v27 ; 0A403619 v_mac_f32_e32 v32, s24, v29 ; 2C403A18 v_mac_f32_e32 v32, s27, v28 ; 2C40381B v_mac_f32_e32 v32, s29, v5 ; 2C400A1D v_mul_f32_e32 v33, s33, v27 ; 0A423621 v_mac_f32_e32 v33, s31, v29 ; 2C423A1F v_mac_f32_e32 v33, s34, v28 ; 2C423822 v_mac_f32_e32 v33, s35, v5 ; 2C420A23 v_mov_b32_e32 v34, 0x80000000 ; 7E4402FF 80000000 v_cmp_le_f32_e64 vcc, |v31|, v34 ; D043016A 0002451F v_cndmask_b32_e32 v26, v32, v26 ; 00343520 v_cndmask_b32_e32 v30, v33, v30 ; 003C3D21 v_cndmask_b32_e64 v31, 2.0, 1.0, vcc ; D100001F 01A9E4F4 v_cmp_le_f32_e64 vcc, |v25|, v34 ; D043016A 00024519 v_cndmask_b32_e32 v26, v26, v23 ; 00342F1A v_cndmask_b32_e32 v30, v30, v24 ; 003C311E v_cndmask_b32_e64 v33, v31, 0, vcc ; D1000021 01A9011F v_mul_f32_e32 v23, s64, v27 ; 0A2E3640 v_mac_f32_e32 v23, s63, v29 ; 2C2E3A3F v_mac_f32_e32 v23, s65, v28 ; 2C2E3841 v_mac_f32_e32 v23, s60, v5 ; 2C2E0A3C v_add_f32_e64 v31, 0, v26 clamp ; D101801F 00023480 v_add_f32_e64 v32, 0, v30 clamp ; D1018020 00023C80 v_add_f32_e32 v24, -1.0, v33 ; 023042F3 v_add_f32_e32 v25, -2.0, v33 ; 023242F5 v_cmp_le_f32_e64 vcc, |v33|, v34 ; D043016A 00024521 v_mov_b32_e32 v35, s58 ; 7E46023A v_cndmask_b32_e32 v35, 0, v35 ; 00464680 v_mov_b32_e32 v36, s59 ; 7E48023B v_cndmask_b32_e32 v36, 0, v36 ; 00484880 v_mov_b32_e32 v37, s56 ; 7E4A0238 v_cndmask_b32_e32 v37, 0, v37 ; 004A4A80 v_mov_b32_e32 v38, s57 ; 7E4C0239 v_cndmask_b32_e32 v38, 0, v38 ; 004C4C80 v_cmp_le_f32_e64 vcc, |v24|, v34 ; D043016A 00024518 v_mov_b32_e32 v24, s40 ; 7E300228 v_cndmask_b32_e32 v24, v35, v24 ; 00303123 v_mov_b32_e32 v35, s42 ; 7E46022A v_cndmask_b32_e32 v35, v36, v35 ; 00464724 v_mov_b32_e32 v36, s36 ; 7E480224 v_cndmask_b32_e32 v36, v37, v36 ; 00484925 v_mov_b32_e32 v37, s38 ; 7E4A0226 v_cndmask_b32_e32 v37, v38, v37 ; 004A4B26 v_cmp_le_f32_e64 vcc, |v25|, v34 ; D043016A 00024519 v_mov_b32_e32 v25, s41 ; 7E320229 v_cndmask_b32_e32 v34, v24, v25 ; 00443318 v_mov_b32_e32 v24, s43 ; 7E30022B v_cndmask_b32_e32 v35, v35, v24 ; 00463123 v_mov_b32_e32 v24, s37 ; 7E300225 v_cndmask_b32_e32 v24, v36, v24 ; 00303124 v_mov_b32_e32 v25, s39 ; 7E320227 v_cndmask_b32_e32 v25, v37, v25 ; 00323325 v_mac_f32_e32 v24, v34, v31 ; 2C303F22 v_mac_f32_e32 v25, v35, v32 ; 2C324123 v_mov_b32_e32 v31, 0x3a000000 ; 7E3E02FF 3A000000 v_add_f32_e32 v35, v31, v24 ; 0246311F v_add_f32_e32 v36, v31, v25 ; 0248331F v_add_f32_e32 v34, 0, v23 ; 02442E80 s_mov_b32 s56, 0 ; BEB80080 v_mov_b32_e32 v37, s56 ; 7E4A0238 v_mov_b32_e32 v31, 0xba000000 ; 7E3E02FF BA000000 v_add_f32_e32 v32, v31, v24 ; 0240311F v_mov_b32_e32 v38, v34 ; 7E4C0322 v_mov_b32_e32 v39, v35 ; 7E4E0323 v_mov_b32_e32 v40, v36 ; 7E500324 v_mov_b32_e32 v41, v37 ; 7E520325 v_add_f32_e32 v31, v31, v25 ; 023E331F v_mov_b32_e32 v39, v32 ; 7E4E0320 v_mov_b32_e32 v42, v34 ; 7E540322 v_mov_b32_e32 v43, v35 ; 7E560323 v_mov_b32_e32 v44, v36 ; 7E580324 v_mov_b32_e32 v45, v37 ; 7E5A0325 v_mov_b32_e32 v40, v36 ; 7E500324 v_mov_b32_e32 v44, v31 ; 7E58031F v_mov_b32_e32 v41, s56 ; 7E520238 v_mov_b32_e32 v45, s56 ; 7E5A0238 image_sample_c_l v32, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2022 s_nop 0 ; BF800000 image_sample_c_l v46, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB2E26 v_mov_b32_e32 v40, v31 ; 7E50031F image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[44:51], s[52:55] ; F0B00100 01AB2A2A v_mov_b32_e32 v41, s56 ; 7E520238 image_sample_c_l v43, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB2B26 v_add_f32_e32 v40, 0, v25 ; 02503280 v_mov_b32_e32 v47, v34 ; 7E5E0322 v_mov_b32_e32 v48, v35 ; 7E600323 v_mov_b32_e32 v49, v36 ; 7E620324 v_mov_b32_e32 v50, v37 ; 7E640325 v_mov_b32_e32 v49, v40 ; 7E620328 v_add_f32_e32 v35, 0, v24 ; 02463080 v_mov_b32_e32 v50, s56 ; 7E640238 v_mov_b32_e32 v51, v34 ; 7E660322 v_mov_b32_e32 v52, v35 ; 7E680323 v_mov_b32_e32 v53, v36 ; 7E6A0324 v_mov_b32_e32 v54, v37 ; 7E6C0325 image_sample_c_l v44, 1, 0, 0, 0, 0, 0, 0, 0, v[47:50], s[44:51], s[52:55] ; F0B00100 01AB2C2F v_mov_b32_e32 v53, v31 ; 7E6A031F v_mov_b32_e32 v41, s56 ; 7E520238 image_sample_c_l v31, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB1F26 v_mov_b32_e32 v54, s56 ; 7E6C0238 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[51:54], s[44:51], s[52:55] ; F0B00100 01AB2633 v_mov_b32_e32 v37, s56 ; 7E4A0238 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2222 v_mov_b32_e32 v35, 0x3d800000 ; 7E4602FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v36, v35, v46 ; 0A485D23 v_mac_f32_e32 v36, v35, v32 ; 2C484123 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v36, v35, v42 ; 2C485523 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v36, v35, v43 ; 2C485723 v_mov_b32_e32 v32, 0x3e000000 ; 7E4002FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v31, v32, v31 ; 0A3E3F20 v_mac_f32_e32 v31, v32, v44 ; 2C3E5920 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v31, v32, v38 ; 2C3E4D20 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v31, v32, v34 ; 2C3E4520 v_add_f32_e32 v26, -0.5, v26 ; 023434F1 v_add_f32_e32 v30, -0.5, v30 ; 023C3CF1 v_sub_f32_e64 v26, |v26|, s1 ; D102011A 0000031A v_sub_f32_e64 v30, |v30|, s1 ; D102011E 0000031E v_mul_f32_e32 v26, s2, v26 ; 0A343402 v_mul_f32_e32 v30, s2, v30 ; 0A3C3C02 v_add_f32_e64 v26, 0, v26 clamp ; D101801A 00023480 v_add_f32_e64 v30, 0, v30 clamp ; D101801E 00023C80 v_sub_f32_e32 v26, 1.0, v26 ; 043434F2 v_mad_f32 v32, -v30, v26, v26 ; D1C10020 246A351E v_mov_b32_e32 v26, 0 ; 7E340280 v_add_f32_e32 v30, v36, v31 ; 023C3F24 image_sample_c_l v24, 1, 0, 0, 0, 0, 0, 0, 0, v[23:26], s[44:51], s[52:55] ; F0B00100 01AB1817 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v30, v24, v30, 0x3e800000 ; 2E3C3D18 3E800000 v_mov_b32_e32 v31, s0 ; 7E3E0200 v_cmp_gt_f32_e32 vcc, 1.0, v32 ; 7C8840F2 s_and_saveexec_b64 s[58:59], vcc ; BEBA206A s_xor_b64 s[58:59], exec, s[58:59] ; 88BA3A7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s57, s[12:15], 0x510 ; C0220E46 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x514 ; C0220F06 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x518 ; C0220F46 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x51c ; C0220F86 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x520 ; C0220FC6 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x524 ; C0221006 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x528 ; C0221046 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x52c ; C0221086 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x580 ; C02210C6 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x584 ; C0221106 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x588 ; C0221146 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x58c ; C0221186 0000058C v_mov_b32_e32 v24, s26 ; 7E30021A v_mov_b32_e32 v25, s28 ; 7E32021C v_mov_b32_e32 v26, s30 ; 7E34021E v_mov_b32_e32 v34, s32 ; 7E440220 v_mov_b32_e32 v35, s20 ; 7E460214 v_mov_b32_e32 v36, s21 ; 7E480215 v_mov_b32_e32 v37, s22 ; 7E4A0216 v_mov_b32_e32 v38, s23 ; 7E4C0217 v_mov_b32_e32 v39, s24 ; 7E4E0218 v_mov_b32_e32 v40, s25 ; 7E500219 v_mov_b32_e32 v41, s27 ; 7E52021B v_add_f32_e32 v42, 0, v33 ; 02544280 v_mov_b32_e32 v43, 0x80000000 ; 7E5602FF 80000000 v_cmp_le_f32_e64 vcc, |v42|, v43 ; D043016A 0002572A v_add_f32_e32 v42, -1.0, v33 ; 025442F3 v_cmp_le_f32_e64 s[0:1], |v42|, v43 ; D0430100 0002572A v_mov_b32_e32 v42, s29 ; 7E54021D v_cndmask_b32_e32 v24, 0, v24 ; 00303080 v_cndmask_b32_e64 v24, v24, v39, s[0:1] ; D1000018 00024F18 v_mov_b32_e32 v39, s31 ; 7E4E021F v_cndmask_b32_e32 v25, 0, v25 ; 00323280 v_cndmask_b32_e64 v25, v25, v40, s[0:1] ; D1000019 00025119 v_mov_b32_e32 v40, s33 ; 7E500221 v_cndmask_b32_e32 v26, 0, v26 ; 00343480 v_cndmask_b32_e64 v26, v26, v41, s[0:1] ; D100001A 0002531A v_mov_b32_e32 v41, s34 ; 7E520222 v_cndmask_b32_e32 v34, 0, v34 ; 00444480 v_cndmask_b32_e64 v34, v34, v42, s[0:1] ; D1000022 00025522 v_mov_b32_e32 v42, s35 ; 7E540223 v_cndmask_b32_e32 v35, 0, v35 ; 00464680 v_cndmask_b32_e64 v35, v35, v39, s[0:1] ; D1000023 00024F23 v_mov_b32_e32 v39, s36 ; 7E4E0224 v_cndmask_b32_e32 v36, 0, v36 ; 00484880 v_cndmask_b32_e64 v36, v36, v40, s[0:1] ; D1000024 00025124 v_mov_b32_e32 v40, s38 ; 7E500226 v_cndmask_b32_e32 v37, 0, v37 ; 004A4A80 v_cndmask_b32_e64 v37, v37, v41, s[0:1] ; D1000025 00025325 v_mov_b32_e32 v41, s40 ; 7E520228 v_cndmask_b32_e32 v38, 0, v38 ; 004C4C80 v_cndmask_b32_e64 v38, v38, v42, s[0:1] ; D1000026 00025526 v_mov_b32_e32 v42, s42 ; 7E54022A v_add_f32_e32 v33, -2.0, v33 ; 024242F5 v_cmp_le_f32_e64 s[2:3], |v33|, v43 ; D0430102 00025721 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v43, s57 ; 7E560239 v_cndmask_b32_e64 v24, v24, v43, s[2:3] ; D1000018 000A5718 v_mov_b32_e32 v43, s60 ; 7E56023C v_cndmask_b32_e64 v25, v25, v43, s[2:3] ; D1000019 000A5719 v_mov_b32_e32 v43, s61 ; 7E56023D v_cndmask_b32_e64 v26, v26, v43, s[2:3] ; D100001A 000A571A v_mov_b32_e32 v43, s62 ; 7E56023E v_cndmask_b32_e64 v34, v34, v43, s[2:3] ; D1000022 000A5722 v_mov_b32_e32 v43, s63 ; 7E56023F v_cndmask_b32_e64 v35, v35, v43, s[2:3] ; D1000023 000A5723 v_mov_b32_e32 v43, s64 ; 7E560240 v_cndmask_b32_e64 v36, v36, v43, s[2:3] ; D1000024 000A5724 v_mov_b32_e32 v43, s65 ; 7E560241 v_cndmask_b32_e64 v37, v37, v43, s[2:3] ; D1000025 000A5725 v_mov_b32_e32 v43, s66 ; 7E560242 v_cndmask_b32_e64 v38, v38, v43, s[2:3] ; D1000026 000A5726 v_mov_b32_e32 v43, s37 ; 7E560225 v_mul_f32_e32 v25, v25, v27 ; 0A323719 v_mac_f32_e32 v25, v24, v29 ; 2C323B18 v_mov_b32_e32 v24, s39 ; 7E300227 v_mac_f32_e32 v25, v26, v28 ; 2C32391A v_mov_b32_e32 v26, s41 ; 7E340229 v_mac_f32_e32 v25, v34, v5 ; 2C320B22 v_mov_b32_e32 v34, s43 ; 7E44022B v_add_f32_e64 v44, 0, v25 clamp ; D101802C 00023280 v_mul_f32_e32 v25, v36, v27 ; 0A323724 v_mac_f32_e32 v25, v35, v29 ; 2C323B23 v_mac_f32_e32 v25, v37, v28 ; 2C323925 v_mac_f32_e32 v25, v38, v5 ; 2C320B26 v_add_f32_e64 v5, 0, v25 clamp ; D1018005 00023280 v_cndmask_b32_e32 v25, 0, v41 ; 00325280 v_cndmask_b32_e32 v27, 0, v42 ; 00365480 v_cndmask_b32_e32 v28, 0, v39 ; 00384E80 v_cndmask_b32_e32 v29, 0, v40 ; 003A5080 v_cndmask_b32_e64 v25, v25, v26, s[0:1] ; D1000019 00023519 v_cndmask_b32_e64 v26, v27, v34, s[0:1] ; D100001A 0002451B v_cndmask_b32_e64 v27, v28, v43, s[0:1] ; D100001B 0002571C v_cndmask_b32_e64 v28, v29, v24, s[0:1] ; D100001C 0002311D v_mov_b32_e32 v24, s69 ; 7E300245 v_cndmask_b32_e64 v29, v25, v24, s[2:3] ; D100001D 000A3119 v_mov_b32_e32 v24, s70 ; 7E300246 v_cndmask_b32_e64 v26, v26, v24, s[2:3] ; D100001A 000A311A v_mov_b32_e32 v24, s67 ; 7E300243 v_cndmask_b32_e64 v24, v27, v24, s[2:3] ; D1000018 000A311B v_mov_b32_e32 v25, s68 ; 7E320244 v_cndmask_b32_e64 v25, v28, v25, s[2:3] ; D1000019 000A331C v_mac_f32_e32 v24, v29, v44 ; 2C30591D v_mac_f32_e32 v25, v26, v5 ; 2C320B1A v_mov_b32_e32 v5, 0x3a000000 ; 7E0A02FF 3A000000 v_add_f32_e32 v27, v5, v24 ; 02363105 v_add_f32_e32 v28, v5, v25 ; 02383305 v_add_f32_e32 v26, 0, v23 ; 02342E80 v_mov_b32_e32 v29, s56 ; 7E3A0238 v_mov_b32_e32 v5, 0xba000000 ; 7E0A02FF BA000000 v_add_f32_e32 v34, v5, v24 ; 02443105 v_mov_b32_e32 v35, v26 ; 7E46031A v_mov_b32_e32 v36, v27 ; 7E48031B v_mov_b32_e32 v37, v28 ; 7E4A031C v_mov_b32_e32 v38, v29 ; 7E4C031D v_mov_b32_e32 v36, v34 ; 7E480322 v_add_f32_e32 v5, v5, v25 ; 020A3305 v_mov_b32_e32 v37, v28 ; 7E4A031C v_mov_b32_e32 v39, v26 ; 7E4E031A v_mov_b32_e32 v40, v27 ; 7E50031B v_mov_b32_e32 v41, v28 ; 7E52031C v_mov_b32_e32 v42, v29 ; 7E54031D image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[26:29], s[44:51], s[52:55] ; F0B00100 01AB221A v_mov_b32_e32 v38, s56 ; 7E4C0238 v_mov_b32_e32 v41, v5 ; 7E520305 image_sample_c_l v43, 1, 0, 0, 0, 0, 0, 0, 0, v[35:38], s[44:51], s[52:55] ; F0B00100 01AB2B23 v_mov_b32_e32 v42, s56 ; 7E540238 v_mov_b32_e32 v37, v5 ; 7E4A0305 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[52:55] ; F0B00100 01AB2727 v_mov_b32_e32 v38, s56 ; 7E4C0238 image_sample_c_l v40, 1, 0, 0, 0, 0, 0, 0, 0, v[35:38], s[44:51], s[52:55] ; F0B00100 01AB2823 v_add_f32_e32 v37, 0, v25 ; 024A3280 v_mov_b32_e32 v44, v26 ; 7E58031A v_mov_b32_e32 v45, v27 ; 7E5A031B v_mov_b32_e32 v46, v28 ; 7E5C031C v_mov_b32_e32 v47, v29 ; 7E5E031D v_mov_b32_e32 v46, v37 ; 7E5C0325 v_add_f32_e32 v27, 0, v24 ; 02363080 v_mov_b32_e32 v47, s56 ; 7E5E0238 v_mov_b32_e32 v48, v26 ; 7E60031A v_mov_b32_e32 v49, v27 ; 7E62031B v_mov_b32_e32 v50, v28 ; 7E64031C v_mov_b32_e32 v51, v29 ; 7E66031D image_sample_c_l v41, 1, 0, 0, 0, 0, 0, 0, 0, v[44:47], s[44:51], s[52:55] ; F0B00100 01AB292C v_mov_b32_e32 v50, v5 ; 7E640305 v_mov_b32_e32 v38, s56 ; 7E4C0238 image_sample_c_l v5, 1, 0, 0, 0, 0, 0, 0, 0, v[35:38], s[44:51], s[52:55] ; F0B00100 01AB0523 v_mov_b32_e32 v51, s56 ; 7E660238 image_sample_c_l v35, 1, 0, 0, 0, 0, 0, 0, 0, v[48:51], s[44:51], s[52:55] ; F0B00100 01AB2330 v_mov_b32_e32 v29, s56 ; 7E3A0238 image_sample_c_l v27, 1, 0, 0, 0, 0, 0, 0, 0, v[26:29], s[44:51], s[52:55] ; F0B00100 01AB1B1A v_mov_b32_e32 v26, 0 ; 7E340280 image_sample_c_l v23, 1, 0, 0, 0, 0, 0, 0, 0, v[23:26], s[44:51], s[52:55] ; F0B00100 01AB1717 v_mov_b32_e32 v24, 0x3d800000 ; 7E3002FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v25, v24, v43 ; 0A325718 v_mac_f32_e32 v25, v24, v34 ; 2C324518 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v25, v24, v39 ; 2C324F18 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v25, v24, v40 ; 2C325118 v_mov_b32_e32 v24, 0x3e000000 ; 7E3002FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v5, v24, v5 ; 0A0A0B18 v_mac_f32_e32 v5, v24, v41 ; 2C0A5318 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v5, v24, v35 ; 2C0A4718 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v5, v24, v27 ; 2C0A3718 v_add_f32_e32 v5, v25, v5 ; 020A0B19 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v5, v23, v5, 0x3e800000 ; 2E0A0B17 3E800000 v_cmp_le_f32_e32 vcc, 0, v33 ; 7C864280 v_cndmask_b32_e64 v5, v5, 1.0, vcc ; D1000005 01A9E505 v_mad_f32 v5, -v32, v5, v5 ; D1C10005 24160B20 v_mac_f32_e32 v5, v32, v30 ; 2C0A3D20 v_mov_b32_e32 v30, v5 ; 7E3C0305 s_or_b64 exec, exec, s[58:59] ; 87FE3A7E v_mul_f32_e32 v5, 0x3e59999a, v19 ; 0A0A26FF 3E59999A v_madmk_f32_e32 v5, v20, v5, 0x3f372474 ; 2E0A0B14 3F372474 v_madmk_f32_e32 v5, v21, v5, 0x3d93a92a ; 2E0A0B15 3D93A92A v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mul_f32_e32 v5, v22, v5 ; 0A0A0B16 v_subrev_f32_e32 v19, s19, v8 ; 06261013 v_subrev_f32_e32 v20, s18, v10 ; 06281412 v_subrev_f32_e32 v21, s10, v11 ; 062A160A v_mul_f32_e32 v19, v19, v19 ; 0A262713 v_mac_f32_e32 v19, v20, v20 ; 2C262914 v_mac_f32_e32 v19, v21, v21 ; 2C262B15 v_mad_f32 v19, v31, v19, s9 ; D1C10013 0026271F v_add_f32_e64 v19, 0, v19 clamp ; D1018013 00022680 v_sub_f32_e32 v20, 1.0, v19 ; 042826F2 v_mac_f32_e32 v19, v20, v30 ; 2C263D14 v_sub_f32_e32 v20, 1.0, v19 ; 042826F2 v_mad_f32 v19, -v19, v5, v5 ; D1C10013 24160B13 v_mad_f32 v5, -v20, v5, 1.0 ; D1C10005 23CA0B14 v_mad_f32 v20, -v19, v4, v4 ; D1C10014 24120913 v_mad_f32 v4, -v19, v1, v1 ; D1C10004 24060313 v_mad_f32 v19, -v19, v0, v0 ; D1C10013 24020113 v_mad_f32 v5, 0.5, v5, 0.5 ; D1C10005 03C20AF0 v_mad_f32 v0, -v5, v20, v20 ; D1C10000 24522905 v_mac_f32_e32 v0, v5, v19 ; 2C002705 v_mad_f32 v1, -v5, v4, v4 ; D1C10001 24120905 v_mac_f32_e32 v1, v5, v4 ; 2C020905 v_mad_f32 v4, -v5, v19, v19 ; D1C10004 244E2705 v_mac_f32_e32 v4, v5, v20 ; 2C082905 s_or_b64 exec, exec, s[16:17] ; 87FE107E s_buffer_load_dword s5, s[12:15], 0xa0 ; C0220146 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0xa4 ; C0220186 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0xa8 ; C02201C6 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xb0 ; C0220106 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0xb8 ; C0220046 000000B8 v_mov_b32_e32 v19, s11 ; 7E26020B v_mov_b32_e32 v5, s8 ; 7E0A0208 s_buffer_load_dword s3, s[12:15], 0x1d0 ; C02200C6 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d4 ; C0220086 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x1d8 ; C0220006 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x1f0 ; C02202C6 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x1f4 ; C0220286 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x1f8 ; C0220246 000001F8 v_mad_f32 v12, -v9, v12, v12 ; D1C1000C 24321909 v_mac_f32_e32 v12, v9, v16 ; 2C182109 v_mad_f32 v13, -v9, v13, v13 ; D1C1000D 24361B09 v_mac_f32_e32 v13, v9, v17 ; 2C1A2309 v_mad_f32 v14, -v9, v14, v14 ; D1C1000E 243A1D09 v_mac_f32_e32 v14, v9, v18 ; 2C1C2509 v_mul_f32_e32 v9, v2, v12 ; 0A121902 v_mul_f32_e32 v3, v3, v13 ; 0A061B03 v_mul_f32_e32 v6, v6, v14 ; 0A0C1D06 v_mul_f32_e32 v2, v7, v15 ; 0A041F07 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v0, s11, v0 ; 0200000B v_add_f32_e32 v1, s10, v1 ; 0202020A v_add_f32_e32 v4, s9, v4 ; 02080809 v_mul_f32_e32 v0, v0, v9 ; 0A001300 v_mul_f32_e32 v1, v1, v3 ; 0A020701 v_mul_f32_e32 v3, v4, v6 ; 0A060D04 v_sub_f32_e32 v4, s5, v8 ; 04081005 v_sub_f32_e32 v6, s6, v10 ; 040C1406 v_sub_f32_e32 v7, s7, v11 ; 040E1607 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mac_f32_e32 v4, v6, v6 ; 2C080D06 v_mac_f32_e32 v4, v7, v7 ; 2C080F07 v_sqrt_f32_e32 v4, v4 ; 7E084F04 v_mad_f32 v4, v19, v4, s4 ; D1C10004 00120913 v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_min_f32_e32 v4, s1, v4 ; 14080801 v_mul_f32_e32 v6, s8, v0 ; 0A0C0008 v_mul_f32_e32 v7, s8, v1 ; 0A0E0208 v_mul_f32_e32 v8, s8, v3 ; 0A100608 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mad_f32 v0, -v0, v5, s3 ; D1C10000 200E0B00 v_mad_f32 v1, -v1, v5, s2 ; D1C10001 200A0B01 v_mad_f32 v3, -v3, v5, s0 ; D1C10003 20020B03 v_mac_f32_e32 v6, v0, v4 ; 2C0C0900 v_mac_f32_e32 v7, v1, v4 ; 2C0E0901 v_mac_f32_e32 v8, v3, v4 ; 2C100903 v_cvt_pkrtz_f16_f32_e64 v0, v6, v7 ; D2960000 00020F06 v_cvt_pkrtz_f16_f32_e64 v1, v8, v2 ; D2960001 00020508 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 56 Code Size: 3268 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] DCL OUT[5], GENERIC[3] DCL OUT[6], GENERIC[4] DCL CONST[0..57] DCL TEMP[0..13], LOCAL IMM[0] FLT32 { -128.0000, 1.0000, -2.0000, -64.0000} IMM[1] FLT32 { -0.0159, 0.0159, 2.2000, 19.0000} IMM[2] FLT32 { 0.2125, 0.7154, 0.0721, 0.2500} IMM[3] FLT32 { 0.1592, 0.3676, 0.3406, 6.2832} IMM[4] FLT32 { -3.1416, -0.0000, 0.0000, -0.0014} IMM[5] FLT32 { 0.0417, 3.0000, 0.1000, 0.4000} IMM[6] FLT32 { 0.0001, 0.0000, 0.0000, 0.0000} 0: ABS TEMP[0].x, CONST[50].xxxx 1: FSLT TEMP[1].x, -TEMP[0].xxxx, TEMP[0].xxxx 2: AND TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy 3: ADD TEMP[0].xyz, IN[2].xyzz, IN[2].xyzz 4: LG2 TEMP[1].x, TEMP[0].xxxx 5: LG2 TEMP[3].x, TEMP[0].yyyy 6: MOV TEMP[1].y, TEMP[3].xxxx 7: LG2 TEMP[4].x, TEMP[0].zzzz 8: MOV TEMP[1].z, TEMP[4].xxxx 9: MUL TEMP[0].xyz, TEMP[1].xyzz, IMM[1].zzzz 10: EX2 TEMP[1].x, TEMP[0].xxxx 11: EX2 TEMP[4].x, TEMP[0].yyyy 12: MOV TEMP[1].y, TEMP[4].xxxx 13: EX2 TEMP[4].x, TEMP[0].zzzz 14: MOV TEMP[1].z, TEMP[4].xxxx 15: MUL TEMP[4].xyz, TEMP[2].xxxx, TEMP[1].xyzz 16: DP3 TEMP[5].x, TEMP[1].xyzz, IMM[2].xyzz 17: ADD TEMP[6].x, CONST[0].yyyy, -IN[2].wwww 18: MUL TEMP[0].x, TEMP[5].xxxx, TEMP[6].xxxx 19: MUL TEMP[5].x, TEMP[0].xxxx, TEMP[2].xxxx 20: MOV TEMP[5].w, TEMP[5].xxxx 21: DP4 TEMP[6].x, IN[3], CONST[48] 22: DP4 TEMP[7].x, IN[3], CONST[49] 23: MOV TEMP[6].y, TEMP[7].xxxx 24: MOV TEMP[0].x, CONST[54].wwww 25: MOV TEMP[0].y, CONST[55].wwww 26: MOV TEMP[0].z, CONST[56].wwww 27: DP3 TEMP[7].x, TEMP[0].xyzz, CONST[0].yyyy 28: MAD TEMP[1].x, TEMP[7].xxxx, IMM[1].wwww, CONST[12].yyyy 29: MUL TEMP[1].xy, TEMP[1].xxxx, CONST[15].xxxx 30: MUL TEMP[8].xy, TEMP[1].yyyy, CONST[51].xxxx 31: MOV TEMP[1].zw, TEMP[8].yyxy 32: MAD TEMP[1], TEMP[1], IMM[3].xyxz, IMM[2].wwww 33: FRC TEMP[8], TEMP[1] 34: MAD TEMP[1], TEMP[8], IMM[3].wwww, IMM[4].xxxx 35: MUL TEMP[1], TEMP[1], TEMP[1] 36: MAD TEMP[2], TEMP[1], IMM[4].yyyy, IMM[4].zzzz 37: MAD TEMP[2], TEMP[1], TEMP[2], IMM[4].wwww 38: MAD TEMP[2], TEMP[1], TEMP[2], IMM[5].xxxx 39: MAD TEMP[2], TEMP[1], TEMP[2], -CONST[0].wwww 40: MAD TEMP[1], TEMP[1], TEMP[2], CONST[0].yyyy 41: MUL TEMP[2].xy, CONST[12].zwww, CONST[12].zwww 42: ADD TEMP[2].x, TEMP[2].yyyy, TEMP[2].xxxx 43: SQRT TEMP[2].x, TEMP[2].xxxx 44: ADD TEMP[8].x, TEMP[2].xxxx, -CONST[52].xxxx 45: ADD TEMP[9].x, -CONST[52].xxxx, CONST[52].yyyy 46: RCP TEMP[9].x, TEMP[9].xxxx 47: MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx 48: MOV_SAT TEMP[8].x, TEMP[8].xxxx 49: MAD TEMP[9].x, TEMP[8].xxxx, IMM[0].zzzz, IMM[5].yyyy 50: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[8].xxxx 51: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx 52: LRP TEMP[3].xy, TEMP[8].xxxx, TEMP[1].zwww, TEMP[1].xyyy 53: ADD TEMP[1].xy, TEMP[3].xyyy, IMM[5].zwww 54: MUL TEMP[8].xyz, CONST[12].wwww, CONST[55].xyzz 55: MAD TEMP[8].xyz, CONST[54].xyzz, CONST[12].zzzz, TEMP[8].xyzz 56: DP3 TEMP[9].x, TEMP[8].xyzz, TEMP[8].xyzz 57: SQRT TEMP[9].x, TEMP[9].xxxx 58: MOV TEMP[0].z, TEMP[9].xxxx 59: MAD TEMP[3].xyz, IN[4].xyzz, CONST[13].xxxx, IN[0].xyzz 60: MUL TEMP[9].xy, TEMP[3].xyyy, TEMP[3].xyyy 61: ADD TEMP[9].x, TEMP[9].yyyy, TEMP[9].xxxx 62: SQRT TEMP[9].x, TEMP[9].xxxx 63: MOV TEMP[0].w, TEMP[9].xxxx 64: MAX TEMP[9].xy, TEMP[0].zwww, IMM[6].xxxx 65: MUL TEMP[9].x, TEMP[9].yyyy, TEMP[9].xxxx 66: RCP TEMP[9].x, TEMP[9].xxxx 67: MOV TEMP[3].w, CONST[0].xxxx 68: DP3 TEMP[10].x, TEMP[8].xyzz, TEMP[3].xyww 69: ABS TEMP[10].x, TEMP[10].xxxx 70: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx 71: MIN TEMP[9].x, TEMP[9].xxxx, CONST[0].yyyy 72: ADD TEMP[9].x, -TEMP[9].xxxx, CONST[0].yyyy 73: MUL TEMP[9].x, TEMP[9].xxxx, CONST[15].yyyy 74: ADD TEMP[11].xy, CONST[0].yyyy, -CONST[14].ywww 75: MUL TEMP[11].xy, TEMP[11].xyyy, CONST[14].xzzz 76: RCP TEMP[12].x, TEMP[11].yyyy 77: RCP TEMP[11].x, TEMP[11].xxxx 78: MAD TEMP[10].xyz, CONST[14].xzzz, -CONST[14].ywww, TEMP[3].zxyy 79: MUL TEMP[13].xy, TEMP[10].yzzz, TEMP[10].yzzz 80: ADD TEMP[13].x, TEMP[13].yyyy, TEMP[13].xxxx 81: SQRT TEMP[13].x, TEMP[13].xxxx 82: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx 83: MOV_SAT TEMP[12].x, TEMP[12].xxxx 84: MUL TEMP[9].x, TEMP[12].xxxx, TEMP[9].xxxx 85: MOV TEMP[0].z, TEMP[9].xxxx 86: POW TEMP[9].x, TEMP[12].xxxx, CONST[51].yyyy 87: MUL TEMP[9].x, TEMP[9].xxxx, CONST[15].wwww 88: MOV TEMP[0].w, TEMP[9].xxxx 89: FSGE TEMP[9].x, TEMP[10].xxxx, CONST[0].xxxx 90: AND TEMP[9].x, TEMP[9].xxxx, IMM[0].yyyy 91: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[10].xxxx 92: MOV_SAT TEMP[11].x, TEMP[11].xxxx 93: POW TEMP[11].x, TEMP[11].xxxx, CONST[51].zzzz 94: MUL TEMP[11].x, TEMP[11].xxxx, CONST[15].yyyy 95: MUL TEMP[10].xyz, TEMP[11].xxxx, TEMP[8].xyzz 96: MUL TEMP[9].xy, TEMP[0].zwww, TEMP[9].xxxx 97: MUL TEMP[8].xyz, TEMP[9].xxxx, TEMP[8].xyzz 98: MUL TEMP[8].xyz, TEMP[1].yyyy, TEMP[8].xyzz 99: MAD TEMP[1].xyz, TEMP[10].xyzz, TEMP[1].xxxx, TEMP[8].xyzz 100: DP3 TEMP[8].x, TEMP[3].xyzz, TEMP[3].xyzz 101: RSQ TEMP[8].x, TEMP[8].xxxx 102: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[3].yzxx 103: MUL TEMP[8].xyz, TEMP[8].xyzz, CONST[15].zzzz 104: MAD TEMP[8].xyz, CONST[51].wwww, CONST[12].yyyy, TEMP[8].xyzz 105: MAD TEMP[0].xyz, TEMP[7].xxxx, IMM[1].wwww, TEMP[8].xyzz 106: MAD TEMP[0].xyz, TEMP[0].xyzz, IMM[3].xxxx, IMM[2].wwww 107: FRC TEMP[7].xyz, TEMP[0].xyzz 108: MAD TEMP[0].xyz, TEMP[7].xyzz, IMM[3].wwww, IMM[4].xxxx 109: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[0].xyzz 110: MAD TEMP[7].xyz, TEMP[0].xyzz, IMM[4].yyyy, IMM[4].zzzz 111: MAD TEMP[7].xyz, TEMP[0].xyzz, TEMP[7].xyzz, IMM[4].wwww 112: MAD TEMP[7].xyz, TEMP[0].xyzz, TEMP[7].xyzz, IMM[5].xxxx 113: MAD TEMP[7].xyz, TEMP[0].xyzz, TEMP[7].xyzz, -CONST[0].wwww 114: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[7].xyzz, CONST[0].yyyy 115: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[9].yyyy 116: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[1].xyzz 117: ADD TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xyzz 118: MOV TEMP[0].w, IN[0].wwww 119: DP4 TEMP[1].x, TEMP[0], CONST[54] 120: DP4 TEMP[2].x, TEMP[0], CONST[55] 121: MOV TEMP[1].y, TEMP[2].xxxx 122: DP4 TEMP[0].x, TEMP[0], CONST[56] 123: MOV TEMP[1].z, TEMP[0].xxxx 124: MOV TEMP[1].w, CONST[0].yyyy 125: DP4 TEMP[0].x, TEMP[1], CONST[8] 126: DP4 TEMP[2].x, TEMP[1], CONST[9] 127: MOV TEMP[0].y, TEMP[2].xxxx 128: DP4 TEMP[3].x, TEMP[1], CONST[11] 129: MOV TEMP[0].w, TEMP[3].xxxx 130: DP4 TEMP[7].x, TEMP[1], CONST[10] 131: ADD TEMP[8].xyz, -TEMP[1].xyzz, CONST[2].xyzz 132: MOV TEMP[1].xyz, TEMP[1].xyzx 133: DP3 TEMP[8].x, TEMP[8].xyzz, TEMP[8].xyzz 134: SQRT TEMP[8].x, TEMP[8].xxxx 135: MAD TEMP[8].x, TEMP[8].xxxx, CONST[16].wwww, CONST[16].xxxx 136: MOV_SAT TEMP[8].x, TEMP[8].xxxx 137: MIN TEMP[8].x, TEMP[8].xxxx, CONST[16].zzzz 138: MOV TEMP[8].w, TEMP[8].xxxx 139: MOV TEMP[0].z, TEMP[7].xxxx 140: MOV TEMP[1].w, TEMP[7].xxxx 141: MOV TEMP[6].zw, CONST[0].xxxx 142: MOV TEMP[8].xyz, CONST[0].xxxx 143: MOV TEMP[4].w, CONST[0].xxxx 144: MOV TEMP[5].xyz, CONST[0].xxxx 145: MOV TEMP[9], TEMP[0] 146: MAD TEMP[7].x, TEMP[7].xxxx, CONST[0].zzzz, -TEMP[3].xxxx 147: MOV TEMP[0].z, TEMP[7].xxxx 148: MOV TEMP[0].y, -TEMP[2].xxxx 149: MAD TEMP[0].xy, CONST[57].xyyy, TEMP[3].xxxx, TEMP[0].xyyy 150: MOV OUT[2], TEMP[6] 151: MOV OUT[3], TEMP[5] 152: MOV OUT[4], TEMP[8] 153: MOV OUT[0], TEMP[0] 154: MOV OUT[1], TEMP[9] 155: MOV OUT[5], TEMP[4] 156: MOV OUT[6], TEMP[1] 157: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 196) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 200) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 204) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 224) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 228) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 232) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 236) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 240) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 244) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 248) %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 252) %49 = call float @llvm.SI.load.const(<16 x i8> %13, i32 256) %50 = call float @llvm.SI.load.const(<16 x i8> %13, i32 264) %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 268) %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %53 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %56 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %57 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %59 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %60 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %61 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %62 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %63 = call float @llvm.SI.load.const(<16 x i8> %13, i32 824) %64 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %65 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %66 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %67 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %68 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %69 = call float @llvm.SI.load.const(<16 x i8> %13, i32 872) %70 = call float @llvm.SI.load.const(<16 x i8> %13, i32 876) %71 = call float @llvm.SI.load.const(<16 x i8> %13, i32 880) %72 = call float @llvm.SI.load.const(<16 x i8> %13, i32 884) %73 = call float @llvm.SI.load.const(<16 x i8> %13, i32 888) %74 = call float @llvm.SI.load.const(<16 x i8> %13, i32 892) %75 = call float @llvm.SI.load.const(<16 x i8> %13, i32 896) %76 = call float @llvm.SI.load.const(<16 x i8> %13, i32 900) %77 = call float @llvm.SI.load.const(<16 x i8> %13, i32 904) %78 = call float @llvm.SI.load.const(<16 x i8> %13, i32 908) %79 = call float @llvm.SI.load.const(<16 x i8> %13, i32 912) %80 = call float @llvm.SI.load.const(<16 x i8> %13, i32 916) %81 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %82 = load <16 x i8>, <16 x i8> addrspace(2)* %81, align 16, !tbaa !0 %83 = add i32 %5, %8 %84 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %83) %85 = extractelement <4 x float> %84, i32 0 %86 = extractelement <4 x float> %84, i32 1 %87 = extractelement <4 x float> %84, i32 2 %88 = extractelement <4 x float> %84, i32 3 %89 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %90 = load <16 x i8>, <16 x i8> addrspace(2)* %89, align 16, !tbaa !0 %91 = add i32 %5, %8 %92 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %90, i32 0, i32 %91) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %98 = load <16 x i8>, <16 x i8> addrspace(2)* %97, align 16, !tbaa !0 %99 = add i32 %5, %8 %100 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %98, i32 0, i32 %99) %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = extractelement <4 x float> %100, i32 2 %104 = extractelement <4 x float> %100, i32 3 %105 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %106 = load <16 x i8>, <16 x i8> addrspace(2)* %105, align 16, !tbaa !0 %107 = add i32 %5, %8 %108 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %106, i32 0, i32 %107) %109 = extractelement <4 x float> %108, i32 0 %110 = extractelement <4 x float> %108, i32 1 %111 = extractelement <4 x float> %108, i32 2 %112 = call float @llvm.fabs.f32(float %60) %113 = fsub float -0.000000e+00, %112 %114 = fcmp ogt float %112, %113 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fadd float %93, %93 %117 = fadd float %94, %94 %118 = fadd float %95, %95 %119 = call float @llvm.log2.f32(float %116) %120 = call float @llvm.log2.f32(float %117) %121 = call float @llvm.log2.f32(float %118) %122 = fmul float %119, 0x40019999A0000000 %123 = fmul float %120, 0x40019999A0000000 %124 = fmul float %121, 0x40019999A0000000 %125 = call float @llvm.exp2.f32(float %122) %126 = call float @llvm.exp2.f32(float %123) %127 = call float @llvm.exp2.f32(float %124) %128 = fmul float %115, %125 %129 = fmul float %115, %126 %130 = fmul float %115, %127 %131 = fmul float %125, 0x3FCB333340000000 %132 = fmul float %126, 0x3FE6E48E80000000 %133 = fadd float %132, %131 %134 = fmul float %127, 0x3FB2752540000000 %135 = fadd float %133, %134 %136 = fsub float %15, %96 %137 = fmul float %135, %136 %138 = fmul float %137, %115 %139 = fmul float %101, %52 %140 = fmul float %102, %53 %141 = fadd float %139, %140 %142 = fmul float %103, %54 %143 = fadd float %141, %142 %144 = fmul float %104, %55 %145 = fadd float %143, %144 %146 = fmul float %101, %56 %147 = fmul float %102, %57 %148 = fadd float %146, %147 %149 = fmul float %103, %58 %150 = fadd float %148, %149 %151 = fmul float %104, %59 %152 = fadd float %150, %151 %153 = fmul float %70, %15 %154 = fmul float %74, %15 %155 = fadd float %154, %153 %156 = fmul float %78, %15 %157 = fadd float %155, %156 %158 = fmul float %157, 1.900000e+01 %159 = fadd float %158, %37 %160 = fmul float %159, %45 %161 = fmul float %159, %45 %162 = fmul float %161, %61 %163 = fmul float %161, %61 %164 = fmul float %160, 0x3FC45F3060000000 %165 = fadd float %164, 2.500000e-01 %166 = fmul float %161, 0x3FD7878B20000000 %167 = fadd float %166, 2.500000e-01 %168 = fmul float %162, 0x3FC45F3060000000 %169 = fadd float %168, 2.500000e-01 %170 = fmul float %163, 0x3FD5CC40A0000000 %171 = fadd float %170, 2.500000e-01 %172 = call float @llvm.floor.f32(float %165) %173 = fsub float %165, %172 %174 = call float @llvm.floor.f32(float %167) %175 = fsub float %167, %174 %176 = call float @llvm.floor.f32(float %169) %177 = fsub float %169, %176 %178 = call float @llvm.floor.f32(float %171) %179 = fsub float %171, %178 %180 = fmul float %173, 0x401921FB60000000 %181 = fadd float %180, 0xC00921FB60000000 %182 = fmul float %175, 0x401921FB60000000 %183 = fadd float %182, 0xC00921FB60000000 %184 = fmul float %177, 0x401921FB60000000 %185 = fadd float %184, 0xC00921FB60000000 %186 = fmul float %179, 0x401921FB60000000 %187 = fadd float %186, 0xC00921FB60000000 %188 = fmul float %181, %181 %189 = fmul float %183, %183 %190 = fmul float %185, %185 %191 = fmul float %187, %187 %192 = fmul float %188, 0xBE90F02E80000000 %193 = fadd float %192, 0x3EF9F6B420000000 %194 = fmul float %189, 0xBE90F02E80000000 %195 = fadd float %194, 0x3EF9F6B420000000 %196 = fmul float %190, 0xBE90F02E80000000 %197 = fadd float %196, 0x3EF9F6B420000000 %198 = fmul float %191, 0xBE90F02E80000000 %199 = fadd float %198, 0x3EF9F6B420000000 %200 = fmul float %188, %193 %201 = fadd float %200, 0xBF56C13740000000 %202 = fmul float %189, %195 %203 = fadd float %202, 0xBF56C13740000000 %204 = fmul float %190, %197 %205 = fadd float %204, 0xBF56C13740000000 %206 = fmul float %191, %199 %207 = fadd float %206, 0xBF56C13740000000 %208 = fmul float %188, %201 %209 = fadd float %208, 0x3FA5555480000000 %210 = fmul float %189, %203 %211 = fadd float %210, 0x3FA5555480000000 %212 = fmul float %190, %205 %213 = fadd float %212, 0x3FA5555480000000 %214 = fmul float %191, %207 %215 = fadd float %214, 0x3FA5555480000000 %216 = fmul float %188, %209 %217 = fsub float %216, %17 %218 = fmul float %189, %211 %219 = fsub float %218, %17 %220 = fmul float %190, %213 %221 = fsub float %220, %17 %222 = fmul float %191, %215 %223 = fsub float %222, %17 %224 = fmul float %188, %217 %225 = fadd float %224, %15 %226 = fmul float %189, %219 %227 = fadd float %226, %15 %228 = fmul float %190, %221 %229 = fadd float %228, %15 %230 = fmul float %191, %223 %231 = fadd float %230, %15 %232 = fmul float %38, %38 %233 = fmul float %39, %39 %234 = fadd float %233, %232 %235 = call float @llvm.sqrt.f32(float %234) %236 = fsub float %235, %65 %237 = fsub float %66, %65 %238 = fdiv float 1.000000e+00, %237 %239 = fmul float %238, %236 %240 = call float @llvm.AMDIL.clamp.(float %239, float 0.000000e+00, float 1.000000e+00) %241 = fmul float %240, -2.000000e+00 %242 = fadd float %241, 3.000000e+00 %243 = fmul float %240, %240 %244 = fmul float %243, %242 %245 = fsub float 1.000000e+00, %244 %246 = fmul float %229, %244 %247 = fmul float %225, %245 %248 = fadd float %246, %247 %249 = fsub float 1.000000e+00, %244 %250 = fmul float %231, %244 %251 = fmul float %227, %249 %252 = fadd float %250, %251 %253 = fadd float %248, 0x3FB99999A0000000 %254 = fadd float %252, 0x3FD99999A0000000 %255 = fmul float %39, %71 %256 = fmul float %39, %72 %257 = fmul float %39, %73 %258 = fmul float %67, %38 %259 = fadd float %258, %255 %260 = fmul float %68, %38 %261 = fadd float %260, %256 %262 = fmul float %69, %38 %263 = fadd float %262, %257 %264 = fmul float %259, %259 %265 = fmul float %261, %261 %266 = fadd float %265, %264 %267 = fmul float %263, %263 %268 = fadd float %266, %267 %269 = call float @llvm.sqrt.f32(float %268) %270 = fmul float %109, %40 %271 = fadd float %270, %85 %272 = fmul float %110, %40 %273 = fadd float %272, %86 %274 = fmul float %111, %40 %275 = fadd float %274, %87 %276 = fmul float %271, %271 %277 = fmul float %273, %273 %278 = fadd float %277, %276 %279 = call float @llvm.sqrt.f32(float %278) %280 = call float @llvm.maxnum.f32(float %269, float 0x3F1A36E2E0000000) %281 = call float @llvm.maxnum.f32(float %279, float 0x3F1A36E2E0000000) %282 = fmul float %281, %280 %283 = fdiv float 1.000000e+00, %282 %284 = fmul float %259, %271 %285 = fmul float %261, %273 %286 = fadd float %285, %284 %287 = fmul float %263, %14 %288 = fadd float %286, %287 %289 = call float @llvm.fabs.f32(float %288) %290 = fmul float %283, %289 %291 = call float @llvm.minnum.f32(float %290, float %15) %292 = fsub float %15, %291 %293 = fmul float %292, %46 %294 = fsub float %15, %42 %295 = fsub float %15, %44 %296 = fmul float %294, %41 %297 = fmul float %295, %43 %298 = fdiv float 1.000000e+00, %297 %299 = fdiv float 1.000000e+00, %296 %300 = fmul float %42, %41 %301 = fsub float %275, %300 %302 = fmul float %44, %43 %303 = fsub float %271, %302 %304 = fmul float %44, %43 %305 = fsub float %273, %304 %306 = fmul float %303, %303 %307 = fmul float %305, %305 %308 = fadd float %307, %306 %309 = call float @llvm.sqrt.f32(float %308) %310 = fmul float %298, %309 %311 = call float @llvm.AMDIL.clamp.(float %310, float 0.000000e+00, float 1.000000e+00) %312 = fmul float %311, %293 %313 = call float @llvm.pow.f32(float %311, float %62) %314 = fmul float %313, %48 %315 = fcmp oge float %301, %14 %316 = select i1 %315, float 1.000000e+00, float 0.000000e+00 %317 = fmul float %299, %301 %318 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00) %319 = call float @llvm.pow.f32(float %318, float %63) %320 = fmul float %319, %46 %321 = fmul float %320, %259 %322 = fmul float %320, %261 %323 = fmul float %320, %263 %324 = fmul float %312, %316 %325 = fmul float %314, %316 %326 = fmul float %324, %259 %327 = fmul float %324, %261 %328 = fmul float %324, %263 %329 = fmul float %254, %326 %330 = fmul float %254, %327 %331 = fmul float %254, %328 %332 = fmul float %321, %253 %333 = fadd float %332, %329 %334 = fmul float %322, %253 %335 = fadd float %334, %330 %336 = fmul float %323, %253 %337 = fadd float %336, %331 %338 = fmul float %271, %271 %339 = fmul float %273, %273 %340 = fadd float %339, %338 %341 = fmul float %275, %275 %342 = fadd float %340, %341 %343 = call float @llvm.AMDGPU.rsq.clamped.f32(float %342) %344 = fmul float %343, %273 %345 = fmul float %343, %275 %346 = fmul float %343, %271 %347 = fmul float %344, %47 %348 = fmul float %345, %47 %349 = fmul float %346, %47 %350 = fmul float %64, %37 %351 = fadd float %350, %347 %352 = fmul float %64, %37 %353 = fadd float %352, %348 %354 = fmul float %64, %37 %355 = fadd float %354, %349 %356 = fmul float %157, 1.900000e+01 %357 = fadd float %356, %351 %358 = fmul float %157, 1.900000e+01 %359 = fadd float %358, %353 %360 = fmul float %157, 1.900000e+01 %361 = fadd float %360, %355 %362 = fmul float %357, 0x3FC45F3060000000 %363 = fadd float %362, 2.500000e-01 %364 = fmul float %359, 0x3FC45F3060000000 %365 = fadd float %364, 2.500000e-01 %366 = fmul float %361, 0x3FC45F3060000000 %367 = fadd float %366, 2.500000e-01 %368 = call float @llvm.floor.f32(float %363) %369 = fsub float %363, %368 %370 = call float @llvm.floor.f32(float %365) %371 = fsub float %365, %370 %372 = call float @llvm.floor.f32(float %367) %373 = fsub float %367, %372 %374 = fmul float %369, 0x401921FB60000000 %375 = fadd float %374, 0xC00921FB60000000 %376 = fmul float %371, 0x401921FB60000000 %377 = fadd float %376, 0xC00921FB60000000 %378 = fmul float %373, 0x401921FB60000000 %379 = fadd float %378, 0xC00921FB60000000 %380 = fmul float %375, %375 %381 = fmul float %377, %377 %382 = fmul float %379, %379 %383 = fmul float %380, 0xBE90F02E80000000 %384 = fadd float %383, 0x3EF9F6B420000000 %385 = fmul float %381, 0xBE90F02E80000000 %386 = fadd float %385, 0x3EF9F6B420000000 %387 = fmul float %382, 0xBE90F02E80000000 %388 = fadd float %387, 0x3EF9F6B420000000 %389 = fmul float %380, %384 %390 = fadd float %389, 0xBF56C13740000000 %391 = fmul float %381, %386 %392 = fadd float %391, 0xBF56C13740000000 %393 = fmul float %382, %388 %394 = fadd float %393, 0xBF56C13740000000 %395 = fmul float %380, %390 %396 = fadd float %395, 0x3FA5555480000000 %397 = fmul float %381, %392 %398 = fadd float %397, 0x3FA5555480000000 %399 = fmul float %382, %394 %400 = fadd float %399, 0x3FA5555480000000 %401 = fmul float %380, %396 %402 = fsub float %401, %17 %403 = fmul float %381, %398 %404 = fsub float %403, %17 %405 = fmul float %382, %400 %406 = fsub float %405, %17 %407 = fmul float %380, %402 %408 = fadd float %407, %15 %409 = fmul float %381, %404 %410 = fadd float %409, %15 %411 = fmul float %382, %406 %412 = fadd float %411, %15 %413 = fmul float %408, %325 %414 = fmul float %410, %325 %415 = fmul float %412, %325 %416 = fmul float %235, %413 %417 = fadd float %416, %333 %418 = fmul float %235, %414 %419 = fadd float %418, %335 %420 = fmul float %235, %415 %421 = fadd float %420, %337 %422 = fadd float %417, %271 %423 = fadd float %419, %273 %424 = fadd float %421, %275 %425 = fmul float %422, %67 %426 = fmul float %423, %68 %427 = fadd float %425, %426 %428 = fmul float %424, %69 %429 = fadd float %427, %428 %430 = fmul float %88, %70 %431 = fadd float %429, %430 %432 = fmul float %422, %71 %433 = fmul float %423, %72 %434 = fadd float %432, %433 %435 = fmul float %424, %73 %436 = fadd float %434, %435 %437 = fmul float %88, %74 %438 = fadd float %436, %437 %439 = fmul float %422, %75 %440 = fmul float %423, %76 %441 = fadd float %439, %440 %442 = fmul float %424, %77 %443 = fadd float %441, %442 %444 = fmul float %88, %78 %445 = fadd float %443, %444 %446 = fmul float %431, %21 %447 = fmul float %438, %22 %448 = fadd float %446, %447 %449 = fmul float %445, %23 %450 = fadd float %448, %449 %451 = fmul float %15, %24 %452 = fadd float %450, %451 %453 = fmul float %431, %25 %454 = fmul float %438, %26 %455 = fadd float %453, %454 %456 = fmul float %445, %27 %457 = fadd float %455, %456 %458 = fmul float %15, %28 %459 = fadd float %457, %458 %460 = fmul float %431, %33 %461 = fmul float %438, %34 %462 = fadd float %460, %461 %463 = fmul float %445, %35 %464 = fadd float %462, %463 %465 = fmul float %15, %36 %466 = fadd float %464, %465 %467 = fmul float %431, %29 %468 = fmul float %438, %30 %469 = fadd float %467, %468 %470 = fmul float %445, %31 %471 = fadd float %469, %470 %472 = fmul float %15, %32 %473 = fadd float %471, %472 %474 = fsub float %18, %431 %475 = fsub float %19, %438 %476 = fsub float %20, %445 %477 = fmul float %474, %474 %478 = fmul float %475, %475 %479 = fadd float %478, %477 %480 = fmul float %476, %476 %481 = fadd float %479, %480 %482 = call float @llvm.sqrt.f32(float %481) %483 = fmul float %482, %51 %484 = fadd float %483, %49 %485 = call float @llvm.AMDIL.clamp.(float %484, float 0.000000e+00, float 1.000000e+00) %486 = call float @llvm.minnum.f32(float %485, float %50) %487 = fmul float %473, %16 %488 = fsub float %487, %466 %489 = fmul float %79, %466 %490 = fadd float %489, %452 %491 = fmul float %80, %466 %492 = fsub float %491, %459 %493 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %494 = load <16 x i8>, <16 x i8> addrspace(2)* %493, align 16, !tbaa !0 %495 = call float @llvm.SI.load.const(<16 x i8> %494, i32 0) %496 = fmul float %495, %452 %497 = call float @llvm.SI.load.const(<16 x i8> %494, i32 4) %498 = fmul float %497, %459 %499 = fadd float %496, %498 %500 = call float @llvm.SI.load.const(<16 x i8> %494, i32 8) %501 = fmul float %500, %473 %502 = fadd float %499, %501 %503 = call float @llvm.SI.load.const(<16 x i8> %494, i32 12) %504 = fmul float %503, %466 %505 = fadd float %502, %504 %506 = call float @llvm.SI.load.const(<16 x i8> %494, i32 16) %507 = fmul float %506, %452 %508 = call float @llvm.SI.load.const(<16 x i8> %494, i32 20) %509 = fmul float %508, %459 %510 = fadd float %507, %509 %511 = call float @llvm.SI.load.const(<16 x i8> %494, i32 24) %512 = fmul float %511, %473 %513 = fadd float %510, %512 %514 = call float @llvm.SI.load.const(<16 x i8> %494, i32 28) %515 = fmul float %514, %466 %516 = fadd float %513, %515 %517 = call float @llvm.SI.load.const(<16 x i8> %494, i32 32) %518 = fmul float %517, %452 %519 = call float @llvm.SI.load.const(<16 x i8> %494, i32 36) %520 = fmul float %519, %459 %521 = fadd float %518, %520 %522 = call float @llvm.SI.load.const(<16 x i8> %494, i32 40) %523 = fmul float %522, %473 %524 = fadd float %521, %523 %525 = call float @llvm.SI.load.const(<16 x i8> %494, i32 44) %526 = fmul float %525, %466 %527 = fadd float %524, %526 %528 = call float @llvm.SI.load.const(<16 x i8> %494, i32 48) %529 = fmul float %528, %452 %530 = call float @llvm.SI.load.const(<16 x i8> %494, i32 52) %531 = fmul float %530, %459 %532 = fadd float %529, %531 %533 = call float @llvm.SI.load.const(<16 x i8> %494, i32 56) %534 = fmul float %533, %473 %535 = fadd float %532, %534 %536 = call float @llvm.SI.load.const(<16 x i8> %494, i32 60) %537 = fmul float %536, %466 %538 = fadd float %535, %537 %539 = call float @llvm.SI.load.const(<16 x i8> %494, i32 64) %540 = fmul float %539, %452 %541 = call float @llvm.SI.load.const(<16 x i8> %494, i32 68) %542 = fmul float %541, %459 %543 = fadd float %540, %542 %544 = call float @llvm.SI.load.const(<16 x i8> %494, i32 72) %545 = fmul float %544, %473 %546 = fadd float %543, %545 %547 = call float @llvm.SI.load.const(<16 x i8> %494, i32 76) %548 = fmul float %547, %466 %549 = fadd float %546, %548 %550 = call float @llvm.SI.load.const(<16 x i8> %494, i32 80) %551 = fmul float %550, %452 %552 = call float @llvm.SI.load.const(<16 x i8> %494, i32 84) %553 = fmul float %552, %459 %554 = fadd float %551, %553 %555 = call float @llvm.SI.load.const(<16 x i8> %494, i32 88) %556 = fmul float %555, %473 %557 = fadd float %554, %556 %558 = call float @llvm.SI.load.const(<16 x i8> %494, i32 92) %559 = fmul float %558, %466 %560 = fadd float %557, %559 %561 = call float @llvm.SI.load.const(<16 x i8> %494, i32 96) %562 = fmul float %561, %452 %563 = call float @llvm.SI.load.const(<16 x i8> %494, i32 100) %564 = fmul float %563, %459 %565 = fadd float %562, %564 %566 = call float @llvm.SI.load.const(<16 x i8> %494, i32 104) %567 = fmul float %566, %473 %568 = fadd float %565, %567 %569 = call float @llvm.SI.load.const(<16 x i8> %494, i32 108) %570 = fmul float %569, %466 %571 = fadd float %568, %570 %572 = call float @llvm.SI.load.const(<16 x i8> %494, i32 112) %573 = fmul float %572, %452 %574 = call float @llvm.SI.load.const(<16 x i8> %494, i32 116) %575 = fmul float %574, %459 %576 = fadd float %573, %575 %577 = call float @llvm.SI.load.const(<16 x i8> %494, i32 120) %578 = fmul float %577, %473 %579 = fadd float %576, %578 %580 = call float @llvm.SI.load.const(<16 x i8> %494, i32 124) %581 = fmul float %580, %466 %582 = fadd float %579, %581 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %145, float %152, float %14, float %14) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %14, float %14, float %14, float %138) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %14, float %14, float %14, float %486) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %128, float %129, float %130, float %14) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %431, float %438, float %445, float %473) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %490, float %492, float %488, float %466) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %505, float %516, float %527, float %538) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %549, float %560, float %571, float %582) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.log2.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.exp2.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.floor.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.pow.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: v_mov_b32_e32 v1, 0x400ccccd ; 7E0202FF 400CCCCD v_mov_b32_e32 v13, 0x41980000 ; 7E1A02FF 41980000 v_mov_b32_e32 v16, 0x38d1b717 ; 7E2002FF 38D1B717 v_mov_b32_e32 v17, 0xff7fffff ; 7E2202FF FF7FFFFF v_mov_b32_e32 v12, 0x3e800000 ; 7E1802FF 3E800000 v_mov_b32_e32 v14, 0x3e22f983 ; 7E1C02FF 3E22F983 v_mov_b32_e32 v9, 0xc0490fdb ; 7E1202FF C0490FDB v_mov_b32_e32 v11, 0x40c90fdb ; 7E1602FF 40C90FDB s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x20 ; C00A0304 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x30 ; C00A0404 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x40 ; C00A0504 00000040 v_mov_b32_e32 v7, 0x37cfb5a1 ; 7E0E02FF 37CFB5A1 v_mov_b32_e32 v10, 0xb4878174 ; 7E1402FF B4878174 v_mov_b32_e32 v8, 0xbab609ba ; 7E1002FF BAB609BA v_mov_b32_e32 v6, 0x3d2aaaa4 ; 7E0C02FF 3D2AAAA4 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[2:5], v0, s[4:7], 0 idxen ; E00C2000 80010200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[18:21], v0, s[12:15], 0 idxen ; E00C2000 80031200 s_load_dwordx4 s[88:91], s[2:3], 0x0 ; C00A1601 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[84:87], s[2:3], 0x100 ; C00A1501 00000100 buffer_load_format_xyzw v[22:25], v0, s[16:19], 0 idxen ; E00C2000 80041600 s_nop 0 ; BF800000 buffer_load_format_xyzw v[26:29], v0, s[20:23], 0 idxen ; E00C2000 80051A00 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s24, s[88:91], 0xcc ; C022062C 000000CC s_nop 0 ; BF800000 s_buffer_load_dword s83, s[88:91], 0xd0 ; C02214EC 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[88:91], 0xe0 ; C0220AAC 000000E0 s_nop 0 ; BF800000 s_buffer_load_dword s76, s[88:91], 0xe4 ; C022132C 000000E4 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[88:91], 0xe8 ; C0220AEC 000000E8 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[88:91], 0x368 ; C022026C 00000368 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[88:91], 0x36c ; C022022C 0000036C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[88:91], 0x370 ; C02202EC 00000370 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[88:91], 0x374 ; C022036C 00000374 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[88:91], 0x378 ; C02202AC 00000378 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[88:91], 0xb4 ; C02201EC 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[88:91], 0xb8 ; C022012C 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[88:91], 0xbc ; C02209EC 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s30, s[88:91], 0xc4 ; C02207AC 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[88:91], 0xc8 ; C022086C 000000C8 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[88:91], 0x33c ; C0220A6C 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[88:91], 0x340 ; C02208AC 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[88:91], 0x344 ; C022092C 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[88:91], 0x360 ; C02203EC 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[88:91], 0x364 ; C022052C 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s73, s[88:91], 0x0 ; C022126C 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[88:91], 0x4 ; C022016C 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[88:91], 0x8 ; C02200EC 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[88:91], 0xc ; C02207EC 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[88:91], 0x20 ; C022032C 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s74, s[88:91], 0xec ; C02212AC 000000EC s_nop 0 ; BF800000 s_buffer_load_dword s37, s[88:91], 0xf0 ; C022096C 000000F0 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[88:91], 0xf4 ; C02211AC 000000F4 s_nop 0 ; BF800000 s_buffer_load_dword s71, s[88:91], 0xf8 ; C02211EC 000000F8 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[88:91], 0xfc ; C02209AC 000000FC s_nop 0 ; BF800000 s_buffer_load_dword s19, s[88:91], 0x37c ; C02204EC 0000037C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[88:91], 0x380 ; C02205EC 00000380 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[88:91], 0x384 ; C02206EC 00000384 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[88:91], 0x388 ; C02205AC 00000388 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[88:91], 0x38c ; C022056C 0000038C s_nop 0 ; BF800000 s_buffer_load_dword s75, s[88:91], 0x31c ; C02212EC 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s0, s[88:91], 0x320 ; C022002C 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[88:91], 0x330 ; C0220B2C 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[88:91], 0x334 ; C0220A2C 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s72, s[88:91], 0x338 ; C022122C 00000338 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[88:91], 0x24 ; C022042C 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[88:91], 0x28 ; C022046C 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[88:91], 0x80 ; C02204AC 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[88:91], 0x84 ; C02206AC 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[88:91], 0x88 ; C02203AC 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[88:91], 0x100 ; C0220B6C 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F v_cmp_gt_f32_e64 s[0:1], |s0|, -|s0| ; D0440300 40000000 s_buffer_load_dword s2, s[88:91], 0x108 ; C02200AC 00000108 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[88:91], 0x10c ; C02201AC 0000010C s_nop 0 ; BF800000 s_buffer_load_dword s79, s[88:91], 0x300 ; C02213EC 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s92, s[88:91], 0x304 ; C022172C 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s78, s[88:91], 0x308 ; C02213AC 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s77, s[88:91], 0x30c ; C022136C 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s81, s[88:91], 0x310 ; C022146C 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s82, s[88:91], 0x314 ; C02214AC 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s80, s[88:91], 0x318 ; C022142C 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[88:91], 0x8c ; C0220BAC 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[88:91], 0x90 ; C022072C 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[88:91], 0x94 ; C022082C 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[88:91], 0x98 ; C022066C 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[88:91], 0x9c ; C0220BEC 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[88:91], 0xa0 ; C022076C 000000A0 v_mov_b32_e32 v0, s11 ; 7E00020B s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v29, s24, v0 ; 0A3A0018 v_mul_f32_e64 v0, s33, s33 ; D1050000 00004221 v_mac_f32_e64 v0, s24, s24 ; D1160000 00003018 v_sqrt_f32_e32 v30, v0 ; 7E3C4F00 v_mov_b32_e32 v0, s13 ; 7E00020D v_mul_f32_e32 v31, s24, v0 ; 0A3E0018 v_mov_b32_e32 v0, s33 ; 7E000221 s_buffer_load_dword s35, s[88:91], 0xa4 ; C02208EC 000000A4 v_mac_f32_e32 v29, s15, v0 ; 2C3A000F v_mac_f32_e32 v31, s20, v0 ; 2C3E0014 v_mov_b32_e32 v15, s10 ; 7E1E020A v_mul_f32_e32 v32, s24, v15 ; 0A401E18 v_mac_f32_e32 v32, s9, v0 ; 2C400009 s_buffer_load_dword s33, s[88:91], 0xa8 ; C022086C 000000A8 v_mul_f32_e32 v0, v29, v29 ; 0A003B1D v_mac_f32_e32 v0, v31, v31 ; 2C003F1F v_mac_f32_e32 v0, v32, v32 ; 2C004120 v_sqrt_f32_e32 v0, v0 ; 7E004F00 v_max_f32_e32 v33, v16, v0 ; 16420110 v_mov_b32_e32 v0, s5 ; 7E000205 v_mul_f32_e32 v34, s8, v0 ; 0A440008 v_mac_f32_e32 v34, s19, v0 ; 2C440013 v_mac_f32_e32 v34, s21, v0 ; 2C440015 v_mov_b32_e32 v35, s42 ; 7E46022A v_mov_b32_e32 v36, s43 ; 7E48022B v_mad_f32 v0, v34, v13, s30 ; D1C10000 007A1B22 v_mul_f32_e32 v0, s37, v0 ; 0A000025 s_buffer_load_dword s48, s[88:91], 0xac ; C0220C2C 000000AC v_mul_f32_e32 v15, s44, v0 ; 0A1E002C s_buffer_load_dword s37, s[88:91], 0xb0 ; C022096C 000000B0 v_madmk_f32_e32 v37, v0, v12, 0x3ebc3c59 ; 2E4A1900 3EBC3C59 v_mad_f32 v0, v14, v0, v12 ; D1C10000 0432010E v_fract_f32_e32 v37, v37 ; 7E4A3725 v_fract_f32_e32 v0, v0 ; 7E003700 v_mad_f32 v37, v11, v37, v9 ; D1C10025 04264B0B v_mad_f32 v0, v11, v0, v9 ; D1C10000 0426010B v_mul_f32_e32 v37, v37, v37 ; 0A4A4B25 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_subrev_f32_e32 v38, s34, v30 ; 064C3C22 v_mov_b32_e32 v39, s34 ; 7E4E0222 v_sub_f32_e32 v39, s36, v39 ; 044E4E24 v_rcp_f32_e32 v39, v39 ; 7E4E4527 s_buffer_load_dword s34, s[84:87], 0x0 ; C02208AA 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[84:87], 0x4 ; C022092A 00000004 v_mov_b32_e32 v40, s30 ; 7E50021E s_buffer_load_dword s30, s[84:87], 0x8 ; C02207AA 00000008 v_mul_f32_e32 v38, v38, v39 ; 0A4C4F26 v_mul_f32_e32 v39, s41, v40 ; 0A4E5029 s_buffer_load_dword s24, s[84:87], 0xc ; C022062A 0000000C v_add_f32_e64 v38, 0, v38 clamp ; D1018026 00024C80 v_madmk_f32_e32 v40, v15, v12, 0x3eae6205 ; 2E50190F 3EAE6205 v_mad_f32 v15, v14, v15, v12 ; D1C1000F 04321F0E v_fract_f32_e32 v40, v40 ; 7E503728 v_fract_f32_e32 v15, v15 ; 7E1E370F v_mad_f32 v40, v11, v40, v9 ; D1C10028 0426510B v_mad_f32 v15, v11, v15, v9 ; D1C1000F 04261F0B v_mul_f32_e32 v40, v40, v40 ; 0A505128 v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_mad_f32 v41, v10, v37, v7 ; D1C10029 041E4B0A v_mad_f32 v41, v41, v37, v8 ; D1C10029 04224B29 v_mad_f32 v41, v41, v37, v6 ; D1C10029 041A4B29 v_mad_f32 v41, v37, v41, -s31 ; D1C10029 807E5325 v_mad_f32 v37, v37, v41, s5 ; D1C10025 00165325 v_mad_f32 v41, v10, v0, v7 ; D1C10029 041E010A v_mad_f32 v41, v41, v0, v8 ; D1C10029 04220129 v_mad_f32 v41, v41, v0, v6 ; D1C10029 041A0129 v_mad_f32 v41, v0, v41, -s31 ; D1C10029 807E5300 v_mad_f32 v0, v0, v41, s5 ; D1C10000 00165300 v_mad_f32 v41, v10, v40, v7 ; D1C10029 041E510A v_mad_f32 v41, v41, v40, v8 ; D1C10029 04225129 v_mad_f32 v41, v41, v40, v6 ; D1C10029 041A5129 v_mad_f32 v41, v40, v41, -s31 ; D1C10029 807E5328 v_mad_f32 v40, v40, v41, s5 ; D1C10028 00165328 v_mad_f32 v41, v10, v15, v7 ; D1C10029 041E1F0A v_mad_f32 v41, v41, v15, v8 ; D1C10029 04221F29 v_mad_f32 v41, v41, v15, v6 ; D1C10029 041A1F29 v_mad_f32 v41, v15, v41, -s31 ; D1C10029 807E530F v_mad_f32 v15, v15, v41, s5 ; D1C1000F 0016530F v_madak_f32_e32 v41, -2.0, v38, 0x40400000 ; 30524CF5 40400000 v_mul_f32_e32 v38, v38, v38 ; 0A4C4D26 v_mad_f32 v42, -v38, v41, 1.0 ; D1C1002A 23CA5326 v_mul_f32_e32 v38, v41, v38 ; 0A4C4D29 v_madak_f32_e32 v37, v37, v42, 0x3ecccccd ; 304A5525 3ECCCCCD v_madak_f32_e32 v41, v0, v42, 0x3dcccccd ; 30525500 3DCCCCCD v_mac_f32_e32 v37, v38, v40 ; 2C4A5126 v_mac_f32_e32 v41, v38, v15 ; 2C521F26 v_mov_b32_e32 v15, s45 ; 7E1E022D s_buffer_load_dword s45, s[84:87], 0x10 ; C0220B6A 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v38, s47 ; 7E4C022F s_buffer_load_dword s52, s[84:87], 0x14 ; C0220D2A 00000014 v_mov_b32_e32 v40, s46 ; 7E50022E s_buffer_load_dword s41, s[84:87], 0x18 ; C0220A6A 00000018 v_mov_b32_e32 v42, s39 ; 7E540227 s_buffer_load_dword s39, s[84:87], 0x1c ; C02209EA 0000001C v_mov_b32_e32 v43, s48 ; 7E560230 s_buffer_load_dword s49, s[84:87], 0x20 ; C0220C6A 00000020 v_mov_b32_e32 v0, s76 ; 7E00024C v_sub_f32_e32 v0, s5, v0 ; 04000005 v_mul_f32_e32 v0, s42, v0 ; 0A00002A s_buffer_load_dword s57, s[84:87], 0x24 ; C0220E6A 00000024 v_rcp_f32_e32 v44, v0 ; 7E584500 v_mov_b32_e32 v0, s74 ; 7E00024A v_sub_f32_e32 v0, s5, v0 ; 04000005 v_mul_f32_e32 v0, s43, v0 ; 0A00002B v_rcp_f32_e32 v45, v0 ; 7E5A4500 s_buffer_load_dword s48, s[84:87], 0x28 ; C0220C2A 00000028 v_mov_b32_e32 v0, s73 ; 7E000249 s_buffer_load_dword s42, s[84:87], 0x2c ; C0220AAA 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s55, s[84:87], 0x30 ; C0220DEA 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[84:87], 0x34 ; C0220F6A 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[84:87], 0x38 ; C0220CAA 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[84:87], 0x3c ; C0220AEA 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s56, s[84:87], 0x40 ; C0220E2A 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[84:87], 0x44 ; C0220FAA 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[84:87], 0x48 ; C0220CEA 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[84:87], 0x4c ; C0220B2A 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s58, s[84:87], 0x50 ; C0220EAA 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[84:87], 0x54 ; C0220FEA 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s53, s[84:87], 0x58 ; C0220D6A 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[84:87], 0x5c ; C0220BAA 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s59, s[84:87], 0x60 ; C0220EEA 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[84:87], 0x64 ; C022102A 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[84:87], 0x68 ; C0220DAA 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[84:87], 0x6c ; C0220BEA 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[84:87], 0x70 ; C0220F2A 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[84:87], 0x74 ; C022106A 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[88:91], 0x390 ; C022112C 00000390 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[88:91], 0x394 ; C022116C 00000394 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[84:87], 0x78 ; C02210EA 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[84:87], 0x7c ; C02210AA 0000007C v_add_f32_e32 v18, v18, v18 ; 02242512 v_mul_f32_e32 v46, s92, v23 ; 0A5C2E5C v_mad_f32 v2, s83, v26, v2 ; D1C10002 040A3453 v_mad_f32 v3, s83, v27, v3 ; D1C10003 040E3653 v_mad_f32 v4, s83, v28, v4 ; D1C10004 04123853 v_mad_f32 v26, -s76, v35, v4 ; D1C1001A 2412464C v_mul_f32_e32 v23, s82, v23 ; 0A2E2E52 v_mac_f32_e32 v46, s79, v22 ; 2C5C2C4F v_mac_f32_e32 v23, s81, v22 ; 2C2E2C51 v_mac_f32_e32 v46, s78, v24 ; 2C5C304E v_mac_f32_e32 v23, s80, v24 ; 2C2E3050 v_mac_f32_e32 v46, s77, v25 ; 2C5C324D v_cmp_le_f32_e32 vcc, s73, v26 ; 7C863449 v_cndmask_b32_e64 v22, 0, 1.0, vcc ; D1000016 01A9E480 v_mac_f32_e32 v23, s75, v25 ; 2C2E324B v_mad_f32 v24, -s74, v36, v2 ; D1C10018 240A484A v_mad_f32 v25, -s74, v36, v3 ; D1C10019 240E484A v_mul_f32_e32 v27, v2, v29 ; 0A363B02 v_mac_f32_e32 v27, v3, v31 ; 2C363F03 v_mac_f32_e32 v27, s73, v32 ; 2C364049 v_mul_f32_e32 v28, v2, v2 ; 0A380502 v_mac_f32_e32 v28, v3, v3 ; 2C380703 v_sqrt_f32_e32 v35, v28 ; 7E464F1C v_mac_f32_e32 v28, v4, v4 ; 2C380904 v_rsq_f32_e32 v28, v28 ; 7E38491C v_max_f32_e32 v16, v16, v35 ; 16204710 v_mul_f32_e32 v16, v33, v16 ; 0A202121 v_mul_f32_e32 v26, v26, v44 ; 0A34591A v_min_f32_e32 v28, 0x7f7fffff, v28 ; 143838FF 7F7FFFFF v_max_f32_e32 v17, v28, v17 ; 1622231C v_rcp_f32_e32 v16, v16 ; 7E204510 v_add_f32_e64 v26, 0, v26 clamp ; D101801A 00023480 v_log_f32_e32 v26, v26 ; 7E34431A v_mul_f32_e32 v28, v3, v17 ; 0A382303 v_mul_f32_e32 v33, v4, v17 ; 0A422304 v_mul_f32_e32 v17, v2, v17 ; 0A222302 v_mad_f32 v28, s71, v28, v39 ; D1C1001C 049E3847 v_mad_f32 v33, s71, v33, v39 ; D1C10021 049E4247 v_mac_f32_e32 v39, s71, v17 ; 2C4E2247 v_mul_legacy_f32_e32 v17, s72, v26 ; 08223448 v_mul_f32_e64 v16, v16, |v27| ; D1050210 00023710 v_min_f32_e32 v16, s5, v16 ; 14202005 v_sub_f32_e32 v16, s5, v16 ; 04202005 v_mul_f32_e32 v16, s70, v16 ; 0A202046 v_exp_f32_e32 v17, v17 ; 7E224111 v_mul_f32_e32 v17, s70, v17 ; 0A222246 v_add_f32_e32 v19, v19, v19 ; 02262713 v_add_f32_e32 v20, v20, v20 ; 02282914 v_sub_f32_e32 v21, s5, v21 ; 042A2A05 exp 15, 32, 0, 0, 0, v46, v23, v0, v0 ; C400020F 0000172E v_mac_f32_e32 v28, v13, v34 ; 2C38450D v_mac_f32_e32 v33, v13, v34 ; 2C42450D v_mac_f32_e32 v39, v13, v34 ; 2C4E450D v_mad_f32 v13, v14, v28, v12 ; D1C1000D 0432390E s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v23, v14, v33, v12 ; D1C10017 0432430E v_mac_f32_e32 v12, v14, v39 ; 2C184F0E v_fract_f32_e32 v13, v13 ; 7E1A370D v_fract_f32_e32 v14, v23 ; 7E1C3717 v_fract_f32_e32 v12, v12 ; 7E18370C v_mad_f32 v13, v11, v13, v9 ; D1C1000D 04261B0B v_mad_f32 v14, v11, v14, v9 ; D1C1000E 04261D0B v_mac_f32_e32 v9, v11, v12 ; 2C12190B v_mul_f32_e32 v11, v24, v24 ; 0A163118 v_mac_f32_e32 v11, v25, v25 ; 2C163319 v_sqrt_f32_e32 v11, v11 ; 7E164F0B v_mul_f32_e32 v11, v11, v45 ; 0A165B0B v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mul_f32_e32 v12, v16, v11 ; 0A181710 v_mul_f32_e32 v12, v22, v12 ; 0A181916 v_mul_f32_e32 v16, v29, v17 ; 0A20231D v_mul_f32_e32 v23, v31, v17 ; 0A2E231F v_mul_f32_e32 v17, v32, v17 ; 0A222320 v_mul_f32_e32 v24, v29, v12 ; 0A30191D v_mul_f32_e32 v25, v31, v12 ; 0A32191F v_mul_f32_e32 v12, v32, v12 ; 0A181920 v_mul_f32_e32 v24, v24, v37 ; 0A304B18 v_mul_f32_e32 v25, v25, v37 ; 0A324B19 v_mul_f32_e32 v12, v12, v37 ; 0A184B0C v_log_f32_e32 v11, v11 ; 7E16430B v_mac_f32_e32 v24, v41, v16 ; 2C302129 v_mac_f32_e32 v25, v41, v23 ; 2C322F29 v_mac_f32_e32 v12, v41, v17 ; 2C182329 v_mul_legacy_f32_e32 v11, s40, v11 ; 08161628 v_exp_f32_e32 v11, v11 ; 7E16410B v_mul_f32_e32 v11, s38, v11 ; 0A161626 v_mul_f32_e32 v11, v22, v11 ; 0A161716 v_mul_f32_e32 v13, v13, v13 ; 0A1A1B0D v_mul_f32_e32 v14, v14, v14 ; 0A1C1D0E v_mul_f32_e32 v9, v9, v9 ; 0A121309 v_mad_f32 v16, v10, v13, v7 ; D1C10010 041E1B0A v_mad_f32 v17, v10, v14, v7 ; D1C10011 041E1D0A v_mac_f32_e32 v7, v10, v9 ; 2C0E130A v_mad_f32 v10, v16, v13, v8 ; D1C1000A 04221B10 v_mad_f32 v16, v17, v14, v8 ; D1C10010 04221D11 v_mad_f32 v7, v7, v9, v8 ; D1C10007 04221307 v_mad_f32 v8, v10, v13, v6 ; D1C10008 041A1B0A v_mad_f32 v10, v16, v14, v6 ; D1C1000A 041A1D10 v_mad_f32 v6, v7, v9, v6 ; D1C10006 041A1307 v_mad_f32 v7, v13, v8, -s31 ; D1C10007 807E110D v_mad_f32 v7, v13, v7, s5 ; D1C10007 00160F0D v_mad_f32 v8, v14, v10, -s31 ; D1C10008 807E150E v_mad_f32 v8, v14, v8, s5 ; D1C10008 0016110E v_mad_f32 v6, v9, v6, -s31 ; D1C10006 807E0D09 v_mad_f32 v6, v9, v6, s5 ; D1C10006 00160D09 v_mul_f32_e32 v7, v11, v7 ; 0A0E0F0B v_mul_f32_e32 v8, v11, v8 ; 0A10110B v_mul_f32_e32 v6, v11, v6 ; 0A0C0D0B v_mac_f32_e32 v24, v7, v30 ; 2C303D07 v_mac_f32_e32 v25, v8, v30 ; 2C323D08 v_mac_f32_e32 v12, v6, v30 ; 2C183D06 v_add_f32_e32 v2, v2, v24 ; 02043102 v_add_f32_e32 v3, v3, v25 ; 02063303 v_add_f32_e32 v4, v4, v12 ; 02081904 v_mul_f32_e32 v6, s20, v3 ; 0A0C0614 v_mul_f32_e32 v7, s13, v3 ; 0A0E060D v_mul_f32_e32 v3, s27, v3 ; 0A06061B v_mac_f32_e32 v6, s15, v2 ; 2C0C040F v_mac_f32_e32 v7, s11, v2 ; 2C0E040B v_mac_f32_e32 v3, s23, v2 ; 2C060417 v_mac_f32_e32 v6, s9, v4 ; 2C0C0809 v_mac_f32_e32 v7, s10, v4 ; 2C0E080A v_mac_f32_e32 v3, s22, v4 ; 2C060816 v_mac_f32_e32 v6, s8, v5 ; 2C0C0A08 v_mac_f32_e32 v7, s19, v5 ; 2C0E0A13 v_mac_f32_e32 v3, s21, v5 ; 2C060A15 v_mul_f32_e32 v2, s26, v7 ; 0A040E1A v_mul_f32_e32 v4, s32, v7 ; 0A080E20 v_mul_f32_e32 v5, s7, v7 ; 0A0A0E07 v_mul_f32_e32 v8, s35, v7 ; 0A100E23 v_sub_f32_e32 v9, s12, v6 ; 04120C0C v_sub_f32_e32 v10, s16, v7 ; 04140E10 v_sub_f32_e32 v11, s17, v3 ; 04160611 v_mac_f32_e32 v2, s18, v6 ; 2C040C12 v_mac_f32_e32 v4, s28, v6 ; 2C080C1C v_mac_f32_e32 v5, s37, v6 ; 2C0A0C25 v_mac_f32_e32 v8, s29, v6 ; 2C100C1D v_mul_f32_e32 v9, v9, v9 ; 0A121309 v_mac_f32_e32 v2, s14, v3 ; 2C04060E v_mac_f32_e32 v4, s25, v3 ; 2C080619 v_mac_f32_e32 v5, s4, v3 ; 2C0A0604 v_mac_f32_e32 v8, s33, v3 ; 2C100621 v_mac_f32_e32 v9, v10, v10 ; 2C12150A v_mac_f32_e32 v2, s5, v40 ; 2C045005 v_mac_f32_e32 v4, s5, v38 ; 2C084C05 v_mac_f32_e32 v5, s5, v42 ; 2C0A5405 v_mac_f32_e32 v8, s5, v43 ; 2C105605 v_mac_f32_e32 v9, v11, v11 ; 2C12170B v_sqrt_f32_e32 v9, v9 ; 7E124F09 v_mad_f32 v10, v8, s3, -v5 ; D1C1000A 84140708 s_waitcnt lgkmcnt(0) ; BF8C007F v_mad_f32 v11, s68, v5, v2 ; D1C1000B 040A0A44 v_mad_f32 v12, s69, v5, -v4 ; D1C1000C 84120A45 v_mul_f32_e32 v13, s36, v4 ; 0A1A0824 v_mul_f32_e32 v14, s52, v4 ; 0A1C0834 v_mul_f32_e32 v16, s57, v4 ; 0A200839 v_mul_f32_e32 v17, s61, v4 ; 0A22083D v_mul_f32_e32 v22, s62, v4 ; 0A2C083E v_mul_f32_e32 v23, s63, v4 ; 0A2E083F v_mac_f32_e32 v15, s6, v9 ; 2C1E1206 v_mul_f32_e32 v9, s64, v4 ; 0A120840 v_mul_f32_e32 v4, s65, v4 ; 0A080841 v_mac_f32_e32 v13, s34, v2 ; 2C1A0422 v_mac_f32_e32 v14, s45, v2 ; 2C1C042D v_mac_f32_e32 v16, s49, v2 ; 2C200431 v_mac_f32_e32 v17, s55, v2 ; 2C220437 v_mac_f32_e32 v22, s56, v2 ; 2C2C0438 v_mac_f32_e32 v23, s58, v2 ; 2C2E043A v_mac_f32_e32 v9, s59, v2 ; 2C12043B v_mac_f32_e32 v4, s60, v2 ; 2C08043C v_mac_f32_e32 v13, s30, v8 ; 2C1A101E v_mac_f32_e32 v14, s41, v8 ; 2C1C1029 v_mac_f32_e32 v16, s48, v8 ; 2C201030 v_mac_f32_e32 v17, s50, v8 ; 2C221032 v_mac_f32_e32 v22, s51, v8 ; 2C2C1033 v_mac_f32_e32 v23, s53, v8 ; 2C2E1035 v_mac_f32_e32 v9, s54, v8 ; 2C121036 v_mac_f32_e32 v4, s67, v8 ; 2C081043 v_add_f32_e64 v2, 0, v15 clamp ; D1018002 00021E80 v_min_f32_e32 v2, s2, v2 ; 14040402 v_mac_f32_e32 v13, s24, v5 ; 2C1A0A18 v_mac_f32_e32 v14, s39, v5 ; 2C1C0A27 v_mac_f32_e32 v16, s42, v5 ; 2C200A2A v_cndmask_b32_e64 v15, 0, 1.0, s[0:1] ; D100000F 0001E480 v_mac_f32_e32 v17, s43, v5 ; 2C220A2B v_mac_f32_e32 v22, s44, v5 ; 2C2C0A2C v_mac_f32_e32 v23, s46, v5 ; 2C2E0A2E v_mac_f32_e32 v9, s47, v5 ; 2C120A2F v_log_f32_e32 v18, v18 ; 7E244312 v_log_f32_e32 v19, v19 ; 7E264313 v_log_f32_e32 v20, v20 ; 7E284314 v_mac_f32_e32 v4, s66, v5 ; 2C080A42 v_mul_f32_e32 v18, v1, v18 ; 0A242501 v_mul_f32_e32 v19, v1, v19 ; 0A262701 v_mul_f32_e32 v1, v1, v20 ; 0A022901 v_exp_f32_e32 v18, v18 ; 7E244112 v_exp_f32_e32 v19, v19 ; 7E264113 v_exp_f32_e32 v1, v1 ; 7E024101 v_mul_f32_e32 v20, 0x3e59999a, v18 ; 0A2824FF 3E59999A v_madmk_f32_e32 v20, v19, v20, 0x3f372474 ; 2E282913 3F372474 v_madmk_f32_e32 v20, v1, v20, 0x3d93a92a ; 2E282901 3D93A92A v_mul_f32_e32 v20, v21, v20 ; 0A282915 v_mul_f32_e32 v18, v18, v15 ; 0A241F12 v_mul_f32_e32 v19, v19, v15 ; 0A261F13 v_mul_f32_e32 v1, v1, v15 ; 0A021F01 v_mul_f32_e32 v15, v15, v20 ; 0A1E290F exp 15, 33, 0, 0, 0, v0, v0, v0, v15 ; C400021F 0F000000 exp 15, 34, 0, 0, 0, v0, v0, v0, v2 ; C400022F 02000000 exp 15, 35, 0, 0, 0, v18, v19, v1, v0 ; C400023F 00011312 exp 15, 36, 0, 0, 0, v6, v7, v3, v8 ; C400024F 08030706 exp 15, 12, 0, 0, 0, v11, v12, v10, v5 ; C40000CF 050A0C0B exp 15, 13, 0, 0, 0, v13, v14, v16, v17 ; C40000DF 11100E0D exp 15, 14, 0, 1, 0, v22, v23, v9, v4 ; C40008EF 04091716 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 96 VGPRS: 48 Code Size: 2912 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 6 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL IN[4], GENERIC[4], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..15], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 2.0000, -0.5000} IMM[1] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[2] FLT32 { 0.0005, 0.0000, -0.0005, 0.1250} IMM[3] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[4] FLT32 { 0.2125, 0.7154, 0.0721, 0.5000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: UIF CONST[90].xxxx :0 3: MAD TEMP[1], IN[4].xyzx, IMM[0].xxxy, IMM[0].yyyx 4: DP4 TEMP[2].x, TEMP[1], CONST[69] 5: DP4 TEMP[3].x, TEMP[1], CONST[70] 6: MOV TEMP[2].y, TEMP[3].xxxx 7: MOV_SAT TEMP[4].xy, TEMP[2].xyyy 8: ADD TEMP[4].xy, -TEMP[2].xyyy, TEMP[4].xyyy 9: DP2 TEMP[5].x, TEMP[4].xyyy, IMM[0].xxxx 10: DP4 TEMP[4].x, TEMP[1], CONST[73] 11: DP4 TEMP[6].x, TEMP[1], CONST[74] 12: MOV TEMP[4].y, TEMP[6].xxxx 13: MOV_SAT TEMP[7].xy, TEMP[4].xyyy 14: ADD TEMP[7].xy, -TEMP[4].xyyy, TEMP[7].xyyy 15: DP2 TEMP[8].x, TEMP[7].xyyy, IMM[0].xxxx 16: MOV TEMP[4].w, TEMP[8].xxxx 17: DP4 TEMP[7].x, TEMP[1], CONST[77] 18: DP4 TEMP[9].x, TEMP[1], CONST[78] 19: MOV TEMP[4].z, IMM[0].xxxx 20: MOV TEMP[10].w, TEMP[4] 21: ABS TEMP[11].x, TEMP[8].xxxx 22: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 23: UIF TEMP[11].xxxx :0 24: MOV TEMP[11].x, TEMP[4].xxxx 25: ELSE :0 26: MOV TEMP[11].x, TEMP[7].xxxx 27: ENDIF 28: MOV TEMP[10].x, TEMP[11].xxxx 29: ABS TEMP[11].x, TEMP[8].xxxx 30: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 31: UIF TEMP[11].xxxx :0 32: MOV TEMP[6].x, TEMP[6].xxxx 33: ELSE :0 34: MOV TEMP[6].x, TEMP[9].xxxx 35: ENDIF 36: MOV TEMP[10].y, TEMP[6].xxxx 37: ABS TEMP[6].x, TEMP[8].xxxx 38: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 39: UIF TEMP[6].xxxx :0 40: MOV TEMP[6].x, IMM[0].xxxx 41: ELSE :0 42: MOV TEMP[6].x, IMM[0].zzzz 43: ENDIF 44: MOV TEMP[10].z, TEMP[6].xxxx 45: MOV TEMP[4].xyz, TEMP[10] 46: ABS TEMP[6].x, TEMP[5].xxxx 47: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 48: UIF TEMP[6].xxxx :0 49: MOV TEMP[6].x, TEMP[2].xxxx 50: ELSE :0 51: MOV TEMP[6].x, TEMP[4].xxxx 52: ENDIF 53: MOV TEMP[10].x, TEMP[6].xxxx 54: ABS TEMP[6].x, TEMP[5].xxxx 55: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 56: UIF TEMP[6].xxxx :0 57: MOV TEMP[3].x, TEMP[3].xxxx 58: ELSE :0 59: MOV TEMP[3].x, TEMP[4].yyyy 60: ENDIF 61: MOV TEMP[10].y, TEMP[3].xxxx 62: ABS TEMP[3].x, TEMP[5].xxxx 63: FSGE TEMP[3].x, -TEMP[3].xxxx, IMM[0].yyyy 64: UIF TEMP[3].xxxx :0 65: MOV TEMP[3].x, IMM[0].yyyy 66: ELSE :0 67: MOV TEMP[3].x, TEMP[4].zzzz 68: ENDIF 69: MOV TEMP[10].z, TEMP[3].xxxx 70: MOV TEMP[2].z, TEMP[10].xyzx 71: DP4 TEMP[5].x, TEMP[1], CONST[71] 72: MOV TEMP[4].z, TEMP[5].xxxx 73: ADD TEMP[7].xy, TEMP[10].xyyy, IMM[0].wwww 74: ABS TEMP[6].xy, TEMP[7].xyyy 75: ADD TEMP[7].xy, TEMP[6].xyyy, -CONST[67].zzzz 76: MUL TEMP[7].xy, TEMP[7].xyyy, CONST[67].wwww 77: MOV_SAT TEMP[6].xy, TEMP[7].xyyy 78: ADD TEMP[7].xy, -TEMP[6].xyyy, IMM[0].xxxx 79: MUL TEMP[6].x, TEMP[7].yyyy, TEMP[7].xxxx 80: MOV_SAT TEMP[8].xy, TEMP[10].xyyy 81: ADD TEMP[7].xyz, TEMP[3].xxxx, IMM[1].xyzz 82: MOV TEMP[3].y, IMM[0].yyyy 83: ABS TEMP[11].x, TEMP[7].xxxx 84: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 85: UIF TEMP[11].xxxx :0 86: MOV TEMP[11].x, CONST[85].zzzz 87: ELSE :0 88: MOV TEMP[11].x, IMM[0].yyyy 89: ENDIF 90: ABS TEMP[12].x, TEMP[7].xxxx 91: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 92: UIF TEMP[12].xxxx :0 93: MOV TEMP[12].x, CONST[85].wwww 94: ELSE :0 95: MOV TEMP[12].x, IMM[0].yyyy 96: ENDIF 97: MOV TEMP[10].y, TEMP[12].xxxx 98: ABS TEMP[12].x, TEMP[7].xxxx 99: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 100: UIF TEMP[12].xxxx :0 101: MOV TEMP[12].x, CONST[85].xxxx 102: ELSE :0 103: MOV TEMP[12].x, IMM[0].yyyy 104: ENDIF 105: MOV TEMP[10].z, TEMP[12].xxxx 106: ABS TEMP[12].x, TEMP[7].xxxx 107: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 108: UIF TEMP[12].xxxx :0 109: MOV TEMP[12].x, CONST[85].yyyy 110: ELSE :0 111: MOV TEMP[12].x, IMM[0].yyyy 112: ENDIF 113: MOV TEMP[10].w, TEMP[12].xxxx 114: ABS TEMP[12].x, TEMP[7].yyyy 115: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 116: UIF TEMP[12].xxxx :0 117: MOV TEMP[12].x, CONST[86].zzzz 118: ELSE :0 119: MOV TEMP[12].x, TEMP[11].xxxx 120: ENDIF 121: MOV TEMP[10].x, TEMP[12].xxxx 122: ABS TEMP[11].x, TEMP[7].yyyy 123: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 124: UIF TEMP[11].xxxx :0 125: MOV TEMP[11].x, CONST[86].wwww 126: ELSE :0 127: MOV TEMP[11].x, TEMP[10].yyyy 128: ENDIF 129: MOV TEMP[10].y, TEMP[11].xxxx 130: ABS TEMP[11].x, TEMP[7].yyyy 131: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 132: UIF TEMP[11].xxxx :0 133: MOV TEMP[11].x, CONST[86].xxxx 134: ELSE :0 135: MOV TEMP[11].x, TEMP[10].zzzz 136: ENDIF 137: MOV TEMP[10].z, TEMP[11].xxxx 138: ABS TEMP[11].x, TEMP[7].yyyy 139: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 140: UIF TEMP[11].xxxx :0 141: MOV TEMP[11].x, CONST[86].yyyy 142: ELSE :0 143: MOV TEMP[11].x, TEMP[10].wwww 144: ENDIF 145: MOV TEMP[10].w, TEMP[11].xxxx 146: MOV TEMP[9], TEMP[10] 147: ABS TEMP[11].x, TEMP[7].zzzz 148: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 149: UIF TEMP[11].xxxx :0 150: MOV TEMP[11].x, CONST[87].zzzz 151: ELSE :0 152: MOV TEMP[11].x, TEMP[9].xxxx 153: ENDIF 154: MOV TEMP[10].x, TEMP[11].xxxx 155: ABS TEMP[11].x, TEMP[7].zzzz 156: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 157: UIF TEMP[11].xxxx :0 158: MOV TEMP[11].x, CONST[87].wwww 159: ELSE :0 160: MOV TEMP[11].x, TEMP[9].yyyy 161: ENDIF 162: MOV TEMP[10].y, TEMP[11].xxxx 163: ABS TEMP[11].x, TEMP[7].zzzz 164: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 165: UIF TEMP[11].xxxx :0 166: MOV TEMP[11].x, CONST[87].xxxx 167: ELSE :0 168: MOV TEMP[11].x, TEMP[9].zzzz 169: ENDIF 170: MOV TEMP[10].z, TEMP[11].xxxx 171: ABS TEMP[11].x, TEMP[7].zzzz 172: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 173: UIF TEMP[11].xxxx :0 174: MOV TEMP[11].x, CONST[87].yyyy 175: ELSE :0 176: MOV TEMP[11].x, TEMP[9].wwww 177: ENDIF 178: MOV TEMP[10].w, TEMP[11].xxxx 179: MAD TEMP[4].xy, TEMP[8].xyyy, TEMP[10].xyyy, TEMP[10].zwww 180: MOV TEMP[4].w, IMM[0].yyyy 181: ADD TEMP[7], TEMP[4], IMM[2].xxyy 182: TXL TEMP[8].x, TEMP[7], SAMP[1], SHADOW2D 183: MOV TEMP[7].x, TEMP[8].xxxx 184: ADD TEMP[9], TEMP[4], IMM[2].zxyy 185: ADD TEMP[8], TEMP[4], IMM[2].xzyy 186: ADD TEMP[11], TEMP[4], IMM[2].zzyy 187: TXL TEMP[12].x, TEMP[9], SAMP[1], SHADOW2D 188: MOV TEMP[7].y, TEMP[12].xxxx 189: TXL TEMP[12].x, TEMP[8], SAMP[1], SHADOW2D 190: MOV TEMP[7].z, TEMP[12].xxxx 191: TXL TEMP[12].x, TEMP[11], SAMP[1], SHADOW2D 192: MOV TEMP[7].w, TEMP[12].xxxx 193: DP4 TEMP[12].x, TEMP[7], IMM[1].wwww 194: ADD TEMP[7], TEMP[4], IMM[2].xyyy 195: TXL TEMP[13].x, TEMP[7], SAMP[1], SHADOW2D 196: MOV TEMP[7].x, TEMP[13].xxxx 197: ADD TEMP[9], TEMP[4], IMM[2].zyyy 198: TXL TEMP[13], TEMP[9], SAMP[1], SHADOW2D 199: MOV TEMP[9], TEMP[13] 200: ADD TEMP[8], TEMP[4], IMM[2].yzyy 201: TXL TEMP[14], TEMP[8], SAMP[1], SHADOW2D 202: MOV TEMP[8], TEMP[14] 203: ADD TEMP[11], TEMP[4], IMM[2].yxyy 204: TXL TEMP[15], TEMP[11], SAMP[1], SHADOW2D 205: MOV TEMP[11], TEMP[15] 206: MOV TEMP[7].y, TEMP[13].xxxx 207: MOV TEMP[7].z, TEMP[14].xxxx 208: MOV TEMP[7].w, TEMP[15].xxxx 209: DP4 TEMP[13].x, TEMP[7], IMM[2].wwww 210: MOV TEMP[2].y, TEMP[13].xxxx 211: MOV TEMP[14].xy, TEMP[4].xyyy 212: MOV TEMP[14].z, TEMP[5].xxxx 213: MOV TEMP[14].w, IMM[0].yyyy 214: TXL TEMP[14], TEMP[14], SAMP[1], SHADOW2D 215: MOV TEMP[7].xyz, TEMP[14] 216: ADD TEMP[2].x, TEMP[13].xxxx, TEMP[12].xxxx 217: MAD TEMP[2].x, TEMP[14].xxxx, IMM[3].xxxx, TEMP[2].xxxx 218: FSLT TEMP[12].x, TEMP[6].xxxx, IMM[0].xxxx 219: UIF TEMP[12].xxxx :0 220: ADD TEMP[7].xyz, TEMP[2].zzzz, IMM[3].yzww 221: ABS TEMP[12].x, TEMP[7].xxxx 222: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 223: UIF TEMP[12].xxxx :0 224: MOV TEMP[12].x, CONST[73].xxxx 225: ELSE :0 226: MOV TEMP[12].x, IMM[0].yyyy 227: ENDIF 228: MOV TEMP[10].x, TEMP[12].xxxx 229: ABS TEMP[12].x, TEMP[7].xxxx 230: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 231: UIF TEMP[12].xxxx :0 232: MOV TEMP[12].x, CONST[73].yyyy 233: ELSE :0 234: MOV TEMP[12].x, IMM[0].yyyy 235: ENDIF 236: MOV TEMP[10].y, TEMP[12].xxxx 237: ABS TEMP[12].x, TEMP[7].xxxx 238: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 239: UIF TEMP[12].xxxx :0 240: MOV TEMP[12].x, CONST[73].zzzz 241: ELSE :0 242: MOV TEMP[12].x, IMM[0].yyyy 243: ENDIF 244: MOV TEMP[10].z, TEMP[12].xxxx 245: ABS TEMP[12].x, TEMP[7].xxxx 246: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 247: UIF TEMP[12].xxxx :0 248: MOV TEMP[12].x, CONST[73].wwww 249: ELSE :0 250: MOV TEMP[12].x, IMM[0].yyyy 251: ENDIF 252: MOV TEMP[10].w, TEMP[12].xxxx 253: MOV TEMP[9], TEMP[10] 254: ABS TEMP[12].x, TEMP[7].xxxx 255: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 256: UIF TEMP[12].xxxx :0 257: MOV TEMP[12].x, CONST[74].xxxx 258: ELSE :0 259: MOV TEMP[12].x, IMM[0].yyyy 260: ENDIF 261: MOV TEMP[10].x, TEMP[12].xxxx 262: ABS TEMP[12].x, TEMP[7].xxxx 263: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 264: UIF TEMP[12].xxxx :0 265: MOV TEMP[12].x, CONST[74].yyyy 266: ELSE :0 267: MOV TEMP[12].x, IMM[0].yyyy 268: ENDIF 269: MOV TEMP[10].y, TEMP[12].xxxx 270: ABS TEMP[12].x, TEMP[7].xxxx 271: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 272: UIF TEMP[12].xxxx :0 273: MOV TEMP[12].x, CONST[74].zzzz 274: ELSE :0 275: MOV TEMP[12].x, IMM[0].yyyy 276: ENDIF 277: MOV TEMP[10].z, TEMP[12].xxxx 278: ABS TEMP[12].x, TEMP[7].xxxx 279: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 280: UIF TEMP[12].xxxx :0 281: MOV TEMP[12].x, CONST[74].wwww 282: ELSE :0 283: MOV TEMP[12].x, IMM[0].yyyy 284: ENDIF 285: MOV TEMP[10].w, TEMP[12].xxxx 286: MOV TEMP[8], TEMP[10] 287: ABS TEMP[12].x, TEMP[7].yyyy 288: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 289: UIF TEMP[12].xxxx :0 290: MOV TEMP[12].x, CONST[77].xxxx 291: ELSE :0 292: MOV TEMP[12].x, TEMP[9].xxxx 293: ENDIF 294: MOV TEMP[10].x, TEMP[12].xxxx 295: ABS TEMP[12].x, TEMP[7].yyyy 296: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 297: UIF TEMP[12].xxxx :0 298: MOV TEMP[12].x, CONST[77].yyyy 299: ELSE :0 300: MOV TEMP[12].x, TEMP[9].yyyy 301: ENDIF 302: MOV TEMP[10].y, TEMP[12].xxxx 303: ABS TEMP[12].x, TEMP[7].yyyy 304: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 305: UIF TEMP[12].xxxx :0 306: MOV TEMP[12].x, CONST[77].zzzz 307: ELSE :0 308: MOV TEMP[12].x, TEMP[9].zzzz 309: ENDIF 310: MOV TEMP[10].z, TEMP[12].xxxx 311: ABS TEMP[12].x, TEMP[7].yyyy 312: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 313: UIF TEMP[12].xxxx :0 314: MOV TEMP[12].x, CONST[77].wwww 315: ELSE :0 316: MOV TEMP[12].x, TEMP[9].wwww 317: ENDIF 318: MOV TEMP[10].w, TEMP[12].xxxx 319: MOV TEMP[9], TEMP[10] 320: ABS TEMP[12].x, TEMP[7].yyyy 321: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 322: UIF TEMP[12].xxxx :0 323: MOV TEMP[12].x, CONST[78].xxxx 324: ELSE :0 325: MOV TEMP[12].x, TEMP[8].xxxx 326: ENDIF 327: MOV TEMP[10].x, TEMP[12].xxxx 328: ABS TEMP[12].x, TEMP[7].yyyy 329: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 330: UIF TEMP[12].xxxx :0 331: MOV TEMP[12].x, CONST[78].yyyy 332: ELSE :0 333: MOV TEMP[12].x, TEMP[8].yyyy 334: ENDIF 335: MOV TEMP[10].y, TEMP[12].xxxx 336: ABS TEMP[12].x, TEMP[7].yyyy 337: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 338: UIF TEMP[12].xxxx :0 339: MOV TEMP[12].x, CONST[78].zzzz 340: ELSE :0 341: MOV TEMP[12].x, TEMP[8].zzzz 342: ENDIF 343: MOV TEMP[10].z, TEMP[12].xxxx 344: ABS TEMP[12].x, TEMP[7].yyyy 345: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 346: UIF TEMP[12].xxxx :0 347: MOV TEMP[12].x, CONST[78].wwww 348: ELSE :0 349: MOV TEMP[12].x, TEMP[8].wwww 350: ENDIF 351: MOV TEMP[10].w, TEMP[12].xxxx 352: MOV TEMP[8], TEMP[10] 353: ABS TEMP[12].x, TEMP[7].zzzz 354: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 355: UIF TEMP[12].xxxx :0 356: MOV TEMP[12].x, CONST[81].xxxx 357: ELSE :0 358: MOV TEMP[12].x, TEMP[9].xxxx 359: ENDIF 360: MOV TEMP[10].x, TEMP[12].xxxx 361: ABS TEMP[12].x, TEMP[7].zzzz 362: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 363: UIF TEMP[12].xxxx :0 364: MOV TEMP[12].x, CONST[81].yyyy 365: ELSE :0 366: MOV TEMP[12].x, TEMP[9].yyyy 367: ENDIF 368: MOV TEMP[10].y, TEMP[12].xxxx 369: ABS TEMP[12].x, TEMP[7].zzzz 370: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 371: UIF TEMP[12].xxxx :0 372: MOV TEMP[12].x, CONST[81].zzzz 373: ELSE :0 374: MOV TEMP[12].x, TEMP[9].zzzz 375: ENDIF 376: MOV TEMP[10].z, TEMP[12].xxxx 377: ABS TEMP[12].x, TEMP[7].zzzz 378: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 379: UIF TEMP[12].xxxx :0 380: MOV TEMP[12].x, CONST[81].wwww 381: ELSE :0 382: MOV TEMP[12].x, TEMP[9].wwww 383: ENDIF 384: MOV TEMP[10].w, TEMP[12].xxxx 385: MOV TEMP[9], TEMP[10] 386: ABS TEMP[12].x, TEMP[7].zzzz 387: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 388: UIF TEMP[12].xxxx :0 389: MOV TEMP[12].x, CONST[82].xxxx 390: ELSE :0 391: MOV TEMP[12].x, TEMP[8].xxxx 392: ENDIF 393: MOV TEMP[10].x, TEMP[12].xxxx 394: ABS TEMP[12].x, TEMP[7].zzzz 395: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 396: UIF TEMP[12].xxxx :0 397: MOV TEMP[12].x, CONST[82].yyyy 398: ELSE :0 399: MOV TEMP[12].x, TEMP[8].yyyy 400: ENDIF 401: MOV TEMP[10].y, TEMP[12].xxxx 402: ABS TEMP[12].x, TEMP[7].zzzz 403: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 404: UIF TEMP[12].xxxx :0 405: MOV TEMP[12].x, CONST[82].zzzz 406: ELSE :0 407: MOV TEMP[12].x, TEMP[8].zzzz 408: ENDIF 409: MOV TEMP[10].z, TEMP[12].xxxx 410: ABS TEMP[12].x, TEMP[7].zzzz 411: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 412: UIF TEMP[12].xxxx :0 413: MOV TEMP[12].x, CONST[82].wwww 414: ELSE :0 415: MOV TEMP[12].x, TEMP[8].wwww 416: ENDIF 417: MOV TEMP[10].w, TEMP[12].xxxx 418: DP4 TEMP[9].x, TEMP[1], TEMP[9] 419: MOV_SAT TEMP[9].x, TEMP[9].xxxx 420: DP4 TEMP[12].x, TEMP[1], TEMP[10] 421: MOV_SAT TEMP[12].x, TEMP[12].xxxx 422: MOV TEMP[9].y, TEMP[12].xxxx 423: ABS TEMP[12].x, TEMP[7].xxxx 424: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 425: UIF TEMP[12].xxxx :0 426: MOV TEMP[12].x, CONST[86].zzzz 427: ELSE :0 428: MOV TEMP[12].x, IMM[0].yyyy 429: ENDIF 430: ABS TEMP[13].x, TEMP[7].xxxx 431: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 432: UIF TEMP[13].xxxx :0 433: MOV TEMP[13].x, CONST[86].wwww 434: ELSE :0 435: MOV TEMP[13].x, IMM[0].yyyy 436: ENDIF 437: MOV TEMP[10].y, TEMP[13].xxxx 438: ABS TEMP[13].x, TEMP[7].xxxx 439: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 440: UIF TEMP[13].xxxx :0 441: MOV TEMP[13].x, CONST[86].xxxx 442: ELSE :0 443: MOV TEMP[13].x, IMM[0].yyyy 444: ENDIF 445: MOV TEMP[10].z, TEMP[13].xxxx 446: ABS TEMP[13].x, TEMP[7].xxxx 447: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 448: UIF TEMP[13].xxxx :0 449: MOV TEMP[13].x, CONST[86].yyyy 450: ELSE :0 451: MOV TEMP[13].x, IMM[0].yyyy 452: ENDIF 453: MOV TEMP[10].w, TEMP[13].xxxx 454: ABS TEMP[13].x, TEMP[7].yyyy 455: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 456: UIF TEMP[13].xxxx :0 457: MOV TEMP[13].x, CONST[87].zzzz 458: ELSE :0 459: MOV TEMP[13].x, TEMP[12].xxxx 460: ENDIF 461: ABS TEMP[12].x, TEMP[7].yyyy 462: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 463: UIF TEMP[12].xxxx :0 464: MOV TEMP[12].x, CONST[87].wwww 465: ELSE :0 466: MOV TEMP[12].x, TEMP[10].yyyy 467: ENDIF 468: MOV TEMP[10].y, TEMP[12].xxxx 469: ABS TEMP[12].x, TEMP[7].yyyy 470: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 471: UIF TEMP[12].xxxx :0 472: MOV TEMP[12].x, CONST[87].xxxx 473: ELSE :0 474: MOV TEMP[12].x, TEMP[10].zzzz 475: ENDIF 476: MOV TEMP[10].z, TEMP[12].xxxx 477: ABS TEMP[12].x, TEMP[7].yyyy 478: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 479: UIF TEMP[12].xxxx :0 480: MOV TEMP[12].x, CONST[87].yyyy 481: ELSE :0 482: MOV TEMP[12].x, TEMP[10].wwww 483: ENDIF 484: MOV TEMP[10].w, TEMP[12].xxxx 485: ABS TEMP[12].x, TEMP[7].zzzz 486: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 487: UIF TEMP[12].xxxx :0 488: MOV TEMP[12].x, CONST[88].zzzz 489: ELSE :0 490: MOV TEMP[12].x, TEMP[13].xxxx 491: ENDIF 492: MOV TEMP[10].x, TEMP[12].xxxx 493: ABS TEMP[12].x, TEMP[7].zzzz 494: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 495: UIF TEMP[12].xxxx :0 496: MOV TEMP[12].x, CONST[88].wwww 497: ELSE :0 498: MOV TEMP[12].x, TEMP[10].yyyy 499: ENDIF 500: MOV TEMP[10].y, TEMP[12].xxxx 501: ABS TEMP[12].x, TEMP[7].zzzz 502: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 503: UIF TEMP[12].xxxx :0 504: MOV TEMP[12].x, CONST[88].xxxx 505: ELSE :0 506: MOV TEMP[12].x, TEMP[10].zzzz 507: ENDIF 508: MOV TEMP[10].z, TEMP[12].xxxx 509: ABS TEMP[12].x, TEMP[7].zzzz 510: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 511: UIF TEMP[12].xxxx :0 512: MOV TEMP[12].x, CONST[88].yyyy 513: ELSE :0 514: MOV TEMP[12].x, TEMP[10].wwww 515: ENDIF 516: MOV TEMP[10].w, TEMP[12].xxxx 517: MAD TEMP[4].xy, TEMP[9].xyyy, TEMP[10].xyyy, TEMP[10].zwww 518: ADD TEMP[1], TEMP[4], IMM[2].xxyy 519: TXL TEMP[10].x, TEMP[1], SAMP[1], SHADOW2D 520: MOV TEMP[1].x, TEMP[10].xxxx 521: ADD TEMP[3], TEMP[4], IMM[2].zxyy 522: ADD TEMP[9], TEMP[4], IMM[2].xzyy 523: ADD TEMP[8], TEMP[4], IMM[2].zzyy 524: TXL TEMP[10].x, TEMP[3], SAMP[1], SHADOW2D 525: MOV TEMP[1].y, TEMP[10].xxxx 526: TXL TEMP[10].x, TEMP[9], SAMP[1], SHADOW2D 527: MOV TEMP[1].z, TEMP[10].xxxx 528: TXL TEMP[10].x, TEMP[8], SAMP[1], SHADOW2D 529: MOV TEMP[1].w, TEMP[10].xxxx 530: DP4 TEMP[10].x, TEMP[1], IMM[1].wwww 531: ADD TEMP[3], TEMP[4], IMM[2].xyyy 532: TXL TEMP[12].x, TEMP[3], SAMP[1], SHADOW2D 533: MOV TEMP[3].x, TEMP[12].xxxx 534: ADD TEMP[9], TEMP[4], IMM[2].zyyy 535: TXL TEMP[9].x, TEMP[9], SAMP[1], SHADOW2D 536: ADD TEMP[8], TEMP[4], IMM[2].yzyy 537: TXL TEMP[8].x, TEMP[8], SAMP[1], SHADOW2D 538: ADD TEMP[11], TEMP[4], IMM[2].yxyy 539: TXL TEMP[11].x, TEMP[11], SAMP[1], SHADOW2D 540: MOV TEMP[3].y, TEMP[9].xxxx 541: MOV TEMP[3].z, TEMP[8].xxxx 542: MOV TEMP[3].w, TEMP[11].xxxx 543: DP4 TEMP[3].x, TEMP[3], IMM[2].wwww 544: MOV TEMP[8].xy, TEMP[4].xyyy 545: MOV TEMP[8].z, TEMP[5].xxxx 546: MOV TEMP[8].w, IMM[0].yyyy 547: TXL TEMP[5].x, TEMP[8], SAMP[1], SHADOW2D 548: ADD TEMP[1].x, TEMP[3].xxxx, TEMP[10].xxxx 549: MAD TEMP[1].x, TEMP[5].xxxx, IMM[3].xxxx, TEMP[1].xxxx 550: FSGE TEMP[3].x, TEMP[7].zzzz, IMM[0].yyyy 551: UIF TEMP[3].xxxx :0 552: MOV TEMP[3].x, IMM[0].xxxx 553: ELSE :0 554: MOV TEMP[3].x, TEMP[1].xxxx 555: ENDIF 556: LRP TEMP[4].x, TEMP[6].xxxx, TEMP[2].xxxx, TEMP[3].xxxx 557: MOV TEMP[2].x, TEMP[4].xxxx 558: ENDIF 559: ADD TEMP[1].xyz, -CONST[89].xyzz, IN[4].xyzz 560: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz 561: MAD TEMP[1].x, TEMP[3].xxxx, CONST[68].yyyy, CONST[68].xxxx 562: MOV_SAT TEMP[3].x, TEMP[1].xxxx 563: LRP TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[2].xxxx 564: ELSE :0 565: MOV TEMP[4].x, IMM[0].xxxx 566: ENDIF 567: MAD TEMP[1].xyz, IN[1].xyzz, TEMP[4].xxxx, IN[3].xyzz 568: UIF CONST[90].xxxx :0 569: DP3 TEMP[3].x, TEMP[1].xyzz, IMM[4].xyzz 570: RCP TEMP[3].x, TEMP[3].xxxx 571: MUL TEMP[3].x, TEMP[3].xxxx, IN[1].wwww 572: ADD TEMP[2].x, -TEMP[4].xxxx, IMM[0].xxxx 573: MAD TEMP[3].x, TEMP[3].xxxx, -TEMP[2].xxxx, IMM[0].xxxx 574: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[1].zyxx 575: MAD TEMP[3].x, TEMP[3].xxxx, IMM[4].wwww, IMM[4].wwww 576: LRP TEMP[1].xyz, TEMP[3].xxxx, TEMP[2].zyxx, TEMP[2].xyzz 577: ENDIF 578: ADD TEMP[3].x, TEMP[0].wwww, IMM[1].yyyy 579: MAD TEMP[3].x, CONST[20].wwww, TEMP[3].xxxx, IMM[0].xxxx 580: ADD TEMP[4].x, TEMP[0].wwww, CONST[12].xxxx 581: ADD TEMP[2].xyz, IMM[1].yyyy, CONST[1].xyzz 582: MOV_SAT TEMP[4].x, TEMP[4].xxxx 583: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, IMM[0].xxxx 584: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xyzz 585: MUL TEMP[3].x, TEMP[3].xxxx, CONST[1].wwww 586: MAD TEMP[4].x, TEMP[3].xxxx, IN[3].wwww, -TEMP[3].xxxx 587: MAD TEMP[3].x, CONST[12].wwww, TEMP[4].xxxx, TEMP[3].xxxx 588: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz 589: ABS TEMP[1].x, CONST[12].yyyy 590: MUL TEMP[4].xyz, TEMP[0].xyzz, CONST[30].xxxx 591: MUL TEMP[2].x, CONST[29].wwww, IN[4].wwww 592: FSGE TEMP[5].x, -TEMP[1].xxxx, IMM[0].yyyy 593: UIF TEMP[5].xxxx :0 594: MOV TEMP[3].x, TEMP[3].xxxx 595: ELSE :0 596: MOV TEMP[3].x, TEMP[2].xxxx 597: ENDIF 598: MOV TEMP[1].w, TEMP[3].xxxx 599: MUL TEMP[2].x, IN[2].wwww, IN[2].wwww 600: MAD TEMP[0].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz 601: MAD TEMP[1].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[4].xyzz 602: MOV OUT[0], TEMP[1] 603: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 204) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 332) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 476) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %82 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %83 = load <8 x i32>, <8 x i32> addrspace(2)* %82, align 32, !tbaa !0 %84 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %85 = load <4 x i32>, <4 x i32> addrspace(2)* %84, align 16, !tbaa !0 %86 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %87 = load <8 x i32>, <8 x i32> addrspace(2)* %86, align 32, !tbaa !0 %88 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %89 = load <4 x i32>, <4 x i32> addrspace(2)* %88, align 16, !tbaa !0 %90 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %91 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %92 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %93 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %94 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %95 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %96 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %97 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %98 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %99 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %8) %100 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %6, <2 x i32> %8) %101 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %8) %102 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %8) %103 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %8) %104 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %6, <2 x i32> %8) %105 = bitcast float %90 to i32 %106 = bitcast float %91 to i32 %107 = insertelement <2 x i32> undef, i32 %105, i32 0 %108 = insertelement <2 x i32> %107, i32 %106, i32 1 %109 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %108, <8 x i32> %83, <4 x i32> %85, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %110 = extractelement <4 x float> %109, i32 0 %111 = extractelement <4 x float> %109, i32 1 %112 = extractelement <4 x float> %109, i32 2 %113 = extractelement <4 x float> %109, i32 3 %114 = bitcast float %81 to i32 %115 = icmp eq i32 %114, 0 br i1 %115, label %ENDIF, label %IF IF: ; preds = %main_body %116 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %117 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %118 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %119 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %120 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %121 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %122 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %123 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %124 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %125 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %126 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %127 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %128 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %129 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %130 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %131 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %132 = fadd float %101, 0.000000e+00 %133 = fadd float %102, 0.000000e+00 %134 = fadd float %103, 0.000000e+00 %135 = fmul float %101, 0.000000e+00 %136 = fadd float %135, 1.000000e+00 %137 = fmul float %132, %131 %138 = fmul float %133, %130 %139 = fadd float %137, %138 %140 = fmul float %134, %129 %141 = fadd float %139, %140 %142 = fmul float %136, %128 %143 = fadd float %141, %142 %144 = fmul float %132, %127 %145 = fmul float %133, %126 %146 = fadd float %144, %145 %147 = fmul float %134, %125 %148 = fadd float %146, %147 %149 = fmul float %136, %124 %150 = fadd float %148, %149 %151 = call float @llvm.AMDIL.clamp.(float %143, float 0.000000e+00, float 1.000000e+00) %152 = call float @llvm.AMDIL.clamp.(float %150, float 0.000000e+00, float 1.000000e+00) %153 = fsub float %151, %143 %154 = fsub float %152, %150 %155 = fadd float %153, %154 %156 = fmul float %132, %42 %157 = fmul float %133, %43 %158 = fadd float %156, %157 %159 = fmul float %134, %44 %160 = fadd float %158, %159 %161 = fmul float %136, %45 %162 = fadd float %160, %161 %163 = fmul float %132, %46 %164 = fmul float %133, %47 %165 = fadd float %163, %164 %166 = fmul float %134, %48 %167 = fadd float %165, %166 %168 = fmul float %136, %49 %169 = fadd float %167, %168 %170 = call float @llvm.AMDIL.clamp.(float %162, float 0.000000e+00, float 1.000000e+00) %171 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00) %172 = fsub float %170, %162 %173 = fsub float %171, %169 %174 = fadd float %172, %173 %175 = fmul float %132, %50 %176 = fmul float %133, %51 %177 = fadd float %175, %176 %178 = fmul float %134, %52 %179 = fadd float %177, %178 %180 = fmul float %136, %53 %181 = fadd float %179, %180 %182 = fmul float %132, %54 %183 = fmul float %133, %55 %184 = fadd float %182, %183 %185 = fmul float %134, %56 %186 = fadd float %184, %185 %187 = fmul float %136, %57 %188 = fadd float %186, %187 %189 = call float @llvm.fabs.f32(float %174) %190 = fcmp ole float %189, -0.000000e+00 %. = select i1 %190, float %162, float %181 %191 = call float @llvm.fabs.f32(float %174) %192 = fcmp ole float %191, -0.000000e+00 %temp24.0 = select i1 %192, float %169, float %188 %193 = call float @llvm.fabs.f32(float %174) %194 = fcmp ole float %193, -0.000000e+00 %.238 = select i1 %194, float 1.000000e+00, float 2.000000e+00 %195 = call float @llvm.fabs.f32(float %155) %196 = fcmp ole float %195, -0.000000e+00 %temp24.2 = select i1 %196, float %143, float %. %197 = call float @llvm.fabs.f32(float %155) %198 = fcmp ole float %197, -0.000000e+00 %.temp24.0 = select i1 %198, float %150, float %temp24.0 %199 = call float @llvm.fabs.f32(float %155) %200 = fcmp ole float %199, -0.000000e+00 %temp12.1 = select i1 %200, float 0.000000e+00, float %.238 %201 = fmul float %132, %123 %202 = fmul float %133, %122 %203 = fadd float %201, %202 %204 = fmul float %134, %121 %205 = fadd float %203, %204 %206 = fmul float %136, %120 %207 = fadd float %205, %206 %208 = fadd float %temp24.2, -5.000000e-01 %209 = fadd float %.temp24.0, -5.000000e-01 %210 = call float @llvm.fabs.f32(float %208) %211 = call float @llvm.fabs.f32(float %209) %212 = fsub float %210, %38 %213 = fsub float %211, %38 %214 = fmul float %212, %39 %215 = fmul float %213, %39 %216 = call float @llvm.AMDIL.clamp.(float %214, float 0.000000e+00, float 1.000000e+00) %217 = call float @llvm.AMDIL.clamp.(float %215, float 0.000000e+00, float 1.000000e+00) %218 = fsub float 1.000000e+00, %216 %219 = fsub float 1.000000e+00, %217 %220 = fmul float %219, %218 %221 = call float @llvm.AMDIL.clamp.(float %temp24.2, float 0.000000e+00, float 1.000000e+00) %222 = call float @llvm.AMDIL.clamp.(float %.temp24.0, float 0.000000e+00, float 1.000000e+00) %223 = fadd float %temp12.1, -1.000000e+00 %224 = fadd float %temp12.1, -2.000000e+00 %225 = call float @llvm.fabs.f32(float %temp12.1) %226 = fcmp ole float %225, -0.000000e+00 %.239 = select i1 %226, float %117, float 0.000000e+00 %227 = call float @llvm.fabs.f32(float %temp12.1) %228 = fcmp ole float %227, -0.000000e+00 %temp48.0 = select i1 %228, float %116, float 0.000000e+00 %229 = call float @llvm.fabs.f32(float %temp12.1) %230 = fcmp ole float %229, -0.000000e+00 %.240 = select i1 %230, float %119, float 0.000000e+00 %231 = call float @llvm.fabs.f32(float %temp12.1) %232 = fcmp ole float %231, -0.000000e+00 %temp48.2 = select i1 %232, float %118, float 0.000000e+00 %233 = call float @llvm.fabs.f32(float %223) %234 = fcmp ole float %233, -0.000000e+00 %..239 = select i1 %234, float %68, float %.239 %235 = call float @llvm.fabs.f32(float %223) %236 = fcmp ole float %235, -0.000000e+00 %temp44.2 = select i1 %236, float %69, float %temp48.0 %237 = call float @llvm.fabs.f32(float %223) %238 = fcmp ole float %237, -0.000000e+00 %..240 = select i1 %238, float %66, float %.240 %239 = call float @llvm.fabs.f32(float %223) %240 = fcmp ole float %239, -0.000000e+00 %temp44.4 = select i1 %240, float %67, float %temp48.2 %241 = call float @llvm.fabs.f32(float %224) %242 = fcmp ole float %241, -0.000000e+00 %...239 = select i1 %242, float %72, float %..239 %243 = call float @llvm.fabs.f32(float %224) %244 = fcmp ole float %243, -0.000000e+00 %temp44.6 = select i1 %244, float %73, float %temp44.2 %245 = call float @llvm.fabs.f32(float %224) %246 = fcmp ole float %245, -0.000000e+00 %...240 = select i1 %246, float %70, float %..240 %247 = call float @llvm.fabs.f32(float %224) %248 = fcmp ole float %247, -0.000000e+00 %temp44.8 = select i1 %248, float %71, float %temp44.4 %249 = fmul float %221, %...239 %250 = fadd float %249, %...240 %251 = fmul float %222, %temp44.6 %252 = fadd float %251, %temp44.8 %253 = fadd float %250, 0x3F40000000000000 %254 = fadd float %252, 0x3F40000000000000 %255 = fadd float %207, 0.000000e+00 %256 = bitcast float %255 to i32 %257 = bitcast float %253 to i32 %258 = bitcast float %254 to i32 %259 = insertelement <4 x i32> undef, i32 %256, i32 0 %260 = insertelement <4 x i32> %259, i32 %257, i32 1 %261 = insertelement <4 x i32> %260, i32 %258, i32 2 %262 = insertelement <4 x i32> %261, i32 0, i32 3 %263 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %262, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %264 = extractelement <4 x float> %263, i32 0 %265 = fadd float %250, 0xBF40000000000000 %266 = fadd float %252, 0x3F40000000000000 %267 = fadd float %207, 0.000000e+00 %268 = fadd float %250, 0x3F40000000000000 %269 = fadd float %252, 0xBF40000000000000 %270 = fadd float %207, 0.000000e+00 %271 = fadd float %250, 0xBF40000000000000 %272 = fadd float %252, 0xBF40000000000000 %273 = fadd float %207, 0.000000e+00 %274 = bitcast float %267 to i32 %275 = bitcast float %265 to i32 %276 = bitcast float %266 to i32 %277 = insertelement <4 x i32> undef, i32 %274, i32 0 %278 = insertelement <4 x i32> %277, i32 %275, i32 1 %279 = insertelement <4 x i32> %278, i32 %276, i32 2 %280 = insertelement <4 x i32> %279, i32 0, i32 3 %281 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %280, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %282 = extractelement <4 x float> %281, i32 0 %283 = bitcast float %270 to i32 %284 = bitcast float %268 to i32 %285 = bitcast float %269 to i32 %286 = insertelement <4 x i32> undef, i32 %283, i32 0 %287 = insertelement <4 x i32> %286, i32 %284, i32 1 %288 = insertelement <4 x i32> %287, i32 %285, i32 2 %289 = insertelement <4 x i32> %288, i32 0, i32 3 %290 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %289, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %291 = extractelement <4 x float> %290, i32 0 %292 = bitcast float %273 to i32 %293 = bitcast float %271 to i32 %294 = bitcast float %272 to i32 %295 = insertelement <4 x i32> undef, i32 %292, i32 0 %296 = insertelement <4 x i32> %295, i32 %293, i32 1 %297 = insertelement <4 x i32> %296, i32 %294, i32 2 %298 = insertelement <4 x i32> %297, i32 0, i32 3 %299 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %298, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %300 = extractelement <4 x float> %299, i32 0 %301 = fmul float %264, 6.250000e-02 %302 = fmul float %282, 6.250000e-02 %303 = fadd float %301, %302 %304 = fmul float %291, 6.250000e-02 %305 = fadd float %303, %304 %306 = fmul float %300, 6.250000e-02 %307 = fadd float %305, %306 %308 = fadd float %250, 0x3F40000000000000 %309 = fadd float %252, 0.000000e+00 %310 = fadd float %207, 0.000000e+00 %311 = bitcast float %310 to i32 %312 = bitcast float %308 to i32 %313 = bitcast float %309 to i32 %314 = insertelement <4 x i32> undef, i32 %311, i32 0 %315 = insertelement <4 x i32> %314, i32 %312, i32 1 %316 = insertelement <4 x i32> %315, i32 %313, i32 2 %317 = insertelement <4 x i32> %316, i32 0, i32 3 %318 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %317, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %319 = extractelement <4 x float> %318, i32 0 %320 = fadd float %250, 0xBF40000000000000 %321 = fadd float %252, 0.000000e+00 %322 = fadd float %207, 0.000000e+00 %323 = bitcast float %322 to i32 %324 = bitcast float %320 to i32 %325 = bitcast float %321 to i32 %326 = insertelement <4 x i32> undef, i32 %323, i32 0 %327 = insertelement <4 x i32> %326, i32 %324, i32 1 %328 = insertelement <4 x i32> %327, i32 %325, i32 2 %329 = insertelement <4 x i32> %328, i32 0, i32 3 %330 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %329, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %331 = extractelement <4 x float> %330, i32 0 %332 = fadd float %250, 0.000000e+00 %333 = fadd float %252, 0xBF40000000000000 %334 = fadd float %207, 0.000000e+00 %335 = bitcast float %334 to i32 %336 = bitcast float %332 to i32 %337 = bitcast float %333 to i32 %338 = insertelement <4 x i32> undef, i32 %335, i32 0 %339 = insertelement <4 x i32> %338, i32 %336, i32 1 %340 = insertelement <4 x i32> %339, i32 %337, i32 2 %341 = insertelement <4 x i32> %340, i32 0, i32 3 %342 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %341, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %343 = extractelement <4 x float> %342, i32 0 %344 = fadd float %250, 0.000000e+00 %345 = fadd float %252, 0x3F40000000000000 %346 = fadd float %207, 0.000000e+00 %347 = bitcast float %346 to i32 %348 = bitcast float %344 to i32 %349 = bitcast float %345 to i32 %350 = insertelement <4 x i32> undef, i32 %347, i32 0 %351 = insertelement <4 x i32> %350, i32 %348, i32 1 %352 = insertelement <4 x i32> %351, i32 %349, i32 2 %353 = insertelement <4 x i32> %352, i32 0, i32 3 %354 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %353, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %355 = extractelement <4 x float> %354, i32 0 %356 = fmul float %319, 1.250000e-01 %357 = fmul float %331, 1.250000e-01 %358 = fadd float %356, %357 %359 = fmul float %343, 1.250000e-01 %360 = fadd float %358, %359 %361 = fmul float %355, 1.250000e-01 %362 = fadd float %360, %361 %363 = bitcast float %207 to i32 %364 = bitcast float %250 to i32 %365 = bitcast float %252 to i32 %366 = insertelement <4 x i32> undef, i32 %363, i32 0 %367 = insertelement <4 x i32> %366, i32 %364, i32 1 %368 = insertelement <4 x i32> %367, i32 %365, i32 2 %369 = insertelement <4 x i32> %368, i32 0, i32 3 %370 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %369, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %371 = extractelement <4 x float> %370, i32 0 %372 = fadd float %362, %307 %373 = fmul float %371, 2.500000e-01 %374 = fadd float %373, %372 %375 = fcmp olt float %220, 1.000000e+00 br i1 %375, label %IF119, label %ENDIF118 ENDIF: ; preds = %main_body, %ENDIF118 %temp16.0 = phi float [ %619, %ENDIF118 ], [ 1.000000e+00, %main_body ] %376 = fmul float %92, %temp16.0 %377 = fadd float %376, %97 %378 = fmul float %93, %temp16.0 %379 = fadd float %378, %98 %380 = fmul float %94, %temp16.0 %381 = fadd float %380, %99 %382 = bitcast float %81 to i32 %383 = icmp eq i32 %382, 0 br i1 %383, label %ENDIF232, label %IF233 IF119: ; preds = %IF %384 = fadd float %temp12.1, 0.000000e+00 %385 = fadd float %temp12.1, -1.000000e+00 %386 = fadd float %temp12.1, -2.000000e+00 %387 = call float @llvm.fabs.f32(float %384) %388 = fcmp ole float %387, -0.000000e+00 %.241 = select i1 %388, float %42, float 0.000000e+00 %389 = call float @llvm.fabs.f32(float %384) %390 = fcmp ole float %389, -0.000000e+00 %temp48.5 = select i1 %390, float %43, float 0.000000e+00 %391 = call float @llvm.fabs.f32(float %384) %392 = fcmp ole float %391, -0.000000e+00 %.242 = select i1 %392, float %44, float 0.000000e+00 %393 = call float @llvm.fabs.f32(float %384) %394 = fcmp ole float %393, -0.000000e+00 %temp48.7 = select i1 %394, float %45, float 0.000000e+00 %395 = call float @llvm.fabs.f32(float %384) %396 = fcmp ole float %395, -0.000000e+00 %.243 = select i1 %396, float %46, float 0.000000e+00 %397 = call float @llvm.fabs.f32(float %384) %398 = fcmp ole float %397, -0.000000e+00 %temp48.9 = select i1 %398, float %47, float 0.000000e+00 %399 = call float @llvm.fabs.f32(float %384) %400 = fcmp ole float %399, -0.000000e+00 %.244 = select i1 %400, float %48, float 0.000000e+00 %401 = call float @llvm.fabs.f32(float %384) %402 = fcmp ole float %401, -0.000000e+00 %temp48.11 = select i1 %402, float %49, float 0.000000e+00 %403 = call float @llvm.fabs.f32(float %385) %404 = fcmp ole float %403, -0.000000e+00 %..241 = select i1 %404, float %50, float %.241 %405 = call float @llvm.fabs.f32(float %385) %406 = fcmp ole float %405, -0.000000e+00 %temp48.13 = select i1 %406, float %51, float %temp48.5 %407 = call float @llvm.fabs.f32(float %385) %408 = fcmp ole float %407, -0.000000e+00 %..242 = select i1 %408, float %52, float %.242 %409 = call float @llvm.fabs.f32(float %385) %410 = fcmp ole float %409, -0.000000e+00 %temp48.15 = select i1 %410, float %53, float %temp48.7 %411 = call float @llvm.fabs.f32(float %385) %412 = fcmp ole float %411, -0.000000e+00 %..243 = select i1 %412, float %54, float %.243 %413 = call float @llvm.fabs.f32(float %385) %414 = fcmp ole float %413, -0.000000e+00 %temp48.17 = select i1 %414, float %55, float %temp48.9 %415 = call float @llvm.fabs.f32(float %385) %416 = fcmp ole float %415, -0.000000e+00 %..244 = select i1 %416, float %56, float %.244 %417 = call float @llvm.fabs.f32(float %385) %418 = fcmp ole float %417, -0.000000e+00 %temp48.19 = select i1 %418, float %57, float %temp48.11 %419 = call float @llvm.fabs.f32(float %386) %420 = fcmp ole float %419, -0.000000e+00 %...241 = select i1 %420, float %58, float %..241 %421 = call float @llvm.fabs.f32(float %386) %422 = fcmp ole float %421, -0.000000e+00 %temp48.21 = select i1 %422, float %59, float %temp48.13 %423 = call float @llvm.fabs.f32(float %386) %424 = fcmp ole float %423, -0.000000e+00 %...242 = select i1 %424, float %60, float %..242 %425 = call float @llvm.fabs.f32(float %386) %426 = fcmp ole float %425, -0.000000e+00 %temp48.23 = select i1 %426, float %61, float %temp48.15 %427 = call float @llvm.fabs.f32(float %386) %428 = fcmp ole float %427, -0.000000e+00 %...243 = select i1 %428, float %62, float %..243 %429 = call float @llvm.fabs.f32(float %386) %430 = fcmp ole float %429, -0.000000e+00 %temp48.25 = select i1 %430, float %63, float %temp48.17 %431 = call float @llvm.fabs.f32(float %386) %432 = fcmp ole float %431, -0.000000e+00 %...244 = select i1 %432, float %64, float %..244 %433 = call float @llvm.fabs.f32(float %386) %434 = fcmp ole float %433, -0.000000e+00 %temp48.27 = select i1 %434, float %65, float %temp48.19 %435 = fmul float %132, %...241 %436 = fmul float %133, %temp48.21 %437 = fadd float %435, %436 %438 = fmul float %134, %...242 %439 = fadd float %437, %438 %440 = fmul float %136, %temp48.23 %441 = fadd float %439, %440 %442 = call float @llvm.AMDIL.clamp.(float %441, float 0.000000e+00, float 1.000000e+00) %443 = fmul float %132, %...243 %444 = fmul float %133, %temp48.25 %445 = fadd float %443, %444 %446 = fmul float %134, %...244 %447 = fadd float %445, %446 %448 = fmul float %136, %temp48.27 %449 = fadd float %447, %448 %450 = call float @llvm.AMDIL.clamp.(float %449, float 0.000000e+00, float 1.000000e+00) %451 = call float @llvm.fabs.f32(float %384) %452 = fcmp ole float %451, -0.000000e+00 %.245 = select i1 %452, float %68, float 0.000000e+00 %453 = call float @llvm.fabs.f32(float %384) %454 = fcmp ole float %453, -0.000000e+00 %temp52.0 = select i1 %454, float %69, float 0.000000e+00 %455 = call float @llvm.fabs.f32(float %384) %456 = fcmp ole float %455, -0.000000e+00 %.246 = select i1 %456, float %66, float 0.000000e+00 %457 = call float @llvm.fabs.f32(float %384) %458 = fcmp ole float %457, -0.000000e+00 %temp52.2 = select i1 %458, float %67, float 0.000000e+00 %459 = call float @llvm.fabs.f32(float %385) %460 = fcmp ole float %459, -0.000000e+00 %..245 = select i1 %460, float %72, float %.245 %461 = call float @llvm.fabs.f32(float %385) %462 = fcmp ole float %461, -0.000000e+00 %temp48.29 = select i1 %462, float %73, float %temp52.0 %463 = call float @llvm.fabs.f32(float %385) %464 = fcmp ole float %463, -0.000000e+00 %..246 = select i1 %464, float %70, float %.246 %465 = call float @llvm.fabs.f32(float %385) %466 = fcmp ole float %465, -0.000000e+00 %temp48.31 = select i1 %466, float %71, float %temp52.2 %467 = call float @llvm.fabs.f32(float %386) %468 = fcmp ole float %467, -0.000000e+00 %...245 = select i1 %468, float %76, float %..245 %469 = call float @llvm.fabs.f32(float %386) %470 = fcmp ole float %469, -0.000000e+00 %temp48.33 = select i1 %470, float %77, float %temp48.29 %471 = call float @llvm.fabs.f32(float %386) %472 = fcmp ole float %471, -0.000000e+00 %...246 = select i1 %472, float %74, float %..246 %473 = call float @llvm.fabs.f32(float %386) %474 = fcmp ole float %473, -0.000000e+00 %temp48.35 = select i1 %474, float %75, float %temp48.31 %475 = fmul float %442, %...245 %476 = fadd float %475, %...246 %477 = fmul float %450, %temp48.33 %478 = fadd float %477, %temp48.35 %479 = fadd float %476, 0x3F40000000000000 %480 = fadd float %478, 0x3F40000000000000 %481 = fadd float %207, 0.000000e+00 %482 = bitcast float %481 to i32 %483 = bitcast float %479 to i32 %484 = bitcast float %480 to i32 %485 = insertelement <4 x i32> undef, i32 %482, i32 0 %486 = insertelement <4 x i32> %485, i32 %483, i32 1 %487 = insertelement <4 x i32> %486, i32 %484, i32 2 %488 = insertelement <4 x i32> %487, i32 0, i32 3 %489 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %488, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %490 = extractelement <4 x float> %489, i32 0 %491 = fadd float %476, 0xBF40000000000000 %492 = fadd float %478, 0x3F40000000000000 %493 = fadd float %207, 0.000000e+00 %494 = fadd float %476, 0x3F40000000000000 %495 = fadd float %478, 0xBF40000000000000 %496 = fadd float %207, 0.000000e+00 %497 = fadd float %476, 0xBF40000000000000 %498 = fadd float %478, 0xBF40000000000000 %499 = fadd float %207, 0.000000e+00 %500 = bitcast float %493 to i32 %501 = bitcast float %491 to i32 %502 = bitcast float %492 to i32 %503 = insertelement <4 x i32> undef, i32 %500, i32 0 %504 = insertelement <4 x i32> %503, i32 %501, i32 1 %505 = insertelement <4 x i32> %504, i32 %502, i32 2 %506 = insertelement <4 x i32> %505, i32 0, i32 3 %507 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %506, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %508 = extractelement <4 x float> %507, i32 0 %509 = bitcast float %496 to i32 %510 = bitcast float %494 to i32 %511 = bitcast float %495 to i32 %512 = insertelement <4 x i32> undef, i32 %509, i32 0 %513 = insertelement <4 x i32> %512, i32 %510, i32 1 %514 = insertelement <4 x i32> %513, i32 %511, i32 2 %515 = insertelement <4 x i32> %514, i32 0, i32 3 %516 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %515, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %517 = extractelement <4 x float> %516, i32 0 %518 = bitcast float %499 to i32 %519 = bitcast float %497 to i32 %520 = bitcast float %498 to i32 %521 = insertelement <4 x i32> undef, i32 %518, i32 0 %522 = insertelement <4 x i32> %521, i32 %519, i32 1 %523 = insertelement <4 x i32> %522, i32 %520, i32 2 %524 = insertelement <4 x i32> %523, i32 0, i32 3 %525 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %524, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %526 = extractelement <4 x float> %525, i32 0 %527 = fmul float %490, 6.250000e-02 %528 = fmul float %508, 6.250000e-02 %529 = fadd float %527, %528 %530 = fmul float %517, 6.250000e-02 %531 = fadd float %529, %530 %532 = fmul float %526, 6.250000e-02 %533 = fadd float %531, %532 %534 = fadd float %476, 0x3F40000000000000 %535 = fadd float %478, 0.000000e+00 %536 = fadd float %207, 0.000000e+00 %537 = bitcast float %536 to i32 %538 = bitcast float %534 to i32 %539 = bitcast float %535 to i32 %540 = insertelement <4 x i32> undef, i32 %537, i32 0 %541 = insertelement <4 x i32> %540, i32 %538, i32 1 %542 = insertelement <4 x i32> %541, i32 %539, i32 2 %543 = insertelement <4 x i32> %542, i32 0, i32 3 %544 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %543, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %545 = extractelement <4 x float> %544, i32 0 %546 = fadd float %476, 0xBF40000000000000 %547 = fadd float %478, 0.000000e+00 %548 = fadd float %207, 0.000000e+00 %549 = bitcast float %548 to i32 %550 = bitcast float %546 to i32 %551 = bitcast float %547 to i32 %552 = insertelement <4 x i32> undef, i32 %549, i32 0 %553 = insertelement <4 x i32> %552, i32 %550, i32 1 %554 = insertelement <4 x i32> %553, i32 %551, i32 2 %555 = insertelement <4 x i32> %554, i32 0, i32 3 %556 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %555, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %557 = extractelement <4 x float> %556, i32 0 %558 = fadd float %476, 0.000000e+00 %559 = fadd float %478, 0xBF40000000000000 %560 = fadd float %207, 0.000000e+00 %561 = bitcast float %560 to i32 %562 = bitcast float %558 to i32 %563 = bitcast float %559 to i32 %564 = insertelement <4 x i32> undef, i32 %561, i32 0 %565 = insertelement <4 x i32> %564, i32 %562, i32 1 %566 = insertelement <4 x i32> %565, i32 %563, i32 2 %567 = insertelement <4 x i32> %566, i32 0, i32 3 %568 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %567, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %569 = extractelement <4 x float> %568, i32 0 %570 = fadd float %476, 0.000000e+00 %571 = fadd float %478, 0x3F40000000000000 %572 = fadd float %207, 0.000000e+00 %573 = bitcast float %572 to i32 %574 = bitcast float %570 to i32 %575 = bitcast float %571 to i32 %576 = insertelement <4 x i32> undef, i32 %573, i32 0 %577 = insertelement <4 x i32> %576, i32 %574, i32 1 %578 = insertelement <4 x i32> %577, i32 %575, i32 2 %579 = insertelement <4 x i32> %578, i32 0, i32 3 %580 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %579, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %581 = extractelement <4 x float> %580, i32 0 %582 = fmul float %545, 1.250000e-01 %583 = fmul float %557, 1.250000e-01 %584 = fadd float %582, %583 %585 = fmul float %569, 1.250000e-01 %586 = fadd float %584, %585 %587 = fmul float %581, 1.250000e-01 %588 = fadd float %586, %587 %589 = bitcast float %207 to i32 %590 = bitcast float %476 to i32 %591 = bitcast float %478 to i32 %592 = insertelement <4 x i32> undef, i32 %589, i32 0 %593 = insertelement <4 x i32> %592, i32 %590, i32 1 %594 = insertelement <4 x i32> %593, i32 %591, i32 2 %595 = insertelement <4 x i32> %594, i32 0, i32 3 %596 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %595, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %597 = extractelement <4 x float> %596, i32 0 %598 = fadd float %588, %533 %599 = fmul float %597, 2.500000e-01 %600 = fadd float %599, %598 %601 = fcmp oge float %386, 0.000000e+00 %.247 = select i1 %601, float 1.000000e+00, float %600 %602 = fsub float 1.000000e+00, %220 %603 = fmul float %374, %220 %604 = fmul float %.247, %602 %605 = fadd float %603, %604 br label %ENDIF118 ENDIF118: ; preds = %IF, %IF119 %temp8.0 = phi float [ %605, %IF119 ], [ %374, %IF ] %606 = fsub float %101, %78 %607 = fsub float %102, %79 %608 = fsub float %103, %80 %609 = fmul float %606, %606 %610 = fmul float %607, %607 %611 = fadd float %610, %609 %612 = fmul float %608, %608 %613 = fadd float %611, %612 %614 = fmul float %613, %41 %615 = fadd float %614, %40 %616 = call float @llvm.AMDIL.clamp.(float %615, float 0.000000e+00, float 1.000000e+00) %617 = fsub float 1.000000e+00, %616 %618 = fmul float %temp8.0, %617 %619 = fadd float %616, %618 br label %ENDIF IF233: ; preds = %ENDIF %620 = fmul float %377, 0x3FCB333340000000 %621 = fmul float %379, 0x3FE6E48E80000000 %622 = fadd float %621, %620 %623 = fmul float %381, 0x3FB2752540000000 %624 = fadd float %622, %623 %625 = fdiv float 1.000000e+00, %624 %626 = fmul float %625, %95 %627 = fsub float 1.000000e+00, %temp16.0 %628 = fmul float %627, %626 %629 = fsub float 1.000000e+00, %628 %630 = fmul float %629, %381 %631 = fmul float %629, %379 %632 = fmul float %629, %377 %633 = fmul float %629, 5.000000e-01 %634 = fadd float %633, 5.000000e-01 %635 = fsub float 1.000000e+00, %634 %636 = fmul float %632, %634 %637 = fmul float %630, %635 %638 = fadd float %636, %637 %639 = fsub float 1.000000e+00, %634 %640 = fmul float %631, %634 %641 = fmul float %631, %639 %642 = fadd float %640, %641 %643 = fsub float 1.000000e+00, %634 %644 = fmul float %630, %634 %645 = fmul float %632, %643 %646 = fadd float %644, %645 br label %ENDIF232 ENDIF232: ; preds = %ENDIF, %IF233 %temp5.0 = phi float [ %642, %IF233 ], [ %379, %ENDIF ] %temp6.0 = phi float [ %646, %IF233 ], [ %381, %ENDIF ] %temp4.0 = phi float [ %638, %IF233 ], [ %377, %ENDIF ] %647 = fadd float %113, -1.000000e+00 %648 = fmul float %32, %647 %649 = fadd float %648, 1.000000e+00 %650 = fadd float %113, %29 %651 = fadd float %25, -1.000000e+00 %652 = fadd float %26, -1.000000e+00 %653 = fadd float %27, -1.000000e+00 %654 = call float @llvm.AMDIL.clamp.(float %650, float 0.000000e+00, float 1.000000e+00) %655 = fmul float %654, %651 %656 = fadd float %655, 1.000000e+00 %657 = fmul float %654, %652 %658 = fadd float %657, 1.000000e+00 %659 = fmul float %654, %653 %660 = fadd float %659, 1.000000e+00 %661 = fmul float %temp4.0, %656 %662 = fmul float %temp5.0, %658 %663 = fmul float %temp6.0, %660 %664 = fmul float %649, %28 %665 = fmul float %664, %100 %666 = fsub float %665, %664 %667 = fmul float %31, %666 %668 = fadd float %667, %664 %669 = fmul float %110, %661 %670 = fmul float %111, %662 %671 = fmul float %112, %663 %672 = call float @llvm.fabs.f32(float %30) %673 = fmul float %669, %37 %674 = fmul float %670, %37 %675 = fmul float %671, %37 %676 = fmul float %36, %104 %677 = fcmp ole float %672, -0.000000e+00 %.248 = select i1 %677, float %668, float %676 %678 = fmul float %96, %96 %679 = fmul float %37, %669 %680 = fsub float %33, %679 %681 = fmul float %37, %670 %682 = fsub float %34, %681 %683 = fmul float %37, %671 %684 = fsub float %35, %683 %685 = fmul float %678, %680 %686 = fadd float %685, %673 %687 = fmul float %678, %682 %688 = fadd float %687, %674 %689 = fmul float %678, %684 %690 = fadd float %689, %675 %691 = fcmp uge float %.248, %4 %692 = select i1 %691, float 1.000000e+00, float -1.000000e+00 call void @llvm.AMDGPU.kill(float %692) %693 = call i32 @llvm.SI.packf16(float %686, float %688) %694 = bitcast i32 %693 to float %695 = call i32 @llvm.SI.packf16(float %690, float %.248) %696 = bitcast i32 %695 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %694, float %696, float %694, float %696) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.AMDGPU.kill(float) ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[16:23], s[6:7], 0x0 ; C00E0403 00000000 v_interp_p1_f32 v8, v0, 0, 0, [m0] ; D4200000 v_interp_p2_f32 v8, [v8], v1, 0, 0, [m0] ; D4210001 v_interp_p1_f32 v9, v0, 1, 0, [m0] ; D4240100 v_interp_p2_f32 v9, [v9], v1, 1, 0, [m0] ; D4250101 v_interp_p1_f32 v13, v0, 0, 1, [m0] ; D4340400 v_interp_p2_f32 v13, [v13], v1, 0, 1, [m0] ; D4350401 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s9, s[12:15], 0x1e0 ; C0220246 000001E0 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x5a0 ; C0220286 000005A0 v_interp_p1_f32 v14, v0, 1, 1, [m0] ; D4380500 v_interp_p2_f32 v14, [v14], v1, 1, 1, [m0] ; D4390501 v_interp_p1_f32 v15, v0, 2, 1, [m0] ; D43C0600 v_interp_p2_f32 v15, [v15], v1, 2, 1, [m0] ; D43D0601 v_interp_p1_f32 v12, v0, 3, 1, [m0] ; D4300700 v_interp_p2_f32 v12, [v12], v1, 3, 1, [m0] ; D4310701 v_interp_p1_f32 v2, v0, 3, 2, [m0] ; D4080B00 v_interp_p2_f32 v2, [v2], v1, 3, 2, [m0] ; D4090B01 v_interp_p1_f32 v3, v0, 0, 3, [m0] ; D40C0C00 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v3, [v3], v1, 0, 3, [m0] ; D40D0C01 v_interp_p1_f32 v4, v0, 1, 3, [m0] ; D4100D00 v_interp_p2_f32 v4, [v4], v1, 1, 3, [m0] ; D4110D01 v_interp_p1_f32 v7, v0, 2, 3, [m0] ; D41C0E00 v_interp_p2_f32 v7, [v7], v1, 2, 3, [m0] ; D41D0E01 v_interp_p1_f32 v6, v0, 3, 3, [m0] ; D4180F00 v_interp_p2_f32 v6, [v6], v1, 3, 3, [m0] ; D4190F01 v_interp_p1_f32 v5, v0, 3, 4, [m0] ; D4141300 v_interp_p2_f32 v5, [v5], v1, 3, 4, [m0] ; D4151301 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[8:11], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[16:23], s[0:3] ; F0800F00 00040808 v_cmp_ne_i32_e64 s[0:1], 0, s10 ; D0C50000 00001480 v_mov_b32_e32 v16, 1.0 ; 7E2002F2 s_waitcnt vmcnt(0) ; BF8C0770 s_and_saveexec_b64 s[16:17], s[0:1] ; BE902000 s_xor_b64 s[16:17], exec, s[16:17] ; 8890107E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x440 ; C02202C6 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x4a0 ; C0220486 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a4 ; C0220586 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4a8 ; C02205C6 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4ac ; C0220606 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d0 ; C0220646 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x4d4 ; C0220686 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d8 ; C02206C6 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x4dc ; C0220706 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x4e0 ; C0220786 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x4e4 ; C0220806 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e8 ; C0220846 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4ec ; C02208C6 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s53, s[12:15], 0x550 ; C0220D46 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[12:15], 0x554 ; C0220D86 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[12:15], 0x558 ; C0220DC6 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x570 ; C0220946 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x574 ; C0220986 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x578 ; C0220A06 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x57c ; C0220A86 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x590 ; C0220546 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x594 ; C0220506 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x598 ; C02204C6 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x20 ; C00E0B03 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[56:59], s[4:5], 0x10 ; C00A0E02 00000010 v_interp_p1_f32 v16, v0, 0, 4, [m0] ; D4401000 v_interp_p2_f32 v16, [v16], v1, 0, 4, [m0] ; D4411001 v_interp_p1_f32 v17, v0, 1, 4, [m0] ; D4441100 v_interp_p2_f32 v17, [v17], v1, 1, 4, [m0] ; D4451101 v_interp_p1_f32 v0, v0, 2, 4, [m0] ; D4001200 v_interp_p2_f32 v0, [v0], v1, 2, 4, [m0] ; D4011201 s_buffer_load_dword s60, s[12:15], 0x55c ; C0220F06 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x560 ; C02209C6 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x564 ; C0220A46 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x568 ; C0220AC6 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[12:15], 0x56c ; C0220D06 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x47c ; C0220F46 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x490 ; C0220746 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x494 ; C02207C6 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x498 ; C0220886 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x49c ; C0220906 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x468 ; C0220F86 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x46c ; C0220FC6 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x470 ; C0221006 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x474 ; C0221046 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x478 ; C0221086 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x454 ; C02210C6 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x458 ; C0221106 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x45c ; C0221146 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x460 ; C0221186 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s71, s[12:15], 0x464 ; C02211C6 00000464 v_add_f32_e32 v22, 0, v17 ; 022C2280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s67, v22 ; 0A242C43 v_add_f32_e32 v24, 0, v16 ; 02302080 v_add_f32_e32 v23, 0, v0 ; 022E0080 v_mad_f32 v1, 0, v16, 1.0 ; D1C10001 03CA2080 v_mac_f32_e32 v18, s3, v24 ; 2C243003 v_mac_f32_e32 v18, s68, v23 ; 2C242E44 v_mac_f32_e32 v18, s69, v1 ; 2C240245 v_mul_f32_e32 v19, s71, v22 ; 0A262C47 v_mac_f32_e32 v19, s70, v24 ; 2C263046 v_mac_f32_e32 v19, s62, v23 ; 2C262E3E v_mac_f32_e32 v19, s63, v1 ; 2C26023F v_add_f32_e64 v20, 0, v18 clamp ; D1018014 00022480 v_add_f32_e64 v21, 0, v19 clamp ; D1018015 00022680 v_subrev_f32_e32 v20, v18, v20 ; 06282912 v_subrev_f32_e32 v21, v19, v21 ; 062A2B13 v_add_f32_e32 v20, v21, v20 ; 02282915 v_mul_f32_e32 v21, s31, v22 ; 0A2A2C1F v_mac_f32_e32 v21, s29, v24 ; 2C2A301D v_mac_f32_e32 v21, s34, v23 ; 2C2A2E22 v_mac_f32_e32 v21, s36, v1 ; 2C2A0224 v_mul_f32_e32 v25, s22, v22 ; 0A322C16 v_mac_f32_e32 v25, s18, v24 ; 2C323012 v_mac_f32_e32 v25, s23, v23 ; 2C322E17 v_mac_f32_e32 v25, s24, v1 ; 2C320218 v_add_f32_e64 v26, 0, v21 clamp ; D101801A 00022A80 v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_subrev_f32_e32 v26, v21, v26 ; 06343515 v_subrev_f32_e32 v27, v25, v27 ; 06363719 v_add_f32_e32 v26, v27, v26 ; 0234351B v_mul_f32_e32 v27, s26, v22 ; 0A362C1A v_mac_f32_e32 v27, s25, v24 ; 2C363019 v_mac_f32_e32 v27, s27, v23 ; 2C362E1B v_mac_f32_e32 v27, s28, v1 ; 2C36021C v_mul_f32_e32 v28, s32, v22 ; 0A382C20 v_mac_f32_e32 v28, s30, v24 ; 2C38301E v_mac_f32_e32 v28, s33, v23 ; 2C382E21 v_mac_f32_e32 v28, s35, v1 ; 2C380223 v_mov_b32_e32 v29, 0x80000000 ; 7E3A02FF 80000000 v_cmp_le_f32_e64 vcc, |v26|, v29 ; D043016A 00023B1A v_cndmask_b32_e32 v21, v27, v21 ; 002A2B1B v_cndmask_b32_e32 v25, v28, v25 ; 0032331C v_cndmask_b32_e64 v26, 2.0, 1.0, vcc ; D100001A 01A9E4F4 v_cmp_le_f32_e64 vcc, |v20|, v29 ; D043016A 00023B14 v_cndmask_b32_e32 v21, v21, v18 ; 002A2515 v_cndmask_b32_e32 v25, v25, v19 ; 00322719 v_cndmask_b32_e64 v28, v26, 0, vcc ; D100001C 01A9011A v_mul_f32_e32 v18, s65, v22 ; 0A242C41 v_mac_f32_e32 v18, s64, v24 ; 2C243040 v_mac_f32_e32 v18, s66, v23 ; 2C242E42 v_mac_f32_e32 v18, s61, v1 ; 2C24023D v_add_f32_e64 v26, 0, v21 clamp ; D101801A 00022A80 v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_add_f32_e32 v19, -1.0, v28 ; 022638F3 v_add_f32_e32 v20, -2.0, v28 ; 022838F5 v_cmp_le_f32_e64 vcc, |v28|, v29 ; D043016A 00023B1C v_mov_b32_e32 v30, s55 ; 7E3C0237 v_cndmask_b32_e32 v30, 0, v30 ; 003C3C80 v_mov_b32_e32 v31, s60 ; 7E3E023C v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_mov_b32_e32 v32, s53 ; 7E400235 v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_mov_b32_e32 v33, s54 ; 7E420236 v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_cmp_le_f32_e64 vcc, |v19|, v29 ; D043016A 00023B13 v_mov_b32_e32 v19, s43 ; 7E26022B v_cndmask_b32_e32 v19, v30, v19 ; 0026271E v_mov_b32_e32 v30, s52 ; 7E3C0234 v_cndmask_b32_e32 v30, v31, v30 ; 003C3D1F v_mov_b32_e32 v31, s39 ; 7E3E0227 v_cndmask_b32_e32 v31, v32, v31 ; 003E3F20 v_mov_b32_e32 v32, s41 ; 7E400229 v_cndmask_b32_e32 v32, v33, v32 ; 00404121 v_cmp_le_f32_e64 vcc, |v20|, v29 ; D043016A 00023B14 v_mov_b32_e32 v20, s40 ; 7E280228 v_cndmask_b32_e32 v29, v19, v20 ; 003A2913 v_mov_b32_e32 v19, s42 ; 7E26022A v_cndmask_b32_e32 v30, v30, v19 ; 003C271E v_mov_b32_e32 v19, s37 ; 7E260225 v_cndmask_b32_e32 v19, v31, v19 ; 0026271F v_mov_b32_e32 v20, s38 ; 7E280226 v_cndmask_b32_e32 v20, v32, v20 ; 00282920 v_mac_f32_e32 v19, v29, v26 ; 2C26351D v_mac_f32_e32 v20, v30, v27 ; 2C28371E v_mov_b32_e32 v26, 0x3a000000 ; 7E3402FF 3A000000 v_add_f32_e32 v30, v26, v19 ; 023C271A v_add_f32_e32 v31, v26, v20 ; 023E291A v_add_f32_e32 v29, 0, v18 ; 023A2480 s_mov_b32 s53, 0 ; BEB50080 v_mov_b32_e32 v32, s53 ; 7E400235 v_mov_b32_e32 v26, 0xba000000 ; 7E3402FF BA000000 v_add_f32_e32 v27, v26, v19 ; 0236271A v_mov_b32_e32 v33, v29 ; 7E42031D v_mov_b32_e32 v34, v30 ; 7E44031E v_mov_b32_e32 v35, v31 ; 7E46031F v_mov_b32_e32 v36, v32 ; 7E480320 v_add_f32_e32 v26, v26, v20 ; 0234291A v_mov_b32_e32 v34, v27 ; 7E44031B v_mov_b32_e32 v37, v29 ; 7E4A031D v_mov_b32_e32 v38, v30 ; 7E4C031E v_mov_b32_e32 v39, v31 ; 7E4E031F v_mov_b32_e32 v40, v32 ; 7E500320 v_mov_b32_e32 v35, v31 ; 7E46031F v_mov_b32_e32 v39, v26 ; 7E4E031A v_mov_b32_e32 v36, s53 ; 7E480235 v_mov_b32_e32 v40, s53 ; 7E500235 image_sample_c_l v27, 1, 0, 0, 0, 0, 0, 0, 0, v[29:32], s[44:51], s[56:59] ; F0B00100 01CB1B1D s_nop 0 ; BF800000 image_sample_c_l v41, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[56:59] ; F0B00100 01CB2921 v_mov_b32_e32 v35, v26 ; 7E46031A image_sample_c_l v37, 1, 0, 0, 0, 0, 0, 0, 0, v[37:40], s[44:51], s[56:59] ; F0B00100 01CB2525 v_mov_b32_e32 v36, s53 ; 7E480235 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[56:59] ; F0B00100 01CB2621 v_add_f32_e32 v35, 0, v20 ; 02462880 v_mov_b32_e32 v42, v29 ; 7E54031D v_mov_b32_e32 v43, v30 ; 7E56031E v_mov_b32_e32 v44, v31 ; 7E58031F v_mov_b32_e32 v45, v32 ; 7E5A0320 v_mov_b32_e32 v44, v35 ; 7E580323 v_add_f32_e32 v30, 0, v19 ; 023C2680 v_mov_b32_e32 v45, s53 ; 7E5A0235 v_mov_b32_e32 v46, v29 ; 7E5C031D v_mov_b32_e32 v47, v30 ; 7E5E031E v_mov_b32_e32 v48, v31 ; 7E60031F v_mov_b32_e32 v49, v32 ; 7E620320 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[44:51], s[56:59] ; F0B00100 01CB272A v_mov_b32_e32 v48, v26 ; 7E60031A v_mov_b32_e32 v36, s53 ; 7E480235 image_sample_c_l v26, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[56:59] ; F0B00100 01CB1A21 v_mov_b32_e32 v49, s53 ; 7E620235 image_sample_c_l v33, 1, 0, 0, 0, 0, 0, 0, 0, v[46:49], s[44:51], s[56:59] ; F0B00100 01CB212E v_mov_b32_e32 v32, s53 ; 7E400235 image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[29:32], s[44:51], s[56:59] ; F0B00100 01CB1D1D v_mov_b32_e32 v30, 0x3d800000 ; 7E3C02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v31, v30, v41 ; 0A3E531E v_mac_f32_e32 v31, v30, v27 ; 2C3E371E s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v31, v30, v37 ; 2C3E4B1E s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v31, v30, v38 ; 2C3E4D1E v_mov_b32_e32 v27, 0x3e000000 ; 7E3602FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v26, v27, v26 ; 0A34351B v_mac_f32_e32 v26, v27, v39 ; 2C344F1B s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v26, v27, v33 ; 2C34431B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v26, v27, v29 ; 2C343B1B v_add_f32_e32 v21, -0.5, v21 ; 022A2AF1 v_add_f32_e32 v25, -0.5, v25 ; 023232F1 v_sub_f32_e64 v21, |v21|, s1 ; D1020115 00000315 v_sub_f32_e64 v25, |v25|, s1 ; D1020119 00000319 v_mul_f32_e32 v21, s2, v21 ; 0A2A2A02 v_mul_f32_e32 v25, s2, v25 ; 0A323202 v_add_f32_e64 v21, 0, v21 clamp ; D1018015 00022A80 v_add_f32_e64 v25, 0, v25 clamp ; D1018019 00023280 v_sub_f32_e32 v21, 1.0, v21 ; 042A2AF2 v_mad_f32 v27, -v25, v21, v21 ; D1C1001B 24562B19 v_mov_b32_e32 v21, 0 ; 7E2A0280 v_add_f32_e32 v25, v31, v26 ; 0232351F image_sample_c_l v19, 1, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[44:51], s[56:59] ; F0B00100 01CB1312 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v25, v19, v25, 0x3e800000 ; 2E323313 3E800000 v_mov_b32_e32 v26, s0 ; 7E340200 v_cmp_gt_f32_e32 vcc, 1.0, v27 ; 7C8836F2 s_and_saveexec_b64 s[54:55], vcc ; BEB6206A s_xor_b64 s[54:55], exec, s[54:55] ; 88B6367E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s60, s[12:15], 0x510 ; C0220F06 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x514 ; C0220F46 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x518 ; C0220F86 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x51c ; C0220FC6 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x520 ; C0221006 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x524 ; C0221046 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x528 ; C0221086 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x52c ; C02210C6 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x580 ; C0221106 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x584 ; C0221146 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x588 ; C0221186 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s71, s[12:15], 0x58c ; C02211C6 0000058C v_mov_b32_e32 v19, s29 ; 7E26021D v_mov_b32_e32 v20, s31 ; 7E28021F v_mov_b32_e32 v21, s34 ; 7E2A0222 v_mov_b32_e32 v29, s36 ; 7E3A0224 v_mov_b32_e32 v30, s18 ; 7E3C0212 v_mov_b32_e32 v31, s22 ; 7E3E0216 v_mov_b32_e32 v32, s23 ; 7E400217 v_mov_b32_e32 v33, s24 ; 7E420218 v_mov_b32_e32 v34, s25 ; 7E440219 v_mov_b32_e32 v35, s26 ; 7E46021A v_mov_b32_e32 v36, s27 ; 7E48021B v_add_f32_e32 v37, 0, v28 ; 024A3880 v_mov_b32_e32 v38, 0x80000000 ; 7E4C02FF 80000000 v_cmp_le_f32_e64 vcc, |v37|, v38 ; D043016A 00024D25 v_add_f32_e32 v37, -1.0, v28 ; 024A38F3 v_cmp_le_f32_e64 s[0:1], |v37|, v38 ; D0430100 00024D25 v_mov_b32_e32 v37, s28 ; 7E4A021C v_cndmask_b32_e32 v19, 0, v19 ; 00262680 v_cndmask_b32_e64 v19, v19, v34, s[0:1] ; D1000013 00024513 v_mov_b32_e32 v34, s30 ; 7E44021E v_cndmask_b32_e32 v20, 0, v20 ; 00282880 v_cndmask_b32_e64 v20, v20, v35, s[0:1] ; D1000014 00024714 v_mov_b32_e32 v35, s32 ; 7E460220 v_cndmask_b32_e32 v21, 0, v21 ; 002A2A80 v_cndmask_b32_e64 v21, v21, v36, s[0:1] ; D1000015 00024915 v_mov_b32_e32 v36, s33 ; 7E480221 v_cndmask_b32_e32 v29, 0, v29 ; 003A3A80 v_cndmask_b32_e64 v29, v29, v37, s[0:1] ; D100001D 00024B1D v_mov_b32_e32 v37, s35 ; 7E4A0223 v_cndmask_b32_e32 v30, 0, v30 ; 003C3C80 v_cndmask_b32_e64 v30, v30, v34, s[0:1] ; D100001E 0002451E v_mov_b32_e32 v34, s39 ; 7E440227 v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_cndmask_b32_e64 v31, v31, v35, s[0:1] ; D100001F 0002471F v_mov_b32_e32 v35, s41 ; 7E460229 v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_cndmask_b32_e64 v32, v32, v36, s[0:1] ; D1000020 00024920 v_mov_b32_e32 v36, s43 ; 7E48022B v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_cndmask_b32_e64 v33, v33, v37, s[0:1] ; D1000021 00024B21 v_mov_b32_e32 v37, s52 ; 7E4A0234 v_add_f32_e32 v28, -2.0, v28 ; 023838F5 v_cmp_le_f32_e64 s[2:3], |v28|, v38 ; D0430102 00024D1C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v38, s60 ; 7E4C023C v_cndmask_b32_e64 v19, v19, v38, s[2:3] ; D1000013 000A4D13 v_mov_b32_e32 v38, s61 ; 7E4C023D v_cndmask_b32_e64 v20, v20, v38, s[2:3] ; D1000014 000A4D14 v_mov_b32_e32 v38, s62 ; 7E4C023E v_cndmask_b32_e64 v21, v21, v38, s[2:3] ; D1000015 000A4D15 v_mov_b32_e32 v38, s63 ; 7E4C023F v_cndmask_b32_e64 v29, v29, v38, s[2:3] ; D100001D 000A4D1D v_mov_b32_e32 v38, s64 ; 7E4C0240 v_cndmask_b32_e64 v30, v30, v38, s[2:3] ; D100001E 000A4D1E v_mov_b32_e32 v38, s65 ; 7E4C0241 v_cndmask_b32_e64 v31, v31, v38, s[2:3] ; D100001F 000A4D1F v_mov_b32_e32 v38, s66 ; 7E4C0242 v_cndmask_b32_e64 v32, v32, v38, s[2:3] ; D1000020 000A4D20 v_mov_b32_e32 v38, s67 ; 7E4C0243 v_cndmask_b32_e64 v33, v33, v38, s[2:3] ; D1000021 000A4D21 v_mov_b32_e32 v38, s37 ; 7E4C0225 v_mul_f32_e32 v20, v20, v22 ; 0A282D14 v_mac_f32_e32 v20, v19, v24 ; 2C283113 v_mov_b32_e32 v19, s38 ; 7E260226 v_mac_f32_e32 v20, v21, v23 ; 2C282F15 v_mov_b32_e32 v21, s40 ; 7E2A0228 v_mac_f32_e32 v20, v29, v1 ; 2C28031D v_mov_b32_e32 v29, s42 ; 7E3A022A v_add_f32_e64 v39, 0, v20 clamp ; D1018027 00022880 v_mul_f32_e32 v20, v31, v22 ; 0A282D1F v_mac_f32_e32 v20, v30, v24 ; 2C28311E v_mac_f32_e32 v20, v32, v23 ; 2C282F20 v_mac_f32_e32 v20, v33, v1 ; 2C280321 v_add_f32_e64 v1, 0, v20 clamp ; D1018001 00022880 v_cndmask_b32_e32 v20, 0, v36 ; 00284880 v_cndmask_b32_e32 v22, 0, v37 ; 002C4A80 v_cndmask_b32_e32 v23, 0, v34 ; 002E4480 v_cndmask_b32_e32 v24, 0, v35 ; 00304680 v_cndmask_b32_e64 v20, v20, v21, s[0:1] ; D1000014 00022B14 v_cndmask_b32_e64 v21, v22, v29, s[0:1] ; D1000015 00023B16 v_cndmask_b32_e64 v22, v23, v38, s[0:1] ; D1000016 00024D17 v_cndmask_b32_e64 v23, v24, v19, s[0:1] ; D1000017 00022718 v_mov_b32_e32 v19, s70 ; 7E260246 v_cndmask_b32_e64 v24, v20, v19, s[2:3] ; D1000018 000A2714 v_mov_b32_e32 v19, s71 ; 7E260247 v_cndmask_b32_e64 v21, v21, v19, s[2:3] ; D1000015 000A2715 v_mov_b32_e32 v19, s68 ; 7E260244 v_cndmask_b32_e64 v19, v22, v19, s[2:3] ; D1000013 000A2716 v_mov_b32_e32 v20, s69 ; 7E280245 v_cndmask_b32_e64 v20, v23, v20, s[2:3] ; D1000014 000A2917 v_mac_f32_e32 v19, v24, v39 ; 2C264F18 v_mac_f32_e32 v20, v21, v1 ; 2C280315 v_mov_b32_e32 v1, 0x3a000000 ; 7E0202FF 3A000000 v_add_f32_e32 v22, v1, v19 ; 022C2701 v_add_f32_e32 v23, v1, v20 ; 022E2901 v_add_f32_e32 v21, 0, v18 ; 022A2480 v_mov_b32_e32 v24, s53 ; 7E300235 v_mov_b32_e32 v1, 0xba000000 ; 7E0202FF BA000000 v_add_f32_e32 v29, v1, v19 ; 023A2701 v_mov_b32_e32 v30, v21 ; 7E3C0315 v_mov_b32_e32 v31, v22 ; 7E3E0316 v_mov_b32_e32 v32, v23 ; 7E400317 v_mov_b32_e32 v33, v24 ; 7E420318 v_mov_b32_e32 v31, v29 ; 7E3E031D v_add_f32_e32 v1, v1, v20 ; 02022901 v_mov_b32_e32 v32, v23 ; 7E400317 v_mov_b32_e32 v34, v21 ; 7E440315 v_mov_b32_e32 v35, v22 ; 7E460316 v_mov_b32_e32 v36, v23 ; 7E480317 v_mov_b32_e32 v37, v24 ; 7E4A0318 image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[44:51], s[56:59] ; F0B00100 01CB1D15 v_mov_b32_e32 v33, s53 ; 7E420235 v_mov_b32_e32 v36, v1 ; 7E480301 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[56:59] ; F0B00100 01CB261E v_mov_b32_e32 v37, s53 ; 7E4A0235 v_mov_b32_e32 v32, v1 ; 7E400301 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[56:59] ; F0B00100 01CB2222 v_mov_b32_e32 v33, s53 ; 7E420235 image_sample_c_l v35, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[56:59] ; F0B00100 01CB231E v_add_f32_e32 v32, 0, v20 ; 02402880 v_mov_b32_e32 v39, v21 ; 7E4E0315 v_mov_b32_e32 v40, v22 ; 7E500316 v_mov_b32_e32 v41, v23 ; 7E520317 v_mov_b32_e32 v42, v24 ; 7E540318 v_mov_b32_e32 v41, v32 ; 7E520320 v_add_f32_e32 v22, 0, v19 ; 022C2680 v_mov_b32_e32 v42, s53 ; 7E540235 v_mov_b32_e32 v43, v21 ; 7E560315 v_mov_b32_e32 v44, v22 ; 7E580316 v_mov_b32_e32 v45, v23 ; 7E5A0317 v_mov_b32_e32 v46, v24 ; 7E5C0318 image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[56:59] ; F0B00100 01CB2427 v_mov_b32_e32 v45, v1 ; 7E5A0301 v_mov_b32_e32 v33, s53 ; 7E420235 image_sample_c_l v1, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[56:59] ; F0B00100 01CB011E v_mov_b32_e32 v46, s53 ; 7E5C0235 image_sample_c_l v30, 1, 0, 0, 0, 0, 0, 0, 0, v[43:46], s[44:51], s[56:59] ; F0B00100 01CB1E2B v_mov_b32_e32 v24, s53 ; 7E300235 image_sample_c_l v22, 1, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[44:51], s[56:59] ; F0B00100 01CB1615 v_mov_b32_e32 v21, 0 ; 7E2A0280 image_sample_c_l v18, 1, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[44:51], s[56:59] ; F0B00100 01CB1212 v_mov_b32_e32 v19, 0x3d800000 ; 7E2602FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v20, v19, v38 ; 0A284D13 v_mac_f32_e32 v20, v19, v29 ; 2C283B13 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v20, v19, v34 ; 2C284513 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v20, v19, v35 ; 2C284713 v_mov_b32_e32 v19, 0x3e000000 ; 7E2602FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v1, v19, v1 ; 0A020313 v_mac_f32_e32 v1, v19, v36 ; 2C024913 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v1, v19, v30 ; 2C023D13 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v1, v19, v22 ; 2C022D13 v_add_f32_e32 v1, v20, v1 ; 02020314 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v1, v18, v1, 0x3e800000 ; 2E020312 3E800000 v_cmp_le_f32_e32 vcc, 0, v28 ; 7C863880 v_cndmask_b32_e64 v1, v1, 1.0, vcc ; D1000001 01A9E501 v_mad_f32 v1, -v27, v1, v1 ; D1C10001 2406031B v_mac_f32_e32 v1, v27, v25 ; 2C02331B v_mov_b32_e32 v25, v1 ; 7E320301 s_or_b64 exec, exec, s[54:55] ; 87FE367E v_subrev_f32_e32 v1, s21, v16 ; 06022015 v_subrev_f32_e32 v16, s20, v17 ; 06202214 v_subrev_f32_e32 v0, s19, v0 ; 06000013 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mac_f32_e32 v1, v16, v16 ; 2C022110 v_mac_f32_e32 v1, v0, v0 ; 2C020100 v_mad_f32 v0, v26, v1, s11 ; D1C10000 002E031A v_add_f32_e64 v16, 0, v0 clamp ; D1018010 00020080 v_sub_f32_e32 v0, 1.0, v16 ; 040020F2 v_mac_f32_e32 v16, v0, v25 ; 2C203300 s_or_b64 exec, exec, s[16:17] ; 87FE107E s_buffer_load_dword s20, s[12:15], 0x10 ; C0220506 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x14 ; C0220546 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x18 ; C0220586 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x1c ; C0220486 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0xc0 ; C02205C6 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0xc4 ; C0220006 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0xcc ; C02204C6 000000CC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x14c ; C0220606 0000014C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d0 ; C0220046 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d4 ; C0220086 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x1d8 ; C02200C6 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x1dc ; C02202C6 000001DC v_mov_b32_e32 v0, s9 ; 7E000209 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v3, v16, v13 ; 2C061B10 v_mac_f32_e32 v4, v16, v14 ; 2C081D10 v_mac_f32_e32 v7, v16, v15 ; 2C0E1F10 v_cmp_ne_i32_e64 s[4:5], 0, s10 ; D0C50004 00001480 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842004 s_xor_b64 s[4:5], exec, s[4:5] ; 8884047E s_cbranch_execz BB0_7 ; BF880000 v_mul_f32_e32 v1, 0x3e59999a, v3 ; 0A0206FF 3E59999A v_madmk_f32_e32 v1, v4, v1, 0x3f372474 ; 2E020304 3F372474 v_madmk_f32_e32 v1, v7, v1, 0x3d93a92a ; 2E020307 3D93A92A v_rcp_f32_e32 v1, v1 ; 7E024501 v_mul_f32_e32 v1, v12, v1 ; 0A02030C v_sub_f32_e32 v12, 1.0, v16 ; 041820F2 v_mad_f32 v13, -v16, v1, v1 ; D1C1000D 24060310 v_mad_f32 v1, -v12, v1, 1.0 ; D1C10001 23CA030C v_mad_f32 v12, -v13, v7, v7 ; D1C1000C 241E0F0D v_mad_f32 v7, -v13, v4, v4 ; D1C10007 2412090D v_mad_f32 v13, -v13, v3, v3 ; D1C1000D 240E070D v_mad_f32 v1, 0.5, v1, 0.5 ; D1C10001 03C202F0 v_mad_f32 v3, -v1, v12, v12 ; D1C10003 24321901 v_mac_f32_e32 v3, v1, v13 ; 2C061B01 v_mad_f32 v4, -v1, v7, v7 ; D1C10004 241E0F01 v_mac_f32_e32 v4, v1, v7 ; 2C080F01 v_mad_f32 v7, -v1, v13, v13 ; D1C10007 24361B01 v_mac_f32_e32 v7, v1, v12 ; 2C0E1901 s_or_b64 exec, exec, s[4:5] ; 87FE047E v_mad_f32 v1, v11, s24, -s24 ; D1C10001 8060310B v_add_f32_e32 v11, s23, v11 ; 02161617 v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mad_f32 v12, s20, v11, -v11 ; D1C1000C 842E1614 v_mad_f32 v13, s21, v11, -v11 ; D1C1000D 842E1615 v_mad_f32 v11, s22, v11, -v11 ; D1C1000B 842E1616 v_mac_f32_e32 v3, v3, v12 ; 2C061903 v_mac_f32_e32 v4, v4, v13 ; 2C081B04 v_mac_f32_e32 v7, v7, v11 ; 2C0E1707 v_mad_f32 v1, v1, s18, s18 ; D1C10001 00482501 v_mad_f32 v6, v1, v6, -v1 ; D1C10006 84060D01 v_mac_f32_e32 v1, s19, v6 ; 2C020C13 v_mul_f32_e32 v3, v3, v8 ; 0A061103 v_mul_f32_e32 v4, v4, v9 ; 0A081304 v_mul_f32_e32 v6, v7, v10 ; 0A0C1507 v_mul_f32_e32 v7, s9, v3 ; 0A0E0609 v_mul_f32_e32 v8, s9, v4 ; 0A100809 v_mul_f32_e32 v9, s9, v6 ; 0A120C09 v_mul_f32_e32 v5, s11, v5 ; 0A0A0A0B v_mov_b32_e32 v10, 0x80000000 ; 7E1402FF 80000000 v_cmp_le_f32_e64 vcc, |s0|, v10 ; D043016A 00021400 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_mul_f32_e32 v2, v2, v2 ; 0A040502 v_mad_f32 v3, -v3, v0, s1 ; D1C10003 20060103 v_mad_f32 v4, -v4, v0, s2 ; D1C10004 200A0104 v_mad_f32 v0, -v6, v0, s3 ; D1C10000 200E0106 v_mac_f32_e32 v7, v3, v2 ; 2C0E0503 v_mac_f32_e32 v8, v4, v2 ; 2C100504 v_mac_f32_e32 v9, v0, v2 ; 2C120500 v_cmp_ngt_f32_e32 vcc, s8, v1 ; 7C960208 v_cndmask_b32_e64 v0, -1.0, 1.0, vcc ; D1000000 01A9E4F3 v_cmpx_le_f32_e32 vcc, 0, v0 ; 7CA60080 v_cvt_pkrtz_f16_f32_e64 v0, v7, v8 ; D2960000 00021107 v_cvt_pkrtz_f16_f32_e64 v1, v9, v1 ; D2960001 00020309 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 52 Code Size: 3164 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[3], PERSPECTIVE DCL IN[4], GENERIC[4], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..15], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 2.0000, -0.5000} IMM[1] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[2] FLT32 { 0.0005, 0.0000, -0.0005, 0.1250} IMM[3] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[4] FLT32 { 0.2125, 0.7154, 0.0721, 0.5000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: UIF CONST[90].xxxx :0 3: MAD TEMP[1], IN[4].xyzx, IMM[0].xxxy, IMM[0].yyyx 4: DP4 TEMP[2].x, TEMP[1], CONST[69] 5: DP4 TEMP[3].x, TEMP[1], CONST[70] 6: MOV TEMP[2].y, TEMP[3].xxxx 7: MOV_SAT TEMP[4].xy, TEMP[2].xyyy 8: ADD TEMP[4].xy, -TEMP[2].xyyy, TEMP[4].xyyy 9: DP2 TEMP[5].x, TEMP[4].xyyy, IMM[0].xxxx 10: DP4 TEMP[4].x, TEMP[1], CONST[73] 11: DP4 TEMP[6].x, TEMP[1], CONST[74] 12: MOV TEMP[4].y, TEMP[6].xxxx 13: MOV_SAT TEMP[7].xy, TEMP[4].xyyy 14: ADD TEMP[7].xy, -TEMP[4].xyyy, TEMP[7].xyyy 15: DP2 TEMP[8].x, TEMP[7].xyyy, IMM[0].xxxx 16: MOV TEMP[4].w, TEMP[8].xxxx 17: DP4 TEMP[7].x, TEMP[1], CONST[77] 18: DP4 TEMP[9].x, TEMP[1], CONST[78] 19: MOV TEMP[4].z, IMM[0].xxxx 20: MOV TEMP[10].w, TEMP[4] 21: ABS TEMP[11].x, TEMP[8].xxxx 22: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 23: UIF TEMP[11].xxxx :0 24: MOV TEMP[11].x, TEMP[4].xxxx 25: ELSE :0 26: MOV TEMP[11].x, TEMP[7].xxxx 27: ENDIF 28: MOV TEMP[10].x, TEMP[11].xxxx 29: ABS TEMP[11].x, TEMP[8].xxxx 30: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 31: UIF TEMP[11].xxxx :0 32: MOV TEMP[6].x, TEMP[6].xxxx 33: ELSE :0 34: MOV TEMP[6].x, TEMP[9].xxxx 35: ENDIF 36: MOV TEMP[10].y, TEMP[6].xxxx 37: ABS TEMP[6].x, TEMP[8].xxxx 38: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 39: UIF TEMP[6].xxxx :0 40: MOV TEMP[6].x, IMM[0].xxxx 41: ELSE :0 42: MOV TEMP[6].x, IMM[0].zzzz 43: ENDIF 44: MOV TEMP[10].z, TEMP[6].xxxx 45: MOV TEMP[4].xyz, TEMP[10] 46: ABS TEMP[6].x, TEMP[5].xxxx 47: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 48: UIF TEMP[6].xxxx :0 49: MOV TEMP[6].x, TEMP[2].xxxx 50: ELSE :0 51: MOV TEMP[6].x, TEMP[4].xxxx 52: ENDIF 53: MOV TEMP[10].x, TEMP[6].xxxx 54: ABS TEMP[6].x, TEMP[5].xxxx 55: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].yyyy 56: UIF TEMP[6].xxxx :0 57: MOV TEMP[3].x, TEMP[3].xxxx 58: ELSE :0 59: MOV TEMP[3].x, TEMP[4].yyyy 60: ENDIF 61: MOV TEMP[10].y, TEMP[3].xxxx 62: ABS TEMP[3].x, TEMP[5].xxxx 63: FSGE TEMP[3].x, -TEMP[3].xxxx, IMM[0].yyyy 64: UIF TEMP[3].xxxx :0 65: MOV TEMP[3].x, IMM[0].yyyy 66: ELSE :0 67: MOV TEMP[3].x, TEMP[4].zzzz 68: ENDIF 69: MOV TEMP[10].z, TEMP[3].xxxx 70: MOV TEMP[2].z, TEMP[10].xyzx 71: DP4 TEMP[5].x, TEMP[1], CONST[71] 72: MOV TEMP[4].z, TEMP[5].xxxx 73: ADD TEMP[7].xy, TEMP[10].xyyy, IMM[0].wwww 74: ABS TEMP[6].xy, TEMP[7].xyyy 75: ADD TEMP[7].xy, TEMP[6].xyyy, -CONST[67].zzzz 76: MUL TEMP[7].xy, TEMP[7].xyyy, CONST[67].wwww 77: MOV_SAT TEMP[6].xy, TEMP[7].xyyy 78: ADD TEMP[7].xy, -TEMP[6].xyyy, IMM[0].xxxx 79: MUL TEMP[6].x, TEMP[7].yyyy, TEMP[7].xxxx 80: MOV_SAT TEMP[8].xy, TEMP[10].xyyy 81: ADD TEMP[7].xyz, TEMP[3].xxxx, IMM[1].xyzz 82: MOV TEMP[3].y, IMM[0].yyyy 83: ABS TEMP[11].x, TEMP[7].xxxx 84: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 85: UIF TEMP[11].xxxx :0 86: MOV TEMP[11].x, CONST[85].zzzz 87: ELSE :0 88: MOV TEMP[11].x, IMM[0].yyyy 89: ENDIF 90: ABS TEMP[12].x, TEMP[7].xxxx 91: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 92: UIF TEMP[12].xxxx :0 93: MOV TEMP[12].x, CONST[85].wwww 94: ELSE :0 95: MOV TEMP[12].x, IMM[0].yyyy 96: ENDIF 97: MOV TEMP[10].y, TEMP[12].xxxx 98: ABS TEMP[12].x, TEMP[7].xxxx 99: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 100: UIF TEMP[12].xxxx :0 101: MOV TEMP[12].x, CONST[85].xxxx 102: ELSE :0 103: MOV TEMP[12].x, IMM[0].yyyy 104: ENDIF 105: MOV TEMP[10].z, TEMP[12].xxxx 106: ABS TEMP[12].x, TEMP[7].xxxx 107: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 108: UIF TEMP[12].xxxx :0 109: MOV TEMP[12].x, CONST[85].yyyy 110: ELSE :0 111: MOV TEMP[12].x, IMM[0].yyyy 112: ENDIF 113: MOV TEMP[10].w, TEMP[12].xxxx 114: ABS TEMP[12].x, TEMP[7].yyyy 115: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 116: UIF TEMP[12].xxxx :0 117: MOV TEMP[12].x, CONST[86].zzzz 118: ELSE :0 119: MOV TEMP[12].x, TEMP[11].xxxx 120: ENDIF 121: MOV TEMP[10].x, TEMP[12].xxxx 122: ABS TEMP[11].x, TEMP[7].yyyy 123: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 124: UIF TEMP[11].xxxx :0 125: MOV TEMP[11].x, CONST[86].wwww 126: ELSE :0 127: MOV TEMP[11].x, TEMP[10].yyyy 128: ENDIF 129: MOV TEMP[10].y, TEMP[11].xxxx 130: ABS TEMP[11].x, TEMP[7].yyyy 131: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 132: UIF TEMP[11].xxxx :0 133: MOV TEMP[11].x, CONST[86].xxxx 134: ELSE :0 135: MOV TEMP[11].x, TEMP[10].zzzz 136: ENDIF 137: MOV TEMP[10].z, TEMP[11].xxxx 138: ABS TEMP[11].x, TEMP[7].yyyy 139: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 140: UIF TEMP[11].xxxx :0 141: MOV TEMP[11].x, CONST[86].yyyy 142: ELSE :0 143: MOV TEMP[11].x, TEMP[10].wwww 144: ENDIF 145: MOV TEMP[10].w, TEMP[11].xxxx 146: MOV TEMP[9], TEMP[10] 147: ABS TEMP[11].x, TEMP[7].zzzz 148: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 149: UIF TEMP[11].xxxx :0 150: MOV TEMP[11].x, CONST[87].zzzz 151: ELSE :0 152: MOV TEMP[11].x, TEMP[9].xxxx 153: ENDIF 154: MOV TEMP[10].x, TEMP[11].xxxx 155: ABS TEMP[11].x, TEMP[7].zzzz 156: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 157: UIF TEMP[11].xxxx :0 158: MOV TEMP[11].x, CONST[87].wwww 159: ELSE :0 160: MOV TEMP[11].x, TEMP[9].yyyy 161: ENDIF 162: MOV TEMP[10].y, TEMP[11].xxxx 163: ABS TEMP[11].x, TEMP[7].zzzz 164: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 165: UIF TEMP[11].xxxx :0 166: MOV TEMP[11].x, CONST[87].xxxx 167: ELSE :0 168: MOV TEMP[11].x, TEMP[9].zzzz 169: ENDIF 170: MOV TEMP[10].z, TEMP[11].xxxx 171: ABS TEMP[11].x, TEMP[7].zzzz 172: FSGE TEMP[11].x, -TEMP[11].xxxx, IMM[0].yyyy 173: UIF TEMP[11].xxxx :0 174: MOV TEMP[11].x, CONST[87].yyyy 175: ELSE :0 176: MOV TEMP[11].x, TEMP[9].wwww 177: ENDIF 178: MOV TEMP[10].w, TEMP[11].xxxx 179: MAD TEMP[4].xy, TEMP[8].xyyy, TEMP[10].xyyy, TEMP[10].zwww 180: MOV TEMP[4].w, IMM[0].yyyy 181: ADD TEMP[7], TEMP[4], IMM[2].xxyy 182: TXL TEMP[8].x, TEMP[7], SAMP[1], SHADOW2D 183: MOV TEMP[7].x, TEMP[8].xxxx 184: ADD TEMP[9], TEMP[4], IMM[2].zxyy 185: ADD TEMP[8], TEMP[4], IMM[2].xzyy 186: ADD TEMP[11], TEMP[4], IMM[2].zzyy 187: TXL TEMP[12].x, TEMP[9], SAMP[1], SHADOW2D 188: MOV TEMP[7].y, TEMP[12].xxxx 189: TXL TEMP[12].x, TEMP[8], SAMP[1], SHADOW2D 190: MOV TEMP[7].z, TEMP[12].xxxx 191: TXL TEMP[12].x, TEMP[11], SAMP[1], SHADOW2D 192: MOV TEMP[7].w, TEMP[12].xxxx 193: DP4 TEMP[12].x, TEMP[7], IMM[1].wwww 194: ADD TEMP[7], TEMP[4], IMM[2].xyyy 195: TXL TEMP[13].x, TEMP[7], SAMP[1], SHADOW2D 196: MOV TEMP[7].x, TEMP[13].xxxx 197: ADD TEMP[9], TEMP[4], IMM[2].zyyy 198: TXL TEMP[13], TEMP[9], SAMP[1], SHADOW2D 199: MOV TEMP[9], TEMP[13] 200: ADD TEMP[8], TEMP[4], IMM[2].yzyy 201: TXL TEMP[14], TEMP[8], SAMP[1], SHADOW2D 202: MOV TEMP[8], TEMP[14] 203: ADD TEMP[11], TEMP[4], IMM[2].yxyy 204: TXL TEMP[15], TEMP[11], SAMP[1], SHADOW2D 205: MOV TEMP[11], TEMP[15] 206: MOV TEMP[7].y, TEMP[13].xxxx 207: MOV TEMP[7].z, TEMP[14].xxxx 208: MOV TEMP[7].w, TEMP[15].xxxx 209: DP4 TEMP[13].x, TEMP[7], IMM[2].wwww 210: MOV TEMP[2].y, TEMP[13].xxxx 211: MOV TEMP[14].xy, TEMP[4].xyyy 212: MOV TEMP[14].z, TEMP[5].xxxx 213: MOV TEMP[14].w, IMM[0].yyyy 214: TXL TEMP[14], TEMP[14], SAMP[1], SHADOW2D 215: MOV TEMP[7].xyz, TEMP[14] 216: ADD TEMP[2].x, TEMP[13].xxxx, TEMP[12].xxxx 217: MAD TEMP[2].x, TEMP[14].xxxx, IMM[3].xxxx, TEMP[2].xxxx 218: FSLT TEMP[12].x, TEMP[6].xxxx, IMM[0].xxxx 219: UIF TEMP[12].xxxx :0 220: ADD TEMP[7].xyz, TEMP[2].zzzz, IMM[3].yzww 221: ABS TEMP[12].x, TEMP[7].xxxx 222: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 223: UIF TEMP[12].xxxx :0 224: MOV TEMP[12].x, CONST[73].xxxx 225: ELSE :0 226: MOV TEMP[12].x, IMM[0].yyyy 227: ENDIF 228: MOV TEMP[10].x, TEMP[12].xxxx 229: ABS TEMP[12].x, TEMP[7].xxxx 230: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 231: UIF TEMP[12].xxxx :0 232: MOV TEMP[12].x, CONST[73].yyyy 233: ELSE :0 234: MOV TEMP[12].x, IMM[0].yyyy 235: ENDIF 236: MOV TEMP[10].y, TEMP[12].xxxx 237: ABS TEMP[12].x, TEMP[7].xxxx 238: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 239: UIF TEMP[12].xxxx :0 240: MOV TEMP[12].x, CONST[73].zzzz 241: ELSE :0 242: MOV TEMP[12].x, IMM[0].yyyy 243: ENDIF 244: MOV TEMP[10].z, TEMP[12].xxxx 245: ABS TEMP[12].x, TEMP[7].xxxx 246: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 247: UIF TEMP[12].xxxx :0 248: MOV TEMP[12].x, CONST[73].wwww 249: ELSE :0 250: MOV TEMP[12].x, IMM[0].yyyy 251: ENDIF 252: MOV TEMP[10].w, TEMP[12].xxxx 253: MOV TEMP[9], TEMP[10] 254: ABS TEMP[12].x, TEMP[7].xxxx 255: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 256: UIF TEMP[12].xxxx :0 257: MOV TEMP[12].x, CONST[74].xxxx 258: ELSE :0 259: MOV TEMP[12].x, IMM[0].yyyy 260: ENDIF 261: MOV TEMP[10].x, TEMP[12].xxxx 262: ABS TEMP[12].x, TEMP[7].xxxx 263: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 264: UIF TEMP[12].xxxx :0 265: MOV TEMP[12].x, CONST[74].yyyy 266: ELSE :0 267: MOV TEMP[12].x, IMM[0].yyyy 268: ENDIF 269: MOV TEMP[10].y, TEMP[12].xxxx 270: ABS TEMP[12].x, TEMP[7].xxxx 271: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 272: UIF TEMP[12].xxxx :0 273: MOV TEMP[12].x, CONST[74].zzzz 274: ELSE :0 275: MOV TEMP[12].x, IMM[0].yyyy 276: ENDIF 277: MOV TEMP[10].z, TEMP[12].xxxx 278: ABS TEMP[12].x, TEMP[7].xxxx 279: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 280: UIF TEMP[12].xxxx :0 281: MOV TEMP[12].x, CONST[74].wwww 282: ELSE :0 283: MOV TEMP[12].x, IMM[0].yyyy 284: ENDIF 285: MOV TEMP[10].w, TEMP[12].xxxx 286: MOV TEMP[8], TEMP[10] 287: ABS TEMP[12].x, TEMP[7].yyyy 288: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 289: UIF TEMP[12].xxxx :0 290: MOV TEMP[12].x, CONST[77].xxxx 291: ELSE :0 292: MOV TEMP[12].x, TEMP[9].xxxx 293: ENDIF 294: MOV TEMP[10].x, TEMP[12].xxxx 295: ABS TEMP[12].x, TEMP[7].yyyy 296: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 297: UIF TEMP[12].xxxx :0 298: MOV TEMP[12].x, CONST[77].yyyy 299: ELSE :0 300: MOV TEMP[12].x, TEMP[9].yyyy 301: ENDIF 302: MOV TEMP[10].y, TEMP[12].xxxx 303: ABS TEMP[12].x, TEMP[7].yyyy 304: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 305: UIF TEMP[12].xxxx :0 306: MOV TEMP[12].x, CONST[77].zzzz 307: ELSE :0 308: MOV TEMP[12].x, TEMP[9].zzzz 309: ENDIF 310: MOV TEMP[10].z, TEMP[12].xxxx 311: ABS TEMP[12].x, TEMP[7].yyyy 312: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 313: UIF TEMP[12].xxxx :0 314: MOV TEMP[12].x, CONST[77].wwww 315: ELSE :0 316: MOV TEMP[12].x, TEMP[9].wwww 317: ENDIF 318: MOV TEMP[10].w, TEMP[12].xxxx 319: MOV TEMP[9], TEMP[10] 320: ABS TEMP[12].x, TEMP[7].yyyy 321: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 322: UIF TEMP[12].xxxx :0 323: MOV TEMP[12].x, CONST[78].xxxx 324: ELSE :0 325: MOV TEMP[12].x, TEMP[8].xxxx 326: ENDIF 327: MOV TEMP[10].x, TEMP[12].xxxx 328: ABS TEMP[12].x, TEMP[7].yyyy 329: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 330: UIF TEMP[12].xxxx :0 331: MOV TEMP[12].x, CONST[78].yyyy 332: ELSE :0 333: MOV TEMP[12].x, TEMP[8].yyyy 334: ENDIF 335: MOV TEMP[10].y, TEMP[12].xxxx 336: ABS TEMP[12].x, TEMP[7].yyyy 337: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 338: UIF TEMP[12].xxxx :0 339: MOV TEMP[12].x, CONST[78].zzzz 340: ELSE :0 341: MOV TEMP[12].x, TEMP[8].zzzz 342: ENDIF 343: MOV TEMP[10].z, TEMP[12].xxxx 344: ABS TEMP[12].x, TEMP[7].yyyy 345: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 346: UIF TEMP[12].xxxx :0 347: MOV TEMP[12].x, CONST[78].wwww 348: ELSE :0 349: MOV TEMP[12].x, TEMP[8].wwww 350: ENDIF 351: MOV TEMP[10].w, TEMP[12].xxxx 352: MOV TEMP[8], TEMP[10] 353: ABS TEMP[12].x, TEMP[7].zzzz 354: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 355: UIF TEMP[12].xxxx :0 356: MOV TEMP[12].x, CONST[81].xxxx 357: ELSE :0 358: MOV TEMP[12].x, TEMP[9].xxxx 359: ENDIF 360: MOV TEMP[10].x, TEMP[12].xxxx 361: ABS TEMP[12].x, TEMP[7].zzzz 362: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 363: UIF TEMP[12].xxxx :0 364: MOV TEMP[12].x, CONST[81].yyyy 365: ELSE :0 366: MOV TEMP[12].x, TEMP[9].yyyy 367: ENDIF 368: MOV TEMP[10].y, TEMP[12].xxxx 369: ABS TEMP[12].x, TEMP[7].zzzz 370: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 371: UIF TEMP[12].xxxx :0 372: MOV TEMP[12].x, CONST[81].zzzz 373: ELSE :0 374: MOV TEMP[12].x, TEMP[9].zzzz 375: ENDIF 376: MOV TEMP[10].z, TEMP[12].xxxx 377: ABS TEMP[12].x, TEMP[7].zzzz 378: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 379: UIF TEMP[12].xxxx :0 380: MOV TEMP[12].x, CONST[81].wwww 381: ELSE :0 382: MOV TEMP[12].x, TEMP[9].wwww 383: ENDIF 384: MOV TEMP[10].w, TEMP[12].xxxx 385: MOV TEMP[9], TEMP[10] 386: ABS TEMP[12].x, TEMP[7].zzzz 387: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 388: UIF TEMP[12].xxxx :0 389: MOV TEMP[12].x, CONST[82].xxxx 390: ELSE :0 391: MOV TEMP[12].x, TEMP[8].xxxx 392: ENDIF 393: MOV TEMP[10].x, TEMP[12].xxxx 394: ABS TEMP[12].x, TEMP[7].zzzz 395: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 396: UIF TEMP[12].xxxx :0 397: MOV TEMP[12].x, CONST[82].yyyy 398: ELSE :0 399: MOV TEMP[12].x, TEMP[8].yyyy 400: ENDIF 401: MOV TEMP[10].y, TEMP[12].xxxx 402: ABS TEMP[12].x, TEMP[7].zzzz 403: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 404: UIF TEMP[12].xxxx :0 405: MOV TEMP[12].x, CONST[82].zzzz 406: ELSE :0 407: MOV TEMP[12].x, TEMP[8].zzzz 408: ENDIF 409: MOV TEMP[10].z, TEMP[12].xxxx 410: ABS TEMP[12].x, TEMP[7].zzzz 411: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 412: UIF TEMP[12].xxxx :0 413: MOV TEMP[12].x, CONST[82].wwww 414: ELSE :0 415: MOV TEMP[12].x, TEMP[8].wwww 416: ENDIF 417: MOV TEMP[10].w, TEMP[12].xxxx 418: DP4 TEMP[9].x, TEMP[1], TEMP[9] 419: MOV_SAT TEMP[9].x, TEMP[9].xxxx 420: DP4 TEMP[12].x, TEMP[1], TEMP[10] 421: MOV_SAT TEMP[12].x, TEMP[12].xxxx 422: MOV TEMP[9].y, TEMP[12].xxxx 423: ABS TEMP[12].x, TEMP[7].xxxx 424: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 425: UIF TEMP[12].xxxx :0 426: MOV TEMP[12].x, CONST[86].zzzz 427: ELSE :0 428: MOV TEMP[12].x, IMM[0].yyyy 429: ENDIF 430: ABS TEMP[13].x, TEMP[7].xxxx 431: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 432: UIF TEMP[13].xxxx :0 433: MOV TEMP[13].x, CONST[86].wwww 434: ELSE :0 435: MOV TEMP[13].x, IMM[0].yyyy 436: ENDIF 437: MOV TEMP[10].y, TEMP[13].xxxx 438: ABS TEMP[13].x, TEMP[7].xxxx 439: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 440: UIF TEMP[13].xxxx :0 441: MOV TEMP[13].x, CONST[86].xxxx 442: ELSE :0 443: MOV TEMP[13].x, IMM[0].yyyy 444: ENDIF 445: MOV TEMP[10].z, TEMP[13].xxxx 446: ABS TEMP[13].x, TEMP[7].xxxx 447: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 448: UIF TEMP[13].xxxx :0 449: MOV TEMP[13].x, CONST[86].yyyy 450: ELSE :0 451: MOV TEMP[13].x, IMM[0].yyyy 452: ENDIF 453: MOV TEMP[10].w, TEMP[13].xxxx 454: ABS TEMP[13].x, TEMP[7].yyyy 455: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[0].yyyy 456: UIF TEMP[13].xxxx :0 457: MOV TEMP[13].x, CONST[87].zzzz 458: ELSE :0 459: MOV TEMP[13].x, TEMP[12].xxxx 460: ENDIF 461: ABS TEMP[12].x, TEMP[7].yyyy 462: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 463: UIF TEMP[12].xxxx :0 464: MOV TEMP[12].x, CONST[87].wwww 465: ELSE :0 466: MOV TEMP[12].x, TEMP[10].yyyy 467: ENDIF 468: MOV TEMP[10].y, TEMP[12].xxxx 469: ABS TEMP[12].x, TEMP[7].yyyy 470: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 471: UIF TEMP[12].xxxx :0 472: MOV TEMP[12].x, CONST[87].xxxx 473: ELSE :0 474: MOV TEMP[12].x, TEMP[10].zzzz 475: ENDIF 476: MOV TEMP[10].z, TEMP[12].xxxx 477: ABS TEMP[12].x, TEMP[7].yyyy 478: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 479: UIF TEMP[12].xxxx :0 480: MOV TEMP[12].x, CONST[87].yyyy 481: ELSE :0 482: MOV TEMP[12].x, TEMP[10].wwww 483: ENDIF 484: MOV TEMP[10].w, TEMP[12].xxxx 485: ABS TEMP[12].x, TEMP[7].zzzz 486: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 487: UIF TEMP[12].xxxx :0 488: MOV TEMP[12].x, CONST[88].zzzz 489: ELSE :0 490: MOV TEMP[12].x, TEMP[13].xxxx 491: ENDIF 492: MOV TEMP[10].x, TEMP[12].xxxx 493: ABS TEMP[12].x, TEMP[7].zzzz 494: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 495: UIF TEMP[12].xxxx :0 496: MOV TEMP[12].x, CONST[88].wwww 497: ELSE :0 498: MOV TEMP[12].x, TEMP[10].yyyy 499: ENDIF 500: MOV TEMP[10].y, TEMP[12].xxxx 501: ABS TEMP[12].x, TEMP[7].zzzz 502: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 503: UIF TEMP[12].xxxx :0 504: MOV TEMP[12].x, CONST[88].xxxx 505: ELSE :0 506: MOV TEMP[12].x, TEMP[10].zzzz 507: ENDIF 508: MOV TEMP[10].z, TEMP[12].xxxx 509: ABS TEMP[12].x, TEMP[7].zzzz 510: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[0].yyyy 511: UIF TEMP[12].xxxx :0 512: MOV TEMP[12].x, CONST[88].yyyy 513: ELSE :0 514: MOV TEMP[12].x, TEMP[10].wwww 515: ENDIF 516: MOV TEMP[10].w, TEMP[12].xxxx 517: MAD TEMP[4].xy, TEMP[9].xyyy, TEMP[10].xyyy, TEMP[10].zwww 518: ADD TEMP[1], TEMP[4], IMM[2].xxyy 519: TXL TEMP[10].x, TEMP[1], SAMP[1], SHADOW2D 520: MOV TEMP[1].x, TEMP[10].xxxx 521: ADD TEMP[3], TEMP[4], IMM[2].zxyy 522: ADD TEMP[9], TEMP[4], IMM[2].xzyy 523: ADD TEMP[8], TEMP[4], IMM[2].zzyy 524: TXL TEMP[10].x, TEMP[3], SAMP[1], SHADOW2D 525: MOV TEMP[1].y, TEMP[10].xxxx 526: TXL TEMP[10].x, TEMP[9], SAMP[1], SHADOW2D 527: MOV TEMP[1].z, TEMP[10].xxxx 528: TXL TEMP[10].x, TEMP[8], SAMP[1], SHADOW2D 529: MOV TEMP[1].w, TEMP[10].xxxx 530: DP4 TEMP[10].x, TEMP[1], IMM[1].wwww 531: ADD TEMP[3], TEMP[4], IMM[2].xyyy 532: TXL TEMP[12].x, TEMP[3], SAMP[1], SHADOW2D 533: MOV TEMP[3].x, TEMP[12].xxxx 534: ADD TEMP[9], TEMP[4], IMM[2].zyyy 535: TXL TEMP[9].x, TEMP[9], SAMP[1], SHADOW2D 536: ADD TEMP[8], TEMP[4], IMM[2].yzyy 537: TXL TEMP[8].x, TEMP[8], SAMP[1], SHADOW2D 538: ADD TEMP[11], TEMP[4], IMM[2].yxyy 539: TXL TEMP[11].x, TEMP[11], SAMP[1], SHADOW2D 540: MOV TEMP[3].y, TEMP[9].xxxx 541: MOV TEMP[3].z, TEMP[8].xxxx 542: MOV TEMP[3].w, TEMP[11].xxxx 543: DP4 TEMP[3].x, TEMP[3], IMM[2].wwww 544: MOV TEMP[8].xy, TEMP[4].xyyy 545: MOV TEMP[8].z, TEMP[5].xxxx 546: MOV TEMP[8].w, IMM[0].yyyy 547: TXL TEMP[5].x, TEMP[8], SAMP[1], SHADOW2D 548: ADD TEMP[1].x, TEMP[3].xxxx, TEMP[10].xxxx 549: MAD TEMP[1].x, TEMP[5].xxxx, IMM[3].xxxx, TEMP[1].xxxx 550: FSGE TEMP[3].x, TEMP[7].zzzz, IMM[0].yyyy 551: UIF TEMP[3].xxxx :0 552: MOV TEMP[3].x, IMM[0].xxxx 553: ELSE :0 554: MOV TEMP[3].x, TEMP[1].xxxx 555: ENDIF 556: LRP TEMP[4].x, TEMP[6].xxxx, TEMP[2].xxxx, TEMP[3].xxxx 557: MOV TEMP[2].x, TEMP[4].xxxx 558: ENDIF 559: ADD TEMP[1].xyz, -CONST[89].xyzz, IN[4].xyzz 560: DP3 TEMP[3].x, TEMP[1].xyzz, TEMP[1].xyzz 561: MAD TEMP[1].x, TEMP[3].xxxx, CONST[68].yyyy, CONST[68].xxxx 562: MOV_SAT TEMP[3].x, TEMP[1].xxxx 563: LRP TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx, TEMP[2].xxxx 564: ELSE :0 565: MOV TEMP[4].x, IMM[0].xxxx 566: ENDIF 567: MAD TEMP[1].xyz, IN[1].xyzz, TEMP[4].xxxx, IN[3].xyzz 568: UIF CONST[90].xxxx :0 569: DP3 TEMP[3].x, TEMP[1].xyzz, IMM[4].xyzz 570: RCP TEMP[3].x, TEMP[3].xxxx 571: MUL TEMP[3].x, TEMP[3].xxxx, IN[1].wwww 572: ADD TEMP[2].x, -TEMP[4].xxxx, IMM[0].xxxx 573: MAD TEMP[3].x, TEMP[3].xxxx, -TEMP[2].xxxx, IMM[0].xxxx 574: MUL TEMP[2].xyz, TEMP[3].xxxx, TEMP[1].zyxx 575: MAD TEMP[3].x, TEMP[3].xxxx, IMM[4].wwww, IMM[4].wwww 576: LRP TEMP[1].xyz, TEMP[3].xxxx, TEMP[2].zyxx, TEMP[2].xyzz 577: ENDIF 578: ADD TEMP[3].x, TEMP[0].wwww, IMM[1].yyyy 579: MAD TEMP[3].x, CONST[20].wwww, TEMP[3].xxxx, IMM[0].xxxx 580: ADD TEMP[4].x, TEMP[0].wwww, CONST[12].xxxx 581: ADD TEMP[2].xyz, IMM[1].yyyy, CONST[1].xyzz 582: MOV_SAT TEMP[4].x, TEMP[4].xxxx 583: MAD TEMP[2].xyz, TEMP[4].xxxx, TEMP[2].xyzz, IMM[0].xxxx 584: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xyzz 585: MUL TEMP[3].x, TEMP[3].xxxx, CONST[1].wwww 586: MAD TEMP[4].x, TEMP[3].xxxx, IN[3].wwww, -TEMP[3].xxxx 587: MAD TEMP[3].x, CONST[12].wwww, TEMP[4].xxxx, TEMP[3].xxxx 588: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xyzz 589: ABS TEMP[1].x, CONST[12].yyyy 590: MUL TEMP[4].xyz, TEMP[0].xyzz, CONST[30].xxxx 591: MUL TEMP[2].x, CONST[29].wwww, IN[4].wwww 592: FSGE TEMP[5].x, -TEMP[1].xxxx, IMM[0].yyyy 593: UIF TEMP[5].xxxx :0 594: MOV TEMP[3].x, TEMP[3].xxxx 595: ELSE :0 596: MOV TEMP[3].x, TEMP[2].xxxx 597: ENDIF 598: MOV TEMP[1].w, TEMP[3].xxxx 599: MUL TEMP[2].x, IN[2].wwww, IN[2].wwww 600: MAD TEMP[0].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz 601: MAD TEMP[1].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[4].xyzz 602: MOV OUT[0], TEMP[1] 603: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 16) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 20) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 24) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 28) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 204) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 332) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 476) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %82 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %83 = load <8 x i32>, <8 x i32> addrspace(2)* %82, align 32, !tbaa !0 %84 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %85 = load <4 x i32>, <4 x i32> addrspace(2)* %84, align 16, !tbaa !0 %86 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %87 = load <8 x i32>, <8 x i32> addrspace(2)* %86, align 32, !tbaa !0 %88 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %89 = load <4 x i32>, <4 x i32> addrspace(2)* %88, align 16, !tbaa !0 %90 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %91 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %92 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8) %93 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8) %94 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %6, <2 x i32> %8) %95 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8) %96 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %6, <2 x i32> %8) %97 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %8) %98 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %8) %99 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %8) %100 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %6, <2 x i32> %8) %101 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %8) %102 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %8) %103 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %8) %104 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %6, <2 x i32> %8) %105 = bitcast float %90 to i32 %106 = bitcast float %91 to i32 %107 = insertelement <2 x i32> undef, i32 %105, i32 0 %108 = insertelement <2 x i32> %107, i32 %106, i32 1 %109 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %108, <8 x i32> %83, <4 x i32> %85, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %110 = extractelement <4 x float> %109, i32 0 %111 = extractelement <4 x float> %109, i32 1 %112 = extractelement <4 x float> %109, i32 2 %113 = extractelement <4 x float> %109, i32 3 %114 = bitcast float %81 to i32 %115 = icmp eq i32 %114, 0 br i1 %115, label %ENDIF, label %IF IF: ; preds = %main_body %116 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %117 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %118 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %119 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %120 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %121 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %122 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %123 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %124 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %125 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %126 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %127 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %128 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %129 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %130 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %131 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %132 = fadd float %101, 0.000000e+00 %133 = fadd float %102, 0.000000e+00 %134 = fadd float %103, 0.000000e+00 %135 = fmul float %101, 0.000000e+00 %136 = fadd float %135, 1.000000e+00 %137 = fmul float %132, %131 %138 = fmul float %133, %130 %139 = fadd float %137, %138 %140 = fmul float %134, %129 %141 = fadd float %139, %140 %142 = fmul float %136, %128 %143 = fadd float %141, %142 %144 = fmul float %132, %127 %145 = fmul float %133, %126 %146 = fadd float %144, %145 %147 = fmul float %134, %125 %148 = fadd float %146, %147 %149 = fmul float %136, %124 %150 = fadd float %148, %149 %151 = call float @llvm.AMDIL.clamp.(float %143, float 0.000000e+00, float 1.000000e+00) %152 = call float @llvm.AMDIL.clamp.(float %150, float 0.000000e+00, float 1.000000e+00) %153 = fsub float %151, %143 %154 = fsub float %152, %150 %155 = fadd float %153, %154 %156 = fmul float %132, %42 %157 = fmul float %133, %43 %158 = fadd float %156, %157 %159 = fmul float %134, %44 %160 = fadd float %158, %159 %161 = fmul float %136, %45 %162 = fadd float %160, %161 %163 = fmul float %132, %46 %164 = fmul float %133, %47 %165 = fadd float %163, %164 %166 = fmul float %134, %48 %167 = fadd float %165, %166 %168 = fmul float %136, %49 %169 = fadd float %167, %168 %170 = call float @llvm.AMDIL.clamp.(float %162, float 0.000000e+00, float 1.000000e+00) %171 = call float @llvm.AMDIL.clamp.(float %169, float 0.000000e+00, float 1.000000e+00) %172 = fsub float %170, %162 %173 = fsub float %171, %169 %174 = fadd float %172, %173 %175 = fmul float %132, %50 %176 = fmul float %133, %51 %177 = fadd float %175, %176 %178 = fmul float %134, %52 %179 = fadd float %177, %178 %180 = fmul float %136, %53 %181 = fadd float %179, %180 %182 = fmul float %132, %54 %183 = fmul float %133, %55 %184 = fadd float %182, %183 %185 = fmul float %134, %56 %186 = fadd float %184, %185 %187 = fmul float %136, %57 %188 = fadd float %186, %187 %189 = call float @llvm.fabs.f32(float %174) %190 = fcmp ole float %189, -0.000000e+00 %. = select i1 %190, float %162, float %181 %191 = call float @llvm.fabs.f32(float %174) %192 = fcmp ole float %191, -0.000000e+00 %temp24.0 = select i1 %192, float %169, float %188 %193 = call float @llvm.fabs.f32(float %174) %194 = fcmp ole float %193, -0.000000e+00 %.238 = select i1 %194, float 1.000000e+00, float 2.000000e+00 %195 = call float @llvm.fabs.f32(float %155) %196 = fcmp ole float %195, -0.000000e+00 %temp24.2 = select i1 %196, float %143, float %. %197 = call float @llvm.fabs.f32(float %155) %198 = fcmp ole float %197, -0.000000e+00 %.temp24.0 = select i1 %198, float %150, float %temp24.0 %199 = call float @llvm.fabs.f32(float %155) %200 = fcmp ole float %199, -0.000000e+00 %temp12.1 = select i1 %200, float 0.000000e+00, float %.238 %201 = fmul float %132, %123 %202 = fmul float %133, %122 %203 = fadd float %201, %202 %204 = fmul float %134, %121 %205 = fadd float %203, %204 %206 = fmul float %136, %120 %207 = fadd float %205, %206 %208 = fadd float %temp24.2, -5.000000e-01 %209 = fadd float %.temp24.0, -5.000000e-01 %210 = call float @llvm.fabs.f32(float %208) %211 = call float @llvm.fabs.f32(float %209) %212 = fsub float %210, %38 %213 = fsub float %211, %38 %214 = fmul float %212, %39 %215 = fmul float %213, %39 %216 = call float @llvm.AMDIL.clamp.(float %214, float 0.000000e+00, float 1.000000e+00) %217 = call float @llvm.AMDIL.clamp.(float %215, float 0.000000e+00, float 1.000000e+00) %218 = fsub float 1.000000e+00, %216 %219 = fsub float 1.000000e+00, %217 %220 = fmul float %219, %218 %221 = call float @llvm.AMDIL.clamp.(float %temp24.2, float 0.000000e+00, float 1.000000e+00) %222 = call float @llvm.AMDIL.clamp.(float %.temp24.0, float 0.000000e+00, float 1.000000e+00) %223 = fadd float %temp12.1, -1.000000e+00 %224 = fadd float %temp12.1, -2.000000e+00 %225 = call float @llvm.fabs.f32(float %temp12.1) %226 = fcmp ole float %225, -0.000000e+00 %.239 = select i1 %226, float %117, float 0.000000e+00 %227 = call float @llvm.fabs.f32(float %temp12.1) %228 = fcmp ole float %227, -0.000000e+00 %temp48.0 = select i1 %228, float %116, float 0.000000e+00 %229 = call float @llvm.fabs.f32(float %temp12.1) %230 = fcmp ole float %229, -0.000000e+00 %.240 = select i1 %230, float %119, float 0.000000e+00 %231 = call float @llvm.fabs.f32(float %temp12.1) %232 = fcmp ole float %231, -0.000000e+00 %temp48.2 = select i1 %232, float %118, float 0.000000e+00 %233 = call float @llvm.fabs.f32(float %223) %234 = fcmp ole float %233, -0.000000e+00 %..239 = select i1 %234, float %68, float %.239 %235 = call float @llvm.fabs.f32(float %223) %236 = fcmp ole float %235, -0.000000e+00 %temp44.2 = select i1 %236, float %69, float %temp48.0 %237 = call float @llvm.fabs.f32(float %223) %238 = fcmp ole float %237, -0.000000e+00 %..240 = select i1 %238, float %66, float %.240 %239 = call float @llvm.fabs.f32(float %223) %240 = fcmp ole float %239, -0.000000e+00 %temp44.4 = select i1 %240, float %67, float %temp48.2 %241 = call float @llvm.fabs.f32(float %224) %242 = fcmp ole float %241, -0.000000e+00 %...239 = select i1 %242, float %72, float %..239 %243 = call float @llvm.fabs.f32(float %224) %244 = fcmp ole float %243, -0.000000e+00 %temp44.6 = select i1 %244, float %73, float %temp44.2 %245 = call float @llvm.fabs.f32(float %224) %246 = fcmp ole float %245, -0.000000e+00 %...240 = select i1 %246, float %70, float %..240 %247 = call float @llvm.fabs.f32(float %224) %248 = fcmp ole float %247, -0.000000e+00 %temp44.8 = select i1 %248, float %71, float %temp44.4 %249 = fmul float %221, %...239 %250 = fadd float %249, %...240 %251 = fmul float %222, %temp44.6 %252 = fadd float %251, %temp44.8 %253 = fadd float %250, 0x3F40000000000000 %254 = fadd float %252, 0x3F40000000000000 %255 = fadd float %207, 0.000000e+00 %256 = bitcast float %255 to i32 %257 = bitcast float %253 to i32 %258 = bitcast float %254 to i32 %259 = insertelement <4 x i32> undef, i32 %256, i32 0 %260 = insertelement <4 x i32> %259, i32 %257, i32 1 %261 = insertelement <4 x i32> %260, i32 %258, i32 2 %262 = insertelement <4 x i32> %261, i32 0, i32 3 %263 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %262, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %264 = extractelement <4 x float> %263, i32 0 %265 = fadd float %250, 0xBF40000000000000 %266 = fadd float %252, 0x3F40000000000000 %267 = fadd float %207, 0.000000e+00 %268 = fadd float %250, 0x3F40000000000000 %269 = fadd float %252, 0xBF40000000000000 %270 = fadd float %207, 0.000000e+00 %271 = fadd float %250, 0xBF40000000000000 %272 = fadd float %252, 0xBF40000000000000 %273 = fadd float %207, 0.000000e+00 %274 = bitcast float %267 to i32 %275 = bitcast float %265 to i32 %276 = bitcast float %266 to i32 %277 = insertelement <4 x i32> undef, i32 %274, i32 0 %278 = insertelement <4 x i32> %277, i32 %275, i32 1 %279 = insertelement <4 x i32> %278, i32 %276, i32 2 %280 = insertelement <4 x i32> %279, i32 0, i32 3 %281 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %280, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %282 = extractelement <4 x float> %281, i32 0 %283 = bitcast float %270 to i32 %284 = bitcast float %268 to i32 %285 = bitcast float %269 to i32 %286 = insertelement <4 x i32> undef, i32 %283, i32 0 %287 = insertelement <4 x i32> %286, i32 %284, i32 1 %288 = insertelement <4 x i32> %287, i32 %285, i32 2 %289 = insertelement <4 x i32> %288, i32 0, i32 3 %290 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %289, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %291 = extractelement <4 x float> %290, i32 0 %292 = bitcast float %273 to i32 %293 = bitcast float %271 to i32 %294 = bitcast float %272 to i32 %295 = insertelement <4 x i32> undef, i32 %292, i32 0 %296 = insertelement <4 x i32> %295, i32 %293, i32 1 %297 = insertelement <4 x i32> %296, i32 %294, i32 2 %298 = insertelement <4 x i32> %297, i32 0, i32 3 %299 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %298, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %300 = extractelement <4 x float> %299, i32 0 %301 = fmul float %264, 6.250000e-02 %302 = fmul float %282, 6.250000e-02 %303 = fadd float %301, %302 %304 = fmul float %291, 6.250000e-02 %305 = fadd float %303, %304 %306 = fmul float %300, 6.250000e-02 %307 = fadd float %305, %306 %308 = fadd float %250, 0x3F40000000000000 %309 = fadd float %252, 0.000000e+00 %310 = fadd float %207, 0.000000e+00 %311 = bitcast float %310 to i32 %312 = bitcast float %308 to i32 %313 = bitcast float %309 to i32 %314 = insertelement <4 x i32> undef, i32 %311, i32 0 %315 = insertelement <4 x i32> %314, i32 %312, i32 1 %316 = insertelement <4 x i32> %315, i32 %313, i32 2 %317 = insertelement <4 x i32> %316, i32 0, i32 3 %318 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %317, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %319 = extractelement <4 x float> %318, i32 0 %320 = fadd float %250, 0xBF40000000000000 %321 = fadd float %252, 0.000000e+00 %322 = fadd float %207, 0.000000e+00 %323 = bitcast float %322 to i32 %324 = bitcast float %320 to i32 %325 = bitcast float %321 to i32 %326 = insertelement <4 x i32> undef, i32 %323, i32 0 %327 = insertelement <4 x i32> %326, i32 %324, i32 1 %328 = insertelement <4 x i32> %327, i32 %325, i32 2 %329 = insertelement <4 x i32> %328, i32 0, i32 3 %330 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %329, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %331 = extractelement <4 x float> %330, i32 0 %332 = fadd float %250, 0.000000e+00 %333 = fadd float %252, 0xBF40000000000000 %334 = fadd float %207, 0.000000e+00 %335 = bitcast float %334 to i32 %336 = bitcast float %332 to i32 %337 = bitcast float %333 to i32 %338 = insertelement <4 x i32> undef, i32 %335, i32 0 %339 = insertelement <4 x i32> %338, i32 %336, i32 1 %340 = insertelement <4 x i32> %339, i32 %337, i32 2 %341 = insertelement <4 x i32> %340, i32 0, i32 3 %342 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %341, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %343 = extractelement <4 x float> %342, i32 0 %344 = fadd float %250, 0.000000e+00 %345 = fadd float %252, 0x3F40000000000000 %346 = fadd float %207, 0.000000e+00 %347 = bitcast float %346 to i32 %348 = bitcast float %344 to i32 %349 = bitcast float %345 to i32 %350 = insertelement <4 x i32> undef, i32 %347, i32 0 %351 = insertelement <4 x i32> %350, i32 %348, i32 1 %352 = insertelement <4 x i32> %351, i32 %349, i32 2 %353 = insertelement <4 x i32> %352, i32 0, i32 3 %354 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %353, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %355 = extractelement <4 x float> %354, i32 0 %356 = fmul float %319, 1.250000e-01 %357 = fmul float %331, 1.250000e-01 %358 = fadd float %356, %357 %359 = fmul float %343, 1.250000e-01 %360 = fadd float %358, %359 %361 = fmul float %355, 1.250000e-01 %362 = fadd float %360, %361 %363 = bitcast float %207 to i32 %364 = bitcast float %250 to i32 %365 = bitcast float %252 to i32 %366 = insertelement <4 x i32> undef, i32 %363, i32 0 %367 = insertelement <4 x i32> %366, i32 %364, i32 1 %368 = insertelement <4 x i32> %367, i32 %365, i32 2 %369 = insertelement <4 x i32> %368, i32 0, i32 3 %370 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %369, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %371 = extractelement <4 x float> %370, i32 0 %372 = fadd float %362, %307 %373 = fmul float %371, 2.500000e-01 %374 = fadd float %373, %372 %375 = fcmp olt float %220, 1.000000e+00 br i1 %375, label %IF119, label %ENDIF118 ENDIF: ; preds = %main_body, %ENDIF118 %temp16.0 = phi float [ %619, %ENDIF118 ], [ 1.000000e+00, %main_body ] %376 = fmul float %92, %temp16.0 %377 = fadd float %376, %97 %378 = fmul float %93, %temp16.0 %379 = fadd float %378, %98 %380 = fmul float %94, %temp16.0 %381 = fadd float %380, %99 %382 = bitcast float %81 to i32 %383 = icmp eq i32 %382, 0 br i1 %383, label %ENDIF232, label %IF233 IF119: ; preds = %IF %384 = fadd float %temp12.1, 0.000000e+00 %385 = fadd float %temp12.1, -1.000000e+00 %386 = fadd float %temp12.1, -2.000000e+00 %387 = call float @llvm.fabs.f32(float %384) %388 = fcmp ole float %387, -0.000000e+00 %.241 = select i1 %388, float %42, float 0.000000e+00 %389 = call float @llvm.fabs.f32(float %384) %390 = fcmp ole float %389, -0.000000e+00 %temp48.5 = select i1 %390, float %43, float 0.000000e+00 %391 = call float @llvm.fabs.f32(float %384) %392 = fcmp ole float %391, -0.000000e+00 %.242 = select i1 %392, float %44, float 0.000000e+00 %393 = call float @llvm.fabs.f32(float %384) %394 = fcmp ole float %393, -0.000000e+00 %temp48.7 = select i1 %394, float %45, float 0.000000e+00 %395 = call float @llvm.fabs.f32(float %384) %396 = fcmp ole float %395, -0.000000e+00 %.243 = select i1 %396, float %46, float 0.000000e+00 %397 = call float @llvm.fabs.f32(float %384) %398 = fcmp ole float %397, -0.000000e+00 %temp48.9 = select i1 %398, float %47, float 0.000000e+00 %399 = call float @llvm.fabs.f32(float %384) %400 = fcmp ole float %399, -0.000000e+00 %.244 = select i1 %400, float %48, float 0.000000e+00 %401 = call float @llvm.fabs.f32(float %384) %402 = fcmp ole float %401, -0.000000e+00 %temp48.11 = select i1 %402, float %49, float 0.000000e+00 %403 = call float @llvm.fabs.f32(float %385) %404 = fcmp ole float %403, -0.000000e+00 %..241 = select i1 %404, float %50, float %.241 %405 = call float @llvm.fabs.f32(float %385) %406 = fcmp ole float %405, -0.000000e+00 %temp48.13 = select i1 %406, float %51, float %temp48.5 %407 = call float @llvm.fabs.f32(float %385) %408 = fcmp ole float %407, -0.000000e+00 %..242 = select i1 %408, float %52, float %.242 %409 = call float @llvm.fabs.f32(float %385) %410 = fcmp ole float %409, -0.000000e+00 %temp48.15 = select i1 %410, float %53, float %temp48.7 %411 = call float @llvm.fabs.f32(float %385) %412 = fcmp ole float %411, -0.000000e+00 %..243 = select i1 %412, float %54, float %.243 %413 = call float @llvm.fabs.f32(float %385) %414 = fcmp ole float %413, -0.000000e+00 %temp48.17 = select i1 %414, float %55, float %temp48.9 %415 = call float @llvm.fabs.f32(float %385) %416 = fcmp ole float %415, -0.000000e+00 %..244 = select i1 %416, float %56, float %.244 %417 = call float @llvm.fabs.f32(float %385) %418 = fcmp ole float %417, -0.000000e+00 %temp48.19 = select i1 %418, float %57, float %temp48.11 %419 = call float @llvm.fabs.f32(float %386) %420 = fcmp ole float %419, -0.000000e+00 %...241 = select i1 %420, float %58, float %..241 %421 = call float @llvm.fabs.f32(float %386) %422 = fcmp ole float %421, -0.000000e+00 %temp48.21 = select i1 %422, float %59, float %temp48.13 %423 = call float @llvm.fabs.f32(float %386) %424 = fcmp ole float %423, -0.000000e+00 %...242 = select i1 %424, float %60, float %..242 %425 = call float @llvm.fabs.f32(float %386) %426 = fcmp ole float %425, -0.000000e+00 %temp48.23 = select i1 %426, float %61, float %temp48.15 %427 = call float @llvm.fabs.f32(float %386) %428 = fcmp ole float %427, -0.000000e+00 %...243 = select i1 %428, float %62, float %..243 %429 = call float @llvm.fabs.f32(float %386) %430 = fcmp ole float %429, -0.000000e+00 %temp48.25 = select i1 %430, float %63, float %temp48.17 %431 = call float @llvm.fabs.f32(float %386) %432 = fcmp ole float %431, -0.000000e+00 %...244 = select i1 %432, float %64, float %..244 %433 = call float @llvm.fabs.f32(float %386) %434 = fcmp ole float %433, -0.000000e+00 %temp48.27 = select i1 %434, float %65, float %temp48.19 %435 = fmul float %132, %...241 %436 = fmul float %133, %temp48.21 %437 = fadd float %435, %436 %438 = fmul float %134, %...242 %439 = fadd float %437, %438 %440 = fmul float %136, %temp48.23 %441 = fadd float %439, %440 %442 = call float @llvm.AMDIL.clamp.(float %441, float 0.000000e+00, float 1.000000e+00) %443 = fmul float %132, %...243 %444 = fmul float %133, %temp48.25 %445 = fadd float %443, %444 %446 = fmul float %134, %...244 %447 = fadd float %445, %446 %448 = fmul float %136, %temp48.27 %449 = fadd float %447, %448 %450 = call float @llvm.AMDIL.clamp.(float %449, float 0.000000e+00, float 1.000000e+00) %451 = call float @llvm.fabs.f32(float %384) %452 = fcmp ole float %451, -0.000000e+00 %.245 = select i1 %452, float %68, float 0.000000e+00 %453 = call float @llvm.fabs.f32(float %384) %454 = fcmp ole float %453, -0.000000e+00 %temp52.0 = select i1 %454, float %69, float 0.000000e+00 %455 = call float @llvm.fabs.f32(float %384) %456 = fcmp ole float %455, -0.000000e+00 %.246 = select i1 %456, float %66, float 0.000000e+00 %457 = call float @llvm.fabs.f32(float %384) %458 = fcmp ole float %457, -0.000000e+00 %temp52.2 = select i1 %458, float %67, float 0.000000e+00 %459 = call float @llvm.fabs.f32(float %385) %460 = fcmp ole float %459, -0.000000e+00 %..245 = select i1 %460, float %72, float %.245 %461 = call float @llvm.fabs.f32(float %385) %462 = fcmp ole float %461, -0.000000e+00 %temp48.29 = select i1 %462, float %73, float %temp52.0 %463 = call float @llvm.fabs.f32(float %385) %464 = fcmp ole float %463, -0.000000e+00 %..246 = select i1 %464, float %70, float %.246 %465 = call float @llvm.fabs.f32(float %385) %466 = fcmp ole float %465, -0.000000e+00 %temp48.31 = select i1 %466, float %71, float %temp52.2 %467 = call float @llvm.fabs.f32(float %386) %468 = fcmp ole float %467, -0.000000e+00 %...245 = select i1 %468, float %76, float %..245 %469 = call float @llvm.fabs.f32(float %386) %470 = fcmp ole float %469, -0.000000e+00 %temp48.33 = select i1 %470, float %77, float %temp48.29 %471 = call float @llvm.fabs.f32(float %386) %472 = fcmp ole float %471, -0.000000e+00 %...246 = select i1 %472, float %74, float %..246 %473 = call float @llvm.fabs.f32(float %386) %474 = fcmp ole float %473, -0.000000e+00 %temp48.35 = select i1 %474, float %75, float %temp48.31 %475 = fmul float %442, %...245 %476 = fadd float %475, %...246 %477 = fmul float %450, %temp48.33 %478 = fadd float %477, %temp48.35 %479 = fadd float %476, 0x3F40000000000000 %480 = fadd float %478, 0x3F40000000000000 %481 = fadd float %207, 0.000000e+00 %482 = bitcast float %481 to i32 %483 = bitcast float %479 to i32 %484 = bitcast float %480 to i32 %485 = insertelement <4 x i32> undef, i32 %482, i32 0 %486 = insertelement <4 x i32> %485, i32 %483, i32 1 %487 = insertelement <4 x i32> %486, i32 %484, i32 2 %488 = insertelement <4 x i32> %487, i32 0, i32 3 %489 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %488, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %490 = extractelement <4 x float> %489, i32 0 %491 = fadd float %476, 0xBF40000000000000 %492 = fadd float %478, 0x3F40000000000000 %493 = fadd float %207, 0.000000e+00 %494 = fadd float %476, 0x3F40000000000000 %495 = fadd float %478, 0xBF40000000000000 %496 = fadd float %207, 0.000000e+00 %497 = fadd float %476, 0xBF40000000000000 %498 = fadd float %478, 0xBF40000000000000 %499 = fadd float %207, 0.000000e+00 %500 = bitcast float %493 to i32 %501 = bitcast float %491 to i32 %502 = bitcast float %492 to i32 %503 = insertelement <4 x i32> undef, i32 %500, i32 0 %504 = insertelement <4 x i32> %503, i32 %501, i32 1 %505 = insertelement <4 x i32> %504, i32 %502, i32 2 %506 = insertelement <4 x i32> %505, i32 0, i32 3 %507 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %506, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %508 = extractelement <4 x float> %507, i32 0 %509 = bitcast float %496 to i32 %510 = bitcast float %494 to i32 %511 = bitcast float %495 to i32 %512 = insertelement <4 x i32> undef, i32 %509, i32 0 %513 = insertelement <4 x i32> %512, i32 %510, i32 1 %514 = insertelement <4 x i32> %513, i32 %511, i32 2 %515 = insertelement <4 x i32> %514, i32 0, i32 3 %516 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %515, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %517 = extractelement <4 x float> %516, i32 0 %518 = bitcast float %499 to i32 %519 = bitcast float %497 to i32 %520 = bitcast float %498 to i32 %521 = insertelement <4 x i32> undef, i32 %518, i32 0 %522 = insertelement <4 x i32> %521, i32 %519, i32 1 %523 = insertelement <4 x i32> %522, i32 %520, i32 2 %524 = insertelement <4 x i32> %523, i32 0, i32 3 %525 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %524, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %526 = extractelement <4 x float> %525, i32 0 %527 = fmul float %490, 6.250000e-02 %528 = fmul float %508, 6.250000e-02 %529 = fadd float %527, %528 %530 = fmul float %517, 6.250000e-02 %531 = fadd float %529, %530 %532 = fmul float %526, 6.250000e-02 %533 = fadd float %531, %532 %534 = fadd float %476, 0x3F40000000000000 %535 = fadd float %478, 0.000000e+00 %536 = fadd float %207, 0.000000e+00 %537 = bitcast float %536 to i32 %538 = bitcast float %534 to i32 %539 = bitcast float %535 to i32 %540 = insertelement <4 x i32> undef, i32 %537, i32 0 %541 = insertelement <4 x i32> %540, i32 %538, i32 1 %542 = insertelement <4 x i32> %541, i32 %539, i32 2 %543 = insertelement <4 x i32> %542, i32 0, i32 3 %544 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %543, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %545 = extractelement <4 x float> %544, i32 0 %546 = fadd float %476, 0xBF40000000000000 %547 = fadd float %478, 0.000000e+00 %548 = fadd float %207, 0.000000e+00 %549 = bitcast float %548 to i32 %550 = bitcast float %546 to i32 %551 = bitcast float %547 to i32 %552 = insertelement <4 x i32> undef, i32 %549, i32 0 %553 = insertelement <4 x i32> %552, i32 %550, i32 1 %554 = insertelement <4 x i32> %553, i32 %551, i32 2 %555 = insertelement <4 x i32> %554, i32 0, i32 3 %556 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %555, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %557 = extractelement <4 x float> %556, i32 0 %558 = fadd float %476, 0.000000e+00 %559 = fadd float %478, 0xBF40000000000000 %560 = fadd float %207, 0.000000e+00 %561 = bitcast float %560 to i32 %562 = bitcast float %558 to i32 %563 = bitcast float %559 to i32 %564 = insertelement <4 x i32> undef, i32 %561, i32 0 %565 = insertelement <4 x i32> %564, i32 %562, i32 1 %566 = insertelement <4 x i32> %565, i32 %563, i32 2 %567 = insertelement <4 x i32> %566, i32 0, i32 3 %568 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %567, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %569 = extractelement <4 x float> %568, i32 0 %570 = fadd float %476, 0.000000e+00 %571 = fadd float %478, 0x3F40000000000000 %572 = fadd float %207, 0.000000e+00 %573 = bitcast float %572 to i32 %574 = bitcast float %570 to i32 %575 = bitcast float %571 to i32 %576 = insertelement <4 x i32> undef, i32 %573, i32 0 %577 = insertelement <4 x i32> %576, i32 %574, i32 1 %578 = insertelement <4 x i32> %577, i32 %575, i32 2 %579 = insertelement <4 x i32> %578, i32 0, i32 3 %580 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %579, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %581 = extractelement <4 x float> %580, i32 0 %582 = fmul float %545, 1.250000e-01 %583 = fmul float %557, 1.250000e-01 %584 = fadd float %582, %583 %585 = fmul float %569, 1.250000e-01 %586 = fadd float %584, %585 %587 = fmul float %581, 1.250000e-01 %588 = fadd float %586, %587 %589 = bitcast float %207 to i32 %590 = bitcast float %476 to i32 %591 = bitcast float %478 to i32 %592 = insertelement <4 x i32> undef, i32 %589, i32 0 %593 = insertelement <4 x i32> %592, i32 %590, i32 1 %594 = insertelement <4 x i32> %593, i32 %591, i32 2 %595 = insertelement <4 x i32> %594, i32 0, i32 3 %596 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %595, <8 x i32> %87, <4 x i32> %89, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %597 = extractelement <4 x float> %596, i32 0 %598 = fadd float %588, %533 %599 = fmul float %597, 2.500000e-01 %600 = fadd float %599, %598 %601 = fcmp oge float %386, 0.000000e+00 %.247 = select i1 %601, float 1.000000e+00, float %600 %602 = fsub float 1.000000e+00, %220 %603 = fmul float %374, %220 %604 = fmul float %.247, %602 %605 = fadd float %603, %604 br label %ENDIF118 ENDIF118: ; preds = %IF, %IF119 %temp8.0 = phi float [ %605, %IF119 ], [ %374, %IF ] %606 = fsub float %101, %78 %607 = fsub float %102, %79 %608 = fsub float %103, %80 %609 = fmul float %606, %606 %610 = fmul float %607, %607 %611 = fadd float %610, %609 %612 = fmul float %608, %608 %613 = fadd float %611, %612 %614 = fmul float %613, %41 %615 = fadd float %614, %40 %616 = call float @llvm.AMDIL.clamp.(float %615, float 0.000000e+00, float 1.000000e+00) %617 = fsub float 1.000000e+00, %616 %618 = fmul float %temp8.0, %617 %619 = fadd float %616, %618 br label %ENDIF IF233: ; preds = %ENDIF %620 = fmul float %377, 0x3FCB333340000000 %621 = fmul float %379, 0x3FE6E48E80000000 %622 = fadd float %621, %620 %623 = fmul float %381, 0x3FB2752540000000 %624 = fadd float %622, %623 %625 = fdiv float 1.000000e+00, %624 %626 = fmul float %625, %95 %627 = fsub float 1.000000e+00, %temp16.0 %628 = fmul float %627, %626 %629 = fsub float 1.000000e+00, %628 %630 = fmul float %629, %381 %631 = fmul float %629, %379 %632 = fmul float %629, %377 %633 = fmul float %629, 5.000000e-01 %634 = fadd float %633, 5.000000e-01 %635 = fsub float 1.000000e+00, %634 %636 = fmul float %632, %634 %637 = fmul float %630, %635 %638 = fadd float %636, %637 %639 = fsub float 1.000000e+00, %634 %640 = fmul float %631, %634 %641 = fmul float %631, %639 %642 = fadd float %640, %641 %643 = fsub float 1.000000e+00, %634 %644 = fmul float %630, %634 %645 = fmul float %632, %643 %646 = fadd float %644, %645 br label %ENDIF232 ENDIF232: ; preds = %ENDIF, %IF233 %temp5.0 = phi float [ %642, %IF233 ], [ %379, %ENDIF ] %temp6.0 = phi float [ %646, %IF233 ], [ %381, %ENDIF ] %temp4.0 = phi float [ %638, %IF233 ], [ %377, %ENDIF ] %647 = fadd float %113, -1.000000e+00 %648 = fmul float %32, %647 %649 = fadd float %648, 1.000000e+00 %650 = fadd float %113, %29 %651 = fadd float %25, -1.000000e+00 %652 = fadd float %26, -1.000000e+00 %653 = fadd float %27, -1.000000e+00 %654 = call float @llvm.AMDIL.clamp.(float %650, float 0.000000e+00, float 1.000000e+00) %655 = fmul float %654, %651 %656 = fadd float %655, 1.000000e+00 %657 = fmul float %654, %652 %658 = fadd float %657, 1.000000e+00 %659 = fmul float %654, %653 %660 = fadd float %659, 1.000000e+00 %661 = fmul float %temp4.0, %656 %662 = fmul float %temp5.0, %658 %663 = fmul float %temp6.0, %660 %664 = fmul float %649, %28 %665 = fmul float %664, %100 %666 = fsub float %665, %664 %667 = fmul float %31, %666 %668 = fadd float %667, %664 %669 = fmul float %110, %661 %670 = fmul float %111, %662 %671 = fmul float %112, %663 %672 = call float @llvm.fabs.f32(float %30) %673 = fmul float %669, %37 %674 = fmul float %670, %37 %675 = fmul float %671, %37 %676 = fmul float %36, %104 %677 = fcmp ole float %672, -0.000000e+00 %.248 = select i1 %677, float %668, float %676 %678 = fmul float %96, %96 %679 = fmul float %37, %669 %680 = fsub float %33, %679 %681 = fmul float %37, %670 %682 = fsub float %34, %681 %683 = fmul float %37, %671 %684 = fsub float %35, %683 %685 = fmul float %678, %680 %686 = fadd float %685, %673 %687 = fmul float %678, %682 %688 = fadd float %687, %674 %689 = fmul float %678, %684 %690 = fadd float %689, %675 %691 = call i32 @llvm.SI.packf16(float %686, float %688) %692 = bitcast i32 %691 to float %693 = call i32 @llvm.SI.packf16(float %690, float %.248) %694 = bitcast i32 %693 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %692, float %694, float %692, float %694) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_mov_b32 m0, s10 ; BEFC000A s_load_dwordx8 s[16:23], s[6:7], 0x0 ; C00E0403 00000000 v_interp_p1_f32 v8, v0, 0, 0, [m0] ; D4200000 v_interp_p2_f32 v8, [v8], v1, 0, 0, [m0] ; D4210001 v_interp_p1_f32 v9, v0, 1, 0, [m0] ; D4240100 v_interp_p2_f32 v9, [v9], v1, 1, 0, [m0] ; D4250101 v_interp_p1_f32 v13, v0, 0, 1, [m0] ; D4340400 v_interp_p2_f32 v13, [v13], v1, 0, 1, [m0] ; D4350401 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x5a0 ; C0220246 000005A0 v_interp_p1_f32 v14, v0, 1, 1, [m0] ; D4380500 v_interp_p2_f32 v14, [v14], v1, 1, 1, [m0] ; D4390501 v_interp_p1_f32 v15, v0, 2, 1, [m0] ; D43C0600 v_interp_p2_f32 v15, [v15], v1, 2, 1, [m0] ; D43D0601 v_interp_p1_f32 v12, v0, 3, 1, [m0] ; D4300700 v_interp_p2_f32 v12, [v12], v1, 3, 1, [m0] ; D4310701 v_interp_p1_f32 v2, v0, 3, 2, [m0] ; D4080B00 v_interp_p2_f32 v2, [v2], v1, 3, 2, [m0] ; D4090B01 v_interp_p1_f32 v3, v0, 0, 3, [m0] ; D40C0C00 s_load_dwordx4 s[0:3], s[4:5], 0x0 ; C00A0002 00000000 v_interp_p2_f32 v3, [v3], v1, 0, 3, [m0] ; D40D0C01 v_interp_p1_f32 v4, v0, 1, 3, [m0] ; D4100D00 v_interp_p2_f32 v4, [v4], v1, 1, 3, [m0] ; D4110D01 v_interp_p1_f32 v7, v0, 2, 3, [m0] ; D41C0E00 v_interp_p2_f32 v7, [v7], v1, 2, 3, [m0] ; D41D0E01 v_interp_p1_f32 v6, v0, 3, 3, [m0] ; D4180F00 v_interp_p2_f32 v6, [v6], v1, 3, 3, [m0] ; D4190F01 v_interp_p1_f32 v5, v0, 3, 4, [m0] ; D4141300 v_interp_p2_f32 v5, [v5], v1, 3, 4, [m0] ; D4151301 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[8:11], 15, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[16:23], s[0:3] ; F0800F00 00040808 v_cmp_ne_i32_e64 s[0:1], 0, s9 ; D0C50000 00001280 v_mov_b32_e32 v16, 1.0 ; 7E2002F2 s_waitcnt vmcnt(0) ; BF8C0770 s_and_saveexec_b64 s[10:11], s[0:1] ; BE8A2000 s_xor_b64 s[10:11], exec, s[10:11] ; 888A0A7E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x440 ; C0220406 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x4a0 ; C0220446 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4a4 ; C0220546 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a8 ; C0220586 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4ac ; C02205C6 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4d0 ; C0220606 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d4 ; C0220646 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x4d8 ; C0220686 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4dc ; C02206C6 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4e0 ; C0220746 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4e4 ; C02207C6 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x4e8 ; C0220806 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4ec ; C0220886 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s56, s[12:15], 0x550 ; C0220E06 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[12:15], 0x554 ; C0220E46 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[12:15], 0x558 ; C0220E86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x570 ; C0220906 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x574 ; C0220946 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x578 ; C02209C6 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x57c ; C0220A46 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x590 ; C0220506 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x594 ; C02204C6 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x598 ; C0220486 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x20 ; C00E0B03 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x10 ; C00A0D02 00000010 v_interp_p1_f32 v16, v0, 0, 4, [m0] ; D4401000 v_interp_p2_f32 v16, [v16], v1, 0, 4, [m0] ; D4411001 v_interp_p1_f32 v17, v0, 1, 4, [m0] ; D4441100 v_interp_p2_f32 v17, [v17], v1, 1, 4, [m0] ; D4451101 v_interp_p1_f32 v0, v0, 2, 4, [m0] ; D4001200 v_interp_p2_f32 v0, [v0], v1, 2, 4, [m0] ; D4011201 s_buffer_load_dword s59, s[12:15], 0x55c ; C0220EC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x560 ; C0220986 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x564 ; C0220A06 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x568 ; C0220A86 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x56c ; C0220AC6 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x490 ; C0220706 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x494 ; C0220786 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x498 ; C0220846 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x49c ; C02208C6 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v22, 0, v17 ; 022C2280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s66, v22 ; 0A242C42 v_add_f32_e32 v24, 0, v16 ; 02302080 v_add_f32_e32 v23, 0, v0 ; 022E0080 v_mad_f32 v1, 0, v16, 1.0 ; D1C10001 03CA2080 v_mac_f32_e32 v18, s3, v24 ; 2C243003 v_mac_f32_e32 v18, s67, v23 ; 2C242E43 v_mac_f32_e32 v18, s68, v1 ; 2C240244 v_mul_f32_e32 v19, s70, v22 ; 0A262C46 v_mac_f32_e32 v19, s69, v24 ; 2C263045 v_mac_f32_e32 v19, s61, v23 ; 2C262E3D v_mac_f32_e32 v19, s62, v1 ; 2C26023E v_add_f32_e64 v20, 0, v18 clamp ; D1018014 00022480 v_add_f32_e64 v21, 0, v19 clamp ; D1018015 00022680 v_subrev_f32_e32 v20, v18, v20 ; 06282912 v_subrev_f32_e32 v21, v19, v21 ; 062A2B13 v_add_f32_e32 v20, v21, v20 ; 02282915 v_mul_f32_e32 v21, s30, v22 ; 0A2A2C1E v_mac_f32_e32 v21, s28, v24 ; 2C2A301C v_mac_f32_e32 v21, s33, v23 ; 2C2A2E21 v_mac_f32_e32 v21, s35, v1 ; 2C2A0223 v_mul_f32_e32 v25, s21, v22 ; 0A322C15 v_mac_f32_e32 v25, s17, v24 ; 2C323011 v_mac_f32_e32 v25, s22, v23 ; 2C322E16 v_mac_f32_e32 v25, s23, v1 ; 2C320217 v_add_f32_e64 v26, 0, v21 clamp ; D101801A 00022A80 v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_subrev_f32_e32 v26, v21, v26 ; 06343515 v_subrev_f32_e32 v27, v25, v27 ; 06363719 v_add_f32_e32 v26, v27, v26 ; 0234351B v_mul_f32_e32 v27, s25, v22 ; 0A362C19 v_mac_f32_e32 v27, s24, v24 ; 2C363018 v_mac_f32_e32 v27, s26, v23 ; 2C362E1A v_mac_f32_e32 v27, s27, v1 ; 2C36021B v_mul_f32_e32 v28, s31, v22 ; 0A382C1F v_mac_f32_e32 v28, s29, v24 ; 2C38301D v_mac_f32_e32 v28, s32, v23 ; 2C382E20 v_mac_f32_e32 v28, s34, v1 ; 2C380222 v_mov_b32_e32 v29, 0x80000000 ; 7E3A02FF 80000000 v_cmp_le_f32_e64 vcc, |v26|, v29 ; D043016A 00023B1A v_cndmask_b32_e32 v21, v27, v21 ; 002A2B1B v_cndmask_b32_e32 v25, v28, v25 ; 0032331C v_cndmask_b32_e64 v26, 2.0, 1.0, vcc ; D100001A 01A9E4F4 v_cmp_le_f32_e64 vcc, |v20|, v29 ; D043016A 00023B14 v_cndmask_b32_e32 v21, v21, v18 ; 002A2515 v_cndmask_b32_e32 v25, v25, v19 ; 00322719 v_cndmask_b32_e64 v28, v26, 0, vcc ; D100001C 01A9011A v_mul_f32_e32 v18, s64, v22 ; 0A242C40 v_mac_f32_e32 v18, s63, v24 ; 2C24303F v_mac_f32_e32 v18, s65, v23 ; 2C242E41 v_mac_f32_e32 v18, s60, v1 ; 2C24023C v_add_f32_e64 v26, 0, v21 clamp ; D101801A 00022A80 v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_add_f32_e32 v19, -1.0, v28 ; 022638F3 v_add_f32_e32 v20, -2.0, v28 ; 022838F5 v_cmp_le_f32_e64 vcc, |v28|, v29 ; D043016A 00023B1C v_mov_b32_e32 v30, s58 ; 7E3C023A v_cndmask_b32_e32 v30, 0, v30 ; 003C3C80 v_mov_b32_e32 v31, s59 ; 7E3E023B v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_mov_b32_e32 v32, s56 ; 7E400238 v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_mov_b32_e32 v33, s57 ; 7E420239 v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_cmp_le_f32_e64 vcc, |v19|, v29 ; D043016A 00023B13 v_mov_b32_e32 v19, s42 ; 7E26022A v_cndmask_b32_e32 v19, v30, v19 ; 0026271E v_mov_b32_e32 v30, s43 ; 7E3C022B v_cndmask_b32_e32 v30, v31, v30 ; 003C3D1F v_mov_b32_e32 v31, s38 ; 7E3E0226 v_cndmask_b32_e32 v31, v32, v31 ; 003E3F20 v_mov_b32_e32 v32, s40 ; 7E400228 v_cndmask_b32_e32 v32, v33, v32 ; 00404121 v_cmp_le_f32_e64 vcc, |v20|, v29 ; D043016A 00023B14 v_mov_b32_e32 v20, s39 ; 7E280227 v_cndmask_b32_e32 v29, v19, v20 ; 003A2913 v_mov_b32_e32 v19, s41 ; 7E260229 v_cndmask_b32_e32 v30, v30, v19 ; 003C271E v_mov_b32_e32 v19, s36 ; 7E260224 v_cndmask_b32_e32 v19, v31, v19 ; 0026271F v_mov_b32_e32 v20, s37 ; 7E280225 v_cndmask_b32_e32 v20, v32, v20 ; 00282920 v_mac_f32_e32 v19, v29, v26 ; 2C26351D v_mac_f32_e32 v20, v30, v27 ; 2C28371E v_mov_b32_e32 v26, 0x3a000000 ; 7E3402FF 3A000000 v_add_f32_e32 v30, v26, v19 ; 023C271A v_add_f32_e32 v31, v26, v20 ; 023E291A v_add_f32_e32 v29, 0, v18 ; 023A2480 s_mov_b32 s56, 0 ; BEB80080 v_mov_b32_e32 v32, s56 ; 7E400238 v_mov_b32_e32 v26, 0xba000000 ; 7E3402FF BA000000 v_add_f32_e32 v27, v26, v19 ; 0236271A v_mov_b32_e32 v33, v29 ; 7E42031D v_mov_b32_e32 v34, v30 ; 7E44031E v_mov_b32_e32 v35, v31 ; 7E46031F v_mov_b32_e32 v36, v32 ; 7E480320 v_add_f32_e32 v26, v26, v20 ; 0234291A v_mov_b32_e32 v34, v27 ; 7E44031B v_mov_b32_e32 v37, v29 ; 7E4A031D v_mov_b32_e32 v38, v30 ; 7E4C031E v_mov_b32_e32 v39, v31 ; 7E4E031F v_mov_b32_e32 v40, v32 ; 7E500320 v_mov_b32_e32 v35, v31 ; 7E46031F v_mov_b32_e32 v39, v26 ; 7E4E031A v_mov_b32_e32 v36, s56 ; 7E480238 v_mov_b32_e32 v40, s56 ; 7E500238 image_sample_c_l v27, 1, 0, 0, 0, 0, 0, 0, 0, v[29:32], s[44:51], s[52:55] ; F0B00100 01AB1B1D s_nop 0 ; BF800000 image_sample_c_l v41, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[52:55] ; F0B00100 01AB2921 v_mov_b32_e32 v35, v26 ; 7E46031A image_sample_c_l v37, 1, 0, 0, 0, 0, 0, 0, 0, v[37:40], s[44:51], s[52:55] ; F0B00100 01AB2525 v_mov_b32_e32 v36, s56 ; 7E480238 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[52:55] ; F0B00100 01AB2621 v_add_f32_e32 v35, 0, v20 ; 02462880 v_mov_b32_e32 v42, v29 ; 7E54031D v_mov_b32_e32 v43, v30 ; 7E56031E v_mov_b32_e32 v44, v31 ; 7E58031F v_mov_b32_e32 v45, v32 ; 7E5A0320 v_mov_b32_e32 v44, v35 ; 7E580323 v_add_f32_e32 v30, 0, v19 ; 023C2680 v_mov_b32_e32 v45, s56 ; 7E5A0238 v_mov_b32_e32 v46, v29 ; 7E5C031D v_mov_b32_e32 v47, v30 ; 7E5E031E v_mov_b32_e32 v48, v31 ; 7E60031F v_mov_b32_e32 v49, v32 ; 7E620320 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[44:51], s[52:55] ; F0B00100 01AB272A v_mov_b32_e32 v48, v26 ; 7E60031A v_mov_b32_e32 v36, s56 ; 7E480238 image_sample_c_l v26, 1, 0, 0, 0, 0, 0, 0, 0, v[33:36], s[44:51], s[52:55] ; F0B00100 01AB1A21 v_mov_b32_e32 v49, s56 ; 7E620238 image_sample_c_l v33, 1, 0, 0, 0, 0, 0, 0, 0, v[46:49], s[44:51], s[52:55] ; F0B00100 01AB212E v_mov_b32_e32 v32, s56 ; 7E400238 image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[29:32], s[44:51], s[52:55] ; F0B00100 01AB1D1D v_mov_b32_e32 v30, 0x3d800000 ; 7E3C02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v31, v30, v41 ; 0A3E531E v_mac_f32_e32 v31, v30, v27 ; 2C3E371E s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v31, v30, v37 ; 2C3E4B1E s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v31, v30, v38 ; 2C3E4D1E v_mov_b32_e32 v27, 0x3e000000 ; 7E3602FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v26, v27, v26 ; 0A34351B v_mac_f32_e32 v26, v27, v39 ; 2C344F1B s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v26, v27, v33 ; 2C34431B s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v26, v27, v29 ; 2C343B1B v_add_f32_e32 v21, -0.5, v21 ; 022A2AF1 v_add_f32_e32 v25, -0.5, v25 ; 023232F1 v_sub_f32_e64 v21, |v21|, s1 ; D1020115 00000315 v_sub_f32_e64 v25, |v25|, s1 ; D1020119 00000319 v_mul_f32_e32 v21, s2, v21 ; 0A2A2A02 v_mul_f32_e32 v25, s2, v25 ; 0A323202 v_add_f32_e64 v21, 0, v21 clamp ; D1018015 00022A80 v_add_f32_e64 v25, 0, v25 clamp ; D1018019 00023280 v_sub_f32_e32 v21, 1.0, v21 ; 042A2AF2 v_mad_f32 v27, -v25, v21, v21 ; D1C1001B 24562B19 v_mov_b32_e32 v21, 0 ; 7E2A0280 v_add_f32_e32 v25, v31, v26 ; 0232351F image_sample_c_l v19, 1, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[44:51], s[52:55] ; F0B00100 01AB1312 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v25, v19, v25, 0x3e800000 ; 2E323313 3E800000 v_mov_b32_e32 v26, s0 ; 7E340200 v_cmp_gt_f32_e32 vcc, 1.0, v27 ; 7C8836F2 s_and_saveexec_b64 s[58:59], vcc ; BEBA206A s_xor_b64 s[58:59], exec, s[58:59] ; 88BA3A7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s57, s[12:15], 0x510 ; C0220E46 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x514 ; C0220F06 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x518 ; C0220F46 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x51c ; C0220F86 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x520 ; C0220FC6 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x524 ; C0221006 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x528 ; C0221046 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x52c ; C0221086 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x580 ; C02210C6 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x584 ; C0221106 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x588 ; C0221146 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x58c ; C0221186 0000058C v_mov_b32_e32 v19, s28 ; 7E26021C v_mov_b32_e32 v20, s30 ; 7E28021E v_mov_b32_e32 v21, s33 ; 7E2A0221 v_mov_b32_e32 v29, s35 ; 7E3A0223 v_mov_b32_e32 v30, s17 ; 7E3C0211 v_mov_b32_e32 v31, s21 ; 7E3E0215 v_mov_b32_e32 v32, s22 ; 7E400216 v_mov_b32_e32 v33, s23 ; 7E420217 v_mov_b32_e32 v34, s24 ; 7E440218 v_mov_b32_e32 v35, s25 ; 7E460219 v_mov_b32_e32 v36, s26 ; 7E48021A v_add_f32_e32 v37, 0, v28 ; 024A3880 v_mov_b32_e32 v38, 0x80000000 ; 7E4C02FF 80000000 v_cmp_le_f32_e64 vcc, |v37|, v38 ; D043016A 00024D25 v_add_f32_e32 v37, -1.0, v28 ; 024A38F3 v_cmp_le_f32_e64 s[0:1], |v37|, v38 ; D0430100 00024D25 v_mov_b32_e32 v37, s27 ; 7E4A021B v_cndmask_b32_e32 v19, 0, v19 ; 00262680 v_cndmask_b32_e64 v19, v19, v34, s[0:1] ; D1000013 00024513 v_mov_b32_e32 v34, s29 ; 7E44021D v_cndmask_b32_e32 v20, 0, v20 ; 00282880 v_cndmask_b32_e64 v20, v20, v35, s[0:1] ; D1000014 00024714 v_mov_b32_e32 v35, s31 ; 7E46021F v_cndmask_b32_e32 v21, 0, v21 ; 002A2A80 v_cndmask_b32_e64 v21, v21, v36, s[0:1] ; D1000015 00024915 v_mov_b32_e32 v36, s32 ; 7E480220 v_cndmask_b32_e32 v29, 0, v29 ; 003A3A80 v_cndmask_b32_e64 v29, v29, v37, s[0:1] ; D100001D 00024B1D v_mov_b32_e32 v37, s34 ; 7E4A0222 v_cndmask_b32_e32 v30, 0, v30 ; 003C3C80 v_cndmask_b32_e64 v30, v30, v34, s[0:1] ; D100001E 0002451E v_mov_b32_e32 v34, s38 ; 7E440226 v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_cndmask_b32_e64 v31, v31, v35, s[0:1] ; D100001F 0002471F v_mov_b32_e32 v35, s40 ; 7E460228 v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_cndmask_b32_e64 v32, v32, v36, s[0:1] ; D1000020 00024920 v_mov_b32_e32 v36, s42 ; 7E48022A v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_cndmask_b32_e64 v33, v33, v37, s[0:1] ; D1000021 00024B21 v_mov_b32_e32 v37, s43 ; 7E4A022B v_add_f32_e32 v28, -2.0, v28 ; 023838F5 v_cmp_le_f32_e64 s[2:3], |v28|, v38 ; D0430102 00024D1C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v38, s57 ; 7E4C0239 v_cndmask_b32_e64 v19, v19, v38, s[2:3] ; D1000013 000A4D13 v_mov_b32_e32 v38, s60 ; 7E4C023C v_cndmask_b32_e64 v20, v20, v38, s[2:3] ; D1000014 000A4D14 v_mov_b32_e32 v38, s61 ; 7E4C023D v_cndmask_b32_e64 v21, v21, v38, s[2:3] ; D1000015 000A4D15 v_mov_b32_e32 v38, s62 ; 7E4C023E v_cndmask_b32_e64 v29, v29, v38, s[2:3] ; D100001D 000A4D1D v_mov_b32_e32 v38, s63 ; 7E4C023F v_cndmask_b32_e64 v30, v30, v38, s[2:3] ; D100001E 000A4D1E v_mov_b32_e32 v38, s64 ; 7E4C0240 v_cndmask_b32_e64 v31, v31, v38, s[2:3] ; D100001F 000A4D1F v_mov_b32_e32 v38, s65 ; 7E4C0241 v_cndmask_b32_e64 v32, v32, v38, s[2:3] ; D1000020 000A4D20 v_mov_b32_e32 v38, s66 ; 7E4C0242 v_cndmask_b32_e64 v33, v33, v38, s[2:3] ; D1000021 000A4D21 v_mov_b32_e32 v38, s36 ; 7E4C0224 v_mul_f32_e32 v20, v20, v22 ; 0A282D14 v_mac_f32_e32 v20, v19, v24 ; 2C283113 v_mov_b32_e32 v19, s37 ; 7E260225 v_mac_f32_e32 v20, v21, v23 ; 2C282F15 v_mov_b32_e32 v21, s39 ; 7E2A0227 v_mac_f32_e32 v20, v29, v1 ; 2C28031D v_mov_b32_e32 v29, s41 ; 7E3A0229 v_add_f32_e64 v39, 0, v20 clamp ; D1018027 00022880 v_mul_f32_e32 v20, v31, v22 ; 0A282D1F v_mac_f32_e32 v20, v30, v24 ; 2C28311E v_mac_f32_e32 v20, v32, v23 ; 2C282F20 v_mac_f32_e32 v20, v33, v1 ; 2C280321 v_add_f32_e64 v1, 0, v20 clamp ; D1018001 00022880 v_cndmask_b32_e32 v20, 0, v36 ; 00284880 v_cndmask_b32_e32 v22, 0, v37 ; 002C4A80 v_cndmask_b32_e32 v23, 0, v34 ; 002E4480 v_cndmask_b32_e32 v24, 0, v35 ; 00304680 v_cndmask_b32_e64 v20, v20, v21, s[0:1] ; D1000014 00022B14 v_cndmask_b32_e64 v21, v22, v29, s[0:1] ; D1000015 00023B16 v_cndmask_b32_e64 v22, v23, v38, s[0:1] ; D1000016 00024D17 v_cndmask_b32_e64 v23, v24, v19, s[0:1] ; D1000017 00022718 v_mov_b32_e32 v19, s69 ; 7E260245 v_cndmask_b32_e64 v24, v20, v19, s[2:3] ; D1000018 000A2714 v_mov_b32_e32 v19, s70 ; 7E260246 v_cndmask_b32_e64 v21, v21, v19, s[2:3] ; D1000015 000A2715 v_mov_b32_e32 v19, s67 ; 7E260243 v_cndmask_b32_e64 v19, v22, v19, s[2:3] ; D1000013 000A2716 v_mov_b32_e32 v20, s68 ; 7E280244 v_cndmask_b32_e64 v20, v23, v20, s[2:3] ; D1000014 000A2917 v_mac_f32_e32 v19, v24, v39 ; 2C264F18 v_mac_f32_e32 v20, v21, v1 ; 2C280315 v_mov_b32_e32 v1, 0x3a000000 ; 7E0202FF 3A000000 v_add_f32_e32 v22, v1, v19 ; 022C2701 v_add_f32_e32 v23, v1, v20 ; 022E2901 v_add_f32_e32 v21, 0, v18 ; 022A2480 v_mov_b32_e32 v24, s56 ; 7E300238 v_mov_b32_e32 v1, 0xba000000 ; 7E0202FF BA000000 v_add_f32_e32 v29, v1, v19 ; 023A2701 v_mov_b32_e32 v30, v21 ; 7E3C0315 v_mov_b32_e32 v31, v22 ; 7E3E0316 v_mov_b32_e32 v32, v23 ; 7E400317 v_mov_b32_e32 v33, v24 ; 7E420318 v_mov_b32_e32 v31, v29 ; 7E3E031D v_add_f32_e32 v1, v1, v20 ; 02022901 v_mov_b32_e32 v32, v23 ; 7E400317 v_mov_b32_e32 v34, v21 ; 7E440315 v_mov_b32_e32 v35, v22 ; 7E460316 v_mov_b32_e32 v36, v23 ; 7E480317 v_mov_b32_e32 v37, v24 ; 7E4A0318 image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[44:51], s[52:55] ; F0B00100 01AB1D15 v_mov_b32_e32 v33, s56 ; 7E420238 v_mov_b32_e32 v36, v1 ; 7E480301 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[52:55] ; F0B00100 01AB261E v_mov_b32_e32 v37, s56 ; 7E4A0238 v_mov_b32_e32 v32, v1 ; 7E400301 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2222 v_mov_b32_e32 v33, s56 ; 7E420238 image_sample_c_l v35, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[52:55] ; F0B00100 01AB231E v_add_f32_e32 v32, 0, v20 ; 02402880 v_mov_b32_e32 v39, v21 ; 7E4E0315 v_mov_b32_e32 v40, v22 ; 7E500316 v_mov_b32_e32 v41, v23 ; 7E520317 v_mov_b32_e32 v42, v24 ; 7E540318 v_mov_b32_e32 v41, v32 ; 7E520320 v_add_f32_e32 v22, 0, v19 ; 022C2680 v_mov_b32_e32 v42, s56 ; 7E540238 v_mov_b32_e32 v43, v21 ; 7E560315 v_mov_b32_e32 v44, v22 ; 7E580316 v_mov_b32_e32 v45, v23 ; 7E5A0317 v_mov_b32_e32 v46, v24 ; 7E5C0318 image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[52:55] ; F0B00100 01AB2427 v_mov_b32_e32 v45, v1 ; 7E5A0301 v_mov_b32_e32 v33, s56 ; 7E420238 image_sample_c_l v1, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[52:55] ; F0B00100 01AB011E v_mov_b32_e32 v46, s56 ; 7E5C0238 image_sample_c_l v30, 1, 0, 0, 0, 0, 0, 0, 0, v[43:46], s[44:51], s[52:55] ; F0B00100 01AB1E2B v_mov_b32_e32 v24, s56 ; 7E300238 image_sample_c_l v22, 1, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[44:51], s[52:55] ; F0B00100 01AB1615 v_mov_b32_e32 v21, 0 ; 7E2A0280 image_sample_c_l v18, 1, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[44:51], s[52:55] ; F0B00100 01AB1212 v_mov_b32_e32 v19, 0x3d800000 ; 7E2602FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v20, v19, v38 ; 0A284D13 v_mac_f32_e32 v20, v19, v29 ; 2C283B13 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v20, v19, v34 ; 2C284513 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v20, v19, v35 ; 2C284713 v_mov_b32_e32 v19, 0x3e000000 ; 7E2602FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v1, v19, v1 ; 0A020313 v_mac_f32_e32 v1, v19, v36 ; 2C024913 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v1, v19, v30 ; 2C023D13 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v1, v19, v22 ; 2C022D13 v_add_f32_e32 v1, v20, v1 ; 02020314 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v1, v18, v1, 0x3e800000 ; 2E020312 3E800000 v_cmp_le_f32_e32 vcc, 0, v28 ; 7C863880 v_cndmask_b32_e64 v1, v1, 1.0, vcc ; D1000001 01A9E501 v_mad_f32 v1, -v27, v1, v1 ; D1C10001 2406031B v_mac_f32_e32 v1, v27, v25 ; 2C02331B v_mov_b32_e32 v25, v1 ; 7E320301 s_or_b64 exec, exec, s[58:59] ; 87FE3A7E v_subrev_f32_e32 v1, s20, v16 ; 06022014 v_subrev_f32_e32 v16, s19, v17 ; 06202213 v_subrev_f32_e32 v0, s18, v0 ; 06000012 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mac_f32_e32 v1, v16, v16 ; 2C022110 v_mac_f32_e32 v1, v0, v0 ; 2C020100 v_mad_f32 v0, v26, v1, s16 ; D1C10000 0042031A v_add_f32_e64 v16, 0, v0 clamp ; D1018010 00020080 v_sub_f32_e32 v0, 1.0, v16 ; 040020F2 v_mac_f32_e32 v16, v0, v25 ; 2C203300 s_or_b64 exec, exec, s[10:11] ; 87FE0A7E s_buffer_load_dword s18, s[12:15], 0x10 ; C0220486 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x14 ; C02204C6 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x18 ; C0220506 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x1c ; C0220406 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0xc0 ; C0220546 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0xc4 ; C0220006 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0xcc ; C0220446 000000CC s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x14c ; C0220586 0000014C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d0 ; C0220046 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d4 ; C0220086 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x1d8 ; C02200C6 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x1dc ; C0220306 000001DC v_mov_b32_e32 v0, s8 ; 7E000208 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v3, v16, v13 ; 2C061B10 v_mac_f32_e32 v4, v16, v14 ; 2C081D10 v_mac_f32_e32 v7, v16, v15 ; 2C0E1F10 v_cmp_ne_i32_e64 s[4:5], 0, s9 ; D0C50004 00001280 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842004 s_xor_b64 s[4:5], exec, s[4:5] ; 8884047E s_cbranch_execz BB0_7 ; BF880000 v_mul_f32_e32 v1, 0x3e59999a, v3 ; 0A0206FF 3E59999A v_madmk_f32_e32 v1, v4, v1, 0x3f372474 ; 2E020304 3F372474 v_madmk_f32_e32 v1, v7, v1, 0x3d93a92a ; 2E020307 3D93A92A v_rcp_f32_e32 v1, v1 ; 7E024501 v_mul_f32_e32 v1, v12, v1 ; 0A02030C v_sub_f32_e32 v12, 1.0, v16 ; 041820F2 v_mad_f32 v13, -v16, v1, v1 ; D1C1000D 24060310 v_mad_f32 v1, -v12, v1, 1.0 ; D1C10001 23CA030C v_mad_f32 v12, -v13, v7, v7 ; D1C1000C 241E0F0D v_mad_f32 v7, -v13, v4, v4 ; D1C10007 2412090D v_mad_f32 v13, -v13, v3, v3 ; D1C1000D 240E070D v_mad_f32 v1, 0.5, v1, 0.5 ; D1C10001 03C202F0 v_mad_f32 v3, -v1, v12, v12 ; D1C10003 24321901 v_mac_f32_e32 v3, v1, v13 ; 2C061B01 v_mad_f32 v4, -v1, v7, v7 ; D1C10004 241E0F01 v_mac_f32_e32 v4, v1, v7 ; 2C080F01 v_mad_f32 v7, -v1, v13, v13 ; D1C10007 24361B01 v_mac_f32_e32 v7, v1, v12 ; 2C0E1901 s_or_b64 exec, exec, s[4:5] ; 87FE047E v_mad_f32 v1, v11, s22, -s22 ; D1C10001 80582D0B v_add_f32_e32 v11, s21, v11 ; 02161615 v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mad_f32 v12, s18, v11, -v11 ; D1C1000C 842E1612 v_mad_f32 v13, s19, v11, -v11 ; D1C1000D 842E1613 v_mad_f32 v11, s20, v11, -v11 ; D1C1000B 842E1614 v_mac_f32_e32 v3, v3, v12 ; 2C061903 v_mac_f32_e32 v4, v4, v13 ; 2C081B04 v_mac_f32_e32 v7, v7, v11 ; 2C0E1707 v_mad_f32 v1, v1, s16, s16 ; D1C10001 00402101 v_mad_f32 v6, v1, v6, -v1 ; D1C10006 84060D01 v_mac_f32_e32 v1, s17, v6 ; 2C020C11 v_mul_f32_e32 v3, v3, v8 ; 0A061103 v_mul_f32_e32 v4, v4, v9 ; 0A081304 v_mul_f32_e32 v6, v7, v10 ; 0A0C1507 v_mul_f32_e32 v7, s8, v3 ; 0A0E0608 v_mul_f32_e32 v8, s8, v4 ; 0A100808 v_mul_f32_e32 v9, s8, v6 ; 0A120C08 v_mul_f32_e32 v5, s12, v5 ; 0A0A0A0C v_mov_b32_e32 v10, 0x80000000 ; 7E1402FF 80000000 v_cmp_le_f32_e64 vcc, |s0|, v10 ; D043016A 00021400 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_mul_f32_e32 v2, v2, v2 ; 0A040502 v_mad_f32 v3, -v3, v0, s1 ; D1C10003 20060103 v_mad_f32 v4, -v4, v0, s2 ; D1C10004 200A0104 v_mad_f32 v0, -v6, v0, s3 ; D1C10000 200E0106 v_mac_f32_e32 v7, v3, v2 ; 2C0E0503 v_mac_f32_e32 v8, v4, v2 ; 2C100504 v_mac_f32_e32 v9, v0, v2 ; 2C120500 v_cvt_pkrtz_f16_f32_e64 v0, v7, v8 ; D2960000 00021107 v_cvt_pkrtz_f16_f32_e64 v1, v9, v1 ; D2960001 00020309 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 52 Code Size: 3148 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], CLIPVERTEX DCL OUT[3], GENERIC[0] DCL OUT[4], GENERIC[1] DCL OUT[5], GENERIC[2] DCL CONST[0..51] DCL TEMP[0..6], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, CONST[0].yyyy 2: MAD TEMP[2], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 3: DP4 TEMP[1].x, TEMP[2], CONST[48] 4: DP4 TEMP[3].x, TEMP[2], CONST[49] 5: MOV TEMP[1].y, TEMP[3].xxxx 6: DP4 TEMP[2].x, TEMP[2], CONST[50] 7: MOV TEMP[1].z, TEMP[2].xxxx 8: DP4 TEMP[2].x, TEMP[1], CONST[8] 9: DP4 TEMP[3].x, TEMP[1], CONST[9] 10: MOV TEMP[2].y, TEMP[3].xxxx 11: DP4 TEMP[4].x, TEMP[1], CONST[11] 12: MOV TEMP[2].w, TEMP[4].xxxx 13: DP4 TEMP[5].x, TEMP[1], CONST[10] 14: MOV TEMP[1].w, TEMP[5].xxxx 15: MOV TEMP[2].z, TEMP[5].xxxx 16: MOV TEMP[1], TEMP[1] 17: MOV TEMP[0].xy, IN[1].xyxx 18: MOV TEMP[6], TEMP[2] 19: MAD TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz, -TEMP[4].xxxx 20: MOV TEMP[2].z, TEMP[5].xxxx 21: MOV TEMP[2].y, -TEMP[3].xxxx 22: MAD TEMP[2].xy, CONST[51].xyyy, TEMP[4].xxxx, TEMP[2].xyyy 23: MUL TEMP[3], CONST[0].yyxx, IN[2].xyxx 24: MAD TEMP[4], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 25: MOV OUT[3], TEMP[0] 26: MOV OUT[5], TEMP[3] 27: MOV OUT[4], TEMP[1] 28: MOV OUT[0], TEMP[2] 29: MOV OUT[2], TEMP[6] 30: MOV OUT[1], TEMP[4] 31: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = fmul float %52, %15 %68 = fadd float %67, %14 %69 = fmul float %53, %15 %70 = fadd float %69, %14 %71 = fmul float %54, %15 %72 = fadd float %71, %14 %73 = fmul float %52, %14 %74 = fadd float %73, %15 %75 = fmul float %68, %34 %76 = fmul float %70, %35 %77 = fadd float %75, %76 %78 = fmul float %72, %36 %79 = fadd float %77, %78 %80 = fmul float %74, %37 %81 = fadd float %79, %80 %82 = fmul float %68, %38 %83 = fmul float %70, %39 %84 = fadd float %82, %83 %85 = fmul float %72, %40 %86 = fadd float %84, %85 %87 = fmul float %74, %41 %88 = fadd float %86, %87 %89 = fmul float %68, %42 %90 = fmul float %70, %43 %91 = fadd float %89, %90 %92 = fmul float %72, %44 %93 = fadd float %91, %92 %94 = fmul float %74, %45 %95 = fadd float %93, %94 %96 = fmul float %81, %17 %97 = fmul float %88, %18 %98 = fadd float %96, %97 %99 = fmul float %95, %19 %100 = fadd float %98, %99 %101 = fmul float %15, %20 %102 = fadd float %100, %101 %103 = fmul float %81, %21 %104 = fmul float %88, %22 %105 = fadd float %103, %104 %106 = fmul float %95, %23 %107 = fadd float %105, %106 %108 = fmul float %15, %24 %109 = fadd float %107, %108 %110 = fmul float %81, %29 %111 = fmul float %88, %30 %112 = fadd float %110, %111 %113 = fmul float %95, %31 %114 = fadd float %112, %113 %115 = fmul float %15, %32 %116 = fadd float %114, %115 %117 = fmul float %81, %25 %118 = fmul float %88, %26 %119 = fadd float %117, %118 %120 = fmul float %95, %27 %121 = fadd float %119, %120 %122 = fmul float %15, %28 %123 = fadd float %121, %122 %124 = fmul float %123, %16 %125 = fsub float %124, %116 %126 = fmul float %46, %116 %127 = fadd float %126, %102 %128 = fmul float %47, %116 %129 = fsub float %128, %109 %130 = fmul float %15, %65 %131 = fmul float %15, %66 %132 = fmul float %14, %65 %133 = fmul float %14, %65 %134 = fmul float %33, %14 %135 = fadd float %134, %15 %136 = fmul float %33, %14 %137 = fadd float %136, %15 %138 = fmul float %33, %14 %139 = fadd float %138, %15 %140 = fmul float %33, %15 %141 = fadd float %140, %14 %142 = and i32 %7, 1 %143 = icmp eq i32 %142, 0 br i1 %143, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %144 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00) %145 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00) %146 = call float @llvm.AMDIL.clamp.(float %139, float 0.000000e+00, float 1.000000e+00) %147 = call float @llvm.AMDIL.clamp.(float %141, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.030 = phi float [ %147, %if-true-block ], [ %141, %main_body ] %.029 = phi float [ %146, %if-true-block ], [ %139, %main_body ] %.028 = phi float [ %145, %if-true-block ], [ %137, %main_body ] %.0 = phi float [ %144, %if-true-block ], [ %135, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.028, float %.029, float %.030) %148 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %149 = load <16 x i8>, <16 x i8> addrspace(2)* %148, align 16, !tbaa !0 %150 = call float @llvm.SI.load.const(<16 x i8> %149, i32 0) %151 = fmul float %150, %102 %152 = call float @llvm.SI.load.const(<16 x i8> %149, i32 4) %153 = fmul float %152, %109 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %149, i32 8) %156 = fmul float %155, %123 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %149, i32 12) %159 = fmul float %158, %116 %160 = fadd float %157, %159 %161 = call float @llvm.SI.load.const(<16 x i8> %149, i32 16) %162 = fmul float %161, %102 %163 = call float @llvm.SI.load.const(<16 x i8> %149, i32 20) %164 = fmul float %163, %109 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %149, i32 24) %167 = fmul float %166, %123 %168 = fadd float %165, %167 %169 = call float @llvm.SI.load.const(<16 x i8> %149, i32 28) %170 = fmul float %169, %116 %171 = fadd float %168, %170 %172 = call float @llvm.SI.load.const(<16 x i8> %149, i32 32) %173 = fmul float %172, %102 %174 = call float @llvm.SI.load.const(<16 x i8> %149, i32 36) %175 = fmul float %174, %109 %176 = fadd float %173, %175 %177 = call float @llvm.SI.load.const(<16 x i8> %149, i32 40) %178 = fmul float %177, %123 %179 = fadd float %176, %178 %180 = call float @llvm.SI.load.const(<16 x i8> %149, i32 44) %181 = fmul float %180, %116 %182 = fadd float %179, %181 %183 = call float @llvm.SI.load.const(<16 x i8> %149, i32 48) %184 = fmul float %183, %102 %185 = call float @llvm.SI.load.const(<16 x i8> %149, i32 52) %186 = fmul float %185, %109 %187 = fadd float %184, %186 %188 = call float @llvm.SI.load.const(<16 x i8> %149, i32 56) %189 = fmul float %188, %123 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %149, i32 60) %192 = fmul float %191, %116 %193 = fadd float %190, %192 %194 = call float @llvm.SI.load.const(<16 x i8> %149, i32 64) %195 = fmul float %194, %102 %196 = call float @llvm.SI.load.const(<16 x i8> %149, i32 68) %197 = fmul float %196, %109 %198 = fadd float %195, %197 %199 = call float @llvm.SI.load.const(<16 x i8> %149, i32 72) %200 = fmul float %199, %123 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %149, i32 76) %203 = fmul float %202, %116 %204 = fadd float %201, %203 %205 = call float @llvm.SI.load.const(<16 x i8> %149, i32 80) %206 = fmul float %205, %102 %207 = call float @llvm.SI.load.const(<16 x i8> %149, i32 84) %208 = fmul float %207, %109 %209 = fadd float %206, %208 %210 = call float @llvm.SI.load.const(<16 x i8> %149, i32 88) %211 = fmul float %210, %123 %212 = fadd float %209, %211 %213 = call float @llvm.SI.load.const(<16 x i8> %149, i32 92) %214 = fmul float %213, %116 %215 = fadd float %212, %214 %216 = call float @llvm.SI.load.const(<16 x i8> %149, i32 96) %217 = fmul float %216, %102 %218 = call float @llvm.SI.load.const(<16 x i8> %149, i32 100) %219 = fmul float %218, %109 %220 = fadd float %217, %219 %221 = call float @llvm.SI.load.const(<16 x i8> %149, i32 104) %222 = fmul float %221, %123 %223 = fadd float %220, %222 %224 = call float @llvm.SI.load.const(<16 x i8> %149, i32 108) %225 = fmul float %224, %116 %226 = fadd float %223, %225 %227 = call float @llvm.SI.load.const(<16 x i8> %149, i32 112) %228 = fmul float %227, %102 %229 = call float @llvm.SI.load.const(<16 x i8> %149, i32 116) %230 = fmul float %229, %109 %231 = fadd float %228, %230 %232 = call float @llvm.SI.load.const(<16 x i8> %149, i32 120) %233 = fmul float %232, %123 %234 = fadd float %231, %233 %235 = call float @llvm.SI.load.const(<16 x i8> %149, i32 124) %236 = fmul float %235, %116 %237 = fadd float %234, %236 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %81, float %88, float %95, float %123) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %130, float %131, float %132, float %133) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %127, float %129, float %125, float %116) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %160, float %171, float %182, float %193) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %204, float %215, float %226, float %237) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 v_add_i32_e32 v4, vcc, s10, v0 ; 3208000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[9:12], v4, s[4:7], 0 idxen ; E00C2000 80010904 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v4, s[16:19], 0 idxen ; E00C2000 80040004 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[2:5], v4, s[20:23], 0 idxen ; E00C2000 80050204 s_load_dwordx4 s[36:39], s[2:3], 0x0 ; C00A0901 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[36:39], 0x0 ; C0220012 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[36:39], 0x4 ; C02208D2 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[36:39], 0x8 ; C0220052 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[36:39], 0x80 ; C0220552 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[36:39], 0x84 ; C0220592 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[36:39], 0x88 ; C0220512 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[36:39], 0x8c ; C0220492 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[36:39], 0x90 ; C0220452 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[36:39], 0x94 ; C02204D2 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[36:39], 0x98 ; C0220392 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[36:39], 0x9c ; C0220352 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[36:39], 0xa0 ; C0220112 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[36:39], 0xa4 ; C02201D2 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[36:39], 0xa8 ; C0220152 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[36:39], 0xac ; C0220192 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s8, s[36:39], 0xb0 ; C0220212 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[36:39], 0xb4 ; C02203D2 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[36:39], 0xb8 ; C0220252 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[36:39], 0xbc ; C0220292 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s40, s[36:39], 0x2fc ; C0220A12 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s33, s[36:39], 0x300 ; C0220852 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[36:39], 0x304 ; C0220892 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[36:39], 0x308 ; C0220812 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[36:39], 0x30c ; C0220792 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[36:39], 0x310 ; C0220752 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[36:39], 0x314 ; C02207D2 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[36:39], 0x318 ; C0220712 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[36:39], 0x31c ; C0220692 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s25, s[36:39], 0x320 ; C0220652 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[36:39], 0x324 ; C02206D2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[36:39], 0x328 ; C0220612 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[36:39], 0x32c ; C02205D2 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[36:39], 0x330 ; C0220412 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[36:39], 0x334 ; C02202D2 00000334 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mov_b32_e32 v4, s35 ; 7E080223 v_mov_b32_e32 v5, s0 ; 7E0A0200 v_mad_f32 v6, s40, v5, v4 ; D1C10006 04120A28 v_mad_f32 v5, s40, v4, v5 ; D1C10005 04160828 s_and_b32 s12, 1, s12 ; 860C0C81 v_cmp_eq_i32_e64 s[36:37], 1, s12 ; D0C20024 00001881 v_mov_b32_e32 v8, v6 ; 7E100306 v_mov_b32_e32 v7, v6 ; 7E0E0306 s_and_saveexec_b64 s[36:37], s[36:37] ; BEA42024 s_xor_b64 s[36:37], exec, s[36:37] ; 88A4247E v_add_f32_e64 v7, 0, v6 clamp ; D1018007 00020C80 v_add_f32_e64 v8, 0, v6 clamp ; D1018008 00020C80 v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 s_or_b64 exec, exec, s[36:37] ; 87FE247E v_mad_f32 v12, v4, v9, s0 ; D1C1000C 00021304 v_mad_f32 v10, v10, v4, s0 ; D1C1000A 0002090A v_mad_f32 v11, v11, v4, s0 ; D1C1000B 0002090B v_mad_f32 v9, s0, v9, v4 ; D1C10009 04121200 v_mul_f32_e32 v13, s34, v10 ; 0A1A1422 v_mac_f32_e32 v13, s33, v12 ; 2C1A1821 v_mac_f32_e32 v13, s32, v11 ; 2C1A1620 v_mac_f32_e32 v13, s30, v9 ; 2C1A121E v_mul_f32_e32 v14, s31, v10 ; 0A1C141F v_mac_f32_e32 v14, s29, v12 ; 2C1C181D v_mac_f32_e32 v14, s28, v11 ; 2C1C161C v_mac_f32_e32 v14, s26, v9 ; 2C1C121A v_mul_f32_e32 v10, s27, v10 ; 0A14141B v_mac_f32_e32 v10, s25, v12 ; 2C141819 v_mac_f32_e32 v10, s24, v11 ; 2C141618 v_mac_f32_e32 v10, s23, v9 ; 2C141217 v_mul_f32_e32 v9, s22, v14 ; 0A121C16 v_mac_f32_e32 v9, s21, v13 ; 2C121A15 v_mac_f32_e32 v9, s20, v10 ; 2C121414 v_mac_f32_e32 v9, s18, v4 ; 2C120812 v_mul_f32_e32 v11, s19, v14 ; 0A161C13 v_mac_f32_e32 v11, s17, v13 ; 2C161A11 v_mac_f32_e32 v11, s14, v10 ; 2C16140E v_mac_f32_e32 v11, s13, v4 ; 2C16080D v_mul_f32_e32 v12, s15, v14 ; 0A181C0F s_load_dwordx4 s[12:15], s[2:3], 0x100 ; C00A0301 00000100 v_mac_f32_e32 v12, s8, v13 ; 2C181A08 v_mac_f32_e32 v12, s9, v10 ; 2C181409 v_mac_f32_e32 v12, s10, v4 ; 2C18080A v_mul_f32_e32 v15, s7, v14 ; 0A1E1C07 v_mac_f32_e32 v15, s4, v13 ; 2C1E1A04 v_mac_f32_e32 v15, s5, v10 ; 2C1E1405 v_mac_f32_e32 v15, s6, v4 ; 2C1E0806 v_mad_f32 v16, v15, s1, -v12 ; D1C10010 8430030F v_mad_f32 v17, s16, v12, v9 ; D1C10011 04261810 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[12:15], 0x0 ; C0220046 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x4 ; C0220086 00000004 v_mad_f32 v18, s11, v12, -v11 ; D1C10012 842E180B v_mul_f32_e32 v19, v2, v4 ; 0A260902 v_mul_f32_e32 v3, v3, v4 ; 0A060903 v_mul_f32_e32 v2, s0, v2 ; 0A040400 exp 15, 32, 0, 0, 0, v6, v7, v8, v5 ; C400020F 05080706 s_buffer_load_dword s0, s[12:15], 0x8 ; C0220006 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xc ; C02200C6 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0x14 ; C0220106 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x10 ; C0220146 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v4, s2, v11 ; 0A081602 s_buffer_load_dword s2, s[12:15], 0x18 ; C0220086 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0x1c ; C0220186 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x20 ; C02201C6 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x24 ; C0220206 00000024 v_mac_f32_e32 v4, s1, v9 ; 2C081201 v_mac_f32_e32 v4, s0, v15 ; 2C081E00 v_mac_f32_e32 v4, s3, v12 ; 2C081803 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s4, v11 ; 0A0A1604 s_buffer_load_dword s0, s[12:15], 0x28 ; C0220006 00000028 v_mac_f32_e32 v5, s5, v9 ; 2C0A1205 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v5, s2, v15 ; 2C0A1E02 v_mac_f32_e32 v5, s6, v12 ; 2C0A1806 s_buffer_load_dword s1, s[12:15], 0x2c ; C0220046 0000002C v_mul_f32_e32 v6, s8, v11 ; 0A0C1608 s_buffer_load_dword s2, s[12:15], 0x30 ; C0220086 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x34 ; C02200C6 00000034 v_mac_f32_e32 v6, s7, v9 ; 2C0C1207 s_buffer_load_dword s4, s[12:15], 0x38 ; C0220106 00000038 v_mac_f32_e32 v6, s0, v15 ; 2C0C1E00 s_buffer_load_dword s0, s[12:15], 0x3c ; C0220006 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x40 ; C0220146 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0x44 ; C0220186 00000044 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v6, s1, v12 ; 2C0C1801 s_buffer_load_dword s1, s[12:15], 0x48 ; C0220046 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x4c ; C02201C6 0000004C v_mul_f32_e32 v7, s3, v11 ; 0A0E1603 v_mac_f32_e32 v7, s2, v9 ; 2C0E1202 s_buffer_load_dword s2, s[12:15], 0x50 ; C0220086 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x54 ; C02200C6 00000054 v_mac_f32_e32 v7, s4, v15 ; 2C0E1E04 v_mac_f32_e32 v7, s0, v12 ; 2C0E1800 v_mul_f32_e32 v8, s6, v11 ; 0A101606 v_mac_f32_e32 v8, s5, v9 ; 2C101205 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v8, s1, v15 ; 2C101E01 v_mac_f32_e32 v8, s7, v12 ; 2C101807 s_buffer_load_dword s0, s[12:15], 0x58 ; C0220006 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x5c ; C0220046 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0x60 ; C0220106 00000060 v_mul_f32_e32 v20, s3, v11 ; 0A281603 s_buffer_load_dword s3, s[12:15], 0x64 ; C02200C6 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x68 ; C0220146 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0x6c ; C0220186 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x70 ; C02201C6 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x74 ; C0220206 00000074 v_mac_f32_e32 v20, s2, v9 ; 2C281202 s_buffer_load_dword s2, s[12:15], 0x78 ; C0220086 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x7c ; C0220246 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v20, s0, v15 ; 2C281E00 v_mac_f32_e32 v20, s1, v12 ; 2C281801 v_mul_f32_e32 v21, s3, v11 ; 0A2A1603 v_mac_f32_e32 v21, s4, v9 ; 2C2A1204 v_mac_f32_e32 v21, s5, v15 ; 2C2A1E05 v_mac_f32_e32 v21, s6, v12 ; 2C2A1806 v_mul_f32_e32 v11, s8, v11 ; 0A161608 v_mac_f32_e32 v11, s7, v9 ; 2C161207 v_mac_f32_e32 v11, s2, v15 ; 2C161E02 v_mac_f32_e32 v11, s9, v12 ; 2C161809 v_mov_b32_e32 v9, 0 ; 7E120280 exp 15, 33, 0, 0, 0, v0, v1, v9, v9 ; C400021F 09090100 exp 15, 34, 0, 0, 0, v13, v14, v10, v15 ; C400022F 0F0A0E0D exp 15, 35, 0, 0, 0, v19, v3, v2, v2 ; C400023F 02020313 exp 15, 12, 0, 0, 0, v17, v18, v16, v12 ; C40000CF 0C101211 exp 15, 13, 0, 0, 0, v4, v5, v6, v7 ; C40000DF 07060504 exp 15, 14, 0, 1, 0, v8, v20, v21, v11 ; C40008EF 0B151408 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 24 Code Size: 1320 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL IN[2], GENERIC[1], PERSPECTIVE DCL IN[3], GENERIC[2], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..17], LOCAL IMM[0] FLT32 { 0.0000, 0.2125, 0.7154, 0.0721} IMM[1] FLT32 { 1.0000, 0.0000, 2.0000, -0.5000} IMM[2] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[3] FLT32 { 0.0005, 0.0000, -0.0005, 0.1250} IMM[4] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[5] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[3].xyyy 3: TEX TEMP[2], TEMP[1], SAMP[1], 2D 4: MOV TEMP[3], TEMP[2] 5: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz 6: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww 7: MOV TEMP[0].w, TEMP[0].xxxx 8: MUL TEMP[4].xyz, TEMP[2].xyzz, CONST[12].xyzz 9: FSLT TEMP[5].x, -TEMP[2].wwww, IMM[0].xxxx 10: AND TEMP[5].x, CONST[90].xxxx, TEMP[5].xxxx 11: UIF TEMP[5].xxxx :0 12: DP3 TEMP[5].x, TEMP[2].xyzz, IMM[0].yzww 13: RCP TEMP[5].x, TEMP[5].xxxx 14: MUL TEMP[2].x, TEMP[5].xxxx, TEMP[2].wwww 15: MAD TEMP[3], IN[2].xyzx, IMM[1].xxxy, IMM[1].yyyx 16: DP4 TEMP[5].x, TEMP[3], CONST[69] 17: DP4 TEMP[6].x, TEMP[3], CONST[70] 18: MOV TEMP[5].y, TEMP[6].xxxx 19: MOV_SAT TEMP[7].xy, TEMP[5].xyyy 20: ADD TEMP[7].xy, -TEMP[5].xyyy, TEMP[7].xyyy 21: DP2 TEMP[8].x, TEMP[7].xyyy, IMM[1].xxxx 22: DP4 TEMP[7].x, TEMP[3], CONST[73] 23: DP4 TEMP[9].x, TEMP[3], CONST[74] 24: MOV TEMP[7].y, TEMP[9].xxxx 25: MOV_SAT TEMP[10].xy, TEMP[7].xyyy 26: ADD TEMP[10].xy, -TEMP[7].xyyy, TEMP[10].xyyy 27: DP2 TEMP[11].x, TEMP[10].xyyy, IMM[1].xxxx 28: MOV TEMP[5].w, TEMP[11].xxxx 29: DP4 TEMP[10].x, TEMP[3], CONST[77] 30: DP4 TEMP[12].x, TEMP[3], CONST[78] 31: MOV TEMP[7].z, IMM[1].xxxx 32: MOV TEMP[13].w, TEMP[7] 33: ABS TEMP[14].x, TEMP[11].xxxx 34: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 35: UIF TEMP[14].xxxx :0 36: MOV TEMP[14].x, TEMP[7].xxxx 37: ELSE :0 38: MOV TEMP[14].x, TEMP[10].xxxx 39: ENDIF 40: MOV TEMP[13].x, TEMP[14].xxxx 41: ABS TEMP[14].x, TEMP[11].xxxx 42: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 43: UIF TEMP[14].xxxx :0 44: MOV TEMP[9].x, TEMP[9].xxxx 45: ELSE :0 46: MOV TEMP[9].x, TEMP[12].xxxx 47: ENDIF 48: MOV TEMP[13].y, TEMP[9].xxxx 49: ABS TEMP[9].x, TEMP[11].xxxx 50: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 51: UIF TEMP[9].xxxx :0 52: MOV TEMP[9].x, IMM[1].xxxx 53: ELSE :0 54: MOV TEMP[9].x, IMM[1].zzzz 55: ENDIF 56: MOV TEMP[13].z, TEMP[9].xxxx 57: MOV TEMP[7].xyz, TEMP[13] 58: MOV TEMP[5].z, IMM[0].xxxx 59: MOV TEMP[13].w, TEMP[5] 60: ABS TEMP[9].x, TEMP[8].xxxx 61: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 62: UIF TEMP[9].xxxx :0 63: MOV TEMP[9].x, TEMP[5].xxxx 64: ELSE :0 65: MOV TEMP[9].x, TEMP[7].xxxx 66: ENDIF 67: MOV TEMP[13].x, TEMP[9].xxxx 68: ABS TEMP[9].x, TEMP[8].xxxx 69: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].xxxx 70: UIF TEMP[9].xxxx :0 71: MOV TEMP[6].x, TEMP[6].xxxx 72: ELSE :0 73: MOV TEMP[6].x, TEMP[7].yyyy 74: ENDIF 75: MOV TEMP[13].y, TEMP[6].xxxx 76: ABS TEMP[6].x, TEMP[8].xxxx 77: FSGE TEMP[6].x, -TEMP[6].xxxx, IMM[0].xxxx 78: UIF TEMP[6].xxxx :0 79: MOV TEMP[6].x, IMM[0].xxxx 80: ELSE :0 81: MOV TEMP[6].x, TEMP[7].zzzz 82: ENDIF 83: MOV TEMP[13].z, TEMP[6].xxxx 84: MOV TEMP[5].z, TEMP[13].wwzw 85: DP4 TEMP[8].x, TEMP[3], CONST[71] 86: MOV TEMP[7].z, TEMP[8].xxxx 87: ADD TEMP[10].xy, TEMP[13].xyyy, IMM[1].wwww 88: ABS TEMP[9].xy, TEMP[10].xyyy 89: ADD TEMP[10].xy, TEMP[9].xyyy, -CONST[67].zzzz 90: MUL TEMP[10].xy, TEMP[10].xyyy, CONST[67].wwww 91: MOV_SAT TEMP[9].xy, TEMP[10].xyyy 92: ADD TEMP[10].xy, -TEMP[9].xyyy, IMM[1].xxxx 93: MUL TEMP[9].x, TEMP[10].yyyy, TEMP[10].xxxx 94: MOV_SAT TEMP[11].xy, TEMP[13].xyyy 95: ADD TEMP[10].xyz, TEMP[6].xxxx, IMM[2].xyzz 96: MOV TEMP[6].x, IMM[0].xxxx 97: ABS TEMP[14].x, TEMP[10].xxxx 98: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 99: UIF TEMP[14].xxxx :0 100: MOV TEMP[14].x, CONST[85].zzzz 101: ELSE :0 102: MOV TEMP[14].x, IMM[0].xxxx 103: ENDIF 104: ABS TEMP[15].x, TEMP[10].xxxx 105: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 106: UIF TEMP[15].xxxx :0 107: MOV TEMP[15].x, CONST[85].wwww 108: ELSE :0 109: MOV TEMP[15].x, IMM[0].xxxx 110: ENDIF 111: MOV TEMP[13].y, TEMP[15].xxxx 112: ABS TEMP[15].x, TEMP[10].xxxx 113: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 114: UIF TEMP[15].xxxx :0 115: MOV TEMP[15].x, CONST[85].xxxx 116: ELSE :0 117: MOV TEMP[15].x, IMM[0].xxxx 118: ENDIF 119: MOV TEMP[13].z, TEMP[15].xxxx 120: ABS TEMP[15].x, TEMP[10].xxxx 121: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 122: UIF TEMP[15].xxxx :0 123: MOV TEMP[15].x, CONST[85].yyyy 124: ELSE :0 125: MOV TEMP[15].x, IMM[0].xxxx 126: ENDIF 127: MOV TEMP[13].w, TEMP[15].xxxx 128: ABS TEMP[15].x, TEMP[10].yyyy 129: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 130: UIF TEMP[15].xxxx :0 131: MOV TEMP[15].x, CONST[86].zzzz 132: ELSE :0 133: MOV TEMP[15].x, TEMP[14].xxxx 134: ENDIF 135: MOV TEMP[13].x, TEMP[15].xxxx 136: ABS TEMP[14].x, TEMP[10].yyyy 137: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 138: UIF TEMP[14].xxxx :0 139: MOV TEMP[14].x, CONST[86].wwww 140: ELSE :0 141: MOV TEMP[14].x, TEMP[13].yyyy 142: ENDIF 143: MOV TEMP[13].y, TEMP[14].xxxx 144: ABS TEMP[14].x, TEMP[10].yyyy 145: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 146: UIF TEMP[14].xxxx :0 147: MOV TEMP[14].x, CONST[86].xxxx 148: ELSE :0 149: MOV TEMP[14].x, TEMP[13].zzzz 150: ENDIF 151: MOV TEMP[13].z, TEMP[14].xxxx 152: ABS TEMP[14].x, TEMP[10].yyyy 153: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 154: UIF TEMP[14].xxxx :0 155: MOV TEMP[14].x, CONST[86].yyyy 156: ELSE :0 157: MOV TEMP[14].x, TEMP[13].wwww 158: ENDIF 159: MOV TEMP[13].w, TEMP[14].xxxx 160: MOV TEMP[12], TEMP[13] 161: ABS TEMP[14].x, TEMP[10].zzzz 162: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 163: UIF TEMP[14].xxxx :0 164: MOV TEMP[14].x, CONST[87].zzzz 165: ELSE :0 166: MOV TEMP[14].x, TEMP[12].xxxx 167: ENDIF 168: MOV TEMP[13].x, TEMP[14].xxxx 169: ABS TEMP[14].x, TEMP[10].zzzz 170: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 171: UIF TEMP[14].xxxx :0 172: MOV TEMP[14].x, CONST[87].wwww 173: ELSE :0 174: MOV TEMP[14].x, TEMP[12].yyyy 175: ENDIF 176: MOV TEMP[13].y, TEMP[14].xxxx 177: ABS TEMP[14].x, TEMP[10].zzzz 178: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 179: UIF TEMP[14].xxxx :0 180: MOV TEMP[14].x, CONST[87].xxxx 181: ELSE :0 182: MOV TEMP[14].x, TEMP[12].zzzz 183: ENDIF 184: MOV TEMP[13].z, TEMP[14].xxxx 185: ABS TEMP[14].x, TEMP[10].zzzz 186: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].xxxx 187: UIF TEMP[14].xxxx :0 188: MOV TEMP[14].x, CONST[87].yyyy 189: ELSE :0 190: MOV TEMP[14].x, TEMP[12].wwww 191: ENDIF 192: MOV TEMP[13].w, TEMP[14].xxxx 193: MAD TEMP[7].xy, TEMP[11].xyyy, TEMP[13].xyyy, TEMP[13].zwww 194: MOV TEMP[7].w, IMM[0].xxxx 195: ADD TEMP[10], TEMP[7], IMM[3].xxyy 196: TXL TEMP[11].x, TEMP[10], SAMP[2], SHADOW2D 197: MOV TEMP[10].x, TEMP[11].xxxx 198: ADD TEMP[12], TEMP[7], IMM[3].zxyy 199: ADD TEMP[11], TEMP[7], IMM[3].xzyy 200: ADD TEMP[14], TEMP[7], IMM[3].zzyy 201: TXL TEMP[15].x, TEMP[12], SAMP[2], SHADOW2D 202: MOV TEMP[10].y, TEMP[15].xxxx 203: TXL TEMP[15].x, TEMP[11], SAMP[2], SHADOW2D 204: MOV TEMP[10].z, TEMP[15].xxxx 205: TXL TEMP[15].x, TEMP[14], SAMP[2], SHADOW2D 206: MOV TEMP[10].w, TEMP[15].xxxx 207: DP4 TEMP[15].x, TEMP[10], IMM[2].wwww 208: ADD TEMP[10], TEMP[7], IMM[3].xyyy 209: TXL TEMP[16].x, TEMP[10], SAMP[2], SHADOW2D 210: MOV TEMP[10].x, TEMP[16].xxxx 211: ADD TEMP[12], TEMP[7], IMM[3].zyyy 212: TXL TEMP[16], TEMP[12], SAMP[2], SHADOW2D 213: MOV TEMP[12], TEMP[16] 214: ADD TEMP[11], TEMP[7], IMM[3].yzyy 215: TXL TEMP[17], TEMP[11], SAMP[2], SHADOW2D 216: MOV TEMP[11], TEMP[17] 217: ADD TEMP[14], TEMP[7], IMM[3].yxyy 218: TXL TEMP[14].x, TEMP[14], SAMP[2], SHADOW2D 219: MOV TEMP[10].y, TEMP[16].xxxx 220: MOV TEMP[10].z, TEMP[17].xxxx 221: MOV TEMP[10].w, TEMP[14].xxxx 222: DP4 TEMP[14].x, TEMP[10], IMM[3].wwww 223: MOV TEMP[16].xy, TEMP[7].xyyy 224: MOV TEMP[16].z, TEMP[8].xxxx 225: MOV TEMP[16].w, IMM[0].xxxx 226: TXL TEMP[16], TEMP[16], SAMP[2], SHADOW2D 227: MOV TEMP[10], TEMP[16] 228: ADD TEMP[5].x, TEMP[14].xxxx, TEMP[15].xxxx 229: MAD TEMP[5].x, TEMP[16].xxxx, IMM[4].xxxx, TEMP[5].xxxx 230: FSLT TEMP[14].x, TEMP[9].xxxx, IMM[1].xxxx 231: UIF TEMP[14].xxxx :0 232: ADD TEMP[14].xyz, TEMP[5].zzzz, IMM[4].yzww 233: ABS TEMP[15].x, TEMP[14].xxxx 234: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 235: UIF TEMP[15].xxxx :0 236: MOV TEMP[15].x, CONST[73].xxxx 237: ELSE :0 238: MOV TEMP[15].x, IMM[0].xxxx 239: ENDIF 240: MOV TEMP[13].x, TEMP[15].xxxx 241: ABS TEMP[15].x, TEMP[14].xxxx 242: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 243: UIF TEMP[15].xxxx :0 244: MOV TEMP[15].x, CONST[73].yyyy 245: ELSE :0 246: MOV TEMP[15].x, IMM[0].xxxx 247: ENDIF 248: MOV TEMP[13].y, TEMP[15].xxxx 249: ABS TEMP[15].x, TEMP[14].xxxx 250: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 251: UIF TEMP[15].xxxx :0 252: MOV TEMP[15].x, CONST[73].zzzz 253: ELSE :0 254: MOV TEMP[15].x, IMM[0].xxxx 255: ENDIF 256: MOV TEMP[13].z, TEMP[15].xxxx 257: ABS TEMP[15].x, TEMP[14].xxxx 258: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 259: UIF TEMP[15].xxxx :0 260: MOV TEMP[15].x, CONST[73].wwww 261: ELSE :0 262: MOV TEMP[15].x, IMM[0].xxxx 263: ENDIF 264: MOV TEMP[13].w, TEMP[15].xxxx 265: MOV TEMP[10], TEMP[13] 266: ABS TEMP[15].x, TEMP[14].xxxx 267: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 268: UIF TEMP[15].xxxx :0 269: MOV TEMP[15].x, CONST[74].xxxx 270: ELSE :0 271: MOV TEMP[15].x, IMM[0].xxxx 272: ENDIF 273: MOV TEMP[13].x, TEMP[15].xxxx 274: ABS TEMP[15].x, TEMP[14].xxxx 275: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 276: UIF TEMP[15].xxxx :0 277: MOV TEMP[15].x, CONST[74].yyyy 278: ELSE :0 279: MOV TEMP[15].x, IMM[0].xxxx 280: ENDIF 281: MOV TEMP[13].y, TEMP[15].xxxx 282: ABS TEMP[15].x, TEMP[14].xxxx 283: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 284: UIF TEMP[15].xxxx :0 285: MOV TEMP[15].x, CONST[74].zzzz 286: ELSE :0 287: MOV TEMP[15].x, IMM[0].xxxx 288: ENDIF 289: MOV TEMP[13].z, TEMP[15].xxxx 290: ABS TEMP[15].x, TEMP[14].xxxx 291: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 292: UIF TEMP[15].xxxx :0 293: MOV TEMP[15].x, CONST[74].wwww 294: ELSE :0 295: MOV TEMP[15].x, IMM[0].xxxx 296: ENDIF 297: MOV TEMP[13].w, TEMP[15].xxxx 298: MOV TEMP[12], TEMP[13] 299: ABS TEMP[15].x, TEMP[14].yyyy 300: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 301: UIF TEMP[15].xxxx :0 302: MOV TEMP[15].x, CONST[77].xxxx 303: ELSE :0 304: MOV TEMP[15].x, TEMP[10].xxxx 305: ENDIF 306: MOV TEMP[13].x, TEMP[15].xxxx 307: ABS TEMP[15].x, TEMP[14].yyyy 308: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 309: UIF TEMP[15].xxxx :0 310: MOV TEMP[15].x, CONST[77].yyyy 311: ELSE :0 312: MOV TEMP[15].x, TEMP[10].yyyy 313: ENDIF 314: MOV TEMP[13].y, TEMP[15].xxxx 315: ABS TEMP[15].x, TEMP[14].yyyy 316: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 317: UIF TEMP[15].xxxx :0 318: MOV TEMP[15].x, CONST[77].zzzz 319: ELSE :0 320: MOV TEMP[15].x, TEMP[10].zzzz 321: ENDIF 322: MOV TEMP[13].z, TEMP[15].xxxx 323: ABS TEMP[15].x, TEMP[14].yyyy 324: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 325: UIF TEMP[15].xxxx :0 326: MOV TEMP[15].x, CONST[77].wwww 327: ELSE :0 328: MOV TEMP[15].x, TEMP[10].wwww 329: ENDIF 330: MOV TEMP[13].w, TEMP[15].xxxx 331: MOV TEMP[10], TEMP[13] 332: ABS TEMP[15].x, TEMP[14].yyyy 333: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 334: UIF TEMP[15].xxxx :0 335: MOV TEMP[15].x, CONST[78].xxxx 336: ELSE :0 337: MOV TEMP[15].x, TEMP[12].xxxx 338: ENDIF 339: MOV TEMP[13].x, TEMP[15].xxxx 340: ABS TEMP[15].x, TEMP[14].yyyy 341: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 342: UIF TEMP[15].xxxx :0 343: MOV TEMP[15].x, CONST[78].yyyy 344: ELSE :0 345: MOV TEMP[15].x, TEMP[12].yyyy 346: ENDIF 347: MOV TEMP[13].y, TEMP[15].xxxx 348: ABS TEMP[15].x, TEMP[14].yyyy 349: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 350: UIF TEMP[15].xxxx :0 351: MOV TEMP[15].x, CONST[78].zzzz 352: ELSE :0 353: MOV TEMP[15].x, TEMP[12].zzzz 354: ENDIF 355: MOV TEMP[13].z, TEMP[15].xxxx 356: ABS TEMP[15].x, TEMP[14].yyyy 357: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 358: UIF TEMP[15].xxxx :0 359: MOV TEMP[15].x, CONST[78].wwww 360: ELSE :0 361: MOV TEMP[15].x, TEMP[12].wwww 362: ENDIF 363: MOV TEMP[13].w, TEMP[15].xxxx 364: MOV TEMP[12], TEMP[13] 365: ABS TEMP[15].x, TEMP[14].zzzz 366: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 367: UIF TEMP[15].xxxx :0 368: MOV TEMP[15].x, CONST[81].xxxx 369: ELSE :0 370: MOV TEMP[15].x, TEMP[10].xxxx 371: ENDIF 372: MOV TEMP[13].x, TEMP[15].xxxx 373: ABS TEMP[15].x, TEMP[14].zzzz 374: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 375: UIF TEMP[15].xxxx :0 376: MOV TEMP[15].x, CONST[81].yyyy 377: ELSE :0 378: MOV TEMP[15].x, TEMP[10].yyyy 379: ENDIF 380: MOV TEMP[13].y, TEMP[15].xxxx 381: ABS TEMP[15].x, TEMP[14].zzzz 382: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 383: UIF TEMP[15].xxxx :0 384: MOV TEMP[15].x, CONST[81].zzzz 385: ELSE :0 386: MOV TEMP[15].x, TEMP[10].zzzz 387: ENDIF 388: MOV TEMP[13].z, TEMP[15].xxxx 389: ABS TEMP[15].x, TEMP[14].zzzz 390: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 391: UIF TEMP[15].xxxx :0 392: MOV TEMP[15].x, CONST[81].wwww 393: ELSE :0 394: MOV TEMP[15].x, TEMP[10].wwww 395: ENDIF 396: MOV TEMP[13].w, TEMP[15].xxxx 397: MOV TEMP[10], TEMP[13] 398: ABS TEMP[15].x, TEMP[14].zzzz 399: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 400: UIF TEMP[15].xxxx :0 401: MOV TEMP[15].x, CONST[82].xxxx 402: ELSE :0 403: MOV TEMP[15].x, TEMP[12].xxxx 404: ENDIF 405: MOV TEMP[13].x, TEMP[15].xxxx 406: ABS TEMP[15].x, TEMP[14].zzzz 407: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 408: UIF TEMP[15].xxxx :0 409: MOV TEMP[15].x, CONST[82].yyyy 410: ELSE :0 411: MOV TEMP[15].x, TEMP[12].yyyy 412: ENDIF 413: MOV TEMP[13].y, TEMP[15].xxxx 414: ABS TEMP[15].x, TEMP[14].zzzz 415: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 416: UIF TEMP[15].xxxx :0 417: MOV TEMP[15].x, CONST[82].zzzz 418: ELSE :0 419: MOV TEMP[15].x, TEMP[12].zzzz 420: ENDIF 421: MOV TEMP[13].z, TEMP[15].xxxx 422: ABS TEMP[15].x, TEMP[14].zzzz 423: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 424: UIF TEMP[15].xxxx :0 425: MOV TEMP[15].x, CONST[82].wwww 426: ELSE :0 427: MOV TEMP[15].x, TEMP[12].wwww 428: ENDIF 429: MOV TEMP[13].w, TEMP[15].xxxx 430: DP4 TEMP[10].x, TEMP[3], TEMP[10] 431: MOV_SAT TEMP[10].x, TEMP[10].xxxx 432: DP4 TEMP[15].x, TEMP[3], TEMP[13] 433: MOV_SAT TEMP[15].x, TEMP[15].xxxx 434: MOV TEMP[10].y, TEMP[15].xxxx 435: ABS TEMP[15].x, TEMP[14].xxxx 436: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 437: UIF TEMP[15].xxxx :0 438: MOV TEMP[15].x, CONST[86].zzzz 439: ELSE :0 440: MOV TEMP[15].x, IMM[0].xxxx 441: ENDIF 442: ABS TEMP[16].x, TEMP[14].xxxx 443: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 444: UIF TEMP[16].xxxx :0 445: MOV TEMP[16].x, CONST[86].wwww 446: ELSE :0 447: MOV TEMP[16].x, IMM[0].xxxx 448: ENDIF 449: MOV TEMP[13].y, TEMP[16].xxxx 450: ABS TEMP[16].x, TEMP[14].xxxx 451: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 452: UIF TEMP[16].xxxx :0 453: MOV TEMP[16].x, CONST[86].xxxx 454: ELSE :0 455: MOV TEMP[16].x, IMM[0].xxxx 456: ENDIF 457: MOV TEMP[13].z, TEMP[16].xxxx 458: ABS TEMP[16].x, TEMP[14].xxxx 459: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 460: UIF TEMP[16].xxxx :0 461: MOV TEMP[16].x, CONST[86].yyyy 462: ELSE :0 463: MOV TEMP[16].x, IMM[0].xxxx 464: ENDIF 465: MOV TEMP[13].w, TEMP[16].xxxx 466: ABS TEMP[16].x, TEMP[14].yyyy 467: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].xxxx 468: UIF TEMP[16].xxxx :0 469: MOV TEMP[16].x, CONST[87].zzzz 470: ELSE :0 471: MOV TEMP[16].x, TEMP[15].xxxx 472: ENDIF 473: ABS TEMP[15].x, TEMP[14].yyyy 474: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 475: UIF TEMP[15].xxxx :0 476: MOV TEMP[15].x, CONST[87].wwww 477: ELSE :0 478: MOV TEMP[15].x, TEMP[13].yyyy 479: ENDIF 480: MOV TEMP[13].y, TEMP[15].xxxx 481: ABS TEMP[15].x, TEMP[14].yyyy 482: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 483: UIF TEMP[15].xxxx :0 484: MOV TEMP[15].x, CONST[87].xxxx 485: ELSE :0 486: MOV TEMP[15].x, TEMP[13].zzzz 487: ENDIF 488: MOV TEMP[13].z, TEMP[15].xxxx 489: ABS TEMP[15].x, TEMP[14].yyyy 490: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 491: UIF TEMP[15].xxxx :0 492: MOV TEMP[15].x, CONST[87].yyyy 493: ELSE :0 494: MOV TEMP[15].x, TEMP[13].wwww 495: ENDIF 496: MOV TEMP[13].w, TEMP[15].xxxx 497: ABS TEMP[15].x, TEMP[14].zzzz 498: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 499: UIF TEMP[15].xxxx :0 500: MOV TEMP[15].x, CONST[88].zzzz 501: ELSE :0 502: MOV TEMP[15].x, TEMP[16].xxxx 503: ENDIF 504: MOV TEMP[13].x, TEMP[15].xxxx 505: ABS TEMP[15].x, TEMP[14].zzzz 506: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 507: UIF TEMP[15].xxxx :0 508: MOV TEMP[15].x, CONST[88].wwww 509: ELSE :0 510: MOV TEMP[15].x, TEMP[13].yyyy 511: ENDIF 512: MOV TEMP[13].y, TEMP[15].xxxx 513: ABS TEMP[15].x, TEMP[14].zzzz 514: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 515: UIF TEMP[15].xxxx :0 516: MOV TEMP[15].x, CONST[88].xxxx 517: ELSE :0 518: MOV TEMP[15].x, TEMP[13].zzzz 519: ENDIF 520: MOV TEMP[13].z, TEMP[15].xxxx 521: ABS TEMP[15].x, TEMP[14].zzzz 522: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].xxxx 523: UIF TEMP[15].xxxx :0 524: MOV TEMP[15].x, CONST[88].yyyy 525: ELSE :0 526: MOV TEMP[15].x, TEMP[13].wwww 527: ENDIF 528: MOV TEMP[13].w, TEMP[15].xxxx 529: MAD TEMP[7].xy, TEMP[10].xyyy, TEMP[13].xyyy, TEMP[13].zwww 530: ADD TEMP[3], TEMP[7], IMM[3].xxyy 531: TXL TEMP[13].x, TEMP[3], SAMP[2], SHADOW2D 532: MOV TEMP[3].x, TEMP[13].xxxx 533: ADD TEMP[10], TEMP[7], IMM[3].zxyy 534: ADD TEMP[6], TEMP[7], IMM[3].xzyy 535: ADD TEMP[12], TEMP[7], IMM[3].zzyy 536: TXL TEMP[13].x, TEMP[10], SAMP[2], SHADOW2D 537: MOV TEMP[3].y, TEMP[13].xxxx 538: TXL TEMP[13].x, TEMP[6], SAMP[2], SHADOW2D 539: MOV TEMP[3].z, TEMP[13].xxxx 540: TXL TEMP[13].x, TEMP[12], SAMP[2], SHADOW2D 541: MOV TEMP[3].w, TEMP[13].xxxx 542: DP4 TEMP[13].x, TEMP[3], IMM[2].wwww 543: ADD TEMP[10], TEMP[7], IMM[3].xyyy 544: TXL TEMP[15].x, TEMP[10], SAMP[2], SHADOW2D 545: MOV TEMP[10].x, TEMP[15].xxxx 546: ADD TEMP[6], TEMP[7], IMM[3].zyyy 547: TXL TEMP[6].x, TEMP[6], SAMP[2], SHADOW2D 548: ADD TEMP[12], TEMP[7], IMM[3].yzyy 549: TXL TEMP[12].x, TEMP[12], SAMP[2], SHADOW2D 550: ADD TEMP[11], TEMP[7], IMM[3].yxyy 551: TXL TEMP[11].x, TEMP[11], SAMP[2], SHADOW2D 552: MOV TEMP[10].y, TEMP[6].xxxx 553: MOV TEMP[10].z, TEMP[12].xxxx 554: MOV TEMP[10].w, TEMP[11].xxxx 555: DP4 TEMP[6].x, TEMP[10], IMM[3].wwww 556: MOV TEMP[10].xy, TEMP[7].xyyy 557: MOV TEMP[10].z, TEMP[8].xxxx 558: MOV TEMP[10].w, IMM[0].xxxx 559: TXL TEMP[8].x, TEMP[10], SAMP[2], SHADOW2D 560: ADD TEMP[3].x, TEMP[6].xxxx, TEMP[13].xxxx 561: MAD TEMP[3].x, TEMP[8].xxxx, IMM[4].xxxx, TEMP[3].xxxx 562: FSGE TEMP[6].x, TEMP[14].zzzz, IMM[0].xxxx 563: UIF TEMP[6].xxxx :0 564: MOV TEMP[6].x, IMM[1].xxxx 565: ELSE :0 566: MOV TEMP[6].x, TEMP[3].xxxx 567: ENDIF 568: LRP TEMP[7].x, TEMP[9].xxxx, TEMP[5].xxxx, TEMP[6].xxxx 569: MOV TEMP[5].x, TEMP[7].xxxx 570: ENDIF 571: ADD TEMP[3].xyz, -CONST[89].xyzz, IN[2].xyzz 572: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz 573: MAD TEMP[3].x, TEMP[6].xxxx, CONST[68].yyyy, CONST[68].xxxx 574: MOV_SAT TEMP[6].x, TEMP[3].xxxx 575: LRP TEMP[5].x, TEMP[6].xxxx, IMM[1].xxxx, TEMP[5].xxxx 576: ADD TEMP[3].x, -TEMP[5].xxxx, IMM[1].xxxx 577: MAD TEMP[2].x, TEMP[2].xxxx, -TEMP[3].xxxx, IMM[1].xxxx 578: MUL TEMP[3].xyz, TEMP[2].xxxx, TEMP[4].zyxx 579: MAD TEMP[2].x, TEMP[2].xxxx, IMM[5].xxxx, IMM[5].xxxx 580: LRP TEMP[4].xyz, TEMP[2].xxxx, TEMP[3].zyxx, TEMP[3].xyzz 581: ENDIF 582: ADD TEMP[3].xyz, TEMP[4].xyzz, CONST[31].xyzz 583: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xyzz 584: ADD TEMP[3].xyz, CONST[10].xyzz, -IN[2].xyzz 585: DP3 TEMP[2].x, TEMP[3].xyzz, TEMP[3].xyzz 586: SQRT TEMP[2].x, TEMP[2].xxxx 587: MAD TEMP[2].x, TEMP[2].xxxx, CONST[11].wwww, CONST[11].xxxx 588: MOV_SAT TEMP[2].x, TEMP[2].xxxx 589: MIN TEMP[2].x, TEMP[2].xxxx, CONST[11].zzzz 590: MUL TEMP[3].xyz, TEMP[1].xyzz, CONST[30].xxxx 591: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 592: MAD TEMP[1].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz 593: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[1].xyzz, TEMP[3].xyzz 594: MOV OUT[0], TEMP[0] 595: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %85 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %86 = load <8 x i32>, <8 x i32> addrspace(2)* %85, align 32, !tbaa !0 %87 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %88 = load <4 x i32>, <4 x i32> addrspace(2)* %87, align 16, !tbaa !0 %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = and i32 %5, 1 %98 = icmp ne i32 %97, 0 %99 = select i1 %98, <2 x i32> %7, <2 x i32> %8 %100 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %99) %101 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %99) %102 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %99) %103 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %99) %104 = and i32 %5, 1 %105 = icmp ne i32 %104, 0 %106 = select i1 %105, <2 x i32> %7, <2 x i32> %8 %107 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %106) %108 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %106) %109 = and i32 %5, 1 %110 = icmp ne i32 %109, 0 %111 = select i1 %110, <2 x i32> %7, <2 x i32> %8 %112 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %111) %113 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %111) %114 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %6, <2 x i32> %111) %115 = and i32 %5, 1 %116 = icmp ne i32 %115, 0 %117 = select i1 %116, <2 x i32> %7, <2 x i32> %9 %118 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %117) %119 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %117) %120 = bitcast float %107 to i32 %121 = bitcast float %108 to i32 %122 = insertelement <2 x i32> undef, i32 %120, i32 0 %123 = insertelement <2 x i32> %122, i32 %121, i32 1 %124 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %123, <8 x i32> %86, <4 x i32> %88, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %125 = extractelement <4 x float> %124, i32 0 %126 = extractelement <4 x float> %124, i32 1 %127 = extractelement <4 x float> %124, i32 2 %128 = extractelement <4 x float> %124, i32 3 %129 = bitcast float %118 to i32 %130 = bitcast float %119 to i32 %131 = insertelement <2 x i32> undef, i32 %129, i32 0 %132 = insertelement <2 x i32> %131, i32 %130, i32 1 %133 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %132, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = extractelement <4 x float> %133, i32 2 %137 = extractelement <4 x float> %133, i32 3 %138 = fmul float %125, %100 %139 = fmul float %126, %101 %140 = fmul float %127, %102 %141 = fmul float %128, %103 %142 = fmul float %134, %31 %143 = fmul float %135, %32 %144 = fmul float %136, %33 %145 = fcmp ogt float %137, -0.000000e+00 %146 = bitcast float %84 to i32 %147 = icmp ne i32 %146, 0 %148 = and i1 %145, %147 br i1 %148, label %IF, label %ENDIF IF: ; preds = %main_body %149 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %150 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %151 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %152 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %153 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %154 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %155 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %156 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %157 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %158 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %159 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %160 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %161 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %162 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %163 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %164 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %165 = fmul float %134, 0x3FCB333340000000 %166 = fmul float %135, 0x3FE6E48E80000000 %167 = fadd float %166, %165 %168 = fmul float %136, 0x3FB2752540000000 %169 = fadd float %167, %168 %170 = fdiv float 1.000000e+00, %169 %171 = fmul float %170, %137 %172 = fadd float %112, 0.000000e+00 %173 = fadd float %113, 0.000000e+00 %174 = fadd float %114, 0.000000e+00 %175 = fmul float %112, 0.000000e+00 %176 = fadd float %175, 1.000000e+00 %177 = fmul float %172, %164 %178 = fmul float %173, %163 %179 = fadd float %177, %178 %180 = fmul float %174, %162 %181 = fadd float %179, %180 %182 = fmul float %176, %161 %183 = fadd float %181, %182 %184 = fmul float %172, %160 %185 = fmul float %173, %159 %186 = fadd float %184, %185 %187 = fmul float %174, %158 %188 = fadd float %186, %187 %189 = fmul float %176, %157 %190 = fadd float %188, %189 %191 = call float @llvm.AMDIL.clamp.(float %183, float 0.000000e+00, float 1.000000e+00) %192 = call float @llvm.AMDIL.clamp.(float %190, float 0.000000e+00, float 1.000000e+00) %193 = fsub float %191, %183 %194 = fsub float %192, %190 %195 = fadd float %193, %194 %196 = fmul float %172, %45 %197 = fmul float %173, %46 %198 = fadd float %196, %197 %199 = fmul float %174, %47 %200 = fadd float %198, %199 %201 = fmul float %176, %48 %202 = fadd float %200, %201 %203 = fmul float %172, %49 %204 = fmul float %173, %50 %205 = fadd float %203, %204 %206 = fmul float %174, %51 %207 = fadd float %205, %206 %208 = fmul float %176, %52 %209 = fadd float %207, %208 %210 = call float @llvm.AMDIL.clamp.(float %202, float 0.000000e+00, float 1.000000e+00) %211 = call float @llvm.AMDIL.clamp.(float %209, float 0.000000e+00, float 1.000000e+00) %212 = fsub float %210, %202 %213 = fsub float %211, %209 %214 = fadd float %212, %213 %215 = fmul float %172, %53 %216 = fmul float %173, %54 %217 = fadd float %215, %216 %218 = fmul float %174, %55 %219 = fadd float %217, %218 %220 = fmul float %176, %56 %221 = fadd float %219, %220 %222 = fmul float %172, %57 %223 = fmul float %173, %58 %224 = fadd float %222, %223 %225 = fmul float %174, %59 %226 = fadd float %224, %225 %227 = fmul float %176, %60 %228 = fadd float %226, %227 %229 = call float @llvm.fabs.f32(float %214) %230 = fcmp ole float %229, -0.000000e+00 %. = select i1 %230, float %202, float %221 %231 = call float @llvm.fabs.f32(float %214) %232 = fcmp ole float %231, -0.000000e+00 %temp36.0 = select i1 %232, float %209, float %228 %233 = call float @llvm.fabs.f32(float %214) %234 = fcmp ole float %233, -0.000000e+00 %.240 = select i1 %234, float 1.000000e+00, float 2.000000e+00 %235 = call float @llvm.fabs.f32(float %195) %236 = fcmp ole float %235, -0.000000e+00 %temp36.2 = select i1 %236, float %183, float %. %237 = call float @llvm.fabs.f32(float %195) %238 = fcmp ole float %237, -0.000000e+00 %.temp36.0 = select i1 %238, float %190, float %temp36.0 %239 = call float @llvm.fabs.f32(float %195) %240 = fcmp ole float %239, -0.000000e+00 %temp24.1 = select i1 %240, float 0.000000e+00, float %.240 %241 = fmul float %172, %156 %242 = fmul float %173, %155 %243 = fadd float %241, %242 %244 = fmul float %174, %154 %245 = fadd float %243, %244 %246 = fmul float %176, %153 %247 = fadd float %245, %246 %248 = fadd float %temp36.2, -5.000000e-01 %249 = fadd float %.temp36.0, -5.000000e-01 %250 = call float @llvm.fabs.f32(float %248) %251 = call float @llvm.fabs.f32(float %249) %252 = fsub float %250, %41 %253 = fsub float %251, %41 %254 = fmul float %252, %42 %255 = fmul float %253, %42 %256 = call float @llvm.AMDIL.clamp.(float %254, float 0.000000e+00, float 1.000000e+00) %257 = call float @llvm.AMDIL.clamp.(float %255, float 0.000000e+00, float 1.000000e+00) %258 = fsub float 1.000000e+00, %256 %259 = fsub float 1.000000e+00, %257 %260 = fmul float %259, %258 %261 = call float @llvm.AMDIL.clamp.(float %temp36.2, float 0.000000e+00, float 1.000000e+00) %262 = call float @llvm.AMDIL.clamp.(float %.temp36.0, float 0.000000e+00, float 1.000000e+00) %263 = fadd float %temp24.1, -1.000000e+00 %264 = fadd float %temp24.1, -2.000000e+00 %265 = call float @llvm.fabs.f32(float %temp24.1) %266 = fcmp ole float %265, -0.000000e+00 %.241 = select i1 %266, float %150, float 0.000000e+00 %267 = call float @llvm.fabs.f32(float %temp24.1) %268 = fcmp ole float %267, -0.000000e+00 %temp60.0 = select i1 %268, float %149, float 0.000000e+00 %269 = call float @llvm.fabs.f32(float %temp24.1) %270 = fcmp ole float %269, -0.000000e+00 %.242 = select i1 %270, float %152, float 0.000000e+00 %271 = call float @llvm.fabs.f32(float %temp24.1) %272 = fcmp ole float %271, -0.000000e+00 %temp60.2 = select i1 %272, float %151, float 0.000000e+00 %273 = call float @llvm.fabs.f32(float %263) %274 = fcmp ole float %273, -0.000000e+00 %..241 = select i1 %274, float %71, float %.241 %275 = call float @llvm.fabs.f32(float %263) %276 = fcmp ole float %275, -0.000000e+00 %temp56.2 = select i1 %276, float %72, float %temp60.0 %277 = call float @llvm.fabs.f32(float %263) %278 = fcmp ole float %277, -0.000000e+00 %..242 = select i1 %278, float %69, float %.242 %279 = call float @llvm.fabs.f32(float %263) %280 = fcmp ole float %279, -0.000000e+00 %temp56.4 = select i1 %280, float %70, float %temp60.2 %281 = call float @llvm.fabs.f32(float %264) %282 = fcmp ole float %281, -0.000000e+00 %...241 = select i1 %282, float %75, float %..241 %283 = call float @llvm.fabs.f32(float %264) %284 = fcmp ole float %283, -0.000000e+00 %temp56.6 = select i1 %284, float %76, float %temp56.2 %285 = call float @llvm.fabs.f32(float %264) %286 = fcmp ole float %285, -0.000000e+00 %...242 = select i1 %286, float %73, float %..242 %287 = call float @llvm.fabs.f32(float %264) %288 = fcmp ole float %287, -0.000000e+00 %temp56.8 = select i1 %288, float %74, float %temp56.4 %289 = fmul float %261, %...241 %290 = fadd float %289, %...242 %291 = fmul float %262, %temp56.6 %292 = fadd float %291, %temp56.8 %293 = fadd float %290, 0x3F40000000000000 %294 = fadd float %292, 0x3F40000000000000 %295 = fadd float %247, 0.000000e+00 %296 = bitcast float %295 to i32 %297 = bitcast float %293 to i32 %298 = bitcast float %294 to i32 %299 = insertelement <4 x i32> undef, i32 %296, i32 0 %300 = insertelement <4 x i32> %299, i32 %297, i32 1 %301 = insertelement <4 x i32> %300, i32 %298, i32 2 %302 = insertelement <4 x i32> %301, i32 0, i32 3 %303 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %302, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %304 = extractelement <4 x float> %303, i32 0 %305 = fadd float %290, 0xBF40000000000000 %306 = fadd float %292, 0x3F40000000000000 %307 = fadd float %247, 0.000000e+00 %308 = fadd float %290, 0x3F40000000000000 %309 = fadd float %292, 0xBF40000000000000 %310 = fadd float %247, 0.000000e+00 %311 = fadd float %290, 0xBF40000000000000 %312 = fadd float %292, 0xBF40000000000000 %313 = fadd float %247, 0.000000e+00 %314 = bitcast float %307 to i32 %315 = bitcast float %305 to i32 %316 = bitcast float %306 to i32 %317 = insertelement <4 x i32> undef, i32 %314, i32 0 %318 = insertelement <4 x i32> %317, i32 %315, i32 1 %319 = insertelement <4 x i32> %318, i32 %316, i32 2 %320 = insertelement <4 x i32> %319, i32 0, i32 3 %321 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %320, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %322 = extractelement <4 x float> %321, i32 0 %323 = bitcast float %310 to i32 %324 = bitcast float %308 to i32 %325 = bitcast float %309 to i32 %326 = insertelement <4 x i32> undef, i32 %323, i32 0 %327 = insertelement <4 x i32> %326, i32 %324, i32 1 %328 = insertelement <4 x i32> %327, i32 %325, i32 2 %329 = insertelement <4 x i32> %328, i32 0, i32 3 %330 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %329, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %331 = extractelement <4 x float> %330, i32 0 %332 = bitcast float %313 to i32 %333 = bitcast float %311 to i32 %334 = bitcast float %312 to i32 %335 = insertelement <4 x i32> undef, i32 %332, i32 0 %336 = insertelement <4 x i32> %335, i32 %333, i32 1 %337 = insertelement <4 x i32> %336, i32 %334, i32 2 %338 = insertelement <4 x i32> %337, i32 0, i32 3 %339 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %338, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %340 = extractelement <4 x float> %339, i32 0 %341 = fmul float %304, 6.250000e-02 %342 = fmul float %322, 6.250000e-02 %343 = fadd float %341, %342 %344 = fmul float %331, 6.250000e-02 %345 = fadd float %343, %344 %346 = fmul float %340, 6.250000e-02 %347 = fadd float %345, %346 %348 = fadd float %290, 0x3F40000000000000 %349 = fadd float %292, 0.000000e+00 %350 = fadd float %247, 0.000000e+00 %351 = bitcast float %350 to i32 %352 = bitcast float %348 to i32 %353 = bitcast float %349 to i32 %354 = insertelement <4 x i32> undef, i32 %351, i32 0 %355 = insertelement <4 x i32> %354, i32 %352, i32 1 %356 = insertelement <4 x i32> %355, i32 %353, i32 2 %357 = insertelement <4 x i32> %356, i32 0, i32 3 %358 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %357, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %359 = extractelement <4 x float> %358, i32 0 %360 = fadd float %290, 0xBF40000000000000 %361 = fadd float %292, 0.000000e+00 %362 = fadd float %247, 0.000000e+00 %363 = bitcast float %362 to i32 %364 = bitcast float %360 to i32 %365 = bitcast float %361 to i32 %366 = insertelement <4 x i32> undef, i32 %363, i32 0 %367 = insertelement <4 x i32> %366, i32 %364, i32 1 %368 = insertelement <4 x i32> %367, i32 %365, i32 2 %369 = insertelement <4 x i32> %368, i32 0, i32 3 %370 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %369, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %371 = extractelement <4 x float> %370, i32 0 %372 = fadd float %290, 0.000000e+00 %373 = fadd float %292, 0xBF40000000000000 %374 = fadd float %247, 0.000000e+00 %375 = bitcast float %374 to i32 %376 = bitcast float %372 to i32 %377 = bitcast float %373 to i32 %378 = insertelement <4 x i32> undef, i32 %375, i32 0 %379 = insertelement <4 x i32> %378, i32 %376, i32 1 %380 = insertelement <4 x i32> %379, i32 %377, i32 2 %381 = insertelement <4 x i32> %380, i32 0, i32 3 %382 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %381, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %383 = extractelement <4 x float> %382, i32 0 %384 = fadd float %290, 0.000000e+00 %385 = fadd float %292, 0x3F40000000000000 %386 = fadd float %247, 0.000000e+00 %387 = bitcast float %386 to i32 %388 = bitcast float %384 to i32 %389 = bitcast float %385 to i32 %390 = insertelement <4 x i32> undef, i32 %387, i32 0 %391 = insertelement <4 x i32> %390, i32 %388, i32 1 %392 = insertelement <4 x i32> %391, i32 %389, i32 2 %393 = insertelement <4 x i32> %392, i32 0, i32 3 %394 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %393, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %395 = extractelement <4 x float> %394, i32 0 %396 = fmul float %359, 1.250000e-01 %397 = fmul float %371, 1.250000e-01 %398 = fadd float %396, %397 %399 = fmul float %383, 1.250000e-01 %400 = fadd float %398, %399 %401 = fmul float %395, 1.250000e-01 %402 = fadd float %400, %401 %403 = bitcast float %247 to i32 %404 = bitcast float %290 to i32 %405 = bitcast float %292 to i32 %406 = insertelement <4 x i32> undef, i32 %403, i32 0 %407 = insertelement <4 x i32> %406, i32 %404, i32 1 %408 = insertelement <4 x i32> %407, i32 %405, i32 2 %409 = insertelement <4 x i32> %408, i32 0, i32 3 %410 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %409, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %411 = extractelement <4 x float> %410, i32 0 %412 = fadd float %402, %347 %413 = fmul float %411, 2.500000e-01 %414 = fadd float %413, %412 %415 = fcmp olt float %260, 1.000000e+00 br i1 %415, label %IF127, label %ENDIF126 ENDIF: ; preds = %main_body, %ENDIF126 %temp16.0 = phi float [ %702, %ENDIF126 ], [ %142, %main_body ] %temp17.0 = phi float [ %706, %ENDIF126 ], [ %143, %main_body ] %temp18.0 = phi float [ %710, %ENDIF126 ], [ %144, %main_body ] %416 = fadd float %temp16.0, %38 %417 = fadd float %temp17.0, %39 %418 = fadd float %temp18.0, %40 %419 = fmul float %138, %416 %420 = fmul float %139, %417 %421 = fmul float %140, %418 %422 = fsub float %25, %112 %423 = fsub float %26, %113 %424 = fsub float %27, %114 %425 = fmul float %422, %422 %426 = fmul float %423, %423 %427 = fadd float %426, %425 %428 = fmul float %424, %424 %429 = fadd float %427, %428 %430 = call float @llvm.sqrt.f32(float %429) %431 = fmul float %430, %30 %432 = fadd float %431, %28 %433 = call float @llvm.AMDIL.clamp.(float %432, float 0.000000e+00, float 1.000000e+00) %434 = call float @llvm.minnum.f32(float %433, float %29) %435 = fmul float %419, %37 %436 = fmul float %420, %37 %437 = fmul float %421, %37 %438 = fmul float %434, %434 %439 = fmul float %37, %419 %440 = fsub float %34, %439 %441 = fmul float %37, %420 %442 = fsub float %35, %441 %443 = fmul float %37, %421 %444 = fsub float %36, %443 %445 = fmul float %438, %440 %446 = fadd float %445, %435 %447 = fmul float %438, %442 %448 = fadd float %447, %436 %449 = fmul float %438, %444 %450 = fadd float %449, %437 %451 = call i32 @llvm.SI.packf16(float %446, float %448) %452 = bitcast i32 %451 to float %453 = call i32 @llvm.SI.packf16(float %450, float %141) %454 = bitcast i32 %453 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %452, float %454, float %452, float %454) ret void IF127: ; preds = %IF %455 = fadd float %temp24.1, 0.000000e+00 %456 = fadd float %temp24.1, -1.000000e+00 %457 = fadd float %temp24.1, -2.000000e+00 %458 = call float @llvm.fabs.f32(float %455) %459 = fcmp ole float %458, -0.000000e+00 %.243 = select i1 %459, float %45, float 0.000000e+00 %460 = call float @llvm.fabs.f32(float %455) %461 = fcmp ole float %460, -0.000000e+00 %temp60.5 = select i1 %461, float %46, float 0.000000e+00 %462 = call float @llvm.fabs.f32(float %455) %463 = fcmp ole float %462, -0.000000e+00 %.244 = select i1 %463, float %47, float 0.000000e+00 %464 = call float @llvm.fabs.f32(float %455) %465 = fcmp ole float %464, -0.000000e+00 %temp60.7 = select i1 %465, float %48, float 0.000000e+00 %466 = call float @llvm.fabs.f32(float %455) %467 = fcmp ole float %466, -0.000000e+00 %.245 = select i1 %467, float %49, float 0.000000e+00 %468 = call float @llvm.fabs.f32(float %455) %469 = fcmp ole float %468, -0.000000e+00 %temp60.9 = select i1 %469, float %50, float 0.000000e+00 %470 = call float @llvm.fabs.f32(float %455) %471 = fcmp ole float %470, -0.000000e+00 %.246 = select i1 %471, float %51, float 0.000000e+00 %472 = call float @llvm.fabs.f32(float %455) %473 = fcmp ole float %472, -0.000000e+00 %temp60.11 = select i1 %473, float %52, float 0.000000e+00 %474 = call float @llvm.fabs.f32(float %456) %475 = fcmp ole float %474, -0.000000e+00 %..243 = select i1 %475, float %53, float %.243 %476 = call float @llvm.fabs.f32(float %456) %477 = fcmp ole float %476, -0.000000e+00 %temp60.13 = select i1 %477, float %54, float %temp60.5 %478 = call float @llvm.fabs.f32(float %456) %479 = fcmp ole float %478, -0.000000e+00 %..244 = select i1 %479, float %55, float %.244 %480 = call float @llvm.fabs.f32(float %456) %481 = fcmp ole float %480, -0.000000e+00 %temp60.15 = select i1 %481, float %56, float %temp60.7 %482 = call float @llvm.fabs.f32(float %456) %483 = fcmp ole float %482, -0.000000e+00 %..245 = select i1 %483, float %57, float %.245 %484 = call float @llvm.fabs.f32(float %456) %485 = fcmp ole float %484, -0.000000e+00 %temp60.17 = select i1 %485, float %58, float %temp60.9 %486 = call float @llvm.fabs.f32(float %456) %487 = fcmp ole float %486, -0.000000e+00 %..246 = select i1 %487, float %59, float %.246 %488 = call float @llvm.fabs.f32(float %456) %489 = fcmp ole float %488, -0.000000e+00 %temp60.19 = select i1 %489, float %60, float %temp60.11 %490 = call float @llvm.fabs.f32(float %457) %491 = fcmp ole float %490, -0.000000e+00 %...243 = select i1 %491, float %61, float %..243 %492 = call float @llvm.fabs.f32(float %457) %493 = fcmp ole float %492, -0.000000e+00 %temp60.21 = select i1 %493, float %62, float %temp60.13 %494 = call float @llvm.fabs.f32(float %457) %495 = fcmp ole float %494, -0.000000e+00 %...244 = select i1 %495, float %63, float %..244 %496 = call float @llvm.fabs.f32(float %457) %497 = fcmp ole float %496, -0.000000e+00 %temp60.23 = select i1 %497, float %64, float %temp60.15 %498 = call float @llvm.fabs.f32(float %457) %499 = fcmp ole float %498, -0.000000e+00 %...245 = select i1 %499, float %65, float %..245 %500 = call float @llvm.fabs.f32(float %457) %501 = fcmp ole float %500, -0.000000e+00 %temp60.25 = select i1 %501, float %66, float %temp60.17 %502 = call float @llvm.fabs.f32(float %457) %503 = fcmp ole float %502, -0.000000e+00 %...246 = select i1 %503, float %67, float %..246 %504 = call float @llvm.fabs.f32(float %457) %505 = fcmp ole float %504, -0.000000e+00 %temp60.27 = select i1 %505, float %68, float %temp60.19 %506 = fmul float %172, %...243 %507 = fmul float %173, %temp60.21 %508 = fadd float %506, %507 %509 = fmul float %174, %...244 %510 = fadd float %508, %509 %511 = fmul float %176, %temp60.23 %512 = fadd float %510, %511 %513 = call float @llvm.AMDIL.clamp.(float %512, float 0.000000e+00, float 1.000000e+00) %514 = fmul float %172, %...245 %515 = fmul float %173, %temp60.25 %516 = fadd float %514, %515 %517 = fmul float %174, %...246 %518 = fadd float %516, %517 %519 = fmul float %176, %temp60.27 %520 = fadd float %518, %519 %521 = call float @llvm.AMDIL.clamp.(float %520, float 0.000000e+00, float 1.000000e+00) %522 = call float @llvm.fabs.f32(float %455) %523 = fcmp ole float %522, -0.000000e+00 %.247 = select i1 %523, float %71, float 0.000000e+00 %524 = call float @llvm.fabs.f32(float %455) %525 = fcmp ole float %524, -0.000000e+00 %temp64.0 = select i1 %525, float %72, float 0.000000e+00 %526 = call float @llvm.fabs.f32(float %455) %527 = fcmp ole float %526, -0.000000e+00 %.248 = select i1 %527, float %69, float 0.000000e+00 %528 = call float @llvm.fabs.f32(float %455) %529 = fcmp ole float %528, -0.000000e+00 %temp64.2 = select i1 %529, float %70, float 0.000000e+00 %530 = call float @llvm.fabs.f32(float %456) %531 = fcmp ole float %530, -0.000000e+00 %..247 = select i1 %531, float %75, float %.247 %532 = call float @llvm.fabs.f32(float %456) %533 = fcmp ole float %532, -0.000000e+00 %temp60.29 = select i1 %533, float %76, float %temp64.0 %534 = call float @llvm.fabs.f32(float %456) %535 = fcmp ole float %534, -0.000000e+00 %..248 = select i1 %535, float %73, float %.248 %536 = call float @llvm.fabs.f32(float %456) %537 = fcmp ole float %536, -0.000000e+00 %temp60.31 = select i1 %537, float %74, float %temp64.2 %538 = call float @llvm.fabs.f32(float %457) %539 = fcmp ole float %538, -0.000000e+00 %...247 = select i1 %539, float %79, float %..247 %540 = call float @llvm.fabs.f32(float %457) %541 = fcmp ole float %540, -0.000000e+00 %temp60.33 = select i1 %541, float %80, float %temp60.29 %542 = call float @llvm.fabs.f32(float %457) %543 = fcmp ole float %542, -0.000000e+00 %...248 = select i1 %543, float %77, float %..248 %544 = call float @llvm.fabs.f32(float %457) %545 = fcmp ole float %544, -0.000000e+00 %temp60.35 = select i1 %545, float %78, float %temp60.31 %546 = fmul float %513, %...247 %547 = fadd float %546, %...248 %548 = fmul float %521, %temp60.33 %549 = fadd float %548, %temp60.35 %550 = fadd float %547, 0x3F40000000000000 %551 = fadd float %549, 0x3F40000000000000 %552 = fadd float %247, 0.000000e+00 %553 = bitcast float %552 to i32 %554 = bitcast float %550 to i32 %555 = bitcast float %551 to i32 %556 = insertelement <4 x i32> undef, i32 %553, i32 0 %557 = insertelement <4 x i32> %556, i32 %554, i32 1 %558 = insertelement <4 x i32> %557, i32 %555, i32 2 %559 = insertelement <4 x i32> %558, i32 0, i32 3 %560 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %559, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %561 = extractelement <4 x float> %560, i32 0 %562 = fadd float %547, 0xBF40000000000000 %563 = fadd float %549, 0x3F40000000000000 %564 = fadd float %247, 0.000000e+00 %565 = fadd float %547, 0x3F40000000000000 %566 = fadd float %549, 0xBF40000000000000 %567 = fadd float %247, 0.000000e+00 %568 = fadd float %547, 0xBF40000000000000 %569 = fadd float %549, 0xBF40000000000000 %570 = fadd float %247, 0.000000e+00 %571 = bitcast float %564 to i32 %572 = bitcast float %562 to i32 %573 = bitcast float %563 to i32 %574 = insertelement <4 x i32> undef, i32 %571, i32 0 %575 = insertelement <4 x i32> %574, i32 %572, i32 1 %576 = insertelement <4 x i32> %575, i32 %573, i32 2 %577 = insertelement <4 x i32> %576, i32 0, i32 3 %578 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %577, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %579 = extractelement <4 x float> %578, i32 0 %580 = bitcast float %567 to i32 %581 = bitcast float %565 to i32 %582 = bitcast float %566 to i32 %583 = insertelement <4 x i32> undef, i32 %580, i32 0 %584 = insertelement <4 x i32> %583, i32 %581, i32 1 %585 = insertelement <4 x i32> %584, i32 %582, i32 2 %586 = insertelement <4 x i32> %585, i32 0, i32 3 %587 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %586, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %588 = extractelement <4 x float> %587, i32 0 %589 = bitcast float %570 to i32 %590 = bitcast float %568 to i32 %591 = bitcast float %569 to i32 %592 = insertelement <4 x i32> undef, i32 %589, i32 0 %593 = insertelement <4 x i32> %592, i32 %590, i32 1 %594 = insertelement <4 x i32> %593, i32 %591, i32 2 %595 = insertelement <4 x i32> %594, i32 0, i32 3 %596 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %595, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %597 = extractelement <4 x float> %596, i32 0 %598 = fmul float %561, 6.250000e-02 %599 = fmul float %579, 6.250000e-02 %600 = fadd float %598, %599 %601 = fmul float %588, 6.250000e-02 %602 = fadd float %600, %601 %603 = fmul float %597, 6.250000e-02 %604 = fadd float %602, %603 %605 = fadd float %547, 0x3F40000000000000 %606 = fadd float %549, 0.000000e+00 %607 = fadd float %247, 0.000000e+00 %608 = bitcast float %607 to i32 %609 = bitcast float %605 to i32 %610 = bitcast float %606 to i32 %611 = insertelement <4 x i32> undef, i32 %608, i32 0 %612 = insertelement <4 x i32> %611, i32 %609, i32 1 %613 = insertelement <4 x i32> %612, i32 %610, i32 2 %614 = insertelement <4 x i32> %613, i32 0, i32 3 %615 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %614, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %616 = extractelement <4 x float> %615, i32 0 %617 = fadd float %547, 0xBF40000000000000 %618 = fadd float %549, 0.000000e+00 %619 = fadd float %247, 0.000000e+00 %620 = bitcast float %619 to i32 %621 = bitcast float %617 to i32 %622 = bitcast float %618 to i32 %623 = insertelement <4 x i32> undef, i32 %620, i32 0 %624 = insertelement <4 x i32> %623, i32 %621, i32 1 %625 = insertelement <4 x i32> %624, i32 %622, i32 2 %626 = insertelement <4 x i32> %625, i32 0, i32 3 %627 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %626, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %628 = extractelement <4 x float> %627, i32 0 %629 = fadd float %547, 0.000000e+00 %630 = fadd float %549, 0xBF40000000000000 %631 = fadd float %247, 0.000000e+00 %632 = bitcast float %631 to i32 %633 = bitcast float %629 to i32 %634 = bitcast float %630 to i32 %635 = insertelement <4 x i32> undef, i32 %632, i32 0 %636 = insertelement <4 x i32> %635, i32 %633, i32 1 %637 = insertelement <4 x i32> %636, i32 %634, i32 2 %638 = insertelement <4 x i32> %637, i32 0, i32 3 %639 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %638, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %640 = extractelement <4 x float> %639, i32 0 %641 = fadd float %547, 0.000000e+00 %642 = fadd float %549, 0x3F40000000000000 %643 = fadd float %247, 0.000000e+00 %644 = bitcast float %643 to i32 %645 = bitcast float %641 to i32 %646 = bitcast float %642 to i32 %647 = insertelement <4 x i32> undef, i32 %644, i32 0 %648 = insertelement <4 x i32> %647, i32 %645, i32 1 %649 = insertelement <4 x i32> %648, i32 %646, i32 2 %650 = insertelement <4 x i32> %649, i32 0, i32 3 %651 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %650, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %652 = extractelement <4 x float> %651, i32 0 %653 = fmul float %616, 1.250000e-01 %654 = fmul float %628, 1.250000e-01 %655 = fadd float %653, %654 %656 = fmul float %640, 1.250000e-01 %657 = fadd float %655, %656 %658 = fmul float %652, 1.250000e-01 %659 = fadd float %657, %658 %660 = bitcast float %247 to i32 %661 = bitcast float %547 to i32 %662 = bitcast float %549 to i32 %663 = insertelement <4 x i32> undef, i32 %660, i32 0 %664 = insertelement <4 x i32> %663, i32 %661, i32 1 %665 = insertelement <4 x i32> %664, i32 %662, i32 2 %666 = insertelement <4 x i32> %665, i32 0, i32 3 %667 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %666, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %668 = extractelement <4 x float> %667, i32 0 %669 = fadd float %659, %604 %670 = fmul float %668, 2.500000e-01 %671 = fadd float %670, %669 %672 = fcmp oge float %457, 0.000000e+00 %.249 = select i1 %672, float 1.000000e+00, float %671 %673 = fsub float 1.000000e+00, %260 %674 = fmul float %414, %260 %675 = fmul float %.249, %673 %676 = fadd float %674, %675 br label %ENDIF126 ENDIF126: ; preds = %IF, %IF127 %temp20.0 = phi float [ %676, %IF127 ], [ %414, %IF ] %677 = fsub float %112, %81 %678 = fsub float %113, %82 %679 = fsub float %114, %83 %680 = fmul float %677, %677 %681 = fmul float %678, %678 %682 = fadd float %681, %680 %683 = fmul float %679, %679 %684 = fadd float %682, %683 %685 = fmul float %684, %44 %686 = fadd float %685, %43 %687 = call float @llvm.AMDIL.clamp.(float %686, float 0.000000e+00, float 1.000000e+00) %688 = fsub float 1.000000e+00, %687 %689 = fmul float %temp20.0, %688 %690 = fadd float %687, %689 %691 = fsub float 1.000000e+00, %690 %692 = fmul float %691, %171 %693 = fsub float 1.000000e+00, %692 %694 = fmul float %693, %144 %695 = fmul float %693, %143 %696 = fmul float %693, %142 %697 = fmul float %693, 5.000000e-01 %698 = fadd float %697, 5.000000e-01 %699 = fsub float 1.000000e+00, %698 %700 = fmul float %696, %698 %701 = fmul float %694, %699 %702 = fadd float %700, %701 %703 = fsub float 1.000000e+00, %698 %704 = fmul float %695, %698 %705 = fmul float %695, %703 %706 = fadd float %704, %705 %707 = fsub float 1.000000e+00, %698 %708 = fmul float %694, %698 %709 = fmul float %696, %707 %710 = fadd float %708, %709 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x0 ; C00E0603 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x20 ; C00E0403 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[4:5], 0x0 ; C00A0802 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_and_b32 s11, 1, s9 ; 860B0981 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s9, s[12:15], 0xbc ; C0220246 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0xc0 ; C0220906 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0xc4 ; C0220946 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0xc8 ; C0220986 000000C8 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 v_cmp_eq_i32_e64 vcc, 1, s11 ; D0C2006A 00001681 v_cndmask_b32_e32 v10, v2, v0 ; 00140102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v11, v3, v1 ; 00160303 v_interp_p1_f32 v2, v10, 0, 0, [m0] ; D408000A v_interp_p2_f32 v2, [v2], v11, 0, 0, [m0] ; D409000B v_interp_p1_f32 v3, v10, 1, 0, [m0] ; D40C010A v_interp_p2_f32 v3, [v3], v11, 1, 0, [m0] ; D40D010B v_interp_p1_f32 v6, v10, 2, 0, [m0] ; D418020A v_interp_p2_f32 v6, [v6], v11, 2, 0, [m0] ; D419020B v_interp_p1_f32 v7, v10, 3, 0, [m0] ; D41C030A v_interp_p2_f32 v7, [v7], v11, 3, 0, [m0] ; D41D030B v_interp_p1_f32 v12, v10, 0, 1, [m0] ; D430040A v_interp_p2_f32 v12, [v12], v11, 0, 1, [m0] ; D431040B v_interp_p1_f32 v13, v10, 1, 1, [m0] ; D434050A v_interp_p2_f32 v13, [v13], v11, 1, 1, [m0] ; D435050B v_interp_p1_f32 v8, v10, 0, 2, [m0] ; D420080A v_interp_p2_f32 v8, [v8], v11, 0, 2, [m0] ; D421080B v_interp_p1_f32 v9, v10, 1, 2, [m0] ; D424090A v_interp_p2_f32 v9, [v9], v11, 1, 2, [m0] ; D425090B v_interp_p1_f32 v10, v10, 2, 2, [m0] ; D4280A0A s_buffer_load_dword s10, s[12:15], 0x5a0 ; C0220286 000005A0 v_interp_p2_f32 v10, [v10], v11, 2, 2, [m0] ; D4290A0B v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v4, v0, 0, 3, [m0] ; D4100C00 v_interp_p2_f32 v4, [v4], v1, 0, 3, [m0] ; D4110C01 v_interp_p1_f32 v5, v0, 1, 3, [m0] ; D4140D00 v_interp_p2_f32 v5, [v5], v1, 1, 3, [m0] ; D4150D01 image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[24:31], s[32:35] ; F0800F00 01060B0C s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[16:23], s[0:3] ; F0800F00 00040F04 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mul_f32_e32 v0, s36, v15 ; 0A001E24 v_mul_f32_e32 v1, s37, v16 ; 0A022025 v_mul_f32_e32 v4, s38, v17 ; 0A082226 v_mov_b32_e32 v5, 0x80000000 ; 7E0A02FF 80000000 v_cmp_lt_f32_e32 vcc, v5, v18 ; 7C822505 v_cmp_ne_i32_e64 s[0:1], 0, s10 ; D0C50000 00001480 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[10:11], s[0:1] ; BE8A2000 s_xor_b64 s[10:11], exec, s[10:11] ; 888A0A7E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x440 ; C0220406 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x4a0 ; C0220506 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4a4 ; C0220546 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a8 ; C0220586 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4ac ; C02205C6 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4d0 ; C0220606 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d4 ; C0220646 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d8 ; C02206C6 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4dc ; C0220746 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4e0 ; C02207C6 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e4 ; C0220846 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4e8 ; C0220886 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4ec ; C02208C6 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s56, s[12:15], 0x550 ; C0220E06 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[12:15], 0x554 ; C0220E46 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[12:15], 0x558 ; C0220E86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x570 ; C0220946 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x574 ; C02209C6 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x578 ; C0220A46 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x57c ; C0220AC6 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x590 ; C02204C6 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x594 ; C0220486 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x598 ; C0220446 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x40 ; C00E0B03 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x20 ; C00A0D02 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[12:15], 0x55c ; C0220EC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x560 ; C0220906 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x564 ; C0220986 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x568 ; C0220A06 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x56c ; C0220A86 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x490 ; C0220686 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x494 ; C0220706 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x498 ; C0220786 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x49c ; C0220806 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v23, 0, v9 ; 022E1280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v19, s66, v23 ; 0A262E42 v_add_f32_e32 v25, 0, v8 ; 02321080 v_add_f32_e32 v24, 0, v10 ; 02301480 v_mad_f32 v5, 0, v8, 1.0 ; D1C10005 03CA1080 v_mac_f32_e32 v19, s3, v25 ; 2C263203 v_mac_f32_e32 v19, s67, v24 ; 2C263043 v_mac_f32_e32 v19, s68, v5 ; 2C260A44 v_mul_f32_e32 v20, s70, v23 ; 0A282E46 v_mac_f32_e32 v20, s69, v25 ; 2C283245 v_mac_f32_e32 v20, s61, v24 ; 2C28303D v_mac_f32_e32 v20, s62, v5 ; 2C280A3E v_add_f32_e64 v21, 0, v19 clamp ; D1018015 00022680 v_add_f32_e64 v22, 0, v20 clamp ; D1018016 00022880 v_subrev_f32_e32 v21, v19, v21 ; 062A2B13 v_subrev_f32_e32 v22, v20, v22 ; 062C2D14 v_add_f32_e32 v21, v22, v21 ; 022A2B16 v_mul_f32_e32 v22, s28, v23 ; 0A2C2E1C v_mac_f32_e32 v22, s26, v25 ; 2C2C321A v_mac_f32_e32 v22, s30, v24 ; 2C2C301E v_mac_f32_e32 v22, s32, v5 ; 2C2C0A20 v_mul_f32_e32 v26, s21, v23 ; 0A342E15 v_mac_f32_e32 v26, s20, v25 ; 2C343214 v_mac_f32_e32 v26, s22, v24 ; 2C343016 v_mac_f32_e32 v26, s23, v5 ; 2C340A17 v_add_f32_e64 v27, 0, v22 clamp ; D101801B 00022C80 v_add_f32_e64 v28, 0, v26 clamp ; D101801C 00023480 v_subrev_f32_e32 v27, v22, v27 ; 06363716 v_subrev_f32_e32 v28, v26, v28 ; 0638391A v_add_f32_e32 v27, v28, v27 ; 0236371C v_mul_f32_e32 v28, s25, v23 ; 0A382E19 v_mac_f32_e32 v28, s24, v25 ; 2C383218 v_mac_f32_e32 v28, s27, v24 ; 2C38301B v_mac_f32_e32 v28, s29, v5 ; 2C380A1D v_mul_f32_e32 v29, s33, v23 ; 0A3A2E21 v_mac_f32_e32 v29, s31, v25 ; 2C3A321F v_mac_f32_e32 v29, s34, v24 ; 2C3A3022 v_mac_f32_e32 v29, s35, v5 ; 2C3A0A23 v_mov_b32_e32 v30, 0x80000000 ; 7E3C02FF 80000000 v_cmp_le_f32_e64 vcc, |v27|, v30 ; D043016A 00023D1B v_cndmask_b32_e32 v22, v28, v22 ; 002C2D1C v_cndmask_b32_e32 v26, v29, v26 ; 0034351D v_cndmask_b32_e64 v27, 2.0, 1.0, vcc ; D100001B 01A9E4F4 v_cmp_le_f32_e64 vcc, |v21|, v30 ; D043016A 00023D15 v_cndmask_b32_e32 v22, v22, v19 ; 002C2716 v_cndmask_b32_e32 v26, v26, v20 ; 0034291A v_cndmask_b32_e64 v29, v27, 0, vcc ; D100001D 01A9011B v_mul_f32_e32 v19, s64, v23 ; 0A262E40 v_mac_f32_e32 v19, s63, v25 ; 2C26323F v_mac_f32_e32 v19, s65, v24 ; 2C263041 v_mac_f32_e32 v19, s60, v5 ; 2C260A3C v_add_f32_e64 v27, 0, v22 clamp ; D101801B 00022C80 v_add_f32_e64 v28, 0, v26 clamp ; D101801C 00023480 v_add_f32_e32 v20, -1.0, v29 ; 02283AF3 v_add_f32_e32 v21, -2.0, v29 ; 022A3AF5 v_cmp_le_f32_e64 vcc, |v29|, v30 ; D043016A 00023D1D v_mov_b32_e32 v31, s58 ; 7E3E023A v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_mov_b32_e32 v32, s59 ; 7E40023B v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_mov_b32_e32 v33, s56 ; 7E420238 v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_mov_b32_e32 v34, s57 ; 7E440239 v_cndmask_b32_e32 v34, 0, v34 ; 00444480 v_cmp_le_f32_e64 vcc, |v20|, v30 ; D043016A 00023D14 v_mov_b32_e32 v20, s40 ; 7E280228 v_cndmask_b32_e32 v20, v31, v20 ; 0028291F v_mov_b32_e32 v31, s42 ; 7E3E022A v_cndmask_b32_e32 v31, v32, v31 ; 003E3F20 v_mov_b32_e32 v32, s36 ; 7E400224 v_cndmask_b32_e32 v32, v33, v32 ; 00404121 v_mov_b32_e32 v33, s38 ; 7E420226 v_cndmask_b32_e32 v33, v34, v33 ; 00424322 v_cmp_le_f32_e64 vcc, |v21|, v30 ; D043016A 00023D15 v_mov_b32_e32 v21, s41 ; 7E2A0229 v_cndmask_b32_e32 v30, v20, v21 ; 003C2B14 v_mov_b32_e32 v20, s43 ; 7E28022B v_cndmask_b32_e32 v31, v31, v20 ; 003E291F v_mov_b32_e32 v20, s37 ; 7E280225 v_cndmask_b32_e32 v20, v32, v20 ; 00282920 v_mov_b32_e32 v21, s39 ; 7E2A0227 v_cndmask_b32_e32 v21, v33, v21 ; 002A2B21 v_mac_f32_e32 v20, v30, v27 ; 2C28371E v_mac_f32_e32 v21, v31, v28 ; 2C2A391F v_mov_b32_e32 v27, 0x3a000000 ; 7E3602FF 3A000000 v_add_f32_e32 v31, v27, v20 ; 023E291B v_add_f32_e32 v32, v27, v21 ; 02402B1B v_add_f32_e32 v30, 0, v19 ; 023C2680 s_mov_b32 s56, 0 ; BEB80080 v_mov_b32_e32 v33, s56 ; 7E420238 v_mov_b32_e32 v27, 0xba000000 ; 7E3602FF BA000000 v_add_f32_e32 v28, v27, v20 ; 0238291B v_mov_b32_e32 v34, v30 ; 7E44031E v_mov_b32_e32 v35, v31 ; 7E46031F v_mov_b32_e32 v36, v32 ; 7E480320 v_mov_b32_e32 v37, v33 ; 7E4A0321 v_add_f32_e32 v27, v27, v21 ; 02362B1B v_mov_b32_e32 v35, v28 ; 7E46031C v_mov_b32_e32 v38, v30 ; 7E4C031E v_mov_b32_e32 v39, v31 ; 7E4E031F v_mov_b32_e32 v40, v32 ; 7E500320 v_mov_b32_e32 v41, v33 ; 7E520321 v_mov_b32_e32 v36, v32 ; 7E480320 v_mov_b32_e32 v40, v27 ; 7E50031B v_mov_b32_e32 v37, s56 ; 7E4A0238 v_mov_b32_e32 v41, s56 ; 7E520238 image_sample_c_l v28, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[52:55] ; F0B00100 01AB1C1E s_nop 0 ; BF800000 image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2A22 v_mov_b32_e32 v36, v27 ; 7E48031B image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB2626 v_mov_b32_e32 v37, s56 ; 7E4A0238 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2722 v_add_f32_e32 v36, 0, v21 ; 02482A80 v_mov_b32_e32 v43, v30 ; 7E56031E v_mov_b32_e32 v44, v31 ; 7E58031F v_mov_b32_e32 v45, v32 ; 7E5A0320 v_mov_b32_e32 v46, v33 ; 7E5C0321 v_mov_b32_e32 v45, v36 ; 7E5A0324 v_add_f32_e32 v31, 0, v20 ; 023E2880 v_mov_b32_e32 v46, s56 ; 7E5C0238 v_mov_b32_e32 v47, v30 ; 7E5E031E v_mov_b32_e32 v48, v31 ; 7E60031F v_mov_b32_e32 v49, v32 ; 7E620320 v_mov_b32_e32 v50, v33 ; 7E640321 image_sample_c_l v40, 1, 0, 0, 0, 0, 0, 0, 0, v[43:46], s[44:51], s[52:55] ; F0B00100 01AB282B v_mov_b32_e32 v49, v27 ; 7E62031B v_mov_b32_e32 v37, s56 ; 7E4A0238 image_sample_c_l v27, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB1B22 v_mov_b32_e32 v50, s56 ; 7E640238 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[47:50], s[44:51], s[52:55] ; F0B00100 01AB222F v_mov_b32_e32 v33, s56 ; 7E420238 image_sample_c_l v30, 1, 0, 0, 0, 0, 0, 0, 0, v[30:33], s[44:51], s[52:55] ; F0B00100 01AB1E1E v_mov_b32_e32 v31, 0x3d800000 ; 7E3E02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v32, v31, v42 ; 0A40551F v_mac_f32_e32 v32, v31, v28 ; 2C40391F s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v32, v31, v38 ; 2C404D1F s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v32, v31, v39 ; 2C404F1F v_mov_b32_e32 v28, 0x3e000000 ; 7E3802FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v27, v28, v27 ; 0A36371C v_mac_f32_e32 v27, v28, v40 ; 2C36511C s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v27, v28, v34 ; 2C36451C s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v27, v28, v30 ; 2C363D1C v_add_f32_e32 v22, -0.5, v22 ; 022C2CF1 v_add_f32_e32 v26, -0.5, v26 ; 023434F1 v_sub_f32_e64 v22, |v22|, s1 ; D1020116 00000316 v_sub_f32_e64 v26, |v26|, s1 ; D102011A 0000031A v_mul_f32_e32 v22, s2, v22 ; 0A2C2C02 v_mul_f32_e32 v26, s2, v26 ; 0A343402 v_add_f32_e64 v22, 0, v22 clamp ; D1018016 00022C80 v_add_f32_e64 v26, 0, v26 clamp ; D101801A 00023480 v_sub_f32_e32 v22, 1.0, v22 ; 042C2CF2 v_mad_f32 v28, -v26, v22, v22 ; D1C1001C 245A2D1A v_mov_b32_e32 v22, 0 ; 7E2C0280 v_add_f32_e32 v26, v32, v27 ; 02343720 image_sample_c_l v20, 1, 0, 0, 0, 0, 0, 0, 0, v[19:22], s[44:51], s[52:55] ; F0B00100 01AB1413 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v26, v20, v26, 0x3e800000 ; 2E343514 3E800000 v_mov_b32_e32 v27, s0 ; 7E360200 v_cmp_gt_f32_e32 vcc, 1.0, v28 ; 7C8838F2 s_and_saveexec_b64 s[58:59], vcc ; BEBA206A s_xor_b64 s[58:59], exec, s[58:59] ; 88BA3A7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s57, s[12:15], 0x510 ; C0220E46 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x514 ; C0220F06 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x518 ; C0220F46 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x51c ; C0220F86 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x520 ; C0220FC6 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x524 ; C0221006 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x528 ; C0221046 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x52c ; C0221086 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x580 ; C02210C6 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x584 ; C0221106 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x588 ; C0221146 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x58c ; C0221186 0000058C v_mov_b32_e32 v20, s26 ; 7E28021A v_mov_b32_e32 v21, s28 ; 7E2A021C v_mov_b32_e32 v22, s30 ; 7E2C021E v_mov_b32_e32 v30, s32 ; 7E3C0220 v_mov_b32_e32 v31, s20 ; 7E3E0214 v_mov_b32_e32 v32, s21 ; 7E400215 v_mov_b32_e32 v33, s22 ; 7E420216 v_mov_b32_e32 v34, s23 ; 7E440217 v_mov_b32_e32 v35, s24 ; 7E460218 v_mov_b32_e32 v36, s25 ; 7E480219 v_mov_b32_e32 v37, s27 ; 7E4A021B v_add_f32_e32 v38, 0, v29 ; 024C3A80 v_mov_b32_e32 v39, 0x80000000 ; 7E4E02FF 80000000 v_cmp_le_f32_e64 vcc, |v38|, v39 ; D043016A 00024F26 v_add_f32_e32 v38, -1.0, v29 ; 024C3AF3 v_cmp_le_f32_e64 s[0:1], |v38|, v39 ; D0430100 00024F26 v_mov_b32_e32 v38, s29 ; 7E4C021D v_cndmask_b32_e32 v20, 0, v20 ; 00282880 v_cndmask_b32_e64 v20, v20, v35, s[0:1] ; D1000014 00024714 v_mov_b32_e32 v35, s31 ; 7E46021F v_cndmask_b32_e32 v21, 0, v21 ; 002A2A80 v_cndmask_b32_e64 v21, v21, v36, s[0:1] ; D1000015 00024915 v_mov_b32_e32 v36, s33 ; 7E480221 v_cndmask_b32_e32 v22, 0, v22 ; 002C2C80 v_cndmask_b32_e64 v22, v22, v37, s[0:1] ; D1000016 00024B16 v_mov_b32_e32 v37, s34 ; 7E4A0222 v_cndmask_b32_e32 v30, 0, v30 ; 003C3C80 v_cndmask_b32_e64 v30, v30, v38, s[0:1] ; D100001E 00024D1E v_mov_b32_e32 v38, s35 ; 7E4C0223 v_cndmask_b32_e32 v31, 0, v31 ; 003E3E80 v_cndmask_b32_e64 v31, v31, v35, s[0:1] ; D100001F 0002471F v_mov_b32_e32 v35, s36 ; 7E460224 v_cndmask_b32_e32 v32, 0, v32 ; 00404080 v_cndmask_b32_e64 v32, v32, v36, s[0:1] ; D1000020 00024920 v_mov_b32_e32 v36, s38 ; 7E480226 v_cndmask_b32_e32 v33, 0, v33 ; 00424280 v_cndmask_b32_e64 v33, v33, v37, s[0:1] ; D1000021 00024B21 v_mov_b32_e32 v37, s40 ; 7E4A0228 v_cndmask_b32_e32 v34, 0, v34 ; 00444480 v_cndmask_b32_e64 v34, v34, v38, s[0:1] ; D1000022 00024D22 v_mov_b32_e32 v38, s42 ; 7E4C022A v_add_f32_e32 v29, -2.0, v29 ; 023A3AF5 v_cmp_le_f32_e64 s[2:3], |v29|, v39 ; D0430102 00024F1D s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v39, s57 ; 7E4E0239 v_cndmask_b32_e64 v20, v20, v39, s[2:3] ; D1000014 000A4F14 v_mov_b32_e32 v39, s60 ; 7E4E023C v_cndmask_b32_e64 v21, v21, v39, s[2:3] ; D1000015 000A4F15 v_mov_b32_e32 v39, s61 ; 7E4E023D v_cndmask_b32_e64 v22, v22, v39, s[2:3] ; D1000016 000A4F16 v_mov_b32_e32 v39, s62 ; 7E4E023E v_cndmask_b32_e64 v30, v30, v39, s[2:3] ; D100001E 000A4F1E v_mov_b32_e32 v39, s63 ; 7E4E023F v_cndmask_b32_e64 v31, v31, v39, s[2:3] ; D100001F 000A4F1F v_mov_b32_e32 v39, s64 ; 7E4E0240 v_cndmask_b32_e64 v32, v32, v39, s[2:3] ; D1000020 000A4F20 v_mov_b32_e32 v39, s65 ; 7E4E0241 v_cndmask_b32_e64 v33, v33, v39, s[2:3] ; D1000021 000A4F21 v_mov_b32_e32 v39, s66 ; 7E4E0242 v_cndmask_b32_e64 v34, v34, v39, s[2:3] ; D1000022 000A4F22 v_mov_b32_e32 v39, s37 ; 7E4E0225 v_mul_f32_e32 v21, v21, v23 ; 0A2A2F15 v_mac_f32_e32 v21, v20, v25 ; 2C2A3314 v_mov_b32_e32 v20, s39 ; 7E280227 v_mac_f32_e32 v21, v22, v24 ; 2C2A3116 v_mov_b32_e32 v22, s41 ; 7E2C0229 v_mac_f32_e32 v21, v30, v5 ; 2C2A0B1E v_mov_b32_e32 v30, s43 ; 7E3C022B v_add_f32_e64 v40, 0, v21 clamp ; D1018028 00022A80 v_mul_f32_e32 v21, v32, v23 ; 0A2A2F20 v_mac_f32_e32 v21, v31, v25 ; 2C2A331F v_mac_f32_e32 v21, v33, v24 ; 2C2A3121 v_mac_f32_e32 v21, v34, v5 ; 2C2A0B22 v_add_f32_e64 v5, 0, v21 clamp ; D1018005 00022A80 v_cndmask_b32_e32 v21, 0, v37 ; 002A4A80 v_cndmask_b32_e32 v23, 0, v38 ; 002E4C80 v_cndmask_b32_e32 v24, 0, v35 ; 00304680 v_cndmask_b32_e32 v25, 0, v36 ; 00324880 v_cndmask_b32_e64 v21, v21, v22, s[0:1] ; D1000015 00022D15 v_cndmask_b32_e64 v22, v23, v30, s[0:1] ; D1000016 00023D17 v_cndmask_b32_e64 v23, v24, v39, s[0:1] ; D1000017 00024F18 v_cndmask_b32_e64 v24, v25, v20, s[0:1] ; D1000018 00022919 v_mov_b32_e32 v20, s69 ; 7E280245 v_cndmask_b32_e64 v25, v21, v20, s[2:3] ; D1000019 000A2915 v_mov_b32_e32 v20, s70 ; 7E280246 v_cndmask_b32_e64 v22, v22, v20, s[2:3] ; D1000016 000A2916 v_mov_b32_e32 v20, s67 ; 7E280243 v_cndmask_b32_e64 v20, v23, v20, s[2:3] ; D1000014 000A2917 v_mov_b32_e32 v21, s68 ; 7E2A0244 v_cndmask_b32_e64 v21, v24, v21, s[2:3] ; D1000015 000A2B18 v_mac_f32_e32 v20, v25, v40 ; 2C285119 v_mac_f32_e32 v21, v22, v5 ; 2C2A0B16 v_mov_b32_e32 v5, 0x3a000000 ; 7E0A02FF 3A000000 v_add_f32_e32 v23, v5, v20 ; 022E2905 v_add_f32_e32 v24, v5, v21 ; 02302B05 v_add_f32_e32 v22, 0, v19 ; 022C2680 v_mov_b32_e32 v25, s56 ; 7E320238 v_mov_b32_e32 v5, 0xba000000 ; 7E0A02FF BA000000 v_add_f32_e32 v30, v5, v20 ; 023C2905 v_mov_b32_e32 v31, v22 ; 7E3E0316 v_mov_b32_e32 v32, v23 ; 7E400317 v_mov_b32_e32 v33, v24 ; 7E420318 v_mov_b32_e32 v34, v25 ; 7E440319 v_mov_b32_e32 v32, v30 ; 7E40031E v_add_f32_e32 v5, v5, v21 ; 020A2B05 v_mov_b32_e32 v33, v24 ; 7E420318 v_mov_b32_e32 v35, v22 ; 7E460316 v_mov_b32_e32 v36, v23 ; 7E480317 v_mov_b32_e32 v37, v24 ; 7E4A0318 v_mov_b32_e32 v38, v25 ; 7E4C0319 image_sample_c_l v30, 1, 0, 0, 0, 0, 0, 0, 0, v[22:25], s[44:51], s[52:55] ; F0B00100 01AB1E16 v_mov_b32_e32 v34, s56 ; 7E440238 v_mov_b32_e32 v37, v5 ; 7E4A0305 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[31:34], s[44:51], s[52:55] ; F0B00100 01AB271F v_mov_b32_e32 v38, s56 ; 7E4C0238 v_mov_b32_e32 v33, v5 ; 7E420305 image_sample_c_l v35, 1, 0, 0, 0, 0, 0, 0, 0, v[35:38], s[44:51], s[52:55] ; F0B00100 01AB2323 v_mov_b32_e32 v34, s56 ; 7E440238 image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[31:34], s[44:51], s[52:55] ; F0B00100 01AB241F v_add_f32_e32 v33, 0, v21 ; 02422A80 v_mov_b32_e32 v40, v22 ; 7E500316 v_mov_b32_e32 v41, v23 ; 7E520317 v_mov_b32_e32 v42, v24 ; 7E540318 v_mov_b32_e32 v43, v25 ; 7E560319 v_mov_b32_e32 v42, v33 ; 7E540321 v_add_f32_e32 v23, 0, v20 ; 022E2880 v_mov_b32_e32 v43, s56 ; 7E560238 v_mov_b32_e32 v44, v22 ; 7E580316 v_mov_b32_e32 v45, v23 ; 7E5A0317 v_mov_b32_e32 v46, v24 ; 7E5C0318 v_mov_b32_e32 v47, v25 ; 7E5E0319 image_sample_c_l v37, 1, 0, 0, 0, 0, 0, 0, 0, v[40:43], s[44:51], s[52:55] ; F0B00100 01AB2528 v_mov_b32_e32 v46, v5 ; 7E5C0305 v_mov_b32_e32 v34, s56 ; 7E440238 image_sample_c_l v5, 1, 0, 0, 0, 0, 0, 0, 0, v[31:34], s[44:51], s[52:55] ; F0B00100 01AB051F v_mov_b32_e32 v47, s56 ; 7E5E0238 image_sample_c_l v31, 1, 0, 0, 0, 0, 0, 0, 0, v[44:47], s[44:51], s[52:55] ; F0B00100 01AB1F2C v_mov_b32_e32 v25, s56 ; 7E320238 image_sample_c_l v23, 1, 0, 0, 0, 0, 0, 0, 0, v[22:25], s[44:51], s[52:55] ; F0B00100 01AB1716 v_mov_b32_e32 v22, 0 ; 7E2C0280 image_sample_c_l v19, 1, 0, 0, 0, 0, 0, 0, 0, v[19:22], s[44:51], s[52:55] ; F0B00100 01AB1313 v_mov_b32_e32 v20, 0x3d800000 ; 7E2802FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v21, v20, v39 ; 0A2A4F14 v_mac_f32_e32 v21, v20, v30 ; 2C2A3D14 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v21, v20, v35 ; 2C2A4714 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v21, v20, v36 ; 2C2A4914 v_mov_b32_e32 v20, 0x3e000000 ; 7E2802FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v5, v20, v5 ; 0A0A0B14 v_mac_f32_e32 v5, v20, v37 ; 2C0A4B14 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v5, v20, v31 ; 2C0A3F14 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v5, v20, v23 ; 2C0A2F14 v_add_f32_e32 v5, v21, v5 ; 020A0B15 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v5, v19, v5, 0x3e800000 ; 2E0A0B13 3E800000 v_cmp_le_f32_e32 vcc, 0, v29 ; 7C863A80 v_cndmask_b32_e64 v5, v5, 1.0, vcc ; D1000005 01A9E505 v_mad_f32 v5, -v28, v5, v5 ; D1C10005 24160B1C v_mac_f32_e32 v5, v28, v26 ; 2C0A351C v_mov_b32_e32 v26, v5 ; 7E340305 s_or_b64 exec, exec, s[58:59] ; 87FE3A7E v_mul_f32_e32 v5, 0x3e59999a, v15 ; 0A0A1EFF 3E59999A v_madmk_f32_e32 v5, v16, v5, 0x3f372474 ; 2E0A0B10 3F372474 v_madmk_f32_e32 v5, v17, v5, 0x3d93a92a ; 2E0A0B11 3D93A92A v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mul_f32_e32 v5, v18, v5 ; 0A0A0B12 v_subrev_f32_e32 v15, s19, v8 ; 061E1013 v_subrev_f32_e32 v16, s18, v9 ; 06201212 v_subrev_f32_e32 v17, s17, v10 ; 06221411 v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_mac_f32_e32 v15, v16, v16 ; 2C1E2110 v_mac_f32_e32 v15, v17, v17 ; 2C1E2311 v_mad_f32 v15, v27, v15, s16 ; D1C1000F 00421F1B v_add_f32_e64 v15, 0, v15 clamp ; D101800F 00021E80 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mac_f32_e32 v15, v16, v26 ; 2C1E3510 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mad_f32 v15, -v15, v5, v5 ; D1C1000F 24160B0F v_mad_f32 v5, -v16, v5, 1.0 ; D1C10005 23CA0B10 v_mad_f32 v16, -v15, v4, v4 ; D1C10010 2412090F v_mad_f32 v4, -v15, v1, v1 ; D1C10004 2406030F v_mad_f32 v15, -v15, v0, v0 ; D1C1000F 2402010F v_mad_f32 v5, 0.5, v5, 0.5 ; D1C10005 03C20AF0 v_mad_f32 v0, -v5, v16, v16 ; D1C10000 24422105 v_mac_f32_e32 v0, v5, v15 ; 2C001F05 v_mad_f32 v1, -v5, v4, v4 ; D1C10001 24120905 v_mac_f32_e32 v1, v5, v4 ; 2C020905 v_mad_f32 v4, -v5, v15, v15 ; D1C10004 243E1F05 v_mac_f32_e32 v4, v5, v16 ; 2C082105 s_or_b64 exec, exec, s[10:11] ; 87FE0A7E s_buffer_load_dword s5, s[12:15], 0xa0 ; C0220146 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0xa4 ; C0220186 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0xa8 ; C02201C6 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xb0 ; C0220106 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xb8 ; C02200C6 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x1d0 ; C0220006 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d4 ; C0220046 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d8 ; C0220086 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x1f0 ; C0220406 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x1f4 ; C0220446 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x1f8 ; C0220306 000001F8 v_mov_b32_e32 v15, s9 ; 7E1E0209 v_mov_b32_e32 v5, s8 ; 7E0A0208 v_mul_f32_e32 v11, v2, v11 ; 0A161702 v_mul_f32_e32 v3, v3, v12 ; 0A061903 v_mul_f32_e32 v6, v6, v13 ; 0A0C1B06 v_mul_f32_e32 v2, v7, v14 ; 0A041D07 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v0, s16, v0 ; 02000010 v_add_f32_e32 v1, s17, v1 ; 02020211 v_add_f32_e32 v4, s12, v4 ; 0208080C v_mul_f32_e32 v0, v0, v11 ; 0A001700 v_mul_f32_e32 v1, v1, v3 ; 0A020701 v_mul_f32_e32 v3, v4, v6 ; 0A060D04 v_sub_f32_e32 v4, s5, v8 ; 04081005 v_sub_f32_e32 v6, s6, v9 ; 040C1206 v_sub_f32_e32 v7, s7, v10 ; 040E1407 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mac_f32_e32 v4, v6, v6 ; 2C080D06 v_mac_f32_e32 v4, v7, v7 ; 2C080F07 v_sqrt_f32_e32 v4, v4 ; 7E084F04 v_mad_f32 v4, v15, v4, s4 ; D1C10004 0012090F v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_min_f32_e32 v4, s3, v4 ; 14080803 v_mul_f32_e32 v6, s8, v0 ; 0A0C0008 v_mul_f32_e32 v7, s8, v1 ; 0A0E0208 v_mul_f32_e32 v8, s8, v3 ; 0A100608 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mad_f32 v0, -v0, v5, s0 ; D1C10000 20020B00 v_mad_f32 v1, -v1, v5, s1 ; D1C10001 20060B01 v_mad_f32 v3, -v3, v5, s2 ; D1C10003 200A0B03 v_mac_f32_e32 v6, v0, v4 ; 2C0C0900 v_mac_f32_e32 v7, v1, v4 ; 2C0E0901 v_mac_f32_e32 v8, v3, v4 ; 2C100903 v_cvt_pkrtz_f16_f32_e64 v0, v6, v7 ; D2960000 00020F06 v_cvt_pkrtz_f16_f32_e64 v1, v8, v2 ; D2960001 00020508 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 52 Code Size: 3188 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = add i32 %5, %8 %15 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %13, i32 0, i32 %14) %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, align 16, !tbaa !0 %22 = add i32 %5, %8 %23 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %22) %24 = extractelement <4 x float> %23, i32 0 %25 = extractelement <4 x float> %23, i32 1 %26 = extractelement <4 x float> %23, i32 2 %27 = extractelement <4 x float> %23, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %24, float %25, float %26, float %27) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %16, float %17, float %18, float %19) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C00A0004 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x10 ; C00A0104 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500 s_waitcnt vmcnt(0) ; BF8C0770 exp 15, 32, 0, 0, 0, v5, v6, v7, v8 ; C400020F 08070605 exp 15, 12, 0, 1, 0, v1, v2, v3, v4 ; C40008CF 04030201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 12 Code Size: 72 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6) %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6) %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6) %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6) %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float %29 = call i32 @llvm.SI.packf16(float %25, float %26) %30 = bitcast i32 %29 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %28, float %30, float %28, float %30) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: s_mov_b32 m0, s10 ; BEFC000A v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002 v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102 v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202 v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 16 VGPRS: 4 Code Size: 48 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL CONST[0..17] DCL TEMP[0..4], LOCAL 0: MOV TEMP[0].w, IN[0].wwww 1: MAD TEMP[0].xyz, IN[1].xyzz, CONST[13].xxxx, IN[0].xyzz 2: DP4 TEMP[1].x, TEMP[0], CONST[14] 3: DP4 TEMP[2].x, TEMP[0], CONST[15] 4: MOV TEMP[1].y, TEMP[2].xxxx 5: DP4 TEMP[0].x, TEMP[0], CONST[16] 6: MOV TEMP[1].z, TEMP[0].xxxx 7: MOV TEMP[1].w, CONST[0].yyyy 8: DP4 TEMP[0].x, TEMP[1], CONST[8] 9: DP4 TEMP[2].x, TEMP[1], CONST[9] 10: MOV TEMP[0].y, TEMP[2].xxxx 11: DP4 TEMP[3].x, TEMP[1], CONST[10] 12: MOV TEMP[0].z, TEMP[3].xxxx 13: DP4 TEMP[1].x, TEMP[1], CONST[11] 14: MOV TEMP[0].w, TEMP[1].xxxx 15: MOV TEMP[4], TEMP[0] 16: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[1].xxxx 17: MOV TEMP[0].z, TEMP[3].xxxx 18: MOV TEMP[0].y, -TEMP[2].xxxx 19: MAD TEMP[0].xy, CONST[17].xyyy, TEMP[1].xxxx, TEMP[0].xyyy 20: MOV OUT[0], TEMP[0] 21: MOV OUT[1], TEMP[4] 22: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 224) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 228) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 232) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 236) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 240) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 244) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 248) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 252) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 256) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 260) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 264) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 268) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 272) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 276) %47 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %48 = load <16 x i8>, <16 x i8> addrspace(2)* %47, align 16, !tbaa !0 %49 = add i32 %5, %8 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %49) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = extractelement <4 x float> %50, i32 3 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = fmul float %59, %32 %63 = fadd float %62, %51 %64 = fmul float %60, %32 %65 = fadd float %64, %52 %66 = fmul float %61, %32 %67 = fadd float %66, %53 %68 = fmul float %63, %33 %69 = fmul float %65, %34 %70 = fadd float %68, %69 %71 = fmul float %67, %35 %72 = fadd float %70, %71 %73 = fmul float %54, %36 %74 = fadd float %72, %73 %75 = fmul float %63, %37 %76 = fmul float %65, %38 %77 = fadd float %75, %76 %78 = fmul float %67, %39 %79 = fadd float %77, %78 %80 = fmul float %54, %40 %81 = fadd float %79, %80 %82 = fmul float %63, %41 %83 = fmul float %65, %42 %84 = fadd float %82, %83 %85 = fmul float %67, %43 %86 = fadd float %84, %85 %87 = fmul float %54, %44 %88 = fadd float %86, %87 %89 = fmul float %74, %16 %90 = fmul float %81, %17 %91 = fadd float %89, %90 %92 = fmul float %88, %18 %93 = fadd float %91, %92 %94 = fmul float %14, %19 %95 = fadd float %93, %94 %96 = fmul float %74, %20 %97 = fmul float %81, %21 %98 = fadd float %96, %97 %99 = fmul float %88, %22 %100 = fadd float %98, %99 %101 = fmul float %14, %23 %102 = fadd float %100, %101 %103 = fmul float %74, %24 %104 = fmul float %81, %25 %105 = fadd float %103, %104 %106 = fmul float %88, %26 %107 = fadd float %105, %106 %108 = fmul float %14, %27 %109 = fadd float %107, %108 %110 = fmul float %74, %28 %111 = fmul float %81, %29 %112 = fadd float %110, %111 %113 = fmul float %88, %30 %114 = fadd float %112, %113 %115 = fmul float %14, %31 %116 = fadd float %114, %115 %117 = fmul float %109, %15 %118 = fsub float %117, %116 %119 = fmul float %45, %116 %120 = fadd float %119, %95 %121 = fmul float %46, %116 %122 = fsub float %121, %102 %123 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %124 = load <16 x i8>, <16 x i8> addrspace(2)* %123, align 16, !tbaa !0 %125 = call float @llvm.SI.load.const(<16 x i8> %124, i32 0) %126 = fmul float %125, %95 %127 = call float @llvm.SI.load.const(<16 x i8> %124, i32 4) %128 = fmul float %127, %102 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %124, i32 8) %131 = fmul float %130, %109 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %124, i32 12) %134 = fmul float %133, %116 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %124, i32 16) %137 = fmul float %136, %95 %138 = call float @llvm.SI.load.const(<16 x i8> %124, i32 20) %139 = fmul float %138, %102 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %124, i32 24) %142 = fmul float %141, %109 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %124, i32 28) %145 = fmul float %144, %116 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %124, i32 32) %148 = fmul float %147, %95 %149 = call float @llvm.SI.load.const(<16 x i8> %124, i32 36) %150 = fmul float %149, %102 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %124, i32 40) %153 = fmul float %152, %109 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %124, i32 44) %156 = fmul float %155, %116 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %124, i32 48) %159 = fmul float %158, %95 %160 = call float @llvm.SI.load.const(<16 x i8> %124, i32 52) %161 = fmul float %160, %102 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %124, i32 56) %164 = fmul float %163, %109 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %124, i32 60) %167 = fmul float %166, %116 %168 = fadd float %165, %167 %169 = call float @llvm.SI.load.const(<16 x i8> %124, i32 64) %170 = fmul float %169, %95 %171 = call float @llvm.SI.load.const(<16 x i8> %124, i32 68) %172 = fmul float %171, %102 %173 = fadd float %170, %172 %174 = call float @llvm.SI.load.const(<16 x i8> %124, i32 72) %175 = fmul float %174, %109 %176 = fadd float %173, %175 %177 = call float @llvm.SI.load.const(<16 x i8> %124, i32 76) %178 = fmul float %177, %116 %179 = fadd float %176, %178 %180 = call float @llvm.SI.load.const(<16 x i8> %124, i32 80) %181 = fmul float %180, %95 %182 = call float @llvm.SI.load.const(<16 x i8> %124, i32 84) %183 = fmul float %182, %102 %184 = fadd float %181, %183 %185 = call float @llvm.SI.load.const(<16 x i8> %124, i32 88) %186 = fmul float %185, %109 %187 = fadd float %184, %186 %188 = call float @llvm.SI.load.const(<16 x i8> %124, i32 92) %189 = fmul float %188, %116 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %124, i32 96) %192 = fmul float %191, %95 %193 = call float @llvm.SI.load.const(<16 x i8> %124, i32 100) %194 = fmul float %193, %102 %195 = fadd float %192, %194 %196 = call float @llvm.SI.load.const(<16 x i8> %124, i32 104) %197 = fmul float %196, %109 %198 = fadd float %195, %197 %199 = call float @llvm.SI.load.const(<16 x i8> %124, i32 108) %200 = fmul float %199, %116 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %124, i32 112) %203 = fmul float %202, %95 %204 = call float @llvm.SI.load.const(<16 x i8> %124, i32 116) %205 = fmul float %204, %102 %206 = fadd float %203, %205 %207 = call float @llvm.SI.load.const(<16 x i8> %124, i32 120) %208 = fmul float %207, %109 %209 = fadd float %206, %208 %210 = call float @llvm.SI.load.const(<16 x i8> %124, i32 124) %211 = fmul float %210, %116 %212 = fadd float %209, %211 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %120, float %122, float %118, float %116) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %135, float %146, float %157, float %168) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %179, float %190, float %201, float %212) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x4 ; C0220202 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x8 ; C0220242 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x80 ; C0220282 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x84 ; C02202C2 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x88 ; C0220302 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x8c ; C0220342 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x90 ; C0220382 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x94 ; C02203C2 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x98 ; C0220402 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x9c ; C0220442 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0xa0 ; C0220482 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0xa4 ; C02204C2 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0xa8 ; C0220502 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0xac ; C0220542 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0xb0 ; C0220582 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0xb4 ; C02205C2 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0xb8 ; C0220602 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0xbc ; C0220642 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0xd0 ; C0220682 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0xe0 ; C02206C2 000000E0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0xe4 ; C0220702 000000E4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0xe8 ; C0220742 000000E8 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0xec ; C0220782 000000EC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0xf0 ; C02207C2 000000F0 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0xf4 ; C0220802 000000F4 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0xf8 ; C0220842 000000F8 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0xfc ; C0220882 000000FC s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x100 ; C02208C2 00000100 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x104 ; C0220902 00000104 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x108 ; C0220942 00000108 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[4:7], 0x10c ; C0220982 0000010C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[4:7], 0x110 ; C02209C2 00000110 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x114 ; C0220102 00000114 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0xc ; C0220A00 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x10 ; C0220A40 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x14 ; C0220A80 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x18 ; C0220AC0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x1c ; C0220B00 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x20 ; C0220B40 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x24 ; C0220B80 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x28 ; C0220BC0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x2c ; C0220C00 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x30 ; C0220C40 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x34 ; C0220C80 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x38 ; C0220CC0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x3c ; C0220D00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x40 ; C0220D40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x44 ; C0220D80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x48 ; C0220DC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[0:3], 0x4c ; C0220E00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s57, s[0:3], 0x50 ; C0220E40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[0:3], 0x54 ; C0220E80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[0:3], 0x58 ; C0220EC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[0:3], 0x5c ; C0220F00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[0:3], 0x60 ; C0220F40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[0:3], 0x64 ; C0220F80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[0:3], 0x68 ; C0220FC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[0:3], 0x6c ; C0221000 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s65, s[0:3], 0x70 ; C0221040 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[0:3], 0x74 ; C0221080 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[0:3], 0x78 ; C02210C0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s13 ; 7E00020D s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s21 ; 7E120215 v_mov_b32_e32 v10, s25 ; 7E140219 v_mad_f32 v1, s26, v5, v1 ; D1C10001 04060A1A v_mad_f32 v2, s26, v6, v2 ; D1C10002 040A0C1A v_mad_f32 v3, s26, v7, v3 ; D1C10003 040E0E1A v_mul_f32_e32 v5, s28, v2 ; 0A0A041C v_mul_f32_e32 v6, s32, v2 ; 0A0C0420 v_mul_f32_e32 v2, s36, v2 ; 0A040424 v_mac_f32_e32 v5, s27, v1 ; 2C0A021B v_mac_f32_e32 v6, s31, v1 ; 2C0C021F v_mac_f32_e32 v2, s35, v1 ; 2C040223 v_mac_f32_e32 v5, s29, v3 ; 2C0A061D v_mac_f32_e32 v6, s33, v3 ; 2C0C0621 v_mac_f32_e32 v2, s37, v3 ; 2C040625 v_mac_f32_e32 v5, s30, v4 ; 2C0A081E v_mac_f32_e32 v6, s34, v4 ; 2C0C0822 v_mac_f32_e32 v2, s38, v4 ; 2C040826 v_mul_f32_e32 v1, s11, v6 ; 0A020C0B v_mul_f32_e32 v3, s15, v6 ; 0A060C0F v_mul_f32_e32 v4, s19, v6 ; 0A080C13 v_mul_f32_e32 v6, s23, v6 ; 0A0C0C17 v_mac_f32_e32 v1, s10, v5 ; 2C020A0A v_mac_f32_e32 v3, s14, v5 ; 2C060A0E v_mac_f32_e32 v4, s18, v5 ; 2C080A12 v_mac_f32_e32 v6, s22, v5 ; 2C0C0A16 v_mac_f32_e32 v1, s12, v2 ; 2C02040C v_mac_f32_e32 v3, s16, v2 ; 2C060410 v_mac_f32_e32 v4, s20, v2 ; 2C080414 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s8, v0 ; 2C020008 v_mac_f32_e32 v3, s8, v8 ; 2C061008 v_mac_f32_e32 v4, s8, v9 ; 2C081208 v_mac_f32_e32 v6, s8, v10 ; 2C0C1408 v_mad_f32 v0, v4, s9, -v6 ; D1C10000 84181304 v_mad_f32 v2, s39, v6, v1 ; D1C10002 04060C27 v_mad_f32 v5, s4, v6, -v3 ; D1C10005 840E0C04 v_mul_f32_e32 v7, s6, v3 ; 0A0E0606 v_mul_f32_e32 v8, s42, v3 ; 0A10062A v_mul_f32_e32 v9, s46, v3 ; 0A12062E v_mul_f32_e32 v10, s50, v3 ; 0A140632 v_mul_f32_e32 v11, s54, v3 ; 0A160636 v_mul_f32_e32 v12, s58, v3 ; 0A18063A v_mul_f32_e32 v13, s62, v3 ; 0A1A063E v_mul_f32_e32 v3, s66, v3 ; 0A060642 v_mac_f32_e32 v7, s5, v1 ; 2C0E0205 v_mac_f32_e32 v8, s41, v1 ; 2C100229 v_mac_f32_e32 v9, s45, v1 ; 2C12022D v_mac_f32_e32 v10, s49, v1 ; 2C140231 v_mac_f32_e32 v11, s53, v1 ; 2C160235 v_mac_f32_e32 v12, s57, v1 ; 2C180239 v_mac_f32_e32 v13, s61, v1 ; 2C1A023D v_mac_f32_e32 v3, s65, v1 ; 2C060241 v_mac_f32_e32 v7, s7, v4 ; 2C0E0807 v_mac_f32_e32 v8, s43, v4 ; 2C10082B v_mac_f32_e32 v9, s47, v4 ; 2C12082F v_mac_f32_e32 v10, s51, v4 ; 2C140833 v_mac_f32_e32 v11, s55, v4 ; 2C160837 v_mac_f32_e32 v12, s59, v4 ; 2C18083B v_mac_f32_e32 v13, s63, v4 ; 2C1A083F v_mac_f32_e32 v3, s67, v4 ; 2C060843 v_mac_f32_e32 v7, s40, v6 ; 2C0E0C28 v_mac_f32_e32 v8, s44, v6 ; 2C100C2C v_mac_f32_e32 v9, s48, v6 ; 2C120C30 v_mac_f32_e32 v10, s52, v6 ; 2C140C34 v_mac_f32_e32 v11, s56, v6 ; 2C160C38 v_mac_f32_e32 v12, s60, v6 ; 2C180C3C v_mac_f32_e32 v13, s64, v6 ; 2C1A0C40 v_mac_f32_e32 v3, s0, v6 ; 2C060C00 exp 15, 12, 0, 0, 0, v2, v5, v0, v6 ; C40000CF 06000502 exp 15, 13, 0, 0, 0, v7, v8, v9, v10 ; C40000DF 0A090807 exp 15, 14, 0, 1, 0, v11, v12, v13, v3 ; C40008EF 030D0C0B s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 72 VGPRS: 16 Code Size: 1188 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL OUT[0], COLOR IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xyyx 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 0.000000e+00) %24 = bitcast i32 %23 to float %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00) %26 = bitcast i32 %25 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %24, float %26, float %24, float %26) ret void } ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: v_cvt_pkrtz_f16_f32_e64 v0, 1.0, 0 ; D2960000 000100F2 v_cvt_pkrtz_f16_f32_e64 v1, 0, 1.0 ; D2960001 0001E480 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 28 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL CONST[0..17] DCL TEMP[0..5], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, IN[0].wwww 2: MAD TEMP[1].xyz, IN[2].xyzz, CONST[13].xxxx, IN[0].xyzz 3: DP4 TEMP[2].x, TEMP[1], CONST[14] 4: DP4 TEMP[3].x, TEMP[1], CONST[15] 5: MOV TEMP[2].y, TEMP[3].xxxx 6: DP4 TEMP[1].x, TEMP[1], CONST[16] 7: MOV TEMP[2].z, TEMP[1].xxxx 8: MOV TEMP[2].w, CONST[0].yyyy 9: DP4 TEMP[1].x, TEMP[2], CONST[8] 10: DP4 TEMP[3].x, TEMP[2], CONST[9] 11: MOV TEMP[1].y, TEMP[3].xxxx 12: DP4 TEMP[4].x, TEMP[2], CONST[10] 13: MOV TEMP[1].z, TEMP[4].xxxx 14: DP4 TEMP[2].x, TEMP[2], CONST[11] 15: MOV TEMP[1].w, TEMP[2].xxxx 16: MOV TEMP[0].xy, IN[1].xyxx 17: MOV TEMP[5], TEMP[1] 18: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[2].xxxx 19: MOV TEMP[1].z, TEMP[4].xxxx 20: MOV TEMP[1].y, -TEMP[3].xxxx 21: MAD TEMP[1].xy, CONST[17].xyyy, TEMP[2].xxxx, TEMP[1].xyyy 22: MOV OUT[2], TEMP[0] 23: MOV OUT[0], TEMP[1] 24: MOV OUT[1], TEMP[5] 25: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 224) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 228) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 232) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 236) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 240) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 244) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 248) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 252) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 256) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 260) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 264) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 268) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 272) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 276) %47 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %48 = load <16 x i8>, <16 x i8> addrspace(2)* %47, align 16, !tbaa !0 %49 = add i32 %5, %8 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %49) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = extractelement <4 x float> %50, i32 3 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = extractelement <4 x float> %64, i32 2 %68 = fmul float %65, %32 %69 = fadd float %68, %51 %70 = fmul float %66, %32 %71 = fadd float %70, %52 %72 = fmul float %67, %32 %73 = fadd float %72, %53 %74 = fmul float %69, %33 %75 = fmul float %71, %34 %76 = fadd float %74, %75 %77 = fmul float %73, %35 %78 = fadd float %76, %77 %79 = fmul float %54, %36 %80 = fadd float %78, %79 %81 = fmul float %69, %37 %82 = fmul float %71, %38 %83 = fadd float %81, %82 %84 = fmul float %73, %39 %85 = fadd float %83, %84 %86 = fmul float %54, %40 %87 = fadd float %85, %86 %88 = fmul float %69, %41 %89 = fmul float %71, %42 %90 = fadd float %88, %89 %91 = fmul float %73, %43 %92 = fadd float %90, %91 %93 = fmul float %54, %44 %94 = fadd float %92, %93 %95 = fmul float %80, %16 %96 = fmul float %87, %17 %97 = fadd float %95, %96 %98 = fmul float %94, %18 %99 = fadd float %97, %98 %100 = fmul float %14, %19 %101 = fadd float %99, %100 %102 = fmul float %80, %20 %103 = fmul float %87, %21 %104 = fadd float %102, %103 %105 = fmul float %94, %22 %106 = fadd float %104, %105 %107 = fmul float %14, %23 %108 = fadd float %106, %107 %109 = fmul float %80, %24 %110 = fmul float %87, %25 %111 = fadd float %109, %110 %112 = fmul float %94, %26 %113 = fadd float %111, %112 %114 = fmul float %14, %27 %115 = fadd float %113, %114 %116 = fmul float %80, %28 %117 = fmul float %87, %29 %118 = fadd float %116, %117 %119 = fmul float %94, %30 %120 = fadd float %118, %119 %121 = fmul float %14, %31 %122 = fadd float %120, %121 %123 = fmul float %115, %15 %124 = fsub float %123, %122 %125 = fmul float %45, %122 %126 = fadd float %125, %101 %127 = fmul float %46, %122 %128 = fsub float %127, %108 %129 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %130 = load <16 x i8>, <16 x i8> addrspace(2)* %129, align 16, !tbaa !0 %131 = call float @llvm.SI.load.const(<16 x i8> %130, i32 0) %132 = fmul float %131, %101 %133 = call float @llvm.SI.load.const(<16 x i8> %130, i32 4) %134 = fmul float %133, %108 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %130, i32 8) %137 = fmul float %136, %115 %138 = fadd float %135, %137 %139 = call float @llvm.SI.load.const(<16 x i8> %130, i32 12) %140 = fmul float %139, %122 %141 = fadd float %138, %140 %142 = call float @llvm.SI.load.const(<16 x i8> %130, i32 16) %143 = fmul float %142, %101 %144 = call float @llvm.SI.load.const(<16 x i8> %130, i32 20) %145 = fmul float %144, %108 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %130, i32 24) %148 = fmul float %147, %115 %149 = fadd float %146, %148 %150 = call float @llvm.SI.load.const(<16 x i8> %130, i32 28) %151 = fmul float %150, %122 %152 = fadd float %149, %151 %153 = call float @llvm.SI.load.const(<16 x i8> %130, i32 32) %154 = fmul float %153, %101 %155 = call float @llvm.SI.load.const(<16 x i8> %130, i32 36) %156 = fmul float %155, %108 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %130, i32 40) %159 = fmul float %158, %115 %160 = fadd float %157, %159 %161 = call float @llvm.SI.load.const(<16 x i8> %130, i32 44) %162 = fmul float %161, %122 %163 = fadd float %160, %162 %164 = call float @llvm.SI.load.const(<16 x i8> %130, i32 48) %165 = fmul float %164, %101 %166 = call float @llvm.SI.load.const(<16 x i8> %130, i32 52) %167 = fmul float %166, %108 %168 = fadd float %165, %167 %169 = call float @llvm.SI.load.const(<16 x i8> %130, i32 56) %170 = fmul float %169, %115 %171 = fadd float %168, %170 %172 = call float @llvm.SI.load.const(<16 x i8> %130, i32 60) %173 = fmul float %172, %122 %174 = fadd float %171, %173 %175 = call float @llvm.SI.load.const(<16 x i8> %130, i32 64) %176 = fmul float %175, %101 %177 = call float @llvm.SI.load.const(<16 x i8> %130, i32 68) %178 = fmul float %177, %108 %179 = fadd float %176, %178 %180 = call float @llvm.SI.load.const(<16 x i8> %130, i32 72) %181 = fmul float %180, %115 %182 = fadd float %179, %181 %183 = call float @llvm.SI.load.const(<16 x i8> %130, i32 76) %184 = fmul float %183, %122 %185 = fadd float %182, %184 %186 = call float @llvm.SI.load.const(<16 x i8> %130, i32 80) %187 = fmul float %186, %101 %188 = call float @llvm.SI.load.const(<16 x i8> %130, i32 84) %189 = fmul float %188, %108 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %130, i32 88) %192 = fmul float %191, %115 %193 = fadd float %190, %192 %194 = call float @llvm.SI.load.const(<16 x i8> %130, i32 92) %195 = fmul float %194, %122 %196 = fadd float %193, %195 %197 = call float @llvm.SI.load.const(<16 x i8> %130, i32 96) %198 = fmul float %197, %101 %199 = call float @llvm.SI.load.const(<16 x i8> %130, i32 100) %200 = fmul float %199, %108 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %130, i32 104) %203 = fmul float %202, %115 %204 = fadd float %201, %203 %205 = call float @llvm.SI.load.const(<16 x i8> %130, i32 108) %206 = fmul float %205, %122 %207 = fadd float %204, %206 %208 = call float @llvm.SI.load.const(<16 x i8> %130, i32 112) %209 = fmul float %208, %101 %210 = call float @llvm.SI.load.const(<16 x i8> %130, i32 116) %211 = fmul float %210, %108 %212 = fadd float %209, %211 %213 = call float @llvm.SI.load.const(<16 x i8> %130, i32 120) %214 = fmul float %213, %115 %215 = fadd float %212, %214 %216 = call float @llvm.SI.load.const(<16 x i8> %130, i32 124) %217 = fmul float %216, %122 %218 = fadd float %215, %217 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %126, float %128, float %124, float %122) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %141, float %152, float %163, float %174) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %185, float %196, float %207, float %218) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[2:3], 0x100 ; C00A0101 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x0 ; C00A0404 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x10 ; C00A0504 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x20 ; C00A0604 00000020 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[12:15], 0xb4 ; C0220046 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0xb8 ; C0220006 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0xbc ; C0220086 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xd0 ; C02200C6 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0xe0 ; C0220206 000000E0 buffer_load_format_xyzw v[1:4], v0, s[16:19], 0 idxen ; E00C2000 80040100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[20:23], 0 idxen ; E00C2000 80050500 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[7:10], v0, s[24:27], 0 idxen ; E00C2000 80060700 s_buffer_load_dword s9, s[12:15], 0x4 ; C0220246 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x8 ; C0220286 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x80 ; C02202C6 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x84 ; C0220406 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x88 ; C0220446 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x8c ; C0220486 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x90 ; C02204C6 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x94 ; C0220506 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x98 ; C0220546 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x9c ; C0220586 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0xa0 ; C02205C6 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0xa4 ; C0220606 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0xa8 ; C0220646 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0xac ; C0220686 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0xb0 ; C02206C6 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0xe4 ; C0220706 000000E4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0xe8 ; C0220746 000000E8 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0xec ; C0220786 000000EC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0xf0 ; C02207C6 000000F0 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0xf4 ; C0220806 000000F4 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0xf8 ; C0220846 000000F8 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0xfc ; C0220886 000000FC s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x100 ; C02208C6 00000100 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x104 ; C0220906 00000104 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x108 ; C0220946 00000108 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x10c ; C0220986 0000010C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x110 ; C02209C6 00000110 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x114 ; C0220306 00000114 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x0 ; C0220342 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x4 ; C0220382 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x8 ; C02203C2 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[4:7], 0xc ; C0220A02 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[4:7], 0x10 ; C0220A42 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[4:7], 0x14 ; C0220A82 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[4:7], 0x18 ; C0220AC2 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[4:7], 0x1c ; C0220B02 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[4:7], 0x20 ; C0220B42 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[4:7], 0x24 ; C0220B82 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[4:7], 0x28 ; C0220BC2 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[4:7], 0x2c ; C0220C02 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[4:7], 0x30 ; C0220C42 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[4:7], 0x34 ; C0220C82 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[4:7], 0x38 ; C0220CC2 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[4:7], 0x3c ; C0220D02 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[4:7], 0x40 ; C0220D42 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[4:7], 0x44 ; C0220D82 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[4:7], 0x48 ; C0220DC2 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[4:7], 0x4c ; C0220E02 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s57, s[4:7], 0x50 ; C0220E42 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[4:7], 0x54 ; C0220E82 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[4:7], 0x58 ; C0220EC2 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[4:7], 0x5c ; C0220F02 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[4:7], 0x60 ; C0220F42 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[4:7], 0x64 ; C0220F82 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[4:7], 0x68 ; C0220FC2 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[4:7], 0x6c ; C0221002 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s65, s[4:7], 0x70 ; C0221042 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[4:7], 0x74 ; C0221082 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[4:7], 0x78 ; C02210C2 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x7c ; C0220102 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s18 ; 7E000212 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v10, s22 ; 7E140216 v_mov_b32_e32 v11, s26 ; 7E16021A v_mov_b32_e32 v12, s2 ; 7E180202 v_mad_f32 v1, s3, v7, v1 ; D1C10001 04060E03 v_mad_f32 v2, s3, v8, v2 ; D1C10002 040A1003 v_mad_f32 v3, s3, v9, v3 ; D1C10003 040E1203 v_mul_f32_e32 v7, s28, v2 ; 0A0E041C v_mul_f32_e32 v8, s32, v2 ; 0A100420 v_mul_f32_e32 v2, s36, v2 ; 0A040424 v_mac_f32_e32 v7, s8, v1 ; 2C0E0208 v_mac_f32_e32 v8, s31, v1 ; 2C10021F v_mac_f32_e32 v2, s35, v1 ; 2C040223 v_mac_f32_e32 v7, s29, v3 ; 2C0E061D v_mac_f32_e32 v8, s33, v3 ; 2C100621 v_mac_f32_e32 v2, s37, v3 ; 2C040625 v_mac_f32_e32 v7, s30, v4 ; 2C0E081E v_mac_f32_e32 v8, s34, v4 ; 2C100822 v_mac_f32_e32 v2, s38, v4 ; 2C040826 v_mul_f32_e32 v1, s16, v8 ; 0A021010 v_mul_f32_e32 v3, s20, v8 ; 0A061014 v_mul_f32_e32 v4, s24, v8 ; 0A081018 v_mov_b32_e32 v9, 0 ; 7E120280 exp 15, 32, 0, 0, 0, v5, v6, v9, v9 ; C400020F 09090605 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s1, v8 ; 0A0A1001 v_mac_f32_e32 v1, s11, v7 ; 2C020E0B v_mac_f32_e32 v3, s19, v7 ; 2C060E13 v_mac_f32_e32 v4, s23, v7 ; 2C080E17 v_mac_f32_e32 v5, s27, v7 ; 2C0A0E1B v_mac_f32_e32 v1, s17, v2 ; 2C020411 v_mac_f32_e32 v3, s21, v2 ; 2C060415 v_mac_f32_e32 v4, s25, v2 ; 2C080419 v_mac_f32_e32 v5, s0, v2 ; 2C0A0400 v_mac_f32_e32 v1, s9, v0 ; 2C020009 v_mac_f32_e32 v3, s9, v10 ; 2C061409 v_mac_f32_e32 v4, s9, v11 ; 2C081609 v_mac_f32_e32 v5, s9, v12 ; 2C0A1809 v_mad_f32 v0, v4, s10, -v5 ; D1C10000 84141504 v_mad_f32 v2, s39, v5, v1 ; D1C10002 04060A27 v_mad_f32 v6, s12, v5, -v3 ; D1C10006 840E0A0C v_mul_f32_e32 v7, s14, v3 ; 0A0E060E v_mul_f32_e32 v8, s42, v3 ; 0A10062A v_mul_f32_e32 v9, s46, v3 ; 0A12062E v_mul_f32_e32 v10, s50, v3 ; 0A140632 v_mul_f32_e32 v11, s54, v3 ; 0A160636 v_mul_f32_e32 v12, s58, v3 ; 0A18063A v_mul_f32_e32 v13, s62, v3 ; 0A1A063E v_mul_f32_e32 v3, s66, v3 ; 0A060642 v_mac_f32_e32 v7, s13, v1 ; 2C0E020D v_mac_f32_e32 v8, s41, v1 ; 2C100229 v_mac_f32_e32 v9, s45, v1 ; 2C12022D v_mac_f32_e32 v10, s49, v1 ; 2C140231 v_mac_f32_e32 v11, s53, v1 ; 2C160235 v_mac_f32_e32 v12, s57, v1 ; 2C180239 v_mac_f32_e32 v13, s61, v1 ; 2C1A023D v_mac_f32_e32 v3, s65, v1 ; 2C060241 v_mac_f32_e32 v7, s15, v4 ; 2C0E080F v_mac_f32_e32 v8, s43, v4 ; 2C10082B v_mac_f32_e32 v9, s47, v4 ; 2C12082F v_mac_f32_e32 v10, s51, v4 ; 2C140833 v_mac_f32_e32 v11, s55, v4 ; 2C160837 v_mac_f32_e32 v12, s59, v4 ; 2C18083B v_mac_f32_e32 v13, s63, v4 ; 2C1A083F v_mac_f32_e32 v3, s67, v4 ; 2C060843 v_mac_f32_e32 v7, s40, v5 ; 2C0E0A28 v_mac_f32_e32 v8, s44, v5 ; 2C100A2C v_mac_f32_e32 v9, s48, v5 ; 2C120A30 v_mac_f32_e32 v10, s52, v5 ; 2C140A34 v_mac_f32_e32 v11, s56, v5 ; 2C160A38 v_mac_f32_e32 v12, s60, v5 ; 2C180A3C v_mac_f32_e32 v13, s64, v5 ; 2C1A0A40 v_mac_f32_e32 v3, s4, v5 ; 2C060A04 exp 15, 12, 0, 0, 0, v2, v6, v0, v5 ; C40000CF 05000602 exp 15, 13, 0, 0, 0, v7, v8, v9, v10 ; C40000DF 0A090807 exp 15, 14, 0, 1, 0, v11, v12, v13, v3 ; C40008EF 030D0C0B s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 72 VGPRS: 16 Code Size: 1224 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: ADD TEMP[1].xyz, TEMP[0].wwww, -CONST[0].xxxx 3: FSLT TEMP[2].x, TEMP[1].xxxx, IMM[0].xxxx 4: FSLT TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 5: OR TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 6: FSLT TEMP[1].x, TEMP[1].zzzz, IMM[0].xxxx 7: OR TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx 8: AND TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy 9: KILL_IF -TEMP[1].xxxx 10: MOV OUT[0], TEMP[0] 11: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %27 = load <8 x i32>, <8 x i32> addrspace(2)* %26, align 32, !tbaa !0 %28 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %32 = bitcast float %30 to i32 %33 = bitcast float %31 to i32 %34 = insertelement <2 x i32> undef, i32 %32, i32 0 %35 = insertelement <2 x i32> %34, i32 %33, i32 1 %36 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %35, <8 x i32> %27, <4 x i32> %29, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = fsub float %40, %25 %42 = fsub float %40, %25 %43 = fsub float %40, %25 %44 = fcmp olt float %41, 0.000000e+00 %45 = fcmp olt float %42, 0.000000e+00 %46 = or i1 %44, %45 %47 = fcmp olt float %43, 0.000000e+00 %48 = or i1 %46, %47 %49 = select i1 %48, float -1.000000e+00, float 0.000000e+00 call void @llvm.AMDGPU.kill(float %49) %50 = call i32 @llvm.SI.packf16(float %37, float %38) %51 = bitcast i32 %50 to float %52 = call i32 @llvm.SI.packf16(float %39, float %40) %53 = bitcast i32 %52 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.AMDGPU.kill(float) ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[0:3], 0x0 ; C0220000 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800F00 00230002 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_subrev_f32_e32 v4, s0, v3 ; 06080600 v_cmp_gt_f32_e32 vcc, 0, v4 ; 7C880880 v_cndmask_b32_e64 v4, 0, -1.0, vcc ; D1000004 01A9E680 v_cmpx_le_f32_e32 vcc, 0, v4 ; 7CA60880 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 128 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL CONST[0..17] DCL TEMP[0..4], LOCAL 0: MOV TEMP[0].w, IN[0].wwww 1: MAD TEMP[0].xyz, IN[1].xyzz, CONST[13].xxxx, IN[0].xyzz 2: DP4 TEMP[1].x, TEMP[0], CONST[14] 3: DP4 TEMP[2].x, TEMP[0], CONST[15] 4: MOV TEMP[1].y, TEMP[2].xxxx 5: DP4 TEMP[0].x, TEMP[0], CONST[16] 6: MOV TEMP[1].z, TEMP[0].xxxx 7: MOV TEMP[1].w, CONST[0].yyyy 8: DP4 TEMP[0].x, TEMP[1], CONST[8] 9: DP4 TEMP[2].x, TEMP[1], CONST[9] 10: MOV TEMP[0].y, TEMP[2].xxxx 11: DP4 TEMP[3].x, TEMP[1], CONST[10] 12: MOV TEMP[0].z, TEMP[3].xxxx 13: DP4 TEMP[1].x, TEMP[1], CONST[11] 14: MOV TEMP[0].w, TEMP[1].xxxx 15: MOV TEMP[4], TEMP[0] 16: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[1].xxxx 17: MOV TEMP[0].z, TEMP[3].xxxx 18: MOV TEMP[0].y, -TEMP[2].xxxx 19: MAD TEMP[0].xy, CONST[17].xyyy, TEMP[1].xxxx, TEMP[0].xyyy 20: MOV OUT[0], TEMP[0] 21: MOV OUT[1], TEMP[4] 22: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 224) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 228) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 232) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 236) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 240) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 244) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 248) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 252) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 256) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 260) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 264) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 268) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 272) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 276) %47 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %48 = load <16 x i8>, <16 x i8> addrspace(2)* %47, align 16, !tbaa !0 %49 = add i32 %5, %8 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %49) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = extractelement <4 x float> %50, i32 3 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = fmul float %59, %32 %63 = fadd float %62, %51 %64 = fmul float %60, %32 %65 = fadd float %64, %52 %66 = fmul float %61, %32 %67 = fadd float %66, %53 %68 = fmul float %63, %33 %69 = fmul float %65, %34 %70 = fadd float %68, %69 %71 = fmul float %67, %35 %72 = fadd float %70, %71 %73 = fmul float %54, %36 %74 = fadd float %72, %73 %75 = fmul float %63, %37 %76 = fmul float %65, %38 %77 = fadd float %75, %76 %78 = fmul float %67, %39 %79 = fadd float %77, %78 %80 = fmul float %54, %40 %81 = fadd float %79, %80 %82 = fmul float %63, %41 %83 = fmul float %65, %42 %84 = fadd float %82, %83 %85 = fmul float %67, %43 %86 = fadd float %84, %85 %87 = fmul float %54, %44 %88 = fadd float %86, %87 %89 = fmul float %74, %16 %90 = fmul float %81, %17 %91 = fadd float %89, %90 %92 = fmul float %88, %18 %93 = fadd float %91, %92 %94 = fmul float %14, %19 %95 = fadd float %93, %94 %96 = fmul float %74, %20 %97 = fmul float %81, %21 %98 = fadd float %96, %97 %99 = fmul float %88, %22 %100 = fadd float %98, %99 %101 = fmul float %14, %23 %102 = fadd float %100, %101 %103 = fmul float %74, %24 %104 = fmul float %81, %25 %105 = fadd float %103, %104 %106 = fmul float %88, %26 %107 = fadd float %105, %106 %108 = fmul float %14, %27 %109 = fadd float %107, %108 %110 = fmul float %74, %28 %111 = fmul float %81, %29 %112 = fadd float %110, %111 %113 = fmul float %88, %30 %114 = fadd float %112, %113 %115 = fmul float %14, %31 %116 = fadd float %114, %115 %117 = fmul float %109, %15 %118 = fsub float %117, %116 %119 = fmul float %45, %116 %120 = fadd float %119, %95 %121 = fmul float %46, %116 %122 = fsub float %121, %102 %123 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %124 = load <16 x i8>, <16 x i8> addrspace(2)* %123, align 16, !tbaa !0 %125 = call float @llvm.SI.load.const(<16 x i8> %124, i32 0) %126 = fmul float %125, %95 %127 = call float @llvm.SI.load.const(<16 x i8> %124, i32 4) %128 = fmul float %127, %102 %129 = fadd float %126, %128 %130 = call float @llvm.SI.load.const(<16 x i8> %124, i32 8) %131 = fmul float %130, %109 %132 = fadd float %129, %131 %133 = call float @llvm.SI.load.const(<16 x i8> %124, i32 12) %134 = fmul float %133, %116 %135 = fadd float %132, %134 %136 = call float @llvm.SI.load.const(<16 x i8> %124, i32 16) %137 = fmul float %136, %95 %138 = call float @llvm.SI.load.const(<16 x i8> %124, i32 20) %139 = fmul float %138, %102 %140 = fadd float %137, %139 %141 = call float @llvm.SI.load.const(<16 x i8> %124, i32 24) %142 = fmul float %141, %109 %143 = fadd float %140, %142 %144 = call float @llvm.SI.load.const(<16 x i8> %124, i32 28) %145 = fmul float %144, %116 %146 = fadd float %143, %145 %147 = call float @llvm.SI.load.const(<16 x i8> %124, i32 32) %148 = fmul float %147, %95 %149 = call float @llvm.SI.load.const(<16 x i8> %124, i32 36) %150 = fmul float %149, %102 %151 = fadd float %148, %150 %152 = call float @llvm.SI.load.const(<16 x i8> %124, i32 40) %153 = fmul float %152, %109 %154 = fadd float %151, %153 %155 = call float @llvm.SI.load.const(<16 x i8> %124, i32 44) %156 = fmul float %155, %116 %157 = fadd float %154, %156 %158 = call float @llvm.SI.load.const(<16 x i8> %124, i32 48) %159 = fmul float %158, %95 %160 = call float @llvm.SI.load.const(<16 x i8> %124, i32 52) %161 = fmul float %160, %102 %162 = fadd float %159, %161 %163 = call float @llvm.SI.load.const(<16 x i8> %124, i32 56) %164 = fmul float %163, %109 %165 = fadd float %162, %164 %166 = call float @llvm.SI.load.const(<16 x i8> %124, i32 60) %167 = fmul float %166, %116 %168 = fadd float %165, %167 %169 = call float @llvm.SI.load.const(<16 x i8> %124, i32 64) %170 = fmul float %169, %95 %171 = call float @llvm.SI.load.const(<16 x i8> %124, i32 68) %172 = fmul float %171, %102 %173 = fadd float %170, %172 %174 = call float @llvm.SI.load.const(<16 x i8> %124, i32 72) %175 = fmul float %174, %109 %176 = fadd float %173, %175 %177 = call float @llvm.SI.load.const(<16 x i8> %124, i32 76) %178 = fmul float %177, %116 %179 = fadd float %176, %178 %180 = call float @llvm.SI.load.const(<16 x i8> %124, i32 80) %181 = fmul float %180, %95 %182 = call float @llvm.SI.load.const(<16 x i8> %124, i32 84) %183 = fmul float %182, %102 %184 = fadd float %181, %183 %185 = call float @llvm.SI.load.const(<16 x i8> %124, i32 88) %186 = fmul float %185, %109 %187 = fadd float %184, %186 %188 = call float @llvm.SI.load.const(<16 x i8> %124, i32 92) %189 = fmul float %188, %116 %190 = fadd float %187, %189 %191 = call float @llvm.SI.load.const(<16 x i8> %124, i32 96) %192 = fmul float %191, %95 %193 = call float @llvm.SI.load.const(<16 x i8> %124, i32 100) %194 = fmul float %193, %102 %195 = fadd float %192, %194 %196 = call float @llvm.SI.load.const(<16 x i8> %124, i32 104) %197 = fmul float %196, %109 %198 = fadd float %195, %197 %199 = call float @llvm.SI.load.const(<16 x i8> %124, i32 108) %200 = fmul float %199, %116 %201 = fadd float %198, %200 %202 = call float @llvm.SI.load.const(<16 x i8> %124, i32 112) %203 = fmul float %202, %95 %204 = call float @llvm.SI.load.const(<16 x i8> %124, i32 116) %205 = fmul float %204, %102 %206 = fadd float %203, %205 %207 = call float @llvm.SI.load.const(<16 x i8> %124, i32 120) %208 = fmul float %207, %109 %209 = fadd float %206, %208 %210 = call float @llvm.SI.load.const(<16 x i8> %124, i32 124) %211 = fmul float %210, %116 %212 = fadd float %209, %211 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %120, float %122, float %118, float %116) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %135, float %146, float %157, float %168) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %179, float %190, float %201, float %212) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[1:4], v0, s[4:7], 0 idxen ; E00C2000 80010100 s_nop 0 ; BF800000 buffer_load_format_xyzw v[5:8], v0, s[12:15], 0 idxen ; E00C2000 80030500 s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s8, s[4:7], 0x4 ; C0220202 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x8 ; C0220242 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x80 ; C0220282 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x84 ; C02202C2 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x88 ; C0220302 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x8c ; C0220342 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x90 ; C0220382 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x94 ; C02203C2 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x98 ; C0220402 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x9c ; C0220442 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0xa0 ; C0220482 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0xa4 ; C02204C2 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0xa8 ; C0220502 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0xac ; C0220542 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0xb0 ; C0220582 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0xb4 ; C02205C2 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0xb8 ; C0220602 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0xbc ; C0220642 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0xd0 ; C0220682 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0xe0 ; C02206C2 000000E0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0xe4 ; C0220702 000000E4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0xe8 ; C0220742 000000E8 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0xec ; C0220782 000000EC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0xf0 ; C02207C2 000000F0 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0xf4 ; C0220802 000000F4 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0xf8 ; C0220842 000000F8 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0xfc ; C0220882 000000FC s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x100 ; C02208C2 00000100 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x104 ; C0220902 00000104 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x108 ; C0220942 00000108 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[4:7], 0x10c ; C0220982 0000010C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[4:7], 0x110 ; C02209C2 00000110 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x114 ; C0220102 00000114 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0xc ; C0220A00 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x10 ; C0220A40 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x14 ; C0220A80 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x18 ; C0220AC0 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x1c ; C0220B00 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x20 ; C0220B40 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x24 ; C0220B80 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x28 ; C0220BC0 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x2c ; C0220C00 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x30 ; C0220C40 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[0:3], 0x34 ; C0220C80 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[0:3], 0x38 ; C0220CC0 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s52, s[0:3], 0x3c ; C0220D00 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s53, s[0:3], 0x40 ; C0220D40 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[0:3], 0x44 ; C0220D80 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s55, s[0:3], 0x48 ; C0220DC0 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s56, s[0:3], 0x4c ; C0220E00 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s57, s[0:3], 0x50 ; C0220E40 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[0:3], 0x54 ; C0220E80 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[0:3], 0x58 ; C0220EC0 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[0:3], 0x5c ; C0220F00 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[0:3], 0x60 ; C0220F40 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[0:3], 0x64 ; C0220F80 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[0:3], 0x68 ; C0220FC0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[0:3], 0x6c ; C0221000 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s65, s[0:3], 0x70 ; C0221040 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[0:3], 0x74 ; C0221080 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[0:3], 0x78 ; C02210C0 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s13 ; 7E00020D s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v8, s17 ; 7E100211 v_mov_b32_e32 v9, s21 ; 7E120215 v_mov_b32_e32 v10, s25 ; 7E140219 v_mad_f32 v1, s26, v5, v1 ; D1C10001 04060A1A v_mad_f32 v2, s26, v6, v2 ; D1C10002 040A0C1A v_mad_f32 v3, s26, v7, v3 ; D1C10003 040E0E1A v_mul_f32_e32 v5, s28, v2 ; 0A0A041C v_mul_f32_e32 v6, s32, v2 ; 0A0C0420 v_mul_f32_e32 v2, s36, v2 ; 0A040424 v_mac_f32_e32 v5, s27, v1 ; 2C0A021B v_mac_f32_e32 v6, s31, v1 ; 2C0C021F v_mac_f32_e32 v2, s35, v1 ; 2C040223 v_mac_f32_e32 v5, s29, v3 ; 2C0A061D v_mac_f32_e32 v6, s33, v3 ; 2C0C0621 v_mac_f32_e32 v2, s37, v3 ; 2C040625 v_mac_f32_e32 v5, s30, v4 ; 2C0A081E v_mac_f32_e32 v6, s34, v4 ; 2C0C0822 v_mac_f32_e32 v2, s38, v4 ; 2C040826 v_mul_f32_e32 v1, s11, v6 ; 0A020C0B v_mul_f32_e32 v3, s15, v6 ; 0A060C0F v_mul_f32_e32 v4, s19, v6 ; 0A080C13 v_mul_f32_e32 v6, s23, v6 ; 0A0C0C17 v_mac_f32_e32 v1, s10, v5 ; 2C020A0A v_mac_f32_e32 v3, s14, v5 ; 2C060A0E v_mac_f32_e32 v4, s18, v5 ; 2C080A12 v_mac_f32_e32 v6, s22, v5 ; 2C0C0A16 v_mac_f32_e32 v1, s12, v2 ; 2C02040C v_mac_f32_e32 v3, s16, v2 ; 2C060410 v_mac_f32_e32 v4, s20, v2 ; 2C080414 v_mac_f32_e32 v6, s24, v2 ; 2C0C0418 v_mac_f32_e32 v1, s8, v0 ; 2C020008 v_mac_f32_e32 v3, s8, v8 ; 2C061008 v_mac_f32_e32 v4, s8, v9 ; 2C081208 v_mac_f32_e32 v6, s8, v10 ; 2C0C1408 v_mad_f32 v0, v4, s9, -v6 ; D1C10000 84181304 v_mad_f32 v2, s39, v6, v1 ; D1C10002 04060C27 v_mad_f32 v5, s4, v6, -v3 ; D1C10005 840E0C04 v_mul_f32_e32 v7, s6, v3 ; 0A0E0606 v_mul_f32_e32 v8, s42, v3 ; 0A10062A v_mul_f32_e32 v9, s46, v3 ; 0A12062E v_mul_f32_e32 v10, s50, v3 ; 0A140632 v_mul_f32_e32 v11, s54, v3 ; 0A160636 v_mul_f32_e32 v12, s58, v3 ; 0A18063A v_mul_f32_e32 v13, s62, v3 ; 0A1A063E v_mul_f32_e32 v3, s66, v3 ; 0A060642 v_mac_f32_e32 v7, s5, v1 ; 2C0E0205 v_mac_f32_e32 v8, s41, v1 ; 2C100229 v_mac_f32_e32 v9, s45, v1 ; 2C12022D v_mac_f32_e32 v10, s49, v1 ; 2C140231 v_mac_f32_e32 v11, s53, v1 ; 2C160235 v_mac_f32_e32 v12, s57, v1 ; 2C180239 v_mac_f32_e32 v13, s61, v1 ; 2C1A023D v_mac_f32_e32 v3, s65, v1 ; 2C060241 v_mac_f32_e32 v7, s7, v4 ; 2C0E0807 v_mac_f32_e32 v8, s43, v4 ; 2C10082B v_mac_f32_e32 v9, s47, v4 ; 2C12082F v_mac_f32_e32 v10, s51, v4 ; 2C140833 v_mac_f32_e32 v11, s55, v4 ; 2C160837 v_mac_f32_e32 v12, s59, v4 ; 2C18083B v_mac_f32_e32 v13, s63, v4 ; 2C1A083F v_mac_f32_e32 v3, s67, v4 ; 2C060843 v_mac_f32_e32 v7, s40, v6 ; 2C0E0C28 v_mac_f32_e32 v8, s44, v6 ; 2C100C2C v_mac_f32_e32 v9, s48, v6 ; 2C120C30 v_mac_f32_e32 v10, s52, v6 ; 2C140C34 v_mac_f32_e32 v11, s56, v6 ; 2C160C38 v_mac_f32_e32 v12, s60, v6 ; 2C180C3C v_mac_f32_e32 v13, s64, v6 ; 2C1A0C40 v_mac_f32_e32 v3, s0, v6 ; 2C060C00 exp 15, 12, 0, 0, 0, v2, v5, v0, v6 ; C40000CF 06000502 exp 15, 13, 0, 0, 0, v7, v8, v9, v10 ; C40000DF 0A090807 exp 15, 14, 0, 1, 0, v11, v12, v13, v3 ; C40008EF 030D0C0B s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 72 VGPRS: 16 Code Size: 1188 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL OUT[0], COLOR IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xyyx 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 0.000000e+00) %24 = bitcast i32 %23 to float %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00) %26 = bitcast i32 %25 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %24, float %26, float %24, float %26) ret void } ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: v_cvt_pkrtz_f16_f32_e64 v0, 1.0, 0 ; D2960000 000100F2 v_cvt_pkrtz_f16_f32_e64 v1, 0, 1.0 ; D2960001 0001E480 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 28 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[0] DCL CONST[0..61] DCL TEMP[0..11], LOCAL IMM[0] FLT32 { 0.0000, 19.0000, 0.2500, 6.2832} IMM[1] FLT32 { 0.1592, 0.3676, 0.3406, -3.1416} IMM[2] FLT32 { -0.0000, 0.0000, -0.0014, 0.0417} IMM[3] FLT32 { -2.0000, 3.0000, 0.1000, 0.4000} IMM[4] FLT32 { 0.0001, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].x, CONST[58].wwww 2: MOV TEMP[1].y, CONST[59].wwww 3: MOV TEMP[1].z, CONST[60].wwww 4: DP3 TEMP[2].x, TEMP[1].xyzz, CONST[0].yyyy 5: MAD TEMP[3].x, TEMP[2].xxxx, IMM[0].yyyy, CONST[50].xxxx 6: MUL TEMP[3].xy, TEMP[3].xxxx, CONST[53].xxxx 7: MUL TEMP[4].xy, TEMP[3].yyyy, CONST[51].wwww 8: MOV TEMP[3].zw, TEMP[4].yyxy 9: MAD TEMP[3], TEMP[3], IMM[1].xyxz, IMM[0].zzzz 10: FRC TEMP[4], TEMP[3] 11: MAD TEMP[3], TEMP[4], IMM[0].wwww, IMM[1].wwww 12: MUL TEMP[3], TEMP[3], TEMP[3] 13: MAD TEMP[4], TEMP[3], IMM[2].xxxx, IMM[2].yyyy 14: MAD TEMP[4], TEMP[3], TEMP[4], IMM[2].zzzz 15: MAD TEMP[4], TEMP[3], TEMP[4], IMM[2].wwww 16: MAD TEMP[4], TEMP[3], TEMP[4], -CONST[0].wwww 17: MAD TEMP[3], TEMP[3], TEMP[4], CONST[0].yyyy 18: MUL TEMP[5].xy, CONST[50].yzzz, CONST[50].yzzz 19: ADD TEMP[5].x, TEMP[5].yyyy, TEMP[5].xxxx 20: SQRT TEMP[5].x, TEMP[5].xxxx 21: ADD TEMP[6].x, TEMP[5].xxxx, -CONST[57].xxxx 22: ADD TEMP[7].x, -CONST[57].xxxx, CONST[57].yyyy 23: RCP TEMP[7].x, TEMP[7].xxxx 24: MUL TEMP[6].x, TEMP[7].xxxx, TEMP[6].xxxx 25: MOV_SAT TEMP[6].x, TEMP[6].xxxx 26: MAD TEMP[7].x, TEMP[6].xxxx, IMM[3].xxxx, IMM[3].yyyy 27: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[6].xxxx 28: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx 29: LRP TEMP[4].xy, TEMP[6].xxxx, TEMP[3].zwww, TEMP[3].xyyy 30: ADD TEMP[6].xy, TEMP[4].xyyy, IMM[3].zwww 31: MUL TEMP[3].xyz, CONST[50].zzzz, CONST[59].xyzz 32: MAD TEMP[7].xyz, CONST[58].xyzz, CONST[50].yyyy, TEMP[3].xyzz 33: DP3 TEMP[3].x, TEMP[7].xyzz, TEMP[7].xyzz 34: SQRT TEMP[3].x, TEMP[3].xxxx 35: MAD TEMP[4].xyz, IN[2].xyzz, CONST[13].xxxx, IN[0].xyzz 36: MUL TEMP[8].xy, TEMP[4].xyyy, TEMP[4].xyyy 37: ADD TEMP[8].x, TEMP[8].yyyy, TEMP[8].xxxx 38: SQRT TEMP[8].x, TEMP[8].xxxx 39: MOV TEMP[3].y, TEMP[8].xxxx 40: MAX TEMP[8].xy, TEMP[3].xyyy, IMM[4].xxxx 41: MUL TEMP[3].x, TEMP[8].yyyy, TEMP[8].xxxx 42: RCP TEMP[3].x, TEMP[3].xxxx 43: MOV TEMP[4].w, CONST[0].xxxx 44: DP3 TEMP[8].x, TEMP[7].xyzz, TEMP[4].xyww 45: ABS TEMP[8].x, TEMP[8].xxxx 46: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx 47: MIN TEMP[8].x, TEMP[3].xxxx, CONST[0].yyyy 48: ADD TEMP[3].x, -TEMP[8].xxxx, CONST[0].yyyy 49: MUL TEMP[3].x, TEMP[3].xxxx, CONST[53].yyyy 50: ADD TEMP[8].xy, CONST[0].yyyy, -CONST[52].ywww 51: MUL TEMP[8].xy, TEMP[8].xyyy, CONST[52].xzzz 52: RCP TEMP[9].x, TEMP[8].yyyy 53: RCP TEMP[8].x, TEMP[8].xxxx 54: MAD TEMP[10].xyz, CONST[52].xzzz, -CONST[52].ywww, TEMP[4].zxyy 55: MUL TEMP[11].xy, TEMP[10].yzzz, TEMP[10].yzzz 56: ADD TEMP[11].x, TEMP[11].yyyy, TEMP[11].xxxx 57: SQRT TEMP[11].x, TEMP[11].xxxx 58: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[11].xxxx 59: MOV_SAT TEMP[9].x, TEMP[9].xxxx 60: MUL TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx 61: POW TEMP[9].x, TEMP[9].xxxx, CONST[51].xxxx 62: MUL TEMP[9].x, TEMP[9].xxxx, CONST[53].wwww 63: MOV TEMP[3].z, TEMP[9].xxxx 64: FSGE TEMP[9].x, TEMP[10].xxxx, CONST[0].xxxx 65: AND TEMP[9].x, TEMP[9].xxxx, IMM[4].yyyy 66: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[10].xxxx 67: MOV_SAT TEMP[8].x, TEMP[8].xxxx 68: POW TEMP[8].x, TEMP[8].xxxx, CONST[51].yyyy 69: MUL TEMP[8].x, TEMP[8].xxxx, CONST[53].yyyy 70: MUL TEMP[10].xyz, TEMP[7].xyzz, TEMP[8].xxxx 71: MUL TEMP[3].xy, TEMP[9].xxxx, TEMP[3].xzzz 72: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[3].xxxx 73: MUL TEMP[7].xyz, TEMP[6].yyyy, TEMP[7].xyzz 74: MAD TEMP[6].xyz, TEMP[10].xyzz, TEMP[6].xxxx, TEMP[7].xyzz 75: DP3 TEMP[7].x, TEMP[4].xyzz, TEMP[4].xyzz 76: RSQ TEMP[7].x, TEMP[7].xxxx 77: MUL TEMP[7].xyz, TEMP[7].xxxx, TEMP[4].yzxx 78: MUL TEMP[7].xyz, TEMP[7].xyzz, CONST[53].zzzz 79: MAD TEMP[7].xyz, CONST[51].zzzz, CONST[50].xxxx, TEMP[7].xyzz 80: MAD TEMP[7].xyz, TEMP[2].xxxx, IMM[0].yyyy, TEMP[7].xyzz 81: MAD TEMP[7].xyz, TEMP[7].xyzz, IMM[1].xxxx, IMM[0].zzzz 82: FRC TEMP[7].xyz, TEMP[7].xyzz 83: MAD TEMP[7].xyz, TEMP[7].xyzz, IMM[0].wwww, IMM[1].wwww 84: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[7].xyzz 85: MAD TEMP[8].xyz, TEMP[7].xyzz, IMM[2].xxxx, IMM[2].yyyy 86: MAD TEMP[8].xyz, TEMP[7].xyzz, TEMP[8].xyzz, IMM[2].zzzz 87: MAD TEMP[8].xyz, TEMP[7].xyzz, TEMP[8].xyzz, IMM[2].wwww 88: MAD TEMP[8].xyz, TEMP[7].xyzz, TEMP[8].xyzz, -CONST[0].wwww 89: MAD TEMP[7].xyz, TEMP[7].xyzz, TEMP[8].xyzz, CONST[0].yyyy 90: MUL TEMP[3].xyz, TEMP[7].xyzz, TEMP[3].yyyy 91: MAD TEMP[1].xyz, TEMP[5].xxxx, TEMP[3].xyzz, TEMP[6].xyzz 92: ADD TEMP[1].xyz, TEMP[1].xyzz, TEMP[4].xyzz 93: MOV TEMP[1].w, IN[0].wwww 94: DP4 TEMP[2].x, TEMP[1], CONST[58] 95: DP4 TEMP[3].x, TEMP[1], CONST[59] 96: MOV TEMP[2].y, TEMP[3].xxxx 97: DP4 TEMP[1].x, TEMP[1], CONST[60] 98: MOV TEMP[2].z, TEMP[1].xxxx 99: MOV TEMP[2].w, CONST[0].yyyy 100: DP4 TEMP[1].x, TEMP[2], CONST[8] 101: DP4 TEMP[3].x, TEMP[2], CONST[9] 102: MOV TEMP[1].y, TEMP[3].xxxx 103: DP4 TEMP[4].x, TEMP[2], CONST[10] 104: MOV TEMP[1].z, TEMP[4].xxxx 105: DP4 TEMP[2].x, TEMP[2], CONST[11] 106: MOV TEMP[1].w, TEMP[2].xxxx 107: MOV TEMP[0].xy, IN[1].xyxx 108: MOV TEMP[5], TEMP[1] 109: MAD TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz, -TEMP[2].xxxx 110: MOV TEMP[1].z, TEMP[4].xxxx 111: MOV TEMP[1].y, -TEMP[3].xxxx 112: MAD TEMP[1].xy, CONST[61].xyyy, TEMP[2].xxxx, TEMP[1].xyyy 113: MOV OUT[2], TEMP[0] 114: MOV OUT[0], TEMP[1] 115: MOV OUT[1], TEMP[5] 116: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 824) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 840) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 856) %49 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %50 = call float @llvm.SI.load.const(<16 x i8> %13, i32 912) %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 916) %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 928) %53 = call float @llvm.SI.load.const(<16 x i8> %13, i32 932) %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 936) %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 940) %56 = call float @llvm.SI.load.const(<16 x i8> %13, i32 944) %57 = call float @llvm.SI.load.const(<16 x i8> %13, i32 948) %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 952) %59 = call float @llvm.SI.load.const(<16 x i8> %13, i32 956) %60 = call float @llvm.SI.load.const(<16 x i8> %13, i32 960) %61 = call float @llvm.SI.load.const(<16 x i8> %13, i32 964) %62 = call float @llvm.SI.load.const(<16 x i8> %13, i32 968) %63 = call float @llvm.SI.load.const(<16 x i8> %13, i32 972) %64 = call float @llvm.SI.load.const(<16 x i8> %13, i32 976) %65 = call float @llvm.SI.load.const(<16 x i8> %13, i32 980) %66 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %67 = load <16 x i8>, <16 x i8> addrspace(2)* %66, align 16, !tbaa !0 %68 = add i32 %5, %8 %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %68) %70 = extractelement <4 x float> %69, i32 0 %71 = extractelement <4 x float> %69, i32 1 %72 = extractelement <4 x float> %69, i32 2 %73 = extractelement <4 x float> %69, i32 3 %74 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %75 = load <16 x i8>, <16 x i8> addrspace(2)* %74, align 16, !tbaa !0 %76 = add i32 %5, %8 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %76) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %81 = load <16 x i8>, <16 x i8> addrspace(2)* %80, align 16, !tbaa !0 %82 = add i32 %5, %8 %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %82) %84 = extractelement <4 x float> %83, i32 0 %85 = extractelement <4 x float> %83, i32 1 %86 = extractelement <4 x float> %83, i32 2 %87 = fmul float %55, %15 %88 = fmul float %59, %15 %89 = fadd float %88, %87 %90 = fmul float %63, %15 %91 = fadd float %89, %90 %92 = fmul float %91, 1.900000e+01 %93 = fadd float %92, %35 %94 = fmul float %93, %46 %95 = fmul float %93, %46 %96 = fmul float %95, %41 %97 = fmul float %95, %41 %98 = fmul float %94, 0x3FC45F3060000000 %99 = fadd float %98, 2.500000e-01 %100 = fmul float %95, 0x3FD7878B20000000 %101 = fadd float %100, 2.500000e-01 %102 = fmul float %96, 0x3FC45F3060000000 %103 = fadd float %102, 2.500000e-01 %104 = fmul float %97, 0x3FD5CC40A0000000 %105 = fadd float %104, 2.500000e-01 %106 = call float @llvm.floor.f32(float %99) %107 = fsub float %99, %106 %108 = call float @llvm.floor.f32(float %101) %109 = fsub float %101, %108 %110 = call float @llvm.floor.f32(float %103) %111 = fsub float %103, %110 %112 = call float @llvm.floor.f32(float %105) %113 = fsub float %105, %112 %114 = fmul float %107, 0x401921FB60000000 %115 = fadd float %114, 0xC00921FB60000000 %116 = fmul float %109, 0x401921FB60000000 %117 = fadd float %116, 0xC00921FB60000000 %118 = fmul float %111, 0x401921FB60000000 %119 = fadd float %118, 0xC00921FB60000000 %120 = fmul float %113, 0x401921FB60000000 %121 = fadd float %120, 0xC00921FB60000000 %122 = fmul float %115, %115 %123 = fmul float %117, %117 %124 = fmul float %119, %119 %125 = fmul float %121, %121 %126 = fmul float %122, 0xBE90F02E80000000 %127 = fadd float %126, 0x3EF9F6B420000000 %128 = fmul float %123, 0xBE90F02E80000000 %129 = fadd float %128, 0x3EF9F6B420000000 %130 = fmul float %124, 0xBE90F02E80000000 %131 = fadd float %130, 0x3EF9F6B420000000 %132 = fmul float %125, 0xBE90F02E80000000 %133 = fadd float %132, 0x3EF9F6B420000000 %134 = fmul float %122, %127 %135 = fadd float %134, 0xBF56C13740000000 %136 = fmul float %123, %129 %137 = fadd float %136, 0xBF56C13740000000 %138 = fmul float %124, %131 %139 = fadd float %138, 0xBF56C13740000000 %140 = fmul float %125, %133 %141 = fadd float %140, 0xBF56C13740000000 %142 = fmul float %122, %135 %143 = fadd float %142, 0x3FA5555480000000 %144 = fmul float %123, %137 %145 = fadd float %144, 0x3FA5555480000000 %146 = fmul float %124, %139 %147 = fadd float %146, 0x3FA5555480000000 %148 = fmul float %125, %141 %149 = fadd float %148, 0x3FA5555480000000 %150 = fmul float %122, %143 %151 = fsub float %150, %17 %152 = fmul float %123, %145 %153 = fsub float %152, %17 %154 = fmul float %124, %147 %155 = fsub float %154, %17 %156 = fmul float %125, %149 %157 = fsub float %156, %17 %158 = fmul float %122, %151 %159 = fadd float %158, %15 %160 = fmul float %123, %153 %161 = fadd float %160, %15 %162 = fmul float %124, %155 %163 = fadd float %162, %15 %164 = fmul float %125, %157 %165 = fadd float %164, %15 %166 = fmul float %36, %36 %167 = fmul float %37, %37 %168 = fadd float %167, %166 %169 = call float @llvm.sqrt.f32(float %168) %170 = fsub float %169, %50 %171 = fsub float %51, %50 %172 = fdiv float 1.000000e+00, %171 %173 = fmul float %172, %170 %174 = call float @llvm.AMDIL.clamp.(float %173, float 0.000000e+00, float 1.000000e+00) %175 = fmul float %174, -2.000000e+00 %176 = fadd float %175, 3.000000e+00 %177 = fmul float %174, %174 %178 = fmul float %177, %176 %179 = fsub float 1.000000e+00, %178 %180 = fmul float %163, %178 %181 = fmul float %159, %179 %182 = fadd float %180, %181 %183 = fsub float 1.000000e+00, %178 %184 = fmul float %165, %178 %185 = fmul float %161, %183 %186 = fadd float %184, %185 %187 = fadd float %182, 0x3FB99999A0000000 %188 = fadd float %186, 0x3FD99999A0000000 %189 = fmul float %37, %56 %190 = fmul float %37, %57 %191 = fmul float %37, %58 %192 = fmul float %52, %36 %193 = fadd float %192, %189 %194 = fmul float %53, %36 %195 = fadd float %194, %190 %196 = fmul float %54, %36 %197 = fadd float %196, %191 %198 = fmul float %193, %193 %199 = fmul float %195, %195 %200 = fadd float %199, %198 %201 = fmul float %197, %197 %202 = fadd float %200, %201 %203 = call float @llvm.sqrt.f32(float %202) %204 = fmul float %84, %34 %205 = fadd float %204, %70 %206 = fmul float %85, %34 %207 = fadd float %206, %71 %208 = fmul float %86, %34 %209 = fadd float %208, %72 %210 = fmul float %205, %205 %211 = fmul float %207, %207 %212 = fadd float %211, %210 %213 = call float @llvm.sqrt.f32(float %212) %214 = call float @llvm.maxnum.f32(float %203, float 0x3F1A36E2E0000000) %215 = call float @llvm.maxnum.f32(float %213, float 0x3F1A36E2E0000000) %216 = fmul float %215, %214 %217 = fdiv float 1.000000e+00, %216 %218 = fmul float %193, %205 %219 = fmul float %195, %207 %220 = fadd float %219, %218 %221 = fmul float %197, %14 %222 = fadd float %220, %221 %223 = call float @llvm.fabs.f32(float %222) %224 = fmul float %217, %223 %225 = call float @llvm.minnum.f32(float %224, float %15) %226 = fsub float %15, %225 %227 = fmul float %226, %47 %228 = fsub float %15, %43 %229 = fsub float %15, %45 %230 = fmul float %228, %42 %231 = fmul float %229, %44 %232 = fdiv float 1.000000e+00, %231 %233 = fdiv float 1.000000e+00, %230 %234 = fmul float %43, %42 %235 = fsub float %209, %234 %236 = fmul float %45, %44 %237 = fsub float %205, %236 %238 = fmul float %45, %44 %239 = fsub float %207, %238 %240 = fmul float %237, %237 %241 = fmul float %239, %239 %242 = fadd float %241, %240 %243 = call float @llvm.sqrt.f32(float %242) %244 = fmul float %232, %243 %245 = call float @llvm.AMDIL.clamp.(float %244, float 0.000000e+00, float 1.000000e+00) %246 = fmul float %245, %227 %247 = call float @llvm.pow.f32(float %245, float %38) %248 = fmul float %247, %49 %249 = fcmp oge float %235, %14 %250 = select i1 %249, float 1.000000e+00, float 0.000000e+00 %251 = fmul float %233, %235 %252 = call float @llvm.AMDIL.clamp.(float %251, float 0.000000e+00, float 1.000000e+00) %253 = call float @llvm.pow.f32(float %252, float %39) %254 = fmul float %253, %47 %255 = fmul float %193, %254 %256 = fmul float %195, %254 %257 = fmul float %197, %254 %258 = fmul float %250, %246 %259 = fmul float %250, %248 %260 = fmul float %193, %258 %261 = fmul float %195, %258 %262 = fmul float %197, %258 %263 = fmul float %188, %260 %264 = fmul float %188, %261 %265 = fmul float %188, %262 %266 = fmul float %255, %187 %267 = fadd float %266, %263 %268 = fmul float %256, %187 %269 = fadd float %268, %264 %270 = fmul float %257, %187 %271 = fadd float %270, %265 %272 = fmul float %205, %205 %273 = fmul float %207, %207 %274 = fadd float %273, %272 %275 = fmul float %209, %209 %276 = fadd float %274, %275 %277 = call float @llvm.AMDGPU.rsq.clamped.f32(float %276) %278 = fmul float %277, %207 %279 = fmul float %277, %209 %280 = fmul float %277, %205 %281 = fmul float %278, %48 %282 = fmul float %279, %48 %283 = fmul float %280, %48 %284 = fmul float %40, %35 %285 = fadd float %284, %281 %286 = fmul float %40, %35 %287 = fadd float %286, %282 %288 = fmul float %40, %35 %289 = fadd float %288, %283 %290 = fmul float %91, 1.900000e+01 %291 = fadd float %290, %285 %292 = fmul float %91, 1.900000e+01 %293 = fadd float %292, %287 %294 = fmul float %91, 1.900000e+01 %295 = fadd float %294, %289 %296 = fmul float %291, 0x3FC45F3060000000 %297 = fadd float %296, 2.500000e-01 %298 = fmul float %293, 0x3FC45F3060000000 %299 = fadd float %298, 2.500000e-01 %300 = fmul float %295, 0x3FC45F3060000000 %301 = fadd float %300, 2.500000e-01 %302 = call float @llvm.floor.f32(float %297) %303 = fsub float %297, %302 %304 = call float @llvm.floor.f32(float %299) %305 = fsub float %299, %304 %306 = call float @llvm.floor.f32(float %301) %307 = fsub float %301, %306 %308 = fmul float %303, 0x401921FB60000000 %309 = fadd float %308, 0xC00921FB60000000 %310 = fmul float %305, 0x401921FB60000000 %311 = fadd float %310, 0xC00921FB60000000 %312 = fmul float %307, 0x401921FB60000000 %313 = fadd float %312, 0xC00921FB60000000 %314 = fmul float %309, %309 %315 = fmul float %311, %311 %316 = fmul float %313, %313 %317 = fmul float %314, 0xBE90F02E80000000 %318 = fadd float %317, 0x3EF9F6B420000000 %319 = fmul float %315, 0xBE90F02E80000000 %320 = fadd float %319, 0x3EF9F6B420000000 %321 = fmul float %316, 0xBE90F02E80000000 %322 = fadd float %321, 0x3EF9F6B420000000 %323 = fmul float %314, %318 %324 = fadd float %323, 0xBF56C13740000000 %325 = fmul float %315, %320 %326 = fadd float %325, 0xBF56C13740000000 %327 = fmul float %316, %322 %328 = fadd float %327, 0xBF56C13740000000 %329 = fmul float %314, %324 %330 = fadd float %329, 0x3FA5555480000000 %331 = fmul float %315, %326 %332 = fadd float %331, 0x3FA5555480000000 %333 = fmul float %316, %328 %334 = fadd float %333, 0x3FA5555480000000 %335 = fmul float %314, %330 %336 = fsub float %335, %17 %337 = fmul float %315, %332 %338 = fsub float %337, %17 %339 = fmul float %316, %334 %340 = fsub float %339, %17 %341 = fmul float %314, %336 %342 = fadd float %341, %15 %343 = fmul float %315, %338 %344 = fadd float %343, %15 %345 = fmul float %316, %340 %346 = fadd float %345, %15 %347 = fmul float %342, %259 %348 = fmul float %344, %259 %349 = fmul float %346, %259 %350 = fmul float %169, %347 %351 = fadd float %350, %267 %352 = fmul float %169, %348 %353 = fadd float %352, %269 %354 = fmul float %169, %349 %355 = fadd float %354, %271 %356 = fadd float %351, %205 %357 = fadd float %353, %207 %358 = fadd float %355, %209 %359 = fmul float %356, %52 %360 = fmul float %357, %53 %361 = fadd float %359, %360 %362 = fmul float %358, %54 %363 = fadd float %361, %362 %364 = fmul float %73, %55 %365 = fadd float %363, %364 %366 = fmul float %356, %56 %367 = fmul float %357, %57 %368 = fadd float %366, %367 %369 = fmul float %358, %58 %370 = fadd float %368, %369 %371 = fmul float %73, %59 %372 = fadd float %370, %371 %373 = fmul float %356, %60 %374 = fmul float %357, %61 %375 = fadd float %373, %374 %376 = fmul float %358, %62 %377 = fadd float %375, %376 %378 = fmul float %73, %63 %379 = fadd float %377, %378 %380 = fmul float %365, %18 %381 = fmul float %372, %19 %382 = fadd float %380, %381 %383 = fmul float %379, %20 %384 = fadd float %382, %383 %385 = fmul float %15, %21 %386 = fadd float %384, %385 %387 = fmul float %365, %22 %388 = fmul float %372, %23 %389 = fadd float %387, %388 %390 = fmul float %379, %24 %391 = fadd float %389, %390 %392 = fmul float %15, %25 %393 = fadd float %391, %392 %394 = fmul float %365, %26 %395 = fmul float %372, %27 %396 = fadd float %394, %395 %397 = fmul float %379, %28 %398 = fadd float %396, %397 %399 = fmul float %15, %29 %400 = fadd float %398, %399 %401 = fmul float %365, %30 %402 = fmul float %372, %31 %403 = fadd float %401, %402 %404 = fmul float %379, %32 %405 = fadd float %403, %404 %406 = fmul float %15, %33 %407 = fadd float %405, %406 %408 = fmul float %400, %16 %409 = fsub float %408, %407 %410 = fmul float %64, %407 %411 = fadd float %410, %386 %412 = fmul float %65, %407 %413 = fsub float %412, %393 %414 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %415 = load <16 x i8>, <16 x i8> addrspace(2)* %414, align 16, !tbaa !0 %416 = call float @llvm.SI.load.const(<16 x i8> %415, i32 0) %417 = fmul float %416, %386 %418 = call float @llvm.SI.load.const(<16 x i8> %415, i32 4) %419 = fmul float %418, %393 %420 = fadd float %417, %419 %421 = call float @llvm.SI.load.const(<16 x i8> %415, i32 8) %422 = fmul float %421, %400 %423 = fadd float %420, %422 %424 = call float @llvm.SI.load.const(<16 x i8> %415, i32 12) %425 = fmul float %424, %407 %426 = fadd float %423, %425 %427 = call float @llvm.SI.load.const(<16 x i8> %415, i32 16) %428 = fmul float %427, %386 %429 = call float @llvm.SI.load.const(<16 x i8> %415, i32 20) %430 = fmul float %429, %393 %431 = fadd float %428, %430 %432 = call float @llvm.SI.load.const(<16 x i8> %415, i32 24) %433 = fmul float %432, %400 %434 = fadd float %431, %433 %435 = call float @llvm.SI.load.const(<16 x i8> %415, i32 28) %436 = fmul float %435, %407 %437 = fadd float %434, %436 %438 = call float @llvm.SI.load.const(<16 x i8> %415, i32 32) %439 = fmul float %438, %386 %440 = call float @llvm.SI.load.const(<16 x i8> %415, i32 36) %441 = fmul float %440, %393 %442 = fadd float %439, %441 %443 = call float @llvm.SI.load.const(<16 x i8> %415, i32 40) %444 = fmul float %443, %400 %445 = fadd float %442, %444 %446 = call float @llvm.SI.load.const(<16 x i8> %415, i32 44) %447 = fmul float %446, %407 %448 = fadd float %445, %447 %449 = call float @llvm.SI.load.const(<16 x i8> %415, i32 48) %450 = fmul float %449, %386 %451 = call float @llvm.SI.load.const(<16 x i8> %415, i32 52) %452 = fmul float %451, %393 %453 = fadd float %450, %452 %454 = call float @llvm.SI.load.const(<16 x i8> %415, i32 56) %455 = fmul float %454, %400 %456 = fadd float %453, %455 %457 = call float @llvm.SI.load.const(<16 x i8> %415, i32 60) %458 = fmul float %457, %407 %459 = fadd float %456, %458 %460 = call float @llvm.SI.load.const(<16 x i8> %415, i32 64) %461 = fmul float %460, %386 %462 = call float @llvm.SI.load.const(<16 x i8> %415, i32 68) %463 = fmul float %462, %393 %464 = fadd float %461, %463 %465 = call float @llvm.SI.load.const(<16 x i8> %415, i32 72) %466 = fmul float %465, %400 %467 = fadd float %464, %466 %468 = call float @llvm.SI.load.const(<16 x i8> %415, i32 76) %469 = fmul float %468, %407 %470 = fadd float %467, %469 %471 = call float @llvm.SI.load.const(<16 x i8> %415, i32 80) %472 = fmul float %471, %386 %473 = call float @llvm.SI.load.const(<16 x i8> %415, i32 84) %474 = fmul float %473, %393 %475 = fadd float %472, %474 %476 = call float @llvm.SI.load.const(<16 x i8> %415, i32 88) %477 = fmul float %476, %400 %478 = fadd float %475, %477 %479 = call float @llvm.SI.load.const(<16 x i8> %415, i32 92) %480 = fmul float %479, %407 %481 = fadd float %478, %480 %482 = call float @llvm.SI.load.const(<16 x i8> %415, i32 96) %483 = fmul float %482, %386 %484 = call float @llvm.SI.load.const(<16 x i8> %415, i32 100) %485 = fmul float %484, %393 %486 = fadd float %483, %485 %487 = call float @llvm.SI.load.const(<16 x i8> %415, i32 104) %488 = fmul float %487, %400 %489 = fadd float %486, %488 %490 = call float @llvm.SI.load.const(<16 x i8> %415, i32 108) %491 = fmul float %490, %407 %492 = fadd float %489, %491 %493 = call float @llvm.SI.load.const(<16 x i8> %415, i32 112) %494 = fmul float %493, %386 %495 = call float @llvm.SI.load.const(<16 x i8> %415, i32 116) %496 = fmul float %495, %393 %497 = fadd float %494, %496 %498 = call float @llvm.SI.load.const(<16 x i8> %415, i32 120) %499 = fmul float %498, %400 %500 = fadd float %497, %499 %501 = call float @llvm.SI.load.const(<16 x i8> %415, i32 124) %502 = fmul float %501, %407 %503 = fadd float %500, %502 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %78, float %79, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %411, float %413, float %409, float %407) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %426, float %437, float %448, float %459) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %470, float %481, float %492, float %503) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.floor.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.pow.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[8:9], 0x20 ; C00A0804 00000020 v_add_i32_e32 v4, vcc, s10, v0 ; 3208000A v_mov_b32_e32 v5, 0x41980000 ; 7E0A02FF 41980000 v_mov_b32_e32 v6, 0x3e800000 ; 7E0C02FF 3E800000 v_mov_b32_e32 v7, 0x3e22f983 ; 7E0E02FF 3E22F983 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s31, s[12:15], 0xd0 ; C02207C6 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x320 ; C0220746 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x324 ; C0220606 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x328 ; C0220646 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x330 ; C02205C6 00000330 buffer_load_format_xyzw v[0:3], v4, s[4:7], 0 idxen ; E00C2000 80010004 s_nop 0 ; BF800000 buffer_load_format_xyzw v[8:11], v4, s[16:19], 0 idxen ; E00C2000 80040804 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[10:13], v4, s[32:35], 0 idxen ; E00C2000 80080A04 s_buffer_load_dword s6, s[12:15], 0x3bc ; C0220186 000003BC s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x3c0 ; C0220406 000003C0 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x3c4 ; C0220446 000003C4 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x3c8 ; C0220206 000003C8 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x3cc ; C02201C6 000003CC s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e64 v4, s24, s24 ; D1050004 00003018 v_mac_f32_e64 v4, s25, s25 ; D1160004 00003219 v_sqrt_f32_e32 v4, v4 ; 7E084F04 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v13, 0xc0490fdb ; 7E1A02FF C0490FDB v_mov_b32_e32 v14, 0x40c90fdb ; 7E1C02FF 40C90FDB v_mov_b32_e32 v15, 0x37cfb5a1 ; 7E1E02FF 37CFB5A1 v_mov_b32_e32 v16, 0xb4878174 ; 7E2002FF B4878174 v_mov_b32_e32 v17, 0xbab609ba ; 7E2202FF BAB609BA v_mov_b32_e32 v18, 0x3d2aaaa4 ; 7E2402FF 3D2AAAA4 v_mov_b32_e32 v19, 0 ; 7E260280 s_buffer_load_dword s9, s[12:15], 0x3ac ; C0220246 000003AC s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x3b0 ; C0220486 000003B0 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x3b4 ; C02204C6 000003B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x3b8 ; C02202C6 000003B8 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x390 ; C0220806 00000390 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x394 ; C0220846 00000394 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x3a0 ; C0220506 000003A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x3a4 ; C0220546 000003A4 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0x4 ; C0220106 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x8 ; C0220146 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0xc ; C0220586 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x80 ; C0220286 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x33c ; C0220886 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x340 ; C02206C6 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x344 ; C0220706 00000344 s_waitcnt lgkmcnt(0) ; BF8C007F v_subrev_f32_e32 v20, s32, v4 ; 06280820 s_buffer_load_dword s35, s[12:15], 0x350 ; C02208C6 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x354 ; C0220686 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x358 ; C0220786 00000358 v_mov_b32_e32 v21, s4 ; 7E2A0204 v_mul_f32_e32 v22, s9, v21 ; 0A2C2A09 v_mac_f32_e32 v22, s6, v21 ; 2C2C2A06 v_mac_f32_e32 v22, s7, v21 ; 2C2C2A07 v_mad_f32 v21, v22, v5, s29 ; D1C10015 00760B16 v_mov_b32_e32 v23, s32 ; 7E2E0220 v_sub_f32_e32 v23, s33, v23 ; 042E2E21 v_rcp_f32_e32 v23, v23 ; 7E2E4517 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v21, s35, v21 ; 0A2A2A23 v_mul_f32_e32 v24, s34, v21 ; 0A302A22 exp 15, 32, 0, 0, 0, v8, v9, v19, v19 ; C400020F 13130908 v_mad_f32 v0, s31, v10, v0 ; D1C10000 0402141F v_mad_f32 v1, s31, v11, v1 ; D1C10001 0406161F v_mad_f32 v2, s31, v12, v2 ; D1C10002 040A181F s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v8, v7, v21, v6 ; D1C10008 041A2B07 v_madmk_f32_e32 v9, v21, v6, 0x3ebc3c59 ; 2E120D15 3EBC3C59 v_fract_f32_e32 v8, v8 ; 7E103708 v_fract_f32_e32 v9, v9 ; 7E123709 v_mad_f32 v8, v14, v8, v13 ; D1C10008 0436110E v_mad_f32 v9, v14, v9, v13 ; D1C10009 0436130E v_mul_f32_e32 v8, v8, v8 ; 0A101108 v_mul_f32_e32 v9, v9, v9 ; 0A121309 v_mul_f32_e32 v10, v20, v23 ; 0A142F14 v_add_f32_e64 v10, 0, v10 clamp ; D101800A 00021480 v_madak_f32_e32 v11, -2.0, v10, 0x40400000 ; 301614F5 40400000 v_mul_f32_e32 v10, v10, v10 ; 0A14150A v_mul_f32_e32 v12, v11, v10 ; 0A18150B v_mad_f32 v10, -v10, v11, 1.0 ; D1C1000A 23CA170A v_mad_f32 v11, v16, v8, v15 ; D1C1000B 043E1110 v_mad_f32 v11, v11, v8, v17 ; D1C1000B 0446110B v_mad_f32 v11, v11, v8, v18 ; D1C1000B 044A110B v_mad_f32 v11, v8, v11, -s22 ; D1C1000B 805A1708 v_mad_f32 v8, v8, v11, s4 ; D1C10008 00121708 v_mad_f32 v11, v16, v9, v15 ; D1C1000B 043E1310 v_mad_f32 v11, v11, v9, v17 ; D1C1000B 0446130B v_mad_f32 v11, v11, v9, v18 ; D1C1000B 044A130B v_mad_f32 v11, v9, v11, -s22 ; D1C1000B 805A1709 v_mad_f32 v9, v9, v11, s4 ; D1C10009 00121709 v_mad_f32 v11, v7, v24, v6 ; D1C1000B 041A3107 v_fract_f32_e32 v11, v11 ; 7E16370B v_mad_f32 v11, v14, v11, v13 ; D1C1000B 0436170E v_mul_f32_e32 v11, v11, v11 ; 0A16170B v_mad_f32 v19, v16, v11, v15 ; D1C10013 043E1710 v_mad_f32 v19, v19, v11, v17 ; D1C10013 04461713 v_mad_f32 v19, v19, v11, v18 ; D1C10013 044A1713 v_mad_f32 v19, v11, v19, -s22 ; D1C10013 805A270B v_mad_f32 v11, v11, v19, s4 ; D1C1000B 0012270B v_madmk_f32_e32 v19, v24, v6, 0x3eae6205 ; 2E260D18 3EAE6205 v_fract_f32_e32 v19, v19 ; 7E263713 v_mad_f32 v19, v14, v19, v13 ; D1C10013 0436270E v_mul_f32_e32 v19, v19, v19 ; 0A262713 v_mad_f32 v20, v16, v19, v15 ; D1C10014 043E2710 v_mad_f32 v20, v20, v19, v17 ; D1C10014 04462714 v_mad_f32 v20, v20, v19, v18 ; D1C10014 044A2714 v_mad_f32 v20, v19, v20, -s22 ; D1C10014 805A2913 v_mad_f32 v19, v19, v20, s4 ; D1C10013 00122913 s_buffer_load_dword s31, s[12:15], 0x338 ; C02207C6 00000338 v_madak_f32_e32 v8, v8, v10, 0x3dcccccd ; 30101508 3DCCCCCD v_madak_f32_e32 v9, v9, v10, 0x3ecccccd ; 30121509 3ECCCCCD v_mac_f32_e32 v8, v12, v11 ; 2C10170C v_mul_f32_e32 v10, v0, v0 ; 0A140100 v_mac_f32_e32 v10, v1, v1 ; 2C140301 v_sqrt_f32_e32 v11, v10 ; 7E164F0A v_mac_f32_e32 v10, v2, v2 ; 2C140502 v_rsq_f32_e32 v10, v10 ; 7E14490A v_mac_f32_e32 v9, v12, v19 ; 2C12270C v_mov_b32_e32 v12, 0xff7fffff ; 7E1802FF FF7FFFFF v_mov_b32_e32 v19, s29 ; 7E26021D s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v19, s31, v19 ; 0A26261F v_min_f32_e32 v10, 0x7f7fffff, v10 ; 141414FF 7F7FFFFF v_max_f32_e32 v10, v10, v12 ; 1614190A v_mul_f32_e32 v12, v1, v10 ; 0A181501 v_mul_f32_e32 v20, v2, v10 ; 0A281502 v_mul_f32_e32 v10, v0, v10 ; 0A141500 v_mad_f32 v12, s30, v12, v19 ; D1C1000C 044E181E v_mad_f32 v20, s30, v20, v19 ; D1C10014 044E281E v_mac_f32_e32 v19, s30, v10 ; 2C26141E s_buffer_load_dword s29, s[12:15], 0x0 ; C0220746 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x334 ; C0220786 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x348 ; C02207C6 00000348 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x34c ; C0220806 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x35c ; C0220846 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x3a8 ; C0220886 000003A8 v_mac_f32_e32 v12, v5, v22 ; 2C182D05 v_mac_f32_e32 v20, v5, v22 ; 2C282D05 v_mac_f32_e32 v19, v5, v22 ; 2C262D05 v_mov_b32_e32 v5, 0x38d1b717 ; 7E0A02FF 38D1B717 v_mov_b32_e32 v10, s18 ; 7E140212 v_mul_f32_e32 v10, s25, v10 ; 0A141419 v_mad_f32 v12, v7, v12, v6 ; D1C1000C 041A1907 v_mad_f32 v20, v7, v20, v6 ; D1C10014 041A2907 v_mac_f32_e32 v6, v7, v19 ; 2C0C2707 v_mov_b32_e32 v7, s19 ; 7E0E0213 v_mul_f32_e32 v7, s25, v7 ; 0A0E0E19 v_mov_b32_e32 v19, s11 ; 7E26020B v_mul_f32_e32 v19, s25, v19 ; 0A262619 v_fract_f32_e32 v12, v12 ; 7E18370C v_fract_f32_e32 v20, v20 ; 7E283714 v_fract_f32_e32 v6, v6 ; 7E0C3706 v_mad_f32 v12, v14, v12, v13 ; D1C1000C 0436190E v_mad_f32 v20, v14, v20, v13 ; D1C10014 0436290E v_mac_f32_e32 v13, v14, v6 ; 2C1A0D0E v_mov_b32_e32 v6, s24 ; 7E0C0218 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v14, s31 ; 7E1C021F v_mac_f32_e32 v10, s20, v6 ; 2C140C14 v_mac_f32_e32 v7, s21, v6 ; 2C0E0C15 v_mac_f32_e32 v19, s34, v6 ; 2C260C22 v_mad_f32 v6, -s32, v14, v0 ; D1C10006 24021C20 v_mad_f32 v14, -s32, v14, v1 ; D1C1000E 24061C20 v_mul_f32_e32 v6, v6, v6 ; 0A0C0D06 v_mac_f32_e32 v6, v14, v14 ; 2C0C1D0E v_mul_f32_e32 v14, v10, v10 ; 0A1C150A v_mac_f32_e32 v14, v7, v7 ; 2C1C0F07 v_mac_f32_e32 v14, v19, v19 ; 2C1C2713 v_sqrt_f32_e32 v14, v14 ; 7E1C4F0E v_max_f32_e32 v14, v5, v14 ; 161C1D05 v_max_f32_e32 v5, v5, v11 ; 160A1705 v_mov_b32_e32 v11, s28 ; 7E16021C v_sub_f32_e32 v11, s4, v11 ; 04161604 v_mul_f32_e32 v5, v14, v5 ; 0A0A0B0E v_mov_b32_e32 v14, s32 ; 7E1C0220 v_sub_f32_e32 v14, s4, v14 ; 041C1C04 v_mul_f32_e32 v14, s31, v14 ; 0A1C1C1F v_rcp_f32_e32 v14, v14 ; 7E1C450E v_mul_f32_e32 v11, s27, v11 ; 0A16161B v_rcp_f32_e32 v11, v11 ; 7E16450B v_sqrt_f32_e32 v6, v6 ; 7E0C4F06 v_mul_f32_e32 v6, v6, v14 ; 0A0C1D06 v_mov_b32_e32 v14, s27 ; 7E1C021B v_mad_f32 v14, -s28, v14, v2 ; D1C1000E 240A1C1C v_cmp_le_f32_e32 vcc, s29, v14 ; 7C861C1D v_mul_f32_e32 v11, v14, v11 ; 0A16170E v_mul_f32_e32 v14, v0, v10 ; 0A1C1500 v_mac_f32_e32 v14, v1, v7 ; 2C1C0F01 v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mac_f32_e32 v14, s29, v19 ; 2C1C261D v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_mul_f32_e64 v5, v5, |v14| ; D1050205 00021D05 v_log_f32_e32 v14, v6 ; 7E1C4306 v_log_f32_e32 v11, v11 ; 7E16430B v_min_f32_e32 v5, s4, v5 ; 140A0A04 v_sub_f32_e32 v5, s4, v5 ; 040A0A04 v_mul_f32_e32 v5, s26, v5 ; 0A0A0A1A v_mul_f32_e32 v5, v5, v6 ; 0A0A0D05 v_cndmask_b32_e64 v6, 0, 1.0, vcc ; D1000006 01A9E480 v_mul_legacy_f32_e32 v14, s23, v14 ; 081C1C17 v_mul_legacy_f32_e32 v11, s30, v11 ; 0816161E v_exp_f32_e32 v14, v14 ; 7E1C410E v_exp_f32_e32 v11, v11 ; 7E16410B v_mul_f32_e32 v14, s33, v14 ; 0A1C1C21 v_mul_f32_e32 v11, s26, v11 ; 0A16161A v_mul_f32_e32 v5, v5, v6 ; 0A0A0D05 v_mul_f32_e32 v6, v14, v6 ; 0A0C0D0E v_mul_f32_e32 v14, v11, v10 ; 0A1C150B v_mul_f32_e32 v21, v11, v7 ; 0A2A0F0B v_mul_f32_e32 v11, v11, v19 ; 0A16270B v_mul_f32_e32 v10, v5, v10 ; 0A141505 v_mul_f32_e32 v7, v5, v7 ; 0A0E0F05 v_mul_f32_e32 v5, v5, v19 ; 0A0A2705 v_mul_f32_e32 v10, v10, v9 ; 0A14130A v_mul_f32_e32 v7, v7, v9 ; 0A0E1307 v_mul_f32_e32 v5, v5, v9 ; 0A0A1305 v_mac_f32_e32 v10, v8, v14 ; 2C141D08 v_mac_f32_e32 v7, v8, v21 ; 2C0E2B08 v_mul_f32_e32 v9, v12, v12 ; 0A12190C v_mul_f32_e32 v12, v20, v20 ; 0A182914 v_mul_f32_e32 v13, v13, v13 ; 0A1A1B0D v_mac_f32_e32 v5, v8, v11 ; 2C0A1708 v_mad_f32 v8, v16, v9, v15 ; D1C10008 043E1310 v_mad_f32 v11, v16, v12, v15 ; D1C1000B 043E1910 v_mac_f32_e32 v15, v16, v13 ; 2C1E1B10 v_mad_f32 v8, v8, v9, v17 ; D1C10008 04461308 v_mad_f32 v11, v11, v12, v17 ; D1C1000B 0446190B v_mad_f32 v14, v15, v13, v17 ; D1C1000E 04461B0F v_mad_f32 v8, v8, v9, v18 ; D1C10008 044A1308 v_mad_f32 v11, v11, v12, v18 ; D1C1000B 044A190B v_mad_f32 v14, v14, v13, v18 ; D1C1000E 044A1B0E v_mad_f32 v8, v9, v8, -s22 ; D1C10008 805A1109 v_mad_f32 v8, v9, v8, s4 ; D1C10008 00121109 v_mad_f32 v9, v12, v11, -s22 ; D1C10009 805A170C v_mad_f32 v9, v12, v9, s4 ; D1C10009 0012130C v_mad_f32 v11, v13, v14, -s22 ; D1C1000B 805A1D0D v_mad_f32 v11, v13, v11, s4 ; D1C1000B 0012170D v_mul_f32_e32 v8, v6, v8 ; 0A101106 v_mul_f32_e32 v9, v6, v9 ; 0A121306 v_mul_f32_e32 v6, v6, v11 ; 0A0C1706 v_mac_f32_e32 v10, v8, v4 ; 2C140908 v_mac_f32_e32 v7, v9, v4 ; 2C0E0909 v_mac_f32_e32 v5, v6, v4 ; 2C0A0906 v_add_f32_e32 v0, v0, v10 ; 02001500 v_add_f32_e32 v1, v1, v7 ; 02020F01 v_add_f32_e32 v2, v2, v5 ; 02040B02 v_mul_f32_e32 v4, s21, v1 ; 0A080215 v_mul_f32_e32 v5, s19, v1 ; 0A0A0213 v_mul_f32_e32 v1, s17, v1 ; 0A020211 v_mac_f32_e32 v4, s20, v0 ; 2C080014 v_mac_f32_e32 v5, s18, v0 ; 2C0A0012 v_mac_f32_e32 v1, s16, v0 ; 2C020010 s_buffer_load_dword s16, s[12:15], 0x84 ; C0220406 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x88 ; C0220446 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x8c ; C0220486 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x90 ; C02204C6 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x94 ; C0220506 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x98 ; C0220546 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x9c ; C0220586 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0xa0 ; C02205C6 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0xa4 ; C0220606 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0xa8 ; C0220646 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0xac ; C0220686 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0xb0 ; C02206C6 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0xb4 ; C0220706 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0xb8 ; C0220746 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0xbc ; C0220786 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x3d0 ; C02207C6 000003D0 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x3d4 ; C0220306 000003D4 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x0 ; C0220340 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x4 ; C0220380 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[0:3], 0x8 ; C02203C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0xc ; C0220800 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x10 ; C0220840 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x14 ; C02208C0 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x18 ; C0220900 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x1c ; C0220940 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x20 ; C0220980 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x24 ; C02209C0 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x28 ; C0220A00 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x2c ; C0220A40 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x30 ; C0220A80 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x34 ; C0220AC0 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x38 ; C0220B00 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x3c ; C0220B40 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x40 ; C0220B80 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x44 ; C0220BC0 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x48 ; C0220C00 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x4c ; C0220C40 0000004C v_mac_f32_e32 v4, s34, v2 ; 2C080422 v_mac_f32_e32 v5, s11, v2 ; 2C0A040B v_mac_f32_e32 v1, s8, v2 ; 2C020408 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s18 ; 7E000212 v_mac_f32_e32 v4, s9, v3 ; 2C080609 v_mac_f32_e32 v5, s6, v3 ; 2C0A0606 v_mac_f32_e32 v1, s7, v3 ; 2C020607 v_mov_b32_e32 v2, s22 ; 7E040216 v_mul_f32_e32 v3, s16, v5 ; 0A060A10 v_mul_f32_e32 v6, s20, v5 ; 0A0C0A14 v_mul_f32_e32 v7, s24, v5 ; 0A0E0A18 v_mul_f32_e32 v5, s28, v5 ; 0A0A0A1C v_mac_f32_e32 v3, s10, v4 ; 2C06080A v_mac_f32_e32 v6, s19, v4 ; 2C0C0813 v_mac_f32_e32 v7, s23, v4 ; 2C0E0817 v_mac_f32_e32 v5, s27, v4 ; 2C0A081B v_mov_b32_e32 v4, s26 ; 7E08021A v_mac_f32_e32 v3, s17, v1 ; 2C060211 v_mac_f32_e32 v6, s21, v1 ; 2C0C0215 v_mac_f32_e32 v7, s25, v1 ; 2C0E0219 v_mac_f32_e32 v5, s29, v1 ; 2C0A021D v_mov_b32_e32 v1, s30 ; 7E02021E v_mac_f32_e32 v3, s4, v0 ; 2C060004 v_mac_f32_e32 v6, s4, v2 ; 2C0C0404 v_mac_f32_e32 v7, s4, v4 ; 2C0E0804 v_mac_f32_e32 v5, s4, v1 ; 2C0A0204 v_mad_f32 v0, v7, s5, -v5 ; D1C10000 84140B07 v_mad_f32 v1, s31, v5, v3 ; D1C10001 040E0A1F v_mad_f32 v2, s12, v5, -v6 ; D1C10002 841A0A0C v_mul_f32_e32 v4, s14, v6 ; 0A080C0E exp 15, 12, 0, 0, 0, v1, v2, v0, v5 ; C40000CF 05000201 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s35, v6 ; 0A000C23 v_mul_f32_e32 v1, s39, v6 ; 0A020C27 v_mul_f32_e32 v2, s43, v6 ; 0A040C2B v_mac_f32_e32 v4, s13, v3 ; 2C08060D v_mac_f32_e32 v0, s33, v3 ; 2C000621 v_mac_f32_e32 v1, s38, v3 ; 2C020626 v_mac_f32_e32 v2, s42, v3 ; 2C04062A v_mac_f32_e32 v4, s15, v7 ; 2C080E0F v_mac_f32_e32 v0, s36, v7 ; 2C000E24 v_mac_f32_e32 v1, s40, v7 ; 2C020E28 v_mac_f32_e32 v2, s44, v7 ; 2C040E2C v_mac_f32_e32 v4, s32, v5 ; 2C080A20 v_mac_f32_e32 v0, s37, v5 ; 2C000A25 v_mac_f32_e32 v1, s41, v5 ; 2C020A29 v_mac_f32_e32 v2, s45, v5 ; 2C040A2D exp 15, 13, 0, 0, 0, v4, v0, v1, v2 ; C40000DF 02010004 s_buffer_load_dword s4, s[0:3], 0x64 ; C0220100 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x74 ; C0220140 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x50 ; C0220180 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x54 ; C02201C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x58 ; C0220200 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x5c ; C0220240 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x60 ; C0220280 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x68 ; C02202C0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x6c ; C0220300 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x70 ; C0220340 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x78 ; C0220380 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s47, v6 ; 0A000C2F s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v1, s7, v6 ; 0A020C07 v_mul_f32_e32 v2, s4, v6 ; 0A040C04 v_mul_f32_e32 v4, s5, v6 ; 0A080C05 v_mac_f32_e32 v0, s46, v3 ; 2C00062E v_mac_f32_e32 v1, s6, v3 ; 2C020606 v_mac_f32_e32 v2, s10, v3 ; 2C04060A v_mac_f32_e32 v4, s13, v3 ; 2C08060D v_mac_f32_e32 v0, s48, v7 ; 2C000E30 v_mac_f32_e32 v1, s8, v7 ; 2C020E08 v_mac_f32_e32 v2, s11, v7 ; 2C040E0B v_mac_f32_e32 v4, s14, v7 ; 2C080E0E v_mac_f32_e32 v0, s49, v5 ; 2C000A31 v_mac_f32_e32 v1, s9, v5 ; 2C020A09 v_mac_f32_e32 v2, s12, v5 ; 2C040A0C v_mac_f32_e32 v4, s0, v5 ; 2C080A00 exp 15, 14, 0, 1, 0, v0, v1, v2, v4 ; C40008EF 04020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 56 VGPRS: 28 Code Size: 2540 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL CONST[0] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: ADD TEMP[1].xyz, TEMP[0].wwww, -CONST[0].xxxx 3: FSLT TEMP[2].x, TEMP[1].xxxx, IMM[0].xxxx 4: FSLT TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 5: OR TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 6: FSLT TEMP[1].x, TEMP[1].zzzz, IMM[0].xxxx 7: OR TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx 8: AND TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy 9: KILL_IF -TEMP[1].xxxx 10: MOV OUT[0], TEMP[0] 11: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %27 = load <8 x i32>, <8 x i32> addrspace(2)* %26, align 32, !tbaa !0 %28 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !tbaa !0 %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8) %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8) %32 = bitcast float %30 to i32 %33 = bitcast float %31 to i32 %34 = insertelement <2 x i32> undef, i32 %32, i32 0 %35 = insertelement <2 x i32> %34, i32 %33, i32 1 %36 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %35, <8 x i32> %27, <4 x i32> %29, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %37 = extractelement <4 x float> %36, i32 0 %38 = extractelement <4 x float> %36, i32 1 %39 = extractelement <4 x float> %36, i32 2 %40 = extractelement <4 x float> %36, i32 3 %41 = fsub float %40, %25 %42 = fsub float %40, %25 %43 = fsub float %40, %25 %44 = fcmp olt float %41, 0.000000e+00 %45 = fcmp olt float %42, 0.000000e+00 %46 = or i1 %44, %45 %47 = fcmp olt float %43, 0.000000e+00 %48 = or i1 %46, %47 %49 = select i1 %48, float -1.000000e+00, float 0.000000e+00 call void @llvm.AMDGPU.kill(float %49) %50 = call i32 @llvm.SI.packf16(float %37, float %38) %51 = bitcast i32 %50 to float %52 = call i32 @llvm.SI.packf16(float %39, float %40) %53 = bitcast i32 %52 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare void @llvm.AMDGPU.kill(float) ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[0:3], s[2:3], 0x0 ; C00A0001 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[12:19], s[6:7], 0x0 ; C00E0303 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x0 ; C00A0102 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[0:3], 0x0 ; C0220000 00000000 s_mov_b32 m0, s10 ; BEFC000A v_interp_p1_f32 v2, v0, 0, 0, [m0] ; D4080000 v_interp_p2_f32 v2, [v2], v1, 0, 0, [m0] ; D4090001 v_interp_p1_f32 v3, v0, 1, 0, [m0] ; D40C0100 v_interp_p2_f32 v3, [v3], v1, 1, 0, [m0] ; D40D0101 image_sample v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[4:7] ; F0800F00 00230002 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_subrev_f32_e32 v4, s0, v3 ; 06080600 v_cmp_gt_f32_e32 vcc, 0, v4 ; 7C880880 v_cndmask_b32_e64 v4, 0, -1.0, vcc ; D1000004 01A9E680 v_cmpx_le_f32_e32 vcc, 0, v4 ; 7CA60880 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 24 VGPRS: 8 Code Size: 128 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL CONST[0..61] DCL TEMP[0..10], LOCAL IMM[0] FLT32 { 19.0000, 0.1592, 0.3676, 0.3406} IMM[1] FLT32 { 0.2500, 6.2832, -3.1416, -0.0000} IMM[2] FLT32 { 0.0000, -0.0014, 0.0417, -2.0000} IMM[3] FLT32 { 3.0000, 0.1000, 0.4000, 0.0001} IMM[4] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].x, CONST[58].wwww 1: MOV TEMP[0].y, CONST[59].wwww 2: MOV TEMP[0].z, CONST[60].wwww 3: DP3 TEMP[1].x, TEMP[0].xyzz, CONST[0].yyyy 4: MAD TEMP[2].x, TEMP[1].xxxx, IMM[0].xxxx, CONST[50].xxxx 5: MUL TEMP[2].xy, TEMP[2].xxxx, CONST[53].xxxx 6: MUL TEMP[3].xy, TEMP[2].yyyy, CONST[51].wwww 7: MOV TEMP[2].zw, TEMP[3].yyxy 8: MAD TEMP[2], TEMP[2], IMM[0].yzyw, IMM[1].xxxx 9: FRC TEMP[3], TEMP[2] 10: MAD TEMP[2], TEMP[3], IMM[1].yyyy, IMM[1].zzzz 11: MUL TEMP[2], TEMP[2], TEMP[2] 12: MAD TEMP[3], TEMP[2], IMM[1].wwww, IMM[2].xxxx 13: MAD TEMP[3], TEMP[2], TEMP[3], IMM[2].yyyy 14: MAD TEMP[3], TEMP[2], TEMP[3], IMM[2].zzzz 15: MAD TEMP[3], TEMP[2], TEMP[3], -CONST[0].wwww 16: MAD TEMP[2], TEMP[2], TEMP[3], CONST[0].yyyy 17: MUL TEMP[4].xy, CONST[50].yzzz, CONST[50].yzzz 18: ADD TEMP[4].x, TEMP[4].yyyy, TEMP[4].xxxx 19: SQRT TEMP[4].x, TEMP[4].xxxx 20: ADD TEMP[5].x, TEMP[4].xxxx, -CONST[57].xxxx 21: ADD TEMP[6].x, -CONST[57].xxxx, CONST[57].yyyy 22: RCP TEMP[6].x, TEMP[6].xxxx 23: MUL TEMP[5].x, TEMP[6].xxxx, TEMP[5].xxxx 24: MOV_SAT TEMP[5].x, TEMP[5].xxxx 25: MAD TEMP[6].x, TEMP[5].xxxx, IMM[2].wwww, IMM[3].xxxx 26: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 27: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 28: LRP TEMP[3].xy, TEMP[5].xxxx, TEMP[2].zwww, TEMP[2].xyyy 29: ADD TEMP[5].xy, TEMP[3].xyyy, IMM[3].yzzz 30: MUL TEMP[2].xyz, CONST[50].zzzz, CONST[59].xyzz 31: MAD TEMP[6].xyz, CONST[58].xyzz, CONST[50].yyyy, TEMP[2].xyzz 32: DP3 TEMP[2].x, TEMP[6].xyzz, TEMP[6].xyzz 33: SQRT TEMP[2].x, TEMP[2].xxxx 34: MAD TEMP[3].xyz, IN[1].xyzz, CONST[13].xxxx, IN[0].xyzz 35: MUL TEMP[7].xy, TEMP[3].xyyy, TEMP[3].xyyy 36: ADD TEMP[7].x, TEMP[7].yyyy, TEMP[7].xxxx 37: SQRT TEMP[7].x, TEMP[7].xxxx 38: MOV TEMP[2].y, TEMP[7].xxxx 39: MAX TEMP[7].xy, TEMP[2].xyyy, IMM[3].wwww 40: MUL TEMP[2].x, TEMP[7].yyyy, TEMP[7].xxxx 41: RCP TEMP[2].x, TEMP[2].xxxx 42: MOV TEMP[3].w, CONST[0].xxxx 43: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[3].xyww 44: ABS TEMP[7].x, TEMP[7].xxxx 45: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[7].xxxx 46: MIN TEMP[7].x, TEMP[2].xxxx, CONST[0].yyyy 47: ADD TEMP[2].x, -TEMP[7].xxxx, CONST[0].yyyy 48: MUL TEMP[2].x, TEMP[2].xxxx, CONST[53].yyyy 49: ADD TEMP[7].xy, CONST[0].yyyy, -CONST[52].ywww 50: MUL TEMP[7].xy, TEMP[7].xyyy, CONST[52].xzzz 51: RCP TEMP[8].x, TEMP[7].yyyy 52: RCP TEMP[7].x, TEMP[7].xxxx 53: MAD TEMP[9].xyz, CONST[52].xzzz, -CONST[52].ywww, TEMP[3].zxyy 54: MUL TEMP[10].xy, TEMP[9].yzzz, TEMP[9].yzzz 55: ADD TEMP[10].x, TEMP[10].yyyy, TEMP[10].xxxx 56: SQRT TEMP[10].x, TEMP[10].xxxx 57: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[10].xxxx 58: MOV_SAT TEMP[8].x, TEMP[8].xxxx 59: MUL TEMP[2].x, TEMP[8].xxxx, TEMP[2].xxxx 60: POW TEMP[8].x, TEMP[8].xxxx, CONST[51].xxxx 61: MUL TEMP[8].x, TEMP[8].xxxx, CONST[53].wwww 62: MOV TEMP[2].z, TEMP[8].xxxx 63: FSGE TEMP[8].x, TEMP[9].xxxx, CONST[0].xxxx 64: AND TEMP[8].x, TEMP[8].xxxx, IMM[4].xxxx 65: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[9].xxxx 66: MOV_SAT TEMP[7].x, TEMP[7].xxxx 67: POW TEMP[7].x, TEMP[7].xxxx, CONST[51].yyyy 68: MUL TEMP[7].x, TEMP[7].xxxx, CONST[53].yyyy 69: MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[7].xxxx 70: MUL TEMP[2].xy, TEMP[8].xxxx, TEMP[2].xzzz 71: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[2].xxxx 72: MUL TEMP[6].xyz, TEMP[5].yyyy, TEMP[6].xyzz 73: MAD TEMP[5].xyz, TEMP[9].xyzz, TEMP[5].xxxx, TEMP[6].xyzz 74: DP3 TEMP[6].x, TEMP[3].xyzz, TEMP[3].xyzz 75: RSQ TEMP[6].x, TEMP[6].xxxx 76: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[3].yzxx 77: MUL TEMP[6].xyz, TEMP[6].xyzz, CONST[53].zzzz 78: MAD TEMP[6].xyz, CONST[51].zzzz, CONST[50].xxxx, TEMP[6].xyzz 79: MAD TEMP[6].xyz, TEMP[1].xxxx, IMM[0].xxxx, TEMP[6].xyzz 80: MAD TEMP[6].xyz, TEMP[6].xyzz, IMM[0].yyyy, IMM[1].xxxx 81: FRC TEMP[6].xyz, TEMP[6].xyzz 82: MAD TEMP[6].xyz, TEMP[6].xyzz, IMM[1].yyyy, IMM[1].zzzz 83: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[6].xyzz 84: MAD TEMP[7].xyz, TEMP[6].xyzz, IMM[1].wwww, IMM[2].xxxx 85: MAD TEMP[7].xyz, TEMP[6].xyzz, TEMP[7].xyzz, IMM[2].yyyy 86: MAD TEMP[7].xyz, TEMP[6].xyzz, TEMP[7].xyzz, IMM[2].zzzz 87: MAD TEMP[7].xyz, TEMP[6].xyzz, TEMP[7].xyzz, -CONST[0].wwww 88: MAD TEMP[6].xyz, TEMP[6].xyzz, TEMP[7].xyzz, CONST[0].yyyy 89: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[2].yyyy 90: MAD TEMP[0].xyz, TEMP[4].xxxx, TEMP[2].xyzz, TEMP[5].xyzz 91: ADD TEMP[0].xyz, TEMP[0].xyzz, TEMP[3].xyzz 92: MOV TEMP[0].w, IN[0].wwww 93: DP4 TEMP[1].x, TEMP[0], CONST[58] 94: DP4 TEMP[2].x, TEMP[0], CONST[59] 95: MOV TEMP[1].y, TEMP[2].xxxx 96: DP4 TEMP[0].x, TEMP[0], CONST[60] 97: MOV TEMP[1].z, TEMP[0].xxxx 98: MOV TEMP[1].w, CONST[0].yyyy 99: DP4 TEMP[0].x, TEMP[1], CONST[8] 100: DP4 TEMP[2].x, TEMP[1], CONST[9] 101: MOV TEMP[0].y, TEMP[2].xxxx 102: DP4 TEMP[3].x, TEMP[1], CONST[10] 103: MOV TEMP[0].z, TEMP[3].xxxx 104: DP4 TEMP[1].x, TEMP[1], CONST[11] 105: MOV TEMP[0].w, TEMP[1].xxxx 106: MOV TEMP[4], TEMP[0] 107: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[1].xxxx 108: MOV TEMP[0].z, TEMP[3].xxxx 109: MOV TEMP[0].y, -TEMP[2].xxxx 110: MAD TEMP[0].xy, CONST[61].xyyy, TEMP[1].xxxx, TEMP[0].xyyy 111: MOV OUT[0], TEMP[0] 112: MOV OUT[1], TEMP[4] 113: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 824) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 832) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 836) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 840) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 844) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 848) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 852) %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 856) %49 = call float @llvm.SI.load.const(<16 x i8> %13, i32 860) %50 = call float @llvm.SI.load.const(<16 x i8> %13, i32 912) %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 916) %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 928) %53 = call float @llvm.SI.load.const(<16 x i8> %13, i32 932) %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 936) %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 940) %56 = call float @llvm.SI.load.const(<16 x i8> %13, i32 944) %57 = call float @llvm.SI.load.const(<16 x i8> %13, i32 948) %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 952) %59 = call float @llvm.SI.load.const(<16 x i8> %13, i32 956) %60 = call float @llvm.SI.load.const(<16 x i8> %13, i32 960) %61 = call float @llvm.SI.load.const(<16 x i8> %13, i32 964) %62 = call float @llvm.SI.load.const(<16 x i8> %13, i32 968) %63 = call float @llvm.SI.load.const(<16 x i8> %13, i32 972) %64 = call float @llvm.SI.load.const(<16 x i8> %13, i32 976) %65 = call float @llvm.SI.load.const(<16 x i8> %13, i32 980) %66 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %67 = load <16 x i8>, <16 x i8> addrspace(2)* %66, align 16, !tbaa !0 %68 = add i32 %5, %8 %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %68) %70 = extractelement <4 x float> %69, i32 0 %71 = extractelement <4 x float> %69, i32 1 %72 = extractelement <4 x float> %69, i32 2 %73 = extractelement <4 x float> %69, i32 3 %74 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %75 = load <16 x i8>, <16 x i8> addrspace(2)* %74, align 16, !tbaa !0 %76 = add i32 %5, %8 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %76) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = extractelement <4 x float> %77, i32 2 %81 = fmul float %55, %15 %82 = fmul float %59, %15 %83 = fadd float %82, %81 %84 = fmul float %63, %15 %85 = fadd float %83, %84 %86 = fmul float %85, 1.900000e+01 %87 = fadd float %86, %35 %88 = fmul float %87, %46 %89 = fmul float %87, %46 %90 = fmul float %89, %41 %91 = fmul float %89, %41 %92 = fmul float %88, 0x3FC45F3060000000 %93 = fadd float %92, 2.500000e-01 %94 = fmul float %89, 0x3FD7878B20000000 %95 = fadd float %94, 2.500000e-01 %96 = fmul float %90, 0x3FC45F3060000000 %97 = fadd float %96, 2.500000e-01 %98 = fmul float %91, 0x3FD5CC40A0000000 %99 = fadd float %98, 2.500000e-01 %100 = call float @llvm.floor.f32(float %93) %101 = fsub float %93, %100 %102 = call float @llvm.floor.f32(float %95) %103 = fsub float %95, %102 %104 = call float @llvm.floor.f32(float %97) %105 = fsub float %97, %104 %106 = call float @llvm.floor.f32(float %99) %107 = fsub float %99, %106 %108 = fmul float %101, 0x401921FB60000000 %109 = fadd float %108, 0xC00921FB60000000 %110 = fmul float %103, 0x401921FB60000000 %111 = fadd float %110, 0xC00921FB60000000 %112 = fmul float %105, 0x401921FB60000000 %113 = fadd float %112, 0xC00921FB60000000 %114 = fmul float %107, 0x401921FB60000000 %115 = fadd float %114, 0xC00921FB60000000 %116 = fmul float %109, %109 %117 = fmul float %111, %111 %118 = fmul float %113, %113 %119 = fmul float %115, %115 %120 = fmul float %116, 0xBE90F02E80000000 %121 = fadd float %120, 0x3EF9F6B420000000 %122 = fmul float %117, 0xBE90F02E80000000 %123 = fadd float %122, 0x3EF9F6B420000000 %124 = fmul float %118, 0xBE90F02E80000000 %125 = fadd float %124, 0x3EF9F6B420000000 %126 = fmul float %119, 0xBE90F02E80000000 %127 = fadd float %126, 0x3EF9F6B420000000 %128 = fmul float %116, %121 %129 = fadd float %128, 0xBF56C13740000000 %130 = fmul float %117, %123 %131 = fadd float %130, 0xBF56C13740000000 %132 = fmul float %118, %125 %133 = fadd float %132, 0xBF56C13740000000 %134 = fmul float %119, %127 %135 = fadd float %134, 0xBF56C13740000000 %136 = fmul float %116, %129 %137 = fadd float %136, 0x3FA5555480000000 %138 = fmul float %117, %131 %139 = fadd float %138, 0x3FA5555480000000 %140 = fmul float %118, %133 %141 = fadd float %140, 0x3FA5555480000000 %142 = fmul float %119, %135 %143 = fadd float %142, 0x3FA5555480000000 %144 = fmul float %116, %137 %145 = fsub float %144, %17 %146 = fmul float %117, %139 %147 = fsub float %146, %17 %148 = fmul float %118, %141 %149 = fsub float %148, %17 %150 = fmul float %119, %143 %151 = fsub float %150, %17 %152 = fmul float %116, %145 %153 = fadd float %152, %15 %154 = fmul float %117, %147 %155 = fadd float %154, %15 %156 = fmul float %118, %149 %157 = fadd float %156, %15 %158 = fmul float %119, %151 %159 = fadd float %158, %15 %160 = fmul float %36, %36 %161 = fmul float %37, %37 %162 = fadd float %161, %160 %163 = call float @llvm.sqrt.f32(float %162) %164 = fsub float %163, %50 %165 = fsub float %51, %50 %166 = fdiv float 1.000000e+00, %165 %167 = fmul float %166, %164 %168 = call float @llvm.AMDIL.clamp.(float %167, float 0.000000e+00, float 1.000000e+00) %169 = fmul float %168, -2.000000e+00 %170 = fadd float %169, 3.000000e+00 %171 = fmul float %168, %168 %172 = fmul float %171, %170 %173 = fsub float 1.000000e+00, %172 %174 = fmul float %157, %172 %175 = fmul float %153, %173 %176 = fadd float %174, %175 %177 = fsub float 1.000000e+00, %172 %178 = fmul float %159, %172 %179 = fmul float %155, %177 %180 = fadd float %178, %179 %181 = fadd float %176, 0x3FB99999A0000000 %182 = fadd float %180, 0x3FD99999A0000000 %183 = fmul float %37, %56 %184 = fmul float %37, %57 %185 = fmul float %37, %58 %186 = fmul float %52, %36 %187 = fadd float %186, %183 %188 = fmul float %53, %36 %189 = fadd float %188, %184 %190 = fmul float %54, %36 %191 = fadd float %190, %185 %192 = fmul float %187, %187 %193 = fmul float %189, %189 %194 = fadd float %193, %192 %195 = fmul float %191, %191 %196 = fadd float %194, %195 %197 = call float @llvm.sqrt.f32(float %196) %198 = fmul float %78, %34 %199 = fadd float %198, %70 %200 = fmul float %79, %34 %201 = fadd float %200, %71 %202 = fmul float %80, %34 %203 = fadd float %202, %72 %204 = fmul float %199, %199 %205 = fmul float %201, %201 %206 = fadd float %205, %204 %207 = call float @llvm.sqrt.f32(float %206) %208 = call float @llvm.maxnum.f32(float %197, float 0x3F1A36E2E0000000) %209 = call float @llvm.maxnum.f32(float %207, float 0x3F1A36E2E0000000) %210 = fmul float %209, %208 %211 = fdiv float 1.000000e+00, %210 %212 = fmul float %187, %199 %213 = fmul float %189, %201 %214 = fadd float %213, %212 %215 = fmul float %191, %14 %216 = fadd float %214, %215 %217 = call float @llvm.fabs.f32(float %216) %218 = fmul float %211, %217 %219 = call float @llvm.minnum.f32(float %218, float %15) %220 = fsub float %15, %219 %221 = fmul float %220, %47 %222 = fsub float %15, %43 %223 = fsub float %15, %45 %224 = fmul float %222, %42 %225 = fmul float %223, %44 %226 = fdiv float 1.000000e+00, %225 %227 = fdiv float 1.000000e+00, %224 %228 = fmul float %43, %42 %229 = fsub float %203, %228 %230 = fmul float %45, %44 %231 = fsub float %199, %230 %232 = fmul float %45, %44 %233 = fsub float %201, %232 %234 = fmul float %231, %231 %235 = fmul float %233, %233 %236 = fadd float %235, %234 %237 = call float @llvm.sqrt.f32(float %236) %238 = fmul float %226, %237 %239 = call float @llvm.AMDIL.clamp.(float %238, float 0.000000e+00, float 1.000000e+00) %240 = fmul float %239, %221 %241 = call float @llvm.pow.f32(float %239, float %38) %242 = fmul float %241, %49 %243 = fcmp oge float %229, %14 %244 = select i1 %243, float 1.000000e+00, float 0.000000e+00 %245 = fmul float %227, %229 %246 = call float @llvm.AMDIL.clamp.(float %245, float 0.000000e+00, float 1.000000e+00) %247 = call float @llvm.pow.f32(float %246, float %39) %248 = fmul float %247, %47 %249 = fmul float %187, %248 %250 = fmul float %189, %248 %251 = fmul float %191, %248 %252 = fmul float %244, %240 %253 = fmul float %244, %242 %254 = fmul float %187, %252 %255 = fmul float %189, %252 %256 = fmul float %191, %252 %257 = fmul float %182, %254 %258 = fmul float %182, %255 %259 = fmul float %182, %256 %260 = fmul float %249, %181 %261 = fadd float %260, %257 %262 = fmul float %250, %181 %263 = fadd float %262, %258 %264 = fmul float %251, %181 %265 = fadd float %264, %259 %266 = fmul float %199, %199 %267 = fmul float %201, %201 %268 = fadd float %267, %266 %269 = fmul float %203, %203 %270 = fadd float %268, %269 %271 = call float @llvm.AMDGPU.rsq.clamped.f32(float %270) %272 = fmul float %271, %201 %273 = fmul float %271, %203 %274 = fmul float %271, %199 %275 = fmul float %272, %48 %276 = fmul float %273, %48 %277 = fmul float %274, %48 %278 = fmul float %40, %35 %279 = fadd float %278, %275 %280 = fmul float %40, %35 %281 = fadd float %280, %276 %282 = fmul float %40, %35 %283 = fadd float %282, %277 %284 = fmul float %85, 1.900000e+01 %285 = fadd float %284, %279 %286 = fmul float %85, 1.900000e+01 %287 = fadd float %286, %281 %288 = fmul float %85, 1.900000e+01 %289 = fadd float %288, %283 %290 = fmul float %285, 0x3FC45F3060000000 %291 = fadd float %290, 2.500000e-01 %292 = fmul float %287, 0x3FC45F3060000000 %293 = fadd float %292, 2.500000e-01 %294 = fmul float %289, 0x3FC45F3060000000 %295 = fadd float %294, 2.500000e-01 %296 = call float @llvm.floor.f32(float %291) %297 = fsub float %291, %296 %298 = call float @llvm.floor.f32(float %293) %299 = fsub float %293, %298 %300 = call float @llvm.floor.f32(float %295) %301 = fsub float %295, %300 %302 = fmul float %297, 0x401921FB60000000 %303 = fadd float %302, 0xC00921FB60000000 %304 = fmul float %299, 0x401921FB60000000 %305 = fadd float %304, 0xC00921FB60000000 %306 = fmul float %301, 0x401921FB60000000 %307 = fadd float %306, 0xC00921FB60000000 %308 = fmul float %303, %303 %309 = fmul float %305, %305 %310 = fmul float %307, %307 %311 = fmul float %308, 0xBE90F02E80000000 %312 = fadd float %311, 0x3EF9F6B420000000 %313 = fmul float %309, 0xBE90F02E80000000 %314 = fadd float %313, 0x3EF9F6B420000000 %315 = fmul float %310, 0xBE90F02E80000000 %316 = fadd float %315, 0x3EF9F6B420000000 %317 = fmul float %308, %312 %318 = fadd float %317, 0xBF56C13740000000 %319 = fmul float %309, %314 %320 = fadd float %319, 0xBF56C13740000000 %321 = fmul float %310, %316 %322 = fadd float %321, 0xBF56C13740000000 %323 = fmul float %308, %318 %324 = fadd float %323, 0x3FA5555480000000 %325 = fmul float %309, %320 %326 = fadd float %325, 0x3FA5555480000000 %327 = fmul float %310, %322 %328 = fadd float %327, 0x3FA5555480000000 %329 = fmul float %308, %324 %330 = fsub float %329, %17 %331 = fmul float %309, %326 %332 = fsub float %331, %17 %333 = fmul float %310, %328 %334 = fsub float %333, %17 %335 = fmul float %308, %330 %336 = fadd float %335, %15 %337 = fmul float %309, %332 %338 = fadd float %337, %15 %339 = fmul float %310, %334 %340 = fadd float %339, %15 %341 = fmul float %336, %253 %342 = fmul float %338, %253 %343 = fmul float %340, %253 %344 = fmul float %163, %341 %345 = fadd float %344, %261 %346 = fmul float %163, %342 %347 = fadd float %346, %263 %348 = fmul float %163, %343 %349 = fadd float %348, %265 %350 = fadd float %345, %199 %351 = fadd float %347, %201 %352 = fadd float %349, %203 %353 = fmul float %350, %52 %354 = fmul float %351, %53 %355 = fadd float %353, %354 %356 = fmul float %352, %54 %357 = fadd float %355, %356 %358 = fmul float %73, %55 %359 = fadd float %357, %358 %360 = fmul float %350, %56 %361 = fmul float %351, %57 %362 = fadd float %360, %361 %363 = fmul float %352, %58 %364 = fadd float %362, %363 %365 = fmul float %73, %59 %366 = fadd float %364, %365 %367 = fmul float %350, %60 %368 = fmul float %351, %61 %369 = fadd float %367, %368 %370 = fmul float %352, %62 %371 = fadd float %369, %370 %372 = fmul float %73, %63 %373 = fadd float %371, %372 %374 = fmul float %359, %18 %375 = fmul float %366, %19 %376 = fadd float %374, %375 %377 = fmul float %373, %20 %378 = fadd float %376, %377 %379 = fmul float %15, %21 %380 = fadd float %378, %379 %381 = fmul float %359, %22 %382 = fmul float %366, %23 %383 = fadd float %381, %382 %384 = fmul float %373, %24 %385 = fadd float %383, %384 %386 = fmul float %15, %25 %387 = fadd float %385, %386 %388 = fmul float %359, %26 %389 = fmul float %366, %27 %390 = fadd float %388, %389 %391 = fmul float %373, %28 %392 = fadd float %390, %391 %393 = fmul float %15, %29 %394 = fadd float %392, %393 %395 = fmul float %359, %30 %396 = fmul float %366, %31 %397 = fadd float %395, %396 %398 = fmul float %373, %32 %399 = fadd float %397, %398 %400 = fmul float %15, %33 %401 = fadd float %399, %400 %402 = fmul float %394, %16 %403 = fsub float %402, %401 %404 = fmul float %64, %401 %405 = fadd float %404, %380 %406 = fmul float %65, %401 %407 = fsub float %406, %387 %408 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %409 = load <16 x i8>, <16 x i8> addrspace(2)* %408, align 16, !tbaa !0 %410 = call float @llvm.SI.load.const(<16 x i8> %409, i32 0) %411 = fmul float %410, %380 %412 = call float @llvm.SI.load.const(<16 x i8> %409, i32 4) %413 = fmul float %412, %387 %414 = fadd float %411, %413 %415 = call float @llvm.SI.load.const(<16 x i8> %409, i32 8) %416 = fmul float %415, %394 %417 = fadd float %414, %416 %418 = call float @llvm.SI.load.const(<16 x i8> %409, i32 12) %419 = fmul float %418, %401 %420 = fadd float %417, %419 %421 = call float @llvm.SI.load.const(<16 x i8> %409, i32 16) %422 = fmul float %421, %380 %423 = call float @llvm.SI.load.const(<16 x i8> %409, i32 20) %424 = fmul float %423, %387 %425 = fadd float %422, %424 %426 = call float @llvm.SI.load.const(<16 x i8> %409, i32 24) %427 = fmul float %426, %394 %428 = fadd float %425, %427 %429 = call float @llvm.SI.load.const(<16 x i8> %409, i32 28) %430 = fmul float %429, %401 %431 = fadd float %428, %430 %432 = call float @llvm.SI.load.const(<16 x i8> %409, i32 32) %433 = fmul float %432, %380 %434 = call float @llvm.SI.load.const(<16 x i8> %409, i32 36) %435 = fmul float %434, %387 %436 = fadd float %433, %435 %437 = call float @llvm.SI.load.const(<16 x i8> %409, i32 40) %438 = fmul float %437, %394 %439 = fadd float %436, %438 %440 = call float @llvm.SI.load.const(<16 x i8> %409, i32 44) %441 = fmul float %440, %401 %442 = fadd float %439, %441 %443 = call float @llvm.SI.load.const(<16 x i8> %409, i32 48) %444 = fmul float %443, %380 %445 = call float @llvm.SI.load.const(<16 x i8> %409, i32 52) %446 = fmul float %445, %387 %447 = fadd float %444, %446 %448 = call float @llvm.SI.load.const(<16 x i8> %409, i32 56) %449 = fmul float %448, %394 %450 = fadd float %447, %449 %451 = call float @llvm.SI.load.const(<16 x i8> %409, i32 60) %452 = fmul float %451, %401 %453 = fadd float %450, %452 %454 = call float @llvm.SI.load.const(<16 x i8> %409, i32 64) %455 = fmul float %454, %380 %456 = call float @llvm.SI.load.const(<16 x i8> %409, i32 68) %457 = fmul float %456, %387 %458 = fadd float %455, %457 %459 = call float @llvm.SI.load.const(<16 x i8> %409, i32 72) %460 = fmul float %459, %394 %461 = fadd float %458, %460 %462 = call float @llvm.SI.load.const(<16 x i8> %409, i32 76) %463 = fmul float %462, %401 %464 = fadd float %461, %463 %465 = call float @llvm.SI.load.const(<16 x i8> %409, i32 80) %466 = fmul float %465, %380 %467 = call float @llvm.SI.load.const(<16 x i8> %409, i32 84) %468 = fmul float %467, %387 %469 = fadd float %466, %468 %470 = call float @llvm.SI.load.const(<16 x i8> %409, i32 88) %471 = fmul float %470, %394 %472 = fadd float %469, %471 %473 = call float @llvm.SI.load.const(<16 x i8> %409, i32 92) %474 = fmul float %473, %401 %475 = fadd float %472, %474 %476 = call float @llvm.SI.load.const(<16 x i8> %409, i32 96) %477 = fmul float %476, %380 %478 = call float @llvm.SI.load.const(<16 x i8> %409, i32 100) %479 = fmul float %478, %387 %480 = fadd float %477, %479 %481 = call float @llvm.SI.load.const(<16 x i8> %409, i32 104) %482 = fmul float %481, %394 %483 = fadd float %480, %482 %484 = call float @llvm.SI.load.const(<16 x i8> %409, i32 108) %485 = fmul float %484, %401 %486 = fadd float %483, %485 %487 = call float @llvm.SI.load.const(<16 x i8> %409, i32 112) %488 = fmul float %487, %380 %489 = call float @llvm.SI.load.const(<16 x i8> %409, i32 116) %490 = fmul float %489, %387 %491 = fadd float %488, %490 %492 = call float @llvm.SI.load.const(<16 x i8> %409, i32 120) %493 = fmul float %492, %394 %494 = fadd float %491, %493 %495 = call float @llvm.SI.load.const(<16 x i8> %409, i32 124) %496 = fmul float %495, %401 %497 = fadd float %494, %496 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %405, float %407, float %403, float %401) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %420, float %431, float %442, float %453) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %464, float %475, float %486, float %497) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.floor.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.pow.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x0 ; C00A0404 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x10 ; C00A0304 00000010 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 0x41980000 ; 7E0202FF 41980000 v_mov_b32_e32 v2, 0x3e800000 ; 7E0402FF 3E800000 v_mov_b32_e32 v3, 0x3e22f983 ; 7E0602FF 3E22F983 v_mov_b32_e32 v4, 0xc0490fdb ; 7E0802FF C0490FDB v_mov_b32_e32 v5, 0x40c90fdb ; 7E0A02FF 40C90FDB s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[6:9], v0, s[16:19], 0 idxen ; E00C2000 80040600 s_nop 0 ; BF800000 buffer_load_format_xyzw v[10:13], v0, s[12:15], 0 idxen ; E00C2000 80030A00 v_mov_b32_e32 v0, 0x37cfb5a1 ; 7E0002FF 37CFB5A1 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v13, 0xb4878174 ; 7E1A02FF B4878174 v_mov_b32_e32 v14, 0xbab609ba ; 7E1C02FF BAB609BA v_mov_b32_e32 v15, 0x3d2aaaa4 ; 7E1E02FF 3D2AAAA4 s_buffer_load_dword s9, s[4:7], 0x4 ; C0220242 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0xc ; C0220442 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x80 ; C0220282 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0xd0 ; C0220782 000000D0 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x320 ; C02207C2 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x324 ; C02206C2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x328 ; C0220702 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x330 ; C02205C2 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x33c ; C0220802 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x340 ; C0220642 00000340 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x344 ; C0220682 00000344 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x350 ; C0220842 00000350 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x354 ; C0220602 00000354 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x358 ; C0220742 00000358 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x3ac ; C02202C2 000003AC s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x3bc ; C0220302 000003BC s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x3c0 ; C0220402 000003C0 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x3c4 ; C0220482 000003C4 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x3c8 ; C0220382 000003C8 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x3cc ; C0220342 000003CC s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x390 ; C0220882 00000390 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x394 ; C02208C2 00000394 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x3a0 ; C02204C2 000003A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x3a4 ; C0220542 000003A4 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x3b0 ; C0220502 000003B0 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x3b4 ; C0220582 000003B4 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x3b8 ; C02203C2 000003B8 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v16, s9 ; 7E200209 v_mul_f32_e32 v17, s11, v16 ; 0A22200B v_mul_f32_e64 v18, s27, s27 ; D1050012 0000361B v_mac_f32_e32 v17, s12, v16 ; 2C22200C v_mac_f32_e64 v18, s28, s28 ; D1160012 0000381C v_mac_f32_e32 v17, s13, v16 ; 2C22200D v_sqrt_f32_e32 v16, v18 ; 7E204F12 v_mad_f32 v18, v17, v1, s31 ; D1C10012 007E0311 v_subrev_f32_e32 v19, s34, v16 ; 06262022 v_mov_b32_e32 v20, s34 ; 7E280222 v_sub_f32_e32 v20, s35, v20 ; 04282823 v_mul_f32_e32 v18, s33, v18 ; 0A242421 v_rcp_f32_e32 v20, v20 ; 7E284514 v_mad_f32 v6, s30, v10, v6 ; D1C10006 041A141E v_mad_f32 v7, s30, v11, v7 ; D1C10007 041E161E v_mad_f32 v8, s30, v12, v8 ; D1C10008 0422181E v_mul_f32_e32 v10, s32, v18 ; 0A142420 v_mad_f32 v11, v3, v18, v2 ; D1C1000B 040A2503 v_madmk_f32_e32 v12, v18, v2, 0x3ebc3c59 ; 2E180512 3EBC3C59 v_fract_f32_e32 v11, v11 ; 7E16370B v_fract_f32_e32 v12, v12 ; 7E18370C v_mad_f32 v11, v5, v11, v4 ; D1C1000B 04121705 v_mad_f32 v12, v5, v12, v4 ; D1C1000C 04121905 v_mul_f32_e32 v11, v11, v11 ; 0A16170B v_mul_f32_e32 v12, v12, v12 ; 0A18190C v_mul_f32_e32 v18, v19, v20 ; 0A242913 v_add_f32_e64 v18, 0, v18 clamp ; D1018012 00022480 v_madak_f32_e32 v19, -2.0, v18, 0x40400000 ; 302624F5 40400000 v_mul_f32_e32 v18, v18, v18 ; 0A242512 v_mul_f32_e32 v20, v19, v18 ; 0A282513 v_mad_f32 v18, -v18, v19, 1.0 ; D1C10012 23CA2712 v_mad_f32 v19, v13, v11, v0 ; D1C10013 0402170D v_mad_f32 v19, v19, v11, v14 ; D1C10013 043A1713 v_mad_f32 v19, v19, v11, v15 ; D1C10013 043E1713 v_mad_f32 v19, v11, v19, -s17 ; D1C10013 8046270B v_mad_f32 v11, v11, v19, s9 ; D1C1000B 0026270B v_mad_f32 v19, v13, v12, v0 ; D1C10013 0402190D v_mad_f32 v19, v19, v12, v14 ; D1C10013 043A1913 v_mad_f32 v19, v19, v12, v15 ; D1C10013 043E1913 v_mad_f32 v19, v12, v19, -s17 ; D1C10013 8046270C v_mad_f32 v12, v12, v19, s9 ; D1C1000C 0026270C v_mad_f32 v19, v3, v10, v2 ; D1C10013 040A1503 v_fract_f32_e32 v19, v19 ; 7E263713 v_mad_f32 v19, v5, v19, v4 ; D1C10013 04122705 v_mul_f32_e32 v19, v19, v19 ; 0A262713 v_mad_f32 v21, v13, v19, v0 ; D1C10015 0402270D v_mad_f32 v21, v21, v19, v14 ; D1C10015 043A2715 v_mad_f32 v21, v21, v19, v15 ; D1C10015 043E2715 v_mad_f32 v21, v19, v21, -s17 ; D1C10015 80462B13 v_mad_f32 v19, v19, v21, s9 ; D1C10013 00262B13 v_madmk_f32_e32 v10, v10, v2, 0x3eae6205 ; 2E14050A 3EAE6205 v_fract_f32_e32 v10, v10 ; 7E14370A v_mad_f32 v10, v5, v10, v4 ; D1C1000A 04121505 v_mul_f32_e32 v10, v10, v10 ; 0A14150A v_mad_f32 v21, v13, v10, v0 ; D1C10015 0402150D v_mad_f32 v21, v21, v10, v14 ; D1C10015 043A1515 v_mad_f32 v21, v21, v10, v15 ; D1C10015 043E1515 v_mad_f32 v21, v10, v21, -s17 ; D1C10015 80462B0A v_mad_f32 v10, v10, v21, s9 ; D1C1000A 00262B0A s_buffer_load_dword s30, s[4:7], 0x338 ; C0220782 00000338 v_madak_f32_e32 v11, v11, v18, 0x3dcccccd ; 3016250B 3DCCCCCD v_madak_f32_e32 v12, v12, v18, 0x3ecccccd ; 3018250C 3ECCCCCD v_mac_f32_e32 v11, v20, v19 ; 2C162714 v_mul_f32_e32 v18, v6, v6 ; 0A240D06 v_mac_f32_e32 v18, v7, v7 ; 2C240F07 v_sqrt_f32_e32 v19, v18 ; 7E264F12 v_mac_f32_e32 v18, v8, v8 ; 2C241108 v_rsq_f32_e32 v18, v18 ; 7E244912 v_mac_f32_e32 v12, v20, v10 ; 2C181514 v_mov_b32_e32 v10, 0xff7fffff ; 7E1402FF FF7FFFFF v_mov_b32_e32 v20, s31 ; 7E28021F s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v20, s30, v20 ; 0A28281E v_min_f32_e32 v18, 0x7f7fffff, v18 ; 142424FF 7F7FFFFF v_max_f32_e32 v10, v18, v10 ; 16141512 v_mul_f32_e32 v18, v7, v10 ; 0A241507 v_mul_f32_e32 v21, v8, v10 ; 0A2A1508 v_mul_f32_e32 v10, v6, v10 ; 0A141506 v_mad_f32 v18, s29, v18, v20 ; D1C10012 0452241D v_mad_f32 v21, s29, v21, v20 ; D1C10015 04522A1D v_mac_f32_e32 v20, s29, v10 ; 2C28141D s_buffer_load_dword s29, s[4:7], 0x0 ; C0220742 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0x334 ; C0220782 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x348 ; C02207C2 00000348 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x34c ; C0220802 0000034C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x35c ; C0220842 0000035C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x3a8 ; C0220882 000003A8 v_mac_f32_e32 v18, v1, v17 ; 2C242301 v_mac_f32_e32 v21, v1, v17 ; 2C2A2301 v_mac_f32_e32 v20, v1, v17 ; 2C282301 v_mov_b32_e32 v1, 0x38d1b717 ; 7E0202FF 38D1B717 v_mov_b32_e32 v10, s20 ; 7E140214 v_mul_f32_e32 v10, s28, v10 ; 0A14141C v_mad_f32 v17, v3, v18, v2 ; D1C10011 040A2503 v_mad_f32 v18, v3, v21, v2 ; D1C10012 040A2B03 v_mac_f32_e32 v2, v3, v20 ; 2C042903 v_mov_b32_e32 v3, s22 ; 7E060216 v_mul_f32_e32 v3, s28, v3 ; 0A06061C v_mov_b32_e32 v20, s15 ; 7E28020F v_mul_f32_e32 v20, s28, v20 ; 0A28281C v_fract_f32_e32 v17, v17 ; 7E223711 v_fract_f32_e32 v18, v18 ; 7E243712 v_fract_f32_e32 v2, v2 ; 7E043702 v_mad_f32 v17, v5, v17, v4 ; D1C10011 04122305 v_mad_f32 v18, v5, v18, v4 ; D1C10012 04122505 v_mac_f32_e32 v4, v5, v2 ; 2C080505 v_mov_b32_e32 v2, s27 ; 7E04021B s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v5, s31 ; 7E0A021F v_mac_f32_e32 v10, s19, v2 ; 2C140413 v_mac_f32_e32 v3, s21, v2 ; 2C060415 v_mac_f32_e32 v20, s34, v2 ; 2C280422 v_mad_f32 v2, -s32, v5, v6 ; D1C10002 241A0A20 v_mad_f32 v5, -s32, v5, v7 ; D1C10005 241E0A20 v_mul_f32_e32 v2, v2, v2 ; 0A040502 v_mac_f32_e32 v2, v5, v5 ; 2C040B05 v_mul_f32_e32 v5, v10, v10 ; 0A0A150A v_mac_f32_e32 v5, v3, v3 ; 2C0A0703 v_mac_f32_e32 v5, v20, v20 ; 2C0A2914 v_sqrt_f32_e32 v5, v5 ; 7E0A4F05 v_max_f32_e32 v5, v1, v5 ; 160A0B01 v_max_f32_e32 v1, v1, v19 ; 16022701 v_mov_b32_e32 v19, s26 ; 7E26021A v_sub_f32_e32 v19, s9, v19 ; 04262609 v_mul_f32_e32 v1, v5, v1 ; 0A020305 v_mov_b32_e32 v5, s32 ; 7E0A0220 v_sub_f32_e32 v5, s9, v5 ; 040A0A09 v_mul_f32_e32 v5, s31, v5 ; 0A0A0A1F v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mul_f32_e32 v19, s25, v19 ; 0A262619 v_rcp_f32_e32 v19, v19 ; 7E264513 v_sqrt_f32_e32 v2, v2 ; 7E044F02 v_mul_f32_e32 v2, v2, v5 ; 0A040B02 v_mov_b32_e32 v5, s25 ; 7E0A0219 v_mad_f32 v5, -s26, v5, v8 ; D1C10005 24220A1A v_cmp_le_f32_e32 vcc, s29, v5 ; 7C860A1D v_mul_f32_e32 v5, v5, v19 ; 0A0A2705 v_mul_f32_e32 v19, v6, v10 ; 0A261506 v_mac_f32_e32 v19, v7, v3 ; 2C260707 v_rcp_f32_e32 v1, v1 ; 7E024501 v_mac_f32_e32 v19, s29, v20 ; 2C26281D v_add_f32_e64 v2, 0, v2 clamp ; D1018002 00020480 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_mul_f32_e64 v1, v1, |v19| ; D1050201 00022701 v_log_f32_e32 v19, v2 ; 7E264302 v_log_f32_e32 v5, v5 ; 7E0A4305 v_min_f32_e32 v1, s9, v1 ; 14020209 v_sub_f32_e32 v1, s9, v1 ; 04020209 v_mul_f32_e32 v1, s24, v1 ; 0A020218 v_mul_f32_e32 v1, v1, v2 ; 0A020501 v_cndmask_b32_e64 v2, 0, 1.0, vcc ; D1000002 01A9E480 v_mul_legacy_f32_e32 v19, s23, v19 ; 08262617 v_mul_legacy_f32_e32 v5, s30, v5 ; 080A0A1E v_exp_f32_e32 v19, v19 ; 7E264113 v_exp_f32_e32 v5, v5 ; 7E0A4105 v_mul_f32_e32 v19, s33, v19 ; 0A262621 v_mul_f32_e32 v5, s24, v5 ; 0A0A0A18 v_mul_f32_e32 v1, v1, v2 ; 0A020501 v_mul_f32_e32 v2, v19, v2 ; 0A040513 v_mul_f32_e32 v19, v5, v10 ; 0A261505 v_mul_f32_e32 v21, v5, v3 ; 0A2A0705 v_mul_f32_e32 v5, v5, v20 ; 0A0A2905 v_mul_f32_e32 v10, v1, v10 ; 0A141501 v_mul_f32_e32 v3, v1, v3 ; 0A060701 v_mul_f32_e32 v1, v1, v20 ; 0A022901 v_mul_f32_e32 v10, v10, v12 ; 0A14190A v_mul_f32_e32 v3, v3, v12 ; 0A061903 v_mul_f32_e32 v1, v1, v12 ; 0A021901 v_mac_f32_e32 v10, v11, v19 ; 2C14270B v_mac_f32_e32 v3, v11, v21 ; 2C062B0B v_mul_f32_e32 v12, v17, v17 ; 0A182311 v_mul_f32_e32 v17, v18, v18 ; 0A222512 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mac_f32_e32 v1, v11, v5 ; 2C020B0B v_mad_f32 v5, v13, v12, v0 ; D1C10005 0402190D v_mad_f32 v11, v13, v17, v0 ; D1C1000B 0402230D v_mac_f32_e32 v0, v13, v4 ; 2C00090D v_mad_f32 v5, v5, v12, v14 ; D1C10005 043A1905 v_mad_f32 v11, v11, v17, v14 ; D1C1000B 043A230B v_mad_f32 v0, v0, v4, v14 ; D1C10000 043A0900 v_mad_f32 v5, v5, v12, v15 ; D1C10005 043E1905 v_mad_f32 v11, v11, v17, v15 ; D1C1000B 043E230B v_mad_f32 v0, v0, v4, v15 ; D1C10000 043E0900 v_mad_f32 v5, v12, v5, -s17 ; D1C10005 80460B0C v_mad_f32 v5, v12, v5, s9 ; D1C10005 00260B0C v_mad_f32 v11, v17, v11, -s17 ; D1C1000B 80461711 v_mad_f32 v11, v17, v11, s9 ; D1C1000B 00261711 v_mad_f32 v0, v4, v0, -s17 ; D1C10000 80460104 v_mad_f32 v0, v4, v0, s9 ; D1C10000 00260104 v_mul_f32_e32 v4, v2, v5 ; 0A080B02 v_mul_f32_e32 v5, v2, v11 ; 0A0A1702 v_mul_f32_e32 v0, v2, v0 ; 0A000102 v_mac_f32_e32 v10, v4, v16 ; 2C142104 v_mac_f32_e32 v3, v5, v16 ; 2C062105 v_mac_f32_e32 v1, v0, v16 ; 2C022100 v_add_f32_e32 v0, v6, v10 ; 02001506 v_add_f32_e32 v2, v7, v3 ; 02040707 v_add_f32_e32 v1, v8, v1 ; 02020308 v_mul_f32_e32 v3, s21, v2 ; 0A060415 v_mul_f32_e32 v4, s22, v2 ; 0A080416 v_mul_f32_e32 v2, s18, v2 ; 0A040412 v_mac_f32_e32 v3, s19, v0 ; 2C060013 v_mac_f32_e32 v4, s20, v0 ; 2C080014 v_mac_f32_e32 v2, s16, v0 ; 2C040010 s_buffer_load_dword s16, s[4:7], 0x84 ; C0220402 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x88 ; C0220442 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x8c ; C0220482 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x90 ; C02204C2 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x94 ; C0220502 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x98 ; C0220542 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x9c ; C0220582 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0xa0 ; C02205C2 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0xa4 ; C0220602 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0xa8 ; C0220642 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0xac ; C0220682 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0xb0 ; C02206C2 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0xb4 ; C0220702 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0xb8 ; C0220742 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0xbc ; C0220782 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x3d0 ; C02207C2 000003D0 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x3d4 ; C0220102 000003D4 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0xc ; C0220800 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x10 ; C0220840 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x14 ; C02208C0 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x18 ; C0220900 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x1c ; C0220940 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x20 ; C0220980 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x24 ; C02209C0 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x28 ; C0220A00 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x2c ; C0220A40 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x30 ; C0220A80 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x34 ; C0220AC0 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[0:3], 0x38 ; C0220B00 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[0:3], 0x3c ; C0220B40 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s46, s[0:3], 0x40 ; C0220B80 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[0:3], 0x44 ; C0220BC0 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s48, s[0:3], 0x48 ; C0220C00 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[0:3], 0x4c ; C0220C40 0000004C v_mac_f32_e32 v3, s34, v1 ; 2C060222 v_mac_f32_e32 v4, s15, v1 ; 2C08020F v_mac_f32_e32 v2, s14, v1 ; 2C04020E s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s18 ; 7E000212 v_mac_f32_e32 v3, s11, v9 ; 2C06120B v_mac_f32_e32 v4, s12, v9 ; 2C08120C v_mac_f32_e32 v2, s13, v9 ; 2C04120D v_mov_b32_e32 v1, s22 ; 7E020216 v_mul_f32_e32 v5, s16, v4 ; 0A0A0810 v_mul_f32_e32 v6, s20, v4 ; 0A0C0814 v_mul_f32_e32 v7, s24, v4 ; 0A0E0818 v_mul_f32_e32 v4, s28, v4 ; 0A08081C v_mac_f32_e32 v5, s10, v3 ; 2C0A060A v_mac_f32_e32 v6, s19, v3 ; 2C0C0613 v_mac_f32_e32 v7, s23, v3 ; 2C0E0617 v_mac_f32_e32 v4, s27, v3 ; 2C08061B v_mov_b32_e32 v3, s26 ; 7E06021A v_mac_f32_e32 v5, s17, v2 ; 2C0A0411 v_mac_f32_e32 v6, s21, v2 ; 2C0C0415 v_mac_f32_e32 v7, s25, v2 ; 2C0E0419 v_mac_f32_e32 v4, s29, v2 ; 2C08041D v_mov_b32_e32 v2, s30 ; 7E04021E v_mac_f32_e32 v5, s9, v0 ; 2C0A0009 v_mac_f32_e32 v6, s9, v1 ; 2C0C0209 v_mac_f32_e32 v7, s9, v3 ; 2C0E0609 v_mac_f32_e32 v4, s9, v2 ; 2C080409 v_mad_f32 v0, v7, s8, -v4 ; D1C10000 84101107 v_mad_f32 v1, s31, v4, v5 ; D1C10001 0416081F v_mad_f32 v2, s4, v4, -v6 ; D1C10002 841A0804 v_mul_f32_e32 v3, s6, v6 ; 0A060C06 exp 15, 12, 0, 0, 0, v1, v2, v0, v4 ; C40000CF 04000201 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s35, v6 ; 0A000C23 v_mul_f32_e32 v1, s39, v6 ; 0A020C27 v_mul_f32_e32 v2, s43, v6 ; 0A040C2B v_mac_f32_e32 v3, s5, v5 ; 2C060A05 v_mac_f32_e32 v0, s33, v5 ; 2C000A21 v_mac_f32_e32 v1, s38, v5 ; 2C020A26 v_mac_f32_e32 v2, s42, v5 ; 2C040A2A v_mac_f32_e32 v3, s7, v7 ; 2C060E07 v_mac_f32_e32 v0, s36, v7 ; 2C000E24 v_mac_f32_e32 v1, s40, v7 ; 2C020E28 v_mac_f32_e32 v2, s44, v7 ; 2C040E2C v_mac_f32_e32 v3, s32, v4 ; 2C060820 v_mac_f32_e32 v0, s37, v4 ; 2C000825 v_mac_f32_e32 v1, s41, v4 ; 2C020829 v_mac_f32_e32 v2, s45, v4 ; 2C04082D exp 15, 13, 0, 0, 0, v3, v0, v1, v2 ; C40000DF 02010003 s_buffer_load_dword s4, s[0:3], 0x64 ; C0220100 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x74 ; C0220140 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x50 ; C0220180 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x54 ; C02201C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x58 ; C0220200 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x5c ; C0220240 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x60 ; C0220280 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x68 ; C02202C0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x6c ; C0220300 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x70 ; C0220340 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x78 ; C0220380 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v0, s47, v6 ; 0A000C2F s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v1, s7, v6 ; 0A020C07 v_mul_f32_e32 v2, s4, v6 ; 0A040C04 v_mul_f32_e32 v3, s5, v6 ; 0A060C05 v_mac_f32_e32 v0, s46, v5 ; 2C000A2E v_mac_f32_e32 v1, s6, v5 ; 2C020A06 v_mac_f32_e32 v2, s10, v5 ; 2C040A0A v_mac_f32_e32 v3, s13, v5 ; 2C060A0D v_mac_f32_e32 v0, s48, v7 ; 2C000E30 v_mac_f32_e32 v1, s8, v7 ; 2C020E08 v_mac_f32_e32 v2, s11, v7 ; 2C040E0B v_mac_f32_e32 v3, s14, v7 ; 2C060E0E v_mac_f32_e32 v0, s49, v4 ; 2C000831 v_mac_f32_e32 v1, s9, v4 ; 2C020809 v_mac_f32_e32 v2, s12, v4 ; 2C04080C v_mac_f32_e32 v3, s0, v4 ; 2C060800 exp 15, 14, 0, 1, 0, v0, v1, v2, v3 ; C40008EF 03020100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 56 VGPRS: 24 Code Size: 2504 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL OUT[0], COLOR IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xyyx 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 0.000000e+00) %24 = bitcast i32 %23 to float %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00) %26 = bitcast i32 %25 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %24, float %26, float %24, float %26) ret void } ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: v_cvt_pkrtz_f16_f32_e64 v0, 1.0, 0 ; D2960000 000100F2 v_cvt_pkrtz_f16_f32_e64 v1, 0, 1.0 ; D2960001 0001E480 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 28 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL CONST[0..175] DCL TEMP[0..7], LOCAL DCL ADDR[0] IMM[0] FLT32 { 765.0059, 0.0000, 0.0000, 0.0000} IMM[1] INT32 {1, 2, 0, 0} 0: MUL TEMP[0].xyz, IMM[0].xxxx, IN[2].zyxx 1: MOV TEMP[1].xyz, TEMP[0].xyzx 2: ADD TEMP[0].xy, CONST[0].yyyy, IN[1].xyyy 3: MUL TEMP[0].xy, TEMP[0].xyyy, IMM[0].yyyy 4: F2I TEMP[2].x, TEMP[1].yyyy 5: UARL ADDR[0].x, TEMP[2].xxxx 6: UARL ADDR[0].x, TEMP[2].xxxx 7: MUL TEMP[2], TEMP[0].yyyy, CONST[ADDR[0].x+14] 8: F2I TEMP[3].x, TEMP[1].xxxx 9: UARL ADDR[0].x, TEMP[3].xxxx 10: UARL ADDR[0].x, TEMP[3].xxxx 11: MAD TEMP[2], CONST[ADDR[0].x+14], TEMP[0].xxxx, TEMP[2] 12: ADD TEMP[3].x, TEMP[0].yyyy, TEMP[0].xxxx 13: ADD TEMP[3].x, -TEMP[3].xxxx, CONST[0].yyyy 14: F2I TEMP[4].x, TEMP[1].zzzz 15: UARL ADDR[0].x, TEMP[4].xxxx 16: UARL ADDR[0].x, TEMP[4].xxxx 17: MAD TEMP[2], CONST[ADDR[0].x+14], TEMP[3].xxxx, TEMP[2] 18: MOV TEMP[4].w, IN[0].wwww 19: MAD TEMP[4].xyz, IN[3].xyzz, CONST[13].xxxx, IN[0].xyzz 20: DP4 TEMP[2].x, TEMP[4], TEMP[2] 21: F2I TEMP[5].x, TEMP[1].yyyy 22: UADD TEMP[5].x, TEMP[5].xxxx, IMM[1].xxxx 23: UARL ADDR[0].x, TEMP[5].xxxx 24: UARL ADDR[0].x, TEMP[5].xxxx 25: MUL TEMP[5], TEMP[0].yyyy, CONST[ADDR[0].x+14] 26: F2I TEMP[6].x, TEMP[1].yyyy 27: UADD TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy 28: UARL ADDR[0].x, TEMP[6].xxxx 29: UARL ADDR[0].x, TEMP[6].xxxx 30: MUL TEMP[6], TEMP[0].yyyy, CONST[ADDR[0].x+14] 31: F2I TEMP[7].x, TEMP[1].xxxx 32: UADD TEMP[7].x, TEMP[7].xxxx, IMM[1].yyyy 33: UARL ADDR[0].x, TEMP[7].xxxx 34: UARL ADDR[0].x, TEMP[7].xxxx 35: MAD TEMP[6], CONST[ADDR[0].x+14], TEMP[0].xxxx, TEMP[6] 36: F2I TEMP[7].x, TEMP[1].xxxx 37: UADD TEMP[7].x, TEMP[7].xxxx, IMM[1].xxxx 38: UARL ADDR[0].x, TEMP[7].xxxx 39: UARL ADDR[0].x, TEMP[7].xxxx 40: MAD TEMP[5], CONST[ADDR[0].x+14], TEMP[0].xxxx, TEMP[5] 41: F2I TEMP[7].x, TEMP[1].zzzz 42: UADD TEMP[7].x, TEMP[7].xxxx, IMM[1].xxxx 43: UARL ADDR[0].x, TEMP[7].xxxx 44: UARL ADDR[0].x, TEMP[7].xxxx 45: MAD TEMP[5], CONST[ADDR[0].x+14], TEMP[3].xxxx, TEMP[5] 46: F2I TEMP[1].x, TEMP[1].zzzz 47: UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].yyyy 48: UARL ADDR[0].x, TEMP[1].xxxx 49: UARL ADDR[0].x, TEMP[1].xxxx 50: MAD TEMP[0], CONST[ADDR[0].x+14], TEMP[3].xxxx, TEMP[6] 51: DP4 TEMP[0].x, TEMP[4], TEMP[0] 52: MOV TEMP[2].z, TEMP[0].xxxx 53: DP4 TEMP[0].x, TEMP[4], TEMP[5] 54: MOV TEMP[2].y, TEMP[0].xxxx 55: MOV TEMP[2].w, CONST[0].yyyy 56: DP4 TEMP[0].x, TEMP[2], CONST[8] 57: DP4 TEMP[1].x, TEMP[2], CONST[9] 58: MOV TEMP[0].y, TEMP[1].xxxx 59: DP4 TEMP[3].x, TEMP[2], CONST[10] 60: MOV TEMP[0].z, TEMP[3].xxxx 61: DP4 TEMP[2].x, TEMP[2], CONST[11] 62: MOV TEMP[0].w, TEMP[2].xxxx 63: MOV TEMP[4], TEMP[0] 64: MAD TEMP[3].x, TEMP[3].xxxx, CONST[0].zzzz, -TEMP[2].xxxx 65: MOV TEMP[0].z, TEMP[3].xxxx 66: MOV TEMP[0].y, -TEMP[1].xxxx 67: MAD TEMP[0].xy, CONST[175].xyyy, TEMP[2].xxxx, TEMP[0].xyyy 68: MOV OUT[0], TEMP[0] 69: MOV OUT[1], TEMP[4] 70: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 208) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 2800) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 2804) %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !0 %37 = add i32 %5, %8 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %37) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %44 = load <16 x i8>, <16 x i8> addrspace(2)* %43, align 16, !tbaa !0 %45 = add i32 %5, %8 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %45) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %50 = load <16 x i8>, <16 x i8> addrspace(2)* %49, align 16, !tbaa !0 %51 = add i32 %5, %8 %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %51) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = extractelement <4 x float> %52, i32 2 %56 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %57 = load <16 x i8>, <16 x i8> addrspace(2)* %56, align 16, !tbaa !0 %58 = add i32 %5, %8 %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %58) %60 = extractelement <4 x float> %59, i32 0 %61 = extractelement <4 x float> %59, i32 1 %62 = extractelement <4 x float> %59, i32 2 %63 = fmul float %55, 0x4087E80C00000000 %64 = fmul float %54, 0x4087E80C00000000 %65 = fmul float %53, 0x4087E80C00000000 %66 = fadd float %14, %47 %67 = fadd float %14, %48 %68 = fmul float %66, 0x3F00000000000000 %69 = fmul float %67, 0x3F00000000000000 %70 = fptosi float %64 to i32 %71 = shl i32 %70, 4 %72 = add i32 %71, 224 %73 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %72) %74 = fmul float %69, %73 %75 = shl i32 %70, 4 %76 = add i32 %75, 228 %77 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %76) %78 = fmul float %69, %77 %79 = shl i32 %70, 4 %80 = add i32 %79, 232 %81 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %80) %82 = fmul float %69, %81 %83 = shl i32 %70, 4 %84 = add i32 %83, 236 %85 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %84) %86 = fmul float %69, %85 %87 = fptosi float %63 to i32 %88 = shl i32 %87, 4 %89 = add i32 %88, 224 %90 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %89) %91 = fmul float %90, %68 %92 = fadd float %91, %74 %93 = shl i32 %87, 4 %94 = add i32 %93, 228 %95 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %94) %96 = fmul float %95, %68 %97 = fadd float %96, %78 %98 = shl i32 %87, 4 %99 = add i32 %98, 232 %100 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %99) %101 = fmul float %100, %68 %102 = fadd float %101, %82 %103 = shl i32 %87, 4 %104 = add i32 %103, 236 %105 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %104) %106 = fmul float %105, %68 %107 = fadd float %106, %86 %108 = fadd float %69, %68 %109 = fsub float %14, %108 %110 = fptosi float %65 to i32 %111 = shl i32 %110, 4 %112 = add i32 %111, 224 %113 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %112) %114 = fmul float %113, %109 %115 = fadd float %114, %92 %116 = shl i32 %110, 4 %117 = add i32 %116, 228 %118 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %117) %119 = fmul float %118, %109 %120 = fadd float %119, %97 %121 = shl i32 %110, 4 %122 = add i32 %121, 232 %123 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %122) %124 = fmul float %123, %109 %125 = fadd float %124, %102 %126 = shl i32 %110, 4 %127 = add i32 %126, 236 %128 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %127) %129 = fmul float %128, %109 %130 = fadd float %129, %107 %131 = fmul float %60, %32 %132 = fadd float %131, %39 %133 = fmul float %61, %32 %134 = fadd float %133, %40 %135 = fmul float %62, %32 %136 = fadd float %135, %41 %137 = fmul float %132, %115 %138 = fmul float %134, %120 %139 = fadd float %137, %138 %140 = fmul float %136, %125 %141 = fadd float %139, %140 %142 = fmul float %42, %130 %143 = fadd float %141, %142 %144 = fptosi float %64 to i32 %145 = add i32 %144, 1 %146 = shl i32 %145, 4 %147 = add i32 %146, 224 %148 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %147) %149 = fmul float %69, %148 %150 = shl i32 %145, 4 %151 = add i32 %150, 228 %152 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %151) %153 = fmul float %69, %152 %154 = shl i32 %145, 4 %155 = add i32 %154, 232 %156 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %155) %157 = fmul float %69, %156 %158 = shl i32 %145, 4 %159 = add i32 %158, 236 %160 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %159) %161 = fmul float %69, %160 %162 = fptosi float %64 to i32 %163 = add i32 %162, 2 %164 = shl i32 %163, 4 %165 = add i32 %164, 224 %166 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %165) %167 = fmul float %69, %166 %168 = shl i32 %163, 4 %169 = add i32 %168, 228 %170 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %169) %171 = fmul float %69, %170 %172 = shl i32 %163, 4 %173 = add i32 %172, 232 %174 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %173) %175 = fmul float %69, %174 %176 = shl i32 %163, 4 %177 = add i32 %176, 236 %178 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %177) %179 = fmul float %69, %178 %180 = fptosi float %63 to i32 %181 = add i32 %180, 2 %182 = shl i32 %181, 4 %183 = add i32 %182, 224 %184 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %183) %185 = fmul float %184, %68 %186 = fadd float %185, %167 %187 = shl i32 %181, 4 %188 = add i32 %187, 228 %189 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %188) %190 = fmul float %189, %68 %191 = fadd float %190, %171 %192 = shl i32 %181, 4 %193 = add i32 %192, 232 %194 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %193) %195 = fmul float %194, %68 %196 = fadd float %195, %175 %197 = shl i32 %181, 4 %198 = add i32 %197, 236 %199 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %198) %200 = fmul float %199, %68 %201 = fadd float %200, %179 %202 = fptosi float %63 to i32 %203 = add i32 %202, 1 %204 = shl i32 %203, 4 %205 = add i32 %204, 224 %206 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %205) %207 = fmul float %206, %68 %208 = fadd float %207, %149 %209 = shl i32 %203, 4 %210 = add i32 %209, 228 %211 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %210) %212 = fmul float %211, %68 %213 = fadd float %212, %153 %214 = shl i32 %203, 4 %215 = add i32 %214, 232 %216 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %215) %217 = fmul float %216, %68 %218 = fadd float %217, %157 %219 = shl i32 %203, 4 %220 = add i32 %219, 236 %221 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %220) %222 = fmul float %221, %68 %223 = fadd float %222, %161 %224 = fptosi float %65 to i32 %225 = add i32 %224, 1 %226 = shl i32 %225, 4 %227 = add i32 %226, 224 %228 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %227) %229 = fmul float %228, %109 %230 = fadd float %229, %208 %231 = shl i32 %225, 4 %232 = add i32 %231, 228 %233 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %232) %234 = fmul float %233, %109 %235 = fadd float %234, %213 %236 = shl i32 %225, 4 %237 = add i32 %236, 232 %238 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %237) %239 = fmul float %238, %109 %240 = fadd float %239, %218 %241 = shl i32 %225, 4 %242 = add i32 %241, 236 %243 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %242) %244 = fmul float %243, %109 %245 = fadd float %244, %223 %246 = fptosi float %65 to i32 %247 = add i32 %246, 2 %248 = shl i32 %247, 4 %249 = add i32 %248, 224 %250 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %249) %251 = fmul float %250, %109 %252 = fadd float %251, %186 %253 = shl i32 %247, 4 %254 = add i32 %253, 228 %255 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %254) %256 = fmul float %255, %109 %257 = fadd float %256, %191 %258 = shl i32 %247, 4 %259 = add i32 %258, 232 %260 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %259) %261 = fmul float %260, %109 %262 = fadd float %261, %196 %263 = shl i32 %247, 4 %264 = add i32 %263, 236 %265 = call float @llvm.SI.load.const(<16 x i8> %13, i32 %264) %266 = fmul float %265, %109 %267 = fadd float %266, %201 %268 = fmul float %132, %252 %269 = fmul float %134, %257 %270 = fadd float %268, %269 %271 = fmul float %136, %262 %272 = fadd float %270, %271 %273 = fmul float %42, %267 %274 = fadd float %272, %273 %275 = fmul float %132, %230 %276 = fmul float %134, %235 %277 = fadd float %275, %276 %278 = fmul float %136, %240 %279 = fadd float %277, %278 %280 = fmul float %42, %245 %281 = fadd float %279, %280 %282 = fmul float %143, %16 %283 = fmul float %281, %17 %284 = fadd float %282, %283 %285 = fmul float %274, %18 %286 = fadd float %284, %285 %287 = fmul float %14, %19 %288 = fadd float %286, %287 %289 = fmul float %143, %20 %290 = fmul float %281, %21 %291 = fadd float %289, %290 %292 = fmul float %274, %22 %293 = fadd float %291, %292 %294 = fmul float %14, %23 %295 = fadd float %293, %294 %296 = fmul float %143, %24 %297 = fmul float %281, %25 %298 = fadd float %296, %297 %299 = fmul float %274, %26 %300 = fadd float %298, %299 %301 = fmul float %14, %27 %302 = fadd float %300, %301 %303 = fmul float %143, %28 %304 = fmul float %281, %29 %305 = fadd float %303, %304 %306 = fmul float %274, %30 %307 = fadd float %305, %306 %308 = fmul float %14, %31 %309 = fadd float %307, %308 %310 = fmul float %302, %15 %311 = fsub float %310, %309 %312 = fmul float %33, %309 %313 = fadd float %312, %288 %314 = fmul float %34, %309 %315 = fsub float %314, %295 %316 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %317 = load <16 x i8>, <16 x i8> addrspace(2)* %316, align 16, !tbaa !0 %318 = call float @llvm.SI.load.const(<16 x i8> %317, i32 0) %319 = fmul float %318, %288 %320 = call float @llvm.SI.load.const(<16 x i8> %317, i32 4) %321 = fmul float %320, %295 %322 = fadd float %319, %321 %323 = call float @llvm.SI.load.const(<16 x i8> %317, i32 8) %324 = fmul float %323, %302 %325 = fadd float %322, %324 %326 = call float @llvm.SI.load.const(<16 x i8> %317, i32 12) %327 = fmul float %326, %309 %328 = fadd float %325, %327 %329 = call float @llvm.SI.load.const(<16 x i8> %317, i32 16) %330 = fmul float %329, %288 %331 = call float @llvm.SI.load.const(<16 x i8> %317, i32 20) %332 = fmul float %331, %295 %333 = fadd float %330, %332 %334 = call float @llvm.SI.load.const(<16 x i8> %317, i32 24) %335 = fmul float %334, %302 %336 = fadd float %333, %335 %337 = call float @llvm.SI.load.const(<16 x i8> %317, i32 28) %338 = fmul float %337, %309 %339 = fadd float %336, %338 %340 = call float @llvm.SI.load.const(<16 x i8> %317, i32 32) %341 = fmul float %340, %288 %342 = call float @llvm.SI.load.const(<16 x i8> %317, i32 36) %343 = fmul float %342, %295 %344 = fadd float %341, %343 %345 = call float @llvm.SI.load.const(<16 x i8> %317, i32 40) %346 = fmul float %345, %302 %347 = fadd float %344, %346 %348 = call float @llvm.SI.load.const(<16 x i8> %317, i32 44) %349 = fmul float %348, %309 %350 = fadd float %347, %349 %351 = call float @llvm.SI.load.const(<16 x i8> %317, i32 48) %352 = fmul float %351, %288 %353 = call float @llvm.SI.load.const(<16 x i8> %317, i32 52) %354 = fmul float %353, %295 %355 = fadd float %352, %354 %356 = call float @llvm.SI.load.const(<16 x i8> %317, i32 56) %357 = fmul float %356, %302 %358 = fadd float %355, %357 %359 = call float @llvm.SI.load.const(<16 x i8> %317, i32 60) %360 = fmul float %359, %309 %361 = fadd float %358, %360 %362 = call float @llvm.SI.load.const(<16 x i8> %317, i32 64) %363 = fmul float %362, %288 %364 = call float @llvm.SI.load.const(<16 x i8> %317, i32 68) %365 = fmul float %364, %295 %366 = fadd float %363, %365 %367 = call float @llvm.SI.load.const(<16 x i8> %317, i32 72) %368 = fmul float %367, %302 %369 = fadd float %366, %368 %370 = call float @llvm.SI.load.const(<16 x i8> %317, i32 76) %371 = fmul float %370, %309 %372 = fadd float %369, %371 %373 = call float @llvm.SI.load.const(<16 x i8> %317, i32 80) %374 = fmul float %373, %288 %375 = call float @llvm.SI.load.const(<16 x i8> %317, i32 84) %376 = fmul float %375, %295 %377 = fadd float %374, %376 %378 = call float @llvm.SI.load.const(<16 x i8> %317, i32 88) %379 = fmul float %378, %302 %380 = fadd float %377, %379 %381 = call float @llvm.SI.load.const(<16 x i8> %317, i32 92) %382 = fmul float %381, %309 %383 = fadd float %380, %382 %384 = call float @llvm.SI.load.const(<16 x i8> %317, i32 96) %385 = fmul float %384, %288 %386 = call float @llvm.SI.load.const(<16 x i8> %317, i32 100) %387 = fmul float %386, %295 %388 = fadd float %385, %387 %389 = call float @llvm.SI.load.const(<16 x i8> %317, i32 104) %390 = fmul float %389, %302 %391 = fadd float %388, %390 %392 = call float @llvm.SI.load.const(<16 x i8> %317, i32 108) %393 = fmul float %392, %309 %394 = fadd float %391, %393 %395 = call float @llvm.SI.load.const(<16 x i8> %317, i32 112) %396 = fmul float %395, %288 %397 = call float @llvm.SI.load.const(<16 x i8> %317, i32 116) %398 = fmul float %397, %295 %399 = fadd float %396, %398 %400 = call float @llvm.SI.load.const(<16 x i8> %317, i32 120) %401 = fmul float %400, %302 %402 = fadd float %399, %401 %403 = call float @llvm.SI.load.const(<16 x i8> %317, i32 124) %404 = fmul float %403, %309 %405 = fadd float %402, %404 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %313, float %315, float %311, float %309) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %328, float %339, float %350, float %361) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %372, float %383, float %394, float %405) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[2:3], 0x100 ; C00A0101 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[8:9], 0x0 ; C00A0004 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x30 ; C00A0604 00000030 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 0x443f4060 ; 7E0202FF 443F4060 s_movk_i32 s9, 0xf4 ; B00900F4 s_movk_i32 s10, 0xe4 ; B00A00E4 s_movk_i32 s11, 0xf0 ; B00B00F0 s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[2:5], v0, s[0:3], 0 idxen ; E00C2000 80000200 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v0, s[16:19], 0 idxen ; E00C2000 80040600 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[8:11], v0, s[20:23], 0 idxen ; E00C2000 80050800 s_movk_i32 s16, 0xe0 ; B01000E0 s_movk_i32 s17, 0xf8 ; B01100F8 s_movk_i32 s18, 0x104 ; B0120104 s_movk_i32 s19, 0xe8 ; B01300E8 s_movk_i32 s20, 0xfc ; B01400FC s_movk_i32 s21, 0x100 ; B0150100 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[11:14], v0, s[24:27], 0 idxen ; E00C2000 80060B00 s_movk_i32 s22, 0xec ; B01600EC s_movk_i32 s23, 0x108 ; B0170108 s_movk_i32 s24, 0x10c ; B018010C s_buffer_load_dword s0, s[12:15], 0x4 ; C0220006 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x8 ; C0220046 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x80 ; C02200C6 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x84 ; C0220206 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x88 ; C0220086 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0xd0 ; C0220646 000000D0 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v0, s0, v7 ; 02000E00 v_mul_f32_e32 v7, v1, v9 ; 0A0E1301 v_mul_f32_e32 v9, v1, v10 ; 0A121501 v_cvt_i32_f32_e32 v7, v7 ; 7E0E1107 v_mul_f32_e32 v1, v1, v8 ; 0A021101 v_cvt_i32_f32_e32 v8, v9 ; 7E101109 v_cvt_i32_f32_e32 v1, v1 ; 7E021101 v_lshlrev_b32_e32 v7, 4, v7 ; 240E0E84 v_lshlrev_b32_e32 v8, 4, v8 ; 24101084 v_lshlrev_b32_e32 v1, 4, v1 ; 24020284 v_add_i32_e32 v9, vcc, s16, v7 ; 32120E10 v_add_i32_e32 v10, vcc, s10, v7 ; 32140E0A s_waitcnt vmcnt(0) ; BF8C0770 v_add_i32_e32 v14, vcc, s19, v7 ; 321C0E13 v_add_i32_e32 v15, vcc, s22, v7 ; 321E0E16 v_add_i32_e32 v16, vcc, s11, v7 ; 32200E0B v_add_i32_e32 v17, vcc, s9, v7 ; 32220E09 v_add_i32_e32 v18, vcc, s17, v7 ; 32240E11 v_add_i32_e32 v19, vcc, s20, v7 ; 32260E14 v_add_i32_e32 v20, vcc, s21, v7 ; 32280E15 v_add_i32_e32 v21, vcc, s18, v7 ; 322A0E12 v_add_i32_e32 v22, vcc, s23, v7 ; 322C0E17 v_add_i32_e32 v7, vcc, s24, v7 ; 320E0E18 v_add_i32_e32 v23, vcc, s16, v8 ; 322E1010 v_add_i32_e32 v24, vcc, s10, v8 ; 3230100A v_add_i32_e32 v25, vcc, s19, v8 ; 32321013 v_add_i32_e32 v26, vcc, s22, v8 ; 32341016 v_add_i32_e32 v27, vcc, s21, v8 ; 32361015 v_add_i32_e32 v28, vcc, s18, v8 ; 32381012 v_add_i32_e32 v29, vcc, s23, v8 ; 323A1017 v_add_i32_e32 v30, vcc, s24, v8 ; 323C1018 v_add_i32_e32 v31, vcc, s11, v8 ; 323E100B v_add_i32_e32 v32, vcc, s9, v8 ; 32401009 v_add_i32_e32 v33, vcc, s17, v8 ; 32421011 v_add_i32_e32 v8, vcc, s20, v8 ; 32101014 buffer_load_dword v9, v9, s[12:15], 0 offen ; E0501000 80030909 s_nop 0 ; BF800000 buffer_load_dword v10, v10, s[12:15], 0 offen ; E0501000 80030A0A s_nop 0 ; BF800000 buffer_load_dword v14, v14, s[12:15], 0 offen ; E0501000 80030E0E s_nop 0 ; BF800000 buffer_load_dword v15, v15, s[12:15], 0 offen ; E0501000 80030F0F s_nop 0 ; BF800000 buffer_load_dword v23, v23, s[12:15], 0 offen ; E0501000 80031717 s_nop 0 ; BF800000 buffer_load_dword v24, v24, s[12:15], 0 offen ; E0501000 80031818 s_nop 0 ; BF800000 buffer_load_dword v25, v25, s[12:15], 0 offen ; E0501000 80031919 s_nop 0 ; BF800000 buffer_load_dword v26, v26, s[12:15], 0 offen ; E0501000 80031A1A v_add_i32_e32 v34, vcc, s16, v1 ; 32440210 buffer_load_dword v34, v34, s[12:15], 0 offen ; E0501000 80032222 v_add_i32_e32 v35, vcc, s10, v1 ; 3246020A buffer_load_dword v35, v35, s[12:15], 0 offen ; E0501000 80032323 v_add_i32_e32 v36, vcc, s19, v1 ; 32480213 buffer_load_dword v36, v36, s[12:15], 0 offen ; E0501000 80032424 v_add_i32_e32 v37, vcc, s22, v1 ; 324A0216 buffer_load_dword v37, v37, s[12:15], 0 offen ; E0501000 80032525 s_nop 0 ; BF800000 buffer_load_dword v16, v16, s[12:15], 0 offen ; E0501000 80031010 s_nop 0 ; BF800000 buffer_load_dword v17, v17, s[12:15], 0 offen ; E0501000 80031111 s_nop 0 ; BF800000 buffer_load_dword v18, v18, s[12:15], 0 offen ; E0501000 80031212 s_nop 0 ; BF800000 buffer_load_dword v19, v19, s[12:15], 0 offen ; E0501000 80031313 s_nop 0 ; BF800000 buffer_load_dword v20, v20, s[12:15], 0 offen ; E0501000 80031414 s_nop 0 ; BF800000 buffer_load_dword v21, v21, s[12:15], 0 offen ; E0501000 80031515 s_nop 0 ; BF800000 buffer_load_dword v22, v22, s[12:15], 0 offen ; E0501000 80031616 s_nop 0 ; BF800000 buffer_load_dword v7, v7, s[12:15], 0 offen ; E0501000 80030707 s_nop 0 ; BF800000 buffer_load_dword v27, v27, s[12:15], 0 offen ; E0501000 80031B1B s_nop 0 ; BF800000 buffer_load_dword v28, v28, s[12:15], 0 offen ; E0501000 80031C1C s_nop 0 ; BF800000 buffer_load_dword v29, v29, s[12:15], 0 offen ; E0501000 80031D1D s_nop 0 ; BF800000 buffer_load_dword v30, v30, s[12:15], 0 offen ; E0501000 80031E1E s_nop 0 ; BF800000 buffer_load_dword v31, v31, s[12:15], 0 offen ; E0501000 80031F1F s_nop 0 ; BF800000 buffer_load_dword v32, v32, s[12:15], 0 offen ; E0501000 80032020 s_nop 0 ; BF800000 buffer_load_dword v33, v33, s[12:15], 0 offen ; E0501000 80032121 s_nop 0 ; BF800000 buffer_load_dword v8, v8, s[12:15], 0 offen ; E0501000 80030808 v_add_i32_e32 v38, vcc, s11, v1 ; 324C020B buffer_load_dword v38, v38, s[12:15], 0 offen ; E0501000 80032626 v_add_i32_e32 v39, vcc, s9, v1 ; 324E0209 buffer_load_dword v39, v39, s[12:15], 0 offen ; E0501000 80032727 v_add_i32_e32 v40, vcc, s17, v1 ; 32500211 buffer_load_dword v40, v40, s[12:15], 0 offen ; E0501000 80032828 v_add_i32_e32 v41, vcc, s20, v1 ; 32520214 buffer_load_dword v41, v41, s[12:15], 0 offen ; E0501000 80032929 v_add_i32_e32 v42, vcc, s21, v1 ; 32540215 buffer_load_dword v42, v42, s[12:15], 0 offen ; E0501000 80032A2A v_add_i32_e32 v43, vcc, s18, v1 ; 32560212 v_add_i32_e32 v44, vcc, s23, v1 ; 32580217 v_add_i32_e32 v1, vcc, s24, v1 ; 32020218 buffer_load_dword v43, v43, s[12:15], 0 offen ; E0501000 80032B2B s_nop 0 ; BF800000 buffer_load_dword v44, v44, s[12:15], 0 offen ; E0501000 80032C2C s_nop 0 ; BF800000 buffer_load_dword v1, v1, s[12:15], 0 offen ; E0501000 80030101 v_add_f32_e32 v6, s0, v6 ; 020C0C00 s_buffer_load_dword s9, s[12:15], 0xaf0 ; C0220246 00000AF0 v_mad_f32 v2, s25, v11, v2 ; D1C10002 040A1619 v_mad_f32 v3, s25, v12, v3 ; D1C10003 040E1819 v_mad_f32 v4, s25, v13, v4 ; D1C10004 04121A19 v_mov_b32_e32 v11, 0x38000000 ; 7E1602FF 38000000 v_mul_f32_e32 v12, v11, v6 ; 0A180D0B v_mad_f32 v6, -v6, v11, s0 ; D1C10006 20021706 v_mad_f32 v6, -v0, v11, v6 ; D1C10006 241A1700 v_mul_f32_e32 v0, v11, v0 ; 0A00010B s_waitcnt ; BF8C077F v_mul_f32_e32 v9, v9, v0 ; 0A120109 v_mul_f32_e32 v10, v10, v0 ; 0A14010A v_mul_f32_e32 v11, v14, v0 ; 0A16010E v_mul_f32_e32 v13, v15, v0 ; 0A1A010F v_mul_f32_e32 v14, v16, v0 ; 0A1C0110 v_mul_f32_e32 v15, v17, v0 ; 0A1E0111 v_mul_f32_e32 v16, v18, v0 ; 0A200112 v_mul_f32_e32 v17, v19, v0 ; 0A220113 v_mul_f32_e32 v18, v20, v0 ; 0A240114 v_mul_f32_e32 v19, v21, v0 ; 0A260115 v_mul_f32_e32 v20, v22, v0 ; 0A280116 v_mul_f32_e32 v0, v7, v0 ; 0A000107 v_mac_f32_e32 v9, v12, v23 ; 2C122F0C v_mac_f32_e32 v10, v12, v24 ; 2C14310C v_mac_f32_e32 v11, v12, v25 ; 2C16330C v_mac_f32_e32 v13, v12, v26 ; 2C1A350C v_mac_f32_e32 v18, v12, v27 ; 2C24370C s_waitcnt vmcnt(14) ; BF8C077E v_mac_f32_e32 v19, v12, v28 ; 2C26390C s_waitcnt vmcnt(13) ; BF8C077D v_mac_f32_e32 v20, v12, v29 ; 2C283B0C s_waitcnt vmcnt(12) ; BF8C077C v_mac_f32_e32 v0, v12, v30 ; 2C003D0C s_waitcnt vmcnt(11) ; BF8C077B v_mac_f32_e32 v14, v12, v31 ; 2C1C3F0C s_waitcnt vmcnt(10) ; BF8C077A v_mac_f32_e32 v15, v12, v32 ; 2C1E410C s_waitcnt vmcnt(9) ; BF8C0779 v_mac_f32_e32 v16, v12, v33 ; 2C20430C s_waitcnt vmcnt(8) ; BF8C0778 v_mac_f32_e32 v17, v12, v8 ; 2C22110C v_mac_f32_e32 v9, v6, v34 ; 2C124506 v_mac_f32_e32 v10, v6, v35 ; 2C144706 v_mac_f32_e32 v11, v6, v36 ; 2C164906 v_mac_f32_e32 v13, v6, v37 ; 2C1A4B06 s_waitcnt vmcnt(7) ; BF8C0777 v_mac_f32_e32 v14, v6, v38 ; 2C1C4D06 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v15, v6, v39 ; 2C1E4F06 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v16, v6, v40 ; 2C205106 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v17, v6, v41 ; 2C225306 s_buffer_load_dword s10, s[12:15], 0xb4 ; C0220286 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0xb8 ; C02202C6 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0xbc ; C0220406 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x8c ; C0220446 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x90 ; C0220486 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x94 ; C02204C6 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x98 ; C0220506 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x9c ; C0220546 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0xa0 ; C0220586 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0xa4 ; C02205C6 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0xa8 ; C0220606 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0xac ; C0220646 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0xb0 ; C0220686 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0xaf4 ; C0220306 00000AF4 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x0 ; C0220342 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x4 ; C0220382 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x8 ; C02203C2 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0xc ; C02206C2 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x10 ; C0220702 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x14 ; C0220742 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0x18 ; C0220782 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x1c ; C02207C2 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x20 ; C0220802 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x24 ; C0220842 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x28 ; C0220882 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x2c ; C02208C2 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x30 ; C0220902 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x34 ; C0220942 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[4:7], 0x38 ; C0220982 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[4:7], 0x3c ; C02209C2 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s40, s[4:7], 0x40 ; C0220A02 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[4:7], 0x44 ; C0220A42 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[4:7], 0x48 ; C0220A82 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[4:7], 0x4c ; C0220AC2 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s44, s[4:7], 0x50 ; C0220B02 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[4:7], 0x54 ; C0220B42 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[4:7], 0x58 ; C0220B82 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[4:7], 0x5c ; C0220BC2 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s48, s[4:7], 0x60 ; C0220C02 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s49, s[4:7], 0x64 ; C0220C42 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s50, s[4:7], 0x68 ; C0220C82 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s51, s[4:7], 0x6c ; C0220CC2 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s52, s[4:7], 0x70 ; C0220D02 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s53, s[4:7], 0x74 ; C0220D42 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s54, s[4:7], 0x78 ; C0220D82 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x7c ; C0220102 0000007C s_waitcnt vmcnt(3) ; BF8C0773 v_mac_f32_e32 v18, v6, v42 ; 2C245506 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v7, s17 ; 7E0E0211 v_mul_f32_e32 v8, v10, v3 ; 0A10070A v_mac_f32_e32 v8, v9, v2 ; 2C100509 v_mov_b32_e32 v9, s21 ; 7E120215 v_mul_f32_e32 v10, v15, v3 ; 0A14070F v_mac_f32_e32 v10, v14, v2 ; 2C14050E v_mov_b32_e32 v12, s25 ; 7E180219 v_mac_f32_e32 v10, v16, v4 ; 2C140910 v_mov_b32_e32 v14, s16 ; 7E1C0210 v_mac_f32_e32 v10, v17, v5 ; 2C140B11 v_mul_f32_e32 v15, s8, v10 ; 0A1E1408 v_mac_f32_e32 v8, v11, v4 ; 2C10090B v_mul_f32_e32 v11, s19, v10 ; 0A161413 v_mac_f32_e32 v8, v13, v5 ; 2C100B0D v_mul_f32_e32 v13, s23, v10 ; 0A1A1417 v_mul_f32_e32 v10, s10, v10 ; 0A14140A v_mac_f32_e32 v15, s3, v8 ; 2C1E1003 v_mac_f32_e32 v11, s18, v8 ; 2C161012 v_mac_f32_e32 v13, s22, v8 ; 2C1A1016 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v19, v6, v43 ; 2C265706 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v20, v6, v44 ; 2C285906 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v0, v6, v1 ; 2C000306 v_mul_f32_e32 v1, v19, v3 ; 0A020713 v_mac_f32_e32 v1, v18, v2 ; 2C020512 v_mac_f32_e32 v1, v20, v4 ; 2C020914 v_mac_f32_e32 v1, v0, v5 ; 2C020B00 v_mac_f32_e32 v10, s26, v8 ; 2C14101A v_mac_f32_e32 v15, s2, v1 ; 2C1E0202 v_mac_f32_e32 v11, s20, v1 ; 2C160214 v_mac_f32_e32 v13, s24, v1 ; 2C1A0218 v_mac_f32_e32 v10, s11, v1 ; 2C14020B v_mac_f32_e32 v15, s0, v7 ; 2C1E0E00 v_mac_f32_e32 v11, s0, v9 ; 2C161200 v_mac_f32_e32 v13, s0, v12 ; 2C1A1800 v_mac_f32_e32 v10, s0, v14 ; 2C141C00 v_mad_f32 v0, v13, s1, -v10 ; D1C10000 8428030D v_mad_f32 v1, s9, v10, v15 ; D1C10001 043E1409 v_mad_f32 v2, s12, v10, -v11 ; D1C10002 842E140C v_mul_f32_e32 v3, s14, v11 ; 0A06160E v_mul_f32_e32 v4, s29, v11 ; 0A08161D v_mul_f32_e32 v5, s33, v11 ; 0A0A1621 v_mul_f32_e32 v6, s37, v11 ; 0A0C1625 v_mul_f32_e32 v7, s41, v11 ; 0A0E1629 v_mul_f32_e32 v8, s45, v11 ; 0A10162D v_mul_f32_e32 v9, s49, v11 ; 0A121631 v_mul_f32_e32 v11, s53, v11 ; 0A161635 v_mac_f32_e32 v3, s13, v15 ; 2C061E0D v_mac_f32_e32 v4, s28, v15 ; 2C081E1C v_mac_f32_e32 v5, s32, v15 ; 2C0A1E20 v_mac_f32_e32 v6, s36, v15 ; 2C0C1E24 v_mac_f32_e32 v7, s40, v15 ; 2C0E1E28 v_mac_f32_e32 v8, s44, v15 ; 2C101E2C v_mac_f32_e32 v9, s48, v15 ; 2C121E30 v_mac_f32_e32 v11, s52, v15 ; 2C161E34 v_mac_f32_e32 v3, s15, v13 ; 2C061A0F v_mac_f32_e32 v4, s30, v13 ; 2C081A1E v_mac_f32_e32 v5, s34, v13 ; 2C0A1A22 v_mac_f32_e32 v6, s38, v13 ; 2C0C1A26 v_mac_f32_e32 v7, s42, v13 ; 2C0E1A2A v_mac_f32_e32 v8, s46, v13 ; 2C101A2E v_mac_f32_e32 v9, s50, v13 ; 2C121A32 v_mac_f32_e32 v11, s54, v13 ; 2C161A36 v_mac_f32_e32 v3, s27, v10 ; 2C06141B v_mac_f32_e32 v4, s31, v10 ; 2C08141F v_mac_f32_e32 v5, s35, v10 ; 2C0A1423 v_mac_f32_e32 v6, s39, v10 ; 2C0C1427 v_mac_f32_e32 v7, s43, v10 ; 2C0E142B v_mac_f32_e32 v8, s47, v10 ; 2C10142F v_mac_f32_e32 v9, s51, v10 ; 2C121433 v_mac_f32_e32 v11, s4, v10 ; 2C161404 exp 15, 12, 0, 0, 0, v1, v2, v0, v10 ; C40000CF 0A000201 exp 15, 13, 0, 0, 0, v3, v4, v5, v6 ; C40000DF 06050403 exp 15, 14, 0, 1, 0, v7, v8, v9, v11 ; C40008EF 0B090807 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 64 VGPRS: 48 Code Size: 1960 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL OUT[0], COLOR IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xyyx 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 0.000000e+00) %24 = bitcast i32 %23 to float %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00) %26 = bitcast i32 %25 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %24, float %26, float %24, float %26) ret void } ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: v_cvt_pkrtz_f16_f32_e64 v0, 1.0, 0 ; D2960000 000100F2 v_cvt_pkrtz_f16_f32_e64 v1, 0, 1.0 ; D2960001 0001E480 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 28 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL CONST[0..57] DCL TEMP[0..6], LOCAL IMM[0] FLT32 { -5.0000, 3.0000, 4.0000, -3.0000} IMM[1] FLT32 { 1.0000, -0.5000, 0.0000, 0.0000} 0: ADD TEMP[0], IN[1], IN[1] 1: MAD TEMP[1], IN[2], IMM[0].xxxx, TEMP[0] 2: MAD TEMP[0], IN[2], IMM[0].yyyy, -IN[1] 3: MAD TEMP[1], IN[3], IMM[0].zzzz, TEMP[1] 4: MAD TEMP[0], IN[3], IMM[0].wwww, TEMP[0] 5: ADD TEMP[2], TEMP[1], -IN[4] 6: ADD TEMP[3], TEMP[0], IN[4] 7: MAD TEMP[0], IN[0].xxxx, TEMP[3], TEMP[2] 8: ADD TEMP[1], IN[3], -IN[1] 9: MAD TEMP[1], IN[0].xxxx, TEMP[0], TEMP[1] 10: MUL TEMP[4].x, IN[0].xxxx, CONST[0].wwww 11: MAD TEMP[0], TEMP[4].xxxx, TEMP[1], IN[2] 12: MAD TEMP[4], TEMP[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 13: DP4 TEMP[5].x, TEMP[4], CONST[48] 14: DP4 TEMP[6].x, TEMP[4], CONST[49] 15: MOV TEMP[5].y, TEMP[6].xxxx 16: DP4 TEMP[6].x, TEMP[4], CONST[50] 17: MOV TEMP[5].z, TEMP[6].xxxx 18: MAD TEMP[4].xyz, TEMP[0].wwww, CONST[0].yxxx, TEMP[5].xyzz 19: MOV TEMP[4].w, CONST[0].yyyy 20: DP4 TEMP[6].x, TEMP[4], CONST[54] 21: RCP TEMP[6].x, TEMP[6].xxxx 22: MOV TEMP[5].w, CONST[0].yyyy 23: DP4 TEMP[4].x, TEMP[4], CONST[51] 24: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx 25: DP4 TEMP[6].x, TEMP[5], CONST[54] 26: RCP TEMP[6].x, TEMP[6].xxxx 27: MUL TEMP[3].xyz, TEMP[3].xyzz, IN[0].xxxx 28: DP4 TEMP[5].x, TEMP[5], CONST[51] 29: MAD TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx, -TEMP[4].xxxx 30: ABS TEMP[4].x, TEMP[4].xxxx 31: MAD TEMP[2].xyz, CONST[0].zzzz, TEMP[3].yzxx, TEMP[2].yzxx 32: RCP TEMP[5].x, TEMP[4].xxxx 33: MAD TEMP[1].xyz, IN[0].xxxx, TEMP[2].xyzz, TEMP[1].yzxx 34: FSLT TEMP[4].x, TEMP[4].xxxx, CONST[55].xxxx 35: AND TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx 36: MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[0].wwww 37: MUL TEMP[5].x, TEMP[5].xxxx, CONST[55].xxxx 38: MAD TEMP[5].x, TEMP[0].wwww, TEMP[5].xxxx, -TEMP[0].wwww 39: DP3 TEMP[6].x, TEMP[1].xyzz, TEMP[1].xyzz 40: RSQ TEMP[6].x, TEMP[6].xxxx 41: MUL TEMP[6].xyz, TEMP[1].xyzz, TEMP[6].xxxx 42: ADD TEMP[1].xyz, TEMP[0].zxyy, -CONST[2].zxyy 43: MAD TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx, TEMP[0].wwww 44: MUL TEMP[3].xyz, TEMP[6].xyzz, TEMP[1].xyzz 45: ADD TEMP[5].x, IN[0].zzzz, IMM[1].yyyy 46: MAD TEMP[2].xyz, TEMP[1].zxyy, TEMP[6].yzxx, -TEMP[3].xyzz 47: MUL TEMP[3].x, TEMP[4].xxxx, TEMP[5].xxxx 48: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[2].xyzz 49: RSQ TEMP[4].x, TEMP[4].xxxx 50: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[4].xxxx 51: MAD TEMP[0].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[0].xyzz 52: MOV TEMP[0].w, CONST[0].yyyy 53: DP4 TEMP[2].x, TEMP[0], CONST[8] 54: DP4 TEMP[3].x, TEMP[0], CONST[9] 55: MOV TEMP[2].y, TEMP[3].xxxx 56: DP4 TEMP[4].x, TEMP[0], CONST[11] 57: MOV TEMP[1].w, TEMP[4].xxxx 58: DP4 TEMP[0].x, TEMP[0], CONST[10] 59: MOV TEMP[1].z, TEMP[0].xxxx 60: MOV TEMP[2].zw, TEMP[1].wwzw 61: MOV TEMP[1], TEMP[2] 62: MAD TEMP[0].x, TEMP[0].xxxx, CONST[0].zzzz, -TEMP[4].xxxx 63: MOV TEMP[2].z, TEMP[0].xxxx 64: MOV TEMP[2].y, -TEMP[3].xxxx 65: MAD TEMP[2].xy, CONST[57].xyyy, TEMP[4].xxxx, TEMP[2].xyyy 66: MOV OUT[0], TEMP[2] 67: MOV OUT[1], TEMP[1] 68: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 12) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 32) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 36) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 40) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %48 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %49 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %50 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %51 = call float @llvm.SI.load.const(<16 x i8> %13, i32 824) %52 = call float @llvm.SI.load.const(<16 x i8> %13, i32 828) %53 = call float @llvm.SI.load.const(<16 x i8> %13, i32 864) %54 = call float @llvm.SI.load.const(<16 x i8> %13, i32 868) %55 = call float @llvm.SI.load.const(<16 x i8> %13, i32 872) %56 = call float @llvm.SI.load.const(<16 x i8> %13, i32 876) %57 = call float @llvm.SI.load.const(<16 x i8> %13, i32 880) %58 = call float @llvm.SI.load.const(<16 x i8> %13, i32 912) %59 = call float @llvm.SI.load.const(<16 x i8> %13, i32 916) %60 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %61 = load <16 x i8>, <16 x i8> addrspace(2)* %60, align 16, !tbaa !0 %62 = add i32 %5, %8 %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %62) %64 = extractelement <4 x float> %63, i32 0 %65 = extractelement <4 x float> %63, i32 2 %66 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %67 = load <16 x i8>, <16 x i8> addrspace(2)* %66, align 16, !tbaa !0 %68 = add i32 %5, %8 %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %68) %70 = extractelement <4 x float> %69, i32 0 %71 = extractelement <4 x float> %69, i32 1 %72 = extractelement <4 x float> %69, i32 2 %73 = extractelement <4 x float> %69, i32 3 %74 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %75 = load <16 x i8>, <16 x i8> addrspace(2)* %74, align 16, !tbaa !0 %76 = add i32 %5, %8 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %76) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = extractelement <4 x float> %77, i32 2 %81 = extractelement <4 x float> %77, i32 3 %82 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %83 = load <16 x i8>, <16 x i8> addrspace(2)* %82, align 16, !tbaa !0 %84 = add i32 %5, %8 %85 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %83, i32 0, i32 %84) %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = extractelement <4 x float> %85, i32 2 %89 = extractelement <4 x float> %85, i32 3 %90 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %91 = load <16 x i8>, <16 x i8> addrspace(2)* %90, align 16, !tbaa !0 %92 = add i32 %5, %8 %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %91, i32 0, i32 %92) %94 = extractelement <4 x float> %93, i32 0 %95 = extractelement <4 x float> %93, i32 1 %96 = extractelement <4 x float> %93, i32 2 %97 = extractelement <4 x float> %93, i32 3 %98 = fadd float %70, %70 %99 = fadd float %71, %71 %100 = fadd float %72, %72 %101 = fadd float %73, %73 %102 = fmul float %78, -5.000000e+00 %103 = fadd float %102, %98 %104 = fmul float %79, -5.000000e+00 %105 = fadd float %104, %99 %106 = fmul float %80, -5.000000e+00 %107 = fadd float %106, %100 %108 = fmul float %81, -5.000000e+00 %109 = fadd float %108, %101 %110 = fmul float %78, 3.000000e+00 %111 = fsub float %110, %70 %112 = fmul float %79, 3.000000e+00 %113 = fsub float %112, %71 %114 = fmul float %80, 3.000000e+00 %115 = fsub float %114, %72 %116 = fmul float %81, 3.000000e+00 %117 = fsub float %116, %73 %118 = fmul float %86, 4.000000e+00 %119 = fadd float %118, %103 %120 = fmul float %87, 4.000000e+00 %121 = fadd float %120, %105 %122 = fmul float %88, 4.000000e+00 %123 = fadd float %122, %107 %124 = fmul float %89, 4.000000e+00 %125 = fadd float %124, %109 %126 = fmul float %86, -3.000000e+00 %127 = fadd float %126, %111 %128 = fmul float %87, -3.000000e+00 %129 = fadd float %128, %113 %130 = fmul float %88, -3.000000e+00 %131 = fadd float %130, %115 %132 = fmul float %89, -3.000000e+00 %133 = fadd float %132, %117 %134 = fsub float %119, %94 %135 = fsub float %121, %95 %136 = fsub float %123, %96 %137 = fsub float %125, %97 %138 = fadd float %127, %94 %139 = fadd float %129, %95 %140 = fadd float %131, %96 %141 = fadd float %133, %97 %142 = fmul float %64, %138 %143 = fadd float %142, %134 %144 = fmul float %64, %139 %145 = fadd float %144, %135 %146 = fmul float %64, %140 %147 = fadd float %146, %136 %148 = fmul float %64, %141 %149 = fadd float %148, %137 %150 = fsub float %86, %70 %151 = fsub float %87, %71 %152 = fsub float %88, %72 %153 = fsub float %89, %73 %154 = fmul float %64, %143 %155 = fadd float %154, %150 %156 = fmul float %64, %145 %157 = fadd float %156, %151 %158 = fmul float %64, %147 %159 = fadd float %158, %152 %160 = fmul float %64, %149 %161 = fadd float %160, %153 %162 = fmul float %64, %17 %163 = fmul float %162, %155 %164 = fadd float %163, %78 %165 = fmul float %162, %157 %166 = fadd float %165, %79 %167 = fmul float %162, %159 %168 = fadd float %167, %80 %169 = fmul float %162, %161 %170 = fadd float %169, %81 %171 = fmul float %164, %15 %172 = fadd float %171, %14 %173 = fmul float %166, %15 %174 = fadd float %173, %14 %175 = fmul float %168, %15 %176 = fadd float %175, %14 %177 = fmul float %164, %14 %178 = fadd float %177, %15 %179 = fmul float %172, %37 %180 = fmul float %174, %38 %181 = fadd float %179, %180 %182 = fmul float %176, %39 %183 = fadd float %181, %182 %184 = fmul float %178, %40 %185 = fadd float %183, %184 %186 = fmul float %172, %41 %187 = fmul float %174, %42 %188 = fadd float %186, %187 %189 = fmul float %176, %43 %190 = fadd float %188, %189 %191 = fmul float %178, %44 %192 = fadd float %190, %191 %193 = fmul float %172, %45 %194 = fmul float %174, %46 %195 = fadd float %193, %194 %196 = fmul float %176, %47 %197 = fadd float %195, %196 %198 = fmul float %178, %48 %199 = fadd float %197, %198 %200 = fmul float %170, %15 %201 = fadd float %200, %185 %202 = fmul float %170, %14 %203 = fadd float %202, %192 %204 = fmul float %170, %14 %205 = fadd float %204, %199 %206 = fmul float %201, %53 %207 = fmul float %203, %54 %208 = fadd float %206, %207 %209 = fmul float %205, %55 %210 = fadd float %208, %209 %211 = fmul float %15, %56 %212 = fadd float %210, %211 %213 = fdiv float 1.000000e+00, %212 %214 = fmul float %201, %49 %215 = fmul float %203, %50 %216 = fadd float %214, %215 %217 = fmul float %205, %51 %218 = fadd float %216, %217 %219 = fmul float %15, %52 %220 = fadd float %218, %219 %221 = fmul float %220, %213 %222 = fmul float %185, %53 %223 = fmul float %192, %54 %224 = fadd float %222, %223 %225 = fmul float %199, %55 %226 = fadd float %224, %225 %227 = fmul float %15, %56 %228 = fadd float %226, %227 %229 = fdiv float 1.000000e+00, %228 %230 = fmul float %138, %64 %231 = fmul float %139, %64 %232 = fmul float %140, %64 %233 = fmul float %185, %49 %234 = fmul float %192, %50 %235 = fadd float %233, %234 %236 = fmul float %199, %51 %237 = fadd float %235, %236 %238 = fmul float %15, %52 %239 = fadd float %237, %238 %240 = fmul float %239, %229 %241 = fsub float %240, %221 %242 = call float @llvm.fabs.f32(float %241) %243 = fmul float %16, %231 %244 = fadd float %243, %135 %245 = fmul float %16, %232 %246 = fadd float %245, %136 %247 = fmul float %16, %230 %248 = fadd float %247, %134 %249 = fdiv float 1.000000e+00, %242 %250 = fmul float %64, %244 %251 = fadd float %250, %157 %252 = fmul float %64, %246 %253 = fadd float %252, %159 %254 = fmul float %64, %248 %255 = fadd float %254, %155 %256 = fcmp olt float %242, %57 %257 = select i1 %256, float 1.000000e+00, float 0.000000e+00 %258 = fmul float %251, %17 %259 = fmul float %253, %17 %260 = fmul float %255, %17 %261 = fmul float %249, %57 %262 = fmul float %170, %261 %263 = fsub float %262, %170 %264 = fmul float %258, %258 %265 = fmul float %259, %259 %266 = fadd float %265, %264 %267 = fmul float %260, %260 %268 = fadd float %266, %267 %269 = call float @llvm.AMDGPU.rsq.clamped.f32(float %268) %270 = fmul float %258, %269 %271 = fmul float %259, %269 %272 = fmul float %260, %269 %273 = fsub float %168, %20 %274 = fsub float %164, %18 %275 = fsub float %166, %19 %276 = fmul float %257, %263 %277 = fadd float %276, %170 %278 = fmul float %270, %273 %279 = fmul float %271, %274 %280 = fmul float %272, %275 %281 = fadd float %65, -5.000000e-01 %282 = fmul float %275, %271 %283 = fsub float %282, %278 %284 = fmul float %273, %272 %285 = fsub float %284, %279 %286 = fmul float %274, %270 %287 = fsub float %286, %280 %288 = fmul float %277, %281 %289 = fmul float %283, %283 %290 = fmul float %285, %285 %291 = fadd float %290, %289 %292 = fmul float %287, %287 %293 = fadd float %291, %292 %294 = call float @llvm.AMDGPU.rsq.clamped.f32(float %293) %295 = fmul float %283, %294 %296 = fmul float %285, %294 %297 = fmul float %287, %294 %298 = fmul float %295, %288 %299 = fadd float %298, %164 %300 = fmul float %296, %288 %301 = fadd float %300, %166 %302 = fmul float %297, %288 %303 = fadd float %302, %168 %304 = fmul float %299, %21 %305 = fmul float %301, %22 %306 = fadd float %304, %305 %307 = fmul float %303, %23 %308 = fadd float %306, %307 %309 = fmul float %15, %24 %310 = fadd float %308, %309 %311 = fmul float %299, %25 %312 = fmul float %301, %26 %313 = fadd float %311, %312 %314 = fmul float %303, %27 %315 = fadd float %313, %314 %316 = fmul float %15, %28 %317 = fadd float %315, %316 %318 = fmul float %299, %33 %319 = fmul float %301, %34 %320 = fadd float %318, %319 %321 = fmul float %303, %35 %322 = fadd float %320, %321 %323 = fmul float %15, %36 %324 = fadd float %322, %323 %325 = fmul float %299, %29 %326 = fmul float %301, %30 %327 = fadd float %325, %326 %328 = fmul float %303, %31 %329 = fadd float %327, %328 %330 = fmul float %15, %32 %331 = fadd float %329, %330 %332 = fmul float %331, %16 %333 = fsub float %332, %324 %334 = fmul float %58, %324 %335 = fadd float %334, %310 %336 = fmul float %59, %324 %337 = fsub float %336, %317 %338 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %339 = load <16 x i8>, <16 x i8> addrspace(2)* %338, align 16, !tbaa !0 %340 = call float @llvm.SI.load.const(<16 x i8> %339, i32 0) %341 = fmul float %340, %310 %342 = call float @llvm.SI.load.const(<16 x i8> %339, i32 4) %343 = fmul float %342, %317 %344 = fadd float %341, %343 %345 = call float @llvm.SI.load.const(<16 x i8> %339, i32 8) %346 = fmul float %345, %331 %347 = fadd float %344, %346 %348 = call float @llvm.SI.load.const(<16 x i8> %339, i32 12) %349 = fmul float %348, %324 %350 = fadd float %347, %349 %351 = call float @llvm.SI.load.const(<16 x i8> %339, i32 16) %352 = fmul float %351, %310 %353 = call float @llvm.SI.load.const(<16 x i8> %339, i32 20) %354 = fmul float %353, %317 %355 = fadd float %352, %354 %356 = call float @llvm.SI.load.const(<16 x i8> %339, i32 24) %357 = fmul float %356, %331 %358 = fadd float %355, %357 %359 = call float @llvm.SI.load.const(<16 x i8> %339, i32 28) %360 = fmul float %359, %324 %361 = fadd float %358, %360 %362 = call float @llvm.SI.load.const(<16 x i8> %339, i32 32) %363 = fmul float %362, %310 %364 = call float @llvm.SI.load.const(<16 x i8> %339, i32 36) %365 = fmul float %364, %317 %366 = fadd float %363, %365 %367 = call float @llvm.SI.load.const(<16 x i8> %339, i32 40) %368 = fmul float %367, %331 %369 = fadd float %366, %368 %370 = call float @llvm.SI.load.const(<16 x i8> %339, i32 44) %371 = fmul float %370, %324 %372 = fadd float %369, %371 %373 = call float @llvm.SI.load.const(<16 x i8> %339, i32 48) %374 = fmul float %373, %310 %375 = call float @llvm.SI.load.const(<16 x i8> %339, i32 52) %376 = fmul float %375, %317 %377 = fadd float %374, %376 %378 = call float @llvm.SI.load.const(<16 x i8> %339, i32 56) %379 = fmul float %378, %331 %380 = fadd float %377, %379 %381 = call float @llvm.SI.load.const(<16 x i8> %339, i32 60) %382 = fmul float %381, %324 %383 = fadd float %380, %382 %384 = call float @llvm.SI.load.const(<16 x i8> %339, i32 64) %385 = fmul float %384, %310 %386 = call float @llvm.SI.load.const(<16 x i8> %339, i32 68) %387 = fmul float %386, %317 %388 = fadd float %385, %387 %389 = call float @llvm.SI.load.const(<16 x i8> %339, i32 72) %390 = fmul float %389, %331 %391 = fadd float %388, %390 %392 = call float @llvm.SI.load.const(<16 x i8> %339, i32 76) %393 = fmul float %392, %324 %394 = fadd float %391, %393 %395 = call float @llvm.SI.load.const(<16 x i8> %339, i32 80) %396 = fmul float %395, %310 %397 = call float @llvm.SI.load.const(<16 x i8> %339, i32 84) %398 = fmul float %397, %317 %399 = fadd float %396, %398 %400 = call float @llvm.SI.load.const(<16 x i8> %339, i32 88) %401 = fmul float %400, %331 %402 = fadd float %399, %401 %403 = call float @llvm.SI.load.const(<16 x i8> %339, i32 92) %404 = fmul float %403, %324 %405 = fadd float %402, %404 %406 = call float @llvm.SI.load.const(<16 x i8> %339, i32 96) %407 = fmul float %406, %310 %408 = call float @llvm.SI.load.const(<16 x i8> %339, i32 100) %409 = fmul float %408, %317 %410 = fadd float %407, %409 %411 = call float @llvm.SI.load.const(<16 x i8> %339, i32 104) %412 = fmul float %411, %331 %413 = fadd float %410, %412 %414 = call float @llvm.SI.load.const(<16 x i8> %339, i32 108) %415 = fmul float %414, %324 %416 = fadd float %413, %415 %417 = call float @llvm.SI.load.const(<16 x i8> %339, i32 112) %418 = fmul float %417, %310 %419 = call float @llvm.SI.load.const(<16 x i8> %339, i32 116) %420 = fmul float %419, %317 %421 = fadd float %418, %420 %422 = call float @llvm.SI.load.const(<16 x i8> %339, i32 120) %423 = fmul float %422, %331 %424 = fadd float %421, %423 %425 = call float @llvm.SI.load.const(<16 x i8> %339, i32 124) %426 = fmul float %425, %324 %427 = fadd float %424, %426 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %335, float %337, float %333, float %324) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %350, float %361, float %372, float %383) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %394, float %405, float %416, float %427) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[2:3], 0x100 ; C00A0001 00000100 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x0 ; C00A0704 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x10 ; C00A0604 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x30 ; C00A0404 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[8:9], 0x40 ; C00A0304 00000040 v_add_i32_e32 v0, vcc, s10, v0 ; 3200000A v_mov_b32_e32 v1, 0x40400000 ; 7E0202FF 40400000 s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[2:5], v0, s[28:31], 0 idxen ; E00C2000 80070200 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[5:8], v0, s[24:27], 0 idxen ; E00C2000 80060500 s_nop 0 ; BF800000 buffer_load_format_xyzw v[9:12], v0, s[20:23], 0 idxen ; E00C2000 80050900 s_nop 0 ; BF800000 buffer_load_format_xyzw v[13:16], v0, s[16:19], 0 idxen ; E00C2000 80040D00 s_nop 0 ; BF800000 buffer_load_format_xyzw v[17:20], v0, s[12:15], 0 idxen ; E00C2000 80031100 s_waitcnt vmcnt(2) ; BF8C0772 v_mad_f32 v0, v9, v1, -v5 ; D1C10000 84160309 v_mad_f32 v3, v10, v1, -v6 ; D1C10003 841A030A v_mad_f32 v21, v11, v1, -v7 ; D1C10015 841E030B v_mad_f32 v1, v12, v1, -v8 ; D1C10001 8422030C v_add_f32_e32 v22, v5, v5 ; 022C0B05 v_add_f32_e32 v23, v6, v6 ; 022E0D06 v_add_f32_e32 v24, v7, v7 ; 02300F07 v_add_f32_e32 v25, v8, v8 ; 02321108 s_waitcnt vmcnt(1) ; BF8C0771 v_subrev_f32_e32 v5, v5, v13 ; 060A1B05 v_subrev_f32_e32 v6, v6, v14 ; 060C1D06 v_subrev_f32_e32 v7, v7, v15 ; 060E1F07 v_subrev_f32_e32 v8, v8, v16 ; 06102108 v_mov_b32_e32 v26, 0xc0a00000 ; 7E3402FF C0A00000 v_mac_f32_e32 v22, v26, v9 ; 2C2C131A v_mac_f32_e32 v23, v26, v10 ; 2C2E151A v_mac_f32_e32 v24, v26, v11 ; 2C30171A v_mac_f32_e32 v25, v26, v12 ; 2C32191A v_mov_b32_e32 v26, 0xc0400000 ; 7E3402FF C0400000 v_mac_f32_e32 v0, v26, v13 ; 2C001B1A v_mac_f32_e32 v3, v26, v14 ; 2C061D1A v_mac_f32_e32 v21, v26, v15 ; 2C2A1F1A v_mac_f32_e32 v1, v26, v16 ; 2C02211A v_mac_f32_e32 v22, 4.0, v13 ; 2C2C1AF6 v_mac_f32_e32 v23, 4.0, v14 ; 2C2E1CF6 v_mac_f32_e32 v24, 4.0, v15 ; 2C301EF6 v_mac_f32_e32 v25, 4.0, v16 ; 2C3220F6 s_buffer_load_dword s10, s[4:7], 0xc ; C0220282 0000000C s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v0, v17, v0 ; 02000111 v_add_f32_e32 v3, v18, v3 ; 02060712 v_add_f32_e32 v13, v19, v21 ; 021A2B13 v_add_f32_e32 v1, v20, v1 ; 02020314 v_subrev_f32_e32 v14, v17, v22 ; 061C2D11 v_subrev_f32_e32 v15, v18, v23 ; 061E2F12 v_subrev_f32_e32 v16, v19, v24 ; 06203113 v_subrev_f32_e32 v17, v20, v25 ; 06223314 s_buffer_load_dword s8, s[4:7], 0x8 ; C0220202 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x20 ; C02202C2 00000020 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s10, v2 ; 0A24040A v_mad_f32 v19, v0, v2, v14 ; D1C10013 043A0500 v_mac_f32_e32 v17, v1, v2 ; 2C220501 v_mad_f32 v1, v3, v2, v15 ; D1C10001 043E0503 v_mac_f32_e32 v5, v19, v2 ; 2C0A0513 v_mad_f32 v19, v13, v2, v16 ; D1C10013 0442050D v_mac_f32_e32 v6, v1, v2 ; 2C0C0501 v_mac_f32_e32 v7, v19, v2 ; 2C0E0513 v_mac_f32_e32 v8, v17, v2 ; 2C100511 v_mad_f32 v1, v5, v18, v9 ; D1C10001 04262505 v_mad_f32 v9, v6, v18, v10 ; D1C10009 042A2506 v_mad_f32 v10, v7, v18, v11 ; D1C1000A 042E2507 v_mac_f32_e32 v12, v8, v18 ; 2C182508 s_buffer_load_dword s12, s[4:7], 0x0 ; C0220302 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x4 ; C0220242 00000004 v_mul_f32_e32 v3, v3, v2 ; 0A060503 v_mac_f32_e32 v15, s8, v3 ; 2C1E0608 v_mov_b32_e32 v3, 0x7f7fffff ; 7E0602FF 7F7FFFFF v_mul_f32_e32 v8, v13, v2 ; 0A10050D v_mac_f32_e32 v16, s8, v8 ; 2C201008 v_mov_b32_e32 v8, 0xff7fffff ; 7E1002FF FF7FFFFF s_buffer_load_dword s13, s[4:7], 0x24 ; C0220342 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x28 ; C0220382 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x80 ; C02203C2 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x84 ; C0220402 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x88 ; C0220442 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x300 ; C0220482 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x304 ; C02204C2 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x308 ; C0220502 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x30c ; C0220542 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x310 ; C0220582 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x314 ; C02205C2 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x318 ; C0220602 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x31c ; C0220642 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0x320 ; C0220682 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x324 ; C02206C2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x328 ; C0220702 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x32c ; C0220742 0000032C v_mul_f32_e32 v0, v0, v2 ; 0A000500 v_mac_f32_e32 v14, s8, v0 ; 2C1C0008 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v0, s12 ; 7E00020C v_mac_f32_e32 v6, v15, v2 ; 2C0C050F v_mov_b32_e32 v11, s9 ; 7E160209 v_mac_f32_e32 v7, v16, v2 ; 2C0E0510 v_add_f32_e32 v4, -0.5, v4 ; 020808F1 v_mac_f32_e32 v5, v14, v2 ; 2C0A050E v_mad_f32 v2, s9, v1, v0 ; D1C10002 04020209 v_mad_f32 v13, s9, v9, v0 ; D1C1000D 04021209 v_mad_f32 v0, s9, v10, v0 ; D1C10000 04021409 v_mad_f32 v11, s12, v1, v11 ; D1C1000B 042E020C v_mul_f32_e32 v6, s10, v6 ; 0A0C0C0A v_mul_f32_e32 v7, s10, v7 ; 0A0E0E0A v_mul_f32_e32 v5, s10, v5 ; 0A0A0A0A v_subrev_f32_e32 v14, s14, v10 ; 061C140E v_mul_f32_e32 v15, s19, v13 ; 0A1E1A13 v_mul_f32_e32 v16, s23, v13 ; 0A201A17 v_mul_f32_e32 v13, s27, v13 ; 0A1A1A1B v_mac_f32_e32 v15, s18, v2 ; 2C1E0412 v_mac_f32_e32 v16, s22, v2 ; 2C200416 v_mac_f32_e32 v13, s26, v2 ; 2C1A041A v_subrev_f32_e32 v2, s11, v1 ; 0604020B v_mac_f32_e32 v15, s20, v0 ; 2C1E0014 v_mac_f32_e32 v16, s24, v0 ; 2C200018 v_mac_f32_e32 v13, s28, v0 ; 2C1A001C v_mul_f32_e32 v0, v6, v6 ; 0A000D06 v_mac_f32_e32 v0, v7, v7 ; 2C000F07 v_mac_f32_e32 v0, v5, v5 ; 2C000B05 v_mac_f32_e32 v15, s21, v11 ; 2C1E1615 v_rsq_f32_e32 v0, v0 ; 7E004900 v_mac_f32_e32 v16, s25, v11 ; 2C201619 v_mac_f32_e32 v13, s29, v11 ; 2C1A161D v_subrev_f32_e32 v11, s13, v9 ; 0616120D v_min_f32_e32 v0, v3, v0 ; 14000103 v_max_f32_e32 v0, v8, v0 ; 16000108 v_mul_f32_e32 v6, v0, v6 ; 0A0C0D00 v_mul_f32_e32 v7, v0, v7 ; 0A0E0F00 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_mul_f32_e32 v5, v14, v6 ; 0A0A0D0E v_mad_f32 v5, v11, v7, -v5 ; D1C10005 84160F0B v_mul_f32_e32 v7, v2, v7 ; 0A0E0F02 v_mad_f32 v7, v14, v0, -v7 ; D1C10007 841E010E s_buffer_load_dword s10, s[4:7], 0x364 ; C0220282 00000364 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x330 ; C02202C2 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x334 ; C0220342 00000334 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x338 ; C0220382 00000338 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x33c ; C0220482 0000033C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x360 ; C02204C2 00000360 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x368 ; C0220502 00000368 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0x36c ; C0220542 0000036C s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0x370 ; C0220582 00000370 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0x390 ; C02205C2 00000390 v_mul_f32_e32 v0, v11, v0 ; 0A00010B v_mad_f32 v11, s9, v12, v15 ; D1C1000B 043E1809 v_mad_f32 v0, v2, v6, -v0 ; D1C10000 84020D02 v_mad_f32 v2, s12, v12, v16 ; D1C10002 0442180C s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v6, s10, v16 ; 0A0C200A v_mul_f32_e32 v14, s13, v16 ; 0A1C200D v_mac_f32_e32 v6, s19, v15 ; 2C0C1E13 v_mac_f32_e32 v14, s11, v15 ; 2C1C1E0B v_mul_f32_e32 v15, s10, v2 ; 0A1E040A v_mul_f32_e32 v2, s13, v2 ; 0A04040D v_mac_f32_e32 v15, s19, v11 ; 2C1E1613 v_mac_f32_e32 v2, s11, v11 ; 2C04160B v_mac_f32_e32 v6, s20, v13 ; 2C0C1A14 v_mac_f32_e32 v14, s14, v13 ; 2C1C1A0E v_mad_f32 v11, s12, v12, v13 ; D1C1000B 0436180C v_mac_f32_e32 v15, s20, v11 ; 2C1E1614 v_mac_f32_e32 v2, s14, v11 ; 2C04160E v_mov_b32_e32 v11, s21 ; 7E160215 v_mac_f32_e32 v6, s9, v11 ; 2C0C1609 v_mac_f32_e32 v15, s9, v11 ; 2C1E1609 v_mov_b32_e32 v11, s18 ; 7E160212 v_rcp_f32_e32 v13, v15 ; 7E1A450F v_rcp_f32_e32 v6, v6 ; 7E0C4506 v_mac_f32_e32 v14, s9, v11 ; 2C1C1609 v_mac_f32_e32 v2, s9, v11 ; 2C041609 v_mul_f32_e32 v2, v13, v2 ; 0A04050D v_mad_f32 v2, v14, v6, -v2 ; D1C10002 840A0D0E v_mul_f32_e32 v6, v5, v5 ; 0A0C0B05 v_mac_f32_e32 v6, v7, v7 ; 2C0C0F07 v_mac_f32_e32 v6, v0, v0 ; 2C0C0100 v_rcp_f32_e64 v11, |v2| ; D162010B 00000102 v_cmp_lt_f32_e64 s[10:11], |v2|, s22 ; D041010A 00002D02 v_rsq_f32_e32 v2, v6 ; 7E044906 v_cndmask_b32_e64 v6, 0, 1.0, s[10:11] ; D1000006 0029E480 v_mul_f32_e32 v11, s22, v11 ; 0A161616 v_mad_f32 v11, v12, v11, -v12 ; D1C1000B 8432170C v_mac_f32_e32 v12, v11, v6 ; 2C180D0B v_mul_f32_e32 v4, v4, v12 ; 0A081904 v_min_f32_e32 v2, v3, v2 ; 14040503 v_max_f32_e32 v2, v8, v2 ; 16040508 s_buffer_load_dword s10, s[4:7], 0xb4 ; C0220282 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0xb8 ; C02202C2 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0xbc ; C0220302 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x8c ; C0220342 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x90 ; C0220382 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x94 ; C0220482 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0x98 ; C02204C2 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0x9c ; C0220502 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0xa0 ; C0220542 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0xa4 ; C0220582 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0xa8 ; C0220602 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0xac ; C0220642 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s26, s[4:7], 0xb0 ; C0220682 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[4:7], 0x394 ; C0220102 00000394 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x0 ; C0220140 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x4 ; C0220180 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x8 ; C02201C0 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[0:3], 0xc ; C02206C0 0000000C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[0:3], 0x10 ; C0220700 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[0:3], 0x14 ; C0220740 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[0:3], 0x18 ; C0220780 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[0:3], 0x1c ; C02207C0 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s32, s[0:3], 0x20 ; C0220800 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[0:3], 0x24 ; C0220840 00000024 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[0:3], 0x28 ; C0220880 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[0:3], 0x2c ; C02208C0 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[0:3], 0x30 ; C0220900 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[0:3], 0x34 ; C0220940 00000034 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[0:3], 0x38 ; C0220980 00000038 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[0:3], 0x3c ; C02209C0 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s40, s[0:3], 0x40 ; C0220A00 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[0:3], 0x44 ; C0220A40 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[0:3], 0x48 ; C0220A80 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[0:3], 0x4c ; C0220AC0 0000004C v_mul_f32_e32 v3, v2, v5 ; 0A060B02 v_mul_f32_e32 v5, v2, v7 ; 0A0A0F02 v_mul_f32_e32 v0, v2, v0 ; 0A000102 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v2, s13 ; 7E04020D v_mac_f32_e32 v1, v4, v3 ; 2C020704 v_mov_b32_e32 v3, s20 ; 7E060214 v_mac_f32_e32 v9, v4, v5 ; 2C120B04 v_mac_f32_e32 v10, v4, v0 ; 2C140104 v_mul_f32_e32 v0, s16, v9 ; 0A001210 v_mul_f32_e32 v4, s18, v9 ; 0A081212 v_mul_f32_e32 v5, s10, v9 ; 0A0A120A v_mul_f32_e32 v6, s22, v9 ; 0A0C1216 v_mac_f32_e32 v0, s15, v1 ; 2C00020F v_mac_f32_e32 v4, s14, v1 ; 2C08020E v_mac_f32_e32 v5, s26, v1 ; 2C0A021A v_mac_f32_e32 v6, s21, v1 ; 2C0C0215 v_mov_b32_e32 v1, s12 ; 7E02020C v_mac_f32_e32 v0, s17, v10 ; 2C001411 v_mac_f32_e32 v4, s19, v10 ; 2C081413 v_mac_f32_e32 v5, s11, v10 ; 2C0A140B v_mac_f32_e32 v6, s24, v10 ; 2C0C1418 v_mov_b32_e32 v7, s25 ; 7E0E0219 v_mac_f32_e32 v0, s9, v2 ; 2C000409 v_mac_f32_e32 v4, s9, v3 ; 2C080609 v_mac_f32_e32 v5, s9, v1 ; 2C0A0209 v_mac_f32_e32 v6, s9, v7 ; 2C0C0E09 v_mad_f32 v1, v6, s8, -v5 ; D1C10001 84141106 v_mad_f32 v2, s23, v5, v0 ; D1C10002 04020A17 v_mad_f32 v3, s4, v5, -v4 ; D1C10003 84120A04 v_mul_f32_e32 v7, s6, v4 ; 0A0E0806 exp 15, 12, 0, 0, 0, v2, v3, v1, v5 ; C40000CF 05010302 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v1, s29, v4 ; 0A02081D v_mul_f32_e32 v2, s33, v4 ; 0A040821 v_mul_f32_e32 v3, s37, v4 ; 0A060825 v_mac_f32_e32 v7, s5, v0 ; 2C0E0005 v_mac_f32_e32 v1, s28, v0 ; 2C02001C v_mac_f32_e32 v2, s32, v0 ; 2C040020 v_mac_f32_e32 v3, s36, v0 ; 2C060024 v_mac_f32_e32 v7, s7, v6 ; 2C0E0C07 v_mac_f32_e32 v1, s30, v6 ; 2C020C1E v_mac_f32_e32 v2, s34, v6 ; 2C040C22 v_mac_f32_e32 v3, s38, v6 ; 2C060C26 v_mac_f32_e32 v7, s27, v5 ; 2C0E0A1B v_mac_f32_e32 v1, s31, v5 ; 2C020A1F v_mac_f32_e32 v2, s35, v5 ; 2C040A23 v_mac_f32_e32 v3, s39, v5 ; 2C060A27 exp 15, 13, 0, 0, 0, v7, v1, v2, v3 ; C40000DF 03020107 s_buffer_load_dword s4, s[0:3], 0x64 ; C0220100 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[0:3], 0x74 ; C0220140 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[0:3], 0x50 ; C0220180 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[0:3], 0x54 ; C02201C0 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[0:3], 0x58 ; C0220200 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[0:3], 0x5c ; C0220240 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s10, s[0:3], 0x60 ; C0220280 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[0:3], 0x68 ; C02202C0 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[0:3], 0x6c ; C0220300 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[0:3], 0x70 ; C0220340 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[0:3], 0x78 ; C0220380 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[0:3], 0x7c ; C0220000 0000007C s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v1, s41, v4 ; 0A020829 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v2, s7, v4 ; 0A040807 v_mul_f32_e32 v3, s4, v4 ; 0A060804 v_mul_f32_e32 v4, s5, v4 ; 0A080805 v_mac_f32_e32 v1, s40, v0 ; 2C020028 v_mac_f32_e32 v2, s6, v0 ; 2C040006 v_mac_f32_e32 v3, s10, v0 ; 2C06000A v_mac_f32_e32 v4, s13, v0 ; 2C08000D v_mac_f32_e32 v1, s42, v6 ; 2C020C2A v_mac_f32_e32 v2, s8, v6 ; 2C040C08 v_mac_f32_e32 v3, s11, v6 ; 2C060C0B v_mac_f32_e32 v4, s14, v6 ; 2C080C0E v_mac_f32_e32 v1, s43, v5 ; 2C020A2B v_mac_f32_e32 v2, s9, v5 ; 2C040A09 v_mac_f32_e32 v3, s12, v5 ; 2C060A0C v_mac_f32_e32 v4, s0, v5 ; 2C080A00 exp 15, 14, 0, 1, 0, v1, v2, v3, v4 ; C40008EF 04030201 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 28 Code Size: 2044 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL OUT[0], COLOR IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00) %24 = bitcast i32 %23 to float %25 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00) %26 = bitcast i32 %25 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %24, float %26, float %24, float %26) ret void } ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } Shader Disassembly: v_cvt_pkrtz_f16_f32_e64 v0, 0, 0 ; D2960000 00010080 v_cvt_pkrtz_f16_f32_e64 v1, 0, 1.0 ; D2960001 0001E480 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 8 VGPRS: 4 Code Size: 28 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], COLOR[1] DCL OUT[3], CLIPVERTEX DCL OUT[4], GENERIC[0] DCL OUT[5], GENERIC[1] DCL OUT[6], GENERIC[2] DCL OUT[7], GENERIC[3] DCL CONST[0..51] DCL TEMP[0..7], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].yzw, IMM[0].xxxx 2: MOV TEMP[2].w, CONST[0].yyyy 3: MAD TEMP[3], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 4: DP4 TEMP[2].x, TEMP[3], CONST[48] 5: DP4 TEMP[4].x, TEMP[3], CONST[49] 6: MOV TEMP[2].y, TEMP[4].xxxx 7: DP4 TEMP[3].x, TEMP[3], CONST[50] 8: MOV TEMP[2].z, TEMP[3].xxxx 9: DP4 TEMP[3].x, TEMP[2], CONST[8] 10: DP4 TEMP[4].x, TEMP[2], CONST[9] 11: MOV TEMP[3].y, TEMP[4].xxxx 12: DP4 TEMP[5].x, TEMP[2], CONST[11] 13: MOV TEMP[3].w, TEMP[5].xxxx 14: DP4 TEMP[6].x, TEMP[2], CONST[10] 15: MOV TEMP[2].w, TEMP[6].xxxx 16: MOV TEMP[3].z, TEMP[6].xxxx 17: MOV TEMP[2], TEMP[2] 18: MOV TEMP[0].xy, IN[1].xyxx 19: MOV TEMP[1].x, IN[3].wwww 20: MOV TEMP[7], TEMP[3] 21: MAD TEMP[6].x, TEMP[6].xxxx, CONST[0].zzzz, -TEMP[5].xxxx 22: MOV TEMP[3].z, TEMP[6].xxxx 23: MOV TEMP[3].y, -TEMP[4].xxxx 24: MAD TEMP[3].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[3].xyyy 25: MUL TEMP[4], CONST[0].yyxx, IN[2].xyxx 26: MUL TEMP[5], CONST[0].xxyy, IN[1].xxxy 27: MAD TEMP[6], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 28: MOV OUT[2], TEMP[1] 29: MOV OUT[4], TEMP[0] 30: MOV OUT[6], TEMP[4] 31: MOV OUT[7], TEMP[5] 32: MOV OUT[5], TEMP[2] 33: MOV OUT[0], TEMP[3] 34: MOV OUT[3], TEMP[7] 35: MOV OUT[1], TEMP[6] 36: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, align 16, !tbaa !0 %69 = add i32 %5, %8 %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69) %71 = extractelement <4 x float> %70, i32 3 %72 = fmul float %52, %15 %73 = fadd float %72, %14 %74 = fmul float %53, %15 %75 = fadd float %74, %14 %76 = fmul float %54, %15 %77 = fadd float %76, %14 %78 = fmul float %52, %14 %79 = fadd float %78, %15 %80 = fmul float %73, %34 %81 = fmul float %75, %35 %82 = fadd float %80, %81 %83 = fmul float %77, %36 %84 = fadd float %82, %83 %85 = fmul float %79, %37 %86 = fadd float %84, %85 %87 = fmul float %73, %38 %88 = fmul float %75, %39 %89 = fadd float %87, %88 %90 = fmul float %77, %40 %91 = fadd float %89, %90 %92 = fmul float %79, %41 %93 = fadd float %91, %92 %94 = fmul float %73, %42 %95 = fmul float %75, %43 %96 = fadd float %94, %95 %97 = fmul float %77, %44 %98 = fadd float %96, %97 %99 = fmul float %79, %45 %100 = fadd float %98, %99 %101 = fmul float %86, %17 %102 = fmul float %93, %18 %103 = fadd float %101, %102 %104 = fmul float %100, %19 %105 = fadd float %103, %104 %106 = fmul float %15, %20 %107 = fadd float %105, %106 %108 = fmul float %86, %21 %109 = fmul float %93, %22 %110 = fadd float %108, %109 %111 = fmul float %100, %23 %112 = fadd float %110, %111 %113 = fmul float %15, %24 %114 = fadd float %112, %113 %115 = fmul float %86, %29 %116 = fmul float %93, %30 %117 = fadd float %115, %116 %118 = fmul float %100, %31 %119 = fadd float %117, %118 %120 = fmul float %15, %32 %121 = fadd float %119, %120 %122 = fmul float %86, %25 %123 = fmul float %93, %26 %124 = fadd float %122, %123 %125 = fmul float %100, %27 %126 = fadd float %124, %125 %127 = fmul float %15, %28 %128 = fadd float %126, %127 %129 = fmul float %128, %16 %130 = fsub float %129, %121 %131 = fmul float %46, %121 %132 = fadd float %131, %107 %133 = fmul float %47, %121 %134 = fsub float %133, %114 %135 = fmul float %15, %65 %136 = fmul float %15, %66 %137 = fmul float %14, %65 %138 = fmul float %14, %65 %139 = fmul float %14, %59 %140 = fmul float %14, %59 %141 = fmul float %15, %59 %142 = fmul float %15, %60 %143 = fmul float %33, %14 %144 = fadd float %143, %15 %145 = fmul float %33, %14 %146 = fadd float %145, %15 %147 = fmul float %33, %14 %148 = fadd float %147, %15 %149 = fmul float %33, %15 %150 = fadd float %149, %14 %151 = and i32 %7, 1 %152 = icmp eq i32 %151, 0 br i1 %152, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %153 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00) %154 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00) %155 = call float @llvm.AMDIL.clamp.(float %148, float 0.000000e+00, float 1.000000e+00) %156 = call float @llvm.AMDIL.clamp.(float %150, float 0.000000e+00, float 1.000000e+00) %157 = call float @llvm.AMDIL.clamp.(float %71, float 0.000000e+00, float 1.000000e+00) %158 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %159 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %160 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.038 = phi float [ %160, %if-true-block ], [ 0.000000e+00, %main_body ] %.037 = phi float [ %159, %if-true-block ], [ 0.000000e+00, %main_body ] %.036 = phi float [ %158, %if-true-block ], [ 0.000000e+00, %main_body ] %.035 = phi float [ %157, %if-true-block ], [ %71, %main_body ] %.034 = phi float [ %156, %if-true-block ], [ %150, %main_body ] %.033 = phi float [ %155, %if-true-block ], [ %148, %main_body ] %.032 = phi float [ %154, %if-true-block ], [ %146, %main_body ] %.0 = phi float [ %153, %if-true-block ], [ %144, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.032, float %.033, float %.034) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %.035, float %.036, float %.037, float %.038) %161 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %162 = load <16 x i8>, <16 x i8> addrspace(2)* %161, align 16, !tbaa !0 %163 = call float @llvm.SI.load.const(<16 x i8> %162, i32 0) %164 = fmul float %163, %107 %165 = call float @llvm.SI.load.const(<16 x i8> %162, i32 4) %166 = fmul float %165, %114 %167 = fadd float %164, %166 %168 = call float @llvm.SI.load.const(<16 x i8> %162, i32 8) %169 = fmul float %168, %128 %170 = fadd float %167, %169 %171 = call float @llvm.SI.load.const(<16 x i8> %162, i32 12) %172 = fmul float %171, %121 %173 = fadd float %170, %172 %174 = call float @llvm.SI.load.const(<16 x i8> %162, i32 16) %175 = fmul float %174, %107 %176 = call float @llvm.SI.load.const(<16 x i8> %162, i32 20) %177 = fmul float %176, %114 %178 = fadd float %175, %177 %179 = call float @llvm.SI.load.const(<16 x i8> %162, i32 24) %180 = fmul float %179, %128 %181 = fadd float %178, %180 %182 = call float @llvm.SI.load.const(<16 x i8> %162, i32 28) %183 = fmul float %182, %121 %184 = fadd float %181, %183 %185 = call float @llvm.SI.load.const(<16 x i8> %162, i32 32) %186 = fmul float %185, %107 %187 = call float @llvm.SI.load.const(<16 x i8> %162, i32 36) %188 = fmul float %187, %114 %189 = fadd float %186, %188 %190 = call float @llvm.SI.load.const(<16 x i8> %162, i32 40) %191 = fmul float %190, %128 %192 = fadd float %189, %191 %193 = call float @llvm.SI.load.const(<16 x i8> %162, i32 44) %194 = fmul float %193, %121 %195 = fadd float %192, %194 %196 = call float @llvm.SI.load.const(<16 x i8> %162, i32 48) %197 = fmul float %196, %107 %198 = call float @llvm.SI.load.const(<16 x i8> %162, i32 52) %199 = fmul float %198, %114 %200 = fadd float %197, %199 %201 = call float @llvm.SI.load.const(<16 x i8> %162, i32 56) %202 = fmul float %201, %128 %203 = fadd float %200, %202 %204 = call float @llvm.SI.load.const(<16 x i8> %162, i32 60) %205 = fmul float %204, %121 %206 = fadd float %203, %205 %207 = call float @llvm.SI.load.const(<16 x i8> %162, i32 64) %208 = fmul float %207, %107 %209 = call float @llvm.SI.load.const(<16 x i8> %162, i32 68) %210 = fmul float %209, %114 %211 = fadd float %208, %210 %212 = call float @llvm.SI.load.const(<16 x i8> %162, i32 72) %213 = fmul float %212, %128 %214 = fadd float %211, %213 %215 = call float @llvm.SI.load.const(<16 x i8> %162, i32 76) %216 = fmul float %215, %121 %217 = fadd float %214, %216 %218 = call float @llvm.SI.load.const(<16 x i8> %162, i32 80) %219 = fmul float %218, %107 %220 = call float @llvm.SI.load.const(<16 x i8> %162, i32 84) %221 = fmul float %220, %114 %222 = fadd float %219, %221 %223 = call float @llvm.SI.load.const(<16 x i8> %162, i32 88) %224 = fmul float %223, %128 %225 = fadd float %222, %224 %226 = call float @llvm.SI.load.const(<16 x i8> %162, i32 92) %227 = fmul float %226, %121 %228 = fadd float %225, %227 %229 = call float @llvm.SI.load.const(<16 x i8> %162, i32 96) %230 = fmul float %229, %107 %231 = call float @llvm.SI.load.const(<16 x i8> %162, i32 100) %232 = fmul float %231, %114 %233 = fadd float %230, %232 %234 = call float @llvm.SI.load.const(<16 x i8> %162, i32 104) %235 = fmul float %234, %128 %236 = fadd float %233, %235 %237 = call float @llvm.SI.load.const(<16 x i8> %162, i32 108) %238 = fmul float %237, %121 %239 = fadd float %236, %238 %240 = call float @llvm.SI.load.const(<16 x i8> %162, i32 112) %241 = fmul float %240, %107 %242 = call float @llvm.SI.load.const(<16 x i8> %162, i32 116) %243 = fmul float %242, %114 %244 = fadd float %241, %243 %245 = call float @llvm.SI.load.const(<16 x i8> %162, i32 120) %246 = fmul float %245, %128 %247 = fadd float %244, %246 %248 = call float @llvm.SI.load.const(<16 x i8> %162, i32 124) %249 = fmul float %248, %121 %250 = fadd float %247, %249 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %86, float %93, float %100, float %128) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %135, float %136, float %137, float %138) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %139, float %140, float %141, float %142) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %132, float %134, float %130, float %121) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %173, float %184, float %195, float %206) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %217, float %228, float %239, float %250) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[36:39], s[2:3], 0x0 ; C00A0901 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x10 ; C00A0604 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x20 ; C00A0704 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[8:9], 0x30 ; C00A0804 00000030 v_add_i32_e32 v6, vcc, s10, v0 ; 320C000A s_and_b32 s0, 1, s12 ; 86000C81 v_cmp_eq_i32_e64 s[40:41], 1, s0 ; D0C20028 00000081 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[36:39], 0x0 ; C0220012 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[36:39], 0x4 ; C0220A92 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[36:39], 0x8 ; C0220052 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[36:39], 0x80 ; C0220452 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[36:39], 0x84 ; C0220552 00000084 buffer_load_format_xyzw v[8:11], v6, s[4:7], 0 idxen ; E00C2000 80010806 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v6, s[24:27], 0 idxen ; E00C2000 80060006 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[2:5], v6, s[28:31], 0 idxen ; E00C2000 80070206 s_waitcnt vmcnt(0) ; BF8C0770 buffer_load_format_xyzw v[4:7], v6, s[32:35], 0 idxen ; E00C2000 80080406 s_buffer_load_dword s12, s[36:39], 0xb0 ; C0220312 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[36:39], 0xb4 ; C0220352 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[36:39], 0xb8 ; C02202D2 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[36:39], 0xbc ; C0220112 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s34, s[36:39], 0x2fc ; C0220892 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s20, s[36:39], 0x88 ; C0220512 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[36:39], 0x8c ; C02204D2 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[36:39], 0x90 ; C0220412 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[36:39], 0x94 ; C0220492 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[36:39], 0x98 ; C02203D2 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[36:39], 0x9c ; C0220392 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s5, s[36:39], 0xa0 ; C0220152 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[36:39], 0xa4 ; C0220212 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[36:39], 0xa8 ; C0220192 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[36:39], 0xac ; C02201D2 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s32, s[36:39], 0x300 ; C0220812 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[36:39], 0x304 ; C0220852 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[36:39], 0x308 ; C02207D2 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[36:39], 0x30c ; C0220792 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[36:39], 0x310 ; C0220712 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[36:39], 0x314 ; C0220752 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[36:39], 0x318 ; C02206D2 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[36:39], 0x31c ; C0220692 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[36:39], 0x320 ; C0220612 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[36:39], 0x324 ; C0220652 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[36:39], 0x328 ; C02205D2 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[36:39], 0x32c ; C0220592 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s9, s[36:39], 0x330 ; C0220252 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[36:39], 0x334 ; C0220292 00000334 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mov_b32_e32 v4, s42 ; 7E08022A v_mov_b32_e32 v5, s0 ; 7E0A0200 v_mad_f32 v11, s34, v5, v4 ; D1C1000B 04120A22 v_mad_f32 v6, s34, v4, v5 ; D1C10006 04160822 v_mov_b32_e32 v5, 0 ; 7E0A0280 v_mov_b32_e32 v13, v11 ; 7E1A030B v_mov_b32_e32 v12, v11 ; 7E18030B s_and_saveexec_b64 s[34:35], s[40:41] ; BEA22028 s_xor_b64 s[34:35], exec, s[34:35] ; 88A2227E v_add_f32_e64 v12, 0, v11 clamp ; D101800C 00021680 v_add_f32_e64 v13, 0, v11 clamp ; D101800D 00021680 v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_add_f32_e64 v7, 0, v7 clamp ; D1018007 00020E80 v_add_f32_e64 v5, 0, 0 clamp ; D1018005 00010080 s_or_b64 exec, exec, s[34:35] ; 87FE227E exp 15, 32, 0, 0, 0, v11, v12, v13, v6 ; C400020F 060D0C0B s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v6, v4, v8, s0 ; D1C10006 00021104 v_mad_f32 v9, v9, v4, s0 ; D1C10009 00020909 v_mad_f32 v10, v10, v4, s0 ; D1C1000A 0002090A v_mad_f32 v8, s0, v8, v4 ; D1C10008 04121000 v_mul_f32_e32 v11, s33, v9 ; 0A161221 v_mac_f32_e32 v11, s32, v6 ; 2C160C20 v_mac_f32_e32 v11, s31, v10 ; 2C16141F v_mac_f32_e32 v11, s30, v8 ; 2C16101E v_mul_f32_e32 v12, s29, v9 ; 0A18121D v_mac_f32_e32 v12, s28, v6 ; 2C180C1C v_mac_f32_e32 v12, s27, v10 ; 2C18141B v_mac_f32_e32 v12, s26, v8 ; 2C18101A v_mul_f32_e32 v9, s25, v9 ; 0A121219 v_mac_f32_e32 v9, s24, v6 ; 2C120C18 v_mac_f32_e32 v9, s23, v10 ; 2C121417 v_mac_f32_e32 v9, s22, v8 ; 2C121016 v_mul_f32_e32 v6, s21, v12 ; 0A0C1815 v_mac_f32_e32 v6, s17, v11 ; 2C0C1611 v_mac_f32_e32 v6, s20, v9 ; 2C0C1214 v_mac_f32_e32 v6, s19, v4 ; 2C0C0813 v_mul_f32_e32 v8, s18, v12 ; 0A101812 v_mac_f32_e32 v8, s16, v11 ; 2C101610 v_mac_f32_e32 v8, s15, v9 ; 2C10120F v_mac_f32_e32 v8, s14, v4 ; 2C10080E v_mul_f32_e32 v10, s13, v12 ; 0A14180D v_mac_f32_e32 v10, s12, v11 ; 2C14160C v_mac_f32_e32 v10, s11, v9 ; 2C14120B s_load_dwordx4 s[12:15], s[2:3], 0x100 ; C00A0301 00000100 v_mac_f32_e32 v10, s4, v4 ; 2C140804 v_mul_f32_e32 v13, s8, v12 ; 0A1A1808 v_mac_f32_e32 v13, s5, v11 ; 2C1A1605 v_mac_f32_e32 v13, s6, v9 ; 2C1A1206 v_mac_f32_e32 v13, s7, v4 ; 2C1A0807 v_mad_f32 v14, v13, s1, -v10 ; D1C1000E 8428030D exp 15, 33, 0, 0, 0, v7, v5, v5, v5 ; C400021F 05050507 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v5, s9, v10, v6 ; D1C10005 041A1409 v_mad_f32 v7, s10, v10, -v8 ; D1C10007 8422140A s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[12:15], 0x0 ; C0220046 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x4 ; C0220086 00000004 v_mul_f32_e32 v15, v2, v4 ; 0A1E0902 s_buffer_load_dword s3, s[12:15], 0x8 ; C02200C6 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xc ; C0220106 0000000C v_mul_f32_e32 v3, v3, v4 ; 0A060903 v_mul_f32_e32 v2, s0, v2 ; 0A040400 v_mul_f32_e32 v16, s0, v0 ; 0A200000 v_mul_f32_e32 v17, v0, v4 ; 0A220900 v_mul_f32_e32 v4, v1, v4 ; 0A080901 s_buffer_load_dword s0, s[12:15], 0x10 ; C0220006 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s2, v8 ; 0A241002 v_mac_f32_e32 v18, s1, v6 ; 2C240C01 v_mac_f32_e32 v18, s3, v13 ; 2C241A03 v_mac_f32_e32 v18, s4, v10 ; 2C241404 s_buffer_load_dword s1, s[12:15], 0x14 ; C0220046 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x18 ; C0220086 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x1c ; C02200C6 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0x20 ; C0220106 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x24 ; C0220146 00000024 v_mov_b32_e32 v19, 0 ; 7E260280 exp 15, 34, 0, 0, 0, v0, v1, v19, v19 ; C400022F 13130100 s_buffer_load_dword s6, s[12:15], 0x28 ; C0220186 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x2c ; C02201C6 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x30 ; C0220206 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x34 ; C0220246 00000034 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v0, s1, v8 ; 0A001001 s_buffer_load_dword s1, s[12:15], 0x38 ; C0220046 00000038 v_mac_f32_e32 v0, s0, v6 ; 2C000C00 v_mac_f32_e32 v0, s2, v13 ; 2C001A02 v_mac_f32_e32 v0, s3, v10 ; 2C001403 v_mul_f32_e32 v1, s5, v8 ; 0A021005 v_mac_f32_e32 v1, s4, v6 ; 2C020C04 v_mac_f32_e32 v1, s6, v13 ; 2C021A06 v_mac_f32_e32 v1, s7, v10 ; 2C021407 v_mul_f32_e32 v19, s9, v8 ; 0A261009 v_mac_f32_e32 v19, s8, v6 ; 2C260C08 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v19, s1, v13 ; 2C261A01 s_buffer_load_dword s0, s[12:15], 0x3c ; C0220006 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x40 ; C0220046 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x44 ; C0220086 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x50 ; C02200C6 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0x54 ; C0220106 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[12:15], 0x58 ; C0220146 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0x5c ; C0220186 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0x60 ; C02201C6 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x64 ; C0220206 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x68 ; C0220246 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x6c ; C0220286 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[12:15], 0x70 ; C02202C6 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x74 ; C0220406 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x48 ; C0220446 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x4c ; C0220486 0000004C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v19, s0, v10 ; 2C261400 v_mul_f32_e32 v20, s2, v8 ; 0A281002 v_mac_f32_e32 v20, s1, v6 ; 2C280C01 v_mul_f32_e32 v21, s4, v8 ; 0A2A1004 v_mac_f32_e32 v21, s3, v6 ; 2C2A0C03 exp 15, 35, 0, 0, 0, v11, v12, v9, v13 ; C400023F 0D090C0B s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v9, s8, v8 ; 0A121008 v_mac_f32_e32 v9, s7, v6 ; 2C120C07 v_mul_f32_e32 v8, s16, v8 ; 0A101010 s_buffer_load_dword s0, s[12:15], 0x78 ; C0220006 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x7c ; C0220046 0000007C exp 15, 36, 0, 0, 0, v15, v3, v2, v2 ; C400024F 0202030F exp 15, 37, 0, 0, 0, v16, v16, v17, v4 ; C400025F 04111010 exp 15, 12, 0, 0, 0, v5, v7, v14, v10 ; C40000CF 0A0E0705 exp 15, 13, 0, 0, 0, v18, v0, v1, v19 ; C40000DF 13010012 v_mac_f32_e32 v8, s11, v6 ; 2C100C0B v_mac_f32_e32 v20, s17, v13 ; 2C281A11 v_mac_f32_e32 v21, s5, v13 ; 2C2A1A05 v_mac_f32_e32 v9, s9, v13 ; 2C121A09 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v8, s0, v13 ; 2C101A00 v_mac_f32_e32 v20, s18, v10 ; 2C281412 v_mac_f32_e32 v21, s6, v10 ; 2C2A1406 v_mac_f32_e32 v9, s10, v10 ; 2C12140A v_mac_f32_e32 v8, s1, v10 ; 2C101401 exp 15, 14, 0, 1, 0, v20, v21, v9, v8 ; C40008EF 08091514 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 24 Code Size: 1416 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], COLOR[1], COLOR DCL IN[2], GENERIC[0], PERSPECTIVE DCL IN[3], GENERIC[1], PERSPECTIVE DCL IN[4], GENERIC[2], PERSPECTIVE, CENTROID DCL IN[5], GENERIC[3], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..17], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, -2.0000, 3.0000} IMM[1] FLT32 { -0.0000, 0.2125, 0.7154, 0.0721} IMM[2] FLT32 { 2.0000, -0.5000, 0.0005, 0.0000} IMM[3] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[4] FLT32 { -0.0005, 0.0005, 0.0000, 0.1250} IMM[5] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[6] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[2].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[2].xyyy 3: TEX TEMP[2].xyz, TEMP[1], SAMP[3], 2D 4: MOV TEMP[2].xyz, TEMP[2].xyzx 5: MOV TEMP[3].xy, IN[4].xyyy 6: TEX TEMP[3], TEMP[3], SAMP[1], 2D 7: MOV TEMP[4], TEMP[3] 8: MOV TEMP[5].xy, IN[5].zwww 9: TEX TEMP[5], TEMP[5], SAMP[2], 2D 10: MOV TEMP[6].w, TEMP[5].zyzw 11: ADD TEMP[7].x, -TEMP[5].xxxx, TEMP[5].yyyy 12: MOV TEMP[2].w, TEMP[7].xxxx 13: ADD TEMP[6].x, TEMP[5].xxxx, TEMP[5].yyyy 14: MIN TEMP[5].x, TEMP[6].xxxx, IMM[0].xxxx 15: MOV TEMP[8].x, TEMP[5].xxxx 16: MOV TEMP[9].xyz, TEMP[2] 17: FSGE TEMP[10].x, TEMP[7].xxxx, IMM[0].yyyy 18: UIF TEMP[10].xxxx :0 19: MOV TEMP[7].x, -TEMP[7].xxxx 20: ELSE :0 21: MOV TEMP[7].x, IMM[0].yyyy 22: ENDIF 23: MOV TEMP[9].w, TEMP[7].xxxx 24: ADD TEMP[6].x, TEMP[7].xxxx, TEMP[5].xxxx 25: ADD TEMP[5].x, TEMP[7].xxxx, IN[1].xxxx 26: RCP TEMP[6].x, TEMP[6].xxxx 27: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 28: MOV_SAT TEMP[5].x, TEMP[5].xxxx 29: MAD TEMP[6].x, TEMP[5].xxxx, IMM[0].zzzz, IMM[0].wwww 30: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 31: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 32: LRP TEMP[6].xyz, TEMP[5].xxxx, TEMP[9].xyzz, TEMP[0].xyzz 33: MUL TEMP[1].xyz, TEMP[6].xyzz, IN[0].xyzz 34: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww 35: MOV TEMP[0].w, TEMP[0].xxxx 36: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[12].xyzz 37: FSLT TEMP[5].x, -TEMP[3].wwww, IMM[1].xxxx 38: AND TEMP[5].x, CONST[90].xxxx, TEMP[5].xxxx 39: UIF TEMP[5].xxxx :0 40: DP3 TEMP[5].x, TEMP[3].xyzz, IMM[1].yzww 41: RCP TEMP[5].x, TEMP[5].xxxx 42: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[3].wwww 43: MAD TEMP[4], IN[3].xyzx, IMM[0].xxxy, IMM[0].yyyx 44: DP4 TEMP[6].x, TEMP[4], CONST[69] 45: DP4 TEMP[5].x, TEMP[4], CONST[70] 46: MOV TEMP[6].y, TEMP[5].xxxx 47: MOV_SAT TEMP[7].xy, TEMP[6].xyyy 48: ADD TEMP[8].xy, -TEMP[6].xyyy, TEMP[7].xyyy 49: DP2 TEMP[7].x, TEMP[8].xyyy, IMM[0].xxxx 50: DP4 TEMP[8].x, TEMP[4], CONST[73] 51: DP4 TEMP[10].x, TEMP[4], CONST[74] 52: MOV TEMP[8].y, TEMP[10].xxxx 53: MOV_SAT TEMP[11].xy, TEMP[8].xyyy 54: ADD TEMP[11].xy, -TEMP[8].xyyy, TEMP[11].xyyy 55: DP2 TEMP[12].x, TEMP[11].xyyy, IMM[0].xxxx 56: MOV TEMP[6].w, TEMP[12].xxxx 57: DP4 TEMP[11].x, TEMP[4], CONST[77] 58: DP4 TEMP[13].x, TEMP[4], CONST[78] 59: MOV TEMP[8].z, IMM[0].xxxx 60: MOV TEMP[9].w, TEMP[8] 61: ABS TEMP[14].x, TEMP[12].xxxx 62: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 63: UIF TEMP[14].xxxx :0 64: MOV TEMP[14].x, TEMP[8].xxxx 65: ELSE :0 66: MOV TEMP[14].x, TEMP[11].xxxx 67: ENDIF 68: MOV TEMP[9].x, TEMP[14].xxxx 69: ABS TEMP[14].x, TEMP[12].xxxx 70: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 71: UIF TEMP[14].xxxx :0 72: MOV TEMP[10].x, TEMP[10].xxxx 73: ELSE :0 74: MOV TEMP[10].x, TEMP[13].xxxx 75: ENDIF 76: MOV TEMP[9].y, TEMP[10].xxxx 77: ABS TEMP[10].x, TEMP[12].xxxx 78: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[0].yyyy 79: UIF TEMP[10].xxxx :0 80: MOV TEMP[10].x, IMM[0].xxxx 81: ELSE :0 82: MOV TEMP[10].x, IMM[2].xxxx 83: ENDIF 84: MOV TEMP[9].z, TEMP[10].xxxx 85: MOV TEMP[8].xyz, TEMP[9] 86: MOV TEMP[6].z, IMM[1].xxxx 87: MOV TEMP[9].w, TEMP[6] 88: ABS TEMP[10].x, TEMP[7].xxxx 89: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[0].yyyy 90: UIF TEMP[10].xxxx :0 91: MOV TEMP[10].x, TEMP[6].xxxx 92: ELSE :0 93: MOV TEMP[10].x, TEMP[8].xxxx 94: ENDIF 95: MOV TEMP[9].x, TEMP[10].xxxx 96: ABS TEMP[10].x, TEMP[7].xxxx 97: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[0].yyyy 98: UIF TEMP[10].xxxx :0 99: MOV TEMP[5].x, TEMP[5].xxxx 100: ELSE :0 101: MOV TEMP[5].x, TEMP[8].yyyy 102: ENDIF 103: MOV TEMP[9].y, TEMP[5].xxxx 104: ABS TEMP[5].x, TEMP[7].xxxx 105: FSGE TEMP[5].x, -TEMP[5].xxxx, IMM[0].yyyy 106: UIF TEMP[5].xxxx :0 107: MOV TEMP[5].x, IMM[1].xxxx 108: ELSE :0 109: MOV TEMP[5].x, TEMP[8].zzzz 110: ENDIF 111: MOV TEMP[9].z, TEMP[5].xxxx 112: MOV TEMP[6].z, TEMP[9].wwzw 113: DP4 TEMP[7].x, TEMP[4], CONST[71] 114: MOV TEMP[8].z, TEMP[7].xxxx 115: ADD TEMP[11].xy, TEMP[9].xyyy, IMM[2].yyyy 116: ABS TEMP[10].xy, TEMP[11].xyyy 117: ADD TEMP[11].xy, TEMP[10].xyyy, -CONST[67].zzzz 118: MUL TEMP[11].xy, TEMP[11].xyyy, CONST[67].wwww 119: MOV_SAT TEMP[10].xy, TEMP[11].xyyy 120: ADD TEMP[11].xy, -TEMP[10].xyyy, IMM[0].xxxx 121: MUL TEMP[10].x, TEMP[11].yyyy, TEMP[11].xxxx 122: MOV_SAT TEMP[12].xy, TEMP[9].xyyy 123: ADD TEMP[11].xyz, TEMP[5].xxxx, IMM[3].xyzz 124: MOV TEMP[5].y, IMM[0].yyyy 125: ABS TEMP[14].x, TEMP[11].xxxx 126: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 127: UIF TEMP[14].xxxx :0 128: MOV TEMP[14].x, CONST[85].zzzz 129: ELSE :0 130: MOV TEMP[14].x, IMM[1].xxxx 131: ENDIF 132: ABS TEMP[15].x, TEMP[11].xxxx 133: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 134: UIF TEMP[15].xxxx :0 135: MOV TEMP[15].x, CONST[85].wwww 136: ELSE :0 137: MOV TEMP[15].x, IMM[1].xxxx 138: ENDIF 139: MOV TEMP[9].y, TEMP[15].xxxx 140: ABS TEMP[15].x, TEMP[11].xxxx 141: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 142: UIF TEMP[15].xxxx :0 143: MOV TEMP[15].x, CONST[85].xxxx 144: ELSE :0 145: MOV TEMP[15].x, IMM[1].xxxx 146: ENDIF 147: MOV TEMP[9].z, TEMP[15].xxxx 148: ABS TEMP[15].x, TEMP[11].xxxx 149: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 150: UIF TEMP[15].xxxx :0 151: MOV TEMP[15].x, CONST[85].yyyy 152: ELSE :0 153: MOV TEMP[15].x, IMM[1].xxxx 154: ENDIF 155: MOV TEMP[9].w, TEMP[15].xxxx 156: ABS TEMP[15].x, TEMP[11].yyyy 157: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 158: UIF TEMP[15].xxxx :0 159: MOV TEMP[15].x, CONST[86].zzzz 160: ELSE :0 161: MOV TEMP[15].x, TEMP[14].xxxx 162: ENDIF 163: MOV TEMP[9].x, TEMP[15].xxxx 164: ABS TEMP[14].x, TEMP[11].yyyy 165: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 166: UIF TEMP[14].xxxx :0 167: MOV TEMP[14].x, CONST[86].wwww 168: ELSE :0 169: MOV TEMP[14].x, TEMP[9].yyyy 170: ENDIF 171: MOV TEMP[9].y, TEMP[14].xxxx 172: ABS TEMP[14].x, TEMP[11].yyyy 173: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 174: UIF TEMP[14].xxxx :0 175: MOV TEMP[14].x, CONST[86].xxxx 176: ELSE :0 177: MOV TEMP[14].x, TEMP[9].zzzz 178: ENDIF 179: MOV TEMP[9].z, TEMP[14].xxxx 180: ABS TEMP[14].x, TEMP[11].yyyy 181: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 182: UIF TEMP[14].xxxx :0 183: MOV TEMP[14].x, CONST[86].yyyy 184: ELSE :0 185: MOV TEMP[14].x, TEMP[9].wwww 186: ENDIF 187: MOV TEMP[9].w, TEMP[14].xxxx 188: MOV TEMP[13], TEMP[9] 189: ABS TEMP[14].x, TEMP[11].zzzz 190: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 191: UIF TEMP[14].xxxx :0 192: MOV TEMP[14].x, CONST[87].zzzz 193: ELSE :0 194: MOV TEMP[14].x, TEMP[13].xxxx 195: ENDIF 196: MOV TEMP[9].x, TEMP[14].xxxx 197: ABS TEMP[14].x, TEMP[11].zzzz 198: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 199: UIF TEMP[14].xxxx :0 200: MOV TEMP[14].x, CONST[87].wwww 201: ELSE :0 202: MOV TEMP[14].x, TEMP[13].yyyy 203: ENDIF 204: MOV TEMP[9].y, TEMP[14].xxxx 205: ABS TEMP[14].x, TEMP[11].zzzz 206: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 207: UIF TEMP[14].xxxx :0 208: MOV TEMP[14].x, CONST[87].xxxx 209: ELSE :0 210: MOV TEMP[14].x, TEMP[13].zzzz 211: ENDIF 212: MOV TEMP[9].z, TEMP[14].xxxx 213: ABS TEMP[14].x, TEMP[11].zzzz 214: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 215: UIF TEMP[14].xxxx :0 216: MOV TEMP[14].x, CONST[87].yyyy 217: ELSE :0 218: MOV TEMP[14].x, TEMP[13].wwww 219: ENDIF 220: MOV TEMP[9].w, TEMP[14].xxxx 221: MAD TEMP[8].xy, TEMP[12].xyyy, TEMP[9].xyyy, TEMP[9].zwww 222: MOV TEMP[8].w, IMM[1].xxxx 223: ADD TEMP[11], TEMP[8], IMM[2].zzww 224: TXL TEMP[12].x, TEMP[11], SAMP[4], SHADOW2D 225: MOV TEMP[11].x, TEMP[12].xxxx 226: ADD TEMP[13], TEMP[8], IMM[4].xyzz 227: ADD TEMP[12], TEMP[8], IMM[4].yxzz 228: ADD TEMP[14], TEMP[8], IMM[4].xxzz 229: TXL TEMP[15].x, TEMP[13], SAMP[4], SHADOW2D 230: MOV TEMP[11].y, TEMP[15].xxxx 231: TXL TEMP[15].x, TEMP[12], SAMP[4], SHADOW2D 232: MOV TEMP[11].z, TEMP[15].xxxx 233: TXL TEMP[15].x, TEMP[14], SAMP[4], SHADOW2D 234: MOV TEMP[11].w, TEMP[15].xxxx 235: DP4 TEMP[15].x, TEMP[11], IMM[3].wwww 236: ADD TEMP[11], TEMP[8], IMM[2].zwww 237: TXL TEMP[16].x, TEMP[11], SAMP[4], SHADOW2D 238: MOV TEMP[11].x, TEMP[16].xxxx 239: ADD TEMP[13], TEMP[8], IMM[4].xzzz 240: TXL TEMP[16], TEMP[13], SAMP[4], SHADOW2D 241: MOV TEMP[13], TEMP[16] 242: ADD TEMP[12], TEMP[8], IMM[4].zxzz 243: TXL TEMP[17], TEMP[12], SAMP[4], SHADOW2D 244: MOV TEMP[12], TEMP[17] 245: ADD TEMP[14], TEMP[8], IMM[2].wzww 246: TXL TEMP[14].x, TEMP[14], SAMP[4], SHADOW2D 247: MOV TEMP[11].y, TEMP[16].xxxx 248: MOV TEMP[11].z, TEMP[17].xxxx 249: MOV TEMP[11].w, TEMP[14].xxxx 250: DP4 TEMP[14].x, TEMP[11], IMM[4].wwww 251: MOV TEMP[16].xy, TEMP[8].xyyy 252: MOV TEMP[16].z, TEMP[7].xxxx 253: MOV TEMP[16].w, IMM[1].xxxx 254: TXL TEMP[16], TEMP[16], SAMP[4], SHADOW2D 255: MOV TEMP[11], TEMP[16] 256: ADD TEMP[6].x, TEMP[14].xxxx, TEMP[15].xxxx 257: MAD TEMP[6].x, TEMP[16].xxxx, IMM[5].xxxx, TEMP[6].xxxx 258: FSLT TEMP[14].x, TEMP[10].xxxx, IMM[0].xxxx 259: UIF TEMP[14].xxxx :0 260: ADD TEMP[14].xyz, TEMP[6].zzzz, IMM[5].yzww 261: ABS TEMP[15].x, TEMP[14].xxxx 262: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 263: UIF TEMP[15].xxxx :0 264: MOV TEMP[15].x, CONST[73].xxxx 265: ELSE :0 266: MOV TEMP[15].x, IMM[1].xxxx 267: ENDIF 268: MOV TEMP[9].x, TEMP[15].xxxx 269: ABS TEMP[15].x, TEMP[14].xxxx 270: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 271: UIF TEMP[15].xxxx :0 272: MOV TEMP[15].x, CONST[73].yyyy 273: ELSE :0 274: MOV TEMP[15].x, IMM[1].xxxx 275: ENDIF 276: MOV TEMP[9].y, TEMP[15].xxxx 277: ABS TEMP[15].x, TEMP[14].xxxx 278: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 279: UIF TEMP[15].xxxx :0 280: MOV TEMP[15].x, CONST[73].zzzz 281: ELSE :0 282: MOV TEMP[15].x, IMM[1].xxxx 283: ENDIF 284: MOV TEMP[9].z, TEMP[15].xxxx 285: ABS TEMP[15].x, TEMP[14].xxxx 286: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 287: UIF TEMP[15].xxxx :0 288: MOV TEMP[15].x, CONST[73].wwww 289: ELSE :0 290: MOV TEMP[15].x, IMM[1].xxxx 291: ENDIF 292: MOV TEMP[9].w, TEMP[15].xxxx 293: MOV TEMP[11], TEMP[9] 294: ABS TEMP[15].x, TEMP[14].xxxx 295: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 296: UIF TEMP[15].xxxx :0 297: MOV TEMP[15].x, CONST[74].xxxx 298: ELSE :0 299: MOV TEMP[15].x, IMM[1].xxxx 300: ENDIF 301: MOV TEMP[9].x, TEMP[15].xxxx 302: ABS TEMP[15].x, TEMP[14].xxxx 303: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 304: UIF TEMP[15].xxxx :0 305: MOV TEMP[15].x, CONST[74].yyyy 306: ELSE :0 307: MOV TEMP[15].x, IMM[1].xxxx 308: ENDIF 309: MOV TEMP[9].y, TEMP[15].xxxx 310: ABS TEMP[15].x, TEMP[14].xxxx 311: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 312: UIF TEMP[15].xxxx :0 313: MOV TEMP[15].x, CONST[74].zzzz 314: ELSE :0 315: MOV TEMP[15].x, IMM[1].xxxx 316: ENDIF 317: MOV TEMP[9].z, TEMP[15].xxxx 318: ABS TEMP[15].x, TEMP[14].xxxx 319: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 320: UIF TEMP[15].xxxx :0 321: MOV TEMP[15].x, CONST[74].wwww 322: ELSE :0 323: MOV TEMP[15].x, IMM[1].xxxx 324: ENDIF 325: MOV TEMP[9].w, TEMP[15].xxxx 326: MOV TEMP[13], TEMP[9] 327: ABS TEMP[15].x, TEMP[14].yyyy 328: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 329: UIF TEMP[15].xxxx :0 330: MOV TEMP[15].x, CONST[77].xxxx 331: ELSE :0 332: MOV TEMP[15].x, TEMP[11].xxxx 333: ENDIF 334: MOV TEMP[9].x, TEMP[15].xxxx 335: ABS TEMP[15].x, TEMP[14].yyyy 336: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 337: UIF TEMP[15].xxxx :0 338: MOV TEMP[15].x, CONST[77].yyyy 339: ELSE :0 340: MOV TEMP[15].x, TEMP[11].yyyy 341: ENDIF 342: MOV TEMP[9].y, TEMP[15].xxxx 343: ABS TEMP[15].x, TEMP[14].yyyy 344: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 345: UIF TEMP[15].xxxx :0 346: MOV TEMP[15].x, CONST[77].zzzz 347: ELSE :0 348: MOV TEMP[15].x, TEMP[11].zzzz 349: ENDIF 350: MOV TEMP[9].z, TEMP[15].xxxx 351: ABS TEMP[15].x, TEMP[14].yyyy 352: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 353: UIF TEMP[15].xxxx :0 354: MOV TEMP[15].x, CONST[77].wwww 355: ELSE :0 356: MOV TEMP[15].x, TEMP[11].wwww 357: ENDIF 358: MOV TEMP[9].w, TEMP[15].xxxx 359: MOV TEMP[11], TEMP[9] 360: ABS TEMP[15].x, TEMP[14].yyyy 361: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 362: UIF TEMP[15].xxxx :0 363: MOV TEMP[15].x, CONST[78].xxxx 364: ELSE :0 365: MOV TEMP[15].x, TEMP[13].xxxx 366: ENDIF 367: MOV TEMP[9].x, TEMP[15].xxxx 368: ABS TEMP[15].x, TEMP[14].yyyy 369: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 370: UIF TEMP[15].xxxx :0 371: MOV TEMP[15].x, CONST[78].yyyy 372: ELSE :0 373: MOV TEMP[15].x, TEMP[13].yyyy 374: ENDIF 375: MOV TEMP[9].y, TEMP[15].xxxx 376: ABS TEMP[15].x, TEMP[14].yyyy 377: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 378: UIF TEMP[15].xxxx :0 379: MOV TEMP[15].x, CONST[78].zzzz 380: ELSE :0 381: MOV TEMP[15].x, TEMP[13].zzzz 382: ENDIF 383: MOV TEMP[9].z, TEMP[15].xxxx 384: ABS TEMP[15].x, TEMP[14].yyyy 385: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 386: UIF TEMP[15].xxxx :0 387: MOV TEMP[15].x, CONST[78].wwww 388: ELSE :0 389: MOV TEMP[15].x, TEMP[13].wwww 390: ENDIF 391: MOV TEMP[9].w, TEMP[15].xxxx 392: MOV TEMP[13], TEMP[9] 393: ABS TEMP[15].x, TEMP[14].zzzz 394: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 395: UIF TEMP[15].xxxx :0 396: MOV TEMP[15].x, CONST[81].xxxx 397: ELSE :0 398: MOV TEMP[15].x, TEMP[11].xxxx 399: ENDIF 400: MOV TEMP[9].x, TEMP[15].xxxx 401: ABS TEMP[15].x, TEMP[14].zzzz 402: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 403: UIF TEMP[15].xxxx :0 404: MOV TEMP[15].x, CONST[81].yyyy 405: ELSE :0 406: MOV TEMP[15].x, TEMP[11].yyyy 407: ENDIF 408: MOV TEMP[9].y, TEMP[15].xxxx 409: ABS TEMP[15].x, TEMP[14].zzzz 410: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 411: UIF TEMP[15].xxxx :0 412: MOV TEMP[15].x, CONST[81].zzzz 413: ELSE :0 414: MOV TEMP[15].x, TEMP[11].zzzz 415: ENDIF 416: MOV TEMP[9].z, TEMP[15].xxxx 417: ABS TEMP[15].x, TEMP[14].zzzz 418: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 419: UIF TEMP[15].xxxx :0 420: MOV TEMP[15].x, CONST[81].wwww 421: ELSE :0 422: MOV TEMP[15].x, TEMP[11].wwww 423: ENDIF 424: MOV TEMP[9].w, TEMP[15].xxxx 425: MOV TEMP[11], TEMP[9] 426: ABS TEMP[15].x, TEMP[14].zzzz 427: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 428: UIF TEMP[15].xxxx :0 429: MOV TEMP[15].x, CONST[82].xxxx 430: ELSE :0 431: MOV TEMP[15].x, TEMP[13].xxxx 432: ENDIF 433: MOV TEMP[9].x, TEMP[15].xxxx 434: ABS TEMP[15].x, TEMP[14].zzzz 435: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 436: UIF TEMP[15].xxxx :0 437: MOV TEMP[15].x, CONST[82].yyyy 438: ELSE :0 439: MOV TEMP[15].x, TEMP[13].yyyy 440: ENDIF 441: MOV TEMP[9].y, TEMP[15].xxxx 442: ABS TEMP[15].x, TEMP[14].zzzz 443: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 444: UIF TEMP[15].xxxx :0 445: MOV TEMP[15].x, CONST[82].zzzz 446: ELSE :0 447: MOV TEMP[15].x, TEMP[13].zzzz 448: ENDIF 449: MOV TEMP[9].z, TEMP[15].xxxx 450: ABS TEMP[15].x, TEMP[14].zzzz 451: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 452: UIF TEMP[15].xxxx :0 453: MOV TEMP[15].x, CONST[82].wwww 454: ELSE :0 455: MOV TEMP[15].x, TEMP[13].wwww 456: ENDIF 457: MOV TEMP[9].w, TEMP[15].xxxx 458: DP4 TEMP[11].x, TEMP[4], TEMP[11] 459: MOV_SAT TEMP[11].x, TEMP[11].xxxx 460: DP4 TEMP[15].x, TEMP[4], TEMP[9] 461: MOV_SAT TEMP[15].x, TEMP[15].xxxx 462: MOV TEMP[11].y, TEMP[15].xxxx 463: ABS TEMP[15].x, TEMP[14].xxxx 464: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 465: UIF TEMP[15].xxxx :0 466: MOV TEMP[15].x, CONST[86].zzzz 467: ELSE :0 468: MOV TEMP[15].x, IMM[1].xxxx 469: ENDIF 470: ABS TEMP[16].x, TEMP[14].xxxx 471: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 472: UIF TEMP[16].xxxx :0 473: MOV TEMP[16].x, CONST[86].wwww 474: ELSE :0 475: MOV TEMP[16].x, IMM[1].xxxx 476: ENDIF 477: MOV TEMP[9].y, TEMP[16].xxxx 478: ABS TEMP[16].x, TEMP[14].xxxx 479: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 480: UIF TEMP[16].xxxx :0 481: MOV TEMP[16].x, CONST[86].xxxx 482: ELSE :0 483: MOV TEMP[16].x, IMM[1].xxxx 484: ENDIF 485: MOV TEMP[9].z, TEMP[16].xxxx 486: ABS TEMP[16].x, TEMP[14].xxxx 487: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 488: UIF TEMP[16].xxxx :0 489: MOV TEMP[16].x, CONST[86].yyyy 490: ELSE :0 491: MOV TEMP[16].x, IMM[1].xxxx 492: ENDIF 493: MOV TEMP[9].w, TEMP[16].xxxx 494: ABS TEMP[16].x, TEMP[14].yyyy 495: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 496: UIF TEMP[16].xxxx :0 497: MOV TEMP[16].x, CONST[87].zzzz 498: ELSE :0 499: MOV TEMP[16].x, TEMP[15].xxxx 500: ENDIF 501: ABS TEMP[15].x, TEMP[14].yyyy 502: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 503: UIF TEMP[15].xxxx :0 504: MOV TEMP[15].x, CONST[87].wwww 505: ELSE :0 506: MOV TEMP[15].x, TEMP[9].yyyy 507: ENDIF 508: MOV TEMP[9].y, TEMP[15].xxxx 509: ABS TEMP[15].x, TEMP[14].yyyy 510: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 511: UIF TEMP[15].xxxx :0 512: MOV TEMP[15].x, CONST[87].xxxx 513: ELSE :0 514: MOV TEMP[15].x, TEMP[9].zzzz 515: ENDIF 516: MOV TEMP[9].z, TEMP[15].xxxx 517: ABS TEMP[15].x, TEMP[14].yyyy 518: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 519: UIF TEMP[15].xxxx :0 520: MOV TEMP[15].x, CONST[87].yyyy 521: ELSE :0 522: MOV TEMP[15].x, TEMP[9].wwww 523: ENDIF 524: MOV TEMP[9].w, TEMP[15].xxxx 525: ABS TEMP[15].x, TEMP[14].zzzz 526: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 527: UIF TEMP[15].xxxx :0 528: MOV TEMP[15].x, CONST[88].zzzz 529: ELSE :0 530: MOV TEMP[15].x, TEMP[16].xxxx 531: ENDIF 532: MOV TEMP[9].x, TEMP[15].xxxx 533: ABS TEMP[15].x, TEMP[14].zzzz 534: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 535: UIF TEMP[15].xxxx :0 536: MOV TEMP[15].x, CONST[88].wwww 537: ELSE :0 538: MOV TEMP[15].x, TEMP[9].yyyy 539: ENDIF 540: MOV TEMP[9].y, TEMP[15].xxxx 541: ABS TEMP[15].x, TEMP[14].zzzz 542: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 543: UIF TEMP[15].xxxx :0 544: MOV TEMP[15].x, CONST[88].xxxx 545: ELSE :0 546: MOV TEMP[15].x, TEMP[9].zzzz 547: ENDIF 548: MOV TEMP[9].z, TEMP[15].xxxx 549: ABS TEMP[15].x, TEMP[14].zzzz 550: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 551: UIF TEMP[15].xxxx :0 552: MOV TEMP[15].x, CONST[88].yyyy 553: ELSE :0 554: MOV TEMP[15].x, TEMP[9].wwww 555: ENDIF 556: MOV TEMP[9].w, TEMP[15].xxxx 557: MAD TEMP[8].xy, TEMP[11].xyyy, TEMP[9].xyyy, TEMP[9].zwww 558: ADD TEMP[4], TEMP[8], IMM[2].zzww 559: TXL TEMP[9].x, TEMP[4], SAMP[4], SHADOW2D 560: MOV TEMP[4].x, TEMP[9].xxxx 561: ADD TEMP[11], TEMP[8], IMM[4].xyzz 562: ADD TEMP[5], TEMP[8], IMM[4].yxzz 563: ADD TEMP[13], TEMP[8], IMM[4].xxzz 564: TXL TEMP[9].x, TEMP[11], SAMP[4], SHADOW2D 565: MOV TEMP[4].y, TEMP[9].xxxx 566: TXL TEMP[9].x, TEMP[5], SAMP[4], SHADOW2D 567: MOV TEMP[4].z, TEMP[9].xxxx 568: TXL TEMP[9].x, TEMP[13], SAMP[4], SHADOW2D 569: MOV TEMP[4].w, TEMP[9].xxxx 570: DP4 TEMP[9].x, TEMP[4], IMM[3].wwww 571: ADD TEMP[11], TEMP[8], IMM[2].zwww 572: TXL TEMP[15].x, TEMP[11], SAMP[4], SHADOW2D 573: MOV TEMP[11].x, TEMP[15].xxxx 574: ADD TEMP[5], TEMP[8], IMM[4].xzzz 575: TXL TEMP[5].x, TEMP[5], SAMP[4], SHADOW2D 576: ADD TEMP[13], TEMP[8], IMM[4].zxzz 577: TXL TEMP[13].x, TEMP[13], SAMP[4], SHADOW2D 578: ADD TEMP[12], TEMP[8], IMM[2].wzww 579: TXL TEMP[12].x, TEMP[12], SAMP[4], SHADOW2D 580: MOV TEMP[11].y, TEMP[5].xxxx 581: MOV TEMP[11].z, TEMP[13].xxxx 582: MOV TEMP[11].w, TEMP[12].xxxx 583: DP4 TEMP[5].x, TEMP[11], IMM[4].wwww 584: MOV TEMP[11].xy, TEMP[8].xyyy 585: MOV TEMP[11].z, TEMP[7].xxxx 586: MOV TEMP[11].w, IMM[1].xxxx 587: TXL TEMP[7].x, TEMP[11], SAMP[4], SHADOW2D 588: ADD TEMP[4].x, TEMP[5].xxxx, TEMP[9].xxxx 589: MAD TEMP[4].x, TEMP[7].xxxx, IMM[5].xxxx, TEMP[4].xxxx 590: FSGE TEMP[5].x, TEMP[14].zzzz, IMM[0].yyyy 591: UIF TEMP[5].xxxx :0 592: MOV TEMP[5].x, IMM[0].xxxx 593: ELSE :0 594: MOV TEMP[5].x, TEMP[4].xxxx 595: ENDIF 596: LRP TEMP[8].x, TEMP[10].xxxx, TEMP[6].xxxx, TEMP[5].xxxx 597: MOV TEMP[6].x, TEMP[8].xxxx 598: ENDIF 599: ADD TEMP[4].xyz, -CONST[89].xyzz, IN[3].xyzz 600: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 601: MAD TEMP[5].x, TEMP[5].xxxx, CONST[68].yyyy, CONST[68].xxxx 602: MOV_SAT TEMP[5].x, TEMP[5].xxxx 603: LRP TEMP[4].x, TEMP[5].xxxx, IMM[0].xxxx, TEMP[6].xxxx 604: ADD TEMP[5].x, -TEMP[4].xxxx, IMM[0].xxxx 605: MAD TEMP[3].x, TEMP[3].xxxx, -TEMP[5].xxxx, IMM[0].xxxx 606: MUL TEMP[4].xyz, TEMP[3].xxxx, TEMP[2].zyxx 607: MAD TEMP[3].x, TEMP[3].xxxx, IMM[6].xxxx, IMM[6].xxxx 608: LRP TEMP[2].xyz, TEMP[3].xxxx, TEMP[4].zyxx, TEMP[4].xyzz 609: ENDIF 610: ADD TEMP[2].xyz, TEMP[2].xyzz, CONST[31].xyzz 611: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xyzz 612: ADD TEMP[2].xyz, CONST[10].xyzz, -IN[3].xyzz 613: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 614: SQRT TEMP[2].x, TEMP[2].xxxx 615: MAD TEMP[2].x, TEMP[2].xxxx, CONST[11].wwww, CONST[11].xxxx 616: MOV_SAT TEMP[2].x, TEMP[2].xxxx 617: MIN TEMP[2].x, TEMP[2].xxxx, CONST[11].zzzz 618: MUL TEMP[3].xyz, TEMP[1].xyzz, CONST[30].xxxx 619: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 620: MAD TEMP[1].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz 621: MAD TEMP[0].xyz, TEMP[2].xxxx, TEMP[1].xyzz, TEMP[3].xyzz 622: MOV OUT[0], TEMP[0] 623: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %85 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %86 = load <8 x i32>, <8 x i32> addrspace(2)* %85, align 32, !tbaa !0 %87 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %88 = load <4 x i32>, <4 x i32> addrspace(2)* %87, align 16, !tbaa !0 %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %102 = load <8 x i32>, <8 x i32> addrspace(2)* %101, align 32, !tbaa !0 %103 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %104 = load <4 x i32>, <4 x i32> addrspace(2)* %103, align 16, !tbaa !0 %105 = and i32 %5, 1 %106 = icmp ne i32 %105, 0 %107 = select i1 %106, <2 x i32> %7, <2 x i32> %8 %108 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %107) %109 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %107) %110 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %107) %111 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %107) %112 = and i32 %5, 1 %113 = icmp ne i32 %112, 0 %114 = select i1 %113, <2 x i32> %7, <2 x i32> %8 %115 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %114) %116 = and i32 %5, 1 %117 = icmp ne i32 %116, 0 %118 = select i1 %117, <2 x i32> %7, <2 x i32> %8 %119 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %118) %120 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %118) %121 = and i32 %5, 1 %122 = icmp ne i32 %121, 0 %123 = select i1 %122, <2 x i32> %7, <2 x i32> %8 %124 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %123) %125 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %123) %126 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %123) %127 = and i32 %5, 1 %128 = icmp ne i32 %127, 0 %129 = select i1 %128, <2 x i32> %7, <2 x i32> %9 %130 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %129) %131 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %129) %132 = and i32 %5, 1 %133 = icmp ne i32 %132, 0 %134 = select i1 %133, <2 x i32> %7, <2 x i32> %9 %135 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %6, <2 x i32> %134) %136 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %6, <2 x i32> %134) %137 = bitcast float %119 to i32 %138 = bitcast float %120 to i32 %139 = insertelement <2 x i32> undef, i32 %137, i32 0 %140 = insertelement <2 x i32> %139, i32 %138, i32 1 %141 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %140, <8 x i32> %86, <4 x i32> %88, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %142 = extractelement <4 x float> %141, i32 0 %143 = extractelement <4 x float> %141, i32 1 %144 = extractelement <4 x float> %141, i32 2 %145 = extractelement <4 x float> %141, i32 3 %146 = bitcast float %119 to i32 %147 = bitcast float %120 to i32 %148 = insertelement <2 x i32> undef, i32 %146, i32 0 %149 = insertelement <2 x i32> %148, i32 %147, i32 1 %150 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %149, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %151 = extractelement <4 x float> %150, i32 0 %152 = extractelement <4 x float> %150, i32 1 %153 = extractelement <4 x float> %150, i32 2 %154 = bitcast float %130 to i32 %155 = bitcast float %131 to i32 %156 = insertelement <2 x i32> undef, i32 %154, i32 0 %157 = insertelement <2 x i32> %156, i32 %155, i32 1 %158 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %157, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %159 = extractelement <4 x float> %158, i32 0 %160 = extractelement <4 x float> %158, i32 1 %161 = extractelement <4 x float> %158, i32 2 %162 = extractelement <4 x float> %158, i32 3 %163 = bitcast float %135 to i32 %164 = bitcast float %136 to i32 %165 = insertelement <2 x i32> undef, i32 %163, i32 0 %166 = insertelement <2 x i32> %165, i32 %164, i32 1 %167 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %166, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %168 = extractelement <4 x float> %167, i32 0 %169 = extractelement <4 x float> %167, i32 1 %170 = fsub float %169, %168 %171 = fadd float %168, %169 %172 = call float @llvm.minnum.f32(float %171, float 1.000000e+00) %173 = fcmp oge float %170, 0.000000e+00 %174 = fsub float -0.000000e+00, %170 %temp28.0 = select i1 %173, float %174, float 0.000000e+00 %175 = fadd float %temp28.0, %172 %176 = fadd float %temp28.0, %115 %177 = fdiv float 1.000000e+00, %175 %178 = fmul float %176, %177 %179 = call float @llvm.AMDIL.clamp.(float %178, float 0.000000e+00, float 1.000000e+00) %180 = fmul float %179, -2.000000e+00 %181 = fadd float %180, 3.000000e+00 %182 = fmul float %179, %179 %183 = fmul float %182, %181 %184 = fsub float 1.000000e+00, %183 %185 = fmul float %151, %183 %186 = fmul float %142, %184 %187 = fadd float %185, %186 %188 = fsub float 1.000000e+00, %183 %189 = fmul float %152, %183 %190 = fmul float %143, %188 %191 = fadd float %189, %190 %192 = fsub float 1.000000e+00, %183 %193 = fmul float %153, %183 %194 = fmul float %144, %192 %195 = fadd float %193, %194 %196 = fmul float %187, %108 %197 = fmul float %191, %109 %198 = fmul float %195, %110 %199 = fmul float %145, %111 %200 = fmul float %159, %31 %201 = fmul float %160, %32 %202 = fmul float %161, %33 %203 = fcmp ogt float %162, 0.000000e+00 %204 = bitcast float %84 to i32 %205 = icmp ne i32 %204, 0 %206 = and i1 %203, %205 br i1 %206, label %IF73, label %ENDIF72 IF73: ; preds = %main_body %207 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %208 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %209 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %210 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %211 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %212 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %213 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %214 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %215 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %216 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %217 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %218 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %219 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %220 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %221 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %222 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %223 = fmul float %159, 0x3FCB333340000000 %224 = fmul float %160, 0x3FE6E48E80000000 %225 = fadd float %224, %223 %226 = fmul float %161, 0x3FB2752540000000 %227 = fadd float %225, %226 %228 = fdiv float 1.000000e+00, %227 %229 = fmul float %228, %162 %230 = fadd float %124, 0.000000e+00 %231 = fadd float %125, 0.000000e+00 %232 = fadd float %126, 0.000000e+00 %233 = fmul float %124, 0.000000e+00 %234 = fadd float %233, 1.000000e+00 %235 = fmul float %230, %222 %236 = fmul float %231, %221 %237 = fadd float %235, %236 %238 = fmul float %232, %220 %239 = fadd float %237, %238 %240 = fmul float %234, %219 %241 = fadd float %239, %240 %242 = fmul float %230, %218 %243 = fmul float %231, %217 %244 = fadd float %242, %243 %245 = fmul float %232, %216 %246 = fadd float %244, %245 %247 = fmul float %234, %215 %248 = fadd float %246, %247 %249 = call float @llvm.AMDIL.clamp.(float %241, float 0.000000e+00, float 1.000000e+00) %250 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00) %251 = fsub float %249, %241 %252 = fsub float %250, %248 %253 = fadd float %251, %252 %254 = fmul float %230, %45 %255 = fmul float %231, %46 %256 = fadd float %254, %255 %257 = fmul float %232, %47 %258 = fadd float %256, %257 %259 = fmul float %234, %48 %260 = fadd float %258, %259 %261 = fmul float %230, %49 %262 = fmul float %231, %50 %263 = fadd float %261, %262 %264 = fmul float %232, %51 %265 = fadd float %263, %264 %266 = fmul float %234, %52 %267 = fadd float %265, %266 %268 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00) %269 = call float @llvm.AMDIL.clamp.(float %267, float 0.000000e+00, float 1.000000e+00) %270 = fsub float %268, %260 %271 = fsub float %269, %267 %272 = fadd float %270, %271 %273 = fmul float %230, %53 %274 = fmul float %231, %54 %275 = fadd float %273, %274 %276 = fmul float %232, %55 %277 = fadd float %275, %276 %278 = fmul float %234, %56 %279 = fadd float %277, %278 %280 = fmul float %230, %57 %281 = fmul float %231, %58 %282 = fadd float %280, %281 %283 = fmul float %232, %59 %284 = fadd float %282, %283 %285 = fmul float %234, %60 %286 = fadd float %284, %285 %287 = call float @llvm.fabs.f32(float %272) %288 = fcmp ole float %287, -0.000000e+00 %. = select i1 %288, float %260, float %279 %289 = call float @llvm.fabs.f32(float %272) %290 = fcmp ole float %289, -0.000000e+00 %temp40.0 = select i1 %290, float %267, float %286 %291 = call float @llvm.fabs.f32(float %272) %292 = fcmp ole float %291, -0.000000e+00 %.243 = select i1 %292, float 1.000000e+00, float 2.000000e+00 %293 = call float @llvm.fabs.f32(float %253) %294 = fcmp ole float %293, -0.000000e+00 %temp40.2 = select i1 %294, float %241, float %. %295 = call float @llvm.fabs.f32(float %253) %296 = fcmp ole float %295, -0.000000e+00 %.temp40.0 = select i1 %296, float %248, float %temp40.0 %297 = call float @llvm.fabs.f32(float %253) %298 = fcmp ole float %297, -0.000000e+00 %temp20.1 = select i1 %298, float -0.000000e+00, float %.243 %299 = fmul float %230, %214 %300 = fmul float %231, %213 %301 = fadd float %299, %300 %302 = fmul float %232, %212 %303 = fadd float %301, %302 %304 = fmul float %234, %211 %305 = fadd float %303, %304 %306 = fadd float %temp40.2, -5.000000e-01 %307 = fadd float %.temp40.0, -5.000000e-01 %308 = call float @llvm.fabs.f32(float %306) %309 = call float @llvm.fabs.f32(float %307) %310 = fsub float %308, %41 %311 = fsub float %309, %41 %312 = fmul float %310, %42 %313 = fmul float %311, %42 %314 = call float @llvm.AMDIL.clamp.(float %312, float 0.000000e+00, float 1.000000e+00) %315 = call float @llvm.AMDIL.clamp.(float %313, float 0.000000e+00, float 1.000000e+00) %316 = fsub float 1.000000e+00, %314 %317 = fsub float 1.000000e+00, %315 %318 = fmul float %317, %316 %319 = call float @llvm.AMDIL.clamp.(float %temp40.2, float 0.000000e+00, float 1.000000e+00) %320 = call float @llvm.AMDIL.clamp.(float %.temp40.0, float 0.000000e+00, float 1.000000e+00) %321 = fadd float %temp20.1, -1.000000e+00 %322 = fadd float %temp20.1, -2.000000e+00 %323 = call float @llvm.fabs.f32(float %temp20.1) %324 = fcmp ole float %323, -0.000000e+00 %.244 = select i1 %324, float %208, float -0.000000e+00 %325 = call float @llvm.fabs.f32(float %temp20.1) %326 = fcmp ole float %325, -0.000000e+00 %temp60.0 = select i1 %326, float %207, float -0.000000e+00 %327 = call float @llvm.fabs.f32(float %temp20.1) %328 = fcmp ole float %327, -0.000000e+00 %.245 = select i1 %328, float %210, float -0.000000e+00 %329 = call float @llvm.fabs.f32(float %temp20.1) %330 = fcmp ole float %329, -0.000000e+00 %temp60.2 = select i1 %330, float %209, float -0.000000e+00 %331 = call float @llvm.fabs.f32(float %321) %332 = fcmp ole float %331, -0.000000e+00 %..244 = select i1 %332, float %71, float %.244 %333 = call float @llvm.fabs.f32(float %321) %334 = fcmp ole float %333, -0.000000e+00 %temp56.2 = select i1 %334, float %72, float %temp60.0 %335 = call float @llvm.fabs.f32(float %321) %336 = fcmp ole float %335, -0.000000e+00 %..245 = select i1 %336, float %69, float %.245 %337 = call float @llvm.fabs.f32(float %321) %338 = fcmp ole float %337, -0.000000e+00 %temp56.4 = select i1 %338, float %70, float %temp60.2 %339 = call float @llvm.fabs.f32(float %322) %340 = fcmp ole float %339, -0.000000e+00 %...244 = select i1 %340, float %75, float %..244 %341 = call float @llvm.fabs.f32(float %322) %342 = fcmp ole float %341, -0.000000e+00 %temp56.6 = select i1 %342, float %76, float %temp56.2 %343 = call float @llvm.fabs.f32(float %322) %344 = fcmp ole float %343, -0.000000e+00 %...245 = select i1 %344, float %73, float %..245 %345 = call float @llvm.fabs.f32(float %322) %346 = fcmp ole float %345, -0.000000e+00 %temp56.8 = select i1 %346, float %74, float %temp56.4 %347 = fmul float %319, %...244 %348 = fadd float %347, %...245 %349 = fmul float %320, %temp56.6 %350 = fadd float %349, %temp56.8 %351 = fadd float %348, 0x3F40000000000000 %352 = fadd float %350, 0x3F40000000000000 %353 = fadd float %305, 0.000000e+00 %354 = bitcast float %353 to i32 %355 = bitcast float %351 to i32 %356 = bitcast float %352 to i32 %357 = insertelement <4 x i32> undef, i32 %354, i32 0 %358 = insertelement <4 x i32> %357, i32 %355, i32 1 %359 = insertelement <4 x i32> %358, i32 %356, i32 2 %360 = insertelement <4 x i32> %359, i32 0, i32 3 %361 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %360, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %362 = extractelement <4 x float> %361, i32 0 %363 = fadd float %348, 0xBF40000000000000 %364 = fadd float %350, 0x3F40000000000000 %365 = fadd float %305, 0.000000e+00 %366 = fadd float %348, 0x3F40000000000000 %367 = fadd float %350, 0xBF40000000000000 %368 = fadd float %305, 0.000000e+00 %369 = fadd float %348, 0xBF40000000000000 %370 = fadd float %350, 0xBF40000000000000 %371 = fadd float %305, 0.000000e+00 %372 = bitcast float %365 to i32 %373 = bitcast float %363 to i32 %374 = bitcast float %364 to i32 %375 = insertelement <4 x i32> undef, i32 %372, i32 0 %376 = insertelement <4 x i32> %375, i32 %373, i32 1 %377 = insertelement <4 x i32> %376, i32 %374, i32 2 %378 = insertelement <4 x i32> %377, i32 0, i32 3 %379 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %378, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %380 = extractelement <4 x float> %379, i32 0 %381 = bitcast float %368 to i32 %382 = bitcast float %366 to i32 %383 = bitcast float %367 to i32 %384 = insertelement <4 x i32> undef, i32 %381, i32 0 %385 = insertelement <4 x i32> %384, i32 %382, i32 1 %386 = insertelement <4 x i32> %385, i32 %383, i32 2 %387 = insertelement <4 x i32> %386, i32 0, i32 3 %388 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %387, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %389 = extractelement <4 x float> %388, i32 0 %390 = bitcast float %371 to i32 %391 = bitcast float %369 to i32 %392 = bitcast float %370 to i32 %393 = insertelement <4 x i32> undef, i32 %390, i32 0 %394 = insertelement <4 x i32> %393, i32 %391, i32 1 %395 = insertelement <4 x i32> %394, i32 %392, i32 2 %396 = insertelement <4 x i32> %395, i32 0, i32 3 %397 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %396, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %398 = extractelement <4 x float> %397, i32 0 %399 = fmul float %362, 6.250000e-02 %400 = fmul float %380, 6.250000e-02 %401 = fadd float %399, %400 %402 = fmul float %389, 6.250000e-02 %403 = fadd float %401, %402 %404 = fmul float %398, 6.250000e-02 %405 = fadd float %403, %404 %406 = fadd float %348, 0x3F40000000000000 %407 = fadd float %350, 0.000000e+00 %408 = fadd float %305, 0.000000e+00 %409 = bitcast float %408 to i32 %410 = bitcast float %406 to i32 %411 = bitcast float %407 to i32 %412 = insertelement <4 x i32> undef, i32 %409, i32 0 %413 = insertelement <4 x i32> %412, i32 %410, i32 1 %414 = insertelement <4 x i32> %413, i32 %411, i32 2 %415 = insertelement <4 x i32> %414, i32 0, i32 3 %416 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %415, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %417 = extractelement <4 x float> %416, i32 0 %418 = fadd float %348, 0xBF40000000000000 %419 = fadd float %350, 0.000000e+00 %420 = fadd float %305, 0.000000e+00 %421 = bitcast float %420 to i32 %422 = bitcast float %418 to i32 %423 = bitcast float %419 to i32 %424 = insertelement <4 x i32> undef, i32 %421, i32 0 %425 = insertelement <4 x i32> %424, i32 %422, i32 1 %426 = insertelement <4 x i32> %425, i32 %423, i32 2 %427 = insertelement <4 x i32> %426, i32 0, i32 3 %428 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %427, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %429 = extractelement <4 x float> %428, i32 0 %430 = fadd float %348, 0.000000e+00 %431 = fadd float %350, 0xBF40000000000000 %432 = fadd float %305, 0.000000e+00 %433 = bitcast float %432 to i32 %434 = bitcast float %430 to i32 %435 = bitcast float %431 to i32 %436 = insertelement <4 x i32> undef, i32 %433, i32 0 %437 = insertelement <4 x i32> %436, i32 %434, i32 1 %438 = insertelement <4 x i32> %437, i32 %435, i32 2 %439 = insertelement <4 x i32> %438, i32 0, i32 3 %440 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %439, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %441 = extractelement <4 x float> %440, i32 0 %442 = fadd float %348, 0.000000e+00 %443 = fadd float %350, 0x3F40000000000000 %444 = fadd float %305, 0.000000e+00 %445 = bitcast float %444 to i32 %446 = bitcast float %442 to i32 %447 = bitcast float %443 to i32 %448 = insertelement <4 x i32> undef, i32 %445, i32 0 %449 = insertelement <4 x i32> %448, i32 %446, i32 1 %450 = insertelement <4 x i32> %449, i32 %447, i32 2 %451 = insertelement <4 x i32> %450, i32 0, i32 3 %452 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %451, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %453 = extractelement <4 x float> %452, i32 0 %454 = fmul float %417, 1.250000e-01 %455 = fmul float %429, 1.250000e-01 %456 = fadd float %454, %455 %457 = fmul float %441, 1.250000e-01 %458 = fadd float %456, %457 %459 = fmul float %453, 1.250000e-01 %460 = fadd float %458, %459 %461 = bitcast float %305 to i32 %462 = bitcast float %348 to i32 %463 = bitcast float %350 to i32 %464 = insertelement <4 x i32> undef, i32 %461, i32 0 %465 = insertelement <4 x i32> %464, i32 %462, i32 1 %466 = insertelement <4 x i32> %465, i32 %463, i32 2 %467 = insertelement <4 x i32> %466, i32 -2147483648, i32 3 %468 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %467, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %469 = extractelement <4 x float> %468, i32 0 %470 = fadd float %460, %405 %471 = fmul float %469, 2.500000e-01 %472 = fadd float %471, %470 %473 = fcmp olt float %318, 1.000000e+00 br i1 %473, label %IF130, label %ENDIF129 ENDIF72: ; preds = %main_body, %ENDIF129 %temp8.0 = phi float [ %760, %ENDIF129 ], [ %200, %main_body ] %temp9.0 = phi float [ %764, %ENDIF129 ], [ %201, %main_body ] %temp10.0 = phi float [ %768, %ENDIF129 ], [ %202, %main_body ] %474 = fadd float %temp8.0, %38 %475 = fadd float %temp9.0, %39 %476 = fadd float %temp10.0, %40 %477 = fmul float %196, %474 %478 = fmul float %197, %475 %479 = fmul float %198, %476 %480 = fsub float %25, %124 %481 = fsub float %26, %125 %482 = fsub float %27, %126 %483 = fmul float %480, %480 %484 = fmul float %481, %481 %485 = fadd float %484, %483 %486 = fmul float %482, %482 %487 = fadd float %485, %486 %488 = call float @llvm.sqrt.f32(float %487) %489 = fmul float %488, %30 %490 = fadd float %489, %28 %491 = call float @llvm.AMDIL.clamp.(float %490, float 0.000000e+00, float 1.000000e+00) %492 = call float @llvm.minnum.f32(float %491, float %29) %493 = fmul float %477, %37 %494 = fmul float %478, %37 %495 = fmul float %479, %37 %496 = fmul float %492, %492 %497 = fmul float %37, %477 %498 = fsub float %34, %497 %499 = fmul float %37, %478 %500 = fsub float %35, %499 %501 = fmul float %37, %479 %502 = fsub float %36, %501 %503 = fmul float %496, %498 %504 = fadd float %503, %493 %505 = fmul float %496, %500 %506 = fadd float %505, %494 %507 = fmul float %496, %502 %508 = fadd float %507, %495 %509 = call i32 @llvm.SI.packf16(float %504, float %506) %510 = bitcast i32 %509 to float %511 = call i32 @llvm.SI.packf16(float %508, float %199) %512 = bitcast i32 %511 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %510, float %512, float %510, float %512) ret void IF130: ; preds = %IF73 %513 = fadd float %temp20.1, 0.000000e+00 %514 = fadd float %temp20.1, -1.000000e+00 %515 = fadd float %temp20.1, -2.000000e+00 %516 = call float @llvm.fabs.f32(float %513) %517 = fcmp ole float %516, -0.000000e+00 %.246 = select i1 %517, float %45, float -0.000000e+00 %518 = call float @llvm.fabs.f32(float %513) %519 = fcmp ole float %518, -0.000000e+00 %temp60.5 = select i1 %519, float %46, float -0.000000e+00 %520 = call float @llvm.fabs.f32(float %513) %521 = fcmp ole float %520, -0.000000e+00 %.247 = select i1 %521, float %47, float -0.000000e+00 %522 = call float @llvm.fabs.f32(float %513) %523 = fcmp ole float %522, -0.000000e+00 %temp60.7 = select i1 %523, float %48, float -0.000000e+00 %524 = call float @llvm.fabs.f32(float %513) %525 = fcmp ole float %524, -0.000000e+00 %.248 = select i1 %525, float %49, float -0.000000e+00 %526 = call float @llvm.fabs.f32(float %513) %527 = fcmp ole float %526, -0.000000e+00 %temp60.9 = select i1 %527, float %50, float -0.000000e+00 %528 = call float @llvm.fabs.f32(float %513) %529 = fcmp ole float %528, -0.000000e+00 %.249 = select i1 %529, float %51, float -0.000000e+00 %530 = call float @llvm.fabs.f32(float %513) %531 = fcmp ole float %530, -0.000000e+00 %temp60.11 = select i1 %531, float %52, float -0.000000e+00 %532 = call float @llvm.fabs.f32(float %514) %533 = fcmp ole float %532, -0.000000e+00 %..246 = select i1 %533, float %53, float %.246 %534 = call float @llvm.fabs.f32(float %514) %535 = fcmp ole float %534, -0.000000e+00 %temp60.13 = select i1 %535, float %54, float %temp60.5 %536 = call float @llvm.fabs.f32(float %514) %537 = fcmp ole float %536, -0.000000e+00 %..247 = select i1 %537, float %55, float %.247 %538 = call float @llvm.fabs.f32(float %514) %539 = fcmp ole float %538, -0.000000e+00 %temp60.15 = select i1 %539, float %56, float %temp60.7 %540 = call float @llvm.fabs.f32(float %514) %541 = fcmp ole float %540, -0.000000e+00 %..248 = select i1 %541, float %57, float %.248 %542 = call float @llvm.fabs.f32(float %514) %543 = fcmp ole float %542, -0.000000e+00 %temp60.17 = select i1 %543, float %58, float %temp60.9 %544 = call float @llvm.fabs.f32(float %514) %545 = fcmp ole float %544, -0.000000e+00 %..249 = select i1 %545, float %59, float %.249 %546 = call float @llvm.fabs.f32(float %514) %547 = fcmp ole float %546, -0.000000e+00 %temp60.19 = select i1 %547, float %60, float %temp60.11 %548 = call float @llvm.fabs.f32(float %515) %549 = fcmp ole float %548, -0.000000e+00 %...246 = select i1 %549, float %61, float %..246 %550 = call float @llvm.fabs.f32(float %515) %551 = fcmp ole float %550, -0.000000e+00 %temp60.21 = select i1 %551, float %62, float %temp60.13 %552 = call float @llvm.fabs.f32(float %515) %553 = fcmp ole float %552, -0.000000e+00 %...247 = select i1 %553, float %63, float %..247 %554 = call float @llvm.fabs.f32(float %515) %555 = fcmp ole float %554, -0.000000e+00 %temp60.23 = select i1 %555, float %64, float %temp60.15 %556 = call float @llvm.fabs.f32(float %515) %557 = fcmp ole float %556, -0.000000e+00 %...248 = select i1 %557, float %65, float %..248 %558 = call float @llvm.fabs.f32(float %515) %559 = fcmp ole float %558, -0.000000e+00 %temp60.25 = select i1 %559, float %66, float %temp60.17 %560 = call float @llvm.fabs.f32(float %515) %561 = fcmp ole float %560, -0.000000e+00 %...249 = select i1 %561, float %67, float %..249 %562 = call float @llvm.fabs.f32(float %515) %563 = fcmp ole float %562, -0.000000e+00 %temp60.27 = select i1 %563, float %68, float %temp60.19 %564 = fmul float %230, %...246 %565 = fmul float %231, %temp60.21 %566 = fadd float %564, %565 %567 = fmul float %232, %...247 %568 = fadd float %566, %567 %569 = fmul float %234, %temp60.23 %570 = fadd float %568, %569 %571 = call float @llvm.AMDIL.clamp.(float %570, float 0.000000e+00, float 1.000000e+00) %572 = fmul float %230, %...248 %573 = fmul float %231, %temp60.25 %574 = fadd float %572, %573 %575 = fmul float %232, %...249 %576 = fadd float %574, %575 %577 = fmul float %234, %temp60.27 %578 = fadd float %576, %577 %579 = call float @llvm.AMDIL.clamp.(float %578, float 0.000000e+00, float 1.000000e+00) %580 = call float @llvm.fabs.f32(float %513) %581 = fcmp ole float %580, -0.000000e+00 %.250 = select i1 %581, float %71, float -0.000000e+00 %582 = call float @llvm.fabs.f32(float %513) %583 = fcmp ole float %582, -0.000000e+00 %temp64.0 = select i1 %583, float %72, float -0.000000e+00 %584 = call float @llvm.fabs.f32(float %513) %585 = fcmp ole float %584, -0.000000e+00 %.251 = select i1 %585, float %69, float -0.000000e+00 %586 = call float @llvm.fabs.f32(float %513) %587 = fcmp ole float %586, -0.000000e+00 %temp64.2 = select i1 %587, float %70, float -0.000000e+00 %588 = call float @llvm.fabs.f32(float %514) %589 = fcmp ole float %588, -0.000000e+00 %..250 = select i1 %589, float %75, float %.250 %590 = call float @llvm.fabs.f32(float %514) %591 = fcmp ole float %590, -0.000000e+00 %temp60.29 = select i1 %591, float %76, float %temp64.0 %592 = call float @llvm.fabs.f32(float %514) %593 = fcmp ole float %592, -0.000000e+00 %..251 = select i1 %593, float %73, float %.251 %594 = call float @llvm.fabs.f32(float %514) %595 = fcmp ole float %594, -0.000000e+00 %temp60.31 = select i1 %595, float %74, float %temp64.2 %596 = call float @llvm.fabs.f32(float %515) %597 = fcmp ole float %596, -0.000000e+00 %...250 = select i1 %597, float %79, float %..250 %598 = call float @llvm.fabs.f32(float %515) %599 = fcmp ole float %598, -0.000000e+00 %temp60.33 = select i1 %599, float %80, float %temp60.29 %600 = call float @llvm.fabs.f32(float %515) %601 = fcmp ole float %600, -0.000000e+00 %...251 = select i1 %601, float %77, float %..251 %602 = call float @llvm.fabs.f32(float %515) %603 = fcmp ole float %602, -0.000000e+00 %temp60.35 = select i1 %603, float %78, float %temp60.31 %604 = fmul float %571, %...250 %605 = fadd float %604, %...251 %606 = fmul float %579, %temp60.33 %607 = fadd float %606, %temp60.35 %608 = fadd float %605, 0x3F40000000000000 %609 = fadd float %607, 0x3F40000000000000 %610 = fadd float %305, 0.000000e+00 %611 = bitcast float %610 to i32 %612 = bitcast float %608 to i32 %613 = bitcast float %609 to i32 %614 = insertelement <4 x i32> undef, i32 %611, i32 0 %615 = insertelement <4 x i32> %614, i32 %612, i32 1 %616 = insertelement <4 x i32> %615, i32 %613, i32 2 %617 = insertelement <4 x i32> %616, i32 0, i32 3 %618 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %617, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %619 = extractelement <4 x float> %618, i32 0 %620 = fadd float %605, 0xBF40000000000000 %621 = fadd float %607, 0x3F40000000000000 %622 = fadd float %305, 0.000000e+00 %623 = fadd float %605, 0x3F40000000000000 %624 = fadd float %607, 0xBF40000000000000 %625 = fadd float %305, 0.000000e+00 %626 = fadd float %605, 0xBF40000000000000 %627 = fadd float %607, 0xBF40000000000000 %628 = fadd float %305, 0.000000e+00 %629 = bitcast float %622 to i32 %630 = bitcast float %620 to i32 %631 = bitcast float %621 to i32 %632 = insertelement <4 x i32> undef, i32 %629, i32 0 %633 = insertelement <4 x i32> %632, i32 %630, i32 1 %634 = insertelement <4 x i32> %633, i32 %631, i32 2 %635 = insertelement <4 x i32> %634, i32 0, i32 3 %636 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %635, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %637 = extractelement <4 x float> %636, i32 0 %638 = bitcast float %625 to i32 %639 = bitcast float %623 to i32 %640 = bitcast float %624 to i32 %641 = insertelement <4 x i32> undef, i32 %638, i32 0 %642 = insertelement <4 x i32> %641, i32 %639, i32 1 %643 = insertelement <4 x i32> %642, i32 %640, i32 2 %644 = insertelement <4 x i32> %643, i32 0, i32 3 %645 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %644, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %646 = extractelement <4 x float> %645, i32 0 %647 = bitcast float %628 to i32 %648 = bitcast float %626 to i32 %649 = bitcast float %627 to i32 %650 = insertelement <4 x i32> undef, i32 %647, i32 0 %651 = insertelement <4 x i32> %650, i32 %648, i32 1 %652 = insertelement <4 x i32> %651, i32 %649, i32 2 %653 = insertelement <4 x i32> %652, i32 0, i32 3 %654 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %653, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %655 = extractelement <4 x float> %654, i32 0 %656 = fmul float %619, 6.250000e-02 %657 = fmul float %637, 6.250000e-02 %658 = fadd float %656, %657 %659 = fmul float %646, 6.250000e-02 %660 = fadd float %658, %659 %661 = fmul float %655, 6.250000e-02 %662 = fadd float %660, %661 %663 = fadd float %605, 0x3F40000000000000 %664 = fadd float %607, 0.000000e+00 %665 = fadd float %305, 0.000000e+00 %666 = bitcast float %665 to i32 %667 = bitcast float %663 to i32 %668 = bitcast float %664 to i32 %669 = insertelement <4 x i32> undef, i32 %666, i32 0 %670 = insertelement <4 x i32> %669, i32 %667, i32 1 %671 = insertelement <4 x i32> %670, i32 %668, i32 2 %672 = insertelement <4 x i32> %671, i32 0, i32 3 %673 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %672, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %674 = extractelement <4 x float> %673, i32 0 %675 = fadd float %605, 0xBF40000000000000 %676 = fadd float %607, 0.000000e+00 %677 = fadd float %305, 0.000000e+00 %678 = bitcast float %677 to i32 %679 = bitcast float %675 to i32 %680 = bitcast float %676 to i32 %681 = insertelement <4 x i32> undef, i32 %678, i32 0 %682 = insertelement <4 x i32> %681, i32 %679, i32 1 %683 = insertelement <4 x i32> %682, i32 %680, i32 2 %684 = insertelement <4 x i32> %683, i32 0, i32 3 %685 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %684, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %686 = extractelement <4 x float> %685, i32 0 %687 = fadd float %605, 0.000000e+00 %688 = fadd float %607, 0xBF40000000000000 %689 = fadd float %305, 0.000000e+00 %690 = bitcast float %689 to i32 %691 = bitcast float %687 to i32 %692 = bitcast float %688 to i32 %693 = insertelement <4 x i32> undef, i32 %690, i32 0 %694 = insertelement <4 x i32> %693, i32 %691, i32 1 %695 = insertelement <4 x i32> %694, i32 %692, i32 2 %696 = insertelement <4 x i32> %695, i32 0, i32 3 %697 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %696, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %698 = extractelement <4 x float> %697, i32 0 %699 = fadd float %605, 0.000000e+00 %700 = fadd float %607, 0x3F40000000000000 %701 = fadd float %305, 0.000000e+00 %702 = bitcast float %701 to i32 %703 = bitcast float %699 to i32 %704 = bitcast float %700 to i32 %705 = insertelement <4 x i32> undef, i32 %702, i32 0 %706 = insertelement <4 x i32> %705, i32 %703, i32 1 %707 = insertelement <4 x i32> %706, i32 %704, i32 2 %708 = insertelement <4 x i32> %707, i32 0, i32 3 %709 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %708, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %710 = extractelement <4 x float> %709, i32 0 %711 = fmul float %674, 1.250000e-01 %712 = fmul float %686, 1.250000e-01 %713 = fadd float %711, %712 %714 = fmul float %698, 1.250000e-01 %715 = fadd float %713, %714 %716 = fmul float %710, 1.250000e-01 %717 = fadd float %715, %716 %718 = bitcast float %305 to i32 %719 = bitcast float %605 to i32 %720 = bitcast float %607 to i32 %721 = insertelement <4 x i32> undef, i32 %718, i32 0 %722 = insertelement <4 x i32> %721, i32 %719, i32 1 %723 = insertelement <4 x i32> %722, i32 %720, i32 2 %724 = insertelement <4 x i32> %723, i32 -2147483648, i32 3 %725 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %724, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %726 = extractelement <4 x float> %725, i32 0 %727 = fadd float %717, %662 %728 = fmul float %726, 2.500000e-01 %729 = fadd float %728, %727 %730 = fcmp oge float %515, 0.000000e+00 %.252 = select i1 %730, float 1.000000e+00, float %729 %731 = fsub float 1.000000e+00, %318 %732 = fmul float %472, %318 %733 = fmul float %.252, %731 %734 = fadd float %732, %733 br label %ENDIF129 ENDIF129: ; preds = %IF73, %IF130 %temp24.0 = phi float [ %734, %IF130 ], [ %472, %IF73 ] %735 = fsub float %124, %81 %736 = fsub float %125, %82 %737 = fsub float %126, %83 %738 = fmul float %735, %735 %739 = fmul float %736, %736 %740 = fadd float %739, %738 %741 = fmul float %737, %737 %742 = fadd float %740, %741 %743 = fmul float %742, %44 %744 = fadd float %743, %43 %745 = call float @llvm.AMDIL.clamp.(float %744, float 0.000000e+00, float 1.000000e+00) %746 = fsub float 1.000000e+00, %745 %747 = fmul float %temp24.0, %746 %748 = fadd float %745, %747 %749 = fsub float 1.000000e+00, %748 %750 = fmul float %749, %229 %751 = fsub float 1.000000e+00, %750 %752 = fmul float %751, %202 %753 = fmul float %751, %201 %754 = fmul float %751, %200 %755 = fmul float %751, 5.000000e-01 %756 = fadd float %755, 5.000000e-01 %757 = fsub float 1.000000e+00, %756 %758 = fmul float %754, %756 %759 = fmul float %752, %757 %760 = fadd float %758, %759 %761 = fsub float 1.000000e+00, %756 %762 = fmul float %753, %756 %763 = fmul float %753, %761 %764 = fadd float %762, %763 %765 = fsub float 1.000000e+00, %756 %766 = fmul float %752, %756 %767 = fmul float %754, %765 %768 = fadd float %766, %767 br label %ENDIF72 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x0 ; C00E0803 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x20 ; C00E0603 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x40 ; C00E0403 00000040 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x60 ; C00E0B03 00000060 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x0 ; C00A0D02 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x10 ; C00A0A02 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x20 ; C00A0002 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[56:59], s[4:5], 0x30 ; C00A0E02 00000030 s_and_b32 s8, 1, s9 ; 86080981 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s11, s[12:15], 0x5a0 ; C02202C6 000005A0 v_cmp_eq_i32_e64 vcc, 1, s8 ; D0C2006A 00001081 v_cndmask_b32_e32 v10, v2, v0 ; 00140102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v11, v3, v1 ; 00160303 v_interp_p1_f32 v2, v10, 0, 0, [m0] ; D408000A v_interp_p2_f32 v2, [v2], v11, 0, 0, [m0] ; D409000B v_interp_p1_f32 v3, v10, 1, 0, [m0] ; D40C010A v_interp_p2_f32 v3, [v3], v11, 1, 0, [m0] ; D40D010B v_interp_p1_f32 v6, v10, 2, 0, [m0] ; D418020A v_interp_p2_f32 v6, [v6], v11, 2, 0, [m0] ; D419020B v_interp_p1_f32 v7, v10, 3, 0, [m0] ; D41C030A v_interp_p2_f32 v7, [v7], v11, 3, 0, [m0] ; D41D030B v_interp_p1_f32 v22, v10, 0, 1, [m0] ; D458040A v_interp_p2_f32 v22, [v22], v11, 0, 1, [m0] ; D459040B v_interp_p1_f32 v15, v10, 0, 2, [m0] ; D43C080A v_interp_p2_f32 v15, [v15], v11, 0, 2, [m0] ; D43D080B v_interp_p1_f32 v16, v10, 1, 2, [m0] ; D440090A v_interp_p2_f32 v16, [v16], v11, 1, 2, [m0] ; D441090B v_interp_p1_f32 v8, v10, 0, 3, [m0] ; D4200C0A v_interp_p2_f32 v8, [v8], v11, 0, 3, [m0] ; D4210C0B v_interp_p1_f32 v9, v10, 1, 3, [m0] ; D4240D0A v_interp_p2_f32 v9, [v9], v11, 1, 3, [m0] ; D4250D0B v_interp_p1_f32 v10, v10, 2, 3, [m0] ; D4280E0A v_interp_p2_f32 v10, [v10], v11, 2, 3, [m0] ; D4290E0B v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v4, v0, 0, 4, [m0] ; D4101000 v_interp_p2_f32 v4, [v4], v1, 0, 4, [m0] ; D4111001 v_interp_p1_f32 v5, v0, 1, 4, [m0] ; D4141100 v_interp_p2_f32 v5, [v5], v1, 1, 4, [m0] ; D4151101 v_interp_p1_f32 v23, v0, 2, 5, [m0] ; D45C1600 v_interp_p2_f32 v23, [v23], v1, 2, 5, [m0] ; D45D1601 v_interp_p1_f32 v24, v0, 3, 5, [m0] ; D4601700 v_interp_p2_f32 v24, [v24], v1, 3, 5, [m0] ; D4611701 image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[32:39], s[52:55] ; F0800F00 01A80B0F s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[44:51], s[56:59] ; F0800F00 01CB0F0F s_waitcnt vmcnt(0) ; BF8C0770 image_sample v[18:21], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[24:31], s[40:43] ; F0800F00 01461204 s_nop 0 ; BF800000 image_sample v[0:1], 3, 0, 0, 0, 0, 0, 0, 0, v[23:24], s[16:23], s[0:3] ; F0800300 00040017 s_waitcnt vmcnt(0) ; BF8C0770 v_subrev_f32_e32 v4, v0, v1 ; 06080300 v_add_f32_e32 v0, v1, v0 ; 02000101 v_min_f32_e32 v0, 1.0, v0 ; 140000F2 v_cmp_le_f32_e32 vcc, 0, v4 ; 7C860880 v_xor_b32_e32 v1, 0x80000000, v4 ; 2A0208FF 80000000 v_cndmask_b32_e32 v1, 0, v1 ; 00020280 s_buffer_load_dword s0, s[12:15], 0xc0 ; C0220006 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0xc4 ; C0220046 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0xc8 ; C0220086 000000C8 v_add_f32_e32 v0, v0, v1 ; 02000300 v_rcp_f32_e32 v0, v0 ; 7E004500 s_buffer_load_dword s9, s[12:15], 0xbc ; C0220246 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 v_add_f32_e32 v1, v22, v1 ; 02020316 v_mul_f32_e32 v0, v0, v1 ; 0A000300 v_add_f32_e64 v5, 0, v0 clamp ; D1018005 00020080 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s0, v18 ; 0A002400 v_mul_f32_e32 v1, s1, v19 ; 0A022601 v_mul_f32_e32 v4, s2, v20 ; 0A082802 v_cmp_lt_f32_e32 vcc, 0, v21 ; 7C822A80 v_cmp_ne_i32_e64 s[0:1], 0, s11 ; D0C50000 00001680 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[10:11], s[0:1] ; BE8A2000 s_xor_b64 s[10:11], exec, s[10:11] ; 888A0A7E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x440 ; C0220406 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x4a0 ; C0220506 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4a4 ; C0220546 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a8 ; C0220586 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4ac ; C02205C6 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4d0 ; C0220606 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d4 ; C0220646 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d8 ; C02206C6 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4dc ; C0220746 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4e0 ; C02207C6 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e4 ; C0220846 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4e8 ; C0220886 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4ec ; C02208C6 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s56, s[12:15], 0x550 ; C0220E06 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[12:15], 0x554 ; C0220E46 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[12:15], 0x558 ; C0220E86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x570 ; C0220946 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x574 ; C02209C6 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x578 ; C0220A46 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x57c ; C0220AC6 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x590 ; C02204C6 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x594 ; C0220486 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x598 ; C0220446 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x80 ; C00E0B03 00000080 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x40 ; C00A0D02 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[12:15], 0x55c ; C0220EC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x560 ; C0220906 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x564 ; C0220986 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x568 ; C0220A06 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x56c ; C0220A86 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x490 ; C0220686 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x494 ; C0220706 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x498 ; C0220786 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x49c ; C0220806 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v27, 0, v9 ; 02361280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v22, s66, v27 ; 0A2C3642 v_add_f32_e32 v29, 0, v8 ; 023A1080 v_add_f32_e32 v28, 0, v10 ; 02381480 v_mad_f32 v26, 0, v8, 1.0 ; D1C1001A 03CA1080 v_mac_f32_e32 v22, s3, v29 ; 2C2C3A03 v_mac_f32_e32 v22, s67, v28 ; 2C2C3843 v_mac_f32_e32 v22, s68, v26 ; 2C2C3444 v_mul_f32_e32 v23, s70, v27 ; 0A2E3646 v_mac_f32_e32 v23, s69, v29 ; 2C2E3A45 v_mac_f32_e32 v23, s61, v28 ; 2C2E383D v_mac_f32_e32 v23, s62, v26 ; 2C2E343E v_add_f32_e64 v24, 0, v22 clamp ; D1018018 00022C80 v_add_f32_e64 v25, 0, v23 clamp ; D1018019 00022E80 v_subrev_f32_e32 v24, v22, v24 ; 06303116 v_subrev_f32_e32 v25, v23, v25 ; 06323317 v_add_f32_e32 v24, v25, v24 ; 02303119 v_mul_f32_e32 v30, s28, v27 ; 0A3C361C v_mac_f32_e32 v30, s26, v29 ; 2C3C3A1A v_mac_f32_e32 v30, s30, v28 ; 2C3C381E v_mac_f32_e32 v30, s32, v26 ; 2C3C3420 v_mul_f32_e32 v31, s21, v27 ; 0A3E3615 v_mac_f32_e32 v31, s20, v29 ; 2C3E3A14 v_mac_f32_e32 v31, s22, v28 ; 2C3E3816 v_mac_f32_e32 v31, s23, v26 ; 2C3E3417 v_add_f32_e64 v25, 0, v30 clamp ; D1018019 00023C80 v_add_f32_e64 v32, 0, v31 clamp ; D1018020 00023E80 v_subrev_f32_e32 v25, v30, v25 ; 0632331E v_subrev_f32_e32 v32, v31, v32 ; 0640411F v_add_f32_e32 v32, v32, v25 ; 02403320 v_mul_f32_e32 v33, s25, v27 ; 0A423619 v_mac_f32_e32 v33, s24, v29 ; 2C423A18 v_mac_f32_e32 v33, s27, v28 ; 2C42381B v_mac_f32_e32 v33, s29, v26 ; 2C42341D v_mul_f32_e32 v34, s33, v27 ; 0A443621 v_mac_f32_e32 v34, s31, v29 ; 2C443A1F v_mac_f32_e32 v34, s34, v28 ; 2C443822 v_mac_f32_e32 v34, s35, v26 ; 2C443423 v_mov_b32_e32 v25, 0x80000000 ; 7E3202FF 80000000 v_cmp_le_f32_e64 vcc, |v32|, v25 ; D043016A 00023320 v_cndmask_b32_e32 v30, v33, v30 ; 003C3D21 v_cndmask_b32_e32 v31, v34, v31 ; 003E3F22 v_cndmask_b32_e64 v32, 2.0, 1.0, vcc ; D1000020 01A9E4F4 v_cmp_le_f32_e64 vcc, |v24|, v25 ; D043016A 00023318 v_cndmask_b32_e32 v30, v30, v22 ; 003C2D1E v_cndmask_b32_e32 v31, v31, v23 ; 003E2F1F v_cndmask_b32_e32 v33, v32, v25 ; 00423320 v_mul_f32_e32 v22, s64, v27 ; 0A2C3640 v_mac_f32_e32 v22, s63, v29 ; 2C2C3A3F v_mac_f32_e32 v22, s65, v28 ; 2C2C3841 v_mac_f32_e32 v22, s60, v26 ; 2C2C343C v_add_f32_e64 v32, 0, v30 clamp ; D1018020 00023C80 v_add_f32_e64 v34, 0, v31 clamp ; D1018022 00023E80 v_add_f32_e32 v23, -1.0, v33 ; 022E42F3 v_add_f32_e32 v24, -2.0, v33 ; 023042F5 v_cmp_le_f32_e64 vcc, |v33|, v25 ; D043016A 00023321 v_mov_b32_e32 v35, s58 ; 7E46023A v_cndmask_b32_e32 v35, v25, v35 ; 00464719 v_mov_b32_e32 v36, s59 ; 7E48023B v_cndmask_b32_e32 v36, v25, v36 ; 00484919 v_mov_b32_e32 v37, s56 ; 7E4A0238 v_cndmask_b32_e32 v37, v25, v37 ; 004A4B19 v_mov_b32_e32 v38, s57 ; 7E4C0239 v_cndmask_b32_e32 v38, v25, v38 ; 004C4D19 v_cmp_le_f32_e64 vcc, |v23|, v25 ; D043016A 00023317 v_mov_b32_e32 v23, s40 ; 7E2E0228 v_cndmask_b32_e32 v23, v35, v23 ; 002E2F23 v_mov_b32_e32 v35, s42 ; 7E46022A v_cndmask_b32_e32 v35, v36, v35 ; 00464724 v_mov_b32_e32 v36, s36 ; 7E480224 v_cndmask_b32_e32 v36, v37, v36 ; 00484925 v_mov_b32_e32 v37, s38 ; 7E4A0226 v_cndmask_b32_e32 v37, v38, v37 ; 004A4B26 v_cmp_le_f32_e64 vcc, |v24|, v25 ; D043016A 00023318 v_mov_b32_e32 v24, s41 ; 7E300229 v_cndmask_b32_e32 v38, v23, v24 ; 004C3117 v_mov_b32_e32 v23, s43 ; 7E2E022B v_cndmask_b32_e32 v35, v35, v23 ; 00462F23 v_mov_b32_e32 v23, s37 ; 7E2E0225 v_cndmask_b32_e32 v23, v36, v23 ; 002E2F24 v_mov_b32_e32 v24, s39 ; 7E300227 v_cndmask_b32_e32 v24, v37, v24 ; 00303125 v_mac_f32_e32 v23, v38, v32 ; 2C2E4126 v_mac_f32_e32 v24, v35, v34 ; 2C304523 v_mov_b32_e32 v32, 0x3a000000 ; 7E4002FF 3A000000 v_add_f32_e32 v35, v32, v23 ; 02462F20 v_add_f32_e32 v36, v32, v24 ; 02483120 v_add_f32_e32 v34, 0, v22 ; 02442C80 v_mov_b32_e32 v37, 0 ; 7E4A0280 v_mov_b32_e32 v32, 0xba000000 ; 7E4002FF BA000000 v_add_f32_e32 v38, v32, v23 ; 024C2F20 v_mov_b32_e32 v39, v34 ; 7E4E0322 v_mov_b32_e32 v40, v35 ; 7E500323 v_mov_b32_e32 v41, v36 ; 7E520324 v_mov_b32_e32 v42, v37 ; 7E540325 v_add_f32_e32 v32, v32, v24 ; 02403120 v_mov_b32_e32 v40, v38 ; 7E500326 v_mov_b32_e32 v43, v34 ; 7E560322 v_mov_b32_e32 v44, v35 ; 7E580323 v_mov_b32_e32 v45, v36 ; 7E5A0324 v_mov_b32_e32 v46, v37 ; 7E5C0325 v_mov_b32_e32 v41, v36 ; 7E520324 v_mov_b32_e32 v45, v32 ; 7E5A0320 v_mov_b32_e32 v42, v37 ; 7E540325 v_mov_b32_e32 v46, v37 ; 7E5C0325 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2622 s_nop 0 ; BF800000 image_sample_c_l v47, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[52:55] ; F0B00100 01AB2F27 v_mov_b32_e32 v41, v32 ; 7E520320 image_sample_c_l v43, 1, 0, 0, 0, 0, 0, 0, 0, v[43:46], s[44:51], s[52:55] ; F0B00100 01AB2B2B v_mov_b32_e32 v42, v37 ; 7E540325 image_sample_c_l v44, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[52:55] ; F0B00100 01AB2C27 v_add_f32_e32 v41, 0, v24 ; 02523080 v_mov_b32_e32 v48, v34 ; 7E600322 v_mov_b32_e32 v49, v35 ; 7E620323 v_mov_b32_e32 v50, v36 ; 7E640324 v_mov_b32_e32 v51, v37 ; 7E660325 v_mov_b32_e32 v50, v41 ; 7E640329 v_mov_b32_e32 v51, v37 ; 7E660325 v_mov_b32_e32 v42, v37 ; 7E540325 v_add_f32_e32 v35, 0, v23 ; 02462E80 v_mov_b32_e32 v52, v34 ; 7E680322 v_mov_b32_e32 v53, v35 ; 7E6A0323 v_mov_b32_e32 v54, v36 ; 7E6C0324 v_mov_b32_e32 v55, v37 ; 7E6E0325 image_sample_c_l v45, 1, 0, 0, 0, 0, 0, 0, 0, v[48:51], s[44:51], s[52:55] ; F0B00100 01AB2D30 v_mov_b32_e32 v54, v32 ; 7E6C0320 image_sample_c_l v32, 1, 0, 0, 0, 0, 0, 0, 0, v[39:42], s[44:51], s[52:55] ; F0B00100 01AB2027 v_mov_b32_e32 v55, v37 ; 7E6E0325 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[52:55], s[44:51], s[52:55] ; F0B00100 01AB2734 s_nop 0 ; BF800000 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2222 v_mov_b32_e32 v35, 0x3d800000 ; 7E4602FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v36, v35, v47 ; 0A485F23 v_mac_f32_e32 v36, v35, v38 ; 2C484D23 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v36, v35, v43 ; 2C485723 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v36, v35, v44 ; 2C485923 v_mov_b32_e32 v35, 0x3e000000 ; 7E4602FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v37, v35, v32 ; 0A4A4123 v_mac_f32_e32 v37, v35, v45 ; 2C4A5B23 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v37, v35, v39 ; 2C4A4F23 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v37, v35, v34 ; 2C4A4523 v_add_f32_e32 v30, -0.5, v30 ; 023C3CF1 v_add_f32_e32 v31, -0.5, v31 ; 023E3EF1 v_sub_f32_e64 v30, |v30|, s1 ; D102011E 0000031E v_sub_f32_e64 v31, |v31|, s1 ; D102011F 0000031F v_mul_f32_e32 v30, s2, v30 ; 0A3C3C02 v_mul_f32_e32 v31, s2, v31 ; 0A3E3E02 v_add_f32_e64 v30, 0, v30 clamp ; D101801E 00023C80 v_add_f32_e64 v31, 0, v31 clamp ; D101801F 00023E80 v_sub_f32_e32 v30, 1.0, v30 ; 043C3CF2 v_mad_f32 v32, -v31, v30, v30 ; D1C10020 247A3D1F v_add_f32_e32 v30, v36, v37 ; 023C4B24 image_sample_c_l v23, 1, 0, 0, 0, 0, 0, 0, 0, v[22:25], s[44:51], s[52:55] ; F0B00100 01AB1716 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v30, v23, v30, 0x3e800000 ; 2E3C3D17 3E800000 v_mov_b32_e32 v31, s0 ; 7E3E0200 v_cmp_gt_f32_e32 vcc, 1.0, v32 ; 7C8840F2 s_and_saveexec_b64 s[56:57], vcc ; BEB8206A s_xor_b64 s[56:57], exec, s[56:57] ; 88B8387E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s58, s[12:15], 0x510 ; C0220E86 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[12:15], 0x514 ; C0220EC6 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x518 ; C0220F06 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x51c ; C0220F46 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x520 ; C0220F86 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x524 ; C0220FC6 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x528 ; C0221006 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x52c ; C0221046 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x580 ; C0221086 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x584 ; C02210C6 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x588 ; C0221106 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x58c ; C0221146 0000058C v_mov_b32_e32 v25, 0x80000000 ; 7E3202FF 80000000 v_mov_b32_e32 v23, s26 ; 7E2E021A v_mov_b32_e32 v24, s28 ; 7E30021C v_mov_b32_e32 v34, s30 ; 7E44021E v_mov_b32_e32 v35, s32 ; 7E460220 v_mov_b32_e32 v36, s20 ; 7E480214 v_mov_b32_e32 v37, s21 ; 7E4A0215 v_mov_b32_e32 v38, s22 ; 7E4C0216 v_mov_b32_e32 v39, s23 ; 7E4E0217 v_mov_b32_e32 v40, s24 ; 7E500218 v_mov_b32_e32 v41, s25 ; 7E520219 v_mov_b32_e32 v42, s27 ; 7E54021B v_mov_b32_e32 v43, s29 ; 7E56021D v_add_f32_e32 v44, 0, v33 ; 02584280 v_cmp_le_f32_e64 vcc, |v44|, v25 ; D043016A 0002332C v_add_f32_e32 v44, -1.0, v33 ; 025842F3 v_cmp_le_f32_e64 s[0:1], |v44|, v25 ; D0430100 0002332C v_mov_b32_e32 v44, s31 ; 7E58021F v_cndmask_b32_e32 v23, v25, v23 ; 002E2F19 v_cndmask_b32_e64 v23, v23, v40, s[0:1] ; D1000017 00025117 v_mov_b32_e32 v40, s33 ; 7E500221 v_cndmask_b32_e32 v24, v25, v24 ; 00303119 v_cndmask_b32_e64 v24, v24, v41, s[0:1] ; D1000018 00025318 v_mov_b32_e32 v41, s34 ; 7E520222 v_cndmask_b32_e32 v34, v25, v34 ; 00444519 v_cndmask_b32_e64 v34, v34, v42, s[0:1] ; D1000022 00025522 v_mov_b32_e32 v42, s35 ; 7E540223 v_cndmask_b32_e32 v35, v25, v35 ; 00464719 v_cndmask_b32_e64 v35, v35, v43, s[0:1] ; D1000023 00025723 v_mov_b32_e32 v43, s36 ; 7E560224 v_cndmask_b32_e32 v36, v25, v36 ; 00484919 v_cndmask_b32_e64 v36, v36, v44, s[0:1] ; D1000024 00025924 v_mov_b32_e32 v44, s38 ; 7E580226 v_cndmask_b32_e32 v37, v25, v37 ; 004A4B19 v_cndmask_b32_e64 v37, v37, v40, s[0:1] ; D1000025 00025125 v_mov_b32_e32 v40, s40 ; 7E500228 v_cndmask_b32_e32 v38, v25, v38 ; 004C4D19 v_cndmask_b32_e64 v38, v38, v41, s[0:1] ; D1000026 00025326 v_mov_b32_e32 v41, s42 ; 7E52022A v_add_f32_e32 v33, -2.0, v33 ; 024242F5 v_cndmask_b32_e32 v39, v25, v39 ; 004E4F19 v_cndmask_b32_e64 v39, v39, v42, s[0:1] ; D1000027 00025527 v_cmp_le_f32_e64 s[2:3], |v33|, v25 ; D0430102 00023321 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v42, s58 ; 7E54023A v_cndmask_b32_e64 v23, v23, v42, s[2:3] ; D1000017 000A5517 v_mov_b32_e32 v42, s59 ; 7E54023B v_cndmask_b32_e64 v24, v24, v42, s[2:3] ; D1000018 000A5518 v_mov_b32_e32 v42, s60 ; 7E54023C v_cndmask_b32_e64 v34, v34, v42, s[2:3] ; D1000022 000A5522 v_mov_b32_e32 v42, s61 ; 7E54023D v_cndmask_b32_e64 v35, v35, v42, s[2:3] ; D1000023 000A5523 v_mov_b32_e32 v42, s62 ; 7E54023E v_cndmask_b32_e64 v36, v36, v42, s[2:3] ; D1000024 000A5524 v_mov_b32_e32 v42, s63 ; 7E54023F v_cndmask_b32_e64 v37, v37, v42, s[2:3] ; D1000025 000A5525 v_mov_b32_e32 v42, s64 ; 7E540240 v_cndmask_b32_e64 v38, v38, v42, s[2:3] ; D1000026 000A5526 v_mov_b32_e32 v42, s65 ; 7E540241 v_cndmask_b32_e64 v39, v39, v42, s[2:3] ; D1000027 000A5527 v_mov_b32_e32 v42, s37 ; 7E540225 v_mul_f32_e32 v24, v24, v27 ; 0A303718 v_mac_f32_e32 v24, v23, v29 ; 2C303B17 v_mov_b32_e32 v23, s39 ; 7E2E0227 v_mac_f32_e32 v24, v34, v28 ; 2C303922 v_mov_b32_e32 v34, s41 ; 7E440229 v_mac_f32_e32 v24, v35, v26 ; 2C303523 v_mov_b32_e32 v35, s43 ; 7E46022B v_add_f32_e64 v45, 0, v24 clamp ; D101802D 00023080 v_mul_f32_e32 v24, v37, v27 ; 0A303725 v_mac_f32_e32 v24, v36, v29 ; 2C303B24 v_mac_f32_e32 v24, v38, v28 ; 2C303926 v_mac_f32_e32 v24, v39, v26 ; 2C303527 v_add_f32_e64 v26, 0, v24 clamp ; D101801A 00023080 v_cndmask_b32_e32 v24, v25, v40 ; 00305119 v_cndmask_b32_e32 v27, v25, v41 ; 00365319 v_cndmask_b32_e32 v28, v25, v43 ; 00385719 v_cndmask_b32_e32 v29, v25, v44 ; 003A5919 v_cndmask_b32_e64 v24, v24, v34, s[0:1] ; D1000018 00024518 v_cndmask_b32_e64 v27, v27, v35, s[0:1] ; D100001B 0002471B v_cndmask_b32_e64 v28, v28, v42, s[0:1] ; D100001C 0002551C v_cndmask_b32_e64 v29, v29, v23, s[0:1] ; D100001D 00022F1D v_mov_b32_e32 v23, s68 ; 7E2E0244 v_cndmask_b32_e64 v34, v24, v23, s[2:3] ; D1000022 000A2F18 v_mov_b32_e32 v23, s69 ; 7E2E0245 v_cndmask_b32_e64 v27, v27, v23, s[2:3] ; D100001B 000A2F1B v_mov_b32_e32 v23, s66 ; 7E2E0242 v_cndmask_b32_e64 v23, v28, v23, s[2:3] ; D1000017 000A2F1C v_mov_b32_e32 v24, s67 ; 7E300243 v_cndmask_b32_e64 v24, v29, v24, s[2:3] ; D1000018 000A311D v_mac_f32_e32 v23, v34, v45 ; 2C2E5B22 v_mac_f32_e32 v24, v27, v26 ; 2C30351B v_mov_b32_e32 v26, 0x3a000000 ; 7E3402FF 3A000000 v_add_f32_e32 v35, v26, v23 ; 02462F1A v_add_f32_e32 v36, v26, v24 ; 0248311A v_add_f32_e32 v34, 0, v22 ; 02442C80 v_mov_b32_e32 v37, 0 ; 7E4A0280 v_mov_b32_e32 v26, 0xba000000 ; 7E3402FF BA000000 v_add_f32_e32 v27, v26, v23 ; 02362F1A v_mov_b32_e32 v38, v34 ; 7E4C0322 v_mov_b32_e32 v39, v35 ; 7E4E0323 v_mov_b32_e32 v40, v36 ; 7E500324 v_mov_b32_e32 v41, v37 ; 7E520325 v_mov_b32_e32 v39, v27 ; 7E4E031B v_add_f32_e32 v26, v26, v24 ; 0234311A v_mov_b32_e32 v40, v36 ; 7E500324 v_mov_b32_e32 v42, v34 ; 7E540322 v_mov_b32_e32 v43, v35 ; 7E560323 v_mov_b32_e32 v44, v36 ; 7E580324 v_mov_b32_e32 v45, v37 ; 7E5A0325 image_sample_c_l v27, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB1B22 v_mov_b32_e32 v41, v37 ; 7E520325 v_mov_b32_e32 v44, v26 ; 7E58031A image_sample_c_l v28, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB1C26 v_mov_b32_e32 v45, v37 ; 7E5A0325 v_mov_b32_e32 v40, v26 ; 7E50031A image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[44:51], s[52:55] ; F0B00100 01AB1D2A v_mov_b32_e32 v41, v37 ; 7E520325 image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB2A26 v_add_f32_e32 v40, 0, v24 ; 02503080 v_mov_b32_e32 v43, v34 ; 7E560322 v_mov_b32_e32 v44, v35 ; 7E580323 v_mov_b32_e32 v45, v36 ; 7E5A0324 v_mov_b32_e32 v46, v37 ; 7E5C0325 v_mov_b32_e32 v45, v40 ; 7E5A0328 v_mov_b32_e32 v46, v37 ; 7E5C0325 v_mov_b32_e32 v41, v37 ; 7E520325 v_add_f32_e32 v35, 0, v23 ; 02462E80 v_mov_b32_e32 v47, v34 ; 7E5E0322 v_mov_b32_e32 v48, v35 ; 7E600323 v_mov_b32_e32 v49, v36 ; 7E620324 v_mov_b32_e32 v50, v37 ; 7E640325 image_sample_c_l v43, 1, 0, 0, 0, 0, 0, 0, 0, v[43:46], s[44:51], s[52:55] ; F0B00100 01AB2B2B v_mov_b32_e32 v49, v26 ; 7E62031A image_sample_c_l v26, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[44:51], s[52:55] ; F0B00100 01AB1A26 v_mov_b32_e32 v50, v37 ; 7E640325 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[47:50], s[44:51], s[52:55] ; F0B00100 01AB262F s_nop 0 ; BF800000 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[34:37], s[44:51], s[52:55] ; F0B00100 01AB2222 s_nop 0 ; BF800000 image_sample_c_l v22, 1, 0, 0, 0, 0, 0, 0, 0, v[22:25], s[44:51], s[52:55] ; F0B00100 01AB1616 v_mov_b32_e32 v23, 0x3d800000 ; 7E2E02FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v24, v23, v28 ; 0A303917 v_mac_f32_e32 v24, v23, v27 ; 2C303717 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v24, v23, v29 ; 2C303B17 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v24, v23, v42 ; 2C305517 v_mov_b32_e32 v23, 0x3e000000 ; 7E2E02FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v25, v23, v26 ; 0A323517 v_mac_f32_e32 v25, v23, v43 ; 2C325717 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v25, v23, v38 ; 2C324D17 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v25, v23, v34 ; 2C324517 v_add_f32_e32 v23, v24, v25 ; 022E3318 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v22, v22, v23, 0x3e800000 ; 2E2C2F16 3E800000 v_cmp_le_f32_e32 vcc, 0, v33 ; 7C864280 v_cndmask_b32_e64 v22, v22, 1.0, vcc ; D1000016 01A9E516 v_mad_f32 v22, -v32, v22, v22 ; D1C10016 245A2D20 v_mac_f32_e32 v22, v32, v30 ; 2C2C3D20 v_mov_b32_e32 v30, v22 ; 7E3C0316 s_or_b64 exec, exec, s[56:57] ; 87FE387E v_mul_f32_e32 v18, 0x3e59999a, v18 ; 0A2424FF 3E59999A v_madmk_f32_e32 v18, v19, v18, 0x3f372474 ; 2E242513 3F372474 v_madmk_f32_e32 v18, v20, v18, 0x3d93a92a ; 2E242514 3D93A92A v_rcp_f32_e32 v18, v18 ; 7E244512 v_mul_f32_e32 v18, v21, v18 ; 0A242515 v_subrev_f32_e32 v19, s19, v8 ; 06261013 v_subrev_f32_e32 v20, s18, v9 ; 06281212 v_subrev_f32_e32 v21, s17, v10 ; 062A1411 v_mul_f32_e32 v19, v19, v19 ; 0A262713 v_mac_f32_e32 v19, v20, v20 ; 2C262914 v_mac_f32_e32 v19, v21, v21 ; 2C262B15 v_mad_f32 v19, v31, v19, s16 ; D1C10013 0042271F v_add_f32_e64 v19, 0, v19 clamp ; D1018013 00022680 v_sub_f32_e32 v20, 1.0, v19 ; 042826F2 v_mac_f32_e32 v19, v20, v30 ; 2C263D14 v_sub_f32_e32 v20, 1.0, v19 ; 042826F2 v_mad_f32 v19, -v19, v18, v18 ; D1C10013 244A2513 v_mad_f32 v18, -v20, v18, 1.0 ; D1C10012 23CA2514 v_mad_f32 v20, -v19, v4, v4 ; D1C10014 24120913 v_mad_f32 v4, -v19, v1, v1 ; D1C10004 24060313 v_mad_f32 v19, -v19, v0, v0 ; D1C10013 24020113 v_mad_f32 v18, 0.5, v18, 0.5 ; D1C10012 03C224F0 v_mad_f32 v0, -v18, v20, v20 ; D1C10000 24522912 v_mac_f32_e32 v0, v18, v19 ; 2C002712 v_mad_f32 v1, -v18, v4, v4 ; D1C10001 24120912 v_mac_f32_e32 v1, v18, v4 ; 2C020912 v_mad_f32 v4, -v18, v19, v19 ; D1C10004 244E2712 v_mac_f32_e32 v4, v18, v20 ; 2C082912 s_or_b64 exec, exec, s[10:11] ; 87FE0A7E s_buffer_load_dword s5, s[12:15], 0xa0 ; C0220146 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0xa4 ; C0220186 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0xa8 ; C02201C6 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xb0 ; C0220106 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0xb8 ; C0220046 000000B8 v_mov_b32_e32 v19, s9 ; 7E260209 v_mov_b32_e32 v18, s8 ; 7E240208 s_buffer_load_dword s3, s[12:15], 0x1d0 ; C02200C6 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d4 ; C0220086 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x1d8 ; C0220006 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x1f0 ; C0220446 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x1f4 ; C0220406 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x1f8 ; C0220246 000001F8 v_madak_f32_e32 v20, -2.0, v5, 0x40400000 ; 30280AF5 40400000 v_mul_f32_e32 v5, v5, v5 ; 0A0A0B05 v_mul_f32_e32 v5, v20, v5 ; 0A0A0B14 v_mad_f32 v11, -v5, v11, v11 ; D1C1000B 242E1705 v_mac_f32_e32 v11, v5, v15 ; 2C161F05 v_mad_f32 v12, -v5, v12, v12 ; D1C1000C 24321905 v_mac_f32_e32 v12, v5, v16 ; 2C182105 v_mad_f32 v13, -v5, v13, v13 ; D1C1000D 24361B05 v_mac_f32_e32 v13, v5, v17 ; 2C1A2305 v_mul_f32_e32 v5, v2, v11 ; 0A0A1702 v_mul_f32_e32 v3, v3, v12 ; 0A061903 v_mul_f32_e32 v6, v6, v13 ; 0A0C1B06 v_mul_f32_e32 v2, v7, v14 ; 0A041D07 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v0, s17, v0 ; 02000011 v_add_f32_e32 v1, s16, v1 ; 02020210 v_add_f32_e32 v4, s9, v4 ; 02080809 v_mul_f32_e32 v0, v0, v5 ; 0A000B00 v_mul_f32_e32 v1, v1, v3 ; 0A020701 v_mul_f32_e32 v3, v4, v6 ; 0A060D04 v_sub_f32_e32 v4, s5, v8 ; 04081005 v_sub_f32_e32 v5, s6, v9 ; 040A1206 v_sub_f32_e32 v6, s7, v10 ; 040C1407 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mac_f32_e32 v4, v5, v5 ; 2C080B05 v_mac_f32_e32 v4, v6, v6 ; 2C080D06 v_sqrt_f32_e32 v4, v4 ; 7E084F04 v_mad_f32 v4, v19, v4, s4 ; D1C10004 00120913 v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_min_f32_e32 v4, s1, v4 ; 14080801 v_mul_f32_e32 v5, s8, v0 ; 0A0A0008 v_mul_f32_e32 v6, s8, v1 ; 0A0C0208 v_mul_f32_e32 v7, s8, v3 ; 0A0E0608 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mad_f32 v0, -v0, v18, s3 ; D1C10000 200E2500 v_mad_f32 v1, -v1, v18, s2 ; D1C10001 200A2501 v_mad_f32 v3, -v3, v18, s0 ; D1C10003 20022503 v_mac_f32_e32 v5, v0, v4 ; 2C0A0900 v_mac_f32_e32 v6, v1, v4 ; 2C0C0901 v_mac_f32_e32 v7, v3, v4 ; 2C0E0903 v_cvt_pkrtz_f16_f32_e64 v0, v5, v6 ; D2960000 00020D05 v_cvt_pkrtz_f16_f32_e64 v1, v7, v2 ; D2960001 00020507 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 56 Code Size: 3364 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], CLIPVERTEX DCL OUT[3], GENERIC[0] DCL OUT[4], GENERIC[1] DCL OUT[5], GENERIC[2] DCL OUT[6], GENERIC[3] DCL OUT[7], GENERIC[4] DCL CONST[0..51] DCL TEMP[0..8], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, CONST[0].yyyy 2: MAD TEMP[2], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 3: DP4 TEMP[1].x, TEMP[2], CONST[48] 4: DP4 TEMP[3].x, TEMP[2], CONST[49] 5: MOV TEMP[1].y, TEMP[3].xxxx 6: DP4 TEMP[3].x, TEMP[2], CONST[50] 7: MOV TEMP[1].z, TEMP[3].xxxx 8: DP4 TEMP[3].x, TEMP[1], CONST[8] 9: DP4 TEMP[4].x, TEMP[1], CONST[9] 10: MOV TEMP[3].y, TEMP[4].xxxx 11: DP4 TEMP[5].x, TEMP[1], CONST[11] 12: MOV TEMP[3].w, TEMP[5].xxxx 13: DP4 TEMP[6].x, TEMP[1], CONST[10] 14: MOV TEMP[1].w, TEMP[6].xxxx 15: MOV TEMP[1], TEMP[1] 16: ADD TEMP[2].xy, IN[3].xyyy, IN[2].xyyy 17: ADD TEMP[7].xy, TEMP[2].yxxx, IN[3].yxxx 18: MOV TEMP[2].zw, TEMP[7].yyxy 19: ADD TEMP[7].xy, TEMP[7].yxxx, IN[3].xyyy 20: MOV TEMP[3].z, TEMP[6].xxxx 21: MOV TEMP[0].xy, IN[1].xyxx 22: MOV TEMP[7].zw, IN[1].yyxy 23: MOV TEMP[8], TEMP[3] 24: MAD TEMP[6].x, TEMP[6].xxxx, CONST[0].zzzz, -TEMP[5].xxxx 25: MOV TEMP[3].z, TEMP[6].xxxx 26: MOV TEMP[3].y, -TEMP[4].xxxx 27: MAD TEMP[3].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[3].xyyy 28: MUL TEMP[4], CONST[0].yyxx, IN[1].xyxx 29: MAD TEMP[5], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 30: MOV OUT[3], TEMP[0] 31: MOV OUT[4], TEMP[4] 32: MOV OUT[6], TEMP[2] 33: MOV OUT[7], TEMP[7] 34: MOV OUT[5], TEMP[1] 35: MOV OUT[0], TEMP[3] 36: MOV OUT[2], TEMP[8] 37: MOV OUT[1], TEMP[5] 38: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, align 16, !tbaa !0 %69 = add i32 %5, %8 %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69) %71 = extractelement <4 x float> %70, i32 0 %72 = extractelement <4 x float> %70, i32 1 %73 = fmul float %52, %15 %74 = fadd float %73, %14 %75 = fmul float %53, %15 %76 = fadd float %75, %14 %77 = fmul float %54, %15 %78 = fadd float %77, %14 %79 = fmul float %52, %14 %80 = fadd float %79, %15 %81 = fmul float %74, %34 %82 = fmul float %76, %35 %83 = fadd float %81, %82 %84 = fmul float %78, %36 %85 = fadd float %83, %84 %86 = fmul float %80, %37 %87 = fadd float %85, %86 %88 = fmul float %74, %38 %89 = fmul float %76, %39 %90 = fadd float %88, %89 %91 = fmul float %78, %40 %92 = fadd float %90, %91 %93 = fmul float %80, %41 %94 = fadd float %92, %93 %95 = fmul float %74, %42 %96 = fmul float %76, %43 %97 = fadd float %95, %96 %98 = fmul float %78, %44 %99 = fadd float %97, %98 %100 = fmul float %80, %45 %101 = fadd float %99, %100 %102 = fmul float %87, %17 %103 = fmul float %94, %18 %104 = fadd float %102, %103 %105 = fmul float %101, %19 %106 = fadd float %104, %105 %107 = fmul float %15, %20 %108 = fadd float %106, %107 %109 = fmul float %87, %21 %110 = fmul float %94, %22 %111 = fadd float %109, %110 %112 = fmul float %101, %23 %113 = fadd float %111, %112 %114 = fmul float %15, %24 %115 = fadd float %113, %114 %116 = fmul float %87, %29 %117 = fmul float %94, %30 %118 = fadd float %116, %117 %119 = fmul float %101, %31 %120 = fadd float %118, %119 %121 = fmul float %15, %32 %122 = fadd float %120, %121 %123 = fmul float %87, %25 %124 = fmul float %94, %26 %125 = fadd float %123, %124 %126 = fmul float %101, %27 %127 = fadd float %125, %126 %128 = fmul float %15, %28 %129 = fadd float %127, %128 %130 = fadd float %71, %65 %131 = fadd float %72, %66 %132 = fadd float %131, %72 %133 = fadd float %130, %71 %134 = fadd float %133, %71 %135 = fadd float %132, %72 %136 = fmul float %129, %16 %137 = fsub float %136, %122 %138 = fmul float %46, %122 %139 = fadd float %138, %108 %140 = fmul float %47, %122 %141 = fsub float %140, %115 %142 = fmul float %15, %59 %143 = fmul float %15, %60 %144 = fmul float %14, %59 %145 = fmul float %14, %59 %146 = fmul float %33, %14 %147 = fadd float %146, %15 %148 = fmul float %33, %14 %149 = fadd float %148, %15 %150 = fmul float %33, %14 %151 = fadd float %150, %15 %152 = fmul float %33, %15 %153 = fadd float %152, %14 %154 = and i32 %7, 1 %155 = icmp eq i32 %154, 0 br i1 %155, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %156 = call float @llvm.AMDIL.clamp.(float %147, float 0.000000e+00, float 1.000000e+00) %157 = call float @llvm.AMDIL.clamp.(float %149, float 0.000000e+00, float 1.000000e+00) %158 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00) %159 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.038 = phi float [ %159, %if-true-block ], [ %153, %main_body ] %.037 = phi float [ %158, %if-true-block ], [ %151, %main_body ] %.036 = phi float [ %157, %if-true-block ], [ %149, %main_body ] %.0 = phi float [ %156, %if-true-block ], [ %147, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.036, float %.037, float %.038) %160 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %161 = load <16 x i8>, <16 x i8> addrspace(2)* %160, align 16, !tbaa !0 %162 = call float @llvm.SI.load.const(<16 x i8> %161, i32 0) %163 = fmul float %162, %108 %164 = call float @llvm.SI.load.const(<16 x i8> %161, i32 4) %165 = fmul float %164, %115 %166 = fadd float %163, %165 %167 = call float @llvm.SI.load.const(<16 x i8> %161, i32 8) %168 = fmul float %167, %129 %169 = fadd float %166, %168 %170 = call float @llvm.SI.load.const(<16 x i8> %161, i32 12) %171 = fmul float %170, %122 %172 = fadd float %169, %171 %173 = call float @llvm.SI.load.const(<16 x i8> %161, i32 16) %174 = fmul float %173, %108 %175 = call float @llvm.SI.load.const(<16 x i8> %161, i32 20) %176 = fmul float %175, %115 %177 = fadd float %174, %176 %178 = call float @llvm.SI.load.const(<16 x i8> %161, i32 24) %179 = fmul float %178, %129 %180 = fadd float %177, %179 %181 = call float @llvm.SI.load.const(<16 x i8> %161, i32 28) %182 = fmul float %181, %122 %183 = fadd float %180, %182 %184 = call float @llvm.SI.load.const(<16 x i8> %161, i32 32) %185 = fmul float %184, %108 %186 = call float @llvm.SI.load.const(<16 x i8> %161, i32 36) %187 = fmul float %186, %115 %188 = fadd float %185, %187 %189 = call float @llvm.SI.load.const(<16 x i8> %161, i32 40) %190 = fmul float %189, %129 %191 = fadd float %188, %190 %192 = call float @llvm.SI.load.const(<16 x i8> %161, i32 44) %193 = fmul float %192, %122 %194 = fadd float %191, %193 %195 = call float @llvm.SI.load.const(<16 x i8> %161, i32 48) %196 = fmul float %195, %108 %197 = call float @llvm.SI.load.const(<16 x i8> %161, i32 52) %198 = fmul float %197, %115 %199 = fadd float %196, %198 %200 = call float @llvm.SI.load.const(<16 x i8> %161, i32 56) %201 = fmul float %200, %129 %202 = fadd float %199, %201 %203 = call float @llvm.SI.load.const(<16 x i8> %161, i32 60) %204 = fmul float %203, %122 %205 = fadd float %202, %204 %206 = call float @llvm.SI.load.const(<16 x i8> %161, i32 64) %207 = fmul float %206, %108 %208 = call float @llvm.SI.load.const(<16 x i8> %161, i32 68) %209 = fmul float %208, %115 %210 = fadd float %207, %209 %211 = call float @llvm.SI.load.const(<16 x i8> %161, i32 72) %212 = fmul float %211, %129 %213 = fadd float %210, %212 %214 = call float @llvm.SI.load.const(<16 x i8> %161, i32 76) %215 = fmul float %214, %122 %216 = fadd float %213, %215 %217 = call float @llvm.SI.load.const(<16 x i8> %161, i32 80) %218 = fmul float %217, %108 %219 = call float @llvm.SI.load.const(<16 x i8> %161, i32 84) %220 = fmul float %219, %115 %221 = fadd float %218, %220 %222 = call float @llvm.SI.load.const(<16 x i8> %161, i32 88) %223 = fmul float %222, %129 %224 = fadd float %221, %223 %225 = call float @llvm.SI.load.const(<16 x i8> %161, i32 92) %226 = fmul float %225, %122 %227 = fadd float %224, %226 %228 = call float @llvm.SI.load.const(<16 x i8> %161, i32 96) %229 = fmul float %228, %108 %230 = call float @llvm.SI.load.const(<16 x i8> %161, i32 100) %231 = fmul float %230, %115 %232 = fadd float %229, %231 %233 = call float @llvm.SI.load.const(<16 x i8> %161, i32 104) %234 = fmul float %233, %129 %235 = fadd float %232, %234 %236 = call float @llvm.SI.load.const(<16 x i8> %161, i32 108) %237 = fmul float %236, %122 %238 = fadd float %235, %237 %239 = call float @llvm.SI.load.const(<16 x i8> %161, i32 112) %240 = fmul float %239, %108 %241 = call float @llvm.SI.load.const(<16 x i8> %161, i32 116) %242 = fmul float %241, %115 %243 = fadd float %240, %242 %244 = call float @llvm.SI.load.const(<16 x i8> %161, i32 120) %245 = fmul float %244, %129 %246 = fadd float %243, %245 %247 = call float @llvm.SI.load.const(<16 x i8> %161, i32 124) %248 = fmul float %247, %122 %249 = fadd float %246, %248 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %142, float %143, float %144, float %145) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %87, float %94, float %101, float %129) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %130, float %131, float %132, float %133) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %134, float %135, float %59, float %60) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %139, float %141, float %137, float %122) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %172, float %183, float %194, float %205) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %216, float %227, float %238, float %249) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x30 ; C00A0604 00000030 v_add_i32_e32 v4, vcc, s10, v0 ; 3208000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[10:13], v4, s[4:7], 0 idxen ; E00C2000 80010A04 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v4, s[16:19], 0 idxen ; E00C2000 80040004 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v4, s[20:23], 0 idxen ; E00C2000 80050604 s_waitcnt vmcnt(1) ; BF8C0771 buffer_load_format_xyzw v[2:5], v4, s[24:27], 0 idxen ; E00C2000 80060204 s_load_dwordx4 s[36:39], s[2:3], 0x0 ; C00A0901 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[36:39], 0x0 ; C0220012 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[36:39], 0x4 ; C02208D2 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[36:39], 0x8 ; C0220152 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[36:39], 0x80 ; C0220552 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[36:39], 0x84 ; C0220592 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[36:39], 0x88 ; C0220512 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[36:39], 0x8c ; C0220492 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[36:39], 0x90 ; C0220452 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[36:39], 0x94 ; C02204D2 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[36:39], 0x98 ; C02203D2 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[36:39], 0x9c ; C0220392 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[36:39], 0xa0 ; C0220212 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[36:39], 0xa4 ; C0220252 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[36:39], 0xa8 ; C02201D2 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[36:39], 0xac ; C0220192 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s13, s[36:39], 0xb0 ; C0220352 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[36:39], 0xb4 ; C0220412 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[36:39], 0xb8 ; C02202D2 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[36:39], 0xbc ; C0220292 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s40, s[36:39], 0x2fc ; C0220A12 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s33, s[36:39], 0x300 ; C0220852 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[36:39], 0x304 ; C0220892 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[36:39], 0x308 ; C0220812 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[36:39], 0x30c ; C0220792 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[36:39], 0x310 ; C0220752 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[36:39], 0x314 ; C02207D2 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[36:39], 0x318 ; C0220712 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[36:39], 0x31c ; C0220692 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s25, s[36:39], 0x320 ; C0220652 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[36:39], 0x324 ; C02206D2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[36:39], 0x328 ; C0220612 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[36:39], 0x32c ; C02205D2 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[36:39], 0x330 ; C0220052 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[36:39], 0x334 ; C0220112 00000334 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mov_b32_e32 v4, s35 ; 7E080223 v_mov_b32_e32 v5, s0 ; 7E0A0200 v_mad_f32 v8, s40, v5, v4 ; D1C10008 04120A28 v_mad_f32 v5, s40, v4, v5 ; D1C10005 04160828 s_and_b32 s12, 1, s12 ; 860C0C81 v_cmp_eq_i32_e64 s[36:37], 1, s12 ; D0C20024 00001881 v_mov_b32_e32 v13, v8 ; 7E1A0308 v_mov_b32_e32 v9, v8 ; 7E120308 s_and_saveexec_b64 s[36:37], s[36:37] ; BEA42024 s_xor_b64 s[36:37], exec, s[36:37] ; 88A4247E v_add_f32_e64 v9, 0, v8 clamp ; D1018009 00021080 v_add_f32_e64 v13, 0, v8 clamp ; D101800D 00021080 v_add_f32_e64 v8, 0, v8 clamp ; D1018008 00021080 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 s_or_b64 exec, exec, s[36:37] ; 87FE247E exp 15, 32, 0, 0, 0, v8, v9, v13, v5 ; C400020F 050D0908 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v5, v4, v10, s0 ; D1C10005 00021504 v_mad_f32 v8, v11, v4, s0 ; D1C10008 0002090B v_mad_f32 v9, v12, v4, s0 ; D1C10009 0002090C v_mad_f32 v10, s0, v10, v4 ; D1C1000A 04121400 v_mul_f32_e32 v11, s34, v8 ; 0A161022 v_mac_f32_e32 v11, s33, v5 ; 2C160A21 v_mac_f32_e32 v11, s32, v9 ; 2C161220 v_mac_f32_e32 v11, s30, v10 ; 2C16141E v_mul_f32_e32 v12, s31, v8 ; 0A18101F v_mac_f32_e32 v12, s29, v5 ; 2C180A1D v_mac_f32_e32 v12, s28, v9 ; 2C18121C v_mac_f32_e32 v12, s26, v10 ; 2C18141A v_mul_f32_e32 v8, s27, v8 ; 0A10101B v_mac_f32_e32 v8, s25, v5 ; 2C100A19 v_mac_f32_e32 v8, s24, v9 ; 2C101218 v_mac_f32_e32 v8, s23, v10 ; 2C101417 v_mul_f32_e32 v5, s22, v12 ; 0A0A1816 v_mac_f32_e32 v5, s21, v11 ; 2C0A1615 v_mac_f32_e32 v5, s20, v8 ; 2C0A1014 v_mac_f32_e32 v5, s18, v4 ; 2C0A0812 v_mul_f32_e32 v9, s19, v12 ; 0A121813 v_mac_f32_e32 v9, s17, v11 ; 2C121611 v_mac_f32_e32 v9, s15, v8 ; 2C12100F v_mac_f32_e32 v9, s14, v4 ; 2C12080E v_mul_f32_e32 v10, s16, v12 ; 0A141810 v_mac_f32_e32 v10, s13, v11 ; 2C14160D v_mac_f32_e32 v10, s11, v8 ; 2C14100B v_mac_f32_e32 v10, s10, v4 ; 2C14080A v_mul_f32_e32 v13, s9, v12 ; 0A1A1809 v_mac_f32_e32 v13, s8, v11 ; 2C1A1608 v_mac_f32_e32 v13, s7, v8 ; 2C1A1007 v_mac_f32_e32 v13, s6, v4 ; 2C1A0806 s_load_dwordx4 s[8:11], s[2:3], 0x100 ; C00A0201 00000100 v_add_f32_e32 v6, v6, v2 ; 020C0506 v_add_f32_e32 v7, v7, v3 ; 020E0707 v_add_f32_e32 v14, v3, v7 ; 021C0F03 v_add_f32_e32 v15, v2, v6 ; 021E0D02 v_add_f32_e32 v2, v2, v15 ; 02041F02 v_add_f32_e32 v3, v3, v14 ; 02061D03 v_mad_f32 v16, v13, s5, -v10 ; D1C10010 84280B0D v_mul_f32_e32 v17, v0, v4 ; 0A220900 v_mul_f32_e32 v4, v1, v4 ; 0A080901 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s2, s[8:11], 0x0 ; C0220084 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x4 ; C02200C4 00000004 v_mov_b32_e32 v18, 0 ; 7E240280 s_buffer_load_dword s5, s[8:11], 0x8 ; C0220144 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0xc ; C0220184 0000000C exp 15, 33, 0, 0, 0, v0, v1, v18, v18 ; C400021F 12120100 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v18, s0, v0 ; 0A240000 exp 15, 34, 0, 0, 0, v17, v4, v18, v18 ; C400022F 12120411 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v4, s1, v10, v5 ; D1C10004 04161401 v_mad_f32 v17, s4, v10, -v9 ; D1C10011 84261404 s_buffer_load_dword s0, s[8:11], 0x10 ; C0220004 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s3, v9 ; 0A241203 v_mac_f32_e32 v18, s2, v5 ; 2C240A02 v_mac_f32_e32 v18, s5, v13 ; 2C241A05 v_mac_f32_e32 v18, s6, v10 ; 2C241406 s_buffer_load_dword s1, s[8:11], 0x14 ; C0220044 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[8:11], 0x18 ; C0220084 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x1c ; C02200C4 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[8:11], 0x20 ; C0220104 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[8:11], 0x24 ; C0220144 00000024 exp 15, 35, 0, 0, 0, v11, v12, v8, v13 ; C400023F 0D080C0B s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0x28 ; C0220184 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[8:11], 0x2c ; C02201C4 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[8:11], 0x30 ; C0220304 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[8:11], 0x34 ; C0220344 00000034 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v8, s1, v9 ; 0A101201 s_buffer_load_dword s1, s[8:11], 0x38 ; C0220044 00000038 v_mac_f32_e32 v8, s0, v5 ; 2C100A00 v_mac_f32_e32 v8, s2, v13 ; 2C101A02 v_mac_f32_e32 v8, s3, v10 ; 2C101403 v_mul_f32_e32 v11, s5, v9 ; 0A161205 v_mac_f32_e32 v11, s4, v5 ; 2C160A04 v_mac_f32_e32 v11, s6, v13 ; 2C161A06 v_mac_f32_e32 v11, s7, v10 ; 2C161407 v_mul_f32_e32 v12, s13, v9 ; 0A18120D v_mac_f32_e32 v12, s12, v5 ; 2C180A0C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s1, v13 ; 2C181A01 s_buffer_load_dword s0, s[8:11], 0x3c ; C0220004 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[8:11], 0x40 ; C0220044 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[8:11], 0x44 ; C0220084 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x48 ; C02200C4 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[8:11], 0x4c ; C0220104 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s5, s[8:11], 0x50 ; C0220144 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0x54 ; C0220184 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[8:11], 0x58 ; C02201C4 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[8:11], 0x5c ; C0220304 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[8:11], 0x60 ; C0220344 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[8:11], 0x64 ; C0220384 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[8:11], 0x68 ; C02203C4 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[8:11], 0x6c ; C0220404 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[8:11], 0x70 ; C0220444 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[8:11], 0x74 ; C0220484 00000074 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s0, v10 ; 2C181400 exp 15, 36, 0, 0, 0, v6, v7, v14, v15 ; C400024F 0F0E0706 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v6, s2, v9 ; 0A0C1202 v_mac_f32_e32 v6, s1, v5 ; 2C0C0A01 v_mul_f32_e32 v7, s6, v9 ; 0A0E1206 v_mac_f32_e32 v7, s5, v5 ; 2C0E0A05 v_mul_f32_e32 v14, s14, v9 ; 0A1C120E v_mac_f32_e32 v14, s13, v5 ; 2C1C0A0D s_buffer_load_dword s0, s[8:11], 0x78 ; C0220004 00000078 v_mul_f32_e32 v9, s18, v9 ; 0A121212 s_buffer_load_dword s1, s[8:11], 0x7c ; C0220044 0000007C exp 15, 37, 0, 0, 0, v2, v3, v0, v1 ; C400025F 01000302 exp 15, 12, 0, 0, 0, v4, v17, v16, v10 ; C40000CF 0A101104 exp 15, 13, 0, 0, 0, v18, v8, v11, v12 ; C40000DF 0C0B0812 v_mac_f32_e32 v9, s17, v5 ; 2C120A11 v_mac_f32_e32 v6, s3, v13 ; 2C0C1A03 v_mac_f32_e32 v7, s7, v13 ; 2C0E1A07 v_mac_f32_e32 v14, s15, v13 ; 2C1C1A0F s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v9, s0, v13 ; 2C121A00 v_mac_f32_e32 v6, s4, v10 ; 2C0C1404 v_mac_f32_e32 v7, s12, v10 ; 2C0E140C v_mac_f32_e32 v14, s16, v10 ; 2C1C1410 v_mac_f32_e32 v9, s1, v10 ; 2C121401 exp 15, 14, 0, 1, 0, v6, v7, v14, v9 ; C40008EF 090E0706 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 20 Code Size: 1416 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL IN[2], GENERIC[1], PERSPECTIVE DCL IN[3], GENERIC[2], PERSPECTIVE DCL IN[4], GENERIC[3], PERSPECTIVE, CENTROID DCL IN[5], GENERIC[4], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..17], LOCAL IMM[0] FLT32 { 0.5774, 0.0000, 0.3333, 1.0000} IMM[1] FLT32 { 0.2125, 0.7154, 0.0721, 2.0000} IMM[2] FLT32 { -0.5000, 0.0000, -1.0000, -2.0000} IMM[3] FLT32 { 0.0005, 0.0000, -0.0005, 0.0625} IMM[4] FLT32 { 0.1250, 0.2500, 0.5000, 0.0000} 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[2].xyyy 3: TEX TEMP[2].xyz, TEMP[1], SAMP[2], 2D 4: MOV TEMP[3].xy, IN[4].xyyy 5: TEX TEMP[3], TEMP[3], SAMP[1], 2D 6: MOV TEMP[4], TEMP[3] 7: MOV TEMP[5].xy, IN[4].wzzz 8: TEX TEMP[5], TEMP[5], SAMP[1], 2D 9: MOV TEMP[6], TEMP[5] 10: MOV TEMP[7].xy, IN[5].xyyy 11: TEX TEMP[7], TEMP[7], SAMP[1], 2D 12: MOV TEMP[8], TEMP[7] 13: MUL TEMP[1].xyz, TEMP[0].xyzz, IN[0].xyzz 14: MUL TEMP[9].x, TEMP[0].wwww, IN[0].wwww 15: MOV TEMP[9].w, TEMP[9].xxxx 16: MUL TEMP[10].xyz, TEMP[2].yyyy, TEMP[5].xyzz 17: MAD TEMP[11].xyz, TEMP[2].xxxx, TEMP[3].xyzz, TEMP[10].xyzz 18: MAD TEMP[0].xyz, TEMP[2].zzzz, TEMP[7].xyzz, TEMP[11].xyzz 19: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[12].xyzz 20: MUL TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx 21: FSLT TEMP[2].x, -TEMP[3].wwww, IMM[0].yyyy 22: AND TEMP[2].x, CONST[90].xxxx, TEMP[2].xxxx 23: UIF TEMP[2].xxxx :0 24: ADD TEMP[4].xyz, TEMP[3].xyzz, TEMP[5].xyzz 25: ADD TEMP[4].xyz, TEMP[7].xyzz, TEMP[4].xyzz 26: DP3 TEMP[2].x, TEMP[4].xyzz, IMM[1].xyzz 27: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz 28: RCP TEMP[2].x, TEMP[2].xxxx 29: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].wwww 30: MAD TEMP[4], IN[3].xyzx, IMM[0].wwwy, IMM[0].yyyw 31: DP4 TEMP[6].x, TEMP[4], CONST[69] 32: DP4 TEMP[3].x, TEMP[4], CONST[70] 33: MOV TEMP[6].y, TEMP[3].xxxx 34: MOV_SAT TEMP[5].xy, TEMP[6].xyyy 35: ADD TEMP[8].xy, -TEMP[6].xyyy, TEMP[5].xyyy 36: DP2 TEMP[5].x, TEMP[8].xyyy, IMM[0].wwww 37: DP4 TEMP[8].x, TEMP[4], CONST[73] 38: DP4 TEMP[7].x, TEMP[4], CONST[74] 39: MOV TEMP[8].y, TEMP[7].xxxx 40: MOV_SAT TEMP[11].xy, TEMP[8].xyyy 41: ADD TEMP[10].xy, -TEMP[8].xyyy, TEMP[11].xyyy 42: DP2 TEMP[11].x, TEMP[10].xyyy, IMM[0].wwww 43: MOV TEMP[6].w, TEMP[11].xxxx 44: DP4 TEMP[10].x, TEMP[4], CONST[77] 45: DP4 TEMP[12].x, TEMP[4], CONST[78] 46: MOV TEMP[8].zw, IMM[0].yywy 47: MOV TEMP[13].w, TEMP[8] 48: ABS TEMP[14].x, TEMP[11].xxxx 49: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 50: UIF TEMP[14].xxxx :0 51: MOV TEMP[14].x, TEMP[8].xxxx 52: ELSE :0 53: MOV TEMP[14].x, TEMP[10].xxxx 54: ENDIF 55: MOV TEMP[13].x, TEMP[14].xxxx 56: ABS TEMP[14].x, TEMP[11].xxxx 57: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 58: UIF TEMP[14].xxxx :0 59: MOV TEMP[7].x, TEMP[7].xxxx 60: ELSE :0 61: MOV TEMP[7].x, TEMP[12].xxxx 62: ENDIF 63: MOV TEMP[13].y, TEMP[7].xxxx 64: ABS TEMP[7].x, TEMP[11].xxxx 65: FSGE TEMP[7].x, -TEMP[7].xxxx, IMM[0].yyyy 66: UIF TEMP[7].xxxx :0 67: MOV TEMP[7].x, IMM[0].wwww 68: ELSE :0 69: MOV TEMP[7].x, IMM[1].wwww 70: ENDIF 71: MOV TEMP[13].z, TEMP[7].xxxx 72: MOV TEMP[8], TEMP[13] 73: MOV TEMP[6].z, IMM[0].yyyy 74: MOV TEMP[13].w, TEMP[6] 75: ABS TEMP[7].x, TEMP[5].xxxx 76: FSGE TEMP[7].x, -TEMP[7].xxxx, IMM[0].yyyy 77: UIF TEMP[7].xxxx :0 78: MOV TEMP[7].x, TEMP[6].xxxx 79: ELSE :0 80: MOV TEMP[7].x, TEMP[8].xxxx 81: ENDIF 82: MOV TEMP[13].x, TEMP[7].xxxx 83: ABS TEMP[7].x, TEMP[5].xxxx 84: FSGE TEMP[7].x, -TEMP[7].xxxx, IMM[0].yyyy 85: UIF TEMP[7].xxxx :0 86: MOV TEMP[3].x, TEMP[3].xxxx 87: ELSE :0 88: MOV TEMP[3].x, TEMP[8].yyyy 89: ENDIF 90: MOV TEMP[13].y, TEMP[3].xxxx 91: ABS TEMP[3].x, TEMP[5].xxxx 92: FSGE TEMP[3].x, -TEMP[3].xxxx, IMM[0].yyyy 93: UIF TEMP[3].xxxx :0 94: MOV TEMP[3].x, IMM[0].yyyy 95: ELSE :0 96: MOV TEMP[3].x, TEMP[8].zzzz 97: ENDIF 98: MOV TEMP[13].z, TEMP[3].xxxx 99: MOV TEMP[6].z, TEMP[13].wwzw 100: DP4 TEMP[5].x, TEMP[4], CONST[71] 101: MOV TEMP[8].z, TEMP[5].xxxx 102: ADD TEMP[10].xy, TEMP[13].xyyy, IMM[2].xxxx 103: ABS TEMP[7].xy, TEMP[10].xyyy 104: ADD TEMP[10].xy, TEMP[7].xyyy, -CONST[67].zzzz 105: MUL TEMP[10].xy, TEMP[10].xyyy, CONST[67].wwww 106: MOV_SAT TEMP[7].xy, TEMP[10].xyyy 107: ADD TEMP[10].xy, -TEMP[7].xyyy, IMM[0].wwww 108: MUL TEMP[7].x, TEMP[10].yyyy, TEMP[10].xxxx 109: MOV_SAT TEMP[11].xy, TEMP[13].xyyy 110: ADD TEMP[10].xyz, TEMP[3].xxxx, IMM[2].yzww 111: MOV TEMP[3].y, IMM[0].yyyy 112: ABS TEMP[14].x, TEMP[10].xxxx 113: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 114: UIF TEMP[14].xxxx :0 115: MOV TEMP[14].x, CONST[85].zzzz 116: ELSE :0 117: MOV TEMP[14].x, IMM[0].yyyy 118: ENDIF 119: ABS TEMP[15].x, TEMP[10].xxxx 120: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 121: UIF TEMP[15].xxxx :0 122: MOV TEMP[15].x, CONST[85].wwww 123: ELSE :0 124: MOV TEMP[15].x, IMM[0].yyyy 125: ENDIF 126: MOV TEMP[13].y, TEMP[15].xxxx 127: ABS TEMP[15].x, TEMP[10].xxxx 128: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 129: UIF TEMP[15].xxxx :0 130: MOV TEMP[15].x, CONST[85].xxxx 131: ELSE :0 132: MOV TEMP[15].x, IMM[0].yyyy 133: ENDIF 134: MOV TEMP[13].z, TEMP[15].xxxx 135: ABS TEMP[15].x, TEMP[10].xxxx 136: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 137: UIF TEMP[15].xxxx :0 138: MOV TEMP[15].x, CONST[85].yyyy 139: ELSE :0 140: MOV TEMP[15].x, IMM[0].yyyy 141: ENDIF 142: MOV TEMP[13].w, TEMP[15].xxxx 143: ABS TEMP[15].x, TEMP[10].yyyy 144: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 145: UIF TEMP[15].xxxx :0 146: MOV TEMP[15].x, CONST[86].zzzz 147: ELSE :0 148: MOV TEMP[15].x, TEMP[14].xxxx 149: ENDIF 150: MOV TEMP[13].x, TEMP[15].xxxx 151: ABS TEMP[14].x, TEMP[10].yyyy 152: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 153: UIF TEMP[14].xxxx :0 154: MOV TEMP[14].x, CONST[86].wwww 155: ELSE :0 156: MOV TEMP[14].x, TEMP[13].yyyy 157: ENDIF 158: MOV TEMP[13].y, TEMP[14].xxxx 159: ABS TEMP[14].x, TEMP[10].yyyy 160: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 161: UIF TEMP[14].xxxx :0 162: MOV TEMP[14].x, CONST[86].xxxx 163: ELSE :0 164: MOV TEMP[14].x, TEMP[13].zzzz 165: ENDIF 166: MOV TEMP[13].z, TEMP[14].xxxx 167: ABS TEMP[14].x, TEMP[10].yyyy 168: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 169: UIF TEMP[14].xxxx :0 170: MOV TEMP[14].x, CONST[86].yyyy 171: ELSE :0 172: MOV TEMP[14].x, TEMP[13].wwww 173: ENDIF 174: MOV TEMP[13].w, TEMP[14].xxxx 175: MOV TEMP[12], TEMP[13] 176: ABS TEMP[14].x, TEMP[10].zzzz 177: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 178: UIF TEMP[14].xxxx :0 179: MOV TEMP[14].x, CONST[87].zzzz 180: ELSE :0 181: MOV TEMP[14].x, TEMP[12].xxxx 182: ENDIF 183: MOV TEMP[13].x, TEMP[14].xxxx 184: ABS TEMP[14].x, TEMP[10].zzzz 185: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 186: UIF TEMP[14].xxxx :0 187: MOV TEMP[14].x, CONST[87].wwww 188: ELSE :0 189: MOV TEMP[14].x, TEMP[12].yyyy 190: ENDIF 191: MOV TEMP[13].y, TEMP[14].xxxx 192: ABS TEMP[14].x, TEMP[10].zzzz 193: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 194: UIF TEMP[14].xxxx :0 195: MOV TEMP[14].x, CONST[87].xxxx 196: ELSE :0 197: MOV TEMP[14].x, TEMP[12].zzzz 198: ENDIF 199: MOV TEMP[13].z, TEMP[14].xxxx 200: ABS TEMP[14].x, TEMP[10].zzzz 201: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].yyyy 202: UIF TEMP[14].xxxx :0 203: MOV TEMP[14].x, CONST[87].yyyy 204: ELSE :0 205: MOV TEMP[14].x, TEMP[12].wwww 206: ENDIF 207: MOV TEMP[13].w, TEMP[14].xxxx 208: MAD TEMP[8].xy, TEMP[11].xyyy, TEMP[13].xyyy, TEMP[13].zwww 209: ADD TEMP[10], TEMP[8], IMM[3].xxyy 210: TXL TEMP[11].x, TEMP[10], SAMP[3], SHADOW2D 211: MOV TEMP[10].x, TEMP[11].xxxx 212: ADD TEMP[12], TEMP[8], IMM[3].zxyy 213: ADD TEMP[11], TEMP[8], IMM[3].xzyy 214: ADD TEMP[14], TEMP[8], IMM[3].zzyy 215: TXL TEMP[15].x, TEMP[12], SAMP[3], SHADOW2D 216: MOV TEMP[10].y, TEMP[15].xxxx 217: TXL TEMP[15].x, TEMP[11], SAMP[3], SHADOW2D 218: MOV TEMP[10].z, TEMP[15].xxxx 219: TXL TEMP[15].x, TEMP[14], SAMP[3], SHADOW2D 220: MOV TEMP[10].w, TEMP[15].xxxx 221: DP4 TEMP[15].x, TEMP[10], IMM[3].wwww 222: ADD TEMP[10], TEMP[8], IMM[3].xyyy 223: TXL TEMP[16].x, TEMP[10], SAMP[3], SHADOW2D 224: MOV TEMP[10].x, TEMP[16].xxxx 225: ADD TEMP[12], TEMP[8], IMM[3].zyyy 226: TXL TEMP[16], TEMP[12], SAMP[3], SHADOW2D 227: MOV TEMP[12], TEMP[16] 228: ADD TEMP[11], TEMP[8], IMM[3].yzyy 229: TXL TEMP[17], TEMP[11], SAMP[3], SHADOW2D 230: MOV TEMP[11], TEMP[17] 231: ADD TEMP[14], TEMP[8], IMM[3].yxyy 232: TXL TEMP[14].x, TEMP[14], SAMP[3], SHADOW2D 233: MOV TEMP[10].y, TEMP[16].xxxx 234: MOV TEMP[10].z, TEMP[17].xxxx 235: MOV TEMP[10].w, TEMP[14].xxxx 236: DP4 TEMP[14].x, TEMP[10], IMM[4].xxxx 237: MOV TEMP[16].xy, TEMP[8].xyyy 238: MOV TEMP[16].z, TEMP[5].xxxx 239: MOV TEMP[16].w, TEMP[8].wwww 240: TXL TEMP[16], TEMP[16], SAMP[3], SHADOW2D 241: MOV TEMP[10], TEMP[16] 242: ADD TEMP[6].x, TEMP[14].xxxx, TEMP[15].xxxx 243: MAD TEMP[6].x, TEMP[16].xxxx, IMM[4].yyyy, TEMP[6].xxxx 244: FSLT TEMP[14].x, TEMP[7].xxxx, IMM[0].wwww 245: UIF TEMP[14].xxxx :0 246: ADD TEMP[14].xyz, TEMP[6].zzzz, IMM[2].yzww 247: ABS TEMP[15].x, TEMP[14].xxxx 248: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 249: UIF TEMP[15].xxxx :0 250: MOV TEMP[15].x, CONST[73].xxxx 251: ELSE :0 252: MOV TEMP[15].x, IMM[0].yyyy 253: ENDIF 254: MOV TEMP[13].x, TEMP[15].xxxx 255: ABS TEMP[15].x, TEMP[14].xxxx 256: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 257: UIF TEMP[15].xxxx :0 258: MOV TEMP[15].x, CONST[73].yyyy 259: ELSE :0 260: MOV TEMP[15].x, IMM[0].yyyy 261: ENDIF 262: MOV TEMP[13].y, TEMP[15].xxxx 263: ABS TEMP[15].x, TEMP[14].xxxx 264: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 265: UIF TEMP[15].xxxx :0 266: MOV TEMP[15].x, CONST[73].zzzz 267: ELSE :0 268: MOV TEMP[15].x, IMM[0].yyyy 269: ENDIF 270: MOV TEMP[13].z, TEMP[15].xxxx 271: ABS TEMP[15].x, TEMP[14].xxxx 272: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 273: UIF TEMP[15].xxxx :0 274: MOV TEMP[15].x, CONST[73].wwww 275: ELSE :0 276: MOV TEMP[15].x, IMM[0].yyyy 277: ENDIF 278: MOV TEMP[13].w, TEMP[15].xxxx 279: MOV TEMP[10], TEMP[13] 280: ABS TEMP[15].x, TEMP[14].xxxx 281: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 282: UIF TEMP[15].xxxx :0 283: MOV TEMP[15].x, CONST[74].xxxx 284: ELSE :0 285: MOV TEMP[15].x, IMM[0].yyyy 286: ENDIF 287: MOV TEMP[13].x, TEMP[15].xxxx 288: ABS TEMP[15].x, TEMP[14].xxxx 289: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 290: UIF TEMP[15].xxxx :0 291: MOV TEMP[15].x, CONST[74].yyyy 292: ELSE :0 293: MOV TEMP[15].x, IMM[0].yyyy 294: ENDIF 295: MOV TEMP[13].y, TEMP[15].xxxx 296: ABS TEMP[15].x, TEMP[14].xxxx 297: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 298: UIF TEMP[15].xxxx :0 299: MOV TEMP[15].x, CONST[74].zzzz 300: ELSE :0 301: MOV TEMP[15].x, IMM[0].yyyy 302: ENDIF 303: MOV TEMP[13].z, TEMP[15].xxxx 304: ABS TEMP[15].x, TEMP[14].xxxx 305: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 306: UIF TEMP[15].xxxx :0 307: MOV TEMP[15].x, CONST[74].wwww 308: ELSE :0 309: MOV TEMP[15].x, IMM[0].yyyy 310: ENDIF 311: MOV TEMP[13].w, TEMP[15].xxxx 312: MOV TEMP[12], TEMP[13] 313: ABS TEMP[15].x, TEMP[14].yyyy 314: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 315: UIF TEMP[15].xxxx :0 316: MOV TEMP[15].x, CONST[77].xxxx 317: ELSE :0 318: MOV TEMP[15].x, TEMP[10].xxxx 319: ENDIF 320: MOV TEMP[13].x, TEMP[15].xxxx 321: ABS TEMP[15].x, TEMP[14].yyyy 322: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 323: UIF TEMP[15].xxxx :0 324: MOV TEMP[15].x, CONST[77].yyyy 325: ELSE :0 326: MOV TEMP[15].x, TEMP[10].yyyy 327: ENDIF 328: MOV TEMP[13].y, TEMP[15].xxxx 329: ABS TEMP[15].x, TEMP[14].yyyy 330: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 331: UIF TEMP[15].xxxx :0 332: MOV TEMP[15].x, CONST[77].zzzz 333: ELSE :0 334: MOV TEMP[15].x, TEMP[10].zzzz 335: ENDIF 336: MOV TEMP[13].z, TEMP[15].xxxx 337: ABS TEMP[15].x, TEMP[14].yyyy 338: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 339: UIF TEMP[15].xxxx :0 340: MOV TEMP[15].x, CONST[77].wwww 341: ELSE :0 342: MOV TEMP[15].x, TEMP[10].wwww 343: ENDIF 344: MOV TEMP[13].w, TEMP[15].xxxx 345: MOV TEMP[10], TEMP[13] 346: ABS TEMP[15].x, TEMP[14].yyyy 347: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 348: UIF TEMP[15].xxxx :0 349: MOV TEMP[15].x, CONST[78].xxxx 350: ELSE :0 351: MOV TEMP[15].x, TEMP[12].xxxx 352: ENDIF 353: MOV TEMP[13].x, TEMP[15].xxxx 354: ABS TEMP[15].x, TEMP[14].yyyy 355: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 356: UIF TEMP[15].xxxx :0 357: MOV TEMP[15].x, CONST[78].yyyy 358: ELSE :0 359: MOV TEMP[15].x, TEMP[12].yyyy 360: ENDIF 361: MOV TEMP[13].y, TEMP[15].xxxx 362: ABS TEMP[15].x, TEMP[14].yyyy 363: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 364: UIF TEMP[15].xxxx :0 365: MOV TEMP[15].x, CONST[78].zzzz 366: ELSE :0 367: MOV TEMP[15].x, TEMP[12].zzzz 368: ENDIF 369: MOV TEMP[13].z, TEMP[15].xxxx 370: ABS TEMP[15].x, TEMP[14].yyyy 371: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 372: UIF TEMP[15].xxxx :0 373: MOV TEMP[15].x, CONST[78].wwww 374: ELSE :0 375: MOV TEMP[15].x, TEMP[12].wwww 376: ENDIF 377: MOV TEMP[13].w, TEMP[15].xxxx 378: MOV TEMP[12], TEMP[13] 379: ABS TEMP[15].x, TEMP[14].zzzz 380: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 381: UIF TEMP[15].xxxx :0 382: MOV TEMP[15].x, CONST[81].xxxx 383: ELSE :0 384: MOV TEMP[15].x, TEMP[10].xxxx 385: ENDIF 386: MOV TEMP[13].x, TEMP[15].xxxx 387: ABS TEMP[15].x, TEMP[14].zzzz 388: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 389: UIF TEMP[15].xxxx :0 390: MOV TEMP[15].x, CONST[81].yyyy 391: ELSE :0 392: MOV TEMP[15].x, TEMP[10].yyyy 393: ENDIF 394: MOV TEMP[13].y, TEMP[15].xxxx 395: ABS TEMP[15].x, TEMP[14].zzzz 396: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 397: UIF TEMP[15].xxxx :0 398: MOV TEMP[15].x, CONST[81].zzzz 399: ELSE :0 400: MOV TEMP[15].x, TEMP[10].zzzz 401: ENDIF 402: MOV TEMP[13].z, TEMP[15].xxxx 403: ABS TEMP[15].x, TEMP[14].zzzz 404: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 405: UIF TEMP[15].xxxx :0 406: MOV TEMP[15].x, CONST[81].wwww 407: ELSE :0 408: MOV TEMP[15].x, TEMP[10].wwww 409: ENDIF 410: MOV TEMP[13].w, TEMP[15].xxxx 411: MOV TEMP[10], TEMP[13] 412: ABS TEMP[15].x, TEMP[14].zzzz 413: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 414: UIF TEMP[15].xxxx :0 415: MOV TEMP[15].x, CONST[82].xxxx 416: ELSE :0 417: MOV TEMP[15].x, TEMP[12].xxxx 418: ENDIF 419: MOV TEMP[13].x, TEMP[15].xxxx 420: ABS TEMP[15].x, TEMP[14].zzzz 421: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 422: UIF TEMP[15].xxxx :0 423: MOV TEMP[15].x, CONST[82].yyyy 424: ELSE :0 425: MOV TEMP[15].x, TEMP[12].yyyy 426: ENDIF 427: MOV TEMP[13].y, TEMP[15].xxxx 428: ABS TEMP[15].x, TEMP[14].zzzz 429: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 430: UIF TEMP[15].xxxx :0 431: MOV TEMP[15].x, CONST[82].zzzz 432: ELSE :0 433: MOV TEMP[15].x, TEMP[12].zzzz 434: ENDIF 435: MOV TEMP[13].z, TEMP[15].xxxx 436: ABS TEMP[15].x, TEMP[14].zzzz 437: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 438: UIF TEMP[15].xxxx :0 439: MOV TEMP[15].x, CONST[82].wwww 440: ELSE :0 441: MOV TEMP[15].x, TEMP[12].wwww 442: ENDIF 443: MOV TEMP[13].w, TEMP[15].xxxx 444: DP4 TEMP[10].x, TEMP[4], TEMP[10] 445: MOV_SAT TEMP[10].x, TEMP[10].xxxx 446: DP4 TEMP[15].x, TEMP[4], TEMP[13] 447: MOV_SAT TEMP[15].x, TEMP[15].xxxx 448: MOV TEMP[10].y, TEMP[15].xxxx 449: ABS TEMP[15].x, TEMP[14].xxxx 450: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 451: UIF TEMP[15].xxxx :0 452: MOV TEMP[15].x, CONST[86].zzzz 453: ELSE :0 454: MOV TEMP[15].x, IMM[0].yyyy 455: ENDIF 456: ABS TEMP[16].x, TEMP[14].xxxx 457: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 458: UIF TEMP[16].xxxx :0 459: MOV TEMP[16].x, CONST[86].wwww 460: ELSE :0 461: MOV TEMP[16].x, IMM[0].yyyy 462: ENDIF 463: MOV TEMP[13].y, TEMP[16].xxxx 464: ABS TEMP[16].x, TEMP[14].xxxx 465: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 466: UIF TEMP[16].xxxx :0 467: MOV TEMP[16].x, CONST[86].xxxx 468: ELSE :0 469: MOV TEMP[16].x, IMM[0].yyyy 470: ENDIF 471: MOV TEMP[13].z, TEMP[16].xxxx 472: ABS TEMP[16].x, TEMP[14].xxxx 473: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 474: UIF TEMP[16].xxxx :0 475: MOV TEMP[16].x, CONST[86].yyyy 476: ELSE :0 477: MOV TEMP[16].x, IMM[0].yyyy 478: ENDIF 479: MOV TEMP[13].w, TEMP[16].xxxx 480: ABS TEMP[16].x, TEMP[14].yyyy 481: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].yyyy 482: UIF TEMP[16].xxxx :0 483: MOV TEMP[16].x, CONST[87].zzzz 484: ELSE :0 485: MOV TEMP[16].x, TEMP[15].xxxx 486: ENDIF 487: ABS TEMP[15].x, TEMP[14].yyyy 488: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 489: UIF TEMP[15].xxxx :0 490: MOV TEMP[15].x, CONST[87].wwww 491: ELSE :0 492: MOV TEMP[15].x, TEMP[13].yyyy 493: ENDIF 494: MOV TEMP[13].y, TEMP[15].xxxx 495: ABS TEMP[15].x, TEMP[14].yyyy 496: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 497: UIF TEMP[15].xxxx :0 498: MOV TEMP[15].x, CONST[87].xxxx 499: ELSE :0 500: MOV TEMP[15].x, TEMP[13].zzzz 501: ENDIF 502: MOV TEMP[13].z, TEMP[15].xxxx 503: ABS TEMP[15].x, TEMP[14].yyyy 504: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 505: UIF TEMP[15].xxxx :0 506: MOV TEMP[15].x, CONST[87].yyyy 507: ELSE :0 508: MOV TEMP[15].x, TEMP[13].wwww 509: ENDIF 510: MOV TEMP[13].w, TEMP[15].xxxx 511: ABS TEMP[15].x, TEMP[14].zzzz 512: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 513: UIF TEMP[15].xxxx :0 514: MOV TEMP[15].x, CONST[88].zzzz 515: ELSE :0 516: MOV TEMP[15].x, TEMP[16].xxxx 517: ENDIF 518: MOV TEMP[13].x, TEMP[15].xxxx 519: ABS TEMP[15].x, TEMP[14].zzzz 520: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 521: UIF TEMP[15].xxxx :0 522: MOV TEMP[15].x, CONST[88].wwww 523: ELSE :0 524: MOV TEMP[15].x, TEMP[13].yyyy 525: ENDIF 526: MOV TEMP[13].y, TEMP[15].xxxx 527: ABS TEMP[15].x, TEMP[14].zzzz 528: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 529: UIF TEMP[15].xxxx :0 530: MOV TEMP[15].x, CONST[88].xxxx 531: ELSE :0 532: MOV TEMP[15].x, TEMP[13].zzzz 533: ENDIF 534: MOV TEMP[13].z, TEMP[15].xxxx 535: ABS TEMP[15].x, TEMP[14].zzzz 536: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[0].yyyy 537: UIF TEMP[15].xxxx :0 538: MOV TEMP[15].x, CONST[88].yyyy 539: ELSE :0 540: MOV TEMP[15].x, TEMP[13].wwww 541: ENDIF 542: MOV TEMP[13].w, TEMP[15].xxxx 543: MAD TEMP[8].xy, TEMP[10].xyyy, TEMP[13].xyyy, TEMP[13].zwww 544: ADD TEMP[4], TEMP[8], IMM[3].xxyy 545: TXL TEMP[13].x, TEMP[4], SAMP[3], SHADOW2D 546: MOV TEMP[4].x, TEMP[13].xxxx 547: ADD TEMP[10], TEMP[8], IMM[3].zxyy 548: ADD TEMP[3], TEMP[8], IMM[3].xzyy 549: ADD TEMP[12], TEMP[8], IMM[3].zzyy 550: TXL TEMP[13].x, TEMP[10], SAMP[3], SHADOW2D 551: MOV TEMP[4].y, TEMP[13].xxxx 552: TXL TEMP[13].x, TEMP[3], SAMP[3], SHADOW2D 553: MOV TEMP[4].z, TEMP[13].xxxx 554: TXL TEMP[13].x, TEMP[12], SAMP[3], SHADOW2D 555: MOV TEMP[4].w, TEMP[13].xxxx 556: DP4 TEMP[13].x, TEMP[4], IMM[3].wwww 557: ADD TEMP[10], TEMP[8], IMM[3].xyyy 558: TXL TEMP[15].x, TEMP[10], SAMP[3], SHADOW2D 559: MOV TEMP[10].x, TEMP[15].xxxx 560: ADD TEMP[3], TEMP[8], IMM[3].zyyy 561: TXL TEMP[3].x, TEMP[3], SAMP[3], SHADOW2D 562: ADD TEMP[12], TEMP[8], IMM[3].yzyy 563: TXL TEMP[12].x, TEMP[12], SAMP[3], SHADOW2D 564: ADD TEMP[11], TEMP[8], IMM[3].yxyy 565: TXL TEMP[11].x, TEMP[11], SAMP[3], SHADOW2D 566: MOV TEMP[10].y, TEMP[3].xxxx 567: MOV TEMP[10].z, TEMP[12].xxxx 568: MOV TEMP[10].w, TEMP[11].xxxx 569: DP4 TEMP[3].x, TEMP[10], IMM[4].xxxx 570: MOV TEMP[10].xy, TEMP[8].xyyy 571: MOV TEMP[10].z, TEMP[5].xxxx 572: MOV TEMP[10].w, TEMP[8].wwww 573: TXL TEMP[5].x, TEMP[10], SAMP[3], SHADOW2D 574: ADD TEMP[4].x, TEMP[3].xxxx, TEMP[13].xxxx 575: MAD TEMP[4].x, TEMP[5].xxxx, IMM[4].yyyy, TEMP[4].xxxx 576: FSGE TEMP[3].x, TEMP[14].zzzz, IMM[0].yyyy 577: UIF TEMP[3].xxxx :0 578: MOV TEMP[3].x, IMM[0].wwww 579: ELSE :0 580: MOV TEMP[3].x, TEMP[4].xxxx 581: ENDIF 582: LRP TEMP[8].x, TEMP[7].xxxx, TEMP[6].xxxx, TEMP[3].xxxx 583: MOV TEMP[6].x, TEMP[8].xxxx 584: ENDIF 585: ADD TEMP[4].xyz, -CONST[89].xyzz, IN[3].xyzz 586: DP3 TEMP[3].x, TEMP[4].xyzz, TEMP[4].xyzz 587: MAD TEMP[3].x, TEMP[3].xxxx, CONST[68].yyyy, CONST[68].xxxx 588: MOV_SAT TEMP[3].x, TEMP[3].xxxx 589: LRP TEMP[4].x, TEMP[3].xxxx, IMM[0].wwww, TEMP[6].xxxx 590: ADD TEMP[3].x, -TEMP[4].xxxx, IMM[0].wwww 591: MAD TEMP[2].x, TEMP[2].xxxx, -TEMP[3].xxxx, IMM[0].wwww 592: MUL TEMP[4].xyz, TEMP[2].xxxx, TEMP[0].zyxx 593: MAD TEMP[2].x, TEMP[2].xxxx, IMM[4].zzzz, IMM[4].zzzz 594: LRP TEMP[0].xyz, TEMP[2].xxxx, TEMP[4].zyxx, TEMP[4].xyzz 595: ENDIF 596: ADD TEMP[0].xyz, TEMP[0].xyzz, CONST[31].xyzz 597: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xyzz 598: ADD TEMP[0].xyz, CONST[10].xyzz, -IN[3].xyzz 599: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[0].xyzz 600: SQRT TEMP[0].x, TEMP[0].xxxx 601: MAD TEMP[0].x, TEMP[0].xxxx, CONST[11].wwww, CONST[11].xxxx 602: MOV_SAT TEMP[0].x, TEMP[0].xxxx 603: MIN TEMP[0].x, TEMP[0].xxxx, CONST[11].zzzz 604: MUL TEMP[2].xyz, TEMP[1].xyzz, CONST[30].xxxx 605: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx 606: MAD TEMP[1].xyz, TEMP[1].xyzz, -CONST[30].xxxx, CONST[29].xyzz 607: MAD TEMP[9].xyz, TEMP[0].xxxx, TEMP[1].xyzz, TEMP[2].xyzz 608: MOV OUT[0], TEMP[9] 609: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %85 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %86 = load <8 x i32>, <8 x i32> addrspace(2)* %85, align 32, !tbaa !0 %87 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %88 = load <4 x i32>, <4 x i32> addrspace(2)* %87, align 16, !tbaa !0 %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = and i32 %5, 1 %102 = icmp ne i32 %101, 0 %103 = select i1 %102, <2 x i32> %7, <2 x i32> %8 %104 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %103) %105 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %103) %106 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %103) %107 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %103) %108 = and i32 %5, 1 %109 = icmp ne i32 %108, 0 %110 = select i1 %109, <2 x i32> %7, <2 x i32> %8 %111 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %110) %112 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %110) %113 = and i32 %5, 1 %114 = icmp ne i32 %113, 0 %115 = select i1 %114, <2 x i32> %7, <2 x i32> %8 %116 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %115) %117 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %115) %118 = and i32 %5, 1 %119 = icmp ne i32 %118, 0 %120 = select i1 %119, <2 x i32> %7, <2 x i32> %8 %121 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %120) %122 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %120) %123 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %120) %124 = and i32 %5, 1 %125 = icmp ne i32 %124, 0 %126 = select i1 %125, <2 x i32> %7, <2 x i32> %9 %127 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %126) %128 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %126) %129 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %126) %130 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %6, <2 x i32> %126) %131 = and i32 %5, 1 %132 = icmp ne i32 %131, 0 %133 = select i1 %132, <2 x i32> %7, <2 x i32> %9 %134 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %6, <2 x i32> %133) %135 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %6, <2 x i32> %133) %136 = bitcast float %111 to i32 %137 = bitcast float %112 to i32 %138 = insertelement <2 x i32> undef, i32 %136, i32 0 %139 = insertelement <2 x i32> %138, i32 %137, i32 1 %140 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %139, <8 x i32> %86, <4 x i32> %88, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = bitcast float %116 to i32 %146 = bitcast float %117 to i32 %147 = insertelement <2 x i32> undef, i32 %145, i32 0 %148 = insertelement <2 x i32> %147, i32 %146, i32 1 %149 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %148, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %150 = extractelement <4 x float> %149, i32 0 %151 = extractelement <4 x float> %149, i32 1 %152 = extractelement <4 x float> %149, i32 2 %153 = bitcast float %127 to i32 %154 = bitcast float %128 to i32 %155 = insertelement <2 x i32> undef, i32 %153, i32 0 %156 = insertelement <2 x i32> %155, i32 %154, i32 1 %157 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %156, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %158 = extractelement <4 x float> %157, i32 0 %159 = extractelement <4 x float> %157, i32 1 %160 = extractelement <4 x float> %157, i32 2 %161 = extractelement <4 x float> %157, i32 3 %162 = bitcast float %130 to i32 %163 = bitcast float %129 to i32 %164 = insertelement <2 x i32> undef, i32 %162, i32 0 %165 = insertelement <2 x i32> %164, i32 %163, i32 1 %166 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %165, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %167 = extractelement <4 x float> %166, i32 0 %168 = extractelement <4 x float> %166, i32 1 %169 = extractelement <4 x float> %166, i32 2 %170 = bitcast float %134 to i32 %171 = bitcast float %135 to i32 %172 = insertelement <2 x i32> undef, i32 %170, i32 0 %173 = insertelement <2 x i32> %172, i32 %171, i32 1 %174 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %173, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %175 = extractelement <4 x float> %174, i32 0 %176 = extractelement <4 x float> %174, i32 1 %177 = extractelement <4 x float> %174, i32 2 %178 = fmul float %141, %104 %179 = fmul float %142, %105 %180 = fmul float %143, %106 %181 = fmul float %144, %107 %182 = fmul float %151, %167 %183 = fmul float %151, %168 %184 = fmul float %151, %169 %185 = fmul float %150, %158 %186 = fadd float %185, %182 %187 = fmul float %150, %159 %188 = fadd float %187, %183 %189 = fmul float %150, %160 %190 = fadd float %189, %184 %191 = fmul float %152, %175 %192 = fadd float %191, %186 %193 = fmul float %152, %176 %194 = fadd float %193, %188 %195 = fmul float %152, %177 %196 = fadd float %195, %190 %197 = fmul float %192, %31 %198 = fmul float %194, %32 %199 = fmul float %196, %33 %200 = fmul float %197, 0x3FE279A740000000 %201 = fmul float %198, 0x3FE279A740000000 %202 = fmul float %199, 0x3FE279A740000000 %203 = fcmp ogt float %161, -0.000000e+00 %204 = bitcast float %84 to i32 %205 = icmp ne i32 %204, 0 %206 = and i1 %203, %205 br i1 %206, label %IF, label %ENDIF IF: ; preds = %main_body %207 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %208 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %209 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %210 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %211 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %212 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %213 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %214 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %215 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %216 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %217 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %218 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %219 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %220 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %221 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %222 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %223 = fadd float %158, %167 %224 = fadd float %159, %168 %225 = fadd float %160, %169 %226 = fadd float %175, %223 %227 = fadd float %176, %224 %228 = fadd float %177, %225 %229 = fmul float %226, 0x3FCB333340000000 %230 = fmul float %227, 0x3FE6E48E80000000 %231 = fadd float %230, %229 %232 = fmul float %228, 0x3FB2752540000000 %233 = fadd float %231, %232 %234 = fmul float %233, 0x3FD554C980000000 %235 = fdiv float 1.000000e+00, %234 %236 = fmul float %235, %161 %237 = fadd float %121, 0.000000e+00 %238 = fadd float %122, 0.000000e+00 %239 = fadd float %123, 0.000000e+00 %240 = fmul float %121, 0.000000e+00 %241 = fadd float %240, 1.000000e+00 %242 = fmul float %237, %222 %243 = fmul float %238, %221 %244 = fadd float %242, %243 %245 = fmul float %239, %220 %246 = fadd float %244, %245 %247 = fmul float %241, %219 %248 = fadd float %246, %247 %249 = fmul float %237, %218 %250 = fmul float %238, %217 %251 = fadd float %249, %250 %252 = fmul float %239, %216 %253 = fadd float %251, %252 %254 = fmul float %241, %215 %255 = fadd float %253, %254 %256 = call float @llvm.AMDIL.clamp.(float %248, float 0.000000e+00, float 1.000000e+00) %257 = call float @llvm.AMDIL.clamp.(float %255, float 0.000000e+00, float 1.000000e+00) %258 = fsub float %256, %248 %259 = fsub float %257, %255 %260 = fadd float %258, %259 %261 = fmul float %237, %45 %262 = fmul float %238, %46 %263 = fadd float %261, %262 %264 = fmul float %239, %47 %265 = fadd float %263, %264 %266 = fmul float %241, %48 %267 = fadd float %265, %266 %268 = fmul float %237, %49 %269 = fmul float %238, %50 %270 = fadd float %268, %269 %271 = fmul float %239, %51 %272 = fadd float %270, %271 %273 = fmul float %241, %52 %274 = fadd float %272, %273 %275 = call float @llvm.AMDIL.clamp.(float %267, float 0.000000e+00, float 1.000000e+00) %276 = call float @llvm.AMDIL.clamp.(float %274, float 0.000000e+00, float 1.000000e+00) %277 = fsub float %275, %267 %278 = fsub float %276, %274 %279 = fadd float %277, %278 %280 = fmul float %237, %53 %281 = fmul float %238, %54 %282 = fadd float %280, %281 %283 = fmul float %239, %55 %284 = fadd float %282, %283 %285 = fmul float %241, %56 %286 = fadd float %284, %285 %287 = fmul float %237, %57 %288 = fmul float %238, %58 %289 = fadd float %287, %288 %290 = fmul float %239, %59 %291 = fadd float %289, %290 %292 = fmul float %241, %60 %293 = fadd float %291, %292 %294 = call float @llvm.fabs.f32(float %279) %295 = fcmp ole float %294, -0.000000e+00 %. = select i1 %295, float %267, float %286 %296 = call float @llvm.fabs.f32(float %279) %297 = fcmp ole float %296, -0.000000e+00 %temp28.0 = select i1 %297, float %274, float %293 %298 = call float @llvm.fabs.f32(float %279) %299 = fcmp ole float %298, -0.000000e+00 %.240 = select i1 %299, float 1.000000e+00, float 2.000000e+00 %300 = call float @llvm.fabs.f32(float %260) %301 = fcmp ole float %300, -0.000000e+00 %temp28.2 = select i1 %301, float %248, float %. %302 = call float @llvm.fabs.f32(float %260) %303 = fcmp ole float %302, -0.000000e+00 %.temp28.0 = select i1 %303, float %255, float %temp28.0 %304 = call float @llvm.fabs.f32(float %260) %305 = fcmp ole float %304, -0.000000e+00 %temp12.1 = select i1 %305, float 0.000000e+00, float %.240 %306 = fmul float %237, %214 %307 = fmul float %238, %213 %308 = fadd float %306, %307 %309 = fmul float %239, %212 %310 = fadd float %308, %309 %311 = fmul float %241, %211 %312 = fadd float %310, %311 %313 = fadd float %temp28.2, -5.000000e-01 %314 = fadd float %.temp28.0, -5.000000e-01 %315 = call float @llvm.fabs.f32(float %313) %316 = call float @llvm.fabs.f32(float %314) %317 = fsub float %315, %41 %318 = fsub float %316, %41 %319 = fmul float %317, %42 %320 = fmul float %318, %42 %321 = call float @llvm.AMDIL.clamp.(float %319, float 0.000000e+00, float 1.000000e+00) %322 = call float @llvm.AMDIL.clamp.(float %320, float 0.000000e+00, float 1.000000e+00) %323 = fsub float 1.000000e+00, %321 %324 = fsub float 1.000000e+00, %322 %325 = fmul float %324, %323 %326 = call float @llvm.AMDIL.clamp.(float %temp28.2, float 0.000000e+00, float 1.000000e+00) %327 = call float @llvm.AMDIL.clamp.(float %.temp28.0, float 0.000000e+00, float 1.000000e+00) %328 = fadd float %temp12.1, 0.000000e+00 %329 = fadd float %temp12.1, -1.000000e+00 %330 = fadd float %temp12.1, -2.000000e+00 %331 = call float @llvm.fabs.f32(float %328) %332 = fcmp ole float %331, -0.000000e+00 %.241 = select i1 %332, float %208, float 0.000000e+00 %333 = call float @llvm.fabs.f32(float %328) %334 = fcmp ole float %333, -0.000000e+00 %temp60.0 = select i1 %334, float %207, float 0.000000e+00 %335 = call float @llvm.fabs.f32(float %328) %336 = fcmp ole float %335, -0.000000e+00 %.242 = select i1 %336, float %210, float 0.000000e+00 %337 = call float @llvm.fabs.f32(float %328) %338 = fcmp ole float %337, -0.000000e+00 %temp60.2 = select i1 %338, float %209, float 0.000000e+00 %339 = call float @llvm.fabs.f32(float %329) %340 = fcmp ole float %339, -0.000000e+00 %..241 = select i1 %340, float %71, float %.241 %341 = call float @llvm.fabs.f32(float %329) %342 = fcmp ole float %341, -0.000000e+00 %temp56.2 = select i1 %342, float %72, float %temp60.0 %343 = call float @llvm.fabs.f32(float %329) %344 = fcmp ole float %343, -0.000000e+00 %..242 = select i1 %344, float %69, float %.242 %345 = call float @llvm.fabs.f32(float %329) %346 = fcmp ole float %345, -0.000000e+00 %temp56.4 = select i1 %346, float %70, float %temp60.2 %347 = call float @llvm.fabs.f32(float %330) %348 = fcmp ole float %347, -0.000000e+00 %...241 = select i1 %348, float %75, float %..241 %349 = call float @llvm.fabs.f32(float %330) %350 = fcmp ole float %349, -0.000000e+00 %temp56.6 = select i1 %350, float %76, float %temp56.2 %351 = call float @llvm.fabs.f32(float %330) %352 = fcmp ole float %351, -0.000000e+00 %...242 = select i1 %352, float %73, float %..242 %353 = call float @llvm.fabs.f32(float %330) %354 = fcmp ole float %353, -0.000000e+00 %temp56.8 = select i1 %354, float %74, float %temp56.4 %355 = fmul float %326, %...241 %356 = fadd float %355, %...242 %357 = fmul float %327, %temp56.6 %358 = fadd float %357, %temp56.8 %359 = fadd float %356, 0x3F40000000000000 %360 = fadd float %358, 0x3F40000000000000 %361 = fadd float %312, 0.000000e+00 %362 = bitcast float %361 to i32 %363 = bitcast float %359 to i32 %364 = bitcast float %360 to i32 %365 = insertelement <4 x i32> undef, i32 %362, i32 0 %366 = insertelement <4 x i32> %365, i32 %363, i32 1 %367 = insertelement <4 x i32> %366, i32 %364, i32 2 %368 = insertelement <4 x i32> %367, i32 0, i32 3 %369 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %368, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %370 = extractelement <4 x float> %369, i32 0 %371 = fadd float %356, 0xBF40000000000000 %372 = fadd float %358, 0x3F40000000000000 %373 = fadd float %312, 0.000000e+00 %374 = fadd float %356, 0x3F40000000000000 %375 = fadd float %358, 0xBF40000000000000 %376 = fadd float %312, 0.000000e+00 %377 = fadd float %356, 0xBF40000000000000 %378 = fadd float %358, 0xBF40000000000000 %379 = fadd float %312, 0.000000e+00 %380 = bitcast float %373 to i32 %381 = bitcast float %371 to i32 %382 = bitcast float %372 to i32 %383 = insertelement <4 x i32> undef, i32 %380, i32 0 %384 = insertelement <4 x i32> %383, i32 %381, i32 1 %385 = insertelement <4 x i32> %384, i32 %382, i32 2 %386 = insertelement <4 x i32> %385, i32 0, i32 3 %387 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %386, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %388 = extractelement <4 x float> %387, i32 0 %389 = bitcast float %376 to i32 %390 = bitcast float %374 to i32 %391 = bitcast float %375 to i32 %392 = insertelement <4 x i32> undef, i32 %389, i32 0 %393 = insertelement <4 x i32> %392, i32 %390, i32 1 %394 = insertelement <4 x i32> %393, i32 %391, i32 2 %395 = insertelement <4 x i32> %394, i32 0, i32 3 %396 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %395, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %397 = extractelement <4 x float> %396, i32 0 %398 = bitcast float %379 to i32 %399 = bitcast float %377 to i32 %400 = bitcast float %378 to i32 %401 = insertelement <4 x i32> undef, i32 %398, i32 0 %402 = insertelement <4 x i32> %401, i32 %399, i32 1 %403 = insertelement <4 x i32> %402, i32 %400, i32 2 %404 = insertelement <4 x i32> %403, i32 0, i32 3 %405 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %404, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %406 = extractelement <4 x float> %405, i32 0 %407 = fmul float %370, 6.250000e-02 %408 = fmul float %388, 6.250000e-02 %409 = fadd float %407, %408 %410 = fmul float %397, 6.250000e-02 %411 = fadd float %409, %410 %412 = fmul float %406, 6.250000e-02 %413 = fadd float %411, %412 %414 = fadd float %356, 0x3F40000000000000 %415 = fadd float %358, 0.000000e+00 %416 = fadd float %312, 0.000000e+00 %417 = bitcast float %416 to i32 %418 = bitcast float %414 to i32 %419 = bitcast float %415 to i32 %420 = insertelement <4 x i32> undef, i32 %417, i32 0 %421 = insertelement <4 x i32> %420, i32 %418, i32 1 %422 = insertelement <4 x i32> %421, i32 %419, i32 2 %423 = insertelement <4 x i32> %422, i32 0, i32 3 %424 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %423, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %425 = extractelement <4 x float> %424, i32 0 %426 = fadd float %356, 0xBF40000000000000 %427 = fadd float %358, 0.000000e+00 %428 = fadd float %312, 0.000000e+00 %429 = bitcast float %428 to i32 %430 = bitcast float %426 to i32 %431 = bitcast float %427 to i32 %432 = insertelement <4 x i32> undef, i32 %429, i32 0 %433 = insertelement <4 x i32> %432, i32 %430, i32 1 %434 = insertelement <4 x i32> %433, i32 %431, i32 2 %435 = insertelement <4 x i32> %434, i32 0, i32 3 %436 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %435, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %437 = extractelement <4 x float> %436, i32 0 %438 = fadd float %356, 0.000000e+00 %439 = fadd float %358, 0xBF40000000000000 %440 = fadd float %312, 0.000000e+00 %441 = bitcast float %440 to i32 %442 = bitcast float %438 to i32 %443 = bitcast float %439 to i32 %444 = insertelement <4 x i32> undef, i32 %441, i32 0 %445 = insertelement <4 x i32> %444, i32 %442, i32 1 %446 = insertelement <4 x i32> %445, i32 %443, i32 2 %447 = insertelement <4 x i32> %446, i32 0, i32 3 %448 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %447, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %449 = extractelement <4 x float> %448, i32 0 %450 = fadd float %356, 0.000000e+00 %451 = fadd float %358, 0x3F40000000000000 %452 = fadd float %312, 0.000000e+00 %453 = bitcast float %452 to i32 %454 = bitcast float %450 to i32 %455 = bitcast float %451 to i32 %456 = insertelement <4 x i32> undef, i32 %453, i32 0 %457 = insertelement <4 x i32> %456, i32 %454, i32 1 %458 = insertelement <4 x i32> %457, i32 %455, i32 2 %459 = insertelement <4 x i32> %458, i32 0, i32 3 %460 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %459, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %461 = extractelement <4 x float> %460, i32 0 %462 = fmul float %425, 1.250000e-01 %463 = fmul float %437, 1.250000e-01 %464 = fadd float %462, %463 %465 = fmul float %449, 1.250000e-01 %466 = fadd float %464, %465 %467 = fmul float %461, 1.250000e-01 %468 = fadd float %466, %467 %469 = bitcast float %312 to i32 %470 = bitcast float %356 to i32 %471 = bitcast float %358 to i32 %472 = insertelement <4 x i32> undef, i32 %469, i32 0 %473 = insertelement <4 x i32> %472, i32 %470, i32 1 %474 = insertelement <4 x i32> %473, i32 %471, i32 2 %475 = insertelement <4 x i32> %474, i32 0, i32 3 %476 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %475, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %477 = extractelement <4 x float> %476, i32 0 %478 = fadd float %468, %413 %479 = fmul float %477, 2.500000e-01 %480 = fadd float %479, %478 %481 = fcmp olt float %325, 1.000000e+00 br i1 %481, label %IF127, label %ENDIF126 ENDIF: ; preds = %main_body, %ENDIF126 %temp2.0 = phi float [ %773, %ENDIF126 ], [ %202, %main_body ] %temp1.0 = phi float [ %769, %ENDIF126 ], [ %201, %main_body ] %temp.0 = phi float [ %765, %ENDIF126 ], [ %200, %main_body ] %482 = fadd float %temp.0, %38 %483 = fadd float %temp1.0, %39 %484 = fadd float %temp2.0, %40 %485 = fmul float %178, %482 %486 = fmul float %179, %483 %487 = fmul float %180, %484 %488 = fsub float %25, %121 %489 = fsub float %26, %122 %490 = fsub float %27, %123 %491 = fmul float %488, %488 %492 = fmul float %489, %489 %493 = fadd float %492, %491 %494 = fmul float %490, %490 %495 = fadd float %493, %494 %496 = call float @llvm.sqrt.f32(float %495) %497 = fmul float %496, %30 %498 = fadd float %497, %28 %499 = call float @llvm.AMDIL.clamp.(float %498, float 0.000000e+00, float 1.000000e+00) %500 = call float @llvm.minnum.f32(float %499, float %29) %501 = fmul float %485, %37 %502 = fmul float %486, %37 %503 = fmul float %487, %37 %504 = fmul float %500, %500 %505 = fmul float %37, %485 %506 = fsub float %34, %505 %507 = fmul float %37, %486 %508 = fsub float %35, %507 %509 = fmul float %37, %487 %510 = fsub float %36, %509 %511 = fmul float %504, %506 %512 = fadd float %511, %501 %513 = fmul float %504, %508 %514 = fadd float %513, %502 %515 = fmul float %504, %510 %516 = fadd float %515, %503 %517 = call i32 @llvm.SI.packf16(float %512, float %514) %518 = bitcast i32 %517 to float %519 = call i32 @llvm.SI.packf16(float %516, float %181) %520 = bitcast i32 %519 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %518, float %520, float %518, float %520) ret void IF127: ; preds = %IF %521 = call float @llvm.fabs.f32(float %328) %522 = fcmp ole float %521, -0.000000e+00 %.243 = select i1 %522, float %45, float 0.000000e+00 %523 = call float @llvm.fabs.f32(float %328) %524 = fcmp ole float %523, -0.000000e+00 %temp60.5 = select i1 %524, float %46, float 0.000000e+00 %525 = call float @llvm.fabs.f32(float %328) %526 = fcmp ole float %525, -0.000000e+00 %.244 = select i1 %526, float %47, float 0.000000e+00 %527 = call float @llvm.fabs.f32(float %328) %528 = fcmp ole float %527, -0.000000e+00 %temp60.7 = select i1 %528, float %48, float 0.000000e+00 %529 = call float @llvm.fabs.f32(float %328) %530 = fcmp ole float %529, -0.000000e+00 %.245 = select i1 %530, float %49, float 0.000000e+00 %531 = call float @llvm.fabs.f32(float %328) %532 = fcmp ole float %531, -0.000000e+00 %temp60.9 = select i1 %532, float %50, float 0.000000e+00 %533 = call float @llvm.fabs.f32(float %328) %534 = fcmp ole float %533, -0.000000e+00 %.246 = select i1 %534, float %51, float 0.000000e+00 %535 = call float @llvm.fabs.f32(float %328) %536 = fcmp ole float %535, -0.000000e+00 %temp60.11 = select i1 %536, float %52, float 0.000000e+00 %537 = call float @llvm.fabs.f32(float %329) %538 = fcmp ole float %537, -0.000000e+00 %..243 = select i1 %538, float %53, float %.243 %539 = call float @llvm.fabs.f32(float %329) %540 = fcmp ole float %539, -0.000000e+00 %temp60.13 = select i1 %540, float %54, float %temp60.5 %541 = call float @llvm.fabs.f32(float %329) %542 = fcmp ole float %541, -0.000000e+00 %..244 = select i1 %542, float %55, float %.244 %543 = call float @llvm.fabs.f32(float %329) %544 = fcmp ole float %543, -0.000000e+00 %temp60.15 = select i1 %544, float %56, float %temp60.7 %545 = call float @llvm.fabs.f32(float %329) %546 = fcmp ole float %545, -0.000000e+00 %..245 = select i1 %546, float %57, float %.245 %547 = call float @llvm.fabs.f32(float %329) %548 = fcmp ole float %547, -0.000000e+00 %temp60.17 = select i1 %548, float %58, float %temp60.9 %549 = call float @llvm.fabs.f32(float %329) %550 = fcmp ole float %549, -0.000000e+00 %..246 = select i1 %550, float %59, float %.246 %551 = call float @llvm.fabs.f32(float %329) %552 = fcmp ole float %551, -0.000000e+00 %temp60.19 = select i1 %552, float %60, float %temp60.11 %553 = call float @llvm.fabs.f32(float %330) %554 = fcmp ole float %553, -0.000000e+00 %...243 = select i1 %554, float %61, float %..243 %555 = call float @llvm.fabs.f32(float %330) %556 = fcmp ole float %555, -0.000000e+00 %temp60.21 = select i1 %556, float %62, float %temp60.13 %557 = call float @llvm.fabs.f32(float %330) %558 = fcmp ole float %557, -0.000000e+00 %...244 = select i1 %558, float %63, float %..244 %559 = call float @llvm.fabs.f32(float %330) %560 = fcmp ole float %559, -0.000000e+00 %temp60.23 = select i1 %560, float %64, float %temp60.15 %561 = call float @llvm.fabs.f32(float %330) %562 = fcmp ole float %561, -0.000000e+00 %...245 = select i1 %562, float %65, float %..245 %563 = call float @llvm.fabs.f32(float %330) %564 = fcmp ole float %563, -0.000000e+00 %temp60.25 = select i1 %564, float %66, float %temp60.17 %565 = call float @llvm.fabs.f32(float %330) %566 = fcmp ole float %565, -0.000000e+00 %...246 = select i1 %566, float %67, float %..246 %567 = call float @llvm.fabs.f32(float %330) %568 = fcmp ole float %567, -0.000000e+00 %temp60.27 = select i1 %568, float %68, float %temp60.19 %569 = fmul float %237, %...243 %570 = fmul float %238, %temp60.21 %571 = fadd float %569, %570 %572 = fmul float %239, %...244 %573 = fadd float %571, %572 %574 = fmul float %241, %temp60.23 %575 = fadd float %573, %574 %576 = call float @llvm.AMDIL.clamp.(float %575, float 0.000000e+00, float 1.000000e+00) %577 = fmul float %237, %...245 %578 = fmul float %238, %temp60.25 %579 = fadd float %577, %578 %580 = fmul float %239, %...246 %581 = fadd float %579, %580 %582 = fmul float %241, %temp60.27 %583 = fadd float %581, %582 %584 = call float @llvm.AMDIL.clamp.(float %583, float 0.000000e+00, float 1.000000e+00) %585 = call float @llvm.fabs.f32(float %328) %586 = fcmp ole float %585, -0.000000e+00 %.247 = select i1 %586, float %71, float 0.000000e+00 %587 = call float @llvm.fabs.f32(float %328) %588 = fcmp ole float %587, -0.000000e+00 %temp64.0 = select i1 %588, float %72, float 0.000000e+00 %589 = call float @llvm.fabs.f32(float %328) %590 = fcmp ole float %589, -0.000000e+00 %.248 = select i1 %590, float %69, float 0.000000e+00 %591 = call float @llvm.fabs.f32(float %328) %592 = fcmp ole float %591, -0.000000e+00 %temp64.2 = select i1 %592, float %70, float 0.000000e+00 %593 = call float @llvm.fabs.f32(float %329) %594 = fcmp ole float %593, -0.000000e+00 %..247 = select i1 %594, float %75, float %.247 %595 = call float @llvm.fabs.f32(float %329) %596 = fcmp ole float %595, -0.000000e+00 %temp60.29 = select i1 %596, float %76, float %temp64.0 %597 = call float @llvm.fabs.f32(float %329) %598 = fcmp ole float %597, -0.000000e+00 %..248 = select i1 %598, float %73, float %.248 %599 = call float @llvm.fabs.f32(float %329) %600 = fcmp ole float %599, -0.000000e+00 %temp60.31 = select i1 %600, float %74, float %temp64.2 %601 = call float @llvm.fabs.f32(float %330) %602 = fcmp ole float %601, -0.000000e+00 %...247 = select i1 %602, float %79, float %..247 %603 = call float @llvm.fabs.f32(float %330) %604 = fcmp ole float %603, -0.000000e+00 %temp60.33 = select i1 %604, float %80, float %temp60.29 %605 = call float @llvm.fabs.f32(float %330) %606 = fcmp ole float %605, -0.000000e+00 %...248 = select i1 %606, float %77, float %..248 %607 = call float @llvm.fabs.f32(float %330) %608 = fcmp ole float %607, -0.000000e+00 %temp60.35 = select i1 %608, float %78, float %temp60.31 %609 = fmul float %576, %...247 %610 = fadd float %609, %...248 %611 = fmul float %584, %temp60.33 %612 = fadd float %611, %temp60.35 %613 = fadd float %610, 0x3F40000000000000 %614 = fadd float %612, 0x3F40000000000000 %615 = fadd float %312, 0.000000e+00 %616 = bitcast float %615 to i32 %617 = bitcast float %613 to i32 %618 = bitcast float %614 to i32 %619 = insertelement <4 x i32> undef, i32 %616, i32 0 %620 = insertelement <4 x i32> %619, i32 %617, i32 1 %621 = insertelement <4 x i32> %620, i32 %618, i32 2 %622 = insertelement <4 x i32> %621, i32 0, i32 3 %623 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %622, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %624 = extractelement <4 x float> %623, i32 0 %625 = fadd float %610, 0xBF40000000000000 %626 = fadd float %612, 0x3F40000000000000 %627 = fadd float %312, 0.000000e+00 %628 = fadd float %610, 0x3F40000000000000 %629 = fadd float %612, 0xBF40000000000000 %630 = fadd float %312, 0.000000e+00 %631 = fadd float %610, 0xBF40000000000000 %632 = fadd float %612, 0xBF40000000000000 %633 = fadd float %312, 0.000000e+00 %634 = bitcast float %627 to i32 %635 = bitcast float %625 to i32 %636 = bitcast float %626 to i32 %637 = insertelement <4 x i32> undef, i32 %634, i32 0 %638 = insertelement <4 x i32> %637, i32 %635, i32 1 %639 = insertelement <4 x i32> %638, i32 %636, i32 2 %640 = insertelement <4 x i32> %639, i32 0, i32 3 %641 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %640, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %642 = extractelement <4 x float> %641, i32 0 %643 = bitcast float %630 to i32 %644 = bitcast float %628 to i32 %645 = bitcast float %629 to i32 %646 = insertelement <4 x i32> undef, i32 %643, i32 0 %647 = insertelement <4 x i32> %646, i32 %644, i32 1 %648 = insertelement <4 x i32> %647, i32 %645, i32 2 %649 = insertelement <4 x i32> %648, i32 0, i32 3 %650 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %649, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %651 = extractelement <4 x float> %650, i32 0 %652 = bitcast float %633 to i32 %653 = bitcast float %631 to i32 %654 = bitcast float %632 to i32 %655 = insertelement <4 x i32> undef, i32 %652, i32 0 %656 = insertelement <4 x i32> %655, i32 %653, i32 1 %657 = insertelement <4 x i32> %656, i32 %654, i32 2 %658 = insertelement <4 x i32> %657, i32 0, i32 3 %659 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %658, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %660 = extractelement <4 x float> %659, i32 0 %661 = fmul float %624, 6.250000e-02 %662 = fmul float %642, 6.250000e-02 %663 = fadd float %661, %662 %664 = fmul float %651, 6.250000e-02 %665 = fadd float %663, %664 %666 = fmul float %660, 6.250000e-02 %667 = fadd float %665, %666 %668 = fadd float %610, 0x3F40000000000000 %669 = fadd float %612, 0.000000e+00 %670 = fadd float %312, 0.000000e+00 %671 = bitcast float %670 to i32 %672 = bitcast float %668 to i32 %673 = bitcast float %669 to i32 %674 = insertelement <4 x i32> undef, i32 %671, i32 0 %675 = insertelement <4 x i32> %674, i32 %672, i32 1 %676 = insertelement <4 x i32> %675, i32 %673, i32 2 %677 = insertelement <4 x i32> %676, i32 0, i32 3 %678 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %677, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %679 = extractelement <4 x float> %678, i32 0 %680 = fadd float %610, 0xBF40000000000000 %681 = fadd float %612, 0.000000e+00 %682 = fadd float %312, 0.000000e+00 %683 = bitcast float %682 to i32 %684 = bitcast float %680 to i32 %685 = bitcast float %681 to i32 %686 = insertelement <4 x i32> undef, i32 %683, i32 0 %687 = insertelement <4 x i32> %686, i32 %684, i32 1 %688 = insertelement <4 x i32> %687, i32 %685, i32 2 %689 = insertelement <4 x i32> %688, i32 0, i32 3 %690 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %689, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %691 = extractelement <4 x float> %690, i32 0 %692 = fadd float %610, 0.000000e+00 %693 = fadd float %612, 0xBF40000000000000 %694 = fadd float %312, 0.000000e+00 %695 = bitcast float %694 to i32 %696 = bitcast float %692 to i32 %697 = bitcast float %693 to i32 %698 = insertelement <4 x i32> undef, i32 %695, i32 0 %699 = insertelement <4 x i32> %698, i32 %696, i32 1 %700 = insertelement <4 x i32> %699, i32 %697, i32 2 %701 = insertelement <4 x i32> %700, i32 0, i32 3 %702 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %701, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %703 = extractelement <4 x float> %702, i32 0 %704 = fadd float %610, 0.000000e+00 %705 = fadd float %612, 0x3F40000000000000 %706 = fadd float %312, 0.000000e+00 %707 = bitcast float %706 to i32 %708 = bitcast float %704 to i32 %709 = bitcast float %705 to i32 %710 = insertelement <4 x i32> undef, i32 %707, i32 0 %711 = insertelement <4 x i32> %710, i32 %708, i32 1 %712 = insertelement <4 x i32> %711, i32 %709, i32 2 %713 = insertelement <4 x i32> %712, i32 0, i32 3 %714 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %713, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %715 = extractelement <4 x float> %714, i32 0 %716 = fmul float %679, 1.250000e-01 %717 = fmul float %691, 1.250000e-01 %718 = fadd float %716, %717 %719 = fmul float %703, 1.250000e-01 %720 = fadd float %718, %719 %721 = fmul float %715, 1.250000e-01 %722 = fadd float %720, %721 %723 = bitcast float %312 to i32 %724 = bitcast float %610 to i32 %725 = bitcast float %612 to i32 %726 = insertelement <4 x i32> undef, i32 %723, i32 0 %727 = insertelement <4 x i32> %726, i32 %724, i32 1 %728 = insertelement <4 x i32> %727, i32 %725, i32 2 %729 = insertelement <4 x i32> %728, i32 0, i32 3 %730 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %729, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %731 = extractelement <4 x float> %730, i32 0 %732 = fadd float %722, %667 %733 = fmul float %731, 2.500000e-01 %734 = fadd float %733, %732 %735 = fcmp oge float %330, 0.000000e+00 %.249 = select i1 %735, float 1.000000e+00, float %734 %736 = fsub float 1.000000e+00, %325 %737 = fmul float %480, %325 %738 = fmul float %.249, %736 %739 = fadd float %737, %738 br label %ENDIF126 ENDIF126: ; preds = %IF, %IF127 %temp24.0 = phi float [ %739, %IF127 ], [ %480, %IF ] %740 = fsub float %121, %81 %741 = fsub float %122, %82 %742 = fsub float %123, %83 %743 = fmul float %740, %740 %744 = fmul float %741, %741 %745 = fadd float %744, %743 %746 = fmul float %742, %742 %747 = fadd float %745, %746 %748 = fmul float %747, %44 %749 = fadd float %748, %43 %750 = call float @llvm.AMDIL.clamp.(float %749, float 0.000000e+00, float 1.000000e+00) %751 = fsub float 1.000000e+00, %750 %752 = fmul float %temp24.0, %751 %753 = fadd float %750, %752 %754 = fsub float 1.000000e+00, %753 %755 = fmul float %754, %236 %756 = fsub float 1.000000e+00, %755 %757 = fmul float %756, %202 %758 = fmul float %756, %201 %759 = fmul float %756, %200 %760 = fmul float %756, 5.000000e-01 %761 = fadd float %760, 5.000000e-01 %762 = fsub float 1.000000e+00, %761 %763 = fmul float %759, %761 %764 = fmul float %757, %762 %765 = fadd float %763, %764 %766 = fsub float 1.000000e+00, %761 %767 = fmul float %758, %761 %768 = fmul float %758, %766 %769 = fadd float %767, %768 %770 = fsub float 1.000000e+00, %761 %771 = fmul float %757, %761 %772 = fmul float %759, %770 %773 = fadd float %771, %772 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x0 ; C00E0803 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x20 ; C00E0403 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x40 ; C00E0603 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[44:47], s[4:5], 0x0 ; C00A0B02 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x20 ; C00A0A02 00000020 s_and_b32 s8, 1, s9 ; 86080981 v_cmp_eq_i32_e64 vcc, 1, s8 ; D0C2006A 00001081 v_cndmask_b32_e32 v10, v2, v0 ; 00140102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v11, v3, v1 ; 00160303 v_interp_p1_f32 v2, v10, 0, 0, [m0] ; D408000A v_interp_p2_f32 v2, [v2], v11, 0, 0, [m0] ; D409000B v_interp_p1_f32 v3, v10, 1, 0, [m0] ; D40C010A v_interp_p2_f32 v3, [v3], v11, 1, 0, [m0] ; D40D010B v_interp_p1_f32 v6, v10, 2, 0, [m0] ; D418020A v_interp_p2_f32 v6, [v6], v11, 2, 0, [m0] ; D419020B v_interp_p1_f32 v7, v10, 3, 0, [m0] ; D41C030A v_interp_p2_f32 v7, [v7], v11, 3, 0, [m0] ; D41D030B v_interp_p1_f32 v12, v10, 0, 1, [m0] ; D430040A v_interp_p2_f32 v12, [v12], v11, 0, 1, [m0] ; D431040B v_interp_p1_f32 v13, v10, 1, 1, [m0] ; D434050A v_interp_p2_f32 v13, [v13], v11, 1, 1, [m0] ; D435050B v_interp_p1_f32 v15, v10, 0, 2, [m0] ; D43C080A v_interp_p2_f32 v15, [v15], v11, 0, 2, [m0] ; D43D080B v_interp_p1_f32 v16, v10, 1, 2, [m0] ; D440090A v_interp_p2_f32 v16, [v16], v11, 1, 2, [m0] ; D441090B v_interp_p1_f32 v8, v10, 0, 3, [m0] ; D4200C0A v_interp_p2_f32 v8, [v8], v11, 0, 3, [m0] ; D4210C0B v_interp_p1_f32 v9, v10, 1, 3, [m0] ; D4240D0A v_interp_p2_f32 v9, [v9], v11, 1, 3, [m0] ; D4250D0B v_interp_p1_f32 v10, v10, 2, 3, [m0] ; D4280E0A v_interp_p2_f32 v10, [v10], v11, 2, 3, [m0] ; D4290E0B v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v4, v0, 0, 4, [m0] ; D4101000 v_interp_p2_f32 v4, [v4], v1, 0, 4, [m0] ; D4111001 v_interp_p1_f32 v5, v0, 1, 4, [m0] ; D4141100 v_interp_p2_f32 v5, [v5], v1, 1, 4, [m0] ; D4151101 v_interp_p1_f32 v20, v0, 2, 4, [m0] ; D4501200 v_interp_p2_f32 v20, [v20], v1, 2, 4, [m0] ; D4511201 v_interp_p1_f32 v19, v0, 3, 4, [m0] ; D44C1300 v_interp_p2_f32 v19, [v19], v1, 3, 4, [m0] ; D44D1301 v_interp_p1_f32 v22, v0, 0, 5, [m0] ; D4581400 v_interp_p2_f32 v22, [v22], v1, 0, 5, [m0] ; D4591401 v_interp_p1_f32 v23, v0, 1, 5, [m0] ; D45C1500 v_interp_p2_f32 v23, [v23], v1, 1, 5, [m0] ; D45D1501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[32:39], s[44:47] ; F0800F00 01680B0C s_nop 0 ; BF800000 image_sample v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[24:31], s[40:43] ; F0800700 0146190F s_nop 0 ; BF800000 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[16:23], s[0:3] ; F0800F00 00040F04 s_nop 0 ; BF800000 image_sample v[19:21], 7, 0, 0, 0, 0, 0, 0, 0, v[19:20], s[16:23], s[0:3] ; F0800700 00041313 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v0, v19, v26 ; 0A003513 v_mac_f32_e32 v0, v15, v25 ; 2C00330F v_mul_f32_e32 v1, v20, v26 ; 0A023514 v_mac_f32_e32 v1, v16, v25 ; 2C023310 v_mul_f32_e32 v4, v21, v26 ; 0A083515 v_mac_f32_e32 v4, v17, v25 ; 2C083311 s_buffer_load_dword s8, s[12:15], 0xc0 ; C0220206 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0xc4 ; C0220246 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0xc8 ; C0220606 000000C8 image_sample v[22:24], 7, 0, 0, 0, 0, 0, 0, 0, v[22:23], s[16:23], s[0:3] ; F0800700 00041616 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v0, v22, v27 ; 2C003716 v_mac_f32_e32 v1, v23, v27 ; 2C023717 v_mac_f32_e32 v4, v24, v27 ; 2C083718 s_buffer_load_dword s11, s[12:15], 0xbc ; C02202C6 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0x1e0 ; C0220286 000001E0 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x5a0 ; C0220006 000005A0 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v0, s8, v0 ; 0A000008 v_mul_f32_e32 v1, s9, v1 ; 0A020209 v_mul_f32_e32 v5, s24, v4 ; 0A0A0818 v_mov_b32_e32 v25, 0x3f13cd3a ; 7E3202FF 3F13CD3A v_mul_f32_e32 v0, v25, v0 ; 0A000119 v_mul_f32_e32 v4, v25, v1 ; 0A080319 v_mul_f32_e32 v1, v25, v5 ; 0A020B19 v_mov_b32_e32 v5, 0x80000000 ; 7E0A02FF 80000000 v_cmp_lt_f32_e32 vcc, v5, v18 ; 7C822505 v_cmp_ne_i32_e64 s[0:1], 0, s0 ; D0C50000 00000080 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[16:17], s[0:1] ; BE902000 s_xor_b64 s[16:17], exec, s[16:17] ; 8890107E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x440 ; C0220486 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a0 ; C0220586 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4a4 ; C02205C6 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4a8 ; C0220606 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4ac ; C0220646 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x4d0 ; C0220686 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d4 ; C02206C6 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4d8 ; C0220746 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4dc ; C02207C6 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e0 ; C0220846 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4e4 ; C02208C6 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x4e8 ; C0220906 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x4ec ; C0220946 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x550 ; C0220206 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x554 ; C0220246 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[12:15], 0x558 ; C0220B86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x570 ; C02209C6 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x574 ; C0220A46 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x578 ; C0220AC6 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[12:15], 0x57c ; C0220B46 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x590 ; C0220546 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x594 ; C0220506 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x598 ; C02204C6 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[48:55], s[6:7], 0x60 ; C00E0C03 00000060 s_nop 0 ; BF800000 s_load_dwordx4 s[56:59], s[4:5], 0x30 ; C00A0E02 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[12:15], 0x55c ; C0220BC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x560 ; C0220986 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x564 ; C0220A06 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x568 ; C0220A86 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[12:15], 0x56c ; C0220B06 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x490 ; C0220706 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x494 ; C0220786 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x498 ; C0220806 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x49c ; C0220886 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v5, 0, v9 ; 020A1280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v25, s66, v5 ; 0A320A42 v_add_f32_e32 v31, 0, v8 ; 023E1080 v_add_f32_e32 v30, 0, v10 ; 023C1480 v_mad_f32 v29, 0, v8, 1.0 ; D1C1001D 03CA1080 v_mac_f32_e32 v25, s3, v31 ; 2C323E03 v_mac_f32_e32 v25, s67, v30 ; 2C323C43 v_mac_f32_e32 v25, s68, v29 ; 2C323A44 v_mul_f32_e32 v26, s70, v5 ; 0A340A46 v_mac_f32_e32 v26, s69, v31 ; 2C343E45 v_mac_f32_e32 v26, s61, v30 ; 2C343C3D v_mac_f32_e32 v26, s62, v29 ; 2C343A3E v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_add_f32_e64 v28, 0, v26 clamp ; D101801C 00023480 v_subrev_f32_e32 v27, v25, v27 ; 06363719 v_subrev_f32_e32 v28, v26, v28 ; 0638391A v_add_f32_e32 v27, v28, v27 ; 0236371C v_mul_f32_e32 v28, s30, v5 ; 0A380A1E v_mac_f32_e32 v28, s28, v31 ; 2C383E1C v_mac_f32_e32 v28, s32, v30 ; 2C383C20 v_mac_f32_e32 v28, s34, v29 ; 2C383A22 v_mul_f32_e32 v32, s23, v5 ; 0A400A17 v_mac_f32_e32 v32, s22, v31 ; 2C403E16 v_mac_f32_e32 v32, s24, v30 ; 2C403C18 v_mac_f32_e32 v32, s25, v29 ; 2C403A19 v_add_f32_e64 v33, 0, v28 clamp ; D1018021 00023880 v_add_f32_e64 v34, 0, v32 clamp ; D1018022 00024080 v_subrev_f32_e32 v33, v28, v33 ; 0642431C v_subrev_f32_e32 v34, v32, v34 ; 06444520 v_add_f32_e32 v33, v34, v33 ; 02424322 v_mul_f32_e32 v34, s27, v5 ; 0A440A1B v_mac_f32_e32 v34, s26, v31 ; 2C443E1A v_mac_f32_e32 v34, s29, v30 ; 2C443C1D v_mac_f32_e32 v34, s31, v29 ; 2C443A1F v_mul_f32_e32 v35, s35, v5 ; 0A460A23 v_mac_f32_e32 v35, s33, v31 ; 2C463E21 v_mac_f32_e32 v35, s36, v30 ; 2C463C24 v_mac_f32_e32 v35, s37, v29 ; 2C463A25 v_mov_b32_e32 v38, 0x80000000 ; 7E4C02FF 80000000 v_cmp_le_f32_e64 vcc, |v33|, v38 ; D043016A 00024D21 v_cndmask_b32_e32 v28, v34, v28 ; 00383922 v_cndmask_b32_e32 v32, v35, v32 ; 00404123 v_cndmask_b32_e64 v33, 2.0, 1.0, vcc ; D1000021 01A9E4F4 v_cmp_le_f32_e64 vcc, |v27|, v38 ; D043016A 00024D1B v_cndmask_b32_e32 v28, v28, v25 ; 0038331C v_cndmask_b32_e32 v32, v32, v26 ; 00403520 v_cndmask_b32_e64 v26, v33, 0, vcc ; D100001A 01A90121 v_mul_f32_e32 v25, s64, v5 ; 0A320A40 v_mac_f32_e32 v25, s63, v31 ; 2C323E3F v_mac_f32_e32 v25, s65, v30 ; 2C323C41 v_mac_f32_e32 v25, s60, v29 ; 2C323A3C v_add_f32_e64 v33, 0, v28 clamp ; D1018021 00023880 v_add_f32_e64 v34, 0, v32 clamp ; D1018022 00024080 v_add_f32_e32 v37, 0, v26 ; 024A3480 v_add_f32_e32 v36, -1.0, v26 ; 024834F3 v_add_f32_e32 v35, -2.0, v26 ; 024634F5 v_cmp_le_f32_e64 vcc, |v37|, v38 ; D043016A 00024D25 v_mov_b32_e32 v26, s46 ; 7E34022E v_cndmask_b32_e32 v26, 0, v26 ; 00343480 v_mov_b32_e32 v27, s47 ; 7E36022F v_cndmask_b32_e32 v27, 0, v27 ; 00363680 v_mov_b32_e32 v39, s8 ; 7E4E0208 v_cndmask_b32_e32 v39, 0, v39 ; 004E4E80 v_mov_b32_e32 v40, s9 ; 7E500209 v_cndmask_b32_e32 v40, 0, v40 ; 00505080 v_cmp_le_f32_e64 vcc, |v36|, v38 ; D043016A 00024D24 v_mov_b32_e32 v41, s42 ; 7E52022A v_cndmask_b32_e32 v26, v26, v41 ; 0034531A v_mov_b32_e32 v41, s44 ; 7E52022C v_cndmask_b32_e32 v27, v27, v41 ; 0036531B v_mov_b32_e32 v41, s38 ; 7E520226 v_cndmask_b32_e32 v39, v39, v41 ; 004E5327 v_mov_b32_e32 v41, s40 ; 7E520228 v_cndmask_b32_e32 v40, v40, v41 ; 00505328 v_cmp_le_f32_e64 vcc, |v35|, v38 ; D043016A 00024D23 v_mov_b32_e32 v38, s43 ; 7E4C022B v_cndmask_b32_e32 v38, v26, v38 ; 004C4D1A v_mov_b32_e32 v26, s45 ; 7E34022D v_cndmask_b32_e32 v41, v27, v26 ; 0052351B v_mov_b32_e32 v26, s39 ; 7E340227 v_cndmask_b32_e32 v26, v39, v26 ; 00343527 v_mov_b32_e32 v27, s41 ; 7E360229 v_cndmask_b32_e32 v27, v40, v27 ; 00363728 v_mac_f32_e32 v26, v38, v33 ; 2C344326 v_mac_f32_e32 v27, v41, v34 ; 2C364529 v_mov_b32_e32 v33, 0x3a000000 ; 7E4202FF 3A000000 v_add_f32_e32 v39, v33, v26 ; 024E3521 v_add_f32_e32 v40, v33, v27 ; 02503721 v_add_f32_e32 v38, 0, v25 ; 024C3280 s_mov_b32 s46, 0 ; BEAE0080 v_mov_b32_e32 v41, s46 ; 7E52022E v_mov_b32_e32 v33, 0xba000000 ; 7E4202FF BA000000 v_add_f32_e32 v34, v33, v26 ; 02443521 v_mov_b32_e32 v42, v38 ; 7E540326 v_mov_b32_e32 v43, v39 ; 7E560327 v_mov_b32_e32 v44, v40 ; 7E580328 v_mov_b32_e32 v45, v41 ; 7E5A0329 v_add_f32_e32 v33, v33, v27 ; 02423721 v_mov_b32_e32 v43, v34 ; 7E560322 v_mov_b32_e32 v46, v38 ; 7E5C0326 v_mov_b32_e32 v47, v39 ; 7E5E0327 v_mov_b32_e32 v48, v40 ; 7E600328 v_mov_b32_e32 v49, v41 ; 7E620329 v_mov_b32_e32 v44, v40 ; 7E580328 v_mov_b32_e32 v48, v33 ; 7E600321 v_mov_b32_e32 v45, s46 ; 7E5A022E v_mov_b32_e32 v49, s46 ; 7E62022E image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[48:55], s[56:59] ; F0B00100 01CC2226 s_nop 0 ; BF800000 image_sample_c_l v50, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[48:55], s[56:59] ; F0B00100 01CC322A v_mov_b32_e32 v44, v33 ; 7E580321 image_sample_c_l v46, 1, 0, 0, 0, 0, 0, 0, 0, v[46:49], s[48:55], s[56:59] ; F0B00100 01CC2E2E v_mov_b32_e32 v45, s46 ; 7E5A022E image_sample_c_l v47, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[48:55], s[56:59] ; F0B00100 01CC2F2A v_add_f32_e32 v44, 0, v27 ; 02583680 v_mov_b32_e32 v51, v38 ; 7E660326 v_mov_b32_e32 v52, v39 ; 7E680327 v_mov_b32_e32 v53, v40 ; 7E6A0328 v_mov_b32_e32 v54, v41 ; 7E6C0329 v_mov_b32_e32 v53, v44 ; 7E6A032C v_add_f32_e32 v39, 0, v26 ; 024E3480 v_mov_b32_e32 v54, s46 ; 7E6C022E v_mov_b32_e32 v55, v38 ; 7E6E0326 v_mov_b32_e32 v56, v39 ; 7E700327 v_mov_b32_e32 v57, v40 ; 7E720328 v_mov_b32_e32 v58, v41 ; 7E740329 image_sample_c_l v48, 1, 0, 0, 0, 0, 0, 0, 0, v[51:54], s[48:55], s[56:59] ; F0B00100 01CC3033 v_mov_b32_e32 v57, v33 ; 7E720321 v_mov_b32_e32 v45, s46 ; 7E5A022E image_sample_c_l v33, 1, 0, 0, 0, 0, 0, 0, 0, v[42:45], s[48:55], s[56:59] ; F0B00100 01CC212A v_mov_b32_e32 v58, s46 ; 7E74022E image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[55:58], s[48:55], s[56:59] ; F0B00100 01CC2A37 v_mov_b32_e32 v41, s46 ; 7E52022E image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[48:55], s[56:59] ; F0B00100 01CC2626 v_mov_b32_e32 v39, 0x3d800000 ; 7E4E02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v40, v39, v50 ; 0A506527 v_mac_f32_e32 v40, v39, v34 ; 2C504527 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v40, v39, v46 ; 2C505D27 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v40, v39, v47 ; 2C505F27 v_mov_b32_e32 v34, 0x3e000000 ; 7E4402FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v33, v34, v33 ; 0A424322 v_mac_f32_e32 v33, v34, v48 ; 2C426122 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v33, v34, v42 ; 2C425522 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v33, v34, v38 ; 2C424D22 v_add_f32_e32 v28, -0.5, v28 ; 023838F1 v_add_f32_e32 v32, -0.5, v32 ; 024040F1 v_sub_f32_e64 v28, |v28|, s1 ; D102011C 0000031C v_sub_f32_e64 v32, |v32|, s1 ; D1020120 00000320 v_mul_f32_e32 v28, s2, v28 ; 0A383802 v_mul_f32_e32 v32, s2, v32 ; 0A404002 v_add_f32_e64 v28, 0, v28 clamp ; D101801C 00023880 v_add_f32_e64 v32, 0, v32 clamp ; D1018020 00024080 v_sub_f32_e32 v28, 1.0, v28 ; 043838F2 v_mad_f32 v34, -v32, v28, v28 ; D1C10022 24723920 v_mov_b32_e32 v28, 0 ; 7E380280 v_add_f32_e32 v32, v40, v33 ; 02404328 image_sample_c_l v26, 1, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[48:55], s[56:59] ; F0B00100 01CC1A19 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v32, v26, v32, 0x3e800000 ; 2E40411A 3E800000 v_mov_b32_e32 v33, s0 ; 7E420200 v_cmp_gt_f32_e32 vcc, 1.0, v34 ; 7C8844F2 s_and_saveexec_b64 s[60:61], vcc ; BEBC206A s_xor_b64 s[60:61], exec, s[60:61] ; 88BC3C7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s8, s[12:15], 0x510 ; C0220206 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x514 ; C0220246 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s47, s[12:15], 0x518 ; C0220BC6 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x51c ; C0220F86 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x520 ; C0220FC6 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x524 ; C0221006 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x528 ; C0221046 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x52c ; C0221086 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x580 ; C02210C6 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x584 ; C0221106 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x588 ; C0221146 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x58c ; C0221186 0000058C v_cmp_le_f32_e32 vcc, 0, v35 ; 7C864680 v_mov_b32_e32 v26, s28 ; 7E34021C v_mov_b32_e32 v27, s30 ; 7E36021E v_mov_b32_e32 v28, s32 ; 7E380220 v_mov_b32_e32 v38, s34 ; 7E4C0222 v_mov_b32_e32 v39, s22 ; 7E4E0216 v_mov_b32_e32 v40, s23 ; 7E500217 v_mov_b32_e32 v41, s24 ; 7E520218 v_mov_b32_e32 v42, s25 ; 7E540219 v_mov_b32_e32 v43, s26 ; 7E56021A v_mov_b32_e32 v44, s27 ; 7E58021B v_mov_b32_e32 v45, 0x80000000 ; 7E5A02FF 80000000 v_cmp_le_f32_e64 s[0:1], |v37|, v45 ; D0430100 00025B25 v_cmp_le_f32_e64 s[2:3], |v36|, v45 ; D0430102 00025B24 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v36, s8 ; 7E480208 v_mov_b32_e32 v37, s9 ; 7E4A0209 v_cmp_le_f32_e64 s[8:9], |v35|, v45 ; D0430108 00025B23 v_mov_b32_e32 v35, s29 ; 7E46021D v_mov_b32_e32 v45, s31 ; 7E5A021F v_cndmask_b32_e64 v26, 0, v26, s[0:1] ; D100001A 00023480 v_cndmask_b32_e64 v26, v26, v43, s[2:3] ; D100001A 000A571A v_mov_b32_e32 v43, s33 ; 7E560221 v_cndmask_b32_e64 v27, 0, v27, s[0:1] ; D100001B 00023680 v_cndmask_b32_e64 v27, v27, v44, s[2:3] ; D100001B 000A591B v_mov_b32_e32 v44, s35 ; 7E580223 v_cndmask_b32_e64 v28, 0, v28, s[0:1] ; D100001C 00023880 v_cndmask_b32_e64 v28, v28, v35, s[2:3] ; D100001C 000A471C v_mov_b32_e32 v35, s36 ; 7E460224 v_cndmask_b32_e64 v38, 0, v38, s[0:1] ; D1000026 00024C80 v_cndmask_b32_e64 v38, v38, v45, s[2:3] ; D1000026 000A5B26 v_mov_b32_e32 v45, s37 ; 7E5A0225 v_cndmask_b32_e64 v39, 0, v39, s[0:1] ; D1000027 00024E80 v_cndmask_b32_e64 v39, v39, v43, s[2:3] ; D1000027 000A5727 v_mov_b32_e32 v43, s38 ; 7E560226 v_cndmask_b32_e64 v40, 0, v40, s[0:1] ; D1000028 00025080 v_cndmask_b32_e64 v40, v40, v44, s[2:3] ; D1000028 000A5928 v_mov_b32_e32 v44, s40 ; 7E580228 v_cndmask_b32_e64 v41, 0, v41, s[0:1] ; D1000029 00025280 v_cndmask_b32_e64 v35, v41, v35, s[2:3] ; D1000023 000A4729 v_mov_b32_e32 v41, s42 ; 7E52022A v_cndmask_b32_e64 v42, 0, v42, s[0:1] ; D100002A 00025480 v_cndmask_b32_e64 v42, v42, v45, s[2:3] ; D100002A 000A5B2A v_mov_b32_e32 v45, s44 ; 7E5A022C v_cndmask_b32_e64 v26, v26, v36, s[8:9] ; D100001A 0022491A v_mov_b32_e32 v36, s39 ; 7E480227 v_cndmask_b32_e64 v27, v27, v37, s[8:9] ; D100001B 00224B1B v_mov_b32_e32 v37, s47 ; 7E4A022F v_cndmask_b32_e64 v28, v28, v37, s[8:9] ; D100001C 00224B1C v_mov_b32_e32 v37, s62 ; 7E4A023E v_cndmask_b32_e64 v37, v38, v37, s[8:9] ; D1000025 00224B26 v_mov_b32_e32 v38, s63 ; 7E4C023F v_cndmask_b32_e64 v38, v39, v38, s[8:9] ; D1000026 00224D27 v_mov_b32_e32 v39, s64 ; 7E4E0240 v_cndmask_b32_e64 v39, v40, v39, s[8:9] ; D1000027 00224F28 v_mov_b32_e32 v40, s65 ; 7E500241 v_cndmask_b32_e64 v35, v35, v40, s[8:9] ; D1000023 00225123 v_mov_b32_e32 v40, s66 ; 7E500242 v_cndmask_b32_e64 v40, v42, v40, s[8:9] ; D1000028 0022512A v_mov_b32_e32 v42, s41 ; 7E540229 v_mul_f32_e32 v27, v27, v5 ; 0A360B1B v_mac_f32_e32 v27, v26, v31 ; 2C363F1A v_mov_b32_e32 v26, s43 ; 7E34022B v_mac_f32_e32 v27, v28, v30 ; 2C363D1C v_mov_b32_e32 v28, s45 ; 7E38022D v_mac_f32_e32 v27, v37, v29 ; 2C363B25 v_add_f32_e64 v37, 0, v27 clamp ; D1018025 00023680 v_mul_f32_e32 v5, v39, v5 ; 0A0A0B27 v_mac_f32_e32 v5, v38, v31 ; 2C0A3F26 v_mac_f32_e32 v5, v35, v30 ; 2C0A3D23 v_mac_f32_e32 v5, v40, v29 ; 2C0A3B28 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_cndmask_b32_e64 v27, 0, v41, s[0:1] ; D100001B 00025280 v_cndmask_b32_e64 v29, 0, v45, s[0:1] ; D100001D 00025A80 v_cndmask_b32_e64 v30, 0, v43, s[0:1] ; D100001E 00025680 v_cndmask_b32_e64 v31, 0, v44, s[0:1] ; D100001F 00025880 v_cndmask_b32_e64 v26, v27, v26, s[2:3] ; D100001A 000A351B v_cndmask_b32_e64 v27, v29, v28, s[2:3] ; D100001B 000A391D v_cndmask_b32_e64 v28, v30, v36, s[2:3] ; D100001C 000A491E v_cndmask_b32_e64 v29, v31, v42, s[2:3] ; D100001D 000A551F v_mov_b32_e32 v30, s69 ; 7E3C0245 v_cndmask_b32_e64 v30, v26, v30, s[8:9] ; D100001E 00223D1A v_mov_b32_e32 v26, s70 ; 7E340246 v_cndmask_b32_e64 v31, v27, v26, s[8:9] ; D100001F 0022351B v_mov_b32_e32 v26, s67 ; 7E340243 v_cndmask_b32_e64 v26, v28, v26, s[8:9] ; D100001A 0022351C v_mov_b32_e32 v27, s68 ; 7E360244 v_cndmask_b32_e64 v27, v29, v27, s[8:9] ; D100001B 0022371D v_mac_f32_e32 v26, v30, v37 ; 2C344B1E v_mac_f32_e32 v27, v31, v5 ; 2C360B1F v_mov_b32_e32 v5, 0x3a000000 ; 7E0A02FF 3A000000 v_add_f32_e32 v29, v5, v26 ; 023A3505 v_add_f32_e32 v30, v5, v27 ; 023C3705 v_add_f32_e32 v28, 0, v25 ; 02383280 v_mov_b32_e32 v31, s46 ; 7E3E022E v_mov_b32_e32 v5, 0xba000000 ; 7E0A02FF BA000000 v_add_f32_e32 v35, v5, v26 ; 02463505 v_mov_b32_e32 v36, v28 ; 7E48031C v_mov_b32_e32 v37, v29 ; 7E4A031D v_mov_b32_e32 v38, v30 ; 7E4C031E v_mov_b32_e32 v39, v31 ; 7E4E031F v_mov_b32_e32 v37, v35 ; 7E4A0323 v_add_f32_e32 v5, v5, v27 ; 020A3705 v_mov_b32_e32 v38, v30 ; 7E4C031E v_mov_b32_e32 v40, v28 ; 7E50031C v_mov_b32_e32 v41, v29 ; 7E52031D v_mov_b32_e32 v42, v30 ; 7E54031E v_mov_b32_e32 v43, v31 ; 7E56031F image_sample_c_l v35, 1, 0, 0, 0, 0, 0, 0, 0, v[28:31], s[48:55], s[56:59] ; F0B00100 01CC231C v_mov_b32_e32 v39, s46 ; 7E4E022E v_mov_b32_e32 v42, v5 ; 7E540305 image_sample_c_l v44, 1, 0, 0, 0, 0, 0, 0, 0, v[36:39], s[48:55], s[56:59] ; F0B00100 01CC2C24 v_mov_b32_e32 v43, s46 ; 7E56022E v_mov_b32_e32 v38, v5 ; 7E4C0305 image_sample_c_l v40, 1, 0, 0, 0, 0, 0, 0, 0, v[40:43], s[48:55], s[56:59] ; F0B00100 01CC2828 v_mov_b32_e32 v39, s46 ; 7E4E022E image_sample_c_l v41, 1, 0, 0, 0, 0, 0, 0, 0, v[36:39], s[48:55], s[56:59] ; F0B00100 01CC2924 v_add_f32_e32 v38, 0, v27 ; 024C3680 v_mov_b32_e32 v45, v28 ; 7E5A031C v_mov_b32_e32 v46, v29 ; 7E5C031D v_mov_b32_e32 v47, v30 ; 7E5E031E v_mov_b32_e32 v48, v31 ; 7E60031F v_mov_b32_e32 v47, v38 ; 7E5E0326 v_add_f32_e32 v29, 0, v26 ; 023A3480 v_mov_b32_e32 v48, s46 ; 7E60022E v_mov_b32_e32 v49, v28 ; 7E62031C v_mov_b32_e32 v50, v29 ; 7E64031D v_mov_b32_e32 v51, v30 ; 7E66031E v_mov_b32_e32 v52, v31 ; 7E68031F image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[45:48], s[48:55], s[56:59] ; F0B00100 01CC2A2D v_mov_b32_e32 v51, v5 ; 7E660305 v_mov_b32_e32 v39, s46 ; 7E4E022E image_sample_c_l v5, 1, 0, 0, 0, 0, 0, 0, 0, v[36:39], s[48:55], s[56:59] ; F0B00100 01CC0524 v_mov_b32_e32 v52, s46 ; 7E68022E image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[49:52], s[48:55], s[56:59] ; F0B00100 01CC2431 v_mov_b32_e32 v31, s46 ; 7E3E022E image_sample_c_l v28, 1, 0, 0, 0, 0, 0, 0, 0, v[28:31], s[48:55], s[56:59] ; F0B00100 01CC1C1C v_mov_b32_e32 v29, 0x3d800000 ; 7E3A02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v30, v29, v44 ; 0A3C591D v_mac_f32_e32 v30, v29, v35 ; 2C3C471D s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v30, v29, v40 ; 2C3C511D s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v30, v29, v41 ; 2C3C531D v_mov_b32_e32 v29, 0x3e000000 ; 7E3A02FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v5, v29, v5 ; 0A0A0B1D v_mac_f32_e32 v5, v29, v42 ; 2C0A551D s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v5, v29, v36 ; 2C0A491D s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v5, v29, v28 ; 2C0A391D v_mov_b32_e32 v28, 0 ; 7E380280 image_sample_c_l v25, 1, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[48:55], s[56:59] ; F0B00100 01CC1919 v_add_f32_e32 v5, v30, v5 ; 020A0B1E s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v5, v25, v5, 0x3e800000 ; 2E0A0B19 3E800000 v_cndmask_b32_e64 v5, v5, 1.0, vcc ; D1000005 01A9E505 v_mad_f32 v5, -v34, v5, v5 ; D1C10005 24160B22 v_mac_f32_e32 v5, v34, v32 ; 2C0A4122 v_mov_b32_e32 v32, v5 ; 7E400305 s_or_b64 exec, exec, s[60:61] ; 87FE3C7E v_add_f32_e32 v5, v19, v15 ; 020A1F13 v_add_f32_e32 v15, v20, v16 ; 021E2114 v_add_f32_e32 v16, v21, v17 ; 02202315 v_add_f32_e32 v5, v5, v22 ; 020A2D05 v_add_f32_e32 v15, v15, v23 ; 021E2F0F v_add_f32_e32 v16, v16, v24 ; 02203110 v_mul_f32_e32 v5, 0x3e59999a, v5 ; 0A0A0AFF 3E59999A v_madmk_f32_e32 v5, v15, v5, 0x3f372474 ; 2E0A0B0F 3F372474 v_madmk_f32_e32 v5, v16, v5, 0x3d93a92a ; 2E0A0B10 3D93A92A v_mov_b32_e32 v15, 0xbeaaa64c ; 7E1E02FF BEAAA64C v_mul_f32_e32 v5, v5, v15 ; 0A0A1F05 v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mul_f32_e32 v5, v18, v5 ; 0A0A0B12 v_subrev_f32_e32 v15, s21, v8 ; 061E1015 v_subrev_f32_e32 v16, s20, v9 ; 06201214 v_subrev_f32_e32 v17, s19, v10 ; 06221413 v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_mac_f32_e32 v15, v16, v16 ; 2C1E2110 v_mac_f32_e32 v15, v17, v17 ; 2C1E2311 v_mad_f32 v15, v33, v15, s18 ; D1C1000F 004A1F21 v_add_f32_e64 v15, 0, v15 clamp ; D101800F 00021E80 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mac_f32_e32 v15, v16, v32 ; 2C1E4110 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mad_f32 v15, -v15, v5, v5 ; D1C1000F 24160B0F v_mad_f32 v5, v16, v5, 1.0 ; D1C10005 03CA0B10 v_mac_f32_e32 v1, v1, v15 ; 2C021F01 v_mac_f32_e32 v4, v4, v15 ; 2C081F04 v_mac_f32_e32 v0, v0, v15 ; 2C001F00 v_mad_f32 v5, 0.5, v5, 0.5 ; D1C10005 03C20AF0 v_mad_f32 v15, -v5, v1, v1 ; D1C1000F 24060305 v_mac_f32_e32 v15, v5, v0 ; 2C1E0105 v_mad_f32 v16, -v5, v4, v4 ; D1C10010 24120905 v_mac_f32_e32 v16, v5, v4 ; 2C200905 v_mad_f32 v17, -v5, v0, v0 ; D1C10011 24020105 v_mac_f32_e32 v17, v5, v1 ; 2C220305 v_mov_b32_e32 v0, v15 ; 7E00030F v_mov_b32_e32 v4, v16 ; 7E080310 v_mov_b32_e32 v1, v17 ; 7E020311 s_or_b64 exec, exec, s[16:17] ; 87FE107E s_buffer_load_dword s5, s[12:15], 0xa0 ; C0220146 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0xa4 ; C0220186 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0xa8 ; C02201C6 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xb0 ; C0220106 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xb8 ; C02200C6 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x1d0 ; C0220006 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d4 ; C0220046 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d8 ; C0220086 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1f0 ; C0220206 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0x1f4 ; C0220246 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x1f8 ; C0220306 000001F8 v_mov_b32_e32 v15, s11 ; 7E1E020B v_mov_b32_e32 v5, s10 ; 7E0A020A v_mul_f32_e32 v11, v2, v11 ; 0A161702 v_mul_f32_e32 v3, v3, v12 ; 0A061903 v_mul_f32_e32 v6, v6, v13 ; 0A0C1B06 v_mul_f32_e32 v2, v7, v14 ; 0A041D07 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v0, s8, v0 ; 02000008 v_add_f32_e32 v4, s9, v4 ; 02080809 v_add_f32_e32 v1, s12, v1 ; 0202020C v_mul_f32_e32 v0, v0, v11 ; 0A001700 v_mul_f32_e32 v3, v4, v3 ; 0A060704 v_mul_f32_e32 v1, v1, v6 ; 0A020D01 v_sub_f32_e32 v4, s5, v8 ; 04081005 v_sub_f32_e32 v6, s6, v9 ; 040C1206 v_sub_f32_e32 v7, s7, v10 ; 040E1407 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mac_f32_e32 v4, v6, v6 ; 2C080D06 v_mac_f32_e32 v4, v7, v7 ; 2C080F07 v_sqrt_f32_e32 v4, v4 ; 7E084F04 v_mad_f32 v4, v15, v4, s4 ; D1C10004 0012090F v_add_f32_e64 v4, 0, v4 clamp ; D1018004 00020880 v_min_f32_e32 v4, s3, v4 ; 14080803 v_mul_f32_e32 v6, s10, v0 ; 0A0C000A v_mul_f32_e32 v7, s10, v3 ; 0A0E060A v_mul_f32_e32 v8, s10, v1 ; 0A10020A v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mad_f32 v0, -v0, v5, s0 ; D1C10000 20020B00 v_mad_f32 v3, -v3, v5, s1 ; D1C10003 20060B03 v_mad_f32 v1, -v1, v5, s2 ; D1C10001 200A0B01 v_mac_f32_e32 v6, v0, v4 ; 2C0C0900 v_mac_f32_e32 v7, v3, v4 ; 2C0E0903 v_mac_f32_e32 v8, v1, v4 ; 2C100901 v_cvt_pkrtz_f16_f32_e64 v0, v6, v7 ; D2960000 00020F06 v_cvt_pkrtz_f16_f32_e64 v1, v8, v2 ; D2960001 00020508 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 60 Code Size: 3432 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL IN[6] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], CLIPVERTEX DCL OUT[3], GENERIC[0] DCL OUT[4], GENERIC[1] DCL OUT[5], GENERIC[2] DCL OUT[6], GENERIC[3] DCL OUT[7], GENERIC[4] DCL OUT[8], GENERIC[5] DCL OUT[9], GENERIC[6] DCL OUT[10], GENERIC[7] DCL CONST[0..51] DCL TEMP[0..11], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, IMM[0].xxxx 2: MOV TEMP[2].w, IMM[0].xxxx 3: MOV TEMP[3].w, IMM[0].xxxx 4: MOV TEMP[4].w, CONST[0].yyyy 5: MAD TEMP[5], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 6: DP4 TEMP[4].x, TEMP[5], CONST[48] 7: DP4 TEMP[6].x, TEMP[5], CONST[49] 8: MOV TEMP[4].y, TEMP[6].xxxx 9: DP4 TEMP[6].x, TEMP[5], CONST[50] 10: MOV TEMP[4].z, TEMP[6].xxxx 11: DP4 TEMP[6].x, TEMP[4], CONST[8] 12: DP4 TEMP[7].x, TEMP[4], CONST[9] 13: MOV TEMP[6].y, TEMP[7].xxxx 14: DP4 TEMP[8].x, TEMP[4], CONST[11] 15: MOV TEMP[6].w, TEMP[8].xxxx 16: DP4 TEMP[9].x, TEMP[4], CONST[10] 17: MOV TEMP[4].w, TEMP[9].xxxx 18: MOV TEMP[4], TEMP[4] 19: DP3 TEMP[10].x, IN[1].xyzz, CONST[48].xyzz 20: MOV TEMP[1].z, TEMP[10].xxxx 21: DP3 TEMP[10].x, IN[1].xyzz, CONST[49].xyzz 22: MOV TEMP[2].z, TEMP[10].xxxx 23: DP3 TEMP[10].x, IN[1].xyzz, CONST[50].xyzz 24: MOV TEMP[3].z, TEMP[10].xxxx 25: DP3 TEMP[1].x, IN[5].xyzz, CONST[48].xyzz 26: DP3 TEMP[2].x, IN[5].xyzz, CONST[49].xyzz 27: DP3 TEMP[3].x, IN[5].xyzz, CONST[50].xyzz 28: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz 29: MOV TEMP[1].y, TEMP[10].xxxx 30: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz 31: MOV TEMP[2].y, TEMP[10].xxxx 32: DP3 TEMP[10].x, IN[6].xyzz, CONST[50].xyzz 33: MOV TEMP[3].y, TEMP[10].xxxx 34: ADD TEMP[5].xy, IN[4].xyyy, IN[3].xyyy 35: ADD TEMP[10].xy, TEMP[5].yxxx, IN[4].yxxx 36: MOV TEMP[5].zw, TEMP[10].yyxy 37: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy 38: MOV TEMP[6].z, TEMP[9].xxxx 39: MOV TEMP[0].xy, IN[2].xyxx 40: MOV TEMP[10].zw, IN[2].yyxy 41: MOV TEMP[11], TEMP[6] 42: MAD TEMP[9].x, TEMP[9].xxxx, CONST[0].zzzz, -TEMP[8].xxxx 43: MOV TEMP[6].z, TEMP[9].xxxx 44: MOV TEMP[6].y, -TEMP[7].xxxx 45: MAD TEMP[6].xy, CONST[51].xyyy, TEMP[8].xxxx, TEMP[6].xyyy 46: MUL TEMP[7], CONST[0].yyxx, IN[2].xyxx 47: MAD TEMP[8], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 48: MOV OUT[3], TEMP[0] 49: MOV OUT[4], TEMP[7] 50: MOV OUT[9], TEMP[5] 51: MOV OUT[10], TEMP[10] 52: MOV OUT[5], TEMP[4] 53: MOV OUT[0], TEMP[6] 54: MOV OUT[6], TEMP[1] 55: MOV OUT[2], TEMP[11] 56: MOV OUT[7], TEMP[2] 57: MOV OUT[1], TEMP[8] 58: MOV OUT[8], TEMP[3] 59: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %63 = load <16 x i8>, <16 x i8> addrspace(2)* %62, align 16, !tbaa !0 %64 = add i32 %5, %8 %65 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %64) %66 = extractelement <4 x float> %65, i32 0 %67 = extractelement <4 x float> %65, i32 1 %68 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %69 = load <16 x i8>, <16 x i8> addrspace(2)* %68, align 16, !tbaa !0 %70 = add i32 %5, %8 %71 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %70) %72 = extractelement <4 x float> %71, i32 0 %73 = extractelement <4 x float> %71, i32 1 %74 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %75 = load <16 x i8>, <16 x i8> addrspace(2)* %74, align 16, !tbaa !0 %76 = add i32 %5, %8 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %76) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 5 %81 = load <16 x i8>, <16 x i8> addrspace(2)* %80, align 16, !tbaa !0 %82 = add i32 %5, %8 %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %82) %84 = extractelement <4 x float> %83, i32 0 %85 = extractelement <4 x float> %83, i32 1 %86 = extractelement <4 x float> %83, i32 2 %87 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 6 %88 = load <16 x i8>, <16 x i8> addrspace(2)* %87, align 16, !tbaa !0 %89 = add i32 %5, %8 %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %89) %91 = extractelement <4 x float> %90, i32 0 %92 = extractelement <4 x float> %90, i32 1 %93 = extractelement <4 x float> %90, i32 2 %94 = fmul float %52, %15 %95 = fadd float %94, %14 %96 = fmul float %53, %15 %97 = fadd float %96, %14 %98 = fmul float %54, %15 %99 = fadd float %98, %14 %100 = fmul float %52, %14 %101 = fadd float %100, %15 %102 = fmul float %95, %34 %103 = fmul float %97, %35 %104 = fadd float %102, %103 %105 = fmul float %99, %36 %106 = fadd float %104, %105 %107 = fmul float %101, %37 %108 = fadd float %106, %107 %109 = fmul float %95, %38 %110 = fmul float %97, %39 %111 = fadd float %109, %110 %112 = fmul float %99, %40 %113 = fadd float %111, %112 %114 = fmul float %101, %41 %115 = fadd float %113, %114 %116 = fmul float %95, %42 %117 = fmul float %97, %43 %118 = fadd float %116, %117 %119 = fmul float %99, %44 %120 = fadd float %118, %119 %121 = fmul float %101, %45 %122 = fadd float %120, %121 %123 = fmul float %108, %17 %124 = fmul float %115, %18 %125 = fadd float %123, %124 %126 = fmul float %122, %19 %127 = fadd float %125, %126 %128 = fmul float %15, %20 %129 = fadd float %127, %128 %130 = fmul float %108, %21 %131 = fmul float %115, %22 %132 = fadd float %130, %131 %133 = fmul float %122, %23 %134 = fadd float %132, %133 %135 = fmul float %15, %24 %136 = fadd float %134, %135 %137 = fmul float %108, %29 %138 = fmul float %115, %30 %139 = fadd float %137, %138 %140 = fmul float %122, %31 %141 = fadd float %139, %140 %142 = fmul float %15, %32 %143 = fadd float %141, %142 %144 = fmul float %108, %25 %145 = fmul float %115, %26 %146 = fadd float %144, %145 %147 = fmul float %122, %27 %148 = fadd float %146, %147 %149 = fmul float %15, %28 %150 = fadd float %148, %149 %151 = fmul float %59, %34 %152 = fmul float %60, %35 %153 = fadd float %152, %151 %154 = fmul float %61, %36 %155 = fadd float %153, %154 %156 = fmul float %59, %38 %157 = fmul float %60, %39 %158 = fadd float %157, %156 %159 = fmul float %61, %40 %160 = fadd float %158, %159 %161 = fmul float %59, %42 %162 = fmul float %60, %43 %163 = fadd float %162, %161 %164 = fmul float %61, %44 %165 = fadd float %163, %164 %166 = fmul float %84, %34 %167 = fmul float %85, %35 %168 = fadd float %167, %166 %169 = fmul float %86, %36 %170 = fadd float %168, %169 %171 = fmul float %84, %38 %172 = fmul float %85, %39 %173 = fadd float %172, %171 %174 = fmul float %86, %40 %175 = fadd float %173, %174 %176 = fmul float %84, %42 %177 = fmul float %85, %43 %178 = fadd float %177, %176 %179 = fmul float %86, %44 %180 = fadd float %178, %179 %181 = fmul float %91, %34 %182 = fmul float %92, %35 %183 = fadd float %182, %181 %184 = fmul float %93, %36 %185 = fadd float %183, %184 %186 = fmul float %91, %38 %187 = fmul float %92, %39 %188 = fadd float %187, %186 %189 = fmul float %93, %40 %190 = fadd float %188, %189 %191 = fmul float %91, %42 %192 = fmul float %92, %43 %193 = fadd float %192, %191 %194 = fmul float %93, %44 %195 = fadd float %193, %194 %196 = fadd float %78, %72 %197 = fadd float %79, %73 %198 = fadd float %197, %79 %199 = fadd float %196, %78 %200 = fadd float %199, %78 %201 = fadd float %198, %79 %202 = fmul float %150, %16 %203 = fsub float %202, %143 %204 = fmul float %46, %143 %205 = fadd float %204, %129 %206 = fmul float %47, %143 %207 = fsub float %206, %136 %208 = fmul float %15, %66 %209 = fmul float %15, %67 %210 = fmul float %14, %66 %211 = fmul float %14, %66 %212 = fmul float %33, %14 %213 = fadd float %212, %15 %214 = fmul float %33, %14 %215 = fadd float %214, %15 %216 = fmul float %33, %14 %217 = fadd float %216, %15 %218 = fmul float %33, %15 %219 = fadd float %218, %14 %220 = and i32 %7, 1 %221 = icmp eq i32 %220, 0 br i1 %221, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %222 = call float @llvm.AMDIL.clamp.(float %213, float 0.000000e+00, float 1.000000e+00) %223 = call float @llvm.AMDIL.clamp.(float %215, float 0.000000e+00, float 1.000000e+00) %224 = call float @llvm.AMDIL.clamp.(float %217, float 0.000000e+00, float 1.000000e+00) %225 = call float @llvm.AMDIL.clamp.(float %219, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.050 = phi float [ %225, %if-true-block ], [ %219, %main_body ] %.049 = phi float [ %224, %if-true-block ], [ %217, %main_body ] %.048 = phi float [ %223, %if-true-block ], [ %215, %main_body ] %.0 = phi float [ %222, %if-true-block ], [ %213, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.048, float %.049, float %.050) %226 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %227 = load <16 x i8>, <16 x i8> addrspace(2)* %226, align 16, !tbaa !0 %228 = call float @llvm.SI.load.const(<16 x i8> %227, i32 0) %229 = fmul float %228, %129 %230 = call float @llvm.SI.load.const(<16 x i8> %227, i32 4) %231 = fmul float %230, %136 %232 = fadd float %229, %231 %233 = call float @llvm.SI.load.const(<16 x i8> %227, i32 8) %234 = fmul float %233, %150 %235 = fadd float %232, %234 %236 = call float @llvm.SI.load.const(<16 x i8> %227, i32 12) %237 = fmul float %236, %143 %238 = fadd float %235, %237 %239 = call float @llvm.SI.load.const(<16 x i8> %227, i32 16) %240 = fmul float %239, %129 %241 = call float @llvm.SI.load.const(<16 x i8> %227, i32 20) %242 = fmul float %241, %136 %243 = fadd float %240, %242 %244 = call float @llvm.SI.load.const(<16 x i8> %227, i32 24) %245 = fmul float %244, %150 %246 = fadd float %243, %245 %247 = call float @llvm.SI.load.const(<16 x i8> %227, i32 28) %248 = fmul float %247, %143 %249 = fadd float %246, %248 %250 = call float @llvm.SI.load.const(<16 x i8> %227, i32 32) %251 = fmul float %250, %129 %252 = call float @llvm.SI.load.const(<16 x i8> %227, i32 36) %253 = fmul float %252, %136 %254 = fadd float %251, %253 %255 = call float @llvm.SI.load.const(<16 x i8> %227, i32 40) %256 = fmul float %255, %150 %257 = fadd float %254, %256 %258 = call float @llvm.SI.load.const(<16 x i8> %227, i32 44) %259 = fmul float %258, %143 %260 = fadd float %257, %259 %261 = call float @llvm.SI.load.const(<16 x i8> %227, i32 48) %262 = fmul float %261, %129 %263 = call float @llvm.SI.load.const(<16 x i8> %227, i32 52) %264 = fmul float %263, %136 %265 = fadd float %262, %264 %266 = call float @llvm.SI.load.const(<16 x i8> %227, i32 56) %267 = fmul float %266, %150 %268 = fadd float %265, %267 %269 = call float @llvm.SI.load.const(<16 x i8> %227, i32 60) %270 = fmul float %269, %143 %271 = fadd float %268, %270 %272 = call float @llvm.SI.load.const(<16 x i8> %227, i32 64) %273 = fmul float %272, %129 %274 = call float @llvm.SI.load.const(<16 x i8> %227, i32 68) %275 = fmul float %274, %136 %276 = fadd float %273, %275 %277 = call float @llvm.SI.load.const(<16 x i8> %227, i32 72) %278 = fmul float %277, %150 %279 = fadd float %276, %278 %280 = call float @llvm.SI.load.const(<16 x i8> %227, i32 76) %281 = fmul float %280, %143 %282 = fadd float %279, %281 %283 = call float @llvm.SI.load.const(<16 x i8> %227, i32 80) %284 = fmul float %283, %129 %285 = call float @llvm.SI.load.const(<16 x i8> %227, i32 84) %286 = fmul float %285, %136 %287 = fadd float %284, %286 %288 = call float @llvm.SI.load.const(<16 x i8> %227, i32 88) %289 = fmul float %288, %150 %290 = fadd float %287, %289 %291 = call float @llvm.SI.load.const(<16 x i8> %227, i32 92) %292 = fmul float %291, %143 %293 = fadd float %290, %292 %294 = call float @llvm.SI.load.const(<16 x i8> %227, i32 96) %295 = fmul float %294, %129 %296 = call float @llvm.SI.load.const(<16 x i8> %227, i32 100) %297 = fmul float %296, %136 %298 = fadd float %295, %297 %299 = call float @llvm.SI.load.const(<16 x i8> %227, i32 104) %300 = fmul float %299, %150 %301 = fadd float %298, %300 %302 = call float @llvm.SI.load.const(<16 x i8> %227, i32 108) %303 = fmul float %302, %143 %304 = fadd float %301, %303 %305 = call float @llvm.SI.load.const(<16 x i8> %227, i32 112) %306 = fmul float %305, %129 %307 = call float @llvm.SI.load.const(<16 x i8> %227, i32 116) %308 = fmul float %307, %136 %309 = fadd float %306, %308 %310 = call float @llvm.SI.load.const(<16 x i8> %227, i32 120) %311 = fmul float %310, %150 %312 = fadd float %309, %311 %313 = call float @llvm.SI.load.const(<16 x i8> %227, i32 124) %314 = fmul float %313, %143 %315 = fadd float %312, %314 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %66, float %67, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %208, float %209, float %210, float %211) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %108, float %115, float %122, float %150) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %170, float %185, float %155, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %175, float %190, float %160, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %180, float %195, float %165, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %196, float %197, float %198, float %199) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 40, i32 0, float %200, float %201, float %66, float %67) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %205, float %207, float %203, float %143) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %238, float %249, float %260, float %271) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %282, float %293, float %304, float %315) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x30 ; C00A0604 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x40 ; C00A0704 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[8:9], 0x50 ; C00A0804 00000050 s_nop 0 ; BF800000 s_load_dwordx4 s[36:39], s[8:9], 0x60 ; C00A0904 00000060 v_add_i32_e32 v14, vcc, s10, v0 ; 321C000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[7:10], v14, s[4:7], 0 idxen ; E00C2000 8001070E s_nop 0 ; BF800000 buffer_load_format_xyzw v[20:23], v14, s[16:19], 0 idxen ; E00C2000 8004140E s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v14, s[20:23], 0 idxen ; E00C2000 8005000E s_waitcnt vmcnt(2) ; BF8C0772 buffer_load_format_xyzw v[10:13], v14, s[24:27], 0 idxen ; E00C2000 80060A0E s_waitcnt vmcnt(1) ; BF8C0771 buffer_load_format_xyzw v[3:6], v14, s[28:31], 0 idxen ; E00C2000 8007030E s_nop 0 ; BF800000 buffer_load_format_xyzw v[16:19], v14, s[32:35], 0 idxen ; E00C2000 8008100E s_waitcnt vmcnt(2) ; BF8C0772 buffer_load_format_xyzw v[12:15], v14, s[36:39], 0 idxen ; E00C2000 80090C0E s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s26, s[4:7], 0x0 ; C0220682 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[4:7], 0x4 ; C02209C2 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[4:7], 0x8 ; C0220002 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x80 ; C02202C2 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x84 ; C0220382 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x88 ; C0220202 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x8c ; C0220042 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x90 ; C02203C2 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x94 ; C0220482 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x98 ; C0220282 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x9c ; C0220242 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0xa0 ; C02204C2 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0xa4 ; C02205C2 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0xa8 ; C0220502 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0xac ; C0220542 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0xb0 ; C0220442 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0xb4 ; C0220582 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0xb8 ; C0220402 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0xbc ; C0220342 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s40, s[4:7], 0x2fc ; C0220A02 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0x300 ; C0220782 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x304 ; C0220842 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x308 ; C0220702 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x30c ; C02206C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x310 ; C0220882 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x314 ; C0220902 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x318 ; C02207C2 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x31c ; C0220742 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x320 ; C0220942 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[4:7], 0x324 ; C0220982 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x328 ; C02208C2 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x32c ; C0220802 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x330 ; C0220602 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x334 ; C0220642 00000334 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v2, s39 ; 7E040227 s_waitcnt vmcnt(2) ; BF8C0772 v_mov_b32_e32 v5, s26 ; 7E0A021A v_mad_f32 v6, s40, v5, v2 ; D1C10006 040A0A28 v_mad_f32 v5, s40, v2, v5 ; D1C10005 04160428 s_and_b32 s4, 1, s12 ; 86040C81 v_cmp_eq_i32_e64 s[4:5], 1, s4 ; D0C20004 00000881 s_waitcnt vmcnt(1) ; BF8C0771 v_mov_b32_e32 v19, v6 ; 7E260306 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v15, v6 ; 7E1E0306 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842004 s_xor_b64 s[4:5], exec, s[4:5] ; 8884047E v_add_f32_e64 v15, 0, v6 clamp ; D101800F 00020C80 v_add_f32_e64 v19, 0, v6 clamp ; D1018013 00020C80 v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 s_or_b64 exec, exec, s[4:5] ; 87FE047E exp 15, 32, 0, 0, 0, v6, v15, v19, v5 ; C400020F 05130F06 s_load_dwordx4 s[4:7], s[2:3], 0x100 ; C00A0101 00000100 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s30, v20 ; 0A0A281E v_mac_f32_e32 v5, s33, v21 ; 2C0A2A21 v_mac_f32_e32 v5, s28, v22 ; 2C0A2C1C v_mul_f32_e32 v6, s34, v20 ; 0A0C2822 v_mac_f32_e32 v6, s36, v21 ; 2C0C2A24 v_mac_f32_e32 v6, s31, v22 ; 2C0C2C1F v_mul_f32_e32 v15, s37, v20 ; 0A1E2825 v_mac_f32_e32 v15, s38, v21 ; 2C1E2A26 v_mac_f32_e32 v15, s35, v22 ; 2C1E2C23 v_mul_f32_e32 v19, s30, v16 ; 0A26201E v_mac_f32_e32 v19, s33, v17 ; 2C262221 v_mac_f32_e32 v19, s28, v18 ; 2C26241C v_mul_f32_e32 v20, s34, v16 ; 0A282022 v_mac_f32_e32 v20, s36, v17 ; 2C282224 v_mac_f32_e32 v20, s31, v18 ; 2C28241F v_mul_f32_e32 v16, s37, v16 ; 0A202025 v_mac_f32_e32 v16, s38, v17 ; 2C202226 v_mac_f32_e32 v16, s35, v18 ; 2C202423 v_mul_f32_e32 v17, s30, v12 ; 0A22181E v_mac_f32_e32 v17, s33, v13 ; 2C221A21 v_mac_f32_e32 v17, s28, v14 ; 2C221C1C v_mul_f32_e32 v18, s34, v12 ; 0A241822 v_mac_f32_e32 v18, s36, v13 ; 2C241A24 v_mac_f32_e32 v18, s31, v14 ; 2C241C1F v_mul_f32_e32 v12, s37, v12 ; 0A181825 v_mac_f32_e32 v12, s38, v13 ; 2C181A26 v_mac_f32_e32 v12, s35, v14 ; 2C181C23 v_mad_f32 v13, v2, v7, s26 ; D1C1000D 006A0F02 v_mad_f32 v8, v8, v2, s26 ; D1C10008 006A0508 v_mad_f32 v9, v9, v2, s26 ; D1C10009 006A0509 v_mad_f32 v7, s26, v7, v2 ; D1C10007 040A0E1A v_add_f32_e32 v10, v10, v3 ; 0214070A v_add_f32_e32 v11, v11, v4 ; 0216090B v_add_f32_e32 v14, v4, v11 ; 021C1704 v_add_f32_e32 v21, v3, v10 ; 022A1503 v_add_f32_e32 v3, v3, v21 ; 02062B03 v_add_f32_e32 v4, v4, v14 ; 02081D04 v_mov_b32_e32 v22, 0 ; 7E2C0280 exp 15, 33, 0, 0, 0, v0, v1, v22, v22 ; C400021F 16160100 v_mul_f32_e32 v23, s26, v0 ; 0A2E001A v_mul_f32_e32 v24, v0, v2 ; 0A300500 v_mul_f32_e32 v25, v1, v2 ; 0A320501 exp 15, 34, 0, 0, 0, v24, v25, v23, v23 ; C400022F 17171918 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v23, s33, v8 ; 0A2E1021 v_mac_f32_e32 v23, s30, v13 ; 2C2E1A1E v_mul_f32_e32 v24, s36, v8 ; 0A301024 v_mac_f32_e32 v24, s34, v13 ; 2C301A22 v_mul_f32_e32 v8, s38, v8 ; 0A101026 v_mac_f32_e32 v8, s37, v13 ; 2C101A25 v_mac_f32_e32 v23, s28, v9 ; 2C2E121C v_mac_f32_e32 v24, s31, v9 ; 2C30121F v_mac_f32_e32 v8, s35, v9 ; 2C101223 v_mac_f32_e32 v23, s27, v7 ; 2C2E0E1B v_mac_f32_e32 v24, s29, v7 ; 2C300E1D v_mac_f32_e32 v8, s32, v7 ; 2C100E20 v_mul_f32_e32 v7, s14, v24 ; 0A0E300E v_mac_f32_e32 v7, s11, v23 ; 2C0E2E0B v_mul_f32_e32 v9, s18, v24 ; 0A123012 v_mac_f32_e32 v9, s15, v23 ; 2C122E0F v_mul_f32_e32 v13, s23, v24 ; 0A1A3017 v_mac_f32_e32 v13, s19, v23 ; 2C1A2E13 v_mac_f32_e32 v13, s20, v8 ; 2C1A1014 v_mac_f32_e32 v13, s21, v2 ; 2C1A0415 exp 15, 35, 0, 0, 0, v23, v24, v8, v13 ; C400023F 0D081817 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v24, s22, v24 ; 0A303016 v_mac_f32_e32 v24, s17, v23 ; 2C302E11 v_mac_f32_e32 v7, s8, v8 ; 2C0E1008 v_mac_f32_e32 v9, s10, v8 ; 2C12100A v_mac_f32_e32 v24, s16, v8 ; 2C301010 v_mac_f32_e32 v7, s1, v2 ; 2C0E0401 v_mac_f32_e32 v9, s9, v2 ; 2C120409 v_mac_f32_e32 v24, s13, v2 ; 2C30040D s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[4:7], 0x0 ; C0220042 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x4 ; C0220082 00000004 exp 15, 36, 0, 0, 0, v19, v17, v5, v22 ; C400024F 16051113 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x8 ; C02200C2 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0xc ; C0220202 0000000C v_mad_f32 v2, v13, s0, -v24 ; D1C10002 8460010D s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v5, s24, v24, v7 ; D1C10005 041E3018 v_mad_f32 v8, s25, v24, -v9 ; D1C10008 84263019 s_buffer_load_dword s0, s[4:7], 0x10 ; C0220002 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x14 ; C0220242 00000014 exp 15, 37, 0, 0, 0, v20, v18, v6, v22 ; C400025F 16061214 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v6, s2, v9 ; 0A0C1202 v_mac_f32_e32 v6, s1, v7 ; 2C0C0E01 v_mac_f32_e32 v6, s3, v13 ; 2C0C1A03 v_mac_f32_e32 v6, s8, v24 ; 2C0C3008 s_buffer_load_dword s1, s[4:7], 0x18 ; C0220042 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x1c ; C0220082 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x20 ; C02200C2 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x24 ; C0220202 00000024 v_mul_f32_e32 v17, s9, v9 ; 0A221209 s_buffer_load_dword s9, s[4:7], 0x28 ; C0220242 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x2c ; C0220282 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30 ; C02202C2 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x34 ; C0220302 00000034 v_mac_f32_e32 v17, s0, v7 ; 2C220E00 s_buffer_load_dword s0, s[4:7], 0x38 ; C0220002 00000038 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v17, s1, v13 ; 2C221A01 v_mac_f32_e32 v17, s2, v24 ; 2C223002 v_mul_f32_e32 v18, s8, v9 ; 0A241208 v_mac_f32_e32 v18, s3, v7 ; 2C240E03 v_mac_f32_e32 v18, s9, v13 ; 2C241A09 v_mac_f32_e32 v18, s10, v24 ; 2C24300A exp 15, 38, 0, 0, 0, v16, v12, v15, v22 ; C400026F 160F0C10 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v12, s12, v9 ; 0A18120C v_mac_f32_e32 v12, s11, v7 ; 2C180E0B v_mac_f32_e32 v12, s0, v13 ; 2C181A00 s_buffer_load_dword s0, s[4:7], 0x3c ; C0220002 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x40 ; C0220042 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x44 ; C0220082 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x50 ; C02200C2 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x54 ; C0220202 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x58 ; C0220242 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x5c ; C0220282 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x60 ; C02202C2 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x64 ; C0220302 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x68 ; C0220342 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x6c ; C0220382 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x70 ; C02203C2 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x74 ; C0220402 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x48 ; C0220442 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x4c ; C0220482 0000004C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s0, v24 ; 2C183000 v_mul_f32_e32 v15, s2, v9 ; 0A1E1202 v_mac_f32_e32 v15, s1, v7 ; 2C1E0E01 v_mul_f32_e32 v16, s8, v9 ; 0A201208 v_mac_f32_e32 v16, s3, v7 ; 2C200E03 v_mul_f32_e32 v19, s12, v9 ; 0A26120C v_mac_f32_e32 v19, s11, v7 ; 2C260E0B v_mul_f32_e32 v9, s16, v9 ; 0A121210 s_buffer_load_dword s0, s[4:7], 0x78 ; C0220002 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x7c ; C0220042 0000007C exp 15, 39, 0, 0, 0, v10, v11, v14, v21 ; C400027F 150E0B0A exp 15, 40, 0, 0, 0, v3, v4, v0, v1 ; C400028F 01000403 exp 15, 12, 0, 0, 0, v5, v8, v2, v24 ; C40000CF 18020805 exp 15, 13, 0, 0, 0, v6, v17, v18, v12 ; C40000DF 0C121106 v_mac_f32_e32 v9, s15, v7 ; 2C120E0F v_mac_f32_e32 v15, s17, v13 ; 2C1E1A11 v_mac_f32_e32 v16, s9, v13 ; 2C201A09 v_mac_f32_e32 v19, s13, v13 ; 2C261A0D s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v9, s0, v13 ; 2C121A00 v_mac_f32_e32 v15, s18, v24 ; 2C1E3012 v_mac_f32_e32 v16, s10, v24 ; 2C20300A v_mac_f32_e32 v19, s14, v24 ; 2C26300E v_mac_f32_e32 v9, s1, v24 ; 2C123001 exp 15, 14, 0, 1, 0, v15, v16, v19, v9 ; C40008EF 0913100F s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 28 Code Size: 1636 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL IN[2], GENERIC[1], PERSPECTIVE DCL IN[3], GENERIC[2], PERSPECTIVE DCL IN[4], GENERIC[3], PERSPECTIVE DCL IN[5], GENERIC[4], PERSPECTIVE DCL IN[6], GENERIC[5], PERSPECTIVE DCL IN[7], GENERIC[6], PERSPECTIVE, CENTROID DCL IN[8], GENERIC[7], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], CUBE, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..20], LOCAL IMM[0] FLT32 { 2.0000, -1.0000, 0.8165, 0.5774} IMM[1] FLT32 { -0.4082, 0.7071, 0.5774, 1.0000} IMM[2] FLT32 { -0.4082, -0.7071, 0.5774, 0.0000} IMM[3] FLT32 { 0.2125, 0.7154, 0.0721, 0.3333} IMM[4] FLT32 { 1.0000, 0.0000, -0.5000, 0.0005} IMM[5] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[6] FLT32 { -0.0005, 0.0005, 0.0000, 0.1250} IMM[7] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[8] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: ADD TEMP[0].xyz, CONST[10].xyzz, -IN[3].xyzz 1: MOV TEMP[1].xy, IN[1].xyyy 2: TEX TEMP[1], TEMP[1], SAMP[0], 2D 3: MOV TEMP[2].xy, IN[2].xyyy 4: TEX TEMP[3], TEMP[2], SAMP[3], 2D 5: MAD TEMP[4].xyz, TEMP[3].xyzz, IMM[0].xxxx, IMM[0].yyyy 6: MOV TEMP[5].xy, IN[7].xyyy 7: TEX TEMP[5], TEMP[5], SAMP[1], 2D 8: MOV TEMP[6], TEMP[5] 9: MOV TEMP[7].xy, IN[7].wzzz 10: TEX TEMP[7], TEMP[7], SAMP[1], 2D 11: MOV TEMP[8], TEMP[7] 12: MOV TEMP[9].xy, IN[8].xyyy 13: TEX TEMP[9], TEMP[9], SAMP[1], 2D 14: MOV TEMP[10], TEMP[9] 15: MUL TEMP[2].xyz, TEMP[1].xyzz, IN[0].xyzz 16: MUL TEMP[1].x, TEMP[1].wwww, IN[0].wwww 17: MOV TEMP[1].w, TEMP[1].xxxx 18: DP2 TEMP[11].x, TEMP[4].xzzz, IMM[0].zwww 19: MOV_SAT TEMP[11].x, TEMP[11].xxxx 20: DP3 TEMP[12].x, TEMP[4].xyzz, IMM[1].xyzz 21: MOV_SAT TEMP[12].x, TEMP[12].xxxx 22: MOV TEMP[11].y, TEMP[12].xxxx 23: DP3 TEMP[12].x, TEMP[4].xyzz, IMM[2].xyzz 24: MOV_SAT TEMP[12].x, TEMP[12].xxxx 25: MOV TEMP[11].z, TEMP[12].xxxx 26: MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[11].xyzz 27: MUL TEMP[12].xyz, TEMP[7].xyzz, TEMP[11].yyyy 28: MAD TEMP[12].xyz, TEMP[11].xxxx, TEMP[5].xyzz, TEMP[12].xyzz 29: MAD TEMP[12].xyz, TEMP[11].zzzz, TEMP[9].xyzz, TEMP[12].xyzz 30: DP3 TEMP[13].x, TEMP[11].xyzz, IMM[1].wwww 31: RCP TEMP[13].x, TEMP[13].xxxx 32: MUL TEMP[11].xyz, TEMP[13].xxxx, CONST[12].xyzz 33: MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].xyzz 34: FSLT TEMP[13].x, -TEMP[5].wwww, IMM[2].wwww 35: AND TEMP[13].x, CONST[90].xxxx, TEMP[13].xxxx 36: UIF TEMP[13].xxxx :0 37: ADD TEMP[6].xyz, TEMP[5].xyzz, TEMP[7].xyzz 38: ADD TEMP[6].xyz, TEMP[9].xyzz, TEMP[6].xyzz 39: DP3 TEMP[7].x, TEMP[6].xyzz, IMM[3].xyzz 40: MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].wwww 41: RCP TEMP[7].x, TEMP[7].xxxx 42: MUL TEMP[5].x, TEMP[7].xxxx, TEMP[5].wwww 43: MAD TEMP[6], IN[3].xyzx, IMM[4].xxxy, IMM[4].yyyx 44: DP4 TEMP[8].x, TEMP[6], CONST[69] 45: DP4 TEMP[7].x, TEMP[6], CONST[70] 46: MOV TEMP[8].y, TEMP[7].xxxx 47: MOV_SAT TEMP[9].xy, TEMP[8].xyyy 48: ADD TEMP[10].xy, -TEMP[8].xyyy, TEMP[9].xyyy 49: DP2 TEMP[9].x, TEMP[10].xyyy, IMM[1].wwww 50: DP4 TEMP[10].x, TEMP[6], CONST[73] 51: DP4 TEMP[13].x, TEMP[6], CONST[74] 52: MOV TEMP[10].y, TEMP[13].xxxx 53: MOV_SAT TEMP[14].xy, TEMP[10].xyyy 54: ADD TEMP[12].xy, -TEMP[10].xyyy, TEMP[14].xyyy 55: DP2 TEMP[14].x, TEMP[12].xyyy, IMM[1].wwww 56: MOV TEMP[8].w, TEMP[14].xxxx 57: DP4 TEMP[12].x, TEMP[6], CONST[77] 58: DP4 TEMP[15].x, TEMP[6], CONST[78] 59: MOV TEMP[10].zw, IMM[4].yyxy 60: MOV TEMP[16].w, TEMP[10] 61: ABS TEMP[17].x, TEMP[14].xxxx 62: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 63: UIF TEMP[17].xxxx :0 64: MOV TEMP[17].x, TEMP[10].xxxx 65: ELSE :0 66: MOV TEMP[17].x, TEMP[12].xxxx 67: ENDIF 68: MOV TEMP[16].x, TEMP[17].xxxx 69: ABS TEMP[17].x, TEMP[14].xxxx 70: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 71: UIF TEMP[17].xxxx :0 72: MOV TEMP[13].x, TEMP[13].xxxx 73: ELSE :0 74: MOV TEMP[13].x, TEMP[15].xxxx 75: ENDIF 76: MOV TEMP[16].y, TEMP[13].xxxx 77: ABS TEMP[13].x, TEMP[14].xxxx 78: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[2].wwww 79: UIF TEMP[13].xxxx :0 80: MOV TEMP[13].x, IMM[4].xxxx 81: ELSE :0 82: MOV TEMP[13].x, IMM[0].xxxx 83: ENDIF 84: MOV TEMP[16].z, TEMP[13].xxxx 85: MOV TEMP[10], TEMP[16] 86: MOV TEMP[8].zw, IMM[2].wwww 87: MOV TEMP[16].w, TEMP[8] 88: ABS TEMP[13].x, TEMP[9].xxxx 89: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[2].wwww 90: UIF TEMP[13].xxxx :0 91: MOV TEMP[13].x, TEMP[8].xxxx 92: ELSE :0 93: MOV TEMP[13].x, TEMP[10].xxxx 94: ENDIF 95: MOV TEMP[16].x, TEMP[13].xxxx 96: ABS TEMP[13].x, TEMP[9].xxxx 97: FSGE TEMP[13].x, -TEMP[13].xxxx, IMM[2].wwww 98: UIF TEMP[13].xxxx :0 99: MOV TEMP[7].x, TEMP[7].xxxx 100: ELSE :0 101: MOV TEMP[7].x, TEMP[10].yyyy 102: ENDIF 103: MOV TEMP[16].y, TEMP[7].xxxx 104: ABS TEMP[7].x, TEMP[9].xxxx 105: FSGE TEMP[7].x, -TEMP[7].xxxx, IMM[2].wwww 106: UIF TEMP[7].xxxx :0 107: MOV TEMP[7].x, IMM[2].wwww 108: ELSE :0 109: MOV TEMP[7].x, TEMP[10].zzzz 110: ENDIF 111: MOV TEMP[16].z, TEMP[7].xxxx 112: MOV TEMP[8].zw, TEMP[16].wwzw 113: DP4 TEMP[9].x, TEMP[6], CONST[71] 114: MOV TEMP[10].z, TEMP[9].xxxx 115: ADD TEMP[12].xy, TEMP[16].xyyy, IMM[4].zzzz 116: ABS TEMP[13].xy, TEMP[12].xyyy 117: ADD TEMP[12].xy, TEMP[13].xyyy, -CONST[67].zzzz 118: MUL TEMP[12].xy, TEMP[12].xyyy, CONST[67].wwww 119: MOV_SAT TEMP[13].xy, TEMP[12].xyyy 120: ADD TEMP[12].xy, -TEMP[13].xyyy, IMM[1].wwww 121: MUL TEMP[13].x, TEMP[12].yyyy, TEMP[12].xxxx 122: MOV_SAT TEMP[14].xy, TEMP[16].xyyy 123: ADD TEMP[12].xyz, TEMP[7].xxxx, IMM[5].xyzz 124: ABS TEMP[15].x, TEMP[12].xxxx 125: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 126: UIF TEMP[15].xxxx :0 127: MOV TEMP[15].x, CONST[85].zzzz 128: ELSE :0 129: MOV TEMP[15].x, TEMP[8].wwww 130: ENDIF 131: ABS TEMP[17].x, TEMP[12].xxxx 132: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 133: UIF TEMP[17].xxxx :0 134: MOV TEMP[17].x, CONST[85].wwww 135: ELSE :0 136: MOV TEMP[17].x, TEMP[8].wwww 137: ENDIF 138: MOV TEMP[16].y, TEMP[17].xxxx 139: ABS TEMP[17].x, TEMP[12].xxxx 140: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 141: UIF TEMP[17].xxxx :0 142: MOV TEMP[17].x, CONST[85].xxxx 143: ELSE :0 144: MOV TEMP[17].x, TEMP[8].wwww 145: ENDIF 146: MOV TEMP[16].z, TEMP[17].xxxx 147: ABS TEMP[17].x, TEMP[12].xxxx 148: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 149: UIF TEMP[17].xxxx :0 150: MOV TEMP[17].x, CONST[85].yyyy 151: ELSE :0 152: MOV TEMP[17].x, TEMP[8].wwww 153: ENDIF 154: MOV TEMP[16].w, TEMP[17].xxxx 155: ABS TEMP[17].x, TEMP[12].yyyy 156: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 157: UIF TEMP[17].xxxx :0 158: MOV TEMP[17].x, CONST[86].zzzz 159: ELSE :0 160: MOV TEMP[17].x, TEMP[15].xxxx 161: ENDIF 162: MOV TEMP[16].x, TEMP[17].xxxx 163: ABS TEMP[15].x, TEMP[12].yyyy 164: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 165: UIF TEMP[15].xxxx :0 166: MOV TEMP[15].x, CONST[86].wwww 167: ELSE :0 168: MOV TEMP[15].x, TEMP[16].yyyy 169: ENDIF 170: MOV TEMP[16].y, TEMP[15].xxxx 171: ABS TEMP[15].x, TEMP[12].yyyy 172: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 173: UIF TEMP[15].xxxx :0 174: MOV TEMP[15].x, CONST[86].xxxx 175: ELSE :0 176: MOV TEMP[15].x, TEMP[16].zzzz 177: ENDIF 178: MOV TEMP[16].z, TEMP[15].xxxx 179: ABS TEMP[15].x, TEMP[12].yyyy 180: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 181: UIF TEMP[15].xxxx :0 182: MOV TEMP[15].x, CONST[86].yyyy 183: ELSE :0 184: MOV TEMP[15].x, TEMP[16].wwww 185: ENDIF 186: MOV TEMP[16].w, TEMP[15].xxxx 187: MOV TEMP[7], TEMP[16] 188: ABS TEMP[15].x, TEMP[12].zzzz 189: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 190: UIF TEMP[15].xxxx :0 191: MOV TEMP[15].x, CONST[87].zzzz 192: ELSE :0 193: MOV TEMP[15].x, TEMP[7].xxxx 194: ENDIF 195: MOV TEMP[16].x, TEMP[15].xxxx 196: ABS TEMP[15].x, TEMP[12].zzzz 197: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 198: UIF TEMP[15].xxxx :0 199: MOV TEMP[15].x, CONST[87].wwww 200: ELSE :0 201: MOV TEMP[15].x, TEMP[7].yyyy 202: ENDIF 203: MOV TEMP[16].y, TEMP[15].xxxx 204: ABS TEMP[15].x, TEMP[12].zzzz 205: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 206: UIF TEMP[15].xxxx :0 207: MOV TEMP[15].x, CONST[87].xxxx 208: ELSE :0 209: MOV TEMP[15].x, TEMP[7].zzzz 210: ENDIF 211: MOV TEMP[16].z, TEMP[15].xxxx 212: ABS TEMP[15].x, TEMP[12].zzzz 213: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 214: UIF TEMP[15].xxxx :0 215: MOV TEMP[15].x, CONST[87].yyyy 216: ELSE :0 217: MOV TEMP[15].x, TEMP[7].wwww 218: ENDIF 219: MOV TEMP[16].w, TEMP[15].xxxx 220: MAD TEMP[10].xy, TEMP[14].xyyy, TEMP[16].xyyy, TEMP[16].zwww 221: ADD TEMP[12], TEMP[10], IMM[4].wwyy 222: TXL TEMP[14].x, TEMP[12], SAMP[4], SHADOW2D 223: MOV TEMP[12].x, TEMP[14].xxxx 224: ADD TEMP[7], TEMP[10], IMM[6].xyzz 225: ADD TEMP[14], TEMP[10], IMM[6].yxzz 226: ADD TEMP[15], TEMP[10], IMM[6].xxzz 227: TXL TEMP[17].x, TEMP[7], SAMP[4], SHADOW2D 228: MOV TEMP[12].y, TEMP[17].xxxx 229: TXL TEMP[17].x, TEMP[14], SAMP[4], SHADOW2D 230: MOV TEMP[12].z, TEMP[17].xxxx 231: TXL TEMP[17].x, TEMP[15], SAMP[4], SHADOW2D 232: MOV TEMP[12].w, TEMP[17].xxxx 233: DP4 TEMP[17].x, TEMP[12], IMM[5].wwww 234: ADD TEMP[12], TEMP[10], IMM[4].wyyy 235: TXL TEMP[18].x, TEMP[12], SAMP[4], SHADOW2D 236: MOV TEMP[12].x, TEMP[18].xxxx 237: ADD TEMP[7], TEMP[10], IMM[6].xzzz 238: TXL TEMP[18], TEMP[7], SAMP[4], SHADOW2D 239: MOV TEMP[7], TEMP[18] 240: ADD TEMP[14], TEMP[10], IMM[6].zxzz 241: TXL TEMP[19], TEMP[14], SAMP[4], SHADOW2D 242: MOV TEMP[14], TEMP[19] 243: ADD TEMP[15], TEMP[10], IMM[4].ywyy 244: TXL TEMP[20], TEMP[15], SAMP[4], SHADOW2D 245: MOV TEMP[15], TEMP[20] 246: MOV TEMP[12].y, TEMP[18].xxxx 247: MOV TEMP[12].z, TEMP[19].xxxx 248: MOV TEMP[12].w, TEMP[20].xxxx 249: DP4 TEMP[18].x, TEMP[12], IMM[6].wwww 250: MOV TEMP[19].xy, TEMP[10].xyyy 251: MOV TEMP[19].z, TEMP[9].xxxx 252: MOV TEMP[19].w, TEMP[10].wwww 253: TXL TEMP[19], TEMP[19], SAMP[4], SHADOW2D 254: MOV TEMP[12].xyz, TEMP[19] 255: ADD TEMP[8].x, TEMP[18].xxxx, TEMP[17].xxxx 256: MAD TEMP[8].x, TEMP[19].xxxx, IMM[7].xxxx, TEMP[8].xxxx 257: FSLT TEMP[17].x, TEMP[13].xxxx, IMM[1].wwww 258: UIF TEMP[17].xxxx :0 259: ADD TEMP[12].xyz, TEMP[8].zzzz, IMM[7].yzww 260: ABS TEMP[17].x, TEMP[12].xxxx 261: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 262: UIF TEMP[17].xxxx :0 263: MOV TEMP[17].x, CONST[73].xxxx 264: ELSE :0 265: MOV TEMP[17].x, TEMP[8].wwww 266: ENDIF 267: MOV TEMP[16].x, TEMP[17].xxxx 268: ABS TEMP[17].x, TEMP[12].xxxx 269: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 270: UIF TEMP[17].xxxx :0 271: MOV TEMP[17].x, CONST[73].yyyy 272: ELSE :0 273: MOV TEMP[17].x, TEMP[8].wwww 274: ENDIF 275: MOV TEMP[16].y, TEMP[17].xxxx 276: ABS TEMP[17].x, TEMP[12].xxxx 277: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 278: UIF TEMP[17].xxxx :0 279: MOV TEMP[17].x, CONST[73].zzzz 280: ELSE :0 281: MOV TEMP[17].x, TEMP[8].wwww 282: ENDIF 283: MOV TEMP[16].z, TEMP[17].xxxx 284: ABS TEMP[17].x, TEMP[12].xxxx 285: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 286: UIF TEMP[17].xxxx :0 287: MOV TEMP[17].x, CONST[73].wwww 288: ELSE :0 289: MOV TEMP[17].x, TEMP[8].wwww 290: ENDIF 291: MOV TEMP[16].w, TEMP[17].xxxx 292: MOV TEMP[7], TEMP[16] 293: ABS TEMP[17].x, TEMP[12].xxxx 294: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 295: UIF TEMP[17].xxxx :0 296: MOV TEMP[17].x, CONST[74].xxxx 297: ELSE :0 298: MOV TEMP[17].x, TEMP[8].wwww 299: ENDIF 300: MOV TEMP[16].x, TEMP[17].xxxx 301: ABS TEMP[17].x, TEMP[12].xxxx 302: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 303: UIF TEMP[17].xxxx :0 304: MOV TEMP[17].x, CONST[74].yyyy 305: ELSE :0 306: MOV TEMP[17].x, TEMP[8].wwww 307: ENDIF 308: MOV TEMP[16].y, TEMP[17].xxxx 309: ABS TEMP[17].x, TEMP[12].xxxx 310: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 311: UIF TEMP[17].xxxx :0 312: MOV TEMP[17].x, CONST[74].zzzz 313: ELSE :0 314: MOV TEMP[17].x, TEMP[8].wwww 315: ENDIF 316: MOV TEMP[16].z, TEMP[17].xxxx 317: ABS TEMP[17].x, TEMP[12].xxxx 318: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 319: UIF TEMP[17].xxxx :0 320: MOV TEMP[17].x, CONST[74].wwww 321: ELSE :0 322: MOV TEMP[17].x, TEMP[8].wwww 323: ENDIF 324: MOV TEMP[16].w, TEMP[17].xxxx 325: MOV TEMP[14], TEMP[16] 326: ABS TEMP[17].x, TEMP[12].yyyy 327: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 328: UIF TEMP[17].xxxx :0 329: MOV TEMP[17].x, CONST[77].xxxx 330: ELSE :0 331: MOV TEMP[17].x, TEMP[7].xxxx 332: ENDIF 333: MOV TEMP[16].x, TEMP[17].xxxx 334: ABS TEMP[17].x, TEMP[12].yyyy 335: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 336: UIF TEMP[17].xxxx :0 337: MOV TEMP[17].x, CONST[77].yyyy 338: ELSE :0 339: MOV TEMP[17].x, TEMP[7].yyyy 340: ENDIF 341: MOV TEMP[16].y, TEMP[17].xxxx 342: ABS TEMP[17].x, TEMP[12].yyyy 343: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 344: UIF TEMP[17].xxxx :0 345: MOV TEMP[17].x, CONST[77].zzzz 346: ELSE :0 347: MOV TEMP[17].x, TEMP[7].zzzz 348: ENDIF 349: MOV TEMP[16].z, TEMP[17].xxxx 350: ABS TEMP[17].x, TEMP[12].yyyy 351: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 352: UIF TEMP[17].xxxx :0 353: MOV TEMP[17].x, CONST[77].wwww 354: ELSE :0 355: MOV TEMP[17].x, TEMP[7].wwww 356: ENDIF 357: MOV TEMP[16].w, TEMP[17].xxxx 358: MOV TEMP[7], TEMP[16] 359: ABS TEMP[17].x, TEMP[12].yyyy 360: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 361: UIF TEMP[17].xxxx :0 362: MOV TEMP[17].x, CONST[78].xxxx 363: ELSE :0 364: MOV TEMP[17].x, TEMP[14].xxxx 365: ENDIF 366: MOV TEMP[16].x, TEMP[17].xxxx 367: ABS TEMP[17].x, TEMP[12].yyyy 368: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 369: UIF TEMP[17].xxxx :0 370: MOV TEMP[17].x, CONST[78].yyyy 371: ELSE :0 372: MOV TEMP[17].x, TEMP[14].yyyy 373: ENDIF 374: MOV TEMP[16].y, TEMP[17].xxxx 375: ABS TEMP[17].x, TEMP[12].yyyy 376: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 377: UIF TEMP[17].xxxx :0 378: MOV TEMP[17].x, CONST[78].zzzz 379: ELSE :0 380: MOV TEMP[17].x, TEMP[14].zzzz 381: ENDIF 382: MOV TEMP[16].z, TEMP[17].xxxx 383: ABS TEMP[17].x, TEMP[12].yyyy 384: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 385: UIF TEMP[17].xxxx :0 386: MOV TEMP[17].x, CONST[78].wwww 387: ELSE :0 388: MOV TEMP[17].x, TEMP[14].wwww 389: ENDIF 390: MOV TEMP[16].w, TEMP[17].xxxx 391: MOV TEMP[14], TEMP[16] 392: ABS TEMP[17].x, TEMP[12].zzzz 393: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 394: UIF TEMP[17].xxxx :0 395: MOV TEMP[17].x, CONST[81].xxxx 396: ELSE :0 397: MOV TEMP[17].x, TEMP[7].xxxx 398: ENDIF 399: MOV TEMP[16].x, TEMP[17].xxxx 400: ABS TEMP[17].x, TEMP[12].zzzz 401: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 402: UIF TEMP[17].xxxx :0 403: MOV TEMP[17].x, CONST[81].yyyy 404: ELSE :0 405: MOV TEMP[17].x, TEMP[7].yyyy 406: ENDIF 407: MOV TEMP[16].y, TEMP[17].xxxx 408: ABS TEMP[17].x, TEMP[12].zzzz 409: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 410: UIF TEMP[17].xxxx :0 411: MOV TEMP[17].x, CONST[81].zzzz 412: ELSE :0 413: MOV TEMP[17].x, TEMP[7].zzzz 414: ENDIF 415: MOV TEMP[16].z, TEMP[17].xxxx 416: ABS TEMP[17].x, TEMP[12].zzzz 417: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 418: UIF TEMP[17].xxxx :0 419: MOV TEMP[17].x, CONST[81].wwww 420: ELSE :0 421: MOV TEMP[17].x, TEMP[7].wwww 422: ENDIF 423: MOV TEMP[16].w, TEMP[17].xxxx 424: MOV TEMP[7], TEMP[16] 425: ABS TEMP[17].x, TEMP[12].zzzz 426: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 427: UIF TEMP[17].xxxx :0 428: MOV TEMP[17].x, CONST[82].xxxx 429: ELSE :0 430: MOV TEMP[17].x, TEMP[14].xxxx 431: ENDIF 432: MOV TEMP[16].x, TEMP[17].xxxx 433: ABS TEMP[17].x, TEMP[12].zzzz 434: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 435: UIF TEMP[17].xxxx :0 436: MOV TEMP[17].x, CONST[82].yyyy 437: ELSE :0 438: MOV TEMP[17].x, TEMP[14].yyyy 439: ENDIF 440: MOV TEMP[16].y, TEMP[17].xxxx 441: ABS TEMP[17].x, TEMP[12].zzzz 442: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 443: UIF TEMP[17].xxxx :0 444: MOV TEMP[17].x, CONST[82].zzzz 445: ELSE :0 446: MOV TEMP[17].x, TEMP[14].zzzz 447: ENDIF 448: MOV TEMP[16].z, TEMP[17].xxxx 449: ABS TEMP[17].x, TEMP[12].zzzz 450: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 451: UIF TEMP[17].xxxx :0 452: MOV TEMP[17].x, CONST[82].wwww 453: ELSE :0 454: MOV TEMP[17].x, TEMP[14].wwww 455: ENDIF 456: MOV TEMP[16].w, TEMP[17].xxxx 457: DP4 TEMP[7].x, TEMP[6], TEMP[7] 458: MOV_SAT TEMP[7].x, TEMP[7].xxxx 459: DP4 TEMP[17].x, TEMP[6], TEMP[16] 460: MOV_SAT TEMP[17].x, TEMP[17].xxxx 461: MOV TEMP[7].y, TEMP[17].xxxx 462: ABS TEMP[17].x, TEMP[12].xxxx 463: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 464: UIF TEMP[17].xxxx :0 465: MOV TEMP[17].x, CONST[86].zzzz 466: ELSE :0 467: MOV TEMP[17].x, TEMP[8].wwww 468: ENDIF 469: ABS TEMP[18].x, TEMP[12].xxxx 470: FSGE TEMP[18].x, -TEMP[18].xxxx, IMM[2].wwww 471: UIF TEMP[18].xxxx :0 472: MOV TEMP[18].x, CONST[86].wwww 473: ELSE :0 474: MOV TEMP[18].x, TEMP[8].wwww 475: ENDIF 476: MOV TEMP[16].y, TEMP[18].xxxx 477: ABS TEMP[18].x, TEMP[12].xxxx 478: FSGE TEMP[18].x, -TEMP[18].xxxx, IMM[2].wwww 479: UIF TEMP[18].xxxx :0 480: MOV TEMP[18].x, CONST[86].xxxx 481: ELSE :0 482: MOV TEMP[18].x, TEMP[8].wwww 483: ENDIF 484: MOV TEMP[16].z, TEMP[18].xxxx 485: ABS TEMP[18].x, TEMP[12].xxxx 486: FSGE TEMP[18].x, -TEMP[18].xxxx, IMM[2].wwww 487: UIF TEMP[18].xxxx :0 488: MOV TEMP[18].x, CONST[86].yyyy 489: ELSE :0 490: MOV TEMP[18].x, TEMP[8].wwww 491: ENDIF 492: MOV TEMP[16].w, TEMP[18].xxxx 493: ABS TEMP[18].x, TEMP[12].yyyy 494: FSGE TEMP[18].x, -TEMP[18].xxxx, IMM[2].wwww 495: UIF TEMP[18].xxxx :0 496: MOV TEMP[18].x, CONST[87].zzzz 497: ELSE :0 498: MOV TEMP[18].x, TEMP[17].xxxx 499: ENDIF 500: ABS TEMP[17].x, TEMP[12].yyyy 501: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 502: UIF TEMP[17].xxxx :0 503: MOV TEMP[17].x, CONST[87].wwww 504: ELSE :0 505: MOV TEMP[17].x, TEMP[16].yyyy 506: ENDIF 507: MOV TEMP[16].y, TEMP[17].xxxx 508: ABS TEMP[17].x, TEMP[12].yyyy 509: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 510: UIF TEMP[17].xxxx :0 511: MOV TEMP[17].x, CONST[87].xxxx 512: ELSE :0 513: MOV TEMP[17].x, TEMP[16].zzzz 514: ENDIF 515: MOV TEMP[16].z, TEMP[17].xxxx 516: ABS TEMP[17].x, TEMP[12].yyyy 517: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 518: UIF TEMP[17].xxxx :0 519: MOV TEMP[17].x, CONST[87].yyyy 520: ELSE :0 521: MOV TEMP[17].x, TEMP[16].wwww 522: ENDIF 523: MOV TEMP[16].w, TEMP[17].xxxx 524: ABS TEMP[17].x, TEMP[12].zzzz 525: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 526: UIF TEMP[17].xxxx :0 527: MOV TEMP[17].x, CONST[88].zzzz 528: ELSE :0 529: MOV TEMP[17].x, TEMP[18].xxxx 530: ENDIF 531: MOV TEMP[16].x, TEMP[17].xxxx 532: ABS TEMP[17].x, TEMP[12].zzzz 533: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 534: UIF TEMP[17].xxxx :0 535: MOV TEMP[17].x, CONST[88].wwww 536: ELSE :0 537: MOV TEMP[17].x, TEMP[16].yyyy 538: ENDIF 539: MOV TEMP[16].y, TEMP[17].xxxx 540: ABS TEMP[17].x, TEMP[12].zzzz 541: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 542: UIF TEMP[17].xxxx :0 543: MOV TEMP[17].x, CONST[88].xxxx 544: ELSE :0 545: MOV TEMP[17].x, TEMP[16].zzzz 546: ENDIF 547: MOV TEMP[16].z, TEMP[17].xxxx 548: ABS TEMP[17].x, TEMP[12].zzzz 549: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[2].wwww 550: UIF TEMP[17].xxxx :0 551: MOV TEMP[17].x, CONST[88].yyyy 552: ELSE :0 553: MOV TEMP[17].x, TEMP[16].wwww 554: ENDIF 555: MOV TEMP[16].w, TEMP[17].xxxx 556: MAD TEMP[10].xy, TEMP[7].xyyy, TEMP[16].xyyy, TEMP[16].zwww 557: ADD TEMP[6], TEMP[10], IMM[4].wwyy 558: TXL TEMP[16].x, TEMP[6], SAMP[4], SHADOW2D 559: MOV TEMP[6].x, TEMP[16].xxxx 560: ADD TEMP[7], TEMP[10], IMM[6].xyzz 561: ADD TEMP[14], TEMP[10], IMM[6].yxzz 562: ADD TEMP[15], TEMP[10], IMM[6].xxzz 563: TXL TEMP[16].x, TEMP[7], SAMP[4], SHADOW2D 564: MOV TEMP[6].y, TEMP[16].xxxx 565: TXL TEMP[16].x, TEMP[14], SAMP[4], SHADOW2D 566: MOV TEMP[6].z, TEMP[16].xxxx 567: TXL TEMP[16].x, TEMP[15], SAMP[4], SHADOW2D 568: MOV TEMP[6].w, TEMP[16].xxxx 569: DP4 TEMP[16].x, TEMP[6], IMM[5].wwww 570: ADD TEMP[7], TEMP[10], IMM[4].wyyy 571: TXL TEMP[17].x, TEMP[7], SAMP[4], SHADOW2D 572: MOV TEMP[7].x, TEMP[17].xxxx 573: ADD TEMP[14], TEMP[10], IMM[6].xzzz 574: TXL TEMP[14].x, TEMP[14], SAMP[4], SHADOW2D 575: ADD TEMP[15], TEMP[10], IMM[6].zxzz 576: TXL TEMP[15].x, TEMP[15], SAMP[4], SHADOW2D 577: ADD TEMP[17], TEMP[10], IMM[4].ywyy 578: TXL TEMP[17].x, TEMP[17], SAMP[4], SHADOW2D 579: MOV TEMP[7].y, TEMP[14].xxxx 580: MOV TEMP[7].z, TEMP[15].xxxx 581: MOV TEMP[7].w, TEMP[17].xxxx 582: DP4 TEMP[7].x, TEMP[7], IMM[6].wwww 583: MOV TEMP[14].xy, TEMP[10].xyyy 584: MOV TEMP[14].z, TEMP[9].xxxx 585: MOV TEMP[14].w, TEMP[10].wwww 586: TXL TEMP[9].x, TEMP[14], SAMP[4], SHADOW2D 587: ADD TEMP[6].x, TEMP[7].xxxx, TEMP[16].xxxx 588: MAD TEMP[6].x, TEMP[9].xxxx, IMM[7].xxxx, TEMP[6].xxxx 589: FSGE TEMP[7].x, TEMP[12].zzzz, IMM[2].wwww 590: UIF TEMP[7].xxxx :0 591: MOV TEMP[7].x, IMM[1].wwww 592: ELSE :0 593: MOV TEMP[7].x, TEMP[6].xxxx 594: ENDIF 595: LRP TEMP[10].x, TEMP[13].xxxx, TEMP[8].xxxx, TEMP[7].xxxx 596: MOV TEMP[8].x, TEMP[10].xxxx 597: ENDIF 598: ADD TEMP[6].xyz, -CONST[89].xyzz, IN[3].xyzz 599: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[6].xyzz 600: MAD TEMP[7].x, TEMP[7].xxxx, CONST[68].yyyy, CONST[68].xxxx 601: MOV_SAT TEMP[7].x, TEMP[7].xxxx 602: LRP TEMP[6].x, TEMP[7].xxxx, IMM[1].wwww, TEMP[8].xxxx 603: ADD TEMP[7].x, -TEMP[6].xxxx, IMM[1].wwww 604: MAD TEMP[5].x, TEMP[5].xxxx, -TEMP[7].xxxx, IMM[1].wwww 605: MUL TEMP[6].xyz, TEMP[5].xxxx, TEMP[11].zyxx 606: MAD TEMP[5].x, TEMP[5].xxxx, IMM[8].xxxx, IMM[8].xxxx 607: LRP TEMP[11].xyz, TEMP[5].xxxx, TEMP[6].zyxx, TEMP[6].xyzz 608: ENDIF 609: DP3 TEMP[6].x, TEMP[4].xyzz, IN[4].xyzz 610: DP3 TEMP[5].x, TEMP[4].xyzz, IN[5].xyzz 611: MOV TEMP[6].y, TEMP[5].xxxx 612: DP3 TEMP[5].x, TEMP[4].xyzz, IN[6].xyzz 613: MOV TEMP[6].z, TEMP[5].xxxx 614: ADD TEMP[4].xyz, TEMP[11].xyzz, CONST[31].xyzz 615: DP3 TEMP[5].x, TEMP[6].xyzz, TEMP[0].xyzz 616: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx 617: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[6].xyzz 618: MUL TEMP[8].xyz, TEMP[0].xyzz, TEMP[7].xxxx 619: MAD TEMP[6].xyz, TEMP[5].xxxx, TEMP[6].xyzz, -TEMP[8].xyzz 620: MOV TEMP[5].xyz, TEMP[6].xyzz 621: TEX TEMP[5].xyz, TEMP[5], SAMP[2], CUBE 622: MUL TEMP[6].xyz, TEMP[5].xyzz, CONST[30].zzzz 623: MUL TEMP[6].xyz, TEMP[3].wwww, TEMP[6].xyzz 624: MUL TEMP[6].xyz, TEMP[6].xyzz, CONST[0].xyzz 625: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[6].xyzz 626: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[4].xyzz, TEMP[6].xyzz 627: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[0].xyzz 628: SQRT TEMP[0].x, TEMP[0].xxxx 629: MAD TEMP[0].x, TEMP[0].xxxx, CONST[11].wwww, CONST[11].xxxx 630: MOV_SAT TEMP[0].x, TEMP[0].xxxx 631: MIN TEMP[3].x, TEMP[0].xxxx, CONST[11].zzzz 632: MUL TEMP[0].xyz, TEMP[2].xyzz, CONST[30].xxxx 633: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx 634: MAD TEMP[2].xyz, TEMP[2].xyzz, -CONST[30].xxxx, CONST[29].xyzz 635: MAD TEMP[1].xyz, TEMP[3].xxxx, TEMP[2].xyzz, TEMP[0].xyzz 636: MOV OUT[0], TEMP[1] 637: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 488) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %85 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %86 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %87 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %88 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %102 = load <8 x i32>, <8 x i32> addrspace(2)* %101, align 32, !tbaa !0 %103 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %104 = load <4 x i32>, <4 x i32> addrspace(2)* %103, align 16, !tbaa !0 %105 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %106 = load <8 x i32>, <8 x i32> addrspace(2)* %105, align 32, !tbaa !0 %107 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %108 = load <4 x i32>, <4 x i32> addrspace(2)* %107, align 16, !tbaa !0 %109 = and i32 %5, 1 %110 = icmp ne i32 %109, 0 %111 = select i1 %110, <2 x i32> %7, <2 x i32> %8 %112 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %111) %113 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %111) %114 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %111) %115 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %111) %116 = and i32 %5, 1 %117 = icmp ne i32 %116, 0 %118 = select i1 %117, <2 x i32> %7, <2 x i32> %8 %119 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %118) %120 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %118) %121 = and i32 %5, 1 %122 = icmp ne i32 %121, 0 %123 = select i1 %122, <2 x i32> %7, <2 x i32> %8 %124 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %123) %125 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %123) %126 = and i32 %5, 1 %127 = icmp ne i32 %126, 0 %128 = select i1 %127, <2 x i32> %7, <2 x i32> %8 %129 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %128) %130 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %128) %131 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %128) %132 = and i32 %5, 1 %133 = icmp ne i32 %132, 0 %134 = select i1 %133, <2 x i32> %7, <2 x i32> %8 %135 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %134) %136 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %134) %137 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %134) %138 = and i32 %5, 1 %139 = icmp ne i32 %138, 0 %140 = select i1 %139, <2 x i32> %7, <2 x i32> %8 %141 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %6, <2 x i32> %140) %142 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %6, <2 x i32> %140) %143 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %6, <2 x i32> %140) %144 = and i32 %5, 1 %145 = icmp ne i32 %144, 0 %146 = select i1 %145, <2 x i32> %7, <2 x i32> %8 %147 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %6, <2 x i32> %146) %148 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %6, <2 x i32> %146) %149 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %6, <2 x i32> %146) %150 = and i32 %5, 1 %151 = icmp ne i32 %150, 0 %152 = select i1 %151, <2 x i32> %7, <2 x i32> %9 %153 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %6, <2 x i32> %152) %154 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %6, <2 x i32> %152) %155 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %6, <2 x i32> %152) %156 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %6, <2 x i32> %152) %157 = and i32 %5, 1 %158 = icmp ne i32 %157, 0 %159 = select i1 %158, <2 x i32> %7, <2 x i32> %9 %160 = call float @llvm.SI.fs.interp(i32 0, i32 8, i32 %6, <2 x i32> %159) %161 = call float @llvm.SI.fs.interp(i32 1, i32 8, i32 %6, <2 x i32> %159) %162 = fsub float %28, %129 %163 = fsub float %29, %130 %164 = fsub float %30, %131 %165 = bitcast float %119 to i32 %166 = bitcast float %120 to i32 %167 = insertelement <2 x i32> undef, i32 %165, i32 0 %168 = insertelement <2 x i32> %167, i32 %166, i32 1 %169 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %168, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %170 = extractelement <4 x float> %169, i32 0 %171 = extractelement <4 x float> %169, i32 1 %172 = extractelement <4 x float> %169, i32 2 %173 = extractelement <4 x float> %169, i32 3 %174 = bitcast float %124 to i32 %175 = bitcast float %125 to i32 %176 = insertelement <2 x i32> undef, i32 %174, i32 0 %177 = insertelement <2 x i32> %176, i32 %175, i32 1 %178 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %177, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %179 = extractelement <4 x float> %178, i32 0 %180 = extractelement <4 x float> %178, i32 1 %181 = extractelement <4 x float> %178, i32 2 %182 = extractelement <4 x float> %178, i32 3 %183 = fmul float %179, 2.000000e+00 %184 = fadd float %183, -1.000000e+00 %185 = fmul float %180, 2.000000e+00 %186 = fadd float %185, -1.000000e+00 %187 = fmul float %181, 2.000000e+00 %188 = fadd float %187, -1.000000e+00 %189 = bitcast float %153 to i32 %190 = bitcast float %154 to i32 %191 = insertelement <2 x i32> undef, i32 %189, i32 0 %192 = insertelement <2 x i32> %191, i32 %190, i32 1 %193 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %192, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %194 = extractelement <4 x float> %193, i32 0 %195 = extractelement <4 x float> %193, i32 1 %196 = extractelement <4 x float> %193, i32 2 %197 = extractelement <4 x float> %193, i32 3 %198 = bitcast float %156 to i32 %199 = bitcast float %155 to i32 %200 = insertelement <2 x i32> undef, i32 %198, i32 0 %201 = insertelement <2 x i32> %200, i32 %199, i32 1 %202 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %201, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %203 = extractelement <4 x float> %202, i32 0 %204 = extractelement <4 x float> %202, i32 1 %205 = extractelement <4 x float> %202, i32 2 %206 = bitcast float %160 to i32 %207 = bitcast float %161 to i32 %208 = insertelement <2 x i32> undef, i32 %206, i32 0 %209 = insertelement <2 x i32> %208, i32 %207, i32 1 %210 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %209, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %211 = extractelement <4 x float> %210, i32 0 %212 = extractelement <4 x float> %210, i32 1 %213 = extractelement <4 x float> %210, i32 2 %214 = fmul float %170, %112 %215 = fmul float %171, %113 %216 = fmul float %172, %114 %217 = fmul float %173, %115 %218 = fmul float %184, 0x3FEA20BD80000000 %219 = fmul float %188, 0x3FE279A740000000 %220 = fadd float %218, %219 %221 = call float @llvm.AMDIL.clamp.(float %220, float 0.000000e+00, float 1.000000e+00) %222 = fmul float %184, 0xBFDA20BDA0000000 %223 = fmul float %186, 0x3FE6A09E60000000 %224 = fadd float %223, %222 %225 = fmul float %188, 0x3FE279A740000000 %226 = fadd float %224, %225 %227 = call float @llvm.AMDIL.clamp.(float %226, float 0.000000e+00, float 1.000000e+00) %228 = fmul float %184, 0xBFDA20BD20000000 %229 = fmul float %186, 0xBFE6A09E80000000 %230 = fadd float %229, %228 %231 = fmul float %188, 0x3FE279A740000000 %232 = fadd float %230, %231 %233 = call float @llvm.AMDIL.clamp.(float %232, float 0.000000e+00, float 1.000000e+00) %234 = fmul float %221, %221 %235 = fmul float %227, %227 %236 = fmul float %233, %233 %237 = fmul float %203, %235 %238 = fmul float %204, %235 %239 = fmul float %205, %235 %240 = fmul float %234, %194 %241 = fadd float %240, %237 %242 = fmul float %234, %195 %243 = fadd float %242, %238 %244 = fmul float %234, %196 %245 = fadd float %244, %239 %246 = fmul float %236, %211 %247 = fadd float %246, %241 %248 = fmul float %236, %212 %249 = fadd float %248, %243 %250 = fmul float %236, %213 %251 = fadd float %250, %245 %252 = fadd float %235, %234 %253 = fadd float %252, %236 %254 = fdiv float 1.000000e+00, %253 %255 = fmul float %254, %34 %256 = fmul float %254, %35 %257 = fmul float %254, %36 %258 = fmul float %255, %247 %259 = fmul float %256, %249 %260 = fmul float %257, %251 %261 = fcmp ogt float %197, -0.000000e+00 %262 = bitcast float %88 to i32 %263 = icmp ne i32 %262, 0 %264 = and i1 %261, %263 br i1 %264, label %IF, label %ENDIF IF: ; preds = %main_body %265 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %266 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %267 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %268 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %269 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %270 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %271 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %272 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %273 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %274 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %275 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %276 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %277 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %278 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %279 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %280 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %281 = fadd float %194, %203 %282 = fadd float %195, %204 %283 = fadd float %196, %205 %284 = fadd float %211, %281 %285 = fadd float %212, %282 %286 = fadd float %213, %283 %287 = fmul float %284, 0x3FCB333340000000 %288 = fmul float %285, 0x3FE6E48E80000000 %289 = fadd float %288, %287 %290 = fmul float %286, 0x3FB2752540000000 %291 = fadd float %289, %290 %292 = fmul float %291, 0x3FD554C980000000 %293 = fdiv float 1.000000e+00, %292 %294 = fmul float %293, %197 %295 = fadd float %129, 0.000000e+00 %296 = fadd float %130, 0.000000e+00 %297 = fadd float %131, 0.000000e+00 %298 = fmul float %129, 0.000000e+00 %299 = fadd float %298, 1.000000e+00 %300 = fmul float %295, %280 %301 = fmul float %296, %279 %302 = fadd float %300, %301 %303 = fmul float %297, %278 %304 = fadd float %302, %303 %305 = fmul float %299, %277 %306 = fadd float %304, %305 %307 = fmul float %295, %276 %308 = fmul float %296, %275 %309 = fadd float %307, %308 %310 = fmul float %297, %274 %311 = fadd float %309, %310 %312 = fmul float %299, %273 %313 = fadd float %311, %312 %314 = call float @llvm.AMDIL.clamp.(float %306, float 0.000000e+00, float 1.000000e+00) %315 = call float @llvm.AMDIL.clamp.(float %313, float 0.000000e+00, float 1.000000e+00) %316 = fsub float %314, %306 %317 = fsub float %315, %313 %318 = fadd float %316, %317 %319 = fmul float %295, %49 %320 = fmul float %296, %50 %321 = fadd float %319, %320 %322 = fmul float %297, %51 %323 = fadd float %321, %322 %324 = fmul float %299, %52 %325 = fadd float %323, %324 %326 = fmul float %295, %53 %327 = fmul float %296, %54 %328 = fadd float %326, %327 %329 = fmul float %297, %55 %330 = fadd float %328, %329 %331 = fmul float %299, %56 %332 = fadd float %330, %331 %333 = call float @llvm.AMDIL.clamp.(float %325, float 0.000000e+00, float 1.000000e+00) %334 = call float @llvm.AMDIL.clamp.(float %332, float 0.000000e+00, float 1.000000e+00) %335 = fsub float %333, %325 %336 = fsub float %334, %332 %337 = fadd float %335, %336 %338 = fmul float %295, %57 %339 = fmul float %296, %58 %340 = fadd float %338, %339 %341 = fmul float %297, %59 %342 = fadd float %340, %341 %343 = fmul float %299, %60 %344 = fadd float %342, %343 %345 = fmul float %295, %61 %346 = fmul float %296, %62 %347 = fadd float %345, %346 %348 = fmul float %297, %63 %349 = fadd float %347, %348 %350 = fmul float %299, %64 %351 = fadd float %349, %350 %352 = call float @llvm.fabs.f32(float %337) %353 = fcmp ole float %352, -0.000000e+00 %. = select i1 %353, float %325, float %344 %354 = call float @llvm.fabs.f32(float %337) %355 = fcmp ole float %354, -0.000000e+00 %temp52.0 = select i1 %355, float %332, float %351 %356 = call float @llvm.fabs.f32(float %337) %357 = fcmp ole float %356, -0.000000e+00 %.252 = select i1 %357, float 1.000000e+00, float 2.000000e+00 %358 = call float @llvm.fabs.f32(float %318) %359 = fcmp ole float %358, -0.000000e+00 %temp52.2 = select i1 %359, float %306, float %. %360 = call float @llvm.fabs.f32(float %318) %361 = fcmp ole float %360, -0.000000e+00 %.temp52.0 = select i1 %361, float %313, float %temp52.0 %362 = call float @llvm.fabs.f32(float %318) %363 = fcmp ole float %362, -0.000000e+00 %temp28.1 = select i1 %363, float 0.000000e+00, float %.252 %364 = fmul float %295, %272 %365 = fmul float %296, %271 %366 = fadd float %364, %365 %367 = fmul float %297, %270 %368 = fadd float %366, %367 %369 = fmul float %299, %269 %370 = fadd float %368, %369 %371 = fadd float %temp52.2, -5.000000e-01 %372 = fadd float %.temp52.0, -5.000000e-01 %373 = call float @llvm.fabs.f32(float %371) %374 = call float @llvm.fabs.f32(float %372) %375 = fsub float %373, %45 %376 = fsub float %374, %45 %377 = fmul float %375, %46 %378 = fmul float %376, %46 %379 = call float @llvm.AMDIL.clamp.(float %377, float 0.000000e+00, float 1.000000e+00) %380 = call float @llvm.AMDIL.clamp.(float %378, float 0.000000e+00, float 1.000000e+00) %381 = fsub float 1.000000e+00, %379 %382 = fsub float 1.000000e+00, %380 %383 = fmul float %382, %381 %384 = call float @llvm.AMDIL.clamp.(float %temp52.2, float 0.000000e+00, float 1.000000e+00) %385 = call float @llvm.AMDIL.clamp.(float %.temp52.0, float 0.000000e+00, float 1.000000e+00) %386 = fadd float %temp28.1, -1.000000e+00 %387 = fadd float %temp28.1, -2.000000e+00 %388 = call float @llvm.fabs.f32(float %temp28.1) %389 = fcmp ole float %388, -0.000000e+00 %.253 = select i1 %389, float %266, float 0.000000e+00 %390 = call float @llvm.fabs.f32(float %temp28.1) %391 = fcmp ole float %390, -0.000000e+00 %temp68.1 = select i1 %391, float %265, float 0.000000e+00 %392 = call float @llvm.fabs.f32(float %temp28.1) %393 = fcmp ole float %392, -0.000000e+00 %.254 = select i1 %393, float %268, float 0.000000e+00 %394 = call float @llvm.fabs.f32(float %temp28.1) %395 = fcmp ole float %394, -0.000000e+00 %temp68.3 = select i1 %395, float %267, float 0.000000e+00 %396 = call float @llvm.fabs.f32(float %386) %397 = fcmp ole float %396, -0.000000e+00 %..253 = select i1 %397, float %75, float %.253 %398 = call float @llvm.fabs.f32(float %386) %399 = fcmp ole float %398, -0.000000e+00 %temp60.1 = select i1 %399, float %76, float %temp68.1 %400 = call float @llvm.fabs.f32(float %386) %401 = fcmp ole float %400, -0.000000e+00 %..254 = select i1 %401, float %73, float %.254 %402 = call float @llvm.fabs.f32(float %386) %403 = fcmp ole float %402, -0.000000e+00 %temp60.3 = select i1 %403, float %74, float %temp68.3 %404 = call float @llvm.fabs.f32(float %387) %405 = fcmp ole float %404, -0.000000e+00 %...253 = select i1 %405, float %79, float %..253 %406 = call float @llvm.fabs.f32(float %387) %407 = fcmp ole float %406, -0.000000e+00 %temp60.5 = select i1 %407, float %80, float %temp60.1 %408 = call float @llvm.fabs.f32(float %387) %409 = fcmp ole float %408, -0.000000e+00 %...254 = select i1 %409, float %77, float %..254 %410 = call float @llvm.fabs.f32(float %387) %411 = fcmp ole float %410, -0.000000e+00 %temp60.7 = select i1 %411, float %78, float %temp60.3 %412 = fmul float %384, %...253 %413 = fadd float %412, %...254 %414 = fmul float %385, %temp60.5 %415 = fadd float %414, %temp60.7 %416 = fadd float %413, 0x3F40000000000000 %417 = fadd float %415, 0x3F40000000000000 %418 = fadd float %370, 0.000000e+00 %419 = bitcast float %418 to i32 %420 = bitcast float %416 to i32 %421 = bitcast float %417 to i32 %422 = insertelement <4 x i32> undef, i32 %419, i32 0 %423 = insertelement <4 x i32> %422, i32 %420, i32 1 %424 = insertelement <4 x i32> %423, i32 %421, i32 2 %425 = insertelement <4 x i32> %424, i32 0, i32 3 %426 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %425, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %427 = extractelement <4 x float> %426, i32 0 %428 = fadd float %413, 0xBF40000000000000 %429 = fadd float %415, 0x3F40000000000000 %430 = fadd float %370, 0.000000e+00 %431 = fadd float %413, 0x3F40000000000000 %432 = fadd float %415, 0xBF40000000000000 %433 = fadd float %370, 0.000000e+00 %434 = fadd float %413, 0xBF40000000000000 %435 = fadd float %415, 0xBF40000000000000 %436 = fadd float %370, 0.000000e+00 %437 = bitcast float %430 to i32 %438 = bitcast float %428 to i32 %439 = bitcast float %429 to i32 %440 = insertelement <4 x i32> undef, i32 %437, i32 0 %441 = insertelement <4 x i32> %440, i32 %438, i32 1 %442 = insertelement <4 x i32> %441, i32 %439, i32 2 %443 = insertelement <4 x i32> %442, i32 0, i32 3 %444 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %443, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %445 = extractelement <4 x float> %444, i32 0 %446 = bitcast float %433 to i32 %447 = bitcast float %431 to i32 %448 = bitcast float %432 to i32 %449 = insertelement <4 x i32> undef, i32 %446, i32 0 %450 = insertelement <4 x i32> %449, i32 %447, i32 1 %451 = insertelement <4 x i32> %450, i32 %448, i32 2 %452 = insertelement <4 x i32> %451, i32 0, i32 3 %453 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %452, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %454 = extractelement <4 x float> %453, i32 0 %455 = bitcast float %436 to i32 %456 = bitcast float %434 to i32 %457 = bitcast float %435 to i32 %458 = insertelement <4 x i32> undef, i32 %455, i32 0 %459 = insertelement <4 x i32> %458, i32 %456, i32 1 %460 = insertelement <4 x i32> %459, i32 %457, i32 2 %461 = insertelement <4 x i32> %460, i32 0, i32 3 %462 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %461, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %463 = extractelement <4 x float> %462, i32 0 %464 = fmul float %427, 6.250000e-02 %465 = fmul float %445, 6.250000e-02 %466 = fadd float %464, %465 %467 = fmul float %454, 6.250000e-02 %468 = fadd float %466, %467 %469 = fmul float %463, 6.250000e-02 %470 = fadd float %468, %469 %471 = fadd float %413, 0x3F40000000000000 %472 = fadd float %415, 0.000000e+00 %473 = fadd float %370, 0.000000e+00 %474 = bitcast float %473 to i32 %475 = bitcast float %471 to i32 %476 = bitcast float %472 to i32 %477 = insertelement <4 x i32> undef, i32 %474, i32 0 %478 = insertelement <4 x i32> %477, i32 %475, i32 1 %479 = insertelement <4 x i32> %478, i32 %476, i32 2 %480 = insertelement <4 x i32> %479, i32 0, i32 3 %481 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %480, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %482 = extractelement <4 x float> %481, i32 0 %483 = fadd float %413, 0xBF40000000000000 %484 = fadd float %415, 0.000000e+00 %485 = fadd float %370, 0.000000e+00 %486 = bitcast float %485 to i32 %487 = bitcast float %483 to i32 %488 = bitcast float %484 to i32 %489 = insertelement <4 x i32> undef, i32 %486, i32 0 %490 = insertelement <4 x i32> %489, i32 %487, i32 1 %491 = insertelement <4 x i32> %490, i32 %488, i32 2 %492 = insertelement <4 x i32> %491, i32 0, i32 3 %493 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %492, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %494 = extractelement <4 x float> %493, i32 0 %495 = fadd float %413, 0.000000e+00 %496 = fadd float %415, 0xBF40000000000000 %497 = fadd float %370, 0.000000e+00 %498 = bitcast float %497 to i32 %499 = bitcast float %495 to i32 %500 = bitcast float %496 to i32 %501 = insertelement <4 x i32> undef, i32 %498, i32 0 %502 = insertelement <4 x i32> %501, i32 %499, i32 1 %503 = insertelement <4 x i32> %502, i32 %500, i32 2 %504 = insertelement <4 x i32> %503, i32 0, i32 3 %505 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %504, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %506 = extractelement <4 x float> %505, i32 0 %507 = fadd float %413, 0.000000e+00 %508 = fadd float %415, 0x3F40000000000000 %509 = fadd float %370, 0.000000e+00 %510 = bitcast float %509 to i32 %511 = bitcast float %507 to i32 %512 = bitcast float %508 to i32 %513 = insertelement <4 x i32> undef, i32 %510, i32 0 %514 = insertelement <4 x i32> %513, i32 %511, i32 1 %515 = insertelement <4 x i32> %514, i32 %512, i32 2 %516 = insertelement <4 x i32> %515, i32 0, i32 3 %517 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %516, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %518 = extractelement <4 x float> %517, i32 0 %519 = fmul float %482, 1.250000e-01 %520 = fmul float %494, 1.250000e-01 %521 = fadd float %519, %520 %522 = fmul float %506, 1.250000e-01 %523 = fadd float %521, %522 %524 = fmul float %518, 1.250000e-01 %525 = fadd float %523, %524 %526 = bitcast float %370 to i32 %527 = bitcast float %413 to i32 %528 = bitcast float %415 to i32 %529 = insertelement <4 x i32> undef, i32 %526, i32 0 %530 = insertelement <4 x i32> %529, i32 %527, i32 1 %531 = insertelement <4 x i32> %530, i32 %528, i32 2 %532 = insertelement <4 x i32> %531, i32 0, i32 3 %533 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %532, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %534 = extractelement <4 x float> %533, i32 0 %535 = fadd float %525, %470 %536 = fmul float %534, 2.500000e-01 %537 = fadd float %536, %535 %538 = fcmp olt float %383, 1.000000e+00 br i1 %538, label %IF139, label %ENDIF138 ENDIF: ; preds = %main_body, %ENDIF138 %temp44.0 = phi float [ %897, %ENDIF138 ], [ %258, %main_body ] %temp45.0 = phi float [ %901, %ENDIF138 ], [ %259, %main_body ] %temp46.0 = phi float [ %905, %ENDIF138 ], [ %260, %main_body ] %539 = fmul float %184, %135 %540 = fmul float %186, %136 %541 = fadd float %540, %539 %542 = fmul float %188, %137 %543 = fadd float %541, %542 %544 = fmul float %184, %141 %545 = fmul float %186, %142 %546 = fadd float %545, %544 %547 = fmul float %188, %143 %548 = fadd float %546, %547 %549 = fmul float %184, %147 %550 = fmul float %186, %148 %551 = fadd float %550, %549 %552 = fmul float %188, %149 %553 = fadd float %551, %552 %554 = fadd float %temp44.0, %42 %555 = fadd float %temp45.0, %43 %556 = fadd float %temp46.0, %44 %557 = fmul float %543, %162 %558 = fmul float %548, %163 %559 = fadd float %558, %557 %560 = fmul float %553, %164 %561 = fadd float %559, %560 %562 = fadd float %561, %561 %563 = fmul float %543, %543 %564 = fmul float %548, %548 %565 = fadd float %564, %563 %566 = fmul float %553, %553 %567 = fadd float %565, %566 %568 = fmul float %162, %567 %569 = fmul float %163, %567 %570 = fmul float %164, %567 %571 = fmul float %562, %543 %572 = fsub float %571, %568 %573 = fmul float %562, %548 %574 = fsub float %573, %569 %575 = fmul float %562, %553 %576 = fsub float %575, %570 %577 = insertelement <4 x float> undef, float %572, i32 0 %578 = insertelement <4 x float> %577, float %574, i32 1 %579 = insertelement <4 x float> %578, float %576, i32 2 %580 = shufflevector <4 x float> %579, <4 x float> %193, <4 x i32> %581 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %580) %582 = extractelement <4 x float> %581, i32 0 %583 = extractelement <4 x float> %581, i32 1 %584 = extractelement <4 x float> %581, i32 2 %585 = extractelement <4 x float> %581, i32 3 %586 = call float @llvm.fabs.f32(float %584) %587 = fdiv float 1.000000e+00, %586 %588 = fmul float %582, %587 %589 = fadd float %588, 1.500000e+00 %590 = fmul float %583, %587 %591 = fadd float %590, 1.500000e+00 %592 = bitcast float %591 to i32 %593 = bitcast float %589 to i32 %594 = bitcast float %585 to i32 %595 = insertelement <4 x i32> undef, i32 %592, i32 0 %596 = insertelement <4 x i32> %595, i32 %593, i32 1 %597 = insertelement <4 x i32> %596, i32 %594, i32 2 %598 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %597, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %599 = extractelement <4 x float> %598, i32 0 %600 = extractelement <4 x float> %598, i32 1 %601 = extractelement <4 x float> %598, i32 2 %602 = fmul float %599, %41 %603 = fmul float %600, %41 %604 = fmul float %601, %41 %605 = fmul float %182, %602 %606 = fmul float %182, %603 %607 = fmul float %182, %604 %608 = fmul float %605, %25 %609 = fmul float %606, %26 %610 = fmul float %607, %27 %611 = fmul float %608, %608 %612 = fmul float %609, %609 %613 = fmul float %610, %610 %614 = fmul float %214, %554 %615 = fadd float %614, %611 %616 = fmul float %215, %555 %617 = fadd float %616, %612 %618 = fmul float %216, %556 %619 = fadd float %618, %613 %620 = fmul float %162, %162 %621 = fmul float %163, %163 %622 = fadd float %621, %620 %623 = fmul float %164, %164 %624 = fadd float %622, %623 %625 = call float @llvm.sqrt.f32(float %624) %626 = fmul float %625, %33 %627 = fadd float %626, %31 %628 = call float @llvm.AMDIL.clamp.(float %627, float 0.000000e+00, float 1.000000e+00) %629 = call float @llvm.minnum.f32(float %628, float %32) %630 = fmul float %615, %40 %631 = fmul float %617, %40 %632 = fmul float %619, %40 %633 = fmul float %629, %629 %634 = fmul float %40, %615 %635 = fsub float %37, %634 %636 = fmul float %40, %617 %637 = fsub float %38, %636 %638 = fmul float %40, %619 %639 = fsub float %39, %638 %640 = fmul float %633, %635 %641 = fadd float %640, %630 %642 = fmul float %633, %637 %643 = fadd float %642, %631 %644 = fmul float %633, %639 %645 = fadd float %644, %632 %646 = call i32 @llvm.SI.packf16(float %641, float %643) %647 = bitcast i32 %646 to float %648 = call i32 @llvm.SI.packf16(float %645, float %217) %649 = bitcast i32 %648 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %647, float %649, float %647, float %649) ret void IF139: ; preds = %IF %650 = fadd float %temp28.1, 0.000000e+00 %651 = fadd float %temp28.1, -1.000000e+00 %652 = fadd float %temp28.1, -2.000000e+00 %653 = call float @llvm.fabs.f32(float %650) %654 = fcmp ole float %653, -0.000000e+00 %.255 = select i1 %654, float %49, float 0.000000e+00 %655 = call float @llvm.fabs.f32(float %650) %656 = fcmp ole float %655, -0.000000e+00 %temp68.6 = select i1 %656, float %50, float 0.000000e+00 %657 = call float @llvm.fabs.f32(float %650) %658 = fcmp ole float %657, -0.000000e+00 %.256 = select i1 %658, float %51, float 0.000000e+00 %659 = call float @llvm.fabs.f32(float %650) %660 = fcmp ole float %659, -0.000000e+00 %temp68.8 = select i1 %660, float %52, float 0.000000e+00 %661 = call float @llvm.fabs.f32(float %650) %662 = fcmp ole float %661, -0.000000e+00 %.257 = select i1 %662, float %53, float 0.000000e+00 %663 = call float @llvm.fabs.f32(float %650) %664 = fcmp ole float %663, -0.000000e+00 %temp68.10 = select i1 %664, float %54, float 0.000000e+00 %665 = call float @llvm.fabs.f32(float %650) %666 = fcmp ole float %665, -0.000000e+00 %.258 = select i1 %666, float %55, float 0.000000e+00 %667 = call float @llvm.fabs.f32(float %650) %668 = fcmp ole float %667, -0.000000e+00 %temp68.12 = select i1 %668, float %56, float 0.000000e+00 %669 = call float @llvm.fabs.f32(float %651) %670 = fcmp ole float %669, -0.000000e+00 %..255 = select i1 %670, float %57, float %.255 %671 = call float @llvm.fabs.f32(float %651) %672 = fcmp ole float %671, -0.000000e+00 %temp68.14 = select i1 %672, float %58, float %temp68.6 %673 = call float @llvm.fabs.f32(float %651) %674 = fcmp ole float %673, -0.000000e+00 %..256 = select i1 %674, float %59, float %.256 %675 = call float @llvm.fabs.f32(float %651) %676 = fcmp ole float %675, -0.000000e+00 %temp68.16 = select i1 %676, float %60, float %temp68.8 %677 = call float @llvm.fabs.f32(float %651) %678 = fcmp ole float %677, -0.000000e+00 %..257 = select i1 %678, float %61, float %.257 %679 = call float @llvm.fabs.f32(float %651) %680 = fcmp ole float %679, -0.000000e+00 %temp68.18 = select i1 %680, float %62, float %temp68.10 %681 = call float @llvm.fabs.f32(float %651) %682 = fcmp ole float %681, -0.000000e+00 %..258 = select i1 %682, float %63, float %.258 %683 = call float @llvm.fabs.f32(float %651) %684 = fcmp ole float %683, -0.000000e+00 %temp68.20 = select i1 %684, float %64, float %temp68.12 %685 = call float @llvm.fabs.f32(float %652) %686 = fcmp ole float %685, -0.000000e+00 %...255 = select i1 %686, float %65, float %..255 %687 = call float @llvm.fabs.f32(float %652) %688 = fcmp ole float %687, -0.000000e+00 %temp68.22 = select i1 %688, float %66, float %temp68.14 %689 = call float @llvm.fabs.f32(float %652) %690 = fcmp ole float %689, -0.000000e+00 %...256 = select i1 %690, float %67, float %..256 %691 = call float @llvm.fabs.f32(float %652) %692 = fcmp ole float %691, -0.000000e+00 %temp68.24 = select i1 %692, float %68, float %temp68.16 %693 = call float @llvm.fabs.f32(float %652) %694 = fcmp ole float %693, -0.000000e+00 %...257 = select i1 %694, float %69, float %..257 %695 = call float @llvm.fabs.f32(float %652) %696 = fcmp ole float %695, -0.000000e+00 %temp68.26 = select i1 %696, float %70, float %temp68.18 %697 = call float @llvm.fabs.f32(float %652) %698 = fcmp ole float %697, -0.000000e+00 %...258 = select i1 %698, float %71, float %..258 %699 = call float @llvm.fabs.f32(float %652) %700 = fcmp ole float %699, -0.000000e+00 %temp68.28 = select i1 %700, float %72, float %temp68.20 %701 = fmul float %295, %...255 %702 = fmul float %296, %temp68.22 %703 = fadd float %701, %702 %704 = fmul float %297, %...256 %705 = fadd float %703, %704 %706 = fmul float %299, %temp68.24 %707 = fadd float %705, %706 %708 = call float @llvm.AMDIL.clamp.(float %707, float 0.000000e+00, float 1.000000e+00) %709 = fmul float %295, %...257 %710 = fmul float %296, %temp68.26 %711 = fadd float %709, %710 %712 = fmul float %297, %...258 %713 = fadd float %711, %712 %714 = fmul float %299, %temp68.28 %715 = fadd float %713, %714 %716 = call float @llvm.AMDIL.clamp.(float %715, float 0.000000e+00, float 1.000000e+00) %717 = call float @llvm.fabs.f32(float %650) %718 = fcmp ole float %717, -0.000000e+00 %.259 = select i1 %718, float %75, float 0.000000e+00 %719 = call float @llvm.fabs.f32(float %650) %720 = fcmp ole float %719, -0.000000e+00 %temp72.0 = select i1 %720, float %76, float 0.000000e+00 %721 = call float @llvm.fabs.f32(float %650) %722 = fcmp ole float %721, -0.000000e+00 %.260 = select i1 %722, float %73, float 0.000000e+00 %723 = call float @llvm.fabs.f32(float %650) %724 = fcmp ole float %723, -0.000000e+00 %temp72.2 = select i1 %724, float %74, float 0.000000e+00 %725 = call float @llvm.fabs.f32(float %651) %726 = fcmp ole float %725, -0.000000e+00 %..259 = select i1 %726, float %79, float %.259 %727 = call float @llvm.fabs.f32(float %651) %728 = fcmp ole float %727, -0.000000e+00 %temp68.30 = select i1 %728, float %80, float %temp72.0 %729 = call float @llvm.fabs.f32(float %651) %730 = fcmp ole float %729, -0.000000e+00 %..260 = select i1 %730, float %77, float %.260 %731 = call float @llvm.fabs.f32(float %651) %732 = fcmp ole float %731, -0.000000e+00 %temp68.32 = select i1 %732, float %78, float %temp72.2 %733 = call float @llvm.fabs.f32(float %652) %734 = fcmp ole float %733, -0.000000e+00 %...259 = select i1 %734, float %83, float %..259 %735 = call float @llvm.fabs.f32(float %652) %736 = fcmp ole float %735, -0.000000e+00 %temp68.34 = select i1 %736, float %84, float %temp68.30 %737 = call float @llvm.fabs.f32(float %652) %738 = fcmp ole float %737, -0.000000e+00 %...260 = select i1 %738, float %81, float %..260 %739 = call float @llvm.fabs.f32(float %652) %740 = fcmp ole float %739, -0.000000e+00 %temp68.36 = select i1 %740, float %82, float %temp68.32 %741 = fmul float %708, %...259 %742 = fadd float %741, %...260 %743 = fmul float %716, %temp68.34 %744 = fadd float %743, %temp68.36 %745 = fadd float %742, 0x3F40000000000000 %746 = fadd float %744, 0x3F40000000000000 %747 = fadd float %370, 0.000000e+00 %748 = bitcast float %747 to i32 %749 = bitcast float %745 to i32 %750 = bitcast float %746 to i32 %751 = insertelement <4 x i32> undef, i32 %748, i32 0 %752 = insertelement <4 x i32> %751, i32 %749, i32 1 %753 = insertelement <4 x i32> %752, i32 %750, i32 2 %754 = insertelement <4 x i32> %753, i32 0, i32 3 %755 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %754, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %756 = extractelement <4 x float> %755, i32 0 %757 = fadd float %742, 0xBF40000000000000 %758 = fadd float %744, 0x3F40000000000000 %759 = fadd float %370, 0.000000e+00 %760 = fadd float %742, 0x3F40000000000000 %761 = fadd float %744, 0xBF40000000000000 %762 = fadd float %370, 0.000000e+00 %763 = fadd float %742, 0xBF40000000000000 %764 = fadd float %744, 0xBF40000000000000 %765 = fadd float %370, 0.000000e+00 %766 = bitcast float %759 to i32 %767 = bitcast float %757 to i32 %768 = bitcast float %758 to i32 %769 = insertelement <4 x i32> undef, i32 %766, i32 0 %770 = insertelement <4 x i32> %769, i32 %767, i32 1 %771 = insertelement <4 x i32> %770, i32 %768, i32 2 %772 = insertelement <4 x i32> %771, i32 0, i32 3 %773 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %772, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %774 = extractelement <4 x float> %773, i32 0 %775 = bitcast float %762 to i32 %776 = bitcast float %760 to i32 %777 = bitcast float %761 to i32 %778 = insertelement <4 x i32> undef, i32 %775, i32 0 %779 = insertelement <4 x i32> %778, i32 %776, i32 1 %780 = insertelement <4 x i32> %779, i32 %777, i32 2 %781 = insertelement <4 x i32> %780, i32 0, i32 3 %782 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %781, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %783 = extractelement <4 x float> %782, i32 0 %784 = bitcast float %765 to i32 %785 = bitcast float %763 to i32 %786 = bitcast float %764 to i32 %787 = insertelement <4 x i32> undef, i32 %784, i32 0 %788 = insertelement <4 x i32> %787, i32 %785, i32 1 %789 = insertelement <4 x i32> %788, i32 %786, i32 2 %790 = insertelement <4 x i32> %789, i32 0, i32 3 %791 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %790, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %792 = extractelement <4 x float> %791, i32 0 %793 = fmul float %756, 6.250000e-02 %794 = fmul float %774, 6.250000e-02 %795 = fadd float %793, %794 %796 = fmul float %783, 6.250000e-02 %797 = fadd float %795, %796 %798 = fmul float %792, 6.250000e-02 %799 = fadd float %797, %798 %800 = fadd float %742, 0x3F40000000000000 %801 = fadd float %744, 0.000000e+00 %802 = fadd float %370, 0.000000e+00 %803 = bitcast float %802 to i32 %804 = bitcast float %800 to i32 %805 = bitcast float %801 to i32 %806 = insertelement <4 x i32> undef, i32 %803, i32 0 %807 = insertelement <4 x i32> %806, i32 %804, i32 1 %808 = insertelement <4 x i32> %807, i32 %805, i32 2 %809 = insertelement <4 x i32> %808, i32 0, i32 3 %810 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %809, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %811 = extractelement <4 x float> %810, i32 0 %812 = fadd float %742, 0xBF40000000000000 %813 = fadd float %744, 0.000000e+00 %814 = fadd float %370, 0.000000e+00 %815 = bitcast float %814 to i32 %816 = bitcast float %812 to i32 %817 = bitcast float %813 to i32 %818 = insertelement <4 x i32> undef, i32 %815, i32 0 %819 = insertelement <4 x i32> %818, i32 %816, i32 1 %820 = insertelement <4 x i32> %819, i32 %817, i32 2 %821 = insertelement <4 x i32> %820, i32 0, i32 3 %822 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %821, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %823 = extractelement <4 x float> %822, i32 0 %824 = fadd float %742, 0.000000e+00 %825 = fadd float %744, 0xBF40000000000000 %826 = fadd float %370, 0.000000e+00 %827 = bitcast float %826 to i32 %828 = bitcast float %824 to i32 %829 = bitcast float %825 to i32 %830 = insertelement <4 x i32> undef, i32 %827, i32 0 %831 = insertelement <4 x i32> %830, i32 %828, i32 1 %832 = insertelement <4 x i32> %831, i32 %829, i32 2 %833 = insertelement <4 x i32> %832, i32 0, i32 3 %834 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %833, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %835 = extractelement <4 x float> %834, i32 0 %836 = fadd float %742, 0.000000e+00 %837 = fadd float %744, 0x3F40000000000000 %838 = fadd float %370, 0.000000e+00 %839 = bitcast float %838 to i32 %840 = bitcast float %836 to i32 %841 = bitcast float %837 to i32 %842 = insertelement <4 x i32> undef, i32 %839, i32 0 %843 = insertelement <4 x i32> %842, i32 %840, i32 1 %844 = insertelement <4 x i32> %843, i32 %841, i32 2 %845 = insertelement <4 x i32> %844, i32 0, i32 3 %846 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %845, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %847 = extractelement <4 x float> %846, i32 0 %848 = fmul float %811, 1.250000e-01 %849 = fmul float %823, 1.250000e-01 %850 = fadd float %848, %849 %851 = fmul float %835, 1.250000e-01 %852 = fadd float %850, %851 %853 = fmul float %847, 1.250000e-01 %854 = fadd float %852, %853 %855 = bitcast float %370 to i32 %856 = bitcast float %742 to i32 %857 = bitcast float %744 to i32 %858 = insertelement <4 x i32> undef, i32 %855, i32 0 %859 = insertelement <4 x i32> %858, i32 %856, i32 1 %860 = insertelement <4 x i32> %859, i32 %857, i32 2 %861 = insertelement <4 x i32> %860, i32 0, i32 3 %862 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %861, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %863 = extractelement <4 x float> %862, i32 0 %864 = fadd float %854, %799 %865 = fmul float %863, 2.500000e-01 %866 = fadd float %865, %864 %867 = fcmp oge float %652, 0.000000e+00 %.261 = select i1 %867, float 1.000000e+00, float %866 %868 = fsub float 1.000000e+00, %383 %869 = fmul float %537, %383 %870 = fmul float %.261, %868 %871 = fadd float %869, %870 br label %ENDIF138 ENDIF138: ; preds = %IF, %IF139 %temp32.0 = phi float [ %871, %IF139 ], [ %537, %IF ] %872 = fsub float %129, %85 %873 = fsub float %130, %86 %874 = fsub float %131, %87 %875 = fmul float %872, %872 %876 = fmul float %873, %873 %877 = fadd float %876, %875 %878 = fmul float %874, %874 %879 = fadd float %877, %878 %880 = fmul float %879, %48 %881 = fadd float %880, %47 %882 = call float @llvm.AMDIL.clamp.(float %881, float 0.000000e+00, float 1.000000e+00) %883 = fsub float 1.000000e+00, %882 %884 = fmul float %temp32.0, %883 %885 = fadd float %882, %884 %886 = fsub float 1.000000e+00, %885 %887 = fmul float %886, %294 %888 = fsub float 1.000000e+00, %887 %889 = fmul float %888, %260 %890 = fmul float %888, %259 %891 = fmul float %888, %258 %892 = fmul float %888, 5.000000e-01 %893 = fadd float %892, 5.000000e-01 %894 = fsub float 1.000000e+00, %893 %895 = fmul float %891, %893 %896 = fmul float %889, %894 %897 = fadd float %895, %896 %898 = fsub float 1.000000e+00, %893 %899 = fmul float %890, %893 %900 = fmul float %890, %898 %901 = fadd float %899, %900 %902 = fsub float 1.000000e+00, %893 %903 = fmul float %889, %893 %904 = fmul float %891, %902 %905 = fadd float %903, %904 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_and_b32 s0, 1, s9 ; 86000981 v_cmp_eq_i32_e64 vcc, 1, s0 ; D0C2006A 00000081 v_cndmask_b32_e32 v11, v2, v0 ; 00160102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v12, v3, v1 ; 00180303 v_interp_p1_f32 v2, v11, 0, 0, [m0] ; D408000B v_interp_p2_f32 v2, [v2], v12, 0, 0, [m0] ; D409000C v_interp_p1_f32 v3, v11, 1, 0, [m0] ; D40C010B v_interp_p2_f32 v3, [v3], v12, 1, 0, [m0] ; D40D010C v_interp_p1_f32 v6, v11, 2, 0, [m0] ; D418020B v_interp_p2_f32 v6, [v6], v12, 2, 0, [m0] ; D419020C v_interp_p1_f32 v7, v11, 3, 0, [m0] ; D41C030B v_interp_p2_f32 v7, [v7], v12, 3, 0, [m0] ; D41D030C v_interp_p1_f32 v13, v11, 0, 1, [m0] ; D434040B v_interp_p2_f32 v13, [v13], v12, 0, 1, [m0] ; D435040C v_interp_p1_f32 v14, v11, 1, 1, [m0] ; D438050B v_interp_p2_f32 v14, [v14], v12, 1, 1, [m0] ; D439050C v_interp_p1_f32 v28, v11, 0, 2, [m0] ; D470080B v_interp_p2_f32 v28, [v28], v12, 0, 2, [m0] ; D471080C v_interp_p1_f32 v29, v11, 1, 2, [m0] ; D474090B v_interp_p2_f32 v29, [v29], v12, 1, 2, [m0] ; D475090C v_interp_p1_f32 v9, v11, 0, 3, [m0] ; D4240C0B v_interp_p2_f32 v9, [v9], v12, 0, 3, [m0] ; D4250C0C v_interp_p1_f32 v16, v11, 1, 3, [m0] ; D4400D0B v_interp_p2_f32 v16, [v16], v12, 1, 3, [m0] ; D4410D0C v_interp_p1_f32 v18, v11, 2, 3, [m0] ; D4480E0B v_interp_p2_f32 v18, [v18], v12, 2, 3, [m0] ; D4490E0C v_interp_p1_f32 v8, v11, 0, 4, [m0] ; D420100B v_interp_p2_f32 v8, [v8], v12, 0, 4, [m0] ; D421100C v_interp_p1_f32 v10, v11, 1, 4, [m0] ; D428110B v_interp_p2_f32 v10, [v10], v12, 1, 4, [m0] ; D429110C v_interp_p1_f32 v15, v11, 2, 4, [m0] ; D43C120B v_interp_p2_f32 v15, [v15], v12, 2, 4, [m0] ; D43D120C v_interp_p1_f32 v17, v11, 0, 5, [m0] ; D444140B v_interp_p2_f32 v17, [v17], v12, 0, 5, [m0] ; D445140C v_interp_p1_f32 v19, v11, 1, 5, [m0] ; D44C150B v_interp_p2_f32 v19, [v19], v12, 1, 5, [m0] ; D44D150C v_interp_p1_f32 v20, v11, 2, 5, [m0] ; D450160B v_interp_p2_f32 v20, [v20], v12, 2, 5, [m0] ; D451160C v_interp_p1_f32 v21, v11, 0, 6, [m0] ; D454180B v_interp_p2_f32 v21, [v21], v12, 0, 6, [m0] ; D455180C v_interp_p1_f32 v22, v11, 1, 6, [m0] ; D458190B v_interp_p2_f32 v22, [v22], v12, 1, 6, [m0] ; D459190C v_interp_p1_f32 v23, v11, 2, 6, [m0] ; D45C1A0B v_interp_p2_f32 v23, [v23], v12, 2, 6, [m0] ; D45D1A0C s_load_dwordx8 s[24:31], s[6:7], 0x60 ; C00E0603 00000060 s_nop 0 ; BF800000 s_load_dwordx4 s[12:15], s[4:5], 0x0 ; C00A0302 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[4:5], 0x30 ; C00A0802 00000030 v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v30, v0, 0, 7, [m0] ; D4781C00 v_interp_p2_f32 v30, [v30], v1, 0, 7, [m0] ; D4791C01 v_interp_p1_f32 v31, v0, 1, 7, [m0] ; D47C1D00 v_interp_p2_f32 v31, [v31], v1, 1, 7, [m0] ; D47D1D01 s_load_dwordx8 s[36:43], s[6:7], 0x0 ; C00E0903 00000000 v_interp_p1_f32 v33, v0, 2, 7, [m0] ; D4841E00 v_interp_p2_f32 v33, [v33], v1, 2, 7, [m0] ; D4851E01 v_interp_p1_f32 v32, v0, 3, 7, [m0] ; D4801F00 v_interp_p2_f32 v32, [v32], v1, 3, 7, [m0] ; D4811F01 v_interp_p1_f32 v35, v0, 0, 8, [m0] ; D48C2000 v_interp_p2_f32 v35, [v35], v1, 0, 8, [m0] ; D48D2001 v_interp_p1_f32 v36, v0, 1, 8, [m0] ; D4902100 v_interp_p2_f32 v36, [v36], v1, 1, 8, [m0] ; D4912101 s_load_dwordx8 s[16:23], s[6:7], 0x20 ; C00E0403 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[8:11], s[4:5], 0x10 ; C00A0202 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[24:27], 15, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[36:43], s[12:15] ; F0800F00 0069180D s_nop 0 ; BF800000 image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[28:29], s[24:31], s[32:35] ; F0800F00 01060B1C s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v0, v11, v11 ; 0200170B v_mov_b32_e32 v1, 0x3ed105ed ; 7E0202FF 3ED105ED v_madmk_f32_e32 v4, v0, v1, 0xbed105ed ; 2E080300 BED105ED v_mov_b32_e32 v1, 0x3ed105e9 ; 7E0202FF 3ED105E9 v_madmk_f32_e32 v5, v0, v1, 0xbed105e9 ; 2E0A0300 BED105E9 v_add_f32_e32 v0, v13, v13 ; 02001B0D v_mov_b32_e32 v28, 0x3f13cd3a ; 7E3802FF 3F13CD3A v_madak_f32_e32 v29, v0, v28, 0xbf13cd3a ; 303A3900 BF13CD3A v_mad_f32 v1, 2.0, v12, -1.0 ; D1C10001 03CE18F4 v_madmk_f32_e32 v12, v1, v4, 0x3f3504f3 ; 2E180901 3F3504F3 v_mad_f32 v0, 2.0, v13, -1.0 ; D1C10000 03CE1AF4 v_mac_f32_e32 v12, v28, v0 ; 2C18011C v_madmk_f32_e32 v5, v1, v5, 0xbf3504f4 ; 2E0A0B01 BF3504F4 v_mac_f32_e32 v5, v28, v0 ; 2C0A011C s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 v_mad_f32 v4, 2.0, v11, -1.0 ; D1C10004 03CE16F4 v_madmk_f32_e32 v11, v4, v29, 0x3f5105ec ; 2E163B04 3F5105EC v_add_f32_e64 v11, 0, v11 clamp ; D101800B 00021680 v_add_f32_e64 v12, 0, v12 clamp ; D101800C 00021880 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 v_mul_f32_e32 v11, v11, v11 ; 0A16170B image_sample v[28:31], 15, 0, 0, 0, 0, 0, 0, 0, v[30:31], s[16:23], s[8:11] ; F0800F00 00441C1E s_nop 0 ; BF800000 image_sample v[32:34], 7, 0, 0, 0, 0, 0, 0, 0, v[32:33], s[16:23], s[8:11] ; F0800700 00442020 v_mul_f32_e32 v13, v12, v12 ; 0A1A190C s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v38, v13, v32 ; 0A4C410D v_mul_f32_e32 v39, v13, v33 ; 0A4E430D v_mul_f32_e32 v13, v13, v34 ; 0A1A450D v_mac_f32_e32 v38, v28, v11 ; 2C4C171C v_mac_f32_e32 v39, v29, v11 ; 2C4E171D v_mac_f32_e32 v13, v30, v11 ; 2C1A171E image_sample v[35:37], 7, 0, 0, 0, 0, 0, 0, 0, v[35:36], s[16:23], s[8:11] ; F0800700 00442323 v_mul_f32_e32 v40, v5, v5 ; 0A500B05 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v38, v35, v40 ; 2C4C5123 v_mac_f32_e32 v39, v36, v40 ; 2C4E5124 v_mac_f32_e32 v13, v37, v40 ; 2C1A5125 v_mac_f32_e32 v11, v12, v12 ; 2C16190C v_mac_f32_e32 v11, v5, v5 ; 2C160B05 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[12:15], 0xc0 ; C0220006 000000C0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0xc4 ; C0220046 000000C4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0xc8 ; C0220086 000000C8 v_rcp_f32_e32 v5, v11 ; 7E0A450B s_buffer_load_dword s11, s[12:15], 0xa0 ; C02202C6 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[12:15], 0xa4 ; C0220286 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[12:15], 0xa8 ; C0220246 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0xbc ; C0220486 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x5a0 ; C02200C6 000005A0 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v11, s0, v5 ; 0A160A00 v_mul_f32_e32 v12, v38, v11 ; 0A181726 v_mul_f32_e32 v11, s1, v5 ; 0A160A01 v_mul_f32_e32 v11, v39, v11 ; 0A161727 v_mul_f32_e32 v5, s2, v5 ; 0A0A0A02 v_mul_f32_e32 v5, v13, v5 ; 0A0A0B0D v_mov_b32_e32 v13, 0x80000000 ; 7E1A02FF 80000000 v_cmp_lt_f32_e32 vcc, v13, v31 ; 7C823F0D v_cmp_ne_i32_e64 s[0:1], 0, s3 ; D0C50000 00000680 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[16:17], s[0:1] ; BE902000 s_xor_b64 s[16:17], exec, s[16:17] ; 8890107E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x440 ; C02204C6 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4a0 ; C02205C6 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4a4 ; C0220606 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4a8 ; C0220646 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x4ac ; C0220686 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d0 ; C02206C6 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x4d4 ; C0220706 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x4d8 ; C0220786 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x4dc ; C0220806 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4e0 ; C0220886 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x4e4 ; C0220906 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x4e8 ; C0220946 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x4ec ; C0220986 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s47, s[12:15], 0x550 ; C0220BC6 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x554 ; C0220F06 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x558 ; C0220F46 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x570 ; C0220A06 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x574 ; C0220A86 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s44, s[12:15], 0x578 ; C0220B06 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s46, s[12:15], 0x57c ; C0220B86 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x590 ; C0220586 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x594 ; C0220546 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x598 ; C0220506 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[48:55], s[6:7], 0x80 ; C00E0C03 00000080 s_nop 0 ; BF800000 s_load_dwordx4 s[56:59], s[4:5], 0x40 ; C00A0E02 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x55c ; C0220F86 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x560 ; C02209C6 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x564 ; C0220A46 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x568 ; C0220AC6 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s45, s[12:15], 0x56c ; C0220B46 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x47c ; C0220FC6 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x490 ; C0220746 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x494 ; C02207C6 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x498 ; C0220846 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x49c ; C02208C6 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x468 ; C0221006 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x46c ; C0221046 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x470 ; C0221086 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x474 ; C02210C6 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x478 ; C0221106 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x454 ; C0221146 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x458 ; C0221186 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s71, s[12:15], 0x45c ; C02211C6 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s72, s[12:15], 0x460 ; C0221206 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s73, s[12:15], 0x464 ; C0221246 00000464 v_add_f32_e32 v42, 0, v16 ; 02542080 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v38, s69, v42 ; 0A4C5445 v_add_f32_e32 v44, 0, v9 ; 02581280 v_add_f32_e32 v43, 0, v18 ; 02562480 v_mad_f32 v13, 0, v9, 1.0 ; D1C1000D 03CA1280 v_mac_f32_e32 v38, s3, v44 ; 2C4C5803 v_mac_f32_e32 v38, s70, v43 ; 2C4C5646 v_mac_f32_e32 v38, s71, v13 ; 2C4C1A47 v_mul_f32_e32 v39, s73, v42 ; 0A4E5449 v_mac_f32_e32 v39, s72, v44 ; 2C4E5848 v_mac_f32_e32 v39, s64, v43 ; 2C4E5640 v_mac_f32_e32 v39, s65, v13 ; 2C4E1A41 v_add_f32_e64 v40, 0, v38 clamp ; D1018028 00024C80 v_add_f32_e64 v41, 0, v39 clamp ; D1018029 00024E80 v_subrev_f32_e32 v40, v38, v40 ; 06505126 v_subrev_f32_e32 v41, v39, v41 ; 06525327 v_add_f32_e32 v40, v41, v40 ; 02505129 v_mul_f32_e32 v41, s31, v42 ; 0A52541F v_mac_f32_e32 v41, s29, v44 ; 2C52581D v_mac_f32_e32 v41, s33, v43 ; 2C525621 v_mac_f32_e32 v41, s35, v13 ; 2C521A23 v_mul_f32_e32 v45, s24, v42 ; 0A5A5418 v_mac_f32_e32 v45, s23, v44 ; 2C5A5817 v_mac_f32_e32 v45, s25, v43 ; 2C5A5619 v_mac_f32_e32 v45, s26, v13 ; 2C5A1A1A v_add_f32_e64 v46, 0, v41 clamp ; D101802E 00025280 v_add_f32_e64 v47, 0, v45 clamp ; D101802F 00025A80 v_subrev_f32_e32 v46, v41, v46 ; 065C5D29 v_subrev_f32_e32 v47, v45, v47 ; 065E5F2D v_add_f32_e32 v46, v47, v46 ; 025C5D2F v_mul_f32_e32 v47, s28, v42 ; 0A5E541C v_mac_f32_e32 v47, s27, v44 ; 2C5E581B v_mac_f32_e32 v47, s30, v43 ; 2C5E561E v_mac_f32_e32 v47, s32, v13 ; 2C5E1A20 v_mul_f32_e32 v48, s36, v42 ; 0A605424 v_mac_f32_e32 v48, s34, v44 ; 2C605822 v_mac_f32_e32 v48, s37, v43 ; 2C605625 v_mac_f32_e32 v48, s38, v13 ; 2C601A26 v_mov_b32_e32 v49, 0x80000000 ; 7E6202FF 80000000 v_cmp_le_f32_e64 vcc, |v46|, v49 ; D043016A 0002632E v_cndmask_b32_e32 v41, v47, v41 ; 0052532F v_cndmask_b32_e32 v45, v48, v45 ; 005A5B30 v_cndmask_b32_e64 v46, 2.0, 1.0, vcc ; D100002E 01A9E4F4 v_cmp_le_f32_e64 vcc, |v40|, v49 ; D043016A 00026328 v_cndmask_b32_e32 v41, v41, v38 ; 00524D29 v_cndmask_b32_e32 v45, v45, v39 ; 005A4F2D v_cndmask_b32_e64 v48, v46, 0, vcc ; D1000030 01A9012E v_mul_f32_e32 v38, s67, v42 ; 0A4C5443 v_mac_f32_e32 v38, s66, v44 ; 2C4C5842 v_mac_f32_e32 v38, s68, v43 ; 2C4C5644 v_mac_f32_e32 v38, s63, v13 ; 2C4C1A3F v_add_f32_e64 v46, 0, v41 clamp ; D101802E 00025280 v_add_f32_e64 v47, 0, v45 clamp ; D101802F 00025A80 v_add_f32_e32 v39, -1.0, v48 ; 024E60F3 v_add_f32_e32 v40, -2.0, v48 ; 025060F5 v_cmp_le_f32_e64 vcc, |v48|, v49 ; D043016A 00026330 v_mov_b32_e32 v50, s61 ; 7E64023D v_cndmask_b32_e32 v50, 0, v50 ; 00646480 v_mov_b32_e32 v51, s62 ; 7E66023E v_cndmask_b32_e32 v51, 0, v51 ; 00666680 v_mov_b32_e32 v52, s47 ; 7E68022F v_cndmask_b32_e32 v52, 0, v52 ; 00686880 v_mov_b32_e32 v53, s60 ; 7E6A023C v_cndmask_b32_e32 v53, 0, v53 ; 006A6A80 v_cmp_le_f32_e64 vcc, |v39|, v49 ; D043016A 00026327 v_mov_b32_e32 v39, s43 ; 7E4E022B v_cndmask_b32_e32 v39, v50, v39 ; 004E4F32 v_mov_b32_e32 v50, s45 ; 7E64022D v_cndmask_b32_e32 v50, v51, v50 ; 00646533 v_mov_b32_e32 v51, s39 ; 7E660227 v_cndmask_b32_e32 v51, v52, v51 ; 00666734 v_mov_b32_e32 v52, s41 ; 7E680229 v_cndmask_b32_e32 v52, v53, v52 ; 00686935 v_cmp_le_f32_e64 vcc, |v40|, v49 ; D043016A 00026328 v_mov_b32_e32 v40, s44 ; 7E50022C v_cndmask_b32_e32 v49, v39, v40 ; 00625127 v_mov_b32_e32 v39, s46 ; 7E4E022E v_cndmask_b32_e32 v50, v50, v39 ; 00644F32 v_mov_b32_e32 v39, s40 ; 7E4E0228 v_cndmask_b32_e32 v39, v51, v39 ; 004E4F33 v_mov_b32_e32 v40, s42 ; 7E50022A v_cndmask_b32_e32 v40, v52, v40 ; 00505134 v_mac_f32_e32 v39, v49, v46 ; 2C4E5D31 v_mac_f32_e32 v40, v50, v47 ; 2C505F32 v_mov_b32_e32 v46, 0x3a000000 ; 7E5C02FF 3A000000 v_add_f32_e32 v50, v46, v39 ; 02644F2E v_add_f32_e32 v51, v46, v40 ; 0266512E v_add_f32_e32 v49, 0, v38 ; 02624C80 s_mov_b32 s47, 0 ; BEAF0080 v_mov_b32_e32 v52, s47 ; 7E68022F v_mov_b32_e32 v46, 0xba000000 ; 7E5C02FF BA000000 v_add_f32_e32 v47, v46, v39 ; 025E4F2E v_mov_b32_e32 v53, v49 ; 7E6A0331 v_mov_b32_e32 v54, v50 ; 7E6C0332 v_mov_b32_e32 v55, v51 ; 7E6E0333 v_mov_b32_e32 v56, v52 ; 7E700334 v_add_f32_e32 v46, v46, v40 ; 025C512E v_mov_b32_e32 v54, v47 ; 7E6C032F v_mov_b32_e32 v57, v49 ; 7E720331 v_mov_b32_e32 v58, v50 ; 7E740332 v_mov_b32_e32 v59, v51 ; 7E760333 v_mov_b32_e32 v60, v52 ; 7E780334 v_mov_b32_e32 v55, v51 ; 7E6E0333 v_mov_b32_e32 v59, v46 ; 7E76032E v_mov_b32_e32 v56, s47 ; 7E70022F v_mov_b32_e32 v60, s47 ; 7E78022F image_sample_c_l v47, 1, 0, 0, 0, 0, 0, 0, 0, v[49:52], s[48:55], s[56:59] ; F0B00100 01CC2F31 s_nop 0 ; BF800000 image_sample_c_l v61, 1, 0, 0, 0, 0, 0, 0, 0, v[53:56], s[48:55], s[56:59] ; F0B00100 01CC3D35 v_mov_b32_e32 v55, v46 ; 7E6E032E image_sample_c_l v57, 1, 0, 0, 0, 0, 0, 0, 0, v[57:60], s[48:55], s[56:59] ; F0B00100 01CC3939 v_mov_b32_e32 v56, s47 ; 7E70022F image_sample_c_l v58, 1, 0, 0, 0, 0, 0, 0, 0, v[53:56], s[48:55], s[56:59] ; F0B00100 01CC3A35 v_add_f32_e32 v55, 0, v40 ; 026E5080 v_mov_b32_e32 v62, v49 ; 7E7C0331 v_mov_b32_e32 v63, v50 ; 7E7E0332 v_mov_b32_e32 v64, v51 ; 7E800333 v_mov_b32_e32 v65, v52 ; 7E820334 v_mov_b32_e32 v64, v55 ; 7E800337 v_add_f32_e32 v50, 0, v39 ; 02644E80 v_mov_b32_e32 v65, s47 ; 7E82022F v_mov_b32_e32 v66, v49 ; 7E840331 v_mov_b32_e32 v67, v50 ; 7E860332 v_mov_b32_e32 v68, v51 ; 7E880333 v_mov_b32_e32 v69, v52 ; 7E8A0334 image_sample_c_l v59, 1, 0, 0, 0, 0, 0, 0, 0, v[62:65], s[48:55], s[56:59] ; F0B00100 01CC3B3E v_mov_b32_e32 v68, v46 ; 7E88032E v_mov_b32_e32 v56, s47 ; 7E70022F image_sample_c_l v46, 1, 0, 0, 0, 0, 0, 0, 0, v[53:56], s[48:55], s[56:59] ; F0B00100 01CC2E35 v_mov_b32_e32 v69, s47 ; 7E8A022F image_sample_c_l v53, 1, 0, 0, 0, 0, 0, 0, 0, v[66:69], s[48:55], s[56:59] ; F0B00100 01CC3542 v_mov_b32_e32 v52, s47 ; 7E68022F image_sample_c_l v49, 1, 0, 0, 0, 0, 0, 0, 0, v[49:52], s[48:55], s[56:59] ; F0B00100 01CC3131 v_mov_b32_e32 v50, 0x3d800000 ; 7E6402FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v51, v50, v61 ; 0A667B32 v_mac_f32_e32 v51, v50, v47 ; 2C665F32 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v51, v50, v57 ; 2C667332 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v51, v50, v58 ; 2C667532 v_mov_b32_e32 v47, 0x3e000000 ; 7E5E02FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v46, v47, v46 ; 0A5C5D2F v_mac_f32_e32 v46, v47, v59 ; 2C5C772F s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v46, v47, v53 ; 2C5C6B2F s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v46, v47, v49 ; 2C5C632F v_add_f32_e32 v41, -0.5, v41 ; 025252F1 v_add_f32_e32 v45, -0.5, v45 ; 025A5AF1 v_sub_f32_e64 v41, |v41|, s1 ; D1020129 00000329 v_sub_f32_e64 v45, |v45|, s1 ; D102012D 0000032D v_mul_f32_e32 v41, s2, v41 ; 0A525202 v_mul_f32_e32 v45, s2, v45 ; 0A5A5A02 v_add_f32_e64 v41, 0, v41 clamp ; D1018029 00025280 v_add_f32_e64 v45, 0, v45 clamp ; D101802D 00025A80 v_sub_f32_e32 v41, 1.0, v41 ; 045252F2 v_mad_f32 v47, -v45, v41, v41 ; D1C1002F 24A6532D v_mov_b32_e32 v41, 0 ; 7E520280 v_add_f32_e32 v45, v51, v46 ; 025A5D33 image_sample_c_l v39, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[48:55], s[56:59] ; F0B00100 01CC2726 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v45, v39, v45, 0x3e800000 ; 2E5A5B27 3E800000 v_mov_b32_e32 v46, s0 ; 7E5C0200 v_cmp_gt_f32_e32 vcc, 1.0, v47 ; 7C885EF2 s_and_saveexec_b64 s[60:61], vcc ; BEBC206A s_xor_b64 s[60:61], exec, s[60:61] ; 88BC3C7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s62, s[12:15], 0x510 ; C0220F86 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x514 ; C0220FC6 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x518 ; C0221006 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x51c ; C0221046 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x520 ; C0221086 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x524 ; C02210C6 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x528 ; C0221106 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x52c ; C0221146 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x580 ; C0221186 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s71, s[12:15], 0x584 ; C02211C6 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s72, s[12:15], 0x588 ; C0221206 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s73, s[12:15], 0x58c ; C0221246 0000058C v_mov_b32_e32 v39, s29 ; 7E4E021D v_mov_b32_e32 v40, s31 ; 7E50021F v_mov_b32_e32 v41, s33 ; 7E520221 v_mov_b32_e32 v49, s35 ; 7E620223 v_mov_b32_e32 v50, s23 ; 7E640217 v_mov_b32_e32 v51, s24 ; 7E660218 v_mov_b32_e32 v52, s25 ; 7E680219 v_mov_b32_e32 v53, s26 ; 7E6A021A v_mov_b32_e32 v54, s27 ; 7E6C021B v_mov_b32_e32 v55, s28 ; 7E6E021C v_mov_b32_e32 v56, s30 ; 7E70021E v_add_f32_e32 v57, 0, v48 ; 02726080 v_mov_b32_e32 v58, 0x80000000 ; 7E7402FF 80000000 v_cmp_le_f32_e64 vcc, |v57|, v58 ; D043016A 00027539 v_add_f32_e32 v57, -1.0, v48 ; 027260F3 v_cmp_le_f32_e64 s[0:1], |v57|, v58 ; D0430100 00027539 v_mov_b32_e32 v57, s32 ; 7E720220 v_cndmask_b32_e32 v39, 0, v39 ; 004E4E80 v_cndmask_b32_e64 v39, v39, v54, s[0:1] ; D1000027 00026D27 v_mov_b32_e32 v54, s34 ; 7E6C0222 v_cndmask_b32_e32 v40, 0, v40 ; 00505080 v_cndmask_b32_e64 v40, v40, v55, s[0:1] ; D1000028 00026F28 v_mov_b32_e32 v55, s36 ; 7E6E0224 v_cndmask_b32_e32 v41, 0, v41 ; 00525280 v_cndmask_b32_e64 v41, v41, v56, s[0:1] ; D1000029 00027129 v_mov_b32_e32 v56, s37 ; 7E700225 v_cndmask_b32_e32 v49, 0, v49 ; 00626280 v_cndmask_b32_e64 v49, v49, v57, s[0:1] ; D1000031 00027331 v_mov_b32_e32 v57, s38 ; 7E720226 v_cndmask_b32_e32 v50, 0, v50 ; 00646480 v_cndmask_b32_e64 v50, v50, v54, s[0:1] ; D1000032 00026D32 v_mov_b32_e32 v54, s39 ; 7E6C0227 v_cndmask_b32_e32 v51, 0, v51 ; 00666680 v_cndmask_b32_e64 v51, v51, v55, s[0:1] ; D1000033 00026F33 v_mov_b32_e32 v55, s41 ; 7E6E0229 v_cndmask_b32_e32 v52, 0, v52 ; 00686880 v_cndmask_b32_e64 v52, v52, v56, s[0:1] ; D1000034 00027134 v_mov_b32_e32 v56, s43 ; 7E70022B v_cndmask_b32_e32 v53, 0, v53 ; 006A6A80 v_cndmask_b32_e64 v53, v53, v57, s[0:1] ; D1000035 00027335 v_mov_b32_e32 v57, s45 ; 7E72022D v_add_f32_e32 v48, -2.0, v48 ; 026060F5 v_cmp_le_f32_e64 s[2:3], |v48|, v58 ; D0430102 00027530 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v58, s62 ; 7E74023E v_cndmask_b32_e64 v39, v39, v58, s[2:3] ; D1000027 000A7527 v_mov_b32_e32 v58, s63 ; 7E74023F v_cndmask_b32_e64 v40, v40, v58, s[2:3] ; D1000028 000A7528 v_mov_b32_e32 v58, s64 ; 7E740240 v_cndmask_b32_e64 v41, v41, v58, s[2:3] ; D1000029 000A7529 v_mov_b32_e32 v58, s65 ; 7E740241 v_cndmask_b32_e64 v49, v49, v58, s[2:3] ; D1000031 000A7531 v_mov_b32_e32 v58, s66 ; 7E740242 v_cndmask_b32_e64 v50, v50, v58, s[2:3] ; D1000032 000A7532 v_mov_b32_e32 v58, s67 ; 7E740243 v_cndmask_b32_e64 v51, v51, v58, s[2:3] ; D1000033 000A7533 v_mov_b32_e32 v58, s68 ; 7E740244 v_cndmask_b32_e64 v52, v52, v58, s[2:3] ; D1000034 000A7534 v_mov_b32_e32 v58, s69 ; 7E740245 v_cndmask_b32_e64 v53, v53, v58, s[2:3] ; D1000035 000A7535 v_mov_b32_e32 v58, s40 ; 7E740228 v_mul_f32_e32 v40, v40, v42 ; 0A505528 v_mac_f32_e32 v40, v39, v44 ; 2C505927 v_mov_b32_e32 v39, s42 ; 7E4E022A v_mac_f32_e32 v40, v41, v43 ; 2C505729 v_mov_b32_e32 v41, s44 ; 7E52022C v_mac_f32_e32 v40, v49, v13 ; 2C501B31 v_mov_b32_e32 v49, s46 ; 7E62022E v_add_f32_e64 v59, 0, v40 clamp ; D101803B 00025080 v_mul_f32_e32 v40, v51, v42 ; 0A505533 v_mac_f32_e32 v40, v50, v44 ; 2C505932 v_mac_f32_e32 v40, v52, v43 ; 2C505734 v_mac_f32_e32 v40, v53, v13 ; 2C501B35 v_add_f32_e64 v13, 0, v40 clamp ; D101800D 00025080 v_cndmask_b32_e32 v40, 0, v56 ; 00507080 v_cndmask_b32_e32 v42, 0, v57 ; 00547280 v_cndmask_b32_e32 v43, 0, v54 ; 00566C80 v_cndmask_b32_e32 v44, 0, v55 ; 00586E80 v_cndmask_b32_e64 v40, v40, v41, s[0:1] ; D1000028 00025328 v_cndmask_b32_e64 v41, v42, v49, s[0:1] ; D1000029 0002632A v_cndmask_b32_e64 v42, v43, v58, s[0:1] ; D100002A 0002752B v_cndmask_b32_e64 v43, v44, v39, s[0:1] ; D100002B 00024F2C v_mov_b32_e32 v39, s72 ; 7E4E0248 v_cndmask_b32_e64 v44, v40, v39, s[2:3] ; D100002C 000A4F28 v_mov_b32_e32 v39, s73 ; 7E4E0249 v_cndmask_b32_e64 v41, v41, v39, s[2:3] ; D1000029 000A4F29 v_mov_b32_e32 v39, s70 ; 7E4E0246 v_cndmask_b32_e64 v39, v42, v39, s[2:3] ; D1000027 000A4F2A v_mov_b32_e32 v40, s71 ; 7E500247 v_cndmask_b32_e64 v40, v43, v40, s[2:3] ; D1000028 000A512B v_mac_f32_e32 v39, v44, v59 ; 2C4E772C v_mac_f32_e32 v40, v41, v13 ; 2C501B29 v_mov_b32_e32 v13, 0x3a000000 ; 7E1A02FF 3A000000 v_add_f32_e32 v42, v13, v39 ; 02544F0D v_add_f32_e32 v43, v13, v40 ; 0256510D v_add_f32_e32 v41, 0, v38 ; 02524C80 v_mov_b32_e32 v44, s47 ; 7E58022F v_mov_b32_e32 v13, 0xba000000 ; 7E1A02FF BA000000 v_add_f32_e32 v49, v13, v39 ; 02624F0D v_mov_b32_e32 v50, v41 ; 7E640329 v_mov_b32_e32 v51, v42 ; 7E66032A v_mov_b32_e32 v52, v43 ; 7E68032B v_mov_b32_e32 v53, v44 ; 7E6A032C v_mov_b32_e32 v51, v49 ; 7E660331 v_add_f32_e32 v13, v13, v40 ; 021A510D v_mov_b32_e32 v52, v43 ; 7E68032B v_mov_b32_e32 v54, v41 ; 7E6C0329 v_mov_b32_e32 v55, v42 ; 7E6E032A v_mov_b32_e32 v56, v43 ; 7E70032B v_mov_b32_e32 v57, v44 ; 7E72032C image_sample_c_l v49, 1, 0, 0, 0, 0, 0, 0, 0, v[41:44], s[48:55], s[56:59] ; F0B00100 01CC3129 v_mov_b32_e32 v53, s47 ; 7E6A022F v_mov_b32_e32 v56, v13 ; 7E70030D image_sample_c_l v58, 1, 0, 0, 0, 0, 0, 0, 0, v[50:53], s[48:55], s[56:59] ; F0B00100 01CC3A32 v_mov_b32_e32 v57, s47 ; 7E72022F v_mov_b32_e32 v52, v13 ; 7E68030D image_sample_c_l v54, 1, 0, 0, 0, 0, 0, 0, 0, v[54:57], s[48:55], s[56:59] ; F0B00100 01CC3636 v_mov_b32_e32 v53, s47 ; 7E6A022F image_sample_c_l v55, 1, 0, 0, 0, 0, 0, 0, 0, v[50:53], s[48:55], s[56:59] ; F0B00100 01CC3732 v_add_f32_e32 v52, 0, v40 ; 02685080 v_mov_b32_e32 v59, v41 ; 7E760329 v_mov_b32_e32 v60, v42 ; 7E78032A v_mov_b32_e32 v61, v43 ; 7E7A032B v_mov_b32_e32 v62, v44 ; 7E7C032C v_mov_b32_e32 v61, v52 ; 7E7A0334 v_add_f32_e32 v42, 0, v39 ; 02544E80 v_mov_b32_e32 v62, s47 ; 7E7C022F v_mov_b32_e32 v63, v41 ; 7E7E0329 v_mov_b32_e32 v64, v42 ; 7E80032A v_mov_b32_e32 v65, v43 ; 7E82032B v_mov_b32_e32 v66, v44 ; 7E84032C image_sample_c_l v56, 1, 0, 0, 0, 0, 0, 0, 0, v[59:62], s[48:55], s[56:59] ; F0B00100 01CC383B v_mov_b32_e32 v65, v13 ; 7E82030D v_mov_b32_e32 v53, s47 ; 7E6A022F image_sample_c_l v13, 1, 0, 0, 0, 0, 0, 0, 0, v[50:53], s[48:55], s[56:59] ; F0B00100 01CC0D32 v_mov_b32_e32 v66, s47 ; 7E84022F image_sample_c_l v50, 1, 0, 0, 0, 0, 0, 0, 0, v[63:66], s[48:55], s[56:59] ; F0B00100 01CC323F v_mov_b32_e32 v44, s47 ; 7E58022F image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[41:44], s[48:55], s[56:59] ; F0B00100 01CC2A29 v_mov_b32_e32 v41, 0 ; 7E520280 image_sample_c_l v38, 1, 0, 0, 0, 0, 0, 0, 0, v[38:41], s[48:55], s[56:59] ; F0B00100 01CC2626 v_mov_b32_e32 v39, 0x3d800000 ; 7E4E02FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v40, v39, v58 ; 0A507527 v_mac_f32_e32 v40, v39, v49 ; 2C506327 s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v40, v39, v54 ; 2C506D27 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v40, v39, v55 ; 2C506F27 v_mov_b32_e32 v39, 0x3e000000 ; 7E4E02FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v13, v39, v13 ; 0A1A1B27 v_mac_f32_e32 v13, v39, v56 ; 2C1A7127 s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v13, v39, v50 ; 2C1A6527 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v13, v39, v42 ; 2C1A5527 v_add_f32_e32 v13, v40, v13 ; 021A1B28 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v13, v38, v13, 0x3e800000 ; 2E1A1B26 3E800000 v_cmp_le_f32_e32 vcc, 0, v48 ; 7C866080 v_cndmask_b32_e64 v13, v13, 1.0, vcc ; D100000D 01A9E50D v_mad_f32 v13, -v47, v13, v13 ; D1C1000D 24361B2F v_mac_f32_e32 v13, v47, v45 ; 2C1A5B2F v_mov_b32_e32 v45, v13 ; 7E5A030D s_or_b64 exec, exec, s[60:61] ; 87FE3C7E v_add_f32_e32 v13, v32, v28 ; 021A3920 v_add_f32_e32 v28, v33, v29 ; 02383B21 v_add_f32_e32 v29, v34, v30 ; 023A3D22 v_add_f32_e32 v13, v13, v35 ; 021A470D v_add_f32_e32 v28, v28, v36 ; 0238491C v_add_f32_e32 v29, v29, v37 ; 023A4B1D v_mul_f32_e32 v13, 0x3e59999a, v13 ; 0A1A1AFF 3E59999A v_madmk_f32_e32 v13, v28, v13, 0x3f372474 ; 2E1A1B1C 3F372474 v_madmk_f32_e32 v13, v29, v13, 0x3d93a92a ; 2E1A1B1D 3D93A92A v_mov_b32_e32 v28, 0xbeaaa64c ; 7E3802FF BEAAA64C v_mul_f32_e32 v13, v13, v28 ; 0A1A390D v_rcp_f32_e32 v13, v13 ; 7E1A450D v_mul_f32_e32 v13, v31, v13 ; 0A1A1B1F v_subrev_f32_e32 v28, s22, v9 ; 06381216 v_subrev_f32_e32 v29, s21, v16 ; 063A2015 v_subrev_f32_e32 v30, s20, v18 ; 063C2414 v_mul_f32_e32 v28, v28, v28 ; 0A38391C v_mac_f32_e32 v28, v29, v29 ; 2C383B1D v_mac_f32_e32 v28, v30, v30 ; 2C383D1E v_mad_f32 v28, v46, v28, s19 ; D1C1001C 004E392E v_add_f32_e64 v28, 0, v28 clamp ; D101801C 00023880 v_sub_f32_e32 v29, 1.0, v28 ; 043A38F2 v_mac_f32_e32 v28, v29, v45 ; 2C385B1D v_sub_f32_e32 v29, 1.0, v28 ; 043A38F2 v_mad_f32 v28, -v28, v13, v13 ; D1C1001C 24361B1C v_mad_f32 v13, v29, v13, 1.0 ; D1C1000D 03CA1B1D v_mac_f32_e32 v5, v5, v28 ; 2C0A3905 v_mac_f32_e32 v11, v11, v28 ; 2C16390B v_mac_f32_e32 v12, v12, v28 ; 2C18390C v_mad_f32 v13, 0.5, v13, 0.5 ; D1C1000D 03C21AF0 v_mad_f32 v28, -v13, v5, v5 ; D1C1001C 24160B0D v_mac_f32_e32 v28, v13, v12 ; 2C38190D v_mad_f32 v29, -v13, v11, v11 ; D1C1001D 242E170D v_mac_f32_e32 v29, v13, v11 ; 2C3A170D v_mad_f32 v11, -v13, v12, v12 ; D1C1000B 2432190D v_mac_f32_e32 v11, v13, v5 ; 2C160B0D v_mov_b32_e32 v5, v11 ; 7E0A030B v_mov_b32_e32 v11, v29 ; 7E16031D v_mov_b32_e32 v12, v28 ; 7E18031C s_or_b64 exec, exec, s[16:17] ; 87FE107E s_buffer_load_dword s20, s[12:15], 0x0 ; C0220506 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4 ; C0220546 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x8 ; C0220586 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0xb0 ; C02204C6 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xb8 ; C02200C6 000000B8 v_mov_b32_e32 v13, s18 ; 7E1A0212 s_buffer_load_dword s0, s[12:15], 0x1d0 ; C0220006 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d4 ; C0220046 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d8 ; C0220086 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x1e8 ; C0220486 000001E8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x1f0 ; C02205C6 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x1f4 ; C0220806 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x1f8 ; C0220306 000001F8 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x40 ; C00E0603 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[4:7], s[4:5], 0x20 ; C00A0102 00000020 v_mov_b32_e32 v28, s8 ; 7E380208 v_sub_f32_e32 v29, s11, v9 ; 043A120B v_sub_f32_e32 v16, s10, v16 ; 0420200A v_sub_f32_e32 v9, s9, v18 ; 04122409 v_mul_f32_e32 v24, v2, v24 ; 0A303102 v_mul_f32_e32 v18, v3, v25 ; 0A243303 v_mul_f32_e32 v3, v6, v26 ; 0A063506 v_mul_f32_e32 v2, v7, v27 ; 0A043707 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v6, v8, v4 ; 0A0C0908 v_mac_f32_e32 v6, v10, v1 ; 2C0C030A v_mac_f32_e32 v6, v15, v0 ; 2C0C010F v_mul_f32_e32 v7, v17, v4 ; 0A0E0911 v_mac_f32_e32 v7, v19, v1 ; 2C0E0313 v_mac_f32_e32 v7, v20, v0 ; 2C0E0114 v_mul_f32_e32 v4, v21, v4 ; 0A080915 v_mac_f32_e32 v4, v22, v1 ; 2C080316 v_mac_f32_e32 v4, v23, v0 ; 2C080117 v_add_f32_e32 v0, s23, v12 ; 02001817 v_add_f32_e32 v1, s32, v11 ; 02021620 v_add_f32_e32 v5, s12, v5 ; 020A0A0C v_mul_f32_e32 v8, v29, v6 ; 0A100D1D v_mac_f32_e32 v8, v16, v7 ; 2C100F10 v_mac_f32_e32 v8, v9, v4 ; 2C100909 v_add_f32_e32 v8, v8, v8 ; 02101108 v_mul_f32_e32 v10, v6, v6 ; 0A140D06 v_mac_f32_e32 v10, v7, v7 ; 2C140F07 v_mac_f32_e32 v10, v4, v4 ; 2C140904 v_mul_f32_e32 v11, v10, v29 ; 0A163B0A v_mul_f32_e32 v12, v10, v16 ; 0A18210A v_mul_f32_e32 v10, v10, v9 ; 0A14130A v_mad_f32 v6, v8, v6, -v11 ; D1C10006 842E0D08 v_mad_f32 v7, v8, v7, -v12 ; D1C10007 84320F08 v_mad_f32 v4, v8, v4, -v10 ; D1C10004 842A0908 v_cubema_f32 v8, v6, v7, v4 ; D1C70008 04120F06 v_cubesc_f32 v10, v6, v7, v4 ; D1C5000A 04120F06 v_rcp_f32_e64 v8, |v8| ; D1620108 00000108 v_cubetc_f32 v11, v6, v7, v4 ; D1C6000B 04120F06 v_cubeid_f32 v21, v6, v7, v4 ; D1C40015 04120F06 v_mov_b32_e32 v19, 0x3fc00000 ; 7E2602FF 3FC00000 v_mad_f32 v20, v8, v11, v19 ; D1C10014 044E1708 v_mac_f32_e32 v19, v8, v10 ; 2C261508 image_sample v[6:8], 7, 0, 0, 0, 0, 0, 0, 0, v[19:22], s[24:31], s[4:7] ; F0800700 00260613 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v4, s18, v6 ; 0A080C12 v_mul_f32_e32 v6, s18, v7 ; 0A0C0E12 v_mul_f32_e32 v7, s18, v8 ; 0A0E1012 v_mul_f32_e32 v4, v4, v14 ; 0A081D04 v_mul_f32_e32 v6, v6, v14 ; 0A0C1D06 v_mul_f32_e32 v7, v7, v14 ; 0A0E1D07 v_mul_f32_e32 v4, s20, v4 ; 0A080814 v_mul_f32_e32 v6, s21, v6 ; 0A0C0C15 v_mul_f32_e32 v7, s22, v7 ; 0A0E0E16 v_mul_f32_e32 v4, v4, v4 ; 0A080904 v_mul_f32_e32 v6, v6, v6 ; 0A0C0D06 v_mul_f32_e32 v7, v7, v7 ; 0A0E0F07 v_mac_f32_e32 v4, v0, v24 ; 2C083100 v_mac_f32_e32 v6, v1, v18 ; 2C0C2501 v_mac_f32_e32 v7, v5, v3 ; 2C0E0705 v_mul_f32_e32 v0, v29, v29 ; 0A003B1D v_mac_f32_e32 v0, v16, v16 ; 2C002110 v_mac_f32_e32 v0, v9, v9 ; 2C001309 v_sqrt_f32_e32 v0, v0 ; 7E004F00 v_mad_f32 v0, v13, v0, s19 ; D1C10000 004E010D v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_min_f32_e32 v0, s3, v0 ; 14000003 v_mul_f32_e32 v1, s8, v4 ; 0A020808 v_mul_f32_e32 v3, s8, v6 ; 0A060C08 v_mul_f32_e32 v5, s8, v7 ; 0A0A0E08 v_mul_f32_e32 v0, v0, v0 ; 0A000100 v_mad_f32 v4, -v4, v28, s0 ; D1C10004 20023904 v_mad_f32 v6, -v6, v28, s1 ; D1C10006 20063906 v_mad_f32 v7, -v7, v28, s2 ; D1C10007 200A3907 v_mac_f32_e32 v1, v4, v0 ; 2C020104 v_mac_f32_e32 v3, v6, v0 ; 2C060106 v_mac_f32_e32 v5, v7, v0 ; 2C0A0107 v_cvt_pkrtz_f16_f32_e64 v0, v1, v3 ; D2960000 00020701 v_cvt_pkrtz_f16_f32_e64 v1, v5, v2 ; D2960001 00020505 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 72 Code Size: 3896 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], CLIPVERTEX DCL OUT[3], GENERIC[0] DCL OUT[4], GENERIC[1] DCL OUT[5], GENERIC[2] DCL OUT[6], GENERIC[3] DCL OUT[7], GENERIC[4] DCL CONST[0..51] DCL TEMP[0..8], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, CONST[0].yyyy 2: MAD TEMP[2], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 3: DP4 TEMP[1].x, TEMP[2], CONST[48] 4: DP4 TEMP[3].x, TEMP[2], CONST[49] 5: MOV TEMP[1].y, TEMP[3].xxxx 6: DP4 TEMP[3].x, TEMP[2], CONST[50] 7: MOV TEMP[1].z, TEMP[3].xxxx 8: DP4 TEMP[3].x, TEMP[1], CONST[8] 9: DP4 TEMP[4].x, TEMP[1], CONST[9] 10: MOV TEMP[3].y, TEMP[4].xxxx 11: DP4 TEMP[5].x, TEMP[1], CONST[11] 12: MOV TEMP[3].w, TEMP[5].xxxx 13: DP4 TEMP[6].x, TEMP[1], CONST[10] 14: MOV TEMP[1].w, TEMP[6].xxxx 15: MOV TEMP[1], TEMP[1] 16: ADD TEMP[2].xy, IN[3].xyyy, IN[2].xyyy 17: ADD TEMP[7].xy, TEMP[2].yxxx, IN[3].yxxx 18: MOV TEMP[2].zw, TEMP[7].yyxy 19: ADD TEMP[7].xy, TEMP[7].yxxx, IN[3].xyyy 20: MOV TEMP[3].z, TEMP[6].xxxx 21: MOV TEMP[0].xy, IN[1].xyxx 22: MOV TEMP[7].zw, IN[1].yyxy 23: MOV TEMP[8], TEMP[3] 24: MAD TEMP[6].x, TEMP[6].xxxx, CONST[0].zzzz, -TEMP[5].xxxx 25: MOV TEMP[3].z, TEMP[6].xxxx 26: MOV TEMP[3].y, -TEMP[4].xxxx 27: MAD TEMP[3].xy, CONST[51].xyyy, TEMP[5].xxxx, TEMP[3].xyyy 28: MUL TEMP[4], CONST[0].yyxx, IN[1].xyxx 29: MAD TEMP[5], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 30: MOV OUT[3], TEMP[0] 31: MOV OUT[4], TEMP[4] 32: MOV OUT[6], TEMP[2] 33: MOV OUT[7], TEMP[7] 34: MOV OUT[5], TEMP[1] 35: MOV OUT[0], TEMP[3] 36: MOV OUT[2], TEMP[8] 37: MOV OUT[1], TEMP[5] 38: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %62 = load <16 x i8>, <16 x i8> addrspace(2)* %61, align 16, !tbaa !0 %63 = add i32 %5, %8 %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %63) %65 = extractelement <4 x float> %64, i32 0 %66 = extractelement <4 x float> %64, i32 1 %67 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, align 16, !tbaa !0 %69 = add i32 %5, %8 %70 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %69) %71 = extractelement <4 x float> %70, i32 0 %72 = extractelement <4 x float> %70, i32 1 %73 = fmul float %52, %15 %74 = fadd float %73, %14 %75 = fmul float %53, %15 %76 = fadd float %75, %14 %77 = fmul float %54, %15 %78 = fadd float %77, %14 %79 = fmul float %52, %14 %80 = fadd float %79, %15 %81 = fmul float %74, %34 %82 = fmul float %76, %35 %83 = fadd float %81, %82 %84 = fmul float %78, %36 %85 = fadd float %83, %84 %86 = fmul float %80, %37 %87 = fadd float %85, %86 %88 = fmul float %74, %38 %89 = fmul float %76, %39 %90 = fadd float %88, %89 %91 = fmul float %78, %40 %92 = fadd float %90, %91 %93 = fmul float %80, %41 %94 = fadd float %92, %93 %95 = fmul float %74, %42 %96 = fmul float %76, %43 %97 = fadd float %95, %96 %98 = fmul float %78, %44 %99 = fadd float %97, %98 %100 = fmul float %80, %45 %101 = fadd float %99, %100 %102 = fmul float %87, %17 %103 = fmul float %94, %18 %104 = fadd float %102, %103 %105 = fmul float %101, %19 %106 = fadd float %104, %105 %107 = fmul float %15, %20 %108 = fadd float %106, %107 %109 = fmul float %87, %21 %110 = fmul float %94, %22 %111 = fadd float %109, %110 %112 = fmul float %101, %23 %113 = fadd float %111, %112 %114 = fmul float %15, %24 %115 = fadd float %113, %114 %116 = fmul float %87, %29 %117 = fmul float %94, %30 %118 = fadd float %116, %117 %119 = fmul float %101, %31 %120 = fadd float %118, %119 %121 = fmul float %15, %32 %122 = fadd float %120, %121 %123 = fmul float %87, %25 %124 = fmul float %94, %26 %125 = fadd float %123, %124 %126 = fmul float %101, %27 %127 = fadd float %125, %126 %128 = fmul float %15, %28 %129 = fadd float %127, %128 %130 = fadd float %71, %65 %131 = fadd float %72, %66 %132 = fadd float %131, %72 %133 = fadd float %130, %71 %134 = fadd float %133, %71 %135 = fadd float %132, %72 %136 = fmul float %129, %16 %137 = fsub float %136, %122 %138 = fmul float %46, %122 %139 = fadd float %138, %108 %140 = fmul float %47, %122 %141 = fsub float %140, %115 %142 = fmul float %15, %59 %143 = fmul float %15, %60 %144 = fmul float %14, %59 %145 = fmul float %14, %59 %146 = fmul float %33, %14 %147 = fadd float %146, %15 %148 = fmul float %33, %14 %149 = fadd float %148, %15 %150 = fmul float %33, %14 %151 = fadd float %150, %15 %152 = fmul float %33, %15 %153 = fadd float %152, %14 %154 = and i32 %7, 1 %155 = icmp eq i32 %154, 0 br i1 %155, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %156 = call float @llvm.AMDIL.clamp.(float %147, float 0.000000e+00, float 1.000000e+00) %157 = call float @llvm.AMDIL.clamp.(float %149, float 0.000000e+00, float 1.000000e+00) %158 = call float @llvm.AMDIL.clamp.(float %151, float 0.000000e+00, float 1.000000e+00) %159 = call float @llvm.AMDIL.clamp.(float %153, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.038 = phi float [ %159, %if-true-block ], [ %153, %main_body ] %.037 = phi float [ %158, %if-true-block ], [ %151, %main_body ] %.036 = phi float [ %157, %if-true-block ], [ %149, %main_body ] %.0 = phi float [ %156, %if-true-block ], [ %147, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.036, float %.037, float %.038) %160 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %161 = load <16 x i8>, <16 x i8> addrspace(2)* %160, align 16, !tbaa !0 %162 = call float @llvm.SI.load.const(<16 x i8> %161, i32 0) %163 = fmul float %162, %108 %164 = call float @llvm.SI.load.const(<16 x i8> %161, i32 4) %165 = fmul float %164, %115 %166 = fadd float %163, %165 %167 = call float @llvm.SI.load.const(<16 x i8> %161, i32 8) %168 = fmul float %167, %129 %169 = fadd float %166, %168 %170 = call float @llvm.SI.load.const(<16 x i8> %161, i32 12) %171 = fmul float %170, %122 %172 = fadd float %169, %171 %173 = call float @llvm.SI.load.const(<16 x i8> %161, i32 16) %174 = fmul float %173, %108 %175 = call float @llvm.SI.load.const(<16 x i8> %161, i32 20) %176 = fmul float %175, %115 %177 = fadd float %174, %176 %178 = call float @llvm.SI.load.const(<16 x i8> %161, i32 24) %179 = fmul float %178, %129 %180 = fadd float %177, %179 %181 = call float @llvm.SI.load.const(<16 x i8> %161, i32 28) %182 = fmul float %181, %122 %183 = fadd float %180, %182 %184 = call float @llvm.SI.load.const(<16 x i8> %161, i32 32) %185 = fmul float %184, %108 %186 = call float @llvm.SI.load.const(<16 x i8> %161, i32 36) %187 = fmul float %186, %115 %188 = fadd float %185, %187 %189 = call float @llvm.SI.load.const(<16 x i8> %161, i32 40) %190 = fmul float %189, %129 %191 = fadd float %188, %190 %192 = call float @llvm.SI.load.const(<16 x i8> %161, i32 44) %193 = fmul float %192, %122 %194 = fadd float %191, %193 %195 = call float @llvm.SI.load.const(<16 x i8> %161, i32 48) %196 = fmul float %195, %108 %197 = call float @llvm.SI.load.const(<16 x i8> %161, i32 52) %198 = fmul float %197, %115 %199 = fadd float %196, %198 %200 = call float @llvm.SI.load.const(<16 x i8> %161, i32 56) %201 = fmul float %200, %129 %202 = fadd float %199, %201 %203 = call float @llvm.SI.load.const(<16 x i8> %161, i32 60) %204 = fmul float %203, %122 %205 = fadd float %202, %204 %206 = call float @llvm.SI.load.const(<16 x i8> %161, i32 64) %207 = fmul float %206, %108 %208 = call float @llvm.SI.load.const(<16 x i8> %161, i32 68) %209 = fmul float %208, %115 %210 = fadd float %207, %209 %211 = call float @llvm.SI.load.const(<16 x i8> %161, i32 72) %212 = fmul float %211, %129 %213 = fadd float %210, %212 %214 = call float @llvm.SI.load.const(<16 x i8> %161, i32 76) %215 = fmul float %214, %122 %216 = fadd float %213, %215 %217 = call float @llvm.SI.load.const(<16 x i8> %161, i32 80) %218 = fmul float %217, %108 %219 = call float @llvm.SI.load.const(<16 x i8> %161, i32 84) %220 = fmul float %219, %115 %221 = fadd float %218, %220 %222 = call float @llvm.SI.load.const(<16 x i8> %161, i32 88) %223 = fmul float %222, %129 %224 = fadd float %221, %223 %225 = call float @llvm.SI.load.const(<16 x i8> %161, i32 92) %226 = fmul float %225, %122 %227 = fadd float %224, %226 %228 = call float @llvm.SI.load.const(<16 x i8> %161, i32 96) %229 = fmul float %228, %108 %230 = call float @llvm.SI.load.const(<16 x i8> %161, i32 100) %231 = fmul float %230, %115 %232 = fadd float %229, %231 %233 = call float @llvm.SI.load.const(<16 x i8> %161, i32 104) %234 = fmul float %233, %129 %235 = fadd float %232, %234 %236 = call float @llvm.SI.load.const(<16 x i8> %161, i32 108) %237 = fmul float %236, %122 %238 = fadd float %235, %237 %239 = call float @llvm.SI.load.const(<16 x i8> %161, i32 112) %240 = fmul float %239, %108 %241 = call float @llvm.SI.load.const(<16 x i8> %161, i32 116) %242 = fmul float %241, %115 %243 = fadd float %240, %242 %244 = call float @llvm.SI.load.const(<16 x i8> %161, i32 120) %245 = fmul float %244, %129 %246 = fadd float %243, %245 %247 = call float @llvm.SI.load.const(<16 x i8> %161, i32 124) %248 = fmul float %247, %122 %249 = fadd float %246, %248 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %59, float %60, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %142, float %143, float %144, float %145) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %87, float %94, float %101, float %129) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %130, float %131, float %132, float %133) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %134, float %135, float %59, float %60) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %139, float %141, float %137, float %122) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %172, float %183, float %194, float %205) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %216, float %227, float %238, float %249) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x30 ; C00A0604 00000030 v_add_i32_e32 v4, vcc, s10, v0 ; 3208000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[10:13], v4, s[4:7], 0 idxen ; E00C2000 80010A04 s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v4, s[16:19], 0 idxen ; E00C2000 80040004 s_nop 0 ; BF800000 buffer_load_format_xyzw v[6:9], v4, s[20:23], 0 idxen ; E00C2000 80050604 s_waitcnt vmcnt(1) ; BF8C0771 buffer_load_format_xyzw v[2:5], v4, s[24:27], 0 idxen ; E00C2000 80060204 s_load_dwordx4 s[36:39], s[2:3], 0x0 ; C00A0901 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s0, s[36:39], 0x0 ; C0220012 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[36:39], 0x4 ; C02208D2 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[36:39], 0x8 ; C0220152 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[36:39], 0x80 ; C0220552 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[36:39], 0x84 ; C0220592 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[36:39], 0x88 ; C0220512 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[36:39], 0x8c ; C0220492 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[36:39], 0x90 ; C0220452 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s19, s[36:39], 0x94 ; C02204D2 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[36:39], 0x98 ; C02203D2 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[36:39], 0x9c ; C0220392 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s8, s[36:39], 0xa0 ; C0220212 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[36:39], 0xa4 ; C0220252 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[36:39], 0xa8 ; C02201D2 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[36:39], 0xac ; C0220192 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s13, s[36:39], 0xb0 ; C0220352 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[36:39], 0xb4 ; C0220412 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[36:39], 0xb8 ; C02202D2 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[36:39], 0xbc ; C0220292 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s40, s[36:39], 0x2fc ; C0220A12 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s33, s[36:39], 0x300 ; C0220852 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[36:39], 0x304 ; C0220892 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[36:39], 0x308 ; C0220812 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[36:39], 0x30c ; C0220792 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s29, s[36:39], 0x310 ; C0220752 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[36:39], 0x314 ; C02207D2 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[36:39], 0x318 ; C0220712 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s26, s[36:39], 0x31c ; C0220692 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s25, s[36:39], 0x320 ; C0220652 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[36:39], 0x324 ; C02206D2 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s24, s[36:39], 0x328 ; C0220612 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[36:39], 0x32c ; C02205D2 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[36:39], 0x330 ; C0220052 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[36:39], 0x334 ; C0220112 00000334 s_waitcnt vmcnt(0) lgkmcnt(0) ; BF8C0070 v_mov_b32_e32 v4, s35 ; 7E080223 v_mov_b32_e32 v5, s0 ; 7E0A0200 v_mad_f32 v8, s40, v5, v4 ; D1C10008 04120A28 v_mad_f32 v5, s40, v4, v5 ; D1C10005 04160828 s_and_b32 s12, 1, s12 ; 860C0C81 v_cmp_eq_i32_e64 s[36:37], 1, s12 ; D0C20024 00001881 v_mov_b32_e32 v13, v8 ; 7E1A0308 v_mov_b32_e32 v9, v8 ; 7E120308 s_and_saveexec_b64 s[36:37], s[36:37] ; BEA42024 s_xor_b64 s[36:37], exec, s[36:37] ; 88A4247E v_add_f32_e64 v9, 0, v8 clamp ; D1018009 00021080 v_add_f32_e64 v13, 0, v8 clamp ; D101800D 00021080 v_add_f32_e64 v8, 0, v8 clamp ; D1018008 00021080 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 s_or_b64 exec, exec, s[36:37] ; 87FE247E exp 15, 32, 0, 0, 0, v8, v9, v13, v5 ; C400020F 050D0908 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v5, v4, v10, s0 ; D1C10005 00021504 v_mad_f32 v8, v11, v4, s0 ; D1C10008 0002090B v_mad_f32 v9, v12, v4, s0 ; D1C10009 0002090C v_mad_f32 v10, s0, v10, v4 ; D1C1000A 04121400 v_mul_f32_e32 v11, s34, v8 ; 0A161022 v_mac_f32_e32 v11, s33, v5 ; 2C160A21 v_mac_f32_e32 v11, s32, v9 ; 2C161220 v_mac_f32_e32 v11, s30, v10 ; 2C16141E v_mul_f32_e32 v12, s31, v8 ; 0A18101F v_mac_f32_e32 v12, s29, v5 ; 2C180A1D v_mac_f32_e32 v12, s28, v9 ; 2C18121C v_mac_f32_e32 v12, s26, v10 ; 2C18141A v_mul_f32_e32 v8, s27, v8 ; 0A10101B v_mac_f32_e32 v8, s25, v5 ; 2C100A19 v_mac_f32_e32 v8, s24, v9 ; 2C101218 v_mac_f32_e32 v8, s23, v10 ; 2C101417 v_mul_f32_e32 v5, s22, v12 ; 0A0A1816 v_mac_f32_e32 v5, s21, v11 ; 2C0A1615 v_mac_f32_e32 v5, s20, v8 ; 2C0A1014 v_mac_f32_e32 v5, s18, v4 ; 2C0A0812 v_mul_f32_e32 v9, s19, v12 ; 0A121813 v_mac_f32_e32 v9, s17, v11 ; 2C121611 v_mac_f32_e32 v9, s15, v8 ; 2C12100F v_mac_f32_e32 v9, s14, v4 ; 2C12080E v_mul_f32_e32 v10, s16, v12 ; 0A141810 v_mac_f32_e32 v10, s13, v11 ; 2C14160D v_mac_f32_e32 v10, s11, v8 ; 2C14100B v_mac_f32_e32 v10, s10, v4 ; 2C14080A v_mul_f32_e32 v13, s9, v12 ; 0A1A1809 v_mac_f32_e32 v13, s8, v11 ; 2C1A1608 v_mac_f32_e32 v13, s7, v8 ; 2C1A1007 v_mac_f32_e32 v13, s6, v4 ; 2C1A0806 s_load_dwordx4 s[8:11], s[2:3], 0x100 ; C00A0201 00000100 v_add_f32_e32 v6, v6, v2 ; 020C0506 v_add_f32_e32 v7, v7, v3 ; 020E0707 v_add_f32_e32 v14, v3, v7 ; 021C0F03 v_add_f32_e32 v15, v2, v6 ; 021E0D02 v_add_f32_e32 v2, v2, v15 ; 02041F02 v_add_f32_e32 v3, v3, v14 ; 02061D03 v_mad_f32 v16, v13, s5, -v10 ; D1C10010 84280B0D v_mul_f32_e32 v17, v0, v4 ; 0A220900 v_mul_f32_e32 v4, v1, v4 ; 0A080901 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s2, s[8:11], 0x0 ; C0220084 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x4 ; C02200C4 00000004 v_mov_b32_e32 v18, 0 ; 7E240280 s_buffer_load_dword s5, s[8:11], 0x8 ; C0220144 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0xc ; C0220184 0000000C exp 15, 33, 0, 0, 0, v0, v1, v18, v18 ; C400021F 12120100 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v18, s0, v0 ; 0A240000 exp 15, 34, 0, 0, 0, v17, v4, v18, v18 ; C400022F 12120411 s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v4, s1, v10, v5 ; D1C10004 04161401 v_mad_f32 v17, s4, v10, -v9 ; D1C10011 84261404 s_buffer_load_dword s0, s[8:11], 0x10 ; C0220004 00000010 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v18, s3, v9 ; 0A241203 v_mac_f32_e32 v18, s2, v5 ; 2C240A02 v_mac_f32_e32 v18, s5, v13 ; 2C241A05 v_mac_f32_e32 v18, s6, v10 ; 2C241406 s_buffer_load_dword s1, s[8:11], 0x14 ; C0220044 00000014 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[8:11], 0x18 ; C0220084 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x1c ; C02200C4 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s4, s[8:11], 0x20 ; C0220104 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s5, s[8:11], 0x24 ; C0220144 00000024 exp 15, 35, 0, 0, 0, v11, v12, v8, v13 ; C400023F 0D080C0B s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0x28 ; C0220184 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[8:11], 0x2c ; C02201C4 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s12, s[8:11], 0x30 ; C0220304 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[8:11], 0x34 ; C0220344 00000034 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v8, s1, v9 ; 0A101201 s_buffer_load_dword s1, s[8:11], 0x38 ; C0220044 00000038 v_mac_f32_e32 v8, s0, v5 ; 2C100A00 v_mac_f32_e32 v8, s2, v13 ; 2C101A02 v_mac_f32_e32 v8, s3, v10 ; 2C101403 v_mul_f32_e32 v11, s5, v9 ; 0A161205 v_mac_f32_e32 v11, s4, v5 ; 2C160A04 v_mac_f32_e32 v11, s6, v13 ; 2C161A06 v_mac_f32_e32 v11, s7, v10 ; 2C161407 v_mul_f32_e32 v12, s13, v9 ; 0A18120D v_mac_f32_e32 v12, s12, v5 ; 2C180A0C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s1, v13 ; 2C181A01 s_buffer_load_dword s0, s[8:11], 0x3c ; C0220004 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[8:11], 0x40 ; C0220044 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[8:11], 0x44 ; C0220084 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[8:11], 0x48 ; C02200C4 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[8:11], 0x4c ; C0220104 0000004C s_nop 0 ; BF800000 s_buffer_load_dword s5, s[8:11], 0x50 ; C0220144 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[8:11], 0x54 ; C0220184 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[8:11], 0x58 ; C02201C4 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[8:11], 0x5c ; C0220304 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s13, s[8:11], 0x60 ; C0220344 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[8:11], 0x64 ; C0220384 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s15, s[8:11], 0x68 ; C02203C4 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[8:11], 0x6c ; C0220404 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s17, s[8:11], 0x70 ; C0220444 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[8:11], 0x74 ; C0220484 00000074 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s0, v10 ; 2C181400 exp 15, 36, 0, 0, 0, v6, v7, v14, v15 ; C400024F 0F0E0706 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v6, s2, v9 ; 0A0C1202 v_mac_f32_e32 v6, s1, v5 ; 2C0C0A01 v_mul_f32_e32 v7, s6, v9 ; 0A0E1206 v_mac_f32_e32 v7, s5, v5 ; 2C0E0A05 v_mul_f32_e32 v14, s14, v9 ; 0A1C120E v_mac_f32_e32 v14, s13, v5 ; 2C1C0A0D s_buffer_load_dword s0, s[8:11], 0x78 ; C0220004 00000078 v_mul_f32_e32 v9, s18, v9 ; 0A121212 s_buffer_load_dword s1, s[8:11], 0x7c ; C0220044 0000007C exp 15, 37, 0, 0, 0, v2, v3, v0, v1 ; C400025F 01000302 exp 15, 12, 0, 0, 0, v4, v17, v16, v10 ; C40000CF 0A101104 exp 15, 13, 0, 0, 0, v18, v8, v11, v12 ; C40000DF 0C0B0812 v_mac_f32_e32 v9, s17, v5 ; 2C120A11 v_mac_f32_e32 v6, s3, v13 ; 2C0C1A03 v_mac_f32_e32 v7, s7, v13 ; 2C0E1A07 v_mac_f32_e32 v14, s15, v13 ; 2C1C1A0F s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v9, s0, v13 ; 2C121A00 v_mac_f32_e32 v6, s4, v10 ; 2C0C1404 v_mac_f32_e32 v7, s12, v10 ; 2C0E140C v_mac_f32_e32 v14, s16, v10 ; 2C1C1410 v_mac_f32_e32 v9, s1, v10 ; 2C121401 exp 15, 14, 0, 1, 0, v6, v7, v14, v9 ; C40008EF 090E0706 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 20 Code Size: 1416 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL IN[2], GENERIC[1], PERSPECTIVE DCL IN[3], GENERIC[2], PERSPECTIVE DCL IN[4], GENERIC[3], PERSPECTIVE, CENTROID DCL IN[5], GENERIC[4], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], 2D, FLOAT DCL SVIEW[3], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..17], LOCAL IMM[0] FLT32 { 2.0000, -1.0000, 0.8165, 0.5774} IMM[1] FLT32 { -0.4082, 0.7071, 0.5774, 1.0000} IMM[2] FLT32 { -0.4082, -0.7071, 0.5774, 0.0000} IMM[3] FLT32 { 0.2125, 0.7154, 0.0721, 0.3333} IMM[4] FLT32 { 1.0000, 0.0000, -0.5000, 0.0005} IMM[5] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[6] FLT32 { -0.0005, 0.0005, 0.0000, 0.1250} IMM[7] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[8] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MOV TEMP[1].xy, IN[2].xyyy 3: TEX TEMP[1].xyz, TEMP[1], SAMP[2], 2D 4: MAD TEMP[1].xyz, TEMP[1].xyzz, IMM[0].xxxx, IMM[0].yyyy 5: MOV TEMP[2].xy, IN[4].xyyy 6: TEX TEMP[2], TEMP[2], SAMP[1], 2D 7: MOV TEMP[3], TEMP[2] 8: MOV TEMP[4].xy, IN[4].wzzz 9: TEX TEMP[4], TEMP[4], SAMP[1], 2D 10: MOV TEMP[5], TEMP[4] 11: MOV TEMP[6].xy, IN[5].xyyy 12: TEX TEMP[6], TEMP[6], SAMP[1], 2D 13: MOV TEMP[7], TEMP[6] 14: MUL TEMP[8].xyz, TEMP[0].xyzz, IN[0].xyzz 15: MUL TEMP[0].x, TEMP[0].wwww, IN[0].wwww 16: MOV TEMP[0].w, TEMP[0].xxxx 17: DP2 TEMP[9].x, TEMP[1].xzzz, IMM[0].zwww 18: MOV_SAT TEMP[9].x, TEMP[9].xxxx 19: DP3 TEMP[10].x, TEMP[1].xyzz, IMM[1].xyzz 20: MOV_SAT TEMP[10].x, TEMP[10].xxxx 21: MOV TEMP[9].y, TEMP[10].xxxx 22: DP3 TEMP[10].x, TEMP[1].xyzz, IMM[2].xyzz 23: MOV_SAT TEMP[10].x, TEMP[10].xxxx 24: MOV TEMP[9].z, TEMP[10].xxxx 25: MUL TEMP[1].xyz, TEMP[9].xyzz, TEMP[9].xyzz 26: MUL TEMP[9].xyz, TEMP[4].xyzz, TEMP[1].yyyy 27: MAD TEMP[9].xyz, TEMP[1].xxxx, TEMP[2].xyzz, TEMP[9].xyzz 28: MAD TEMP[9].xyz, TEMP[1].zzzz, TEMP[6].xyzz, TEMP[9].xyzz 29: DP3 TEMP[10].x, TEMP[1].xyzz, IMM[1].wwww 30: RCP TEMP[10].x, TEMP[10].xxxx 31: MUL TEMP[1].xyz, TEMP[10].xxxx, CONST[12].xyzz 32: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[9].xyzz 33: FSLT TEMP[10].x, -TEMP[2].wwww, IMM[2].wwww 34: AND TEMP[10].x, CONST[90].xxxx, TEMP[10].xxxx 35: UIF TEMP[10].xxxx :0 36: ADD TEMP[3].xyz, TEMP[2].xyzz, TEMP[4].xyzz 37: ADD TEMP[3].xyz, TEMP[6].xyzz, TEMP[3].xyzz 38: DP3 TEMP[4].x, TEMP[3].xyzz, IMM[3].xyzz 39: MUL TEMP[4].x, TEMP[4].xxxx, IMM[3].wwww 40: RCP TEMP[4].x, TEMP[4].xxxx 41: MUL TEMP[2].x, TEMP[4].xxxx, TEMP[2].wwww 42: MAD TEMP[3], IN[3].xyzx, IMM[4].xxxy, IMM[4].yyyx 43: DP4 TEMP[5].x, TEMP[3], CONST[69] 44: DP4 TEMP[4].x, TEMP[3], CONST[70] 45: MOV TEMP[5].y, TEMP[4].xxxx 46: MOV_SAT TEMP[6].xy, TEMP[5].xyyy 47: ADD TEMP[7].xy, -TEMP[5].xyyy, TEMP[6].xyyy 48: DP2 TEMP[6].x, TEMP[7].xyyy, IMM[1].wwww 49: DP4 TEMP[7].x, TEMP[3], CONST[73] 50: DP4 TEMP[10].x, TEMP[3], CONST[74] 51: MOV TEMP[7].y, TEMP[10].xxxx 52: MOV_SAT TEMP[11].xy, TEMP[7].xyyy 53: ADD TEMP[9].xy, -TEMP[7].xyyy, TEMP[11].xyyy 54: DP2 TEMP[11].x, TEMP[9].xyyy, IMM[1].wwww 55: MOV TEMP[5].w, TEMP[11].xxxx 56: DP4 TEMP[9].x, TEMP[3], CONST[77] 57: DP4 TEMP[12].x, TEMP[3], CONST[78] 58: MOV TEMP[7].zw, IMM[4].yyxy 59: MOV TEMP[13].w, TEMP[7] 60: ABS TEMP[14].x, TEMP[11].xxxx 61: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 62: UIF TEMP[14].xxxx :0 63: MOV TEMP[14].x, TEMP[7].xxxx 64: ELSE :0 65: MOV TEMP[14].x, TEMP[9].xxxx 66: ENDIF 67: MOV TEMP[13].x, TEMP[14].xxxx 68: ABS TEMP[14].x, TEMP[11].xxxx 69: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 70: UIF TEMP[14].xxxx :0 71: MOV TEMP[10].x, TEMP[10].xxxx 72: ELSE :0 73: MOV TEMP[10].x, TEMP[12].xxxx 74: ENDIF 75: MOV TEMP[13].y, TEMP[10].xxxx 76: ABS TEMP[10].x, TEMP[11].xxxx 77: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[2].wwww 78: UIF TEMP[10].xxxx :0 79: MOV TEMP[10].x, IMM[4].xxxx 80: ELSE :0 81: MOV TEMP[10].x, IMM[0].xxxx 82: ENDIF 83: MOV TEMP[13].z, TEMP[10].xxxx 84: MOV TEMP[7], TEMP[13] 85: MOV TEMP[5].zw, IMM[2].wwww 86: MOV TEMP[13].w, TEMP[5] 87: ABS TEMP[10].x, TEMP[6].xxxx 88: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[2].wwww 89: UIF TEMP[10].xxxx :0 90: MOV TEMP[10].x, TEMP[5].xxxx 91: ELSE :0 92: MOV TEMP[10].x, TEMP[7].xxxx 93: ENDIF 94: MOV TEMP[13].x, TEMP[10].xxxx 95: ABS TEMP[10].x, TEMP[6].xxxx 96: FSGE TEMP[10].x, -TEMP[10].xxxx, IMM[2].wwww 97: UIF TEMP[10].xxxx :0 98: MOV TEMP[4].x, TEMP[4].xxxx 99: ELSE :0 100: MOV TEMP[4].x, TEMP[7].yyyy 101: ENDIF 102: MOV TEMP[13].y, TEMP[4].xxxx 103: ABS TEMP[4].x, TEMP[6].xxxx 104: FSGE TEMP[4].x, -TEMP[4].xxxx, IMM[2].wwww 105: UIF TEMP[4].xxxx :0 106: MOV TEMP[4].x, IMM[2].wwww 107: ELSE :0 108: MOV TEMP[4].x, TEMP[7].zzzz 109: ENDIF 110: MOV TEMP[13].z, TEMP[4].xxxx 111: MOV TEMP[5].zw, TEMP[13].wwzw 112: DP4 TEMP[6].x, TEMP[3], CONST[71] 113: MOV TEMP[7].z, TEMP[6].xxxx 114: ADD TEMP[9].xy, TEMP[13].xyyy, IMM[4].zzzz 115: ABS TEMP[10].xy, TEMP[9].xyyy 116: ADD TEMP[9].xy, TEMP[10].xyyy, -CONST[67].zzzz 117: MUL TEMP[9].xy, TEMP[9].xyyy, CONST[67].wwww 118: MOV_SAT TEMP[10].xy, TEMP[9].xyyy 119: ADD TEMP[9].xy, -TEMP[10].xyyy, IMM[1].wwww 120: MUL TEMP[10].x, TEMP[9].yyyy, TEMP[9].xxxx 121: MOV_SAT TEMP[11].xy, TEMP[13].xyyy 122: ADD TEMP[9].xyz, TEMP[4].xxxx, IMM[5].xyzz 123: ABS TEMP[12].x, TEMP[9].xxxx 124: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 125: UIF TEMP[12].xxxx :0 126: MOV TEMP[12].x, CONST[85].zzzz 127: ELSE :0 128: MOV TEMP[12].x, TEMP[5].wwww 129: ENDIF 130: ABS TEMP[14].x, TEMP[9].xxxx 131: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 132: UIF TEMP[14].xxxx :0 133: MOV TEMP[14].x, CONST[85].wwww 134: ELSE :0 135: MOV TEMP[14].x, TEMP[5].wwww 136: ENDIF 137: MOV TEMP[13].y, TEMP[14].xxxx 138: ABS TEMP[14].x, TEMP[9].xxxx 139: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 140: UIF TEMP[14].xxxx :0 141: MOV TEMP[14].x, CONST[85].xxxx 142: ELSE :0 143: MOV TEMP[14].x, TEMP[5].wwww 144: ENDIF 145: MOV TEMP[13].z, TEMP[14].xxxx 146: ABS TEMP[14].x, TEMP[9].xxxx 147: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 148: UIF TEMP[14].xxxx :0 149: MOV TEMP[14].x, CONST[85].yyyy 150: ELSE :0 151: MOV TEMP[14].x, TEMP[5].wwww 152: ENDIF 153: MOV TEMP[13].w, TEMP[14].xxxx 154: ABS TEMP[14].x, TEMP[9].yyyy 155: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 156: UIF TEMP[14].xxxx :0 157: MOV TEMP[14].x, CONST[86].zzzz 158: ELSE :0 159: MOV TEMP[14].x, TEMP[12].xxxx 160: ENDIF 161: MOV TEMP[13].x, TEMP[14].xxxx 162: ABS TEMP[12].x, TEMP[9].yyyy 163: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 164: UIF TEMP[12].xxxx :0 165: MOV TEMP[12].x, CONST[86].wwww 166: ELSE :0 167: MOV TEMP[12].x, TEMP[13].yyyy 168: ENDIF 169: MOV TEMP[13].y, TEMP[12].xxxx 170: ABS TEMP[12].x, TEMP[9].yyyy 171: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 172: UIF TEMP[12].xxxx :0 173: MOV TEMP[12].x, CONST[86].xxxx 174: ELSE :0 175: MOV TEMP[12].x, TEMP[13].zzzz 176: ENDIF 177: MOV TEMP[13].z, TEMP[12].xxxx 178: ABS TEMP[12].x, TEMP[9].yyyy 179: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 180: UIF TEMP[12].xxxx :0 181: MOV TEMP[12].x, CONST[86].yyyy 182: ELSE :0 183: MOV TEMP[12].x, TEMP[13].wwww 184: ENDIF 185: MOV TEMP[13].w, TEMP[12].xxxx 186: MOV TEMP[4], TEMP[13] 187: ABS TEMP[12].x, TEMP[9].zzzz 188: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 189: UIF TEMP[12].xxxx :0 190: MOV TEMP[12].x, CONST[87].zzzz 191: ELSE :0 192: MOV TEMP[12].x, TEMP[4].xxxx 193: ENDIF 194: MOV TEMP[13].x, TEMP[12].xxxx 195: ABS TEMP[12].x, TEMP[9].zzzz 196: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 197: UIF TEMP[12].xxxx :0 198: MOV TEMP[12].x, CONST[87].wwww 199: ELSE :0 200: MOV TEMP[12].x, TEMP[4].yyyy 201: ENDIF 202: MOV TEMP[13].y, TEMP[12].xxxx 203: ABS TEMP[12].x, TEMP[9].zzzz 204: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 205: UIF TEMP[12].xxxx :0 206: MOV TEMP[12].x, CONST[87].xxxx 207: ELSE :0 208: MOV TEMP[12].x, TEMP[4].zzzz 209: ENDIF 210: MOV TEMP[13].z, TEMP[12].xxxx 211: ABS TEMP[12].x, TEMP[9].zzzz 212: FSGE TEMP[12].x, -TEMP[12].xxxx, IMM[2].wwww 213: UIF TEMP[12].xxxx :0 214: MOV TEMP[12].x, CONST[87].yyyy 215: ELSE :0 216: MOV TEMP[12].x, TEMP[4].wwww 217: ENDIF 218: MOV TEMP[13].w, TEMP[12].xxxx 219: MAD TEMP[7].xy, TEMP[11].xyyy, TEMP[13].xyyy, TEMP[13].zwww 220: ADD TEMP[9], TEMP[7], IMM[4].wwyy 221: TXL TEMP[11].x, TEMP[9], SAMP[3], SHADOW2D 222: MOV TEMP[9].x, TEMP[11].xxxx 223: ADD TEMP[4], TEMP[7], IMM[6].xyzz 224: ADD TEMP[11], TEMP[7], IMM[6].yxzz 225: ADD TEMP[12], TEMP[7], IMM[6].xxzz 226: TXL TEMP[14].x, TEMP[4], SAMP[3], SHADOW2D 227: MOV TEMP[9].y, TEMP[14].xxxx 228: TXL TEMP[14].x, TEMP[11], SAMP[3], SHADOW2D 229: MOV TEMP[9].z, TEMP[14].xxxx 230: TXL TEMP[14].x, TEMP[12], SAMP[3], SHADOW2D 231: MOV TEMP[9].w, TEMP[14].xxxx 232: DP4 TEMP[14].x, TEMP[9], IMM[5].wwww 233: ADD TEMP[9], TEMP[7], IMM[4].wyyy 234: TXL TEMP[15].x, TEMP[9], SAMP[3], SHADOW2D 235: MOV TEMP[9].x, TEMP[15].xxxx 236: ADD TEMP[4], TEMP[7], IMM[6].xzzz 237: TXL TEMP[15], TEMP[4], SAMP[3], SHADOW2D 238: MOV TEMP[4], TEMP[15] 239: ADD TEMP[11], TEMP[7], IMM[6].zxzz 240: TXL TEMP[16], TEMP[11], SAMP[3], SHADOW2D 241: MOV TEMP[11], TEMP[16] 242: ADD TEMP[12], TEMP[7], IMM[4].ywyy 243: TXL TEMP[17], TEMP[12], SAMP[3], SHADOW2D 244: MOV TEMP[12], TEMP[17] 245: MOV TEMP[9].y, TEMP[15].xxxx 246: MOV TEMP[9].z, TEMP[16].xxxx 247: MOV TEMP[9].w, TEMP[17].xxxx 248: DP4 TEMP[15].x, TEMP[9], IMM[6].wwww 249: MOV TEMP[16].xy, TEMP[7].xyyy 250: MOV TEMP[16].z, TEMP[6].xxxx 251: MOV TEMP[16].w, TEMP[7].wwww 252: TXL TEMP[16], TEMP[16], SAMP[3], SHADOW2D 253: MOV TEMP[9].xyz, TEMP[16] 254: ADD TEMP[5].x, TEMP[15].xxxx, TEMP[14].xxxx 255: MAD TEMP[5].x, TEMP[16].xxxx, IMM[7].xxxx, TEMP[5].xxxx 256: FSLT TEMP[14].x, TEMP[10].xxxx, IMM[1].wwww 257: UIF TEMP[14].xxxx :0 258: ADD TEMP[9].xyz, TEMP[5].zzzz, IMM[7].yzww 259: ABS TEMP[14].x, TEMP[9].xxxx 260: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 261: UIF TEMP[14].xxxx :0 262: MOV TEMP[14].x, CONST[73].xxxx 263: ELSE :0 264: MOV TEMP[14].x, TEMP[5].wwww 265: ENDIF 266: MOV TEMP[13].x, TEMP[14].xxxx 267: ABS TEMP[14].x, TEMP[9].xxxx 268: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 269: UIF TEMP[14].xxxx :0 270: MOV TEMP[14].x, CONST[73].yyyy 271: ELSE :0 272: MOV TEMP[14].x, TEMP[5].wwww 273: ENDIF 274: MOV TEMP[13].y, TEMP[14].xxxx 275: ABS TEMP[14].x, TEMP[9].xxxx 276: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 277: UIF TEMP[14].xxxx :0 278: MOV TEMP[14].x, CONST[73].zzzz 279: ELSE :0 280: MOV TEMP[14].x, TEMP[5].wwww 281: ENDIF 282: MOV TEMP[13].z, TEMP[14].xxxx 283: ABS TEMP[14].x, TEMP[9].xxxx 284: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 285: UIF TEMP[14].xxxx :0 286: MOV TEMP[14].x, CONST[73].wwww 287: ELSE :0 288: MOV TEMP[14].x, TEMP[5].wwww 289: ENDIF 290: MOV TEMP[13].w, TEMP[14].xxxx 291: MOV TEMP[4], TEMP[13] 292: ABS TEMP[14].x, TEMP[9].xxxx 293: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 294: UIF TEMP[14].xxxx :0 295: MOV TEMP[14].x, CONST[74].xxxx 296: ELSE :0 297: MOV TEMP[14].x, TEMP[5].wwww 298: ENDIF 299: MOV TEMP[13].x, TEMP[14].xxxx 300: ABS TEMP[14].x, TEMP[9].xxxx 301: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 302: UIF TEMP[14].xxxx :0 303: MOV TEMP[14].x, CONST[74].yyyy 304: ELSE :0 305: MOV TEMP[14].x, TEMP[5].wwww 306: ENDIF 307: MOV TEMP[13].y, TEMP[14].xxxx 308: ABS TEMP[14].x, TEMP[9].xxxx 309: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 310: UIF TEMP[14].xxxx :0 311: MOV TEMP[14].x, CONST[74].zzzz 312: ELSE :0 313: MOV TEMP[14].x, TEMP[5].wwww 314: ENDIF 315: MOV TEMP[13].z, TEMP[14].xxxx 316: ABS TEMP[14].x, TEMP[9].xxxx 317: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 318: UIF TEMP[14].xxxx :0 319: MOV TEMP[14].x, CONST[74].wwww 320: ELSE :0 321: MOV TEMP[14].x, TEMP[5].wwww 322: ENDIF 323: MOV TEMP[13].w, TEMP[14].xxxx 324: MOV TEMP[11], TEMP[13] 325: ABS TEMP[14].x, TEMP[9].yyyy 326: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 327: UIF TEMP[14].xxxx :0 328: MOV TEMP[14].x, CONST[77].xxxx 329: ELSE :0 330: MOV TEMP[14].x, TEMP[4].xxxx 331: ENDIF 332: MOV TEMP[13].x, TEMP[14].xxxx 333: ABS TEMP[14].x, TEMP[9].yyyy 334: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 335: UIF TEMP[14].xxxx :0 336: MOV TEMP[14].x, CONST[77].yyyy 337: ELSE :0 338: MOV TEMP[14].x, TEMP[4].yyyy 339: ENDIF 340: MOV TEMP[13].y, TEMP[14].xxxx 341: ABS TEMP[14].x, TEMP[9].yyyy 342: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 343: UIF TEMP[14].xxxx :0 344: MOV TEMP[14].x, CONST[77].zzzz 345: ELSE :0 346: MOV TEMP[14].x, TEMP[4].zzzz 347: ENDIF 348: MOV TEMP[13].z, TEMP[14].xxxx 349: ABS TEMP[14].x, TEMP[9].yyyy 350: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 351: UIF TEMP[14].xxxx :0 352: MOV TEMP[14].x, CONST[77].wwww 353: ELSE :0 354: MOV TEMP[14].x, TEMP[4].wwww 355: ENDIF 356: MOV TEMP[13].w, TEMP[14].xxxx 357: MOV TEMP[4], TEMP[13] 358: ABS TEMP[14].x, TEMP[9].yyyy 359: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 360: UIF TEMP[14].xxxx :0 361: MOV TEMP[14].x, CONST[78].xxxx 362: ELSE :0 363: MOV TEMP[14].x, TEMP[11].xxxx 364: ENDIF 365: MOV TEMP[13].x, TEMP[14].xxxx 366: ABS TEMP[14].x, TEMP[9].yyyy 367: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 368: UIF TEMP[14].xxxx :0 369: MOV TEMP[14].x, CONST[78].yyyy 370: ELSE :0 371: MOV TEMP[14].x, TEMP[11].yyyy 372: ENDIF 373: MOV TEMP[13].y, TEMP[14].xxxx 374: ABS TEMP[14].x, TEMP[9].yyyy 375: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 376: UIF TEMP[14].xxxx :0 377: MOV TEMP[14].x, CONST[78].zzzz 378: ELSE :0 379: MOV TEMP[14].x, TEMP[11].zzzz 380: ENDIF 381: MOV TEMP[13].z, TEMP[14].xxxx 382: ABS TEMP[14].x, TEMP[9].yyyy 383: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 384: UIF TEMP[14].xxxx :0 385: MOV TEMP[14].x, CONST[78].wwww 386: ELSE :0 387: MOV TEMP[14].x, TEMP[11].wwww 388: ENDIF 389: MOV TEMP[13].w, TEMP[14].xxxx 390: MOV TEMP[11], TEMP[13] 391: ABS TEMP[14].x, TEMP[9].zzzz 392: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 393: UIF TEMP[14].xxxx :0 394: MOV TEMP[14].x, CONST[81].xxxx 395: ELSE :0 396: MOV TEMP[14].x, TEMP[4].xxxx 397: ENDIF 398: MOV TEMP[13].x, TEMP[14].xxxx 399: ABS TEMP[14].x, TEMP[9].zzzz 400: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 401: UIF TEMP[14].xxxx :0 402: MOV TEMP[14].x, CONST[81].yyyy 403: ELSE :0 404: MOV TEMP[14].x, TEMP[4].yyyy 405: ENDIF 406: MOV TEMP[13].y, TEMP[14].xxxx 407: ABS TEMP[14].x, TEMP[9].zzzz 408: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 409: UIF TEMP[14].xxxx :0 410: MOV TEMP[14].x, CONST[81].zzzz 411: ELSE :0 412: MOV TEMP[14].x, TEMP[4].zzzz 413: ENDIF 414: MOV TEMP[13].z, TEMP[14].xxxx 415: ABS TEMP[14].x, TEMP[9].zzzz 416: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 417: UIF TEMP[14].xxxx :0 418: MOV TEMP[14].x, CONST[81].wwww 419: ELSE :0 420: MOV TEMP[14].x, TEMP[4].wwww 421: ENDIF 422: MOV TEMP[13].w, TEMP[14].xxxx 423: MOV TEMP[4], TEMP[13] 424: ABS TEMP[14].x, TEMP[9].zzzz 425: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 426: UIF TEMP[14].xxxx :0 427: MOV TEMP[14].x, CONST[82].xxxx 428: ELSE :0 429: MOV TEMP[14].x, TEMP[11].xxxx 430: ENDIF 431: MOV TEMP[13].x, TEMP[14].xxxx 432: ABS TEMP[14].x, TEMP[9].zzzz 433: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 434: UIF TEMP[14].xxxx :0 435: MOV TEMP[14].x, CONST[82].yyyy 436: ELSE :0 437: MOV TEMP[14].x, TEMP[11].yyyy 438: ENDIF 439: MOV TEMP[13].y, TEMP[14].xxxx 440: ABS TEMP[14].x, TEMP[9].zzzz 441: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 442: UIF TEMP[14].xxxx :0 443: MOV TEMP[14].x, CONST[82].zzzz 444: ELSE :0 445: MOV TEMP[14].x, TEMP[11].zzzz 446: ENDIF 447: MOV TEMP[13].z, TEMP[14].xxxx 448: ABS TEMP[14].x, TEMP[9].zzzz 449: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 450: UIF TEMP[14].xxxx :0 451: MOV TEMP[14].x, CONST[82].wwww 452: ELSE :0 453: MOV TEMP[14].x, TEMP[11].wwww 454: ENDIF 455: MOV TEMP[13].w, TEMP[14].xxxx 456: DP4 TEMP[4].x, TEMP[3], TEMP[4] 457: MOV_SAT TEMP[4].x, TEMP[4].xxxx 458: DP4 TEMP[14].x, TEMP[3], TEMP[13] 459: MOV_SAT TEMP[14].x, TEMP[14].xxxx 460: MOV TEMP[4].y, TEMP[14].xxxx 461: ABS TEMP[14].x, TEMP[9].xxxx 462: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 463: UIF TEMP[14].xxxx :0 464: MOV TEMP[14].x, CONST[86].zzzz 465: ELSE :0 466: MOV TEMP[14].x, TEMP[5].wwww 467: ENDIF 468: ABS TEMP[15].x, TEMP[9].xxxx 469: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 470: UIF TEMP[15].xxxx :0 471: MOV TEMP[15].x, CONST[86].wwww 472: ELSE :0 473: MOV TEMP[15].x, TEMP[5].wwww 474: ENDIF 475: MOV TEMP[13].y, TEMP[15].xxxx 476: ABS TEMP[15].x, TEMP[9].xxxx 477: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 478: UIF TEMP[15].xxxx :0 479: MOV TEMP[15].x, CONST[86].xxxx 480: ELSE :0 481: MOV TEMP[15].x, TEMP[5].wwww 482: ENDIF 483: MOV TEMP[13].z, TEMP[15].xxxx 484: ABS TEMP[15].x, TEMP[9].xxxx 485: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 486: UIF TEMP[15].xxxx :0 487: MOV TEMP[15].x, CONST[86].yyyy 488: ELSE :0 489: MOV TEMP[15].x, TEMP[5].wwww 490: ENDIF 491: MOV TEMP[13].w, TEMP[15].xxxx 492: ABS TEMP[15].x, TEMP[9].yyyy 493: FSGE TEMP[15].x, -TEMP[15].xxxx, IMM[2].wwww 494: UIF TEMP[15].xxxx :0 495: MOV TEMP[15].x, CONST[87].zzzz 496: ELSE :0 497: MOV TEMP[15].x, TEMP[14].xxxx 498: ENDIF 499: ABS TEMP[14].x, TEMP[9].yyyy 500: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 501: UIF TEMP[14].xxxx :0 502: MOV TEMP[14].x, CONST[87].wwww 503: ELSE :0 504: MOV TEMP[14].x, TEMP[13].yyyy 505: ENDIF 506: MOV TEMP[13].y, TEMP[14].xxxx 507: ABS TEMP[14].x, TEMP[9].yyyy 508: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 509: UIF TEMP[14].xxxx :0 510: MOV TEMP[14].x, CONST[87].xxxx 511: ELSE :0 512: MOV TEMP[14].x, TEMP[13].zzzz 513: ENDIF 514: MOV TEMP[13].z, TEMP[14].xxxx 515: ABS TEMP[14].x, TEMP[9].yyyy 516: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 517: UIF TEMP[14].xxxx :0 518: MOV TEMP[14].x, CONST[87].yyyy 519: ELSE :0 520: MOV TEMP[14].x, TEMP[13].wwww 521: ENDIF 522: MOV TEMP[13].w, TEMP[14].xxxx 523: ABS TEMP[14].x, TEMP[9].zzzz 524: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 525: UIF TEMP[14].xxxx :0 526: MOV TEMP[14].x, CONST[88].zzzz 527: ELSE :0 528: MOV TEMP[14].x, TEMP[15].xxxx 529: ENDIF 530: MOV TEMP[13].x, TEMP[14].xxxx 531: ABS TEMP[14].x, TEMP[9].zzzz 532: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 533: UIF TEMP[14].xxxx :0 534: MOV TEMP[14].x, CONST[88].wwww 535: ELSE :0 536: MOV TEMP[14].x, TEMP[13].yyyy 537: ENDIF 538: MOV TEMP[13].y, TEMP[14].xxxx 539: ABS TEMP[14].x, TEMP[9].zzzz 540: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 541: UIF TEMP[14].xxxx :0 542: MOV TEMP[14].x, CONST[88].xxxx 543: ELSE :0 544: MOV TEMP[14].x, TEMP[13].zzzz 545: ENDIF 546: MOV TEMP[13].z, TEMP[14].xxxx 547: ABS TEMP[14].x, TEMP[9].zzzz 548: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[2].wwww 549: UIF TEMP[14].xxxx :0 550: MOV TEMP[14].x, CONST[88].yyyy 551: ELSE :0 552: MOV TEMP[14].x, TEMP[13].wwww 553: ENDIF 554: MOV TEMP[13].w, TEMP[14].xxxx 555: MAD TEMP[7].xy, TEMP[4].xyyy, TEMP[13].xyyy, TEMP[13].zwww 556: ADD TEMP[3], TEMP[7], IMM[4].wwyy 557: TXL TEMP[13].x, TEMP[3], SAMP[3], SHADOW2D 558: MOV TEMP[3].x, TEMP[13].xxxx 559: ADD TEMP[4], TEMP[7], IMM[6].xyzz 560: ADD TEMP[11], TEMP[7], IMM[6].yxzz 561: ADD TEMP[12], TEMP[7], IMM[6].xxzz 562: TXL TEMP[13].x, TEMP[4], SAMP[3], SHADOW2D 563: MOV TEMP[3].y, TEMP[13].xxxx 564: TXL TEMP[13].x, TEMP[11], SAMP[3], SHADOW2D 565: MOV TEMP[3].z, TEMP[13].xxxx 566: TXL TEMP[13].x, TEMP[12], SAMP[3], SHADOW2D 567: MOV TEMP[3].w, TEMP[13].xxxx 568: DP4 TEMP[13].x, TEMP[3], IMM[5].wwww 569: ADD TEMP[4], TEMP[7], IMM[4].wyyy 570: TXL TEMP[14].x, TEMP[4], SAMP[3], SHADOW2D 571: MOV TEMP[4].x, TEMP[14].xxxx 572: ADD TEMP[11], TEMP[7], IMM[6].xzzz 573: TXL TEMP[11].x, TEMP[11], SAMP[3], SHADOW2D 574: ADD TEMP[12], TEMP[7], IMM[6].zxzz 575: TXL TEMP[12].x, TEMP[12], SAMP[3], SHADOW2D 576: ADD TEMP[14], TEMP[7], IMM[4].ywyy 577: TXL TEMP[14].x, TEMP[14], SAMP[3], SHADOW2D 578: MOV TEMP[4].y, TEMP[11].xxxx 579: MOV TEMP[4].z, TEMP[12].xxxx 580: MOV TEMP[4].w, TEMP[14].xxxx 581: DP4 TEMP[4].x, TEMP[4], IMM[6].wwww 582: MOV TEMP[11].xy, TEMP[7].xyyy 583: MOV TEMP[11].z, TEMP[6].xxxx 584: MOV TEMP[11].w, TEMP[7].wwww 585: TXL TEMP[6].x, TEMP[11], SAMP[3], SHADOW2D 586: ADD TEMP[3].x, TEMP[4].xxxx, TEMP[13].xxxx 587: MAD TEMP[3].x, TEMP[6].xxxx, IMM[7].xxxx, TEMP[3].xxxx 588: FSGE TEMP[4].x, TEMP[9].zzzz, IMM[2].wwww 589: UIF TEMP[4].xxxx :0 590: MOV TEMP[4].x, IMM[1].wwww 591: ELSE :0 592: MOV TEMP[4].x, TEMP[3].xxxx 593: ENDIF 594: LRP TEMP[7].x, TEMP[10].xxxx, TEMP[5].xxxx, TEMP[4].xxxx 595: MOV TEMP[5].x, TEMP[7].xxxx 596: ENDIF 597: ADD TEMP[3].xyz, -CONST[89].xyzz, IN[3].xyzz 598: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz 599: MAD TEMP[4].x, TEMP[4].xxxx, CONST[68].yyyy, CONST[68].xxxx 600: MOV_SAT TEMP[4].x, TEMP[4].xxxx 601: LRP TEMP[3].x, TEMP[4].xxxx, IMM[1].wwww, TEMP[5].xxxx 602: ADD TEMP[4].x, -TEMP[3].xxxx, IMM[1].wwww 603: MAD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx, IMM[1].wwww 604: MUL TEMP[3].xyz, TEMP[2].xxxx, TEMP[1].zyxx 605: MAD TEMP[2].x, TEMP[2].xxxx, IMM[8].xxxx, IMM[8].xxxx 606: LRP TEMP[1].xyz, TEMP[2].xxxx, TEMP[3].zyxx, TEMP[3].xyzz 607: ENDIF 608: ADD TEMP[1].xyz, TEMP[1].xyzz, CONST[31].xyzz 609: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[1].xyzz 610: ADD TEMP[1].xyz, CONST[10].xyzz, -IN[3].xyzz 611: DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[1].xyzz 612: SQRT TEMP[1].x, TEMP[1].xxxx 613: MAD TEMP[1].x, TEMP[1].xxxx, CONST[11].wwww, CONST[11].xxxx 614: MOV_SAT TEMP[1].x, TEMP[1].xxxx 615: MIN TEMP[1].x, TEMP[1].xxxx, CONST[11].zzzz 616: MUL TEMP[2].xyz, TEMP[8].xyzz, CONST[30].xxxx 617: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[1].xxxx 618: MAD TEMP[8].xyz, TEMP[8].xyzz, -CONST[30].xxxx, CONST[29].xyzz 619: MAD TEMP[0].xyz, TEMP[1].xxxx, TEMP[8].xyzz, TEMP[2].xyzz 620: MOV OUT[0], TEMP[0] 621: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %85 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %86 = load <8 x i32>, <8 x i32> addrspace(2)* %85, align 32, !tbaa !0 %87 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %88 = load <4 x i32>, <4 x i32> addrspace(2)* %87, align 16, !tbaa !0 %89 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %90 = load <8 x i32>, <8 x i32> addrspace(2)* %89, align 32, !tbaa !0 %91 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %92 = load <4 x i32>, <4 x i32> addrspace(2)* %91, align 16, !tbaa !0 %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = and i32 %5, 1 %102 = icmp ne i32 %101, 0 %103 = select i1 %102, <2 x i32> %7, <2 x i32> %8 %104 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %103) %105 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %103) %106 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %103) %107 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %103) %108 = and i32 %5, 1 %109 = icmp ne i32 %108, 0 %110 = select i1 %109, <2 x i32> %7, <2 x i32> %8 %111 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %110) %112 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %110) %113 = and i32 %5, 1 %114 = icmp ne i32 %113, 0 %115 = select i1 %114, <2 x i32> %7, <2 x i32> %8 %116 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %115) %117 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %115) %118 = and i32 %5, 1 %119 = icmp ne i32 %118, 0 %120 = select i1 %119, <2 x i32> %7, <2 x i32> %8 %121 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %120) %122 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %120) %123 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %120) %124 = and i32 %5, 1 %125 = icmp ne i32 %124, 0 %126 = select i1 %125, <2 x i32> %7, <2 x i32> %9 %127 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %126) %128 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %126) %129 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %126) %130 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %6, <2 x i32> %126) %131 = and i32 %5, 1 %132 = icmp ne i32 %131, 0 %133 = select i1 %132, <2 x i32> %7, <2 x i32> %9 %134 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %6, <2 x i32> %133) %135 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %6, <2 x i32> %133) %136 = bitcast float %111 to i32 %137 = bitcast float %112 to i32 %138 = insertelement <2 x i32> undef, i32 %136, i32 0 %139 = insertelement <2 x i32> %138, i32 %137, i32 1 %140 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %139, <8 x i32> %86, <4 x i32> %88, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = bitcast float %116 to i32 %146 = bitcast float %117 to i32 %147 = insertelement <2 x i32> undef, i32 %145, i32 0 %148 = insertelement <2 x i32> %147, i32 %146, i32 1 %149 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %148, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %150 = extractelement <4 x float> %149, i32 0 %151 = extractelement <4 x float> %149, i32 1 %152 = extractelement <4 x float> %149, i32 2 %153 = fmul float %150, 2.000000e+00 %154 = fadd float %153, -1.000000e+00 %155 = fmul float %151, 2.000000e+00 %156 = fadd float %155, -1.000000e+00 %157 = fmul float %152, 2.000000e+00 %158 = fadd float %157, -1.000000e+00 %159 = bitcast float %127 to i32 %160 = bitcast float %128 to i32 %161 = insertelement <2 x i32> undef, i32 %159, i32 0 %162 = insertelement <2 x i32> %161, i32 %160, i32 1 %163 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %162, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %164 = extractelement <4 x float> %163, i32 0 %165 = extractelement <4 x float> %163, i32 1 %166 = extractelement <4 x float> %163, i32 2 %167 = extractelement <4 x float> %163, i32 3 %168 = bitcast float %130 to i32 %169 = bitcast float %129 to i32 %170 = insertelement <2 x i32> undef, i32 %168, i32 0 %171 = insertelement <2 x i32> %170, i32 %169, i32 1 %172 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %171, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %173 = extractelement <4 x float> %172, i32 0 %174 = extractelement <4 x float> %172, i32 1 %175 = extractelement <4 x float> %172, i32 2 %176 = bitcast float %134 to i32 %177 = bitcast float %135 to i32 %178 = insertelement <2 x i32> undef, i32 %176, i32 0 %179 = insertelement <2 x i32> %178, i32 %177, i32 1 %180 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %179, <8 x i32> %90, <4 x i32> %92, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %181 = extractelement <4 x float> %180, i32 0 %182 = extractelement <4 x float> %180, i32 1 %183 = extractelement <4 x float> %180, i32 2 %184 = fmul float %141, %104 %185 = fmul float %142, %105 %186 = fmul float %143, %106 %187 = fmul float %144, %107 %188 = fmul float %154, 0x3FEA20BD80000000 %189 = fmul float %158, 0x3FE279A740000000 %190 = fadd float %188, %189 %191 = call float @llvm.AMDIL.clamp.(float %190, float 0.000000e+00, float 1.000000e+00) %192 = fmul float %154, 0xBFDA20BDA0000000 %193 = fmul float %156, 0x3FE6A09E60000000 %194 = fadd float %193, %192 %195 = fmul float %158, 0x3FE279A740000000 %196 = fadd float %194, %195 %197 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00) %198 = fmul float %154, 0xBFDA20BD20000000 %199 = fmul float %156, 0xBFE6A09E80000000 %200 = fadd float %199, %198 %201 = fmul float %158, 0x3FE279A740000000 %202 = fadd float %200, %201 %203 = call float @llvm.AMDIL.clamp.(float %202, float 0.000000e+00, float 1.000000e+00) %204 = fmul float %191, %191 %205 = fmul float %197, %197 %206 = fmul float %203, %203 %207 = fmul float %173, %205 %208 = fmul float %174, %205 %209 = fmul float %175, %205 %210 = fmul float %204, %164 %211 = fadd float %210, %207 %212 = fmul float %204, %165 %213 = fadd float %212, %208 %214 = fmul float %204, %166 %215 = fadd float %214, %209 %216 = fmul float %206, %181 %217 = fadd float %216, %211 %218 = fmul float %206, %182 %219 = fadd float %218, %213 %220 = fmul float %206, %183 %221 = fadd float %220, %215 %222 = fadd float %205, %204 %223 = fadd float %222, %206 %224 = fdiv float 1.000000e+00, %223 %225 = fmul float %224, %31 %226 = fmul float %224, %32 %227 = fmul float %224, %33 %228 = fmul float %225, %217 %229 = fmul float %226, %219 %230 = fmul float %227, %221 %231 = fcmp ogt float %167, -0.000000e+00 %232 = bitcast float %84 to i32 %233 = icmp ne i32 %232, 0 %234 = and i1 %231, %233 br i1 %234, label %IF, label %ENDIF IF: ; preds = %main_body %235 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %236 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %237 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %238 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %239 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %240 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %241 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %242 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %243 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %244 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %245 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %246 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %247 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %248 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %249 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %250 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %251 = fadd float %164, %173 %252 = fadd float %165, %174 %253 = fadd float %166, %175 %254 = fadd float %181, %251 %255 = fadd float %182, %252 %256 = fadd float %183, %253 %257 = fmul float %254, 0x3FCB333340000000 %258 = fmul float %255, 0x3FE6E48E80000000 %259 = fadd float %258, %257 %260 = fmul float %256, 0x3FB2752540000000 %261 = fadd float %259, %260 %262 = fmul float %261, 0x3FD554C980000000 %263 = fdiv float 1.000000e+00, %262 %264 = fmul float %263, %167 %265 = fadd float %121, 0.000000e+00 %266 = fadd float %122, 0.000000e+00 %267 = fadd float %123, 0.000000e+00 %268 = fmul float %121, 0.000000e+00 %269 = fadd float %268, 1.000000e+00 %270 = fmul float %265, %250 %271 = fmul float %266, %249 %272 = fadd float %270, %271 %273 = fmul float %267, %248 %274 = fadd float %272, %273 %275 = fmul float %269, %247 %276 = fadd float %274, %275 %277 = fmul float %265, %246 %278 = fmul float %266, %245 %279 = fadd float %277, %278 %280 = fmul float %267, %244 %281 = fadd float %279, %280 %282 = fmul float %269, %243 %283 = fadd float %281, %282 %284 = call float @llvm.AMDIL.clamp.(float %276, float 0.000000e+00, float 1.000000e+00) %285 = call float @llvm.AMDIL.clamp.(float %283, float 0.000000e+00, float 1.000000e+00) %286 = fsub float %284, %276 %287 = fsub float %285, %283 %288 = fadd float %286, %287 %289 = fmul float %265, %45 %290 = fmul float %266, %46 %291 = fadd float %289, %290 %292 = fmul float %267, %47 %293 = fadd float %291, %292 %294 = fmul float %269, %48 %295 = fadd float %293, %294 %296 = fmul float %265, %49 %297 = fmul float %266, %50 %298 = fadd float %296, %297 %299 = fmul float %267, %51 %300 = fadd float %298, %299 %301 = fmul float %269, %52 %302 = fadd float %300, %301 %303 = call float @llvm.AMDIL.clamp.(float %295, float 0.000000e+00, float 1.000000e+00) %304 = call float @llvm.AMDIL.clamp.(float %302, float 0.000000e+00, float 1.000000e+00) %305 = fsub float %303, %295 %306 = fsub float %304, %302 %307 = fadd float %305, %306 %308 = fmul float %265, %53 %309 = fmul float %266, %54 %310 = fadd float %308, %309 %311 = fmul float %267, %55 %312 = fadd float %310, %311 %313 = fmul float %269, %56 %314 = fadd float %312, %313 %315 = fmul float %265, %57 %316 = fmul float %266, %58 %317 = fadd float %315, %316 %318 = fmul float %267, %59 %319 = fadd float %317, %318 %320 = fmul float %269, %60 %321 = fadd float %319, %320 %322 = call float @llvm.fabs.f32(float %307) %323 = fcmp ole float %322, -0.000000e+00 %. = select i1 %323, float %295, float %314 %324 = call float @llvm.fabs.f32(float %307) %325 = fcmp ole float %324, -0.000000e+00 %temp40.0 = select i1 %325, float %302, float %321 %326 = call float @llvm.fabs.f32(float %307) %327 = fcmp ole float %326, -0.000000e+00 %.240 = select i1 %327, float 1.000000e+00, float 2.000000e+00 %328 = call float @llvm.fabs.f32(float %288) %329 = fcmp ole float %328, -0.000000e+00 %temp40.2 = select i1 %329, float %276, float %. %330 = call float @llvm.fabs.f32(float %288) %331 = fcmp ole float %330, -0.000000e+00 %.temp40.0 = select i1 %331, float %283, float %temp40.0 %332 = call float @llvm.fabs.f32(float %288) %333 = fcmp ole float %332, -0.000000e+00 %temp16.1 = select i1 %333, float 0.000000e+00, float %.240 %334 = fmul float %265, %242 %335 = fmul float %266, %241 %336 = fadd float %334, %335 %337 = fmul float %267, %240 %338 = fadd float %336, %337 %339 = fmul float %269, %239 %340 = fadd float %338, %339 %341 = fadd float %temp40.2, -5.000000e-01 %342 = fadd float %.temp40.0, -5.000000e-01 %343 = call float @llvm.fabs.f32(float %341) %344 = call float @llvm.fabs.f32(float %342) %345 = fsub float %343, %41 %346 = fsub float %344, %41 %347 = fmul float %345, %42 %348 = fmul float %346, %42 %349 = call float @llvm.AMDIL.clamp.(float %347, float 0.000000e+00, float 1.000000e+00) %350 = call float @llvm.AMDIL.clamp.(float %348, float 0.000000e+00, float 1.000000e+00) %351 = fsub float 1.000000e+00, %349 %352 = fsub float 1.000000e+00, %350 %353 = fmul float %352, %351 %354 = call float @llvm.AMDIL.clamp.(float %temp40.2, float 0.000000e+00, float 1.000000e+00) %355 = call float @llvm.AMDIL.clamp.(float %.temp40.0, float 0.000000e+00, float 1.000000e+00) %356 = fadd float %temp16.1, -1.000000e+00 %357 = fadd float %temp16.1, -2.000000e+00 %358 = call float @llvm.fabs.f32(float %temp16.1) %359 = fcmp ole float %358, -0.000000e+00 %.241 = select i1 %359, float %236, float 0.000000e+00 %360 = call float @llvm.fabs.f32(float %temp16.1) %361 = fcmp ole float %360, -0.000000e+00 %temp56.1 = select i1 %361, float %235, float 0.000000e+00 %362 = call float @llvm.fabs.f32(float %temp16.1) %363 = fcmp ole float %362, -0.000000e+00 %.242 = select i1 %363, float %238, float 0.000000e+00 %364 = call float @llvm.fabs.f32(float %temp16.1) %365 = fcmp ole float %364, -0.000000e+00 %temp56.3 = select i1 %365, float %237, float 0.000000e+00 %366 = call float @llvm.fabs.f32(float %356) %367 = fcmp ole float %366, -0.000000e+00 %..241 = select i1 %367, float %71, float %.241 %368 = call float @llvm.fabs.f32(float %356) %369 = fcmp ole float %368, -0.000000e+00 %temp48.1 = select i1 %369, float %72, float %temp56.1 %370 = call float @llvm.fabs.f32(float %356) %371 = fcmp ole float %370, -0.000000e+00 %..242 = select i1 %371, float %69, float %.242 %372 = call float @llvm.fabs.f32(float %356) %373 = fcmp ole float %372, -0.000000e+00 %temp48.3 = select i1 %373, float %70, float %temp56.3 %374 = call float @llvm.fabs.f32(float %357) %375 = fcmp ole float %374, -0.000000e+00 %...241 = select i1 %375, float %75, float %..241 %376 = call float @llvm.fabs.f32(float %357) %377 = fcmp ole float %376, -0.000000e+00 %temp48.5 = select i1 %377, float %76, float %temp48.1 %378 = call float @llvm.fabs.f32(float %357) %379 = fcmp ole float %378, -0.000000e+00 %...242 = select i1 %379, float %73, float %..242 %380 = call float @llvm.fabs.f32(float %357) %381 = fcmp ole float %380, -0.000000e+00 %temp48.7 = select i1 %381, float %74, float %temp48.3 %382 = fmul float %354, %...241 %383 = fadd float %382, %...242 %384 = fmul float %355, %temp48.5 %385 = fadd float %384, %temp48.7 %386 = fadd float %383, 0x3F40000000000000 %387 = fadd float %385, 0x3F40000000000000 %388 = fadd float %340, 0.000000e+00 %389 = bitcast float %388 to i32 %390 = bitcast float %386 to i32 %391 = bitcast float %387 to i32 %392 = insertelement <4 x i32> undef, i32 %389, i32 0 %393 = insertelement <4 x i32> %392, i32 %390, i32 1 %394 = insertelement <4 x i32> %393, i32 %391, i32 2 %395 = insertelement <4 x i32> %394, i32 0, i32 3 %396 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %395, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %397 = extractelement <4 x float> %396, i32 0 %398 = fadd float %383, 0xBF40000000000000 %399 = fadd float %385, 0x3F40000000000000 %400 = fadd float %340, 0.000000e+00 %401 = fadd float %383, 0x3F40000000000000 %402 = fadd float %385, 0xBF40000000000000 %403 = fadd float %340, 0.000000e+00 %404 = fadd float %383, 0xBF40000000000000 %405 = fadd float %385, 0xBF40000000000000 %406 = fadd float %340, 0.000000e+00 %407 = bitcast float %400 to i32 %408 = bitcast float %398 to i32 %409 = bitcast float %399 to i32 %410 = insertelement <4 x i32> undef, i32 %407, i32 0 %411 = insertelement <4 x i32> %410, i32 %408, i32 1 %412 = insertelement <4 x i32> %411, i32 %409, i32 2 %413 = insertelement <4 x i32> %412, i32 0, i32 3 %414 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %413, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %415 = extractelement <4 x float> %414, i32 0 %416 = bitcast float %403 to i32 %417 = bitcast float %401 to i32 %418 = bitcast float %402 to i32 %419 = insertelement <4 x i32> undef, i32 %416, i32 0 %420 = insertelement <4 x i32> %419, i32 %417, i32 1 %421 = insertelement <4 x i32> %420, i32 %418, i32 2 %422 = insertelement <4 x i32> %421, i32 0, i32 3 %423 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %422, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %424 = extractelement <4 x float> %423, i32 0 %425 = bitcast float %406 to i32 %426 = bitcast float %404 to i32 %427 = bitcast float %405 to i32 %428 = insertelement <4 x i32> undef, i32 %425, i32 0 %429 = insertelement <4 x i32> %428, i32 %426, i32 1 %430 = insertelement <4 x i32> %429, i32 %427, i32 2 %431 = insertelement <4 x i32> %430, i32 0, i32 3 %432 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %431, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %433 = extractelement <4 x float> %432, i32 0 %434 = fmul float %397, 6.250000e-02 %435 = fmul float %415, 6.250000e-02 %436 = fadd float %434, %435 %437 = fmul float %424, 6.250000e-02 %438 = fadd float %436, %437 %439 = fmul float %433, 6.250000e-02 %440 = fadd float %438, %439 %441 = fadd float %383, 0x3F40000000000000 %442 = fadd float %385, 0.000000e+00 %443 = fadd float %340, 0.000000e+00 %444 = bitcast float %443 to i32 %445 = bitcast float %441 to i32 %446 = bitcast float %442 to i32 %447 = insertelement <4 x i32> undef, i32 %444, i32 0 %448 = insertelement <4 x i32> %447, i32 %445, i32 1 %449 = insertelement <4 x i32> %448, i32 %446, i32 2 %450 = insertelement <4 x i32> %449, i32 0, i32 3 %451 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %450, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %452 = extractelement <4 x float> %451, i32 0 %453 = fadd float %383, 0xBF40000000000000 %454 = fadd float %385, 0.000000e+00 %455 = fadd float %340, 0.000000e+00 %456 = bitcast float %455 to i32 %457 = bitcast float %453 to i32 %458 = bitcast float %454 to i32 %459 = insertelement <4 x i32> undef, i32 %456, i32 0 %460 = insertelement <4 x i32> %459, i32 %457, i32 1 %461 = insertelement <4 x i32> %460, i32 %458, i32 2 %462 = insertelement <4 x i32> %461, i32 0, i32 3 %463 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %462, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %464 = extractelement <4 x float> %463, i32 0 %465 = fadd float %383, 0.000000e+00 %466 = fadd float %385, 0xBF40000000000000 %467 = fadd float %340, 0.000000e+00 %468 = bitcast float %467 to i32 %469 = bitcast float %465 to i32 %470 = bitcast float %466 to i32 %471 = insertelement <4 x i32> undef, i32 %468, i32 0 %472 = insertelement <4 x i32> %471, i32 %469, i32 1 %473 = insertelement <4 x i32> %472, i32 %470, i32 2 %474 = insertelement <4 x i32> %473, i32 0, i32 3 %475 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %474, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %476 = extractelement <4 x float> %475, i32 0 %477 = fadd float %383, 0.000000e+00 %478 = fadd float %385, 0x3F40000000000000 %479 = fadd float %340, 0.000000e+00 %480 = bitcast float %479 to i32 %481 = bitcast float %477 to i32 %482 = bitcast float %478 to i32 %483 = insertelement <4 x i32> undef, i32 %480, i32 0 %484 = insertelement <4 x i32> %483, i32 %481, i32 1 %485 = insertelement <4 x i32> %484, i32 %482, i32 2 %486 = insertelement <4 x i32> %485, i32 0, i32 3 %487 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %486, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %488 = extractelement <4 x float> %487, i32 0 %489 = fmul float %452, 1.250000e-01 %490 = fmul float %464, 1.250000e-01 %491 = fadd float %489, %490 %492 = fmul float %476, 1.250000e-01 %493 = fadd float %491, %492 %494 = fmul float %488, 1.250000e-01 %495 = fadd float %493, %494 %496 = bitcast float %340 to i32 %497 = bitcast float %383 to i32 %498 = bitcast float %385 to i32 %499 = insertelement <4 x i32> undef, i32 %496, i32 0 %500 = insertelement <4 x i32> %499, i32 %497, i32 1 %501 = insertelement <4 x i32> %500, i32 %498, i32 2 %502 = insertelement <4 x i32> %501, i32 0, i32 3 %503 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %502, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %504 = extractelement <4 x float> %503, i32 0 %505 = fadd float %495, %440 %506 = fmul float %504, 2.500000e-01 %507 = fadd float %506, %505 %508 = fcmp olt float %353, 1.000000e+00 br i1 %508, label %IF127, label %ENDIF126 ENDIF: ; preds = %main_body, %ENDIF126 %temp4.0 = phi float [ %795, %ENDIF126 ], [ %228, %main_body ] %temp5.0 = phi float [ %799, %ENDIF126 ], [ %229, %main_body ] %temp6.0 = phi float [ %803, %ENDIF126 ], [ %230, %main_body ] %509 = fadd float %temp4.0, %38 %510 = fadd float %temp5.0, %39 %511 = fadd float %temp6.0, %40 %512 = fmul float %184, %509 %513 = fmul float %185, %510 %514 = fmul float %186, %511 %515 = fsub float %25, %121 %516 = fsub float %26, %122 %517 = fsub float %27, %123 %518 = fmul float %515, %515 %519 = fmul float %516, %516 %520 = fadd float %519, %518 %521 = fmul float %517, %517 %522 = fadd float %520, %521 %523 = call float @llvm.sqrt.f32(float %522) %524 = fmul float %523, %30 %525 = fadd float %524, %28 %526 = call float @llvm.AMDIL.clamp.(float %525, float 0.000000e+00, float 1.000000e+00) %527 = call float @llvm.minnum.f32(float %526, float %29) %528 = fmul float %512, %37 %529 = fmul float %513, %37 %530 = fmul float %514, %37 %531 = fmul float %527, %527 %532 = fmul float %37, %512 %533 = fsub float %34, %532 %534 = fmul float %37, %513 %535 = fsub float %35, %534 %536 = fmul float %37, %514 %537 = fsub float %36, %536 %538 = fmul float %531, %533 %539 = fadd float %538, %528 %540 = fmul float %531, %535 %541 = fadd float %540, %529 %542 = fmul float %531, %537 %543 = fadd float %542, %530 %544 = call i32 @llvm.SI.packf16(float %539, float %541) %545 = bitcast i32 %544 to float %546 = call i32 @llvm.SI.packf16(float %543, float %187) %547 = bitcast i32 %546 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %545, float %547, float %545, float %547) ret void IF127: ; preds = %IF %548 = fadd float %temp16.1, 0.000000e+00 %549 = fadd float %temp16.1, -1.000000e+00 %550 = fadd float %temp16.1, -2.000000e+00 %551 = call float @llvm.fabs.f32(float %548) %552 = fcmp ole float %551, -0.000000e+00 %.243 = select i1 %552, float %45, float 0.000000e+00 %553 = call float @llvm.fabs.f32(float %548) %554 = fcmp ole float %553, -0.000000e+00 %temp56.6 = select i1 %554, float %46, float 0.000000e+00 %555 = call float @llvm.fabs.f32(float %548) %556 = fcmp ole float %555, -0.000000e+00 %.244 = select i1 %556, float %47, float 0.000000e+00 %557 = call float @llvm.fabs.f32(float %548) %558 = fcmp ole float %557, -0.000000e+00 %temp56.8 = select i1 %558, float %48, float 0.000000e+00 %559 = call float @llvm.fabs.f32(float %548) %560 = fcmp ole float %559, -0.000000e+00 %.245 = select i1 %560, float %49, float 0.000000e+00 %561 = call float @llvm.fabs.f32(float %548) %562 = fcmp ole float %561, -0.000000e+00 %temp56.10 = select i1 %562, float %50, float 0.000000e+00 %563 = call float @llvm.fabs.f32(float %548) %564 = fcmp ole float %563, -0.000000e+00 %.246 = select i1 %564, float %51, float 0.000000e+00 %565 = call float @llvm.fabs.f32(float %548) %566 = fcmp ole float %565, -0.000000e+00 %temp56.12 = select i1 %566, float %52, float 0.000000e+00 %567 = call float @llvm.fabs.f32(float %549) %568 = fcmp ole float %567, -0.000000e+00 %..243 = select i1 %568, float %53, float %.243 %569 = call float @llvm.fabs.f32(float %549) %570 = fcmp ole float %569, -0.000000e+00 %temp56.14 = select i1 %570, float %54, float %temp56.6 %571 = call float @llvm.fabs.f32(float %549) %572 = fcmp ole float %571, -0.000000e+00 %..244 = select i1 %572, float %55, float %.244 %573 = call float @llvm.fabs.f32(float %549) %574 = fcmp ole float %573, -0.000000e+00 %temp56.16 = select i1 %574, float %56, float %temp56.8 %575 = call float @llvm.fabs.f32(float %549) %576 = fcmp ole float %575, -0.000000e+00 %..245 = select i1 %576, float %57, float %.245 %577 = call float @llvm.fabs.f32(float %549) %578 = fcmp ole float %577, -0.000000e+00 %temp56.18 = select i1 %578, float %58, float %temp56.10 %579 = call float @llvm.fabs.f32(float %549) %580 = fcmp ole float %579, -0.000000e+00 %..246 = select i1 %580, float %59, float %.246 %581 = call float @llvm.fabs.f32(float %549) %582 = fcmp ole float %581, -0.000000e+00 %temp56.20 = select i1 %582, float %60, float %temp56.12 %583 = call float @llvm.fabs.f32(float %550) %584 = fcmp ole float %583, -0.000000e+00 %...243 = select i1 %584, float %61, float %..243 %585 = call float @llvm.fabs.f32(float %550) %586 = fcmp ole float %585, -0.000000e+00 %temp56.22 = select i1 %586, float %62, float %temp56.14 %587 = call float @llvm.fabs.f32(float %550) %588 = fcmp ole float %587, -0.000000e+00 %...244 = select i1 %588, float %63, float %..244 %589 = call float @llvm.fabs.f32(float %550) %590 = fcmp ole float %589, -0.000000e+00 %temp56.24 = select i1 %590, float %64, float %temp56.16 %591 = call float @llvm.fabs.f32(float %550) %592 = fcmp ole float %591, -0.000000e+00 %...245 = select i1 %592, float %65, float %..245 %593 = call float @llvm.fabs.f32(float %550) %594 = fcmp ole float %593, -0.000000e+00 %temp56.26 = select i1 %594, float %66, float %temp56.18 %595 = call float @llvm.fabs.f32(float %550) %596 = fcmp ole float %595, -0.000000e+00 %...246 = select i1 %596, float %67, float %..246 %597 = call float @llvm.fabs.f32(float %550) %598 = fcmp ole float %597, -0.000000e+00 %temp56.28 = select i1 %598, float %68, float %temp56.20 %599 = fmul float %265, %...243 %600 = fmul float %266, %temp56.22 %601 = fadd float %599, %600 %602 = fmul float %267, %...244 %603 = fadd float %601, %602 %604 = fmul float %269, %temp56.24 %605 = fadd float %603, %604 %606 = call float @llvm.AMDIL.clamp.(float %605, float 0.000000e+00, float 1.000000e+00) %607 = fmul float %265, %...245 %608 = fmul float %266, %temp56.26 %609 = fadd float %607, %608 %610 = fmul float %267, %...246 %611 = fadd float %609, %610 %612 = fmul float %269, %temp56.28 %613 = fadd float %611, %612 %614 = call float @llvm.AMDIL.clamp.(float %613, float 0.000000e+00, float 1.000000e+00) %615 = call float @llvm.fabs.f32(float %548) %616 = fcmp ole float %615, -0.000000e+00 %.247 = select i1 %616, float %71, float 0.000000e+00 %617 = call float @llvm.fabs.f32(float %548) %618 = fcmp ole float %617, -0.000000e+00 %temp60.0 = select i1 %618, float %72, float 0.000000e+00 %619 = call float @llvm.fabs.f32(float %548) %620 = fcmp ole float %619, -0.000000e+00 %.248 = select i1 %620, float %69, float 0.000000e+00 %621 = call float @llvm.fabs.f32(float %548) %622 = fcmp ole float %621, -0.000000e+00 %temp60.2 = select i1 %622, float %70, float 0.000000e+00 %623 = call float @llvm.fabs.f32(float %549) %624 = fcmp ole float %623, -0.000000e+00 %..247 = select i1 %624, float %75, float %.247 %625 = call float @llvm.fabs.f32(float %549) %626 = fcmp ole float %625, -0.000000e+00 %temp56.30 = select i1 %626, float %76, float %temp60.0 %627 = call float @llvm.fabs.f32(float %549) %628 = fcmp ole float %627, -0.000000e+00 %..248 = select i1 %628, float %73, float %.248 %629 = call float @llvm.fabs.f32(float %549) %630 = fcmp ole float %629, -0.000000e+00 %temp56.32 = select i1 %630, float %74, float %temp60.2 %631 = call float @llvm.fabs.f32(float %550) %632 = fcmp ole float %631, -0.000000e+00 %...247 = select i1 %632, float %79, float %..247 %633 = call float @llvm.fabs.f32(float %550) %634 = fcmp ole float %633, -0.000000e+00 %temp56.34 = select i1 %634, float %80, float %temp56.30 %635 = call float @llvm.fabs.f32(float %550) %636 = fcmp ole float %635, -0.000000e+00 %...248 = select i1 %636, float %77, float %..248 %637 = call float @llvm.fabs.f32(float %550) %638 = fcmp ole float %637, -0.000000e+00 %temp56.36 = select i1 %638, float %78, float %temp56.32 %639 = fmul float %606, %...247 %640 = fadd float %639, %...248 %641 = fmul float %614, %temp56.34 %642 = fadd float %641, %temp56.36 %643 = fadd float %640, 0x3F40000000000000 %644 = fadd float %642, 0x3F40000000000000 %645 = fadd float %340, 0.000000e+00 %646 = bitcast float %645 to i32 %647 = bitcast float %643 to i32 %648 = bitcast float %644 to i32 %649 = insertelement <4 x i32> undef, i32 %646, i32 0 %650 = insertelement <4 x i32> %649, i32 %647, i32 1 %651 = insertelement <4 x i32> %650, i32 %648, i32 2 %652 = insertelement <4 x i32> %651, i32 0, i32 3 %653 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %652, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %654 = extractelement <4 x float> %653, i32 0 %655 = fadd float %640, 0xBF40000000000000 %656 = fadd float %642, 0x3F40000000000000 %657 = fadd float %340, 0.000000e+00 %658 = fadd float %640, 0x3F40000000000000 %659 = fadd float %642, 0xBF40000000000000 %660 = fadd float %340, 0.000000e+00 %661 = fadd float %640, 0xBF40000000000000 %662 = fadd float %642, 0xBF40000000000000 %663 = fadd float %340, 0.000000e+00 %664 = bitcast float %657 to i32 %665 = bitcast float %655 to i32 %666 = bitcast float %656 to i32 %667 = insertelement <4 x i32> undef, i32 %664, i32 0 %668 = insertelement <4 x i32> %667, i32 %665, i32 1 %669 = insertelement <4 x i32> %668, i32 %666, i32 2 %670 = insertelement <4 x i32> %669, i32 0, i32 3 %671 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %670, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %672 = extractelement <4 x float> %671, i32 0 %673 = bitcast float %660 to i32 %674 = bitcast float %658 to i32 %675 = bitcast float %659 to i32 %676 = insertelement <4 x i32> undef, i32 %673, i32 0 %677 = insertelement <4 x i32> %676, i32 %674, i32 1 %678 = insertelement <4 x i32> %677, i32 %675, i32 2 %679 = insertelement <4 x i32> %678, i32 0, i32 3 %680 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %679, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %681 = extractelement <4 x float> %680, i32 0 %682 = bitcast float %663 to i32 %683 = bitcast float %661 to i32 %684 = bitcast float %662 to i32 %685 = insertelement <4 x i32> undef, i32 %682, i32 0 %686 = insertelement <4 x i32> %685, i32 %683, i32 1 %687 = insertelement <4 x i32> %686, i32 %684, i32 2 %688 = insertelement <4 x i32> %687, i32 0, i32 3 %689 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %688, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %690 = extractelement <4 x float> %689, i32 0 %691 = fmul float %654, 6.250000e-02 %692 = fmul float %672, 6.250000e-02 %693 = fadd float %691, %692 %694 = fmul float %681, 6.250000e-02 %695 = fadd float %693, %694 %696 = fmul float %690, 6.250000e-02 %697 = fadd float %695, %696 %698 = fadd float %640, 0x3F40000000000000 %699 = fadd float %642, 0.000000e+00 %700 = fadd float %340, 0.000000e+00 %701 = bitcast float %700 to i32 %702 = bitcast float %698 to i32 %703 = bitcast float %699 to i32 %704 = insertelement <4 x i32> undef, i32 %701, i32 0 %705 = insertelement <4 x i32> %704, i32 %702, i32 1 %706 = insertelement <4 x i32> %705, i32 %703, i32 2 %707 = insertelement <4 x i32> %706, i32 0, i32 3 %708 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %707, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %709 = extractelement <4 x float> %708, i32 0 %710 = fadd float %640, 0xBF40000000000000 %711 = fadd float %642, 0.000000e+00 %712 = fadd float %340, 0.000000e+00 %713 = bitcast float %712 to i32 %714 = bitcast float %710 to i32 %715 = bitcast float %711 to i32 %716 = insertelement <4 x i32> undef, i32 %713, i32 0 %717 = insertelement <4 x i32> %716, i32 %714, i32 1 %718 = insertelement <4 x i32> %717, i32 %715, i32 2 %719 = insertelement <4 x i32> %718, i32 0, i32 3 %720 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %719, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %721 = extractelement <4 x float> %720, i32 0 %722 = fadd float %640, 0.000000e+00 %723 = fadd float %642, 0xBF40000000000000 %724 = fadd float %340, 0.000000e+00 %725 = bitcast float %724 to i32 %726 = bitcast float %722 to i32 %727 = bitcast float %723 to i32 %728 = insertelement <4 x i32> undef, i32 %725, i32 0 %729 = insertelement <4 x i32> %728, i32 %726, i32 1 %730 = insertelement <4 x i32> %729, i32 %727, i32 2 %731 = insertelement <4 x i32> %730, i32 0, i32 3 %732 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %731, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %733 = extractelement <4 x float> %732, i32 0 %734 = fadd float %640, 0.000000e+00 %735 = fadd float %642, 0x3F40000000000000 %736 = fadd float %340, 0.000000e+00 %737 = bitcast float %736 to i32 %738 = bitcast float %734 to i32 %739 = bitcast float %735 to i32 %740 = insertelement <4 x i32> undef, i32 %737, i32 0 %741 = insertelement <4 x i32> %740, i32 %738, i32 1 %742 = insertelement <4 x i32> %741, i32 %739, i32 2 %743 = insertelement <4 x i32> %742, i32 0, i32 3 %744 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %743, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %745 = extractelement <4 x float> %744, i32 0 %746 = fmul float %709, 1.250000e-01 %747 = fmul float %721, 1.250000e-01 %748 = fadd float %746, %747 %749 = fmul float %733, 1.250000e-01 %750 = fadd float %748, %749 %751 = fmul float %745, 1.250000e-01 %752 = fadd float %750, %751 %753 = bitcast float %340 to i32 %754 = bitcast float %640 to i32 %755 = bitcast float %642 to i32 %756 = insertelement <4 x i32> undef, i32 %753, i32 0 %757 = insertelement <4 x i32> %756, i32 %754, i32 1 %758 = insertelement <4 x i32> %757, i32 %755, i32 2 %759 = insertelement <4 x i32> %758, i32 0, i32 3 %760 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %759, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %761 = extractelement <4 x float> %760, i32 0 %762 = fadd float %752, %697 %763 = fmul float %761, 2.500000e-01 %764 = fadd float %763, %762 %765 = fcmp oge float %550, 0.000000e+00 %.249 = select i1 %765, float 1.000000e+00, float %764 %766 = fsub float 1.000000e+00, %353 %767 = fmul float %507, %353 %768 = fmul float %.249, %766 %769 = fadd float %767, %768 br label %ENDIF126 ENDIF126: ; preds = %IF, %IF127 %temp20.0 = phi float [ %769, %IF127 ], [ %507, %IF ] %770 = fsub float %121, %81 %771 = fsub float %122, %82 %772 = fsub float %123, %83 %773 = fmul float %770, %770 %774 = fmul float %771, %771 %775 = fadd float %774, %773 %776 = fmul float %772, %772 %777 = fadd float %775, %776 %778 = fmul float %777, %44 %779 = fadd float %778, %43 %780 = call float @llvm.AMDIL.clamp.(float %779, float 0.000000e+00, float 1.000000e+00) %781 = fsub float 1.000000e+00, %780 %782 = fmul float %temp20.0, %781 %783 = fadd float %780, %782 %784 = fsub float 1.000000e+00, %783 %785 = fmul float %784, %264 %786 = fsub float 1.000000e+00, %785 %787 = fmul float %786, %230 %788 = fmul float %786, %229 %789 = fmul float %786, %228 %790 = fmul float %786, 5.000000e-01 %791 = fadd float %790, 5.000000e-01 %792 = fsub float 1.000000e+00, %791 %793 = fmul float %789, %791 %794 = fmul float %787, %792 %795 = fadd float %793, %794 %796 = fsub float 1.000000e+00, %791 %797 = fmul float %788, %791 %798 = fmul float %788, %796 %799 = fadd float %797, %798 %800 = fsub float 1.000000e+00, %791 %801 = fmul float %787, %791 %802 = fmul float %789, %800 %803 = fadd float %801, %802 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_wqm_b64 exec, exec ; BEFE077E s_load_dwordx4 s[12:15], s[2:3], 0x0 ; C00A0301 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[32:39], s[6:7], 0x0 ; C00E0803 00000000 s_nop 0 ; BF800000 s_load_dwordx8 s[16:23], s[6:7], 0x20 ; C00E0403 00000020 s_nop 0 ; BF800000 s_load_dwordx8 s[24:31], s[6:7], 0x40 ; C00E0603 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[44:47], s[4:5], 0x0 ; C00A0B02 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[0:3], s[4:5], 0x10 ; C00A0002 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[40:43], s[4:5], 0x20 ; C00A0A02 00000020 s_and_b32 s8, 1, s9 ; 86080981 v_cmp_eq_i32_e64 vcc, 1, s8 ; D0C2006A 00001081 v_cndmask_b32_e32 v10, v2, v0 ; 00140102 s_mov_b32 m0, s10 ; BEFC000A v_cndmask_b32_e32 v11, v3, v1 ; 00160303 v_interp_p1_f32 v2, v10, 0, 0, [m0] ; D408000A v_interp_p2_f32 v2, [v2], v11, 0, 0, [m0] ; D409000B v_interp_p1_f32 v3, v10, 1, 0, [m0] ; D40C010A v_interp_p2_f32 v3, [v3], v11, 1, 0, [m0] ; D40D010B v_interp_p1_f32 v6, v10, 2, 0, [m0] ; D418020A v_interp_p2_f32 v6, [v6], v11, 2, 0, [m0] ; D419020B v_interp_p1_f32 v7, v10, 3, 0, [m0] ; D41C030A v_interp_p2_f32 v7, [v7], v11, 3, 0, [m0] ; D41D030B v_interp_p1_f32 v12, v10, 0, 1, [m0] ; D430040A v_interp_p2_f32 v12, [v12], v11, 0, 1, [m0] ; D431040B v_interp_p1_f32 v13, v10, 1, 1, [m0] ; D434050A v_interp_p2_f32 v13, [v13], v11, 1, 1, [m0] ; D435050B v_interp_p1_f32 v15, v10, 0, 2, [m0] ; D43C080A v_interp_p2_f32 v15, [v15], v11, 0, 2, [m0] ; D43D080B v_interp_p1_f32 v16, v10, 1, 2, [m0] ; D440090A v_interp_p2_f32 v16, [v16], v11, 1, 2, [m0] ; D441090B v_interp_p1_f32 v8, v10, 0, 3, [m0] ; D4200C0A v_interp_p2_f32 v8, [v8], v11, 0, 3, [m0] ; D4210C0B v_interp_p1_f32 v9, v10, 1, 3, [m0] ; D4240D0A v_interp_p2_f32 v9, [v9], v11, 1, 3, [m0] ; D4250D0B v_interp_p1_f32 v10, v10, 2, 3, [m0] ; D4280E0A v_interp_p2_f32 v10, [v10], v11, 2, 3, [m0] ; D4290E0B v_cndmask_b32_e32 v0, v4, v0 ; 00000104 v_cndmask_b32_e32 v1, v5, v1 ; 00020305 v_interp_p1_f32 v4, v0, 0, 4, [m0] ; D4101000 v_interp_p2_f32 v4, [v4], v1, 0, 4, [m0] ; D4111001 v_interp_p1_f32 v5, v0, 1, 4, [m0] ; D4141100 v_interp_p2_f32 v5, [v5], v1, 1, 4, [m0] ; D4151101 v_interp_p1_f32 v20, v0, 2, 4, [m0] ; D4501200 v_interp_p2_f32 v20, [v20], v1, 2, 4, [m0] ; D4511201 v_interp_p1_f32 v19, v0, 3, 4, [m0] ; D44C1300 v_interp_p2_f32 v19, [v19], v1, 3, 4, [m0] ; D44D1301 v_interp_p1_f32 v22, v0, 0, 5, [m0] ; D4581400 v_interp_p2_f32 v22, [v22], v1, 0, 5, [m0] ; D4591401 v_interp_p1_f32 v23, v0, 1, 5, [m0] ; D45C1500 v_interp_p2_f32 v23, [v23], v1, 1, 5, [m0] ; D45D1501 s_waitcnt lgkmcnt(0) ; BF8C007F image_sample v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[32:39], s[44:47] ; F0800F00 01680B0C s_nop 0 ; BF800000 image_sample v[15:17], 7, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[24:31], s[40:43] ; F0800700 01460F0F s_waitcnt vmcnt(0) ; BF8C0770 v_add_f32_e32 v0, v15, v15 ; 02001F0F v_mad_f32 v1, 2.0, v15, -1.0 ; D1C10001 03CE1EF4 v_mad_f32 v15, 2.0, v16, -1.0 ; D1C1000F 03CE20F4 v_add_f32_e32 v21, v17, v17 ; 022A2311 v_mad_f32 v16, 2.0, v17, -1.0 ; D1C10010 03CE22F4 v_mov_b32_e32 v17, 0x3ed105ed ; 7E2202FF 3ED105ED v_madmk_f32_e32 v17, v0, v17, 0xbed105ed ; 2E222300 BED105ED v_mov_b32_e32 v18, 0x3ed105e9 ; 7E2402FF 3ED105E9 v_madmk_f32_e32 v0, v0, v18, 0xbed105e9 ; 2E002500 BED105E9 v_mov_b32_e32 v24, 0x3f13cd3a ; 7E3002FF 3F13CD3A v_madmk_f32_e32 v25, v15, v17, 0x3f3504f3 ; 2E32230F 3F3504F3 v_mac_f32_e32 v25, v24, v16 ; 2C322118 v_madmk_f32_e32 v0, v15, v0, 0xbf3504f4 ; 2E00010F BF3504F4 v_mac_f32_e32 v0, v24, v16 ; 2C002118 image_sample v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[16:23], s[0:3] ; F0800F00 00040F04 v_madak_f32_e32 v4, v21, v24, 0xbf13cd3a ; 30083115 BF13CD3A image_sample v[19:21], 7, 0, 0, 0, 0, 0, 0, 0, v[19:20], s[16:23], s[0:3] ; F0800700 00041313 v_madmk_f32_e32 v1, v1, v4, 0x3f5105ec ; 2E020901 3F5105EC v_add_f32_e64 v1, 0, v1 clamp ; D1018001 00020280 v_add_f32_e64 v4, 0, v25 clamp ; D1018004 00023280 v_add_f32_e64 v0, 0, v0 clamp ; D1018000 00020080 v_mul_f32_e32 v1, v1, v1 ; 0A020301 v_mul_f32_e32 v5, v4, v4 ; 0A0A0904 s_waitcnt vmcnt(0) ; BF8C0770 v_mul_f32_e32 v25, v5, v19 ; 0A322705 v_mul_f32_e32 v26, v5, v20 ; 0A342905 v_mul_f32_e32 v5, v5, v21 ; 0A0A2B05 v_mac_f32_e32 v25, v15, v1 ; 2C32030F v_mac_f32_e32 v26, v16, v1 ; 2C340310 v_mac_f32_e32 v5, v17, v1 ; 2C0A0311 image_sample v[22:24], 7, 0, 0, 0, 0, 0, 0, 0, v[22:23], s[16:23], s[0:3] ; F0800700 00041616 v_mul_f32_e32 v27, v0, v0 ; 0A360100 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v25, v22, v27 ; 2C323716 v_mac_f32_e32 v26, v23, v27 ; 2C343717 s_buffer_load_dword s0, s[12:15], 0xc0 ; C0220006 000000C0 v_mac_f32_e32 v5, v24, v27 ; 2C0A3718 s_buffer_load_dword s1, s[12:15], 0xc4 ; C0220046 000000C4 v_mac_f32_e32 v1, v4, v4 ; 2C020904 s_buffer_load_dword s2, s[12:15], 0xc8 ; C0220086 000000C8 v_mac_f32_e32 v1, v0, v0 ; 2C020100 v_rcp_f32_e32 v0, v1 ; 7E004501 s_buffer_load_dword s9, s[12:15], 0xbc ; C0220246 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x5a0 ; C02200C6 000005A0 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[12:15], 0x1e0 ; C0220206 000001E0 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v1, s0, v0 ; 0A020000 v_mul_f32_e32 v4, v25, v1 ; 0A080319 v_mul_f32_e32 v1, s1, v0 ; 0A020001 v_mul_f32_e32 v1, v26, v1 ; 0A02031A v_mul_f32_e32 v0, s2, v0 ; 0A000002 v_mul_f32_e32 v0, v5, v0 ; 0A000105 v_mov_b32_e32 v5, 0x80000000 ; 7E0A02FF 80000000 v_cmp_lt_f32_e32 vcc, v5, v18 ; 7C822505 v_cmp_ne_i32_e64 s[0:1], 0, s3 ; D0C50000 00000680 s_and_b64 s[0:1], vcc, s[0:1] ; 8680006A s_and_saveexec_b64 s[10:11], s[0:1] ; BE8A2000 s_xor_b64 s[10:11], exec, s[10:11] ; 888A0A7E s_cbranch_execz BB0_4 ; BF880000 s_buffer_load_dword s1, s[12:15], 0x438 ; C0220046 00000438 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x43c ; C0220086 0000043C s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x440 ; C0220406 00000440 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x444 ; C0220006 00000444 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0x450 ; C02200C6 00000450 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[12:15], 0x4a0 ; C0220506 000004A0 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[12:15], 0x4a4 ; C0220546 000004A4 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[12:15], 0x4a8 ; C0220586 000004A8 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[12:15], 0x4ac ; C02205C6 000004AC s_nop 0 ; BF800000 s_buffer_load_dword s24, s[12:15], 0x4d0 ; C0220606 000004D0 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[12:15], 0x4d4 ; C0220646 000004D4 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[12:15], 0x4d8 ; C02206C6 000004D8 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[12:15], 0x4dc ; C0220746 000004DC s_nop 0 ; BF800000 s_buffer_load_dword s31, s[12:15], 0x4e0 ; C02207C6 000004E0 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[12:15], 0x4e4 ; C0220846 000004E4 s_nop 0 ; BF800000 s_buffer_load_dword s34, s[12:15], 0x4e8 ; C0220886 000004E8 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[12:15], 0x4ec ; C02208C6 000004EC s_nop 0 ; BF800000 s_buffer_load_dword s56, s[12:15], 0x550 ; C0220E06 00000550 s_nop 0 ; BF800000 s_buffer_load_dword s57, s[12:15], 0x554 ; C0220E46 00000554 s_nop 0 ; BF800000 s_buffer_load_dword s58, s[12:15], 0x558 ; C0220E86 00000558 s_nop 0 ; BF800000 s_buffer_load_dword s37, s[12:15], 0x570 ; C0220946 00000570 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[12:15], 0x574 ; C02209C6 00000574 s_nop 0 ; BF800000 s_buffer_load_dword s41, s[12:15], 0x578 ; C0220A46 00000578 s_nop 0 ; BF800000 s_buffer_load_dword s43, s[12:15], 0x57c ; C0220AC6 0000057C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[12:15], 0x590 ; C02204C6 00000590 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[12:15], 0x594 ; C0220486 00000594 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x598 ; C0220446 00000598 s_nop 0 ; BF800000 s_load_dwordx8 s[44:51], s[6:7], 0x60 ; C00E0B03 00000060 s_nop 0 ; BF800000 s_load_dwordx4 s[52:55], s[4:5], 0x30 ; C00A0D02 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s59, s[12:15], 0x55c ; C0220EC6 0000055C s_nop 0 ; BF800000 s_buffer_load_dword s36, s[12:15], 0x560 ; C0220906 00000560 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[12:15], 0x564 ; C0220986 00000564 s_nop 0 ; BF800000 s_buffer_load_dword s40, s[12:15], 0x568 ; C0220A06 00000568 s_nop 0 ; BF800000 s_buffer_load_dword s42, s[12:15], 0x56c ; C0220A86 0000056C s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x47c ; C0220F06 0000047C s_nop 0 ; BF800000 s_buffer_load_dword s26, s[12:15], 0x490 ; C0220686 00000490 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[12:15], 0x494 ; C0220706 00000494 s_nop 0 ; BF800000 s_buffer_load_dword s30, s[12:15], 0x498 ; C0220786 00000498 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[12:15], 0x49c ; C0220806 0000049C s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x468 ; C0220F46 00000468 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x46c ; C0220F86 0000046C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x470 ; C0220FC6 00000470 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x474 ; C0221006 00000474 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x478 ; C0221046 00000478 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x454 ; C0221086 00000454 s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x458 ; C02210C6 00000458 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x45c ; C0221106 0000045C s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x460 ; C0221146 00000460 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x464 ; C0221186 00000464 v_add_f32_e32 v29, 0, v9 ; 023A1280 s_waitcnt lgkmcnt(0) ; BF8C007F v_mul_f32_e32 v25, s66, v29 ; 0A323A42 v_add_f32_e32 v31, 0, v8 ; 023E1080 v_add_f32_e32 v30, 0, v10 ; 023C1480 v_mad_f32 v5, 0, v8, 1.0 ; D1C10005 03CA1080 v_mac_f32_e32 v25, s3, v31 ; 2C323E03 v_mac_f32_e32 v25, s67, v30 ; 2C323C43 v_mac_f32_e32 v25, s68, v5 ; 2C320A44 v_mul_f32_e32 v26, s70, v29 ; 0A343A46 v_mac_f32_e32 v26, s69, v31 ; 2C343E45 v_mac_f32_e32 v26, s61, v30 ; 2C343C3D v_mac_f32_e32 v26, s62, v5 ; 2C340A3E v_add_f32_e64 v27, 0, v25 clamp ; D101801B 00023280 v_add_f32_e64 v28, 0, v26 clamp ; D101801C 00023480 v_subrev_f32_e32 v27, v25, v27 ; 06363719 v_subrev_f32_e32 v28, v26, v28 ; 0638391A v_add_f32_e32 v27, v28, v27 ; 0236371C v_mul_f32_e32 v28, s28, v29 ; 0A383A1C v_mac_f32_e32 v28, s26, v31 ; 2C383E1A v_mac_f32_e32 v28, s30, v30 ; 2C383C1E v_mac_f32_e32 v28, s32, v5 ; 2C380A20 v_mul_f32_e32 v32, s21, v29 ; 0A403A15 v_mac_f32_e32 v32, s20, v31 ; 2C403E14 v_mac_f32_e32 v32, s22, v30 ; 2C403C16 v_mac_f32_e32 v32, s23, v5 ; 2C400A17 v_add_f32_e64 v33, 0, v28 clamp ; D1018021 00023880 v_add_f32_e64 v34, 0, v32 clamp ; D1018022 00024080 v_subrev_f32_e32 v33, v28, v33 ; 0642431C v_subrev_f32_e32 v34, v32, v34 ; 06444520 v_add_f32_e32 v33, v34, v33 ; 02424322 v_mul_f32_e32 v34, s25, v29 ; 0A443A19 v_mac_f32_e32 v34, s24, v31 ; 2C443E18 v_mac_f32_e32 v34, s27, v30 ; 2C443C1B v_mac_f32_e32 v34, s29, v5 ; 2C440A1D v_mul_f32_e32 v35, s33, v29 ; 0A463A21 v_mac_f32_e32 v35, s31, v31 ; 2C463E1F v_mac_f32_e32 v35, s34, v30 ; 2C463C22 v_mac_f32_e32 v35, s35, v5 ; 2C460A23 v_mov_b32_e32 v36, 0x80000000 ; 7E4802FF 80000000 v_cmp_le_f32_e64 vcc, |v33|, v36 ; D043016A 00024921 v_cndmask_b32_e32 v28, v34, v28 ; 00383922 v_cndmask_b32_e32 v32, v35, v32 ; 00404123 v_cndmask_b32_e64 v33, 2.0, 1.0, vcc ; D1000021 01A9E4F4 v_cmp_le_f32_e64 vcc, |v27|, v36 ; D043016A 0002491B v_cndmask_b32_e32 v28, v28, v25 ; 0038331C v_cndmask_b32_e32 v32, v32, v26 ; 00403520 v_cndmask_b32_e64 v35, v33, 0, vcc ; D1000023 01A90121 v_mul_f32_e32 v25, s64, v29 ; 0A323A40 v_mac_f32_e32 v25, s63, v31 ; 2C323E3F v_mac_f32_e32 v25, s65, v30 ; 2C323C41 v_mac_f32_e32 v25, s60, v5 ; 2C320A3C v_add_f32_e64 v33, 0, v28 clamp ; D1018021 00023880 v_add_f32_e64 v34, 0, v32 clamp ; D1018022 00024080 v_add_f32_e32 v26, -1.0, v35 ; 023446F3 v_add_f32_e32 v27, -2.0, v35 ; 023646F5 v_cmp_le_f32_e64 vcc, |v35|, v36 ; D043016A 00024923 v_mov_b32_e32 v37, s58 ; 7E4A023A v_cndmask_b32_e32 v37, 0, v37 ; 004A4A80 v_mov_b32_e32 v38, s59 ; 7E4C023B v_cndmask_b32_e32 v38, 0, v38 ; 004C4C80 v_mov_b32_e32 v39, s56 ; 7E4E0238 v_cndmask_b32_e32 v39, 0, v39 ; 004E4E80 v_mov_b32_e32 v40, s57 ; 7E500239 v_cndmask_b32_e32 v40, 0, v40 ; 00505080 v_cmp_le_f32_e64 vcc, |v26|, v36 ; D043016A 0002491A v_mov_b32_e32 v26, s40 ; 7E340228 v_cndmask_b32_e32 v26, v37, v26 ; 00343525 v_mov_b32_e32 v37, s42 ; 7E4A022A v_cndmask_b32_e32 v37, v38, v37 ; 004A4B26 v_mov_b32_e32 v38, s36 ; 7E4C0224 v_cndmask_b32_e32 v38, v39, v38 ; 004C4D27 v_mov_b32_e32 v39, s38 ; 7E4E0226 v_cndmask_b32_e32 v39, v40, v39 ; 004E4F28 v_cmp_le_f32_e64 vcc, |v27|, v36 ; D043016A 0002491B v_mov_b32_e32 v27, s41 ; 7E360229 v_cndmask_b32_e32 v36, v26, v27 ; 0048371A v_mov_b32_e32 v26, s43 ; 7E34022B v_cndmask_b32_e32 v37, v37, v26 ; 004A3525 v_mov_b32_e32 v26, s37 ; 7E340225 v_cndmask_b32_e32 v26, v38, v26 ; 00343526 v_mov_b32_e32 v27, s39 ; 7E360227 v_cndmask_b32_e32 v27, v39, v27 ; 00363727 v_mac_f32_e32 v26, v36, v33 ; 2C344324 v_mac_f32_e32 v27, v37, v34 ; 2C364525 v_mov_b32_e32 v33, 0x3a000000 ; 7E4202FF 3A000000 v_add_f32_e32 v37, v33, v26 ; 024A3521 v_add_f32_e32 v38, v33, v27 ; 024C3721 v_add_f32_e32 v36, 0, v25 ; 02483280 s_mov_b32 s56, 0 ; BEB80080 v_mov_b32_e32 v39, s56 ; 7E4E0238 v_mov_b32_e32 v33, 0xba000000 ; 7E4202FF BA000000 v_add_f32_e32 v34, v33, v26 ; 02443521 v_mov_b32_e32 v40, v36 ; 7E500324 v_mov_b32_e32 v41, v37 ; 7E520325 v_mov_b32_e32 v42, v38 ; 7E540326 v_mov_b32_e32 v43, v39 ; 7E560327 v_add_f32_e32 v33, v33, v27 ; 02423721 v_mov_b32_e32 v41, v34 ; 7E520322 v_mov_b32_e32 v44, v36 ; 7E580324 v_mov_b32_e32 v45, v37 ; 7E5A0325 v_mov_b32_e32 v46, v38 ; 7E5C0326 v_mov_b32_e32 v47, v39 ; 7E5E0327 v_mov_b32_e32 v42, v38 ; 7E540326 v_mov_b32_e32 v46, v33 ; 7E5C0321 v_mov_b32_e32 v43, s56 ; 7E560238 v_mov_b32_e32 v47, s56 ; 7E5E0238 image_sample_c_l v34, 1, 0, 0, 0, 0, 0, 0, 0, v[36:39], s[44:51], s[52:55] ; F0B00100 01AB2224 s_nop 0 ; BF800000 image_sample_c_l v48, 1, 0, 0, 0, 0, 0, 0, 0, v[40:43], s[44:51], s[52:55] ; F0B00100 01AB3028 v_mov_b32_e32 v42, v33 ; 7E540321 image_sample_c_l v44, 1, 0, 0, 0, 0, 0, 0, 0, v[44:47], s[44:51], s[52:55] ; F0B00100 01AB2C2C v_mov_b32_e32 v43, s56 ; 7E560238 image_sample_c_l v45, 1, 0, 0, 0, 0, 0, 0, 0, v[40:43], s[44:51], s[52:55] ; F0B00100 01AB2D28 v_add_f32_e32 v42, 0, v27 ; 02543680 v_mov_b32_e32 v49, v36 ; 7E620324 v_mov_b32_e32 v50, v37 ; 7E640325 v_mov_b32_e32 v51, v38 ; 7E660326 v_mov_b32_e32 v52, v39 ; 7E680327 v_mov_b32_e32 v51, v42 ; 7E66032A v_add_f32_e32 v37, 0, v26 ; 024A3480 v_mov_b32_e32 v52, s56 ; 7E680238 v_mov_b32_e32 v53, v36 ; 7E6A0324 v_mov_b32_e32 v54, v37 ; 7E6C0325 v_mov_b32_e32 v55, v38 ; 7E6E0326 v_mov_b32_e32 v56, v39 ; 7E700327 image_sample_c_l v46, 1, 0, 0, 0, 0, 0, 0, 0, v[49:52], s[44:51], s[52:55] ; F0B00100 01AB2E31 v_mov_b32_e32 v55, v33 ; 7E6E0321 v_mov_b32_e32 v43, s56 ; 7E560238 image_sample_c_l v33, 1, 0, 0, 0, 0, 0, 0, 0, v[40:43], s[44:51], s[52:55] ; F0B00100 01AB2128 v_mov_b32_e32 v56, s56 ; 7E700238 image_sample_c_l v40, 1, 0, 0, 0, 0, 0, 0, 0, v[53:56], s[44:51], s[52:55] ; F0B00100 01AB2835 v_mov_b32_e32 v39, s56 ; 7E4E0238 image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[36:39], s[44:51], s[52:55] ; F0B00100 01AB2424 v_mov_b32_e32 v37, 0x3d800000 ; 7E4A02FF 3D800000 s_waitcnt vmcnt(6) ; BF8C0776 v_mul_f32_e32 v38, v37, v48 ; 0A4C6125 v_mac_f32_e32 v38, v37, v34 ; 2C4C4525 s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v38, v37, v44 ; 2C4C5925 s_waitcnt vmcnt(4) ; BF8C0774 v_mac_f32_e32 v38, v37, v45 ; 2C4C5B25 v_mov_b32_e32 v34, 0x3e000000 ; 7E4402FF 3E000000 s_waitcnt vmcnt(2) ; BF8C0772 v_mul_f32_e32 v33, v34, v33 ; 0A424322 v_mac_f32_e32 v33, v34, v46 ; 2C425D22 s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v33, v34, v40 ; 2C425122 s_waitcnt vmcnt(0) ; BF8C0770 v_mac_f32_e32 v33, v34, v36 ; 2C424922 v_add_f32_e32 v28, -0.5, v28 ; 023838F1 v_add_f32_e32 v32, -0.5, v32 ; 024040F1 v_sub_f32_e64 v28, |v28|, s1 ; D102011C 0000031C v_sub_f32_e64 v32, |v32|, s1 ; D1020120 00000320 v_mul_f32_e32 v28, s2, v28 ; 0A383802 v_mul_f32_e32 v32, s2, v32 ; 0A404002 v_add_f32_e64 v28, 0, v28 clamp ; D101801C 00023880 v_add_f32_e64 v32, 0, v32 clamp ; D1018020 00024080 v_sub_f32_e32 v28, 1.0, v28 ; 043838F2 v_mad_f32 v34, -v32, v28, v28 ; D1C10022 24723920 v_mov_b32_e32 v28, 0 ; 7E380280 v_add_f32_e32 v32, v38, v33 ; 02404326 image_sample_c_l v26, 1, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[44:51], s[52:55] ; F0B00100 01AB1A19 s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v32, v26, v32, 0x3e800000 ; 2E40411A 3E800000 v_mov_b32_e32 v33, s0 ; 7E420200 v_cmp_gt_f32_e32 vcc, 1.0, v34 ; 7C8844F2 s_and_saveexec_b64 s[58:59], vcc ; BEBA206A s_xor_b64 s[58:59], exec, s[58:59] ; 88BA3A7E s_cbranch_execz BB0_5 ; BF880000 s_buffer_load_dword s57, s[12:15], 0x510 ; C0220E46 00000510 s_nop 0 ; BF800000 s_buffer_load_dword s60, s[12:15], 0x514 ; C0220F06 00000514 s_nop 0 ; BF800000 s_buffer_load_dword s61, s[12:15], 0x518 ; C0220F46 00000518 s_nop 0 ; BF800000 s_buffer_load_dword s62, s[12:15], 0x51c ; C0220F86 0000051C s_nop 0 ; BF800000 s_buffer_load_dword s63, s[12:15], 0x520 ; C0220FC6 00000520 s_nop 0 ; BF800000 s_buffer_load_dword s64, s[12:15], 0x524 ; C0221006 00000524 s_nop 0 ; BF800000 s_buffer_load_dword s65, s[12:15], 0x528 ; C0221046 00000528 s_nop 0 ; BF800000 s_buffer_load_dword s66, s[12:15], 0x52c ; C0221086 0000052C s_nop 0 ; BF800000 s_buffer_load_dword s67, s[12:15], 0x580 ; C02210C6 00000580 s_nop 0 ; BF800000 s_buffer_load_dword s68, s[12:15], 0x584 ; C0221106 00000584 s_nop 0 ; BF800000 s_buffer_load_dword s69, s[12:15], 0x588 ; C0221146 00000588 s_nop 0 ; BF800000 s_buffer_load_dword s70, s[12:15], 0x58c ; C0221186 0000058C v_mov_b32_e32 v26, s26 ; 7E34021A v_mov_b32_e32 v27, s28 ; 7E36021C v_mov_b32_e32 v28, s30 ; 7E38021E v_mov_b32_e32 v36, s32 ; 7E480220 v_mov_b32_e32 v37, s20 ; 7E4A0214 v_mov_b32_e32 v38, s21 ; 7E4C0215 v_mov_b32_e32 v39, s22 ; 7E4E0216 v_mov_b32_e32 v40, s23 ; 7E500217 v_mov_b32_e32 v41, s24 ; 7E520218 v_mov_b32_e32 v42, s25 ; 7E540219 v_mov_b32_e32 v43, s27 ; 7E56021B v_add_f32_e32 v44, 0, v35 ; 02584680 v_mov_b32_e32 v45, 0x80000000 ; 7E5A02FF 80000000 v_cmp_le_f32_e64 vcc, |v44|, v45 ; D043016A 00025B2C v_add_f32_e32 v44, -1.0, v35 ; 025846F3 v_cmp_le_f32_e64 s[0:1], |v44|, v45 ; D0430100 00025B2C v_mov_b32_e32 v44, s29 ; 7E58021D v_cndmask_b32_e32 v26, 0, v26 ; 00343480 v_cndmask_b32_e64 v26, v26, v41, s[0:1] ; D100001A 0002531A v_mov_b32_e32 v41, s31 ; 7E52021F v_cndmask_b32_e32 v27, 0, v27 ; 00363680 v_cndmask_b32_e64 v27, v27, v42, s[0:1] ; D100001B 0002551B v_mov_b32_e32 v42, s33 ; 7E540221 v_cndmask_b32_e32 v28, 0, v28 ; 00383880 v_cndmask_b32_e64 v28, v28, v43, s[0:1] ; D100001C 0002571C v_mov_b32_e32 v43, s34 ; 7E560222 v_cndmask_b32_e32 v36, 0, v36 ; 00484880 v_cndmask_b32_e64 v36, v36, v44, s[0:1] ; D1000024 00025924 v_mov_b32_e32 v44, s35 ; 7E580223 v_cndmask_b32_e32 v37, 0, v37 ; 004A4A80 v_cndmask_b32_e64 v37, v37, v41, s[0:1] ; D1000025 00025325 v_mov_b32_e32 v41, s36 ; 7E520224 v_cndmask_b32_e32 v38, 0, v38 ; 004C4C80 v_cndmask_b32_e64 v38, v38, v42, s[0:1] ; D1000026 00025526 v_mov_b32_e32 v42, s38 ; 7E540226 v_cndmask_b32_e32 v39, 0, v39 ; 004E4E80 v_cndmask_b32_e64 v39, v39, v43, s[0:1] ; D1000027 00025727 v_mov_b32_e32 v43, s40 ; 7E560228 v_cndmask_b32_e32 v40, 0, v40 ; 00505080 v_cndmask_b32_e64 v40, v40, v44, s[0:1] ; D1000028 00025928 v_mov_b32_e32 v44, s42 ; 7E58022A v_add_f32_e32 v35, -2.0, v35 ; 024646F5 v_cmp_le_f32_e64 s[2:3], |v35|, v45 ; D0430102 00025B23 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v45, s57 ; 7E5A0239 v_cndmask_b32_e64 v26, v26, v45, s[2:3] ; D100001A 000A5B1A v_mov_b32_e32 v45, s60 ; 7E5A023C v_cndmask_b32_e64 v27, v27, v45, s[2:3] ; D100001B 000A5B1B v_mov_b32_e32 v45, s61 ; 7E5A023D v_cndmask_b32_e64 v28, v28, v45, s[2:3] ; D100001C 000A5B1C v_mov_b32_e32 v45, s62 ; 7E5A023E v_cndmask_b32_e64 v36, v36, v45, s[2:3] ; D1000024 000A5B24 v_mov_b32_e32 v45, s63 ; 7E5A023F v_cndmask_b32_e64 v37, v37, v45, s[2:3] ; D1000025 000A5B25 v_mov_b32_e32 v45, s64 ; 7E5A0240 v_cndmask_b32_e64 v38, v38, v45, s[2:3] ; D1000026 000A5B26 v_mov_b32_e32 v45, s65 ; 7E5A0241 v_cndmask_b32_e64 v39, v39, v45, s[2:3] ; D1000027 000A5B27 v_mov_b32_e32 v45, s66 ; 7E5A0242 v_cndmask_b32_e64 v40, v40, v45, s[2:3] ; D1000028 000A5B28 v_mov_b32_e32 v45, s37 ; 7E5A0225 v_mul_f32_e32 v27, v27, v29 ; 0A363B1B v_mac_f32_e32 v27, v26, v31 ; 2C363F1A v_mov_b32_e32 v26, s39 ; 7E340227 v_mac_f32_e32 v27, v28, v30 ; 2C363D1C v_mov_b32_e32 v28, s41 ; 7E380229 v_mac_f32_e32 v27, v36, v5 ; 2C360B24 v_mov_b32_e32 v36, s43 ; 7E48022B v_add_f32_e64 v46, 0, v27 clamp ; D101802E 00023680 v_mul_f32_e32 v27, v38, v29 ; 0A363B26 v_mac_f32_e32 v27, v37, v31 ; 2C363F25 v_mac_f32_e32 v27, v39, v30 ; 2C363D27 v_mac_f32_e32 v27, v40, v5 ; 2C360B28 v_add_f32_e64 v5, 0, v27 clamp ; D1018005 00023680 v_cndmask_b32_e32 v27, 0, v43 ; 00365680 v_cndmask_b32_e32 v29, 0, v44 ; 003A5880 v_cndmask_b32_e32 v30, 0, v41 ; 003C5280 v_cndmask_b32_e32 v31, 0, v42 ; 003E5480 v_cndmask_b32_e64 v27, v27, v28, s[0:1] ; D100001B 0002391B v_cndmask_b32_e64 v28, v29, v36, s[0:1] ; D100001C 0002491D v_cndmask_b32_e64 v29, v30, v45, s[0:1] ; D100001D 00025B1E v_cndmask_b32_e64 v30, v31, v26, s[0:1] ; D100001E 0002351F v_mov_b32_e32 v26, s69 ; 7E340245 v_cndmask_b32_e64 v31, v27, v26, s[2:3] ; D100001F 000A351B v_mov_b32_e32 v26, s70 ; 7E340246 v_cndmask_b32_e64 v28, v28, v26, s[2:3] ; D100001C 000A351C v_mov_b32_e32 v26, s67 ; 7E340243 v_cndmask_b32_e64 v26, v29, v26, s[2:3] ; D100001A 000A351D v_mov_b32_e32 v27, s68 ; 7E360244 v_cndmask_b32_e64 v27, v30, v27, s[2:3] ; D100001B 000A371E v_mac_f32_e32 v26, v31, v46 ; 2C345D1F v_mac_f32_e32 v27, v28, v5 ; 2C360B1C v_mov_b32_e32 v5, 0x3a000000 ; 7E0A02FF 3A000000 v_add_f32_e32 v29, v5, v26 ; 023A3505 v_add_f32_e32 v30, v5, v27 ; 023C3705 v_add_f32_e32 v28, 0, v25 ; 02383280 v_mov_b32_e32 v31, s56 ; 7E3E0238 v_mov_b32_e32 v5, 0xba000000 ; 7E0A02FF BA000000 v_add_f32_e32 v36, v5, v26 ; 02483505 v_mov_b32_e32 v37, v28 ; 7E4A031C v_mov_b32_e32 v38, v29 ; 7E4C031D v_mov_b32_e32 v39, v30 ; 7E4E031E v_mov_b32_e32 v40, v31 ; 7E50031F v_mov_b32_e32 v38, v36 ; 7E4C0324 v_add_f32_e32 v5, v5, v27 ; 020A3705 v_mov_b32_e32 v39, v30 ; 7E4E031E v_mov_b32_e32 v41, v28 ; 7E52031C v_mov_b32_e32 v42, v29 ; 7E54031D v_mov_b32_e32 v43, v30 ; 7E56031E v_mov_b32_e32 v44, v31 ; 7E58031F image_sample_c_l v36, 1, 0, 0, 0, 0, 0, 0, 0, v[28:31], s[44:51], s[52:55] ; F0B00100 01AB241C v_mov_b32_e32 v40, s56 ; 7E500238 v_mov_b32_e32 v43, v5 ; 7E560305 image_sample_c_l v45, 1, 0, 0, 0, 0, 0, 0, 0, v[37:40], s[44:51], s[52:55] ; F0B00100 01AB2D25 v_mov_b32_e32 v44, s56 ; 7E580238 v_mov_b32_e32 v39, v5 ; 7E4E0305 image_sample_c_l v41, 1, 0, 0, 0, 0, 0, 0, 0, v[41:44], s[44:51], s[52:55] ; F0B00100 01AB2929 v_mov_b32_e32 v40, s56 ; 7E500238 image_sample_c_l v42, 1, 0, 0, 0, 0, 0, 0, 0, v[37:40], s[44:51], s[52:55] ; F0B00100 01AB2A25 v_add_f32_e32 v39, 0, v27 ; 024E3680 v_mov_b32_e32 v46, v28 ; 7E5C031C v_mov_b32_e32 v47, v29 ; 7E5E031D v_mov_b32_e32 v48, v30 ; 7E60031E v_mov_b32_e32 v49, v31 ; 7E62031F v_mov_b32_e32 v48, v39 ; 7E600327 v_add_f32_e32 v29, 0, v26 ; 023A3480 v_mov_b32_e32 v49, s56 ; 7E620238 v_mov_b32_e32 v50, v28 ; 7E64031C v_mov_b32_e32 v51, v29 ; 7E66031D v_mov_b32_e32 v52, v30 ; 7E68031E v_mov_b32_e32 v53, v31 ; 7E6A031F image_sample_c_l v43, 1, 0, 0, 0, 0, 0, 0, 0, v[46:49], s[44:51], s[52:55] ; F0B00100 01AB2B2E v_mov_b32_e32 v52, v5 ; 7E680305 v_mov_b32_e32 v40, s56 ; 7E500238 image_sample_c_l v5, 1, 0, 0, 0, 0, 0, 0, 0, v[37:40], s[44:51], s[52:55] ; F0B00100 01AB0525 v_mov_b32_e32 v53, s56 ; 7E6A0238 image_sample_c_l v37, 1, 0, 0, 0, 0, 0, 0, 0, v[50:53], s[44:51], s[52:55] ; F0B00100 01AB2532 v_mov_b32_e32 v31, s56 ; 7E3E0238 image_sample_c_l v29, 1, 0, 0, 0, 0, 0, 0, 0, v[28:31], s[44:51], s[52:55] ; F0B00100 01AB1D1C v_mov_b32_e32 v28, 0 ; 7E380280 image_sample_c_l v25, 1, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[44:51], s[52:55] ; F0B00100 01AB1919 v_mov_b32_e32 v26, 0x3d800000 ; 7E3402FF 3D800000 s_waitcnt vmcnt(7) ; BF8C0777 v_mul_f32_e32 v27, v26, v45 ; 0A365B1A v_mac_f32_e32 v27, v26, v36 ; 2C36491A s_waitcnt vmcnt(6) ; BF8C0776 v_mac_f32_e32 v27, v26, v41 ; 2C36531A s_waitcnt vmcnt(5) ; BF8C0775 v_mac_f32_e32 v27, v26, v42 ; 2C36551A v_mov_b32_e32 v26, 0x3e000000 ; 7E3402FF 3E000000 s_waitcnt vmcnt(3) ; BF8C0773 v_mul_f32_e32 v5, v26, v5 ; 0A0A0B1A v_mac_f32_e32 v5, v26, v43 ; 2C0A571A s_waitcnt vmcnt(2) ; BF8C0772 v_mac_f32_e32 v5, v26, v37 ; 2C0A4B1A s_waitcnt vmcnt(1) ; BF8C0771 v_mac_f32_e32 v5, v26, v29 ; 2C0A3B1A v_add_f32_e32 v5, v27, v5 ; 020A0B1B s_waitcnt vmcnt(0) ; BF8C0770 v_madmk_f32_e32 v5, v25, v5, 0x3e800000 ; 2E0A0B19 3E800000 v_cmp_le_f32_e32 vcc, 0, v35 ; 7C864680 v_cndmask_b32_e64 v5, v5, 1.0, vcc ; D1000005 01A9E505 v_mad_f32 v5, -v34, v5, v5 ; D1C10005 24160B22 v_mac_f32_e32 v5, v34, v32 ; 2C0A4122 v_mov_b32_e32 v32, v5 ; 7E400305 s_or_b64 exec, exec, s[58:59] ; 87FE3A7E v_add_f32_e32 v5, v19, v15 ; 020A1F13 v_add_f32_e32 v15, v20, v16 ; 021E2114 v_add_f32_e32 v16, v21, v17 ; 02202315 v_add_f32_e32 v5, v5, v22 ; 020A2D05 v_add_f32_e32 v15, v15, v23 ; 021E2F0F v_add_f32_e32 v16, v16, v24 ; 02203110 v_mul_f32_e32 v5, 0x3e59999a, v5 ; 0A0A0AFF 3E59999A v_madmk_f32_e32 v5, v15, v5, 0x3f372474 ; 2E0A0B0F 3F372474 v_madmk_f32_e32 v5, v16, v5, 0x3d93a92a ; 2E0A0B10 3D93A92A v_mov_b32_e32 v15, 0xbeaaa64c ; 7E1E02FF BEAAA64C v_mul_f32_e32 v5, v5, v15 ; 0A0A1F05 v_rcp_f32_e32 v5, v5 ; 7E0A4505 v_mul_f32_e32 v5, v18, v5 ; 0A0A0B12 v_subrev_f32_e32 v15, s19, v8 ; 061E1013 v_subrev_f32_e32 v16, s18, v9 ; 06201212 v_subrev_f32_e32 v17, s17, v10 ; 06221411 v_mul_f32_e32 v15, v15, v15 ; 0A1E1F0F v_mac_f32_e32 v15, v16, v16 ; 2C1E2110 v_mac_f32_e32 v15, v17, v17 ; 2C1E2311 v_mad_f32 v15, v33, v15, s16 ; D1C1000F 00421F21 v_add_f32_e64 v15, 0, v15 clamp ; D101800F 00021E80 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mac_f32_e32 v15, v16, v32 ; 2C1E4110 v_sub_f32_e32 v16, 1.0, v15 ; 04201EF2 v_mad_f32 v15, -v15, v5, v5 ; D1C1000F 24160B0F v_mad_f32 v5, v16, v5, 1.0 ; D1C10005 03CA0B10 v_mac_f32_e32 v0, v0, v15 ; 2C001F00 v_mac_f32_e32 v1, v1, v15 ; 2C021F01 v_mac_f32_e32 v4, v4, v15 ; 2C081F04 v_mad_f32 v5, 0.5, v5, 0.5 ; D1C10005 03C20AF0 v_mad_f32 v15, -v5, v0, v0 ; D1C1000F 24020105 v_mac_f32_e32 v15, v5, v4 ; 2C1E0905 v_mad_f32 v16, -v5, v1, v1 ; D1C10010 24060305 v_mac_f32_e32 v16, v5, v1 ; 2C200305 v_mad_f32 v1, -v5, v4, v4 ; D1C10001 24120905 v_mac_f32_e32 v1, v5, v0 ; 2C020105 v_mov_b32_e32 v0, v1 ; 7E000301 v_mov_b32_e32 v1, v16 ; 7E020310 v_mov_b32_e32 v4, v15 ; 7E08030F s_or_b64 exec, exec, s[10:11] ; 87FE0A7E s_buffer_load_dword s5, s[12:15], 0xa0 ; C0220146 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s6, s[12:15], 0xa4 ; C0220186 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s7, s[12:15], 0xa8 ; C02201C6 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s4, s[12:15], 0xb0 ; C0220106 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[12:15], 0xb8 ; C02200C6 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[12:15], 0x1d0 ; C0220006 000001D0 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[12:15], 0x1d4 ; C0220046 000001D4 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[12:15], 0x1d8 ; C0220086 000001D8 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[12:15], 0x1f0 ; C0220406 000001F0 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[12:15], 0x1f4 ; C0220446 000001F4 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[12:15], 0x1f8 ; C0220306 000001F8 v_mov_b32_e32 v15, s9 ; 7E1E0209 v_mov_b32_e32 v5, s8 ; 7E0A0208 v_mul_f32_e32 v11, v2, v11 ; 0A161702 v_mul_f32_e32 v3, v3, v12 ; 0A061903 v_mul_f32_e32 v6, v6, v13 ; 0A0C1B06 v_mul_f32_e32 v2, v7, v14 ; 0A041D07 s_waitcnt lgkmcnt(0) ; BF8C007F v_add_f32_e32 v4, s16, v4 ; 02080810 v_add_f32_e32 v1, s17, v1 ; 02020211 v_add_f32_e32 v0, s12, v0 ; 0200000C v_mul_f32_e32 v4, v4, v11 ; 0A081704 v_mul_f32_e32 v1, v1, v3 ; 0A020701 v_mul_f32_e32 v0, v0, v6 ; 0A000D00 v_sub_f32_e32 v3, s5, v8 ; 04061005 v_sub_f32_e32 v6, s6, v9 ; 040C1206 v_sub_f32_e32 v7, s7, v10 ; 040E1407 v_mul_f32_e32 v3, v3, v3 ; 0A060703 v_mac_f32_e32 v3, v6, v6 ; 2C060D06 v_mac_f32_e32 v3, v7, v7 ; 2C060F07 v_sqrt_f32_e32 v3, v3 ; 7E064F03 v_mad_f32 v3, v15, v3, s4 ; D1C10003 0012070F v_add_f32_e64 v3, 0, v3 clamp ; D1018003 00020680 v_min_f32_e32 v3, s3, v3 ; 14060603 v_mul_f32_e32 v6, s8, v4 ; 0A0C0808 v_mul_f32_e32 v7, s8, v1 ; 0A0E0208 v_mul_f32_e32 v8, s8, v0 ; 0A100008 v_mul_f32_e32 v3, v3, v3 ; 0A060703 v_mad_f32 v4, -v4, v5, s0 ; D1C10004 20020B04 v_mad_f32 v1, -v1, v5, s1 ; D1C10001 20060B01 v_mad_f32 v0, -v0, v5, s2 ; D1C10000 200A0B00 v_mac_f32_e32 v6, v4, v3 ; 2C0C0704 v_mac_f32_e32 v7, v1, v3 ; 2C0E0701 v_mac_f32_e32 v8, v0, v3 ; 2C100700 v_cvt_pkrtz_f16_f32_e64 v0, v6, v7 ; D2960000 00020F06 v_cvt_pkrtz_f16_f32_e64 v1, v8, v2 ; D2960001 00020508 exp 15, 0, 1, 1, 1, v0, v1, v0, v1 ; C4001C0F 01000100 s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 80 VGPRS: 60 Code Size: 3532 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} as_es = 0 as_ls = 0 export_prim_id = 0 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL IN[6] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], CLIPVERTEX DCL OUT[3], GENERIC[0] DCL OUT[4], GENERIC[1] DCL OUT[5], GENERIC[2] DCL OUT[6], GENERIC[3] DCL OUT[7], GENERIC[4] DCL OUT[8], GENERIC[5] DCL OUT[9], GENERIC[6] DCL OUT[10], GENERIC[7] DCL CONST[0..51] DCL TEMP[0..11], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].zw, IMM[0].xxxx 1: MOV TEMP[1].w, IMM[0].xxxx 2: MOV TEMP[2].w, IMM[0].xxxx 3: MOV TEMP[3].w, IMM[0].xxxx 4: MOV TEMP[4].w, CONST[0].yyyy 5: MAD TEMP[5], IN[0].xyzx, CONST[0].yyyx, CONST[0].xxxy 6: DP4 TEMP[4].x, TEMP[5], CONST[48] 7: DP4 TEMP[6].x, TEMP[5], CONST[49] 8: MOV TEMP[4].y, TEMP[6].xxxx 9: DP4 TEMP[6].x, TEMP[5], CONST[50] 10: MOV TEMP[4].z, TEMP[6].xxxx 11: DP4 TEMP[6].x, TEMP[4], CONST[8] 12: DP4 TEMP[7].x, TEMP[4], CONST[9] 13: MOV TEMP[6].y, TEMP[7].xxxx 14: DP4 TEMP[8].x, TEMP[4], CONST[11] 15: MOV TEMP[6].w, TEMP[8].xxxx 16: DP4 TEMP[9].x, TEMP[4], CONST[10] 17: MOV TEMP[4].w, TEMP[9].xxxx 18: MOV TEMP[4], TEMP[4] 19: DP3 TEMP[10].x, IN[1].xyzz, CONST[48].xyzz 20: MOV TEMP[1].z, TEMP[10].xxxx 21: DP3 TEMP[10].x, IN[1].xyzz, CONST[49].xyzz 22: MOV TEMP[2].z, TEMP[10].xxxx 23: DP3 TEMP[10].x, IN[1].xyzz, CONST[50].xyzz 24: MOV TEMP[3].z, TEMP[10].xxxx 25: DP3 TEMP[1].x, IN[5].xyzz, CONST[48].xyzz 26: DP3 TEMP[2].x, IN[5].xyzz, CONST[49].xyzz 27: DP3 TEMP[3].x, IN[5].xyzz, CONST[50].xyzz 28: DP3 TEMP[10].x, IN[6].xyzz, CONST[48].xyzz 29: MOV TEMP[1].y, TEMP[10].xxxx 30: DP3 TEMP[10].x, IN[6].xyzz, CONST[49].xyzz 31: MOV TEMP[2].y, TEMP[10].xxxx 32: DP3 TEMP[10].x, IN[6].xyzz, CONST[50].xyzz 33: MOV TEMP[3].y, TEMP[10].xxxx 34: ADD TEMP[5].xy, IN[4].xyyy, IN[3].xyyy 35: ADD TEMP[10].xy, TEMP[5].yxxx, IN[4].yxxx 36: MOV TEMP[5].zw, TEMP[10].yyxy 37: ADD TEMP[10].xy, TEMP[10].yxxx, IN[4].xyyy 38: MOV TEMP[6].z, TEMP[9].xxxx 39: MOV TEMP[0].xy, IN[2].xyxx 40: MOV TEMP[10].zw, IN[2].yyxy 41: MOV TEMP[11], TEMP[6] 42: MAD TEMP[9].x, TEMP[9].xxxx, CONST[0].zzzz, -TEMP[8].xxxx 43: MOV TEMP[6].z, TEMP[9].xxxx 44: MOV TEMP[6].y, -TEMP[7].xxxx 45: MAD TEMP[6].xy, CONST[51].xyyy, TEMP[8].xxxx, TEMP[6].xyyy 46: MUL TEMP[7], CONST[0].yyxx, IN[2].xyxx 47: MAD TEMP[8], CONST[47].wwww, CONST[0].xxxy, CONST[0].yyyx 48: MOV OUT[3], TEMP[0] 49: MOV OUT[4], TEMP[7] 50: MOV OUT[9], TEMP[5] 51: MOV OUT[10], TEMP[10] 52: MOV OUT[5], TEMP[4] 53: MOV OUT[0], TEMP[6] 54: MOV OUT[6], TEMP[1] 55: MOV OUT[2], TEMP[11] 56: MOV OUT[7], TEMP[2] 57: MOV OUT[1], TEMP[8] 58: MOV OUT[8], TEMP[3] 59: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %12 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %13 = load <16 x i8>, <16 x i8> addrspace(2)* %12, align 16, !tbaa !0 %14 = call float @llvm.SI.load.const(<16 x i8> %13, i32 0) %15 = call float @llvm.SI.load.const(<16 x i8> %13, i32 4) %16 = call float @llvm.SI.load.const(<16 x i8> %13, i32 8) %17 = call float @llvm.SI.load.const(<16 x i8> %13, i32 128) %18 = call float @llvm.SI.load.const(<16 x i8> %13, i32 132) %19 = call float @llvm.SI.load.const(<16 x i8> %13, i32 136) %20 = call float @llvm.SI.load.const(<16 x i8> %13, i32 140) %21 = call float @llvm.SI.load.const(<16 x i8> %13, i32 144) %22 = call float @llvm.SI.load.const(<16 x i8> %13, i32 148) %23 = call float @llvm.SI.load.const(<16 x i8> %13, i32 152) %24 = call float @llvm.SI.load.const(<16 x i8> %13, i32 156) %25 = call float @llvm.SI.load.const(<16 x i8> %13, i32 160) %26 = call float @llvm.SI.load.const(<16 x i8> %13, i32 164) %27 = call float @llvm.SI.load.const(<16 x i8> %13, i32 168) %28 = call float @llvm.SI.load.const(<16 x i8> %13, i32 172) %29 = call float @llvm.SI.load.const(<16 x i8> %13, i32 176) %30 = call float @llvm.SI.load.const(<16 x i8> %13, i32 180) %31 = call float @llvm.SI.load.const(<16 x i8> %13, i32 184) %32 = call float @llvm.SI.load.const(<16 x i8> %13, i32 188) %33 = call float @llvm.SI.load.const(<16 x i8> %13, i32 764) %34 = call float @llvm.SI.load.const(<16 x i8> %13, i32 768) %35 = call float @llvm.SI.load.const(<16 x i8> %13, i32 772) %36 = call float @llvm.SI.load.const(<16 x i8> %13, i32 776) %37 = call float @llvm.SI.load.const(<16 x i8> %13, i32 780) %38 = call float @llvm.SI.load.const(<16 x i8> %13, i32 784) %39 = call float @llvm.SI.load.const(<16 x i8> %13, i32 788) %40 = call float @llvm.SI.load.const(<16 x i8> %13, i32 792) %41 = call float @llvm.SI.load.const(<16 x i8> %13, i32 796) %42 = call float @llvm.SI.load.const(<16 x i8> %13, i32 800) %43 = call float @llvm.SI.load.const(<16 x i8> %13, i32 804) %44 = call float @llvm.SI.load.const(<16 x i8> %13, i32 808) %45 = call float @llvm.SI.load.const(<16 x i8> %13, i32 812) %46 = call float @llvm.SI.load.const(<16 x i8> %13, i32 816) %47 = call float @llvm.SI.load.const(<16 x i8> %13, i32 820) %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !0 %50 = add i32 %5, %8 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1 %56 = load <16 x i8>, <16 x i8> addrspace(2)* %55, align 16, !tbaa !0 %57 = add i32 %5, %8 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 2 %63 = load <16 x i8>, <16 x i8> addrspace(2)* %62, align 16, !tbaa !0 %64 = add i32 %5, %8 %65 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %64) %66 = extractelement <4 x float> %65, i32 0 %67 = extractelement <4 x float> %65, i32 1 %68 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 3 %69 = load <16 x i8>, <16 x i8> addrspace(2)* %68, align 16, !tbaa !0 %70 = add i32 %5, %8 %71 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %69, i32 0, i32 %70) %72 = extractelement <4 x float> %71, i32 0 %73 = extractelement <4 x float> %71, i32 1 %74 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 4 %75 = load <16 x i8>, <16 x i8> addrspace(2)* %74, align 16, !tbaa !0 %76 = add i32 %5, %8 %77 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %76) %78 = extractelement <4 x float> %77, i32 0 %79 = extractelement <4 x float> %77, i32 1 %80 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 5 %81 = load <16 x i8>, <16 x i8> addrspace(2)* %80, align 16, !tbaa !0 %82 = add i32 %5, %8 %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %82) %84 = extractelement <4 x float> %83, i32 0 %85 = extractelement <4 x float> %83, i32 1 %86 = extractelement <4 x float> %83, i32 2 %87 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 6 %88 = load <16 x i8>, <16 x i8> addrspace(2)* %87, align 16, !tbaa !0 %89 = add i32 %5, %8 %90 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %89) %91 = extractelement <4 x float> %90, i32 0 %92 = extractelement <4 x float> %90, i32 1 %93 = extractelement <4 x float> %90, i32 2 %94 = fmul float %52, %15 %95 = fadd float %94, %14 %96 = fmul float %53, %15 %97 = fadd float %96, %14 %98 = fmul float %54, %15 %99 = fadd float %98, %14 %100 = fmul float %52, %14 %101 = fadd float %100, %15 %102 = fmul float %95, %34 %103 = fmul float %97, %35 %104 = fadd float %102, %103 %105 = fmul float %99, %36 %106 = fadd float %104, %105 %107 = fmul float %101, %37 %108 = fadd float %106, %107 %109 = fmul float %95, %38 %110 = fmul float %97, %39 %111 = fadd float %109, %110 %112 = fmul float %99, %40 %113 = fadd float %111, %112 %114 = fmul float %101, %41 %115 = fadd float %113, %114 %116 = fmul float %95, %42 %117 = fmul float %97, %43 %118 = fadd float %116, %117 %119 = fmul float %99, %44 %120 = fadd float %118, %119 %121 = fmul float %101, %45 %122 = fadd float %120, %121 %123 = fmul float %108, %17 %124 = fmul float %115, %18 %125 = fadd float %123, %124 %126 = fmul float %122, %19 %127 = fadd float %125, %126 %128 = fmul float %15, %20 %129 = fadd float %127, %128 %130 = fmul float %108, %21 %131 = fmul float %115, %22 %132 = fadd float %130, %131 %133 = fmul float %122, %23 %134 = fadd float %132, %133 %135 = fmul float %15, %24 %136 = fadd float %134, %135 %137 = fmul float %108, %29 %138 = fmul float %115, %30 %139 = fadd float %137, %138 %140 = fmul float %122, %31 %141 = fadd float %139, %140 %142 = fmul float %15, %32 %143 = fadd float %141, %142 %144 = fmul float %108, %25 %145 = fmul float %115, %26 %146 = fadd float %144, %145 %147 = fmul float %122, %27 %148 = fadd float %146, %147 %149 = fmul float %15, %28 %150 = fadd float %148, %149 %151 = fmul float %59, %34 %152 = fmul float %60, %35 %153 = fadd float %152, %151 %154 = fmul float %61, %36 %155 = fadd float %153, %154 %156 = fmul float %59, %38 %157 = fmul float %60, %39 %158 = fadd float %157, %156 %159 = fmul float %61, %40 %160 = fadd float %158, %159 %161 = fmul float %59, %42 %162 = fmul float %60, %43 %163 = fadd float %162, %161 %164 = fmul float %61, %44 %165 = fadd float %163, %164 %166 = fmul float %84, %34 %167 = fmul float %85, %35 %168 = fadd float %167, %166 %169 = fmul float %86, %36 %170 = fadd float %168, %169 %171 = fmul float %84, %38 %172 = fmul float %85, %39 %173 = fadd float %172, %171 %174 = fmul float %86, %40 %175 = fadd float %173, %174 %176 = fmul float %84, %42 %177 = fmul float %85, %43 %178 = fadd float %177, %176 %179 = fmul float %86, %44 %180 = fadd float %178, %179 %181 = fmul float %91, %34 %182 = fmul float %92, %35 %183 = fadd float %182, %181 %184 = fmul float %93, %36 %185 = fadd float %183, %184 %186 = fmul float %91, %38 %187 = fmul float %92, %39 %188 = fadd float %187, %186 %189 = fmul float %93, %40 %190 = fadd float %188, %189 %191 = fmul float %91, %42 %192 = fmul float %92, %43 %193 = fadd float %192, %191 %194 = fmul float %93, %44 %195 = fadd float %193, %194 %196 = fadd float %78, %72 %197 = fadd float %79, %73 %198 = fadd float %197, %79 %199 = fadd float %196, %78 %200 = fadd float %199, %78 %201 = fadd float %198, %79 %202 = fmul float %150, %16 %203 = fsub float %202, %143 %204 = fmul float %46, %143 %205 = fadd float %204, %129 %206 = fmul float %47, %143 %207 = fsub float %206, %136 %208 = fmul float %15, %66 %209 = fmul float %15, %67 %210 = fmul float %14, %66 %211 = fmul float %14, %66 %212 = fmul float %33, %14 %213 = fadd float %212, %15 %214 = fmul float %33, %14 %215 = fadd float %214, %15 %216 = fmul float %33, %14 %217 = fadd float %216, %15 %218 = fmul float %33, %15 %219 = fadd float %218, %14 %220 = and i32 %7, 1 %221 = icmp eq i32 %220, 0 br i1 %221, label %endif-block, label %if-true-block if-true-block: ; preds = %main_body %222 = call float @llvm.AMDIL.clamp.(float %213, float 0.000000e+00, float 1.000000e+00) %223 = call float @llvm.AMDIL.clamp.(float %215, float 0.000000e+00, float 1.000000e+00) %224 = call float @llvm.AMDIL.clamp.(float %217, float 0.000000e+00, float 1.000000e+00) %225 = call float @llvm.AMDIL.clamp.(float %219, float 0.000000e+00, float 1.000000e+00) br label %endif-block endif-block: ; preds = %main_body, %if-true-block %.050 = phi float [ %225, %if-true-block ], [ %219, %main_body ] %.049 = phi float [ %224, %if-true-block ], [ %217, %main_body ] %.048 = phi float [ %223, %if-true-block ], [ %215, %main_body ] %.0 = phi float [ %222, %if-true-block ], [ %213, %main_body ] call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.0, float %.048, float %.049, float %.050) %226 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 16 %227 = load <16 x i8>, <16 x i8> addrspace(2)* %226, align 16, !tbaa !0 %228 = call float @llvm.SI.load.const(<16 x i8> %227, i32 0) %229 = fmul float %228, %129 %230 = call float @llvm.SI.load.const(<16 x i8> %227, i32 4) %231 = fmul float %230, %136 %232 = fadd float %229, %231 %233 = call float @llvm.SI.load.const(<16 x i8> %227, i32 8) %234 = fmul float %233, %150 %235 = fadd float %232, %234 %236 = call float @llvm.SI.load.const(<16 x i8> %227, i32 12) %237 = fmul float %236, %143 %238 = fadd float %235, %237 %239 = call float @llvm.SI.load.const(<16 x i8> %227, i32 16) %240 = fmul float %239, %129 %241 = call float @llvm.SI.load.const(<16 x i8> %227, i32 20) %242 = fmul float %241, %136 %243 = fadd float %240, %242 %244 = call float @llvm.SI.load.const(<16 x i8> %227, i32 24) %245 = fmul float %244, %150 %246 = fadd float %243, %245 %247 = call float @llvm.SI.load.const(<16 x i8> %227, i32 28) %248 = fmul float %247, %143 %249 = fadd float %246, %248 %250 = call float @llvm.SI.load.const(<16 x i8> %227, i32 32) %251 = fmul float %250, %129 %252 = call float @llvm.SI.load.const(<16 x i8> %227, i32 36) %253 = fmul float %252, %136 %254 = fadd float %251, %253 %255 = call float @llvm.SI.load.const(<16 x i8> %227, i32 40) %256 = fmul float %255, %150 %257 = fadd float %254, %256 %258 = call float @llvm.SI.load.const(<16 x i8> %227, i32 44) %259 = fmul float %258, %143 %260 = fadd float %257, %259 %261 = call float @llvm.SI.load.const(<16 x i8> %227, i32 48) %262 = fmul float %261, %129 %263 = call float @llvm.SI.load.const(<16 x i8> %227, i32 52) %264 = fmul float %263, %136 %265 = fadd float %262, %264 %266 = call float @llvm.SI.load.const(<16 x i8> %227, i32 56) %267 = fmul float %266, %150 %268 = fadd float %265, %267 %269 = call float @llvm.SI.load.const(<16 x i8> %227, i32 60) %270 = fmul float %269, %143 %271 = fadd float %268, %270 %272 = call float @llvm.SI.load.const(<16 x i8> %227, i32 64) %273 = fmul float %272, %129 %274 = call float @llvm.SI.load.const(<16 x i8> %227, i32 68) %275 = fmul float %274, %136 %276 = fadd float %273, %275 %277 = call float @llvm.SI.load.const(<16 x i8> %227, i32 72) %278 = fmul float %277, %150 %279 = fadd float %276, %278 %280 = call float @llvm.SI.load.const(<16 x i8> %227, i32 76) %281 = fmul float %280, %143 %282 = fadd float %279, %281 %283 = call float @llvm.SI.load.const(<16 x i8> %227, i32 80) %284 = fmul float %283, %129 %285 = call float @llvm.SI.load.const(<16 x i8> %227, i32 84) %286 = fmul float %285, %136 %287 = fadd float %284, %286 %288 = call float @llvm.SI.load.const(<16 x i8> %227, i32 88) %289 = fmul float %288, %150 %290 = fadd float %287, %289 %291 = call float @llvm.SI.load.const(<16 x i8> %227, i32 92) %292 = fmul float %291, %143 %293 = fadd float %290, %292 %294 = call float @llvm.SI.load.const(<16 x i8> %227, i32 96) %295 = fmul float %294, %129 %296 = call float @llvm.SI.load.const(<16 x i8> %227, i32 100) %297 = fmul float %296, %136 %298 = fadd float %295, %297 %299 = call float @llvm.SI.load.const(<16 x i8> %227, i32 104) %300 = fmul float %299, %150 %301 = fadd float %298, %300 %302 = call float @llvm.SI.load.const(<16 x i8> %227, i32 108) %303 = fmul float %302, %143 %304 = fadd float %301, %303 %305 = call float @llvm.SI.load.const(<16 x i8> %227, i32 112) %306 = fmul float %305, %129 %307 = call float @llvm.SI.load.const(<16 x i8> %227, i32 116) %308 = fmul float %307, %136 %309 = fadd float %306, %308 %310 = call float @llvm.SI.load.const(<16 x i8> %227, i32 120) %311 = fmul float %310, %150 %312 = fadd float %309, %311 %313 = call float @llvm.SI.load.const(<16 x i8> %227, i32 124) %314 = fmul float %313, %143 %315 = fadd float %312, %314 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %66, float %67, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %208, float %209, float %210, float %211) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %108, float %115, float %122, float %150) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %170, float %185, float %155, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %175, float %190, float %160, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %180, float %195, float %165, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %196, float %197, float %198, float %199) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 40, i32 0, float %200, float %201, float %66, float %67) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %205, float %207, float %203, float %143) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 13, i32 0, float %238, float %249, float %260, float %271) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 14, i32 0, float %282, float %293, float %304, float %315) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} Shader Disassembly: s_load_dwordx4 s[4:7], s[8:9], 0x0 ; C00A0104 00000000 s_nop 0 ; BF800000 s_load_dwordx4 s[16:19], s[8:9], 0x10 ; C00A0404 00000010 s_nop 0 ; BF800000 s_load_dwordx4 s[20:23], s[8:9], 0x20 ; C00A0504 00000020 s_nop 0 ; BF800000 s_load_dwordx4 s[24:27], s[8:9], 0x30 ; C00A0604 00000030 s_nop 0 ; BF800000 s_load_dwordx4 s[28:31], s[8:9], 0x40 ; C00A0704 00000040 s_nop 0 ; BF800000 s_load_dwordx4 s[32:35], s[8:9], 0x50 ; C00A0804 00000050 s_nop 0 ; BF800000 s_load_dwordx4 s[36:39], s[8:9], 0x60 ; C00A0904 00000060 v_add_i32_e32 v14, vcc, s10, v0 ; 321C000A s_waitcnt lgkmcnt(0) ; BF8C007F buffer_load_format_xyzw v[7:10], v14, s[4:7], 0 idxen ; E00C2000 8001070E s_nop 0 ; BF800000 buffer_load_format_xyzw v[20:23], v14, s[16:19], 0 idxen ; E00C2000 8004140E s_nop 0 ; BF800000 buffer_load_format_xyzw v[0:3], v14, s[20:23], 0 idxen ; E00C2000 8005000E s_waitcnt vmcnt(2) ; BF8C0772 buffer_load_format_xyzw v[10:13], v14, s[24:27], 0 idxen ; E00C2000 80060A0E s_waitcnt vmcnt(1) ; BF8C0771 buffer_load_format_xyzw v[3:6], v14, s[28:31], 0 idxen ; E00C2000 8007030E s_nop 0 ; BF800000 buffer_load_format_xyzw v[16:19], v14, s[32:35], 0 idxen ; E00C2000 8008100E s_waitcnt vmcnt(2) ; BF8C0772 buffer_load_format_xyzw v[12:15], v14, s[36:39], 0 idxen ; E00C2000 80090C0E s_load_dwordx4 s[4:7], s[2:3], 0x0 ; C00A0101 00000000 s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s26, s[4:7], 0x0 ; C0220682 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s39, s[4:7], 0x4 ; C02209C2 00000004 s_nop 0 ; BF800000 s_buffer_load_dword s0, s[4:7], 0x8 ; C0220002 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x80 ; C02202C2 00000080 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x84 ; C0220382 00000084 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x88 ; C0220202 00000088 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x8c ; C0220042 0000008C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x90 ; C02203C2 00000090 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x94 ; C0220482 00000094 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x98 ; C0220282 00000098 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x9c ; C0220242 0000009C s_nop 0 ; BF800000 s_buffer_load_dword s19, s[4:7], 0xa0 ; C02204C2 000000A0 s_nop 0 ; BF800000 s_buffer_load_dword s23, s[4:7], 0xa4 ; C02205C2 000000A4 s_nop 0 ; BF800000 s_buffer_load_dword s20, s[4:7], 0xa8 ; C0220502 000000A8 s_nop 0 ; BF800000 s_buffer_load_dword s21, s[4:7], 0xac ; C0220542 000000AC s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0xb0 ; C0220442 000000B0 s_nop 0 ; BF800000 s_buffer_load_dword s22, s[4:7], 0xb4 ; C0220582 000000B4 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0xb8 ; C0220402 000000B8 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0xbc ; C0220342 000000BC s_nop 0 ; BF800000 s_buffer_load_dword s40, s[4:7], 0x2fc ; C0220A02 000002FC s_nop 0 ; BF800000 s_buffer_load_dword s30, s[4:7], 0x300 ; C0220782 00000300 s_nop 0 ; BF800000 s_buffer_load_dword s33, s[4:7], 0x304 ; C0220842 00000304 s_nop 0 ; BF800000 s_buffer_load_dword s28, s[4:7], 0x308 ; C0220702 00000308 s_nop 0 ; BF800000 s_buffer_load_dword s27, s[4:7], 0x30c ; C02206C2 0000030C s_nop 0 ; BF800000 s_buffer_load_dword s34, s[4:7], 0x310 ; C0220882 00000310 s_nop 0 ; BF800000 s_buffer_load_dword s36, s[4:7], 0x314 ; C0220902 00000314 s_nop 0 ; BF800000 s_buffer_load_dword s31, s[4:7], 0x318 ; C02207C2 00000318 s_nop 0 ; BF800000 s_buffer_load_dword s29, s[4:7], 0x31c ; C0220742 0000031C s_nop 0 ; BF800000 s_buffer_load_dword s37, s[4:7], 0x320 ; C0220942 00000320 s_nop 0 ; BF800000 s_buffer_load_dword s38, s[4:7], 0x324 ; C0220982 00000324 s_nop 0 ; BF800000 s_buffer_load_dword s35, s[4:7], 0x328 ; C02208C2 00000328 s_nop 0 ; BF800000 s_buffer_load_dword s32, s[4:7], 0x32c ; C0220802 0000032C s_nop 0 ; BF800000 s_buffer_load_dword s24, s[4:7], 0x330 ; C0220602 00000330 s_nop 0 ; BF800000 s_buffer_load_dword s25, s[4:7], 0x334 ; C0220642 00000334 s_waitcnt lgkmcnt(0) ; BF8C007F v_mov_b32_e32 v2, s39 ; 7E040227 s_waitcnt vmcnt(2) ; BF8C0772 v_mov_b32_e32 v5, s26 ; 7E0A021A v_mad_f32 v6, s40, v5, v2 ; D1C10006 040A0A28 v_mad_f32 v5, s40, v2, v5 ; D1C10005 04160428 s_and_b32 s4, 1, s12 ; 86040C81 v_cmp_eq_i32_e64 s[4:5], 1, s4 ; D0C20004 00000881 s_waitcnt vmcnt(1) ; BF8C0771 v_mov_b32_e32 v19, v6 ; 7E260306 s_waitcnt vmcnt(0) ; BF8C0770 v_mov_b32_e32 v15, v6 ; 7E1E0306 s_and_saveexec_b64 s[4:5], s[4:5] ; BE842004 s_xor_b64 s[4:5], exec, s[4:5] ; 8884047E v_add_f32_e64 v15, 0, v6 clamp ; D101800F 00020C80 v_add_f32_e64 v19, 0, v6 clamp ; D1018013 00020C80 v_add_f32_e64 v6, 0, v6 clamp ; D1018006 00020C80 v_add_f32_e64 v5, 0, v5 clamp ; D1018005 00020A80 s_or_b64 exec, exec, s[4:5] ; 87FE047E exp 15, 32, 0, 0, 0, v6, v15, v19, v5 ; C400020F 05130F06 s_load_dwordx4 s[4:7], s[2:3], 0x100 ; C00A0101 00000100 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v5, s30, v20 ; 0A0A281E v_mac_f32_e32 v5, s33, v21 ; 2C0A2A21 v_mac_f32_e32 v5, s28, v22 ; 2C0A2C1C v_mul_f32_e32 v6, s34, v20 ; 0A0C2822 v_mac_f32_e32 v6, s36, v21 ; 2C0C2A24 v_mac_f32_e32 v6, s31, v22 ; 2C0C2C1F v_mul_f32_e32 v15, s37, v20 ; 0A1E2825 v_mac_f32_e32 v15, s38, v21 ; 2C1E2A26 v_mac_f32_e32 v15, s35, v22 ; 2C1E2C23 v_mul_f32_e32 v19, s30, v16 ; 0A26201E v_mac_f32_e32 v19, s33, v17 ; 2C262221 v_mac_f32_e32 v19, s28, v18 ; 2C26241C v_mul_f32_e32 v20, s34, v16 ; 0A282022 v_mac_f32_e32 v20, s36, v17 ; 2C282224 v_mac_f32_e32 v20, s31, v18 ; 2C28241F v_mul_f32_e32 v16, s37, v16 ; 0A202025 v_mac_f32_e32 v16, s38, v17 ; 2C202226 v_mac_f32_e32 v16, s35, v18 ; 2C202423 v_mul_f32_e32 v17, s30, v12 ; 0A22181E v_mac_f32_e32 v17, s33, v13 ; 2C221A21 v_mac_f32_e32 v17, s28, v14 ; 2C221C1C v_mul_f32_e32 v18, s34, v12 ; 0A241822 v_mac_f32_e32 v18, s36, v13 ; 2C241A24 v_mac_f32_e32 v18, s31, v14 ; 2C241C1F v_mul_f32_e32 v12, s37, v12 ; 0A181825 v_mac_f32_e32 v12, s38, v13 ; 2C181A26 v_mac_f32_e32 v12, s35, v14 ; 2C181C23 v_mad_f32 v13, v2, v7, s26 ; D1C1000D 006A0F02 v_mad_f32 v8, v8, v2, s26 ; D1C10008 006A0508 v_mad_f32 v9, v9, v2, s26 ; D1C10009 006A0509 v_mad_f32 v7, s26, v7, v2 ; D1C10007 040A0E1A v_add_f32_e32 v10, v10, v3 ; 0214070A v_add_f32_e32 v11, v11, v4 ; 0216090B v_add_f32_e32 v14, v4, v11 ; 021C1704 v_add_f32_e32 v21, v3, v10 ; 022A1503 v_add_f32_e32 v3, v3, v21 ; 02062B03 v_add_f32_e32 v4, v4, v14 ; 02081D04 v_mov_b32_e32 v22, 0 ; 7E2C0280 exp 15, 33, 0, 0, 0, v0, v1, v22, v22 ; C400021F 16160100 v_mul_f32_e32 v23, s26, v0 ; 0A2E001A v_mul_f32_e32 v24, v0, v2 ; 0A300500 v_mul_f32_e32 v25, v1, v2 ; 0A320501 exp 15, 34, 0, 0, 0, v24, v25, v23, v23 ; C400022F 17171918 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v23, s33, v8 ; 0A2E1021 v_mac_f32_e32 v23, s30, v13 ; 2C2E1A1E v_mul_f32_e32 v24, s36, v8 ; 0A301024 v_mac_f32_e32 v24, s34, v13 ; 2C301A22 v_mul_f32_e32 v8, s38, v8 ; 0A101026 v_mac_f32_e32 v8, s37, v13 ; 2C101A25 v_mac_f32_e32 v23, s28, v9 ; 2C2E121C v_mac_f32_e32 v24, s31, v9 ; 2C30121F v_mac_f32_e32 v8, s35, v9 ; 2C101223 v_mac_f32_e32 v23, s27, v7 ; 2C2E0E1B v_mac_f32_e32 v24, s29, v7 ; 2C300E1D v_mac_f32_e32 v8, s32, v7 ; 2C100E20 v_mul_f32_e32 v7, s14, v24 ; 0A0E300E v_mac_f32_e32 v7, s11, v23 ; 2C0E2E0B v_mul_f32_e32 v9, s18, v24 ; 0A123012 v_mac_f32_e32 v9, s15, v23 ; 2C122E0F v_mul_f32_e32 v13, s23, v24 ; 0A1A3017 v_mac_f32_e32 v13, s19, v23 ; 2C1A2E13 v_mac_f32_e32 v13, s20, v8 ; 2C1A1014 v_mac_f32_e32 v13, s21, v2 ; 2C1A0415 exp 15, 35, 0, 0, 0, v23, v24, v8, v13 ; C400023F 0D081817 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v24, s22, v24 ; 0A303016 v_mac_f32_e32 v24, s17, v23 ; 2C302E11 v_mac_f32_e32 v7, s8, v8 ; 2C0E1008 v_mac_f32_e32 v9, s10, v8 ; 2C12100A v_mac_f32_e32 v24, s16, v8 ; 2C301010 v_mac_f32_e32 v7, s1, v2 ; 2C0E0401 v_mac_f32_e32 v9, s9, v2 ; 2C120409 v_mac_f32_e32 v24, s13, v2 ; 2C30040D s_waitcnt lgkmcnt(0) ; BF8C007F s_buffer_load_dword s1, s[4:7], 0x0 ; C0220042 00000000 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x4 ; C0220082 00000004 exp 15, 36, 0, 0, 0, v19, v17, v5, v22 ; C400024F 16051113 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x8 ; C02200C2 00000008 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0xc ; C0220202 0000000C v_mad_f32 v2, v13, s0, -v24 ; D1C10002 8460010D s_waitcnt expcnt(0) ; BF8C070F v_mad_f32 v5, s24, v24, v7 ; D1C10005 041E3018 v_mad_f32 v8, s25, v24, -v9 ; D1C10008 84263019 s_buffer_load_dword s0, s[4:7], 0x10 ; C0220002 00000010 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x14 ; C0220242 00000014 exp 15, 37, 0, 0, 0, v20, v18, v6, v22 ; C400025F 16061214 s_waitcnt expcnt(0) lgkmcnt(0) ; BF8C000F v_mul_f32_e32 v6, s2, v9 ; 0A0C1202 v_mac_f32_e32 v6, s1, v7 ; 2C0C0E01 v_mac_f32_e32 v6, s3, v13 ; 2C0C1A03 v_mac_f32_e32 v6, s8, v24 ; 2C0C3008 s_buffer_load_dword s1, s[4:7], 0x18 ; C0220042 00000018 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x1c ; C0220082 0000001C s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x20 ; C02200C2 00000020 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x24 ; C0220202 00000024 v_mul_f32_e32 v17, s9, v9 ; 0A221209 s_buffer_load_dword s9, s[4:7], 0x28 ; C0220242 00000028 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x2c ; C0220282 0000002C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x30 ; C02202C2 00000030 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x34 ; C0220302 00000034 v_mac_f32_e32 v17, s0, v7 ; 2C220E00 s_buffer_load_dword s0, s[4:7], 0x38 ; C0220002 00000038 s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v17, s1, v13 ; 2C221A01 v_mac_f32_e32 v17, s2, v24 ; 2C223002 v_mul_f32_e32 v18, s8, v9 ; 0A241208 v_mac_f32_e32 v18, s3, v7 ; 2C240E03 v_mac_f32_e32 v18, s9, v13 ; 2C241A09 v_mac_f32_e32 v18, s10, v24 ; 2C24300A exp 15, 38, 0, 0, 0, v16, v12, v15, v22 ; C400026F 160F0C10 s_waitcnt expcnt(0) ; BF8C070F v_mul_f32_e32 v12, s12, v9 ; 0A18120C v_mac_f32_e32 v12, s11, v7 ; 2C180E0B v_mac_f32_e32 v12, s0, v13 ; 2C181A00 s_buffer_load_dword s0, s[4:7], 0x3c ; C0220002 0000003C s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x40 ; C0220042 00000040 s_nop 0 ; BF800000 s_buffer_load_dword s2, s[4:7], 0x44 ; C0220082 00000044 s_nop 0 ; BF800000 s_buffer_load_dword s3, s[4:7], 0x50 ; C02200C2 00000050 s_nop 0 ; BF800000 s_buffer_load_dword s8, s[4:7], 0x54 ; C0220202 00000054 s_nop 0 ; BF800000 s_buffer_load_dword s9, s[4:7], 0x58 ; C0220242 00000058 s_nop 0 ; BF800000 s_buffer_load_dword s10, s[4:7], 0x5c ; C0220282 0000005C s_nop 0 ; BF800000 s_buffer_load_dword s11, s[4:7], 0x60 ; C02202C2 00000060 s_nop 0 ; BF800000 s_buffer_load_dword s12, s[4:7], 0x64 ; C0220302 00000064 s_nop 0 ; BF800000 s_buffer_load_dword s13, s[4:7], 0x68 ; C0220342 00000068 s_nop 0 ; BF800000 s_buffer_load_dword s14, s[4:7], 0x6c ; C0220382 0000006C s_nop 0 ; BF800000 s_buffer_load_dword s15, s[4:7], 0x70 ; C02203C2 00000070 s_nop 0 ; BF800000 s_buffer_load_dword s16, s[4:7], 0x74 ; C0220402 00000074 s_nop 0 ; BF800000 s_buffer_load_dword s17, s[4:7], 0x48 ; C0220442 00000048 s_nop 0 ; BF800000 s_buffer_load_dword s18, s[4:7], 0x4c ; C0220482 0000004C s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v12, s0, v24 ; 2C183000 v_mul_f32_e32 v15, s2, v9 ; 0A1E1202 v_mac_f32_e32 v15, s1, v7 ; 2C1E0E01 v_mul_f32_e32 v16, s8, v9 ; 0A201208 v_mac_f32_e32 v16, s3, v7 ; 2C200E03 v_mul_f32_e32 v19, s12, v9 ; 0A26120C v_mac_f32_e32 v19, s11, v7 ; 2C260E0B v_mul_f32_e32 v9, s16, v9 ; 0A121210 s_buffer_load_dword s0, s[4:7], 0x78 ; C0220002 00000078 s_nop 0 ; BF800000 s_buffer_load_dword s1, s[4:7], 0x7c ; C0220042 0000007C exp 15, 39, 0, 0, 0, v10, v11, v14, v21 ; C400027F 150E0B0A exp 15, 40, 0, 0, 0, v3, v4, v0, v1 ; C400028F 01000403 exp 15, 12, 0, 0, 0, v5, v8, v2, v24 ; C40000CF 18020805 exp 15, 13, 0, 0, 0, v6, v17, v18, v12 ; C40000DF 0C121106 v_mac_f32_e32 v9, s15, v7 ; 2C120E0F v_mac_f32_e32 v15, s17, v13 ; 2C1E1A11 v_mac_f32_e32 v16, s9, v13 ; 2C201A09 v_mac_f32_e32 v19, s13, v13 ; 2C261A0D s_waitcnt lgkmcnt(0) ; BF8C007F v_mac_f32_e32 v9, s0, v13 ; 2C121A00 v_mac_f32_e32 v15, s18, v24 ; 2C1E3012 v_mac_f32_e32 v16, s10, v24 ; 2C20300A v_mac_f32_e32 v19, s14, v24 ; 2C26300E v_mac_f32_e32 v9, s1, v24 ; 2C123001 exp 15, 14, 0, 1, 0, v15, v16, v19, v9 ; C40008EF 0913100F s_endpgm ; BF810000 *** SHADER STATS *** SGPRS: 48 VGPRS: 28 Code Size: 1636 bytes LDS: 0 blocks Scratch: 0 bytes per wave ******************** SHADER KEY export_16bpc = 0x3 last_cbuf = 0 color_two_side = 0 alpha_func = 7 alpha_to_one = 0 poly_stipple = 0 clamp_color = 0 FRAG DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL IN[2], GENERIC[1], PERSPECTIVE DCL IN[3], GENERIC[2], PERSPECTIVE DCL IN[4], GENERIC[3], PERSPECTIVE DCL IN[5], GENERIC[4], PERSPECTIVE DCL IN[6], GENERIC[5], PERSPECTIVE DCL IN[7], GENERIC[6], PERSPECTIVE, CENTROID DCL IN[8], GENERIC[7], PERSPECTIVE, CENTROID DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SVIEW[0], 2D, FLOAT DCL SVIEW[1], 2D, FLOAT DCL SVIEW[2], CUBE, FLOAT DCL SVIEW[3], 2D, FLOAT DCL SVIEW[4], SHADOW2D, FLOAT DCL CONST[0..90] DCL TEMP[0..19], LOCAL IMM[0] FLT32 { 0.5774, -0.4082, 0.7071, 0.0000} IMM[1] FLT32 { 0.8165, 0.0000, 0.5774, 0.3333} IMM[2] FLT32 { -0.4082, -0.7071, 0.5774, 1.0000} IMM[3] FLT32 { 0.2125, 0.7154, 0.0721, 2.0000} IMM[4] FLT32 { 1.0000, 0.0000, -0.5000, 0.0005} IMM[5] FLT32 { -0.0000, -1.0000, -2.0000, 0.0625} IMM[6] FLT32 { -0.0005, 0.0005, 0.0000, 0.1250} IMM[7] FLT32 { 0.2500, 0.0000, -1.0000, -2.0000} IMM[8] FLT32 { 0.5000, 0.2990, 0.5870, 0.1140} 0: ADD TEMP[0].xyz, CONST[10].xyzz, -IN[3].xyzz 1: MOV TEMP[1].xy, IN[1].xyyy 2: TEX TEMP[1], TEMP[1], SAMP[0], 2D 3: MOV TEMP[2].xy, IN[2].xyyy 4: TEX TEMP[3], TEMP[2], SAMP[3], 2D 5: MOV TEMP[4].w, TEMP[3].wwww 6: MOV TEMP[5].xy, IN[7].xyyy 7: TEX TEMP[5], TEMP[5], SAMP[1], 2D 8: MOV TEMP[6], TEMP[5] 9: MOV TEMP[7].xy, IN[7].wzzz 10: TEX TEMP[7], TEMP[7], SAMP[1], 2D 11: MOV TEMP[8], TEMP[7] 12: MOV TEMP[9].xy, IN[8].xyyy 13: TEX TEMP[9], TEMP[9], SAMP[1], 2D 14: MOV TEMP[10].xyz, TEMP[9] 15: MUL TEMP[2].xyz, TEMP[1].xyzz, IN[0].xyzz 16: MUL TEMP[1].x, TEMP[1].wwww, IN[0].wwww 17: MOV TEMP[1].w, TEMP[1].xxxx 18: MUL TEMP[11].xyz, TEMP[3].yyyy, TEMP[7].xyzz 19: MAD TEMP[11].xyz, TEMP[3].xxxx, TEMP[5].xyzz, TEMP[11].xyzz 20: MAD TEMP[11].xyz, TEMP[3].zzzz, TEMP[9].xyzz, TEMP[11].xyzz 21: MUL TEMP[11].xyz, TEMP[11].xyzz, CONST[12].xyzz 22: MUL TEMP[11].xyz, TEMP[11].xyzz, IMM[0].xxxx 23: MUL TEMP[12].xyz, TEMP[3].yyyy, IMM[0].yzxx 24: MAD TEMP[12].xyz, TEMP[3].xxxx, IMM[1].xyzz, TEMP[12].xyzz 25: MAD TEMP[4].xyz, TEMP[3].zzzz, IMM[2].xyzz, TEMP[12].xyzz 26: DP3 TEMP[3].x, TEMP[4].xyzz, TEMP[4].xyzz 27: RSQ TEMP[3].x, TEMP[3].xxxx 28: MUL TEMP[12].xyz, TEMP[4].xyzz, TEMP[3].xxxx 29: FSLT TEMP[3].x, -TEMP[5].wwww, IMM[0].wwww 30: AND TEMP[3].x, CONST[90].xxxx, TEMP[3].xxxx 31: UIF TEMP[3].xxxx :0 32: ADD TEMP[4].xyz, TEMP[5].xyzz, TEMP[7].xyzz 33: ADD TEMP[4].xyz, TEMP[9].xyzz, TEMP[4].xyzz 34: DP3 TEMP[3].x, TEMP[4].xyzz, IMM[3].xyzz 35: MUL TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww 36: RCP TEMP[3].x, TEMP[3].xxxx 37: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[5].wwww 38: MAD TEMP[6], IN[3].xyzx, IMM[4].xxxy, IMM[4].yyyx 39: DP4 TEMP[4].x, TEMP[6], CONST[69] 40: DP4 TEMP[5].x, TEMP[6], CONST[70] 41: MOV TEMP[4].y, TEMP[5].xxxx 42: MOV_SAT TEMP[7].xy, TEMP[4].xyyy 43: ADD TEMP[8].xy, -TEMP[4].xyyy, TEMP[7].xyyy 44: DP2 TEMP[7].x, TEMP[8].xyyy, IMM[2].wwww 45: DP4 TEMP[8].x, TEMP[6], CONST[73] 46: DP4 TEMP[9].x, TEMP[6], CONST[74] 47: MOV TEMP[8].y, TEMP[9].xxxx 48: MOV_SAT TEMP[13].xy, TEMP[8].xyyy 49: ADD TEMP[10].xy, -TEMP[8].xyyy, TEMP[13].xyyy 50: DP2 TEMP[13].x, TEMP[10].xyyy, IMM[2].wwww 51: MOV TEMP[8].w, TEMP[13].xxxx 52: DP4 TEMP[10].x, TEMP[6], CONST[77] 53: DP4 TEMP[14].x, TEMP[6], CONST[78] 54: MOV TEMP[8].z, IMM[2].wwww 55: MOV TEMP[10].z, IMM[3].wwww 56: MOV TEMP[15].w, TEMP[8] 57: ABS TEMP[16].x, TEMP[13].xxxx 58: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 59: UIF TEMP[16].xxxx :0 60: MOV TEMP[16].x, TEMP[8].xxxx 61: ELSE :0 62: MOV TEMP[16].x, TEMP[10].xxxx 63: ENDIF 64: MOV TEMP[15].x, TEMP[16].xxxx 65: ABS TEMP[16].x, TEMP[13].xxxx 66: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 67: UIF TEMP[16].xxxx :0 68: MOV TEMP[9].x, TEMP[9].xxxx 69: ELSE :0 70: MOV TEMP[9].x, TEMP[14].xxxx 71: ENDIF 72: MOV TEMP[15].y, TEMP[9].xxxx 73: ABS TEMP[9].x, TEMP[13].xxxx 74: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].wwww 75: UIF TEMP[9].xxxx :0 76: MOV TEMP[9].x, IMM[2].wwww 77: ELSE :0 78: MOV TEMP[9].x, IMM[3].wwww 79: ENDIF 80: MOV TEMP[15].z, TEMP[9].xxxx 81: MOV TEMP[8].xyz, TEMP[15] 82: MOV TEMP[4].z, IMM[0].wwww 83: MOV TEMP[15].w, TEMP[4] 84: ABS TEMP[9].x, TEMP[7].xxxx 85: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].wwww 86: UIF TEMP[9].xxxx :0 87: MOV TEMP[9].x, TEMP[4].xxxx 88: ELSE :0 89: MOV TEMP[9].x, TEMP[8].xxxx 90: ENDIF 91: MOV TEMP[15].x, TEMP[9].xxxx 92: ABS TEMP[9].x, TEMP[7].xxxx 93: FSGE TEMP[9].x, -TEMP[9].xxxx, IMM[0].wwww 94: UIF TEMP[9].xxxx :0 95: MOV TEMP[5].x, TEMP[5].xxxx 96: ELSE :0 97: MOV TEMP[5].x, TEMP[8].yyyy 98: ENDIF 99: MOV TEMP[15].y, TEMP[5].xxxx 100: ABS TEMP[5].x, TEMP[7].xxxx 101: FSGE TEMP[5].x, -TEMP[5].xxxx, IMM[0].wwww 102: UIF TEMP[5].xxxx :0 103: MOV TEMP[5].x, IMM[0].wwww 104: ELSE :0 105: MOV TEMP[5].x, TEMP[8].zzzz 106: ENDIF 107: MOV TEMP[15].z, TEMP[5].xxxx 108: MOV TEMP[4].zw, TEMP[15].wwzw 109: DP4 TEMP[7].x, TEMP[6], CONST[71] 110: MOV TEMP[8].z, TEMP[7].xxxx 111: ADD TEMP[10].xy, TEMP[15].xyyy, IMM[4].zzzz 112: ABS TEMP[9].xy, TEMP[10].xyyy 113: ADD TEMP[10].xy, TEMP[9].xyyy, -CONST[67].zzzz 114: MUL TEMP[10].xy, TEMP[10].xyyy, CONST[67].wwww 115: MOV_SAT TEMP[9].xy, TEMP[10].xyyy 116: ADD TEMP[10].xy, -TEMP[9].xyyy, IMM[2].wwww 117: MUL TEMP[9].x, TEMP[10].yyyy, TEMP[10].xxxx 118: MOV_SAT TEMP[13].xy, TEMP[15].xyyy 119: ADD TEMP[10].xyz, TEMP[5].xxxx, IMM[5].xyzz 120: ABS TEMP[14].x, TEMP[10].xxxx 121: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 122: UIF TEMP[14].xxxx :0 123: MOV TEMP[14].x, CONST[85].zzzz 124: ELSE :0 125: MOV TEMP[14].x, IMM[0].wwww 126: ENDIF 127: ABS TEMP[16].x, TEMP[10].xxxx 128: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 129: UIF TEMP[16].xxxx :0 130: MOV TEMP[16].x, CONST[85].wwww 131: ELSE :0 132: MOV TEMP[16].x, IMM[0].wwww 133: ENDIF 134: MOV TEMP[15].y, TEMP[16].xxxx 135: ABS TEMP[16].x, TEMP[10].xxxx 136: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 137: UIF TEMP[16].xxxx :0 138: MOV TEMP[16].x, CONST[85].xxxx 139: ELSE :0 140: MOV TEMP[16].x, IMM[0].wwww 141: ENDIF 142: MOV TEMP[15].z, TEMP[16].xxxx 143: ABS TEMP[16].x, TEMP[10].xxxx 144: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 145: UIF TEMP[16].xxxx :0 146: MOV TEMP[16].x, CONST[85].yyyy 147: ELSE :0 148: MOV TEMP[16].x, IMM[0].wwww 149: ENDIF 150: MOV TEMP[15].w, TEMP[16].xxxx 151: ABS TEMP[16].x, TEMP[10].yyyy 152: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 153: UIF TEMP[16].xxxx :0 154: MOV TEMP[16].x, CONST[86].zzzz 155: ELSE :0 156: MOV TEMP[16].x, TEMP[14].xxxx 157: ENDIF 158: ABS TEMP[14].x, TEMP[10].yyyy 159: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 160: UIF TEMP[14].xxxx :0 161: MOV TEMP[14].x, CONST[86].wwww 162: ELSE :0 163: MOV TEMP[14].x, TEMP[15].yyyy 164: ENDIF 165: MOV TEMP[15].y, TEMP[14].xxxx 166: ABS TEMP[14].x, TEMP[10].yyyy 167: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 168: UIF TEMP[14].xxxx :0 169: MOV TEMP[14].x, CONST[86].xxxx 170: ELSE :0 171: MOV TEMP[14].x, TEMP[15].zzzz 172: ENDIF 173: MOV TEMP[15].z, TEMP[14].xxxx 174: ABS TEMP[14].x, TEMP[10].yyyy 175: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 176: UIF TEMP[14].xxxx :0 177: MOV TEMP[14].x, CONST[86].yyyy 178: ELSE :0 179: MOV TEMP[14].x, TEMP[15].wwww 180: ENDIF 181: MOV TEMP[15].w, TEMP[14].xxxx 182: ABS TEMP[14].x, TEMP[10].zzzz 183: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 184: UIF TEMP[14].xxxx :0 185: MOV TEMP[14].x, CONST[87].zzzz 186: ELSE :0 187: MOV TEMP[14].x, TEMP[16].xxxx 188: ENDIF 189: MOV TEMP[15].x, TEMP[14].xxxx 190: ABS TEMP[14].x, TEMP[10].zzzz 191: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 192: UIF TEMP[14].xxxx :0 193: MOV TEMP[14].x, CONST[87].wwww 194: ELSE :0 195: MOV TEMP[14].x, TEMP[15].yyyy 196: ENDIF 197: MOV TEMP[15].y, TEMP[14].xxxx 198: ABS TEMP[14].x, TEMP[10].zzzz 199: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 200: UIF TEMP[14].xxxx :0 201: MOV TEMP[14].x, CONST[87].xxxx 202: ELSE :0 203: MOV TEMP[14].x, TEMP[15].zzzz 204: ENDIF 205: MOV TEMP[15].z, TEMP[14].xxxx 206: ABS TEMP[14].x, TEMP[10].zzzz 207: FSGE TEMP[14].x, -TEMP[14].xxxx, IMM[0].wwww 208: UIF TEMP[14].xxxx :0 209: MOV TEMP[14].x, CONST[87].yyyy 210: ELSE :0 211: MOV TEMP[14].x, TEMP[15].wwww 212: ENDIF 213: MOV TEMP[15].w, TEMP[14].xxxx 214: MAD TEMP[8].xy, TEMP[13].xyyy, TEMP[15].xyyy, TEMP[15].zwww 215: MOV TEMP[8].w, IMM[0].wwww 216: ADD TEMP[5], TEMP[8], IMM[4].wwyy 217: TXL TEMP[13].x, TEMP[5], SAMP[4], SHADOW2D 218: MOV TEMP[5].x, TEMP[13].xxxx 219: ADD TEMP[13], TEMP[8], IMM[6].xyzz 220: ADD TEMP[14], TEMP[8], IMM[6].yxzz 221: ADD TEMP[16], TEMP[8], IMM[6].xxzz 222: TXL TEMP[17].x, TEMP[13], SAMP[4], SHADOW2D 223: MOV TEMP[5].y, TEMP[17].xxxx 224: TXL TEMP[17].x, TEMP[14], SAMP[4], SHADOW2D 225: MOV TEMP[5].z, TEMP[17].xxxx 226: TXL TEMP[17].x, TEMP[16], SAMP[4], SHADOW2D 227: MOV TEMP[5].w, TEMP[17].xxxx 228: DP4 TEMP[17].x, TEMP[5], IMM[5].wwww 229: ADD TEMP[5], TEMP[8], IMM[4].wyyy 230: TXL TEMP[18].x, TEMP[5], SAMP[4], SHADOW2D 231: MOV TEMP[5].x, TEMP[18].xxxx 232: ADD TEMP[13], TEMP[8], IMM[6].xzzz 233: TXL TEMP[18], TEMP[13], SAMP[4], SHADOW2D 234: MOV TEMP[13], TEMP[18] 235: ADD TEMP[14], TEMP[8], IMM[6].zxzz 236: TXL TEMP[19], TEMP[14], SAMP[4], SHADOW2D 237: MOV TEMP[14], TEMP[19] 238: ADD TEMP[16], TEMP[8], IMM[4].ywyy 239: TXL TEMP[16].x, TEMP[16], SAMP[4], SHADOW2D 240: MOV TEMP[5].y, TEMP[18].xxxx 241: MOV TEMP[5].z, TEMP[19].xxxx 242: MOV TEMP[5].w, TEMP[16].xxxx 243: DP4 TEMP[16].x, TEMP[5], IMM[6].wwww 244: MOV TEMP[4].y, TEMP[16].xxxx 245: MOV TEMP[18].xy, TEMP[8].xyyy 246: MOV TEMP[18].z, TEMP[7].xxxx 247: MOV TEMP[18].w, IMM[0].wwww 248: TXL TEMP[18], TEMP[18], SAMP[4], SHADOW2D 249: MOV TEMP[5], TEMP[18] 250: ADD TEMP[4].x, TEMP[16].xxxx, TEMP[17].xxxx 251: MAD TEMP[4].x, TEMP[18].xxxx, IMM[7].xxxx, TEMP[4].xxxx 252: FSLT TEMP[16].x, TEMP[9].xxxx, IMM[2].wwww 253: UIF TEMP[16].xxxx :0 254: ADD TEMP[10].xyz, TEMP[4].zzzz, IMM[7].yzww 255: ABS TEMP[16].x, TEMP[10].xxxx 256: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 257: UIF TEMP[16].xxxx :0 258: MOV TEMP[16].x, CONST[73].xxxx 259: ELSE :0 260: MOV TEMP[16].x, IMM[0].wwww 261: ENDIF 262: MOV TEMP[15].x, TEMP[16].xxxx 263: ABS TEMP[16].x, TEMP[10].xxxx 264: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 265: UIF TEMP[16].xxxx :0 266: MOV TEMP[16].x, CONST[73].yyyy 267: ELSE :0 268: MOV TEMP[16].x, IMM[0].wwww 269: ENDIF 270: MOV TEMP[15].y, TEMP[16].xxxx 271: ABS TEMP[16].x, TEMP[10].xxxx 272: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 273: UIF TEMP[16].xxxx :0 274: MOV TEMP[16].x, CONST[73].zzzz 275: ELSE :0 276: MOV TEMP[16].x, IMM[0].wwww 277: ENDIF 278: MOV TEMP[15].z, TEMP[16].xxxx 279: ABS TEMP[16].x, TEMP[10].xxxx 280: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 281: UIF TEMP[16].xxxx :0 282: MOV TEMP[16].x, CONST[73].wwww 283: ELSE :0 284: MOV TEMP[16].x, IMM[0].wwww 285: ENDIF 286: MOV TEMP[15].w, TEMP[16].xxxx 287: MOV TEMP[5], TEMP[15] 288: ABS TEMP[16].x, TEMP[10].xxxx 289: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 290: UIF TEMP[16].xxxx :0 291: MOV TEMP[16].x, CONST[74].xxxx 292: ELSE :0 293: MOV TEMP[16].x, IMM[0].wwww 294: ENDIF 295: MOV TEMP[15].x, TEMP[16].xxxx 296: ABS TEMP[16].x, TEMP[10].xxxx 297: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 298: UIF TEMP[16].xxxx :0 299: MOV TEMP[16].x, CONST[74].yyyy 300: ELSE :0 301: MOV TEMP[16].x, IMM[0].wwww 302: ENDIF 303: MOV TEMP[15].y, TEMP[16].xxxx 304: ABS TEMP[16].x, TEMP[10].xxxx 305: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 306: UIF TEMP[16].xxxx :0 307: MOV TEMP[16].x, CONST[74].zzzz 308: ELSE :0 309: MOV TEMP[16].x, IMM[0].wwww 310: ENDIF 311: MOV TEMP[15].z, TEMP[16].xxxx 312: ABS TEMP[16].x, TEMP[10].xxxx 313: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 314: UIF TEMP[16].xxxx :0 315: MOV TEMP[16].x, CONST[74].wwww 316: ELSE :0 317: MOV TEMP[16].x, IMM[0].wwww 318: ENDIF 319: MOV TEMP[15].w, TEMP[16].xxxx 320: MOV TEMP[13], TEMP[15] 321: ABS TEMP[16].x, TEMP[10].yyyy 322: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 323: UIF TEMP[16].xxxx :0 324: MOV TEMP[16].x, CONST[77].xxxx 325: ELSE :0 326: MOV TEMP[16].x, TEMP[5].xxxx 327: ENDIF 328: MOV TEMP[15].x, TEMP[16].xxxx 329: ABS TEMP[16].x, TEMP[10].yyyy 330: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 331: UIF TEMP[16].xxxx :0 332: MOV TEMP[16].x, CONST[77].yyyy 333: ELSE :0 334: MOV TEMP[16].x, TEMP[5].yyyy 335: ENDIF 336: MOV TEMP[15].y, TEMP[16].xxxx 337: ABS TEMP[16].x, TEMP[10].yyyy 338: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 339: UIF TEMP[16].xxxx :0 340: MOV TEMP[16].x, CONST[77].zzzz 341: ELSE :0 342: MOV TEMP[16].x, TEMP[5].zzzz 343: ENDIF 344: MOV TEMP[15].z, TEMP[16].xxxx 345: ABS TEMP[16].x, TEMP[10].yyyy 346: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 347: UIF TEMP[16].xxxx :0 348: MOV TEMP[16].x, CONST[77].wwww 349: ELSE :0 350: MOV TEMP[16].x, TEMP[5].wwww 351: ENDIF 352: MOV TEMP[15].w, TEMP[16].xxxx 353: MOV TEMP[5], TEMP[15] 354: ABS TEMP[16].x, TEMP[10].yyyy 355: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 356: UIF TEMP[16].xxxx :0 357: MOV TEMP[16].x, CONST[78].xxxx 358: ELSE :0 359: MOV TEMP[16].x, TEMP[13].xxxx 360: ENDIF 361: MOV TEMP[15].x, TEMP[16].xxxx 362: ABS TEMP[16].x, TEMP[10].yyyy 363: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 364: UIF TEMP[16].xxxx :0 365: MOV TEMP[16].x, CONST[78].yyyy 366: ELSE :0 367: MOV TEMP[16].x, TEMP[13].yyyy 368: ENDIF 369: MOV TEMP[15].y, TEMP[16].xxxx 370: ABS TEMP[16].x, TEMP[10].yyyy 371: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 372: UIF TEMP[16].xxxx :0 373: MOV TEMP[16].x, CONST[78].zzzz 374: ELSE :0 375: MOV TEMP[16].x, TEMP[13].zzzz 376: ENDIF 377: MOV TEMP[15].z, TEMP[16].xxxx 378: ABS TEMP[16].x, TEMP[10].yyyy 379: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 380: UIF TEMP[16].xxxx :0 381: MOV TEMP[16].x, CONST[78].wwww 382: ELSE :0 383: MOV TEMP[16].x, TEMP[13].wwww 384: ENDIF 385: MOV TEMP[15].w, TEMP[16].xxxx 386: MOV TEMP[13], TEMP[15] 387: ABS TEMP[16].x, TEMP[10].zzzz 388: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 389: UIF TEMP[16].xxxx :0 390: MOV TEMP[16].x, CONST[81].xxxx 391: ELSE :0 392: MOV TEMP[16].x, TEMP[5].xxxx 393: ENDIF 394: MOV TEMP[15].x, TEMP[16].xxxx 395: ABS TEMP[16].x, TEMP[10].zzzz 396: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 397: UIF TEMP[16].xxxx :0 398: MOV TEMP[16].x, CONST[81].yyyy 399: ELSE :0 400: MOV TEMP[16].x, TEMP[5].yyyy 401: ENDIF 402: MOV TEMP[15].y, TEMP[16].xxxx 403: ABS TEMP[16].x, TEMP[10].zzzz 404: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 405: UIF TEMP[16].xxxx :0 406: MOV TEMP[16].x, CONST[81].zzzz 407: ELSE :0 408: MOV TEMP[16].x, TEMP[5].zzzz 409: ENDIF 410: MOV TEMP[15].z, TEMP[16].xxxx 411: ABS TEMP[16].x, TEMP[10].zzzz 412: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 413: UIF TEMP[16].xxxx :0 414: MOV TEMP[16].x, CONST[81].wwww 415: ELSE :0 416: MOV TEMP[16].x, TEMP[5].wwww 417: ENDIF 418: MOV TEMP[15].w, TEMP[16].xxxx 419: MOV TEMP[5], TEMP[15] 420: ABS TEMP[16].x, TEMP[10].zzzz 421: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 422: UIF TEMP[16].xxxx :0 423: MOV TEMP[16].x, CONST[82].xxxx 424: ELSE :0 425: MOV TEMP[16].x, TEMP[13].xxxx 426: ENDIF 427: MOV TEMP[15].x, TEMP[16].xxxx 428: ABS TEMP[16].x, TEMP[10].zzzz 429: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 430: UIF TEMP[16].xxxx :0 431: MOV TEMP[16].x, CONST[82].yyyy 432: ELSE :0 433: MOV TEMP[16].x, TEMP[13].yyyy 434: ENDIF 435: MOV TEMP[15].y, TEMP[16].xxxx 436: ABS TEMP[16].x, TEMP[10].zzzz 437: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 438: UIF TEMP[16].xxxx :0 439: MOV TEMP[16].x, CONST[82].zzzz 440: ELSE :0 441: MOV TEMP[16].x, TEMP[13].zzzz 442: ENDIF 443: MOV TEMP[15].z, TEMP[16].xxxx 444: ABS TEMP[16].x, TEMP[10].zzzz 445: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 446: UIF TEMP[16].xxxx :0 447: MOV TEMP[16].x, CONST[82].wwww 448: ELSE :0 449: MOV TEMP[16].x, TEMP[13].wwww 450: ENDIF 451: MOV TEMP[15].w, TEMP[16].xxxx 452: DP4 TEMP[5].x, TEMP[6], TEMP[5] 453: MOV_SAT TEMP[5].x, TEMP[5].xxxx 454: DP4 TEMP[16].x, TEMP[6], TEMP[15] 455: MOV_SAT TEMP[16].x, TEMP[16].xxxx 456: MOV TEMP[5].y, TEMP[16].xxxx 457: ABS TEMP[16].x, TEMP[10].xxxx 458: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 459: UIF TEMP[16].xxxx :0 460: MOV TEMP[16].x, CONST[86].zzzz 461: ELSE :0 462: MOV TEMP[16].x, IMM[0].wwww 463: ENDIF 464: ABS TEMP[17].x, TEMP[10].xxxx 465: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[0].wwww 466: UIF TEMP[17].xxxx :0 467: MOV TEMP[17].x, CONST[86].wwww 468: ELSE :0 469: MOV TEMP[17].x, IMM[0].wwww 470: ENDIF 471: MOV TEMP[15].y, TEMP[17].xxxx 472: ABS TEMP[17].x, TEMP[10].xxxx 473: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[0].wwww 474: UIF TEMP[17].xxxx :0 475: MOV TEMP[17].x, CONST[86].xxxx 476: ELSE :0 477: MOV TEMP[17].x, IMM[0].wwww 478: ENDIF 479: MOV TEMP[15].z, TEMP[17].xxxx 480: ABS TEMP[17].x, TEMP[10].xxxx 481: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[0].wwww 482: UIF TEMP[17].xxxx :0 483: MOV TEMP[17].x, CONST[86].yyyy 484: ELSE :0 485: MOV TEMP[17].x, IMM[0].wwww 486: ENDIF 487: MOV TEMP[15].w, TEMP[17].xxxx 488: ABS TEMP[17].x, TEMP[10].yyyy 489: FSGE TEMP[17].x, -TEMP[17].xxxx, IMM[0].wwww 490: UIF TEMP[17].xxxx :0 491: MOV TEMP[17].x, CONST[87].zzzz 492: ELSE :0 493: MOV TEMP[17].x, TEMP[16].xxxx 494: ENDIF 495: ABS TEMP[16].x, TEMP[10].yyyy 496: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 497: UIF TEMP[16].xxxx :0 498: MOV TEMP[16].x, CONST[87].wwww 499: ELSE :0 500: MOV TEMP[16].x, TEMP[15].yyyy 501: ENDIF 502: MOV TEMP[15].y, TEMP[16].xxxx 503: ABS TEMP[16].x, TEMP[10].yyyy 504: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 505: UIF TEMP[16].xxxx :0 506: MOV TEMP[16].x, CONST[87].xxxx 507: ELSE :0 508: MOV TEMP[16].x, TEMP[15].zzzz 509: ENDIF 510: MOV TEMP[15].z, TEMP[16].xxxx 511: ABS TEMP[16].x, TEMP[10].yyyy 512: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 513: UIF TEMP[16].xxxx :0 514: MOV TEMP[16].x, CONST[87].yyyy 515: ELSE :0 516: MOV TEMP[16].x, TEMP[15].wwww 517: ENDIF 518: MOV TEMP[15].w, TEMP[16].xxxx 519: ABS TEMP[16].x, TEMP[10].zzzz 520: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 521: UIF TEMP[16].xxxx :0 522: MOV TEMP[16].x, CONST[88].zzzz 523: ELSE :0 524: MOV TEMP[16].x, TEMP[17].xxxx 525: ENDIF 526: MOV TEMP[15].x, TEMP[16].xxxx 527: ABS TEMP[16].x, TEMP[10].zzzz 528: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 529: UIF TEMP[16].xxxx :0 530: MOV TEMP[16].x, CONST[88].wwww 531: ELSE :0 532: MOV TEMP[16].x, TEMP[15].yyyy 533: ENDIF 534: MOV TEMP[15].y, TEMP[16].xxxx 535: ABS TEMP[16].x, TEMP[10].zzzz 536: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 537: UIF TEMP[16].xxxx :0 538: MOV TEMP[16].x, CONST[88].xxxx 539: ELSE :0 540: MOV TEMP[16].x, TEMP[15].zzzz 541: ENDIF 542: MOV TEMP[15].z, TEMP[16].xxxx 543: ABS TEMP[16].x, TEMP[10].zzzz 544: FSGE TEMP[16].x, -TEMP[16].xxxx, IMM[0].wwww 545: UIF TEMP[16].xxxx :0 546: MOV TEMP[16].x, CONST[88].yyyy 547: ELSE :0 548: MOV TEMP[16].x, TEMP[15].wwww 549: ENDIF 550: MOV TEMP[15].w, TEMP[16].xxxx 551: MAD TEMP[8].xy, TEMP[5].xyyy, TEMP[15].xyyy, TEMP[15].zwww 552: ADD TEMP[6], TEMP[8], IMM[4].wwyy 553: TXL TEMP[16].x, TEMP[6], SAMP[4], SHADOW2D 554: MOV TEMP[6].x, TEMP[16].xxxx 555: ADD TEMP[5], TEMP[8], IMM[6].xyzz 556: ADD TEMP[13], TEMP[8], IMM[6].yxzz 557: ADD TEMP[14], TEMP[8], IMM[6].xxzz 558: TXL TEMP[16].x, TEMP[5], SAMP[4], SHADOW2D 559: MOV TEMP[6].y, TEMP[16].xxxx 560: TXL TEMP[16].x, TEMP[13], SAMP[4], SHADOW2D 561: MOV TEMP[6].z, TEMP[16].xxxx 562: TXL TEMP[16].x, TEMP[14], SAMP[4], SHADOW2D 563: MOV TEMP[6].w, TEMP[16].xxxx 564: DP4 TEMP[16].x, TEMP[6], IMM[5].wwww 565: ADD TEMP[6], TEMP[8], IMM[4].wyyy 566: TXL TEMP[17].x, TEMP[6], SAMP[4], SHADOW2D 567: MOV TEMP[6].x, TEMP[17].xxxx 568: ADD TEMP[5], TEMP[8], IMM[6].xzzz 569: TXL TEMP[5].x, TEMP[5], SAMP[4], SHADOW2D 570: ADD TEMP[13], TEMP[8], IMM[6].zxzz 571: TXL TEMP[13].x, TEMP[13], SAMP[4], SHADOW2D 572: ADD TEMP[14], TEMP[8], IMM[4].ywyy 573: TXL TEMP[14].x, TEMP[14], SAMP[4], SHADOW2D 574: MOV TEMP[6].y, TEMP[5].xxxx 575: MOV TEMP[6].z, TEMP[13].xxxx 576: MOV TEMP[6].w, TEMP[14].xxxx 577: DP4 TEMP[5].x, TEMP[6], IMM[6].wwww 578: MOV TEMP[4].z, TEMP[5].xxxx 579: MOV TEMP[13].xy, TEMP[8].xyyy 580: MOV TEMP[13].z, TEMP[7].xxxx 581: MOV TEMP[13].w, IMM[0].wwww 582: TXL TEMP[7].x, TEMP[13], SAMP[4], SHADOW2D 583: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[16].xxxx 584: MOV TEMP[4].y, TEMP[5].xxxx 585: MAD TEMP[5].x, TEMP[7].xxxx, IMM[7].xxxx, TEMP[5].xxxx 586: MOV TEMP[4].y, TEMP[5].xxxx 587: MOV TEMP[15].zw, TEMP[4] 588: FSGE TEMP[7].x, TEMP[10].zzzz, IMM[0].wwww 589: UIF TEMP[7].xxxx :0 590: MOV TEMP[7].x, IMM[2].wwww 591: ELSE :0 592: MOV TEMP[7].x, TEMP[5].xxxx 593: ENDIF 594: MOV TEMP[15].y, TEMP[7].xxxx 595: MOV TEMP[4].w, TEMP[15].zyzw 596: LRP TEMP[6].x, TEMP[9].xxxx, TEMP[4].xxxx, TEMP[7].xxxx 597: MOV TEMP[4].x, TEMP[6].xxxx 598: ENDIF 599: ADD TEMP[6].xyz, -CONST[89].xyzz, IN[3].xyzz 600: DP3 TEMP[5].x, TEMP[6].xyzz, TEMP[6].xyzz 601: MAD TEMP[5].x, TEMP[5].xxxx, CONST[68].yyyy, CONST[68].xxxx 602: MOV_SAT TEMP[5].x, TEMP[5].xxxx 603: LRP TEMP[6].x, TEMP[5].xxxx, IMM[2].wwww, TEMP[4].xxxx 604: ADD TEMP[5].x, -TEMP[6].xxxx, IMM[2].wwww 605: MAD TEMP[3].x, TEMP[3].xxxx, -TEMP[5].xxxx, IMM[2].wwww 606: MUL TEMP[4].xyz, TEMP[3].xxxx, TEMP[11].zyxx 607: MAD TEMP[3].x, TEMP[3].xxxx, IMM[8].xxxx, IMM[8].xxxx 608: LRP TEMP[11].xyz, TEMP[3].xxxx, TEMP[4].zyxx, TEMP[4].xyzz 609: ENDIF 610: DP3 TEMP[4].x, TEMP[12].xyzz, IN[4].xyzz 611: DP3 TEMP[3].x, TEMP[12].xyzz, IN[5].xyzz 612: MOV TEMP[4].y, TEMP[3].xxxx 613: DP3 TEMP[3].x, TEMP[12].xyzz, IN[6].xyzz 614: MOV TEMP[4].z, TEMP[3].xxxx 615: ADD TEMP[6].xyz, TEMP[11].xyzz, CONST[31].xyzz 616: DP3 TEMP[3].x, TEMP[4].xyzz, TEMP[0].xyzz 617: ADD TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx 618: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz 619: MUL TEMP[8].xyz, TEMP[0].xyzz, TEMP[5].xxxx 620: MAD TEMP[8].xyz, TEMP[3].xxxx, TEMP[4].xyzz, -TEMP[8].xyzz 621: DP3 TEMP[3].x, TEMP[0].xyzz, TEMP[0].xyzz 622: RSQ TEMP[3].x, TEMP[3].xxxx 623: MUL TEMP[0].xyz, TEMP[3].xxxx, TEMP[0].xyzz 624: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[0].xyzz 625: ADD TEMP[0].x, -TEMP[5].xxxx, IMM[2].wwww 626: MAX TEMP[5].x, TEMP[0].xxxx, IMM[0].wwww 627: MUL TEMP[0].x, TEMP[5].xxxx, TEMP[5].xxxx 628: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx 629: MAD TEMP[0].x, TEMP[0].xxxx, CONST[4].zzzz, CONST[4].wwww 630: MOV TEMP[5].xyz, TEMP[8].xyzz 631: TEX TEMP[5].xyz, TEMP[5], SAMP[2], CUBE 632: MUL TEMP[4].xyz, TEMP[5].xyzz, CONST[30].zzzz 633: MUL TEMP[4].xyz, TEMP[4].wwww, TEMP[4].xyzz 634: MUL TEMP[4].xyz, TEMP[4].xyzz, CONST[0].xyzz 635: MAD TEMP[8].xyz, TEMP[4].xyzz, TEMP[4].xyzz, -TEMP[4].xyzz 636: MAD TEMP[4].xyz, CONST[2].xxxx, TEMP[8].xyzz, TEMP[4].xyzz 637: DP3 TEMP[5].x, TEMP[4].xyzz, IMM[8].yzww 638: LRP TEMP[8].xyz, CONST[3].xxxx, TEMP[4].xyzz, TEMP[5].xxxx 639: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[8].xyzz 640: MAD TEMP[0].xyz, TEMP[2].xyzz, TEMP[6].xyzz, TEMP[0].xyzz 641: RCP TEMP[2].x, TEMP[3].xxxx 642: MAD TEMP[2].x, TEMP[2].xxxx, CONST[11].wwww, CONST[11].xxxx 643: MOV_SAT TEMP[2].x, TEMP[2].xxxx 644: MIN TEMP[2].x, TEMP[2].xxxx, CONST[11].zzzz 645: MUL TEMP[3].xyz, TEMP[0].xyzz, CONST[30].xxxx 646: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx 647: MAD TEMP[0].xyz, TEMP[0].xyzz, -CONST[30].xxxx, CONST[29].xyzz 648: MAD TEMP[1].xyz, TEMP[2].xxxx, TEMP[0].xyzz, TEMP[3].xyzz 649: MOV OUT[0], TEMP[1] 650: END ; ModuleID = 'tgsi' define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { main_body: %23 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0 %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !0 %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 0) %26 = call float @llvm.SI.load.const(<16 x i8> %24, i32 4) %27 = call float @llvm.SI.load.const(<16 x i8> %24, i32 8) %28 = call float @llvm.SI.load.const(<16 x i8> %24, i32 32) %29 = call float @llvm.SI.load.const(<16 x i8> %24, i32 48) %30 = call float @llvm.SI.load.const(<16 x i8> %24, i32 72) %31 = call float @llvm.SI.load.const(<16 x i8> %24, i32 76) %32 = call float @llvm.SI.load.const(<16 x i8> %24, i32 160) %33 = call float @llvm.SI.load.const(<16 x i8> %24, i32 164) %34 = call float @llvm.SI.load.const(<16 x i8> %24, i32 168) %35 = call float @llvm.SI.load.const(<16 x i8> %24, i32 176) %36 = call float @llvm.SI.load.const(<16 x i8> %24, i32 184) %37 = call float @llvm.SI.load.const(<16 x i8> %24, i32 188) %38 = call float @llvm.SI.load.const(<16 x i8> %24, i32 192) %39 = call float @llvm.SI.load.const(<16 x i8> %24, i32 196) %40 = call float @llvm.SI.load.const(<16 x i8> %24, i32 200) %41 = call float @llvm.SI.load.const(<16 x i8> %24, i32 464) %42 = call float @llvm.SI.load.const(<16 x i8> %24, i32 468) %43 = call float @llvm.SI.load.const(<16 x i8> %24, i32 472) %44 = call float @llvm.SI.load.const(<16 x i8> %24, i32 480) %45 = call float @llvm.SI.load.const(<16 x i8> %24, i32 488) %46 = call float @llvm.SI.load.const(<16 x i8> %24, i32 496) %47 = call float @llvm.SI.load.const(<16 x i8> %24, i32 500) %48 = call float @llvm.SI.load.const(<16 x i8> %24, i32 504) %49 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1080) %50 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1084) %51 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1088) %52 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1092) %53 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1168) %54 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1172) %55 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1176) %56 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1180) %57 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1184) %58 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1188) %59 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1192) %60 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1196) %61 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1232) %62 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1236) %63 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1240) %64 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1244) %65 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1248) %66 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1252) %67 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1256) %68 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1260) %69 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1296) %70 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1300) %71 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1304) %72 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1308) %73 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1312) %74 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1316) %75 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1320) %76 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1324) %77 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1376) %78 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1380) %79 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1384) %80 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1388) %81 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1392) %82 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1396) %83 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1400) %84 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1404) %85 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1408) %86 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1412) %87 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1416) %88 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1420) %89 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1424) %90 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1428) %91 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1432) %92 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1440) %93 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 0 %94 = load <8 x i32>, <8 x i32> addrspace(2)* %93, align 32, !tbaa !0 %95 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 0 %96 = load <4 x i32>, <4 x i32> addrspace(2)* %95, align 16, !tbaa !0 %97 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 1 %98 = load <8 x i32>, <8 x i32> addrspace(2)* %97, align 32, !tbaa !0 %99 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 1 %100 = load <4 x i32>, <4 x i32> addrspace(2)* %99, align 16, !tbaa !0 %101 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 2 %102 = load <8 x i32>, <8 x i32> addrspace(2)* %101, align 32, !tbaa !0 %103 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 2 %104 = load <4 x i32>, <4 x i32> addrspace(2)* %103, align 16, !tbaa !0 %105 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 3 %106 = load <8 x i32>, <8 x i32> addrspace(2)* %105, align 32, !tbaa !0 %107 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 3 %108 = load <4 x i32>, <4 x i32> addrspace(2)* %107, align 16, !tbaa !0 %109 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %3, i64 0, i64 4 %110 = load <8 x i32>, <8 x i32> addrspace(2)* %109, align 32, !tbaa !0 %111 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %2, i64 0, i64 4 %112 = load <4 x i32>, <4 x i32> addrspace(2)* %111, align 16, !tbaa !0 %113 = and i32 %5, 1 %114 = icmp ne i32 %113, 0 %115 = select i1 %114, <2 x i32> %7, <2 x i32> %8 %116 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %115) %117 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %115) %118 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %6, <2 x i32> %115) %119 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %115) %120 = and i32 %5, 1 %121 = icmp ne i32 %120, 0 %122 = select i1 %121, <2 x i32> %7, <2 x i32> %8 %123 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %122) %124 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %122) %125 = and i32 %5, 1 %126 = icmp ne i32 %125, 0 %127 = select i1 %126, <2 x i32> %7, <2 x i32> %8 %128 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %127) %129 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %127) %130 = and i32 %5, 1 %131 = icmp ne i32 %130, 0 %132 = select i1 %131, <2 x i32> %7, <2 x i32> %8 %133 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %6, <2 x i32> %132) %134 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %6, <2 x i32> %132) %135 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %6, <2 x i32> %132) %136 = and i32 %5, 1 %137 = icmp ne i32 %136, 0 %138 = select i1 %137, <2 x i32> %7, <2 x i32> %8 %139 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %6, <2 x i32> %138) %140 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %6, <2 x i32> %138) %141 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %6, <2 x i32> %138) %142 = and i32 %5, 1 %143 = icmp ne i32 %142, 0 %144 = select i1 %143, <2 x i32> %7, <2 x i32> %8 %145 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %6, <2 x i32> %144) %146 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %6, <2 x i32> %144) %147 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %6, <2 x i32> %144) %148 = and i32 %5, 1 %149 = icmp ne i32 %148, 0 %150 = select i1 %149, <2 x i32> %7, <2 x i32> %8 %151 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %6, <2 x i32> %150) %152 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %6, <2 x i32> %150) %153 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %6, <2 x i32> %150) %154 = and i32 %5, 1 %155 = icmp ne i32 %154, 0 %156 = select i1 %155, <2 x i32> %7, <2 x i32> %9 %157 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %6, <2 x i32> %156) %158 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %6, <2 x i32> %156) %159 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %6, <2 x i32> %156) %160 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %6, <2 x i32> %156) %161 = and i32 %5, 1 %162 = icmp ne i32 %161, 0 %163 = select i1 %162, <2 x i32> %7, <2 x i32> %9 %164 = call float @llvm.SI.fs.interp(i32 0, i32 8, i32 %6, <2 x i32> %163) %165 = call float @llvm.SI.fs.interp(i32 1, i32 8, i32 %6, <2 x i32> %163) %166 = fsub float %32, %133 %167 = fsub float %33, %134 %168 = fsub float %34, %135 %169 = bitcast float %123 to i32 %170 = bitcast float %124 to i32 %171 = insertelement <2 x i32> undef, i32 %169, i32 0 %172 = insertelement <2 x i32> %171, i32 %170, i32 1 %173 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %172, <8 x i32> %94, <4 x i32> %96, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %174 = extractelement <4 x float> %173, i32 0 %175 = extractelement <4 x float> %173, i32 1 %176 = extractelement <4 x float> %173, i32 2 %177 = extractelement <4 x float> %173, i32 3 %178 = bitcast float %128 to i32 %179 = bitcast float %129 to i32 %180 = insertelement <2 x i32> undef, i32 %178, i32 0 %181 = insertelement <2 x i32> %180, i32 %179, i32 1 %182 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %181, <8 x i32> %106, <4 x i32> %108, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %183 = extractelement <4 x float> %182, i32 0 %184 = extractelement <4 x float> %182, i32 1 %185 = extractelement <4 x float> %182, i32 2 %186 = extractelement <4 x float> %182, i32 3 %187 = bitcast float %157 to i32 %188 = bitcast float %158 to i32 %189 = insertelement <2 x i32> undef, i32 %187, i32 0 %190 = insertelement <2 x i32> %189, i32 %188, i32 1 %191 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %190, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %192 = extractelement <4 x float> %191, i32 0 %193 = extractelement <4 x float> %191, i32 1 %194 = extractelement <4 x float> %191, i32 2 %195 = extractelement <4 x float> %191, i32 3 %196 = bitcast float %160 to i32 %197 = bitcast float %159 to i32 %198 = insertelement <2 x i32> undef, i32 %196, i32 0 %199 = insertelement <2 x i32> %198, i32 %197, i32 1 %200 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %199, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %201 = extractelement <4 x float> %200, i32 0 %202 = extractelement <4 x float> %200, i32 1 %203 = extractelement <4 x float> %200, i32 2 %204 = bitcast float %164 to i32 %205 = bitcast float %165 to i32 %206 = insertelement <2 x i32> undef, i32 %204, i32 0 %207 = insertelement <2 x i32> %206, i32 %205, i32 1 %208 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %207, <8 x i32> %98, <4 x i32> %100, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %209 = extractelement <4 x float> %208, i32 0 %210 = extractelement <4 x float> %208, i32 1 %211 = extractelement <4 x float> %208, i32 2 %212 = fmul float %174, %116 %213 = fmul float %175, %117 %214 = fmul float %176, %118 %215 = fmul float %177, %119 %216 = fmul float %184, %201 %217 = fmul float %184, %202 %218 = fmul float %184, %203 %219 = fmul float %183, %192 %220 = fadd float %219, %216 %221 = fmul float %183, %193 %222 = fadd float %221, %217 %223 = fmul float %183, %194 %224 = fadd float %223, %218 %225 = fmul float %185, %209 %226 = fadd float %225, %220 %227 = fmul float %185, %210 %228 = fadd float %227, %222 %229 = fmul float %185, %211 %230 = fadd float %229, %224 %231 = fmul float %226, %38 %232 = fmul float %228, %39 %233 = fmul float %230, %40 %234 = fmul float %231, 0x3FE279A740000000 %235 = fmul float %232, 0x3FE279A740000000 %236 = fmul float %233, 0x3FE279A740000000 %237 = fmul float %184, 0xBFDA20BDA0000000 %238 = fmul float %184, 0x3FE6A09E60000000 %239 = fmul float %184, 0x3FE279A740000000 %240 = fmul float %183, 0x3FEA20BD80000000 %241 = fadd float %240, %237 %242 = fmul float %183, 0.000000e+00 %243 = fadd float %242, %238 %244 = fmul float %183, 0x3FE279A740000000 %245 = fadd float %244, %239 %246 = fmul float %185, 0xBFDA20BD20000000 %247 = fadd float %246, %241 %248 = fmul float %185, 0xBFE6A09E80000000 %249 = fadd float %248, %243 %250 = fmul float %185, 0x3FE279A740000000 %251 = fadd float %250, %245 %252 = fmul float %247, %247 %253 = fmul float %249, %249 %254 = fadd float %253, %252 %255 = fmul float %251, %251 %256 = fadd float %254, %255 %257 = call float @llvm.AMDGPU.rsq.clamped.f32(float %256) %258 = fmul float %247, %257 %259 = fmul float %249, %257 %260 = fmul float %251, %257 %261 = fcmp ogt float %195, -0.000000e+00 %262 = bitcast float %92 to i32 %263 = icmp ne i32 %262, 0 %264 = and i1 %261, %263 br i1 %264, label %IF, label %ENDIF IF: ; preds = %main_body %265 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1372) %266 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1368) %267 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1364) %268 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1360) %269 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1148) %270 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1144) %271 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1140) %272 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1136) %273 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1132) %274 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1128) %275 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1124) %276 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1120) %277 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1116) %278 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1112) %279 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1108) %280 = call float @llvm.SI.load.const(<16 x i8> %24, i32 1104) %281 = fadd float %192, %201 %282 = fadd float %193, %202 %283 = fadd float %194, %203 %284 = fadd float %209, %281 %285 = fadd float %210, %282 %286 = fadd float %211, %283 %287 = fmul float %284, 0x3FCB333340000000 %288 = fmul float %285, 0x3FE6E48E80000000 %289 = fadd float %288, %287 %290 = fmul float %286, 0x3FB2752540000000 %291 = fadd float %289, %290 %292 = fmul float %291, 0x3FD554C980000000 %293 = fdiv float 1.000000e+00, %292 %294 = fmul float %293, %195 %295 = fadd float %133, 0.000000e+00 %296 = fadd float %134, 0.000000e+00 %297 = fadd float %135, 0.000000e+00 %298 = fmul float %133, 0.000000e+00 %299 = fadd float %298, 1.000000e+00 %300 = fmul float %295, %280 %301 = fmul float %296, %279 %302 = fadd float %300, %301 %303 = fmul float %297, %278 %304 = fadd float %302, %303 %305 = fmul float %299, %277 %306 = fadd float %304, %305 %307 = fmul float %295, %276 %308 = fmul float %296, %275 %309 = fadd float %307, %308 %310 = fmul float %297, %274 %311 = fadd float %309, %310 %312 = fmul float %299, %273 %313 = fadd float %311, %312 %314 = call float @llvm.AMDIL.clamp.(float %306, float 0.000000e+00, float 1.000000e+00) %315 = call float @llvm.AMDIL.clamp.(float %313, float 0.000000e+00, float 1.000000e+00) %316 = fsub float %314, %306 %317 = fsub float %315, %313 %318 = fadd float %316, %317 %319 = fmul float %295, %53 %320 = fmul float %296, %54 %321 = fadd float %319, %320 %322 = fmul float %297, %55 %323 = fadd float %321, %322 %324 = fmul float %299, %56 %325 = fadd float %323, %324 %326 = fmul float %295, %57 %327 = fmul float %296, %58 %328 = fadd float %326, %327 %329 = fmul float %297, %59 %330 = fadd float %328, %329 %331 = fmul float %299, %60 %332 = fadd float %330, %331 %333 = call float @llvm.AMDIL.clamp.(float %325, float 0.000000e+00, float 1.000000e+00) %334 = call float @llvm.AMDIL.clamp.(float %332, float 0.000000e+00, float 1.000000e+00) %335 = fsub float %333, %325 %336 = fsub float %334, %332 %337 = fadd float %335, %336 %338 = fmul float %295, %61 %339 = fmul float %296, %62 %340 = fadd float %338, %339 %341 = fmul float %297, %63 %342 = fadd float %340, %341 %343 = fmul float %299, %64 %344 = fadd float %342, %343 %345 = fmul float %295, %65 %346 = fmul float %296, %66 %347 = fadd float %345, %346 %348 = fmul float %297, %67 %349 = fadd float %347, %348 %350 = fmul float %299, %68 %351 = fadd float %349, %350 %352 = call float @llvm.fabs.f32(float %337) %353 = fcmp ole float %352, -0.000000e+00 %. = select i1 %353, float %325, float %344 %354 = call float @llvm.fabs.f32(float %337) %355 = fcmp ole float %354, -0.000000e+00 %temp36.0 = select i1 %355, float %332, float %351 %356 = call float @llvm.fabs.f32(float %337) %357 = fcmp ole float %356, -0.000000e+00 %.248 = select i1 %357, float 1.000000e+00, float 2.000000e+00 %358 = call float @llvm.fabs.f32(float %318) %359 = fcmp ole float %358, -0.000000e+00 %temp36.2 = select i1 %359, float %306, float %. %360 = call float @llvm.fabs.f32(float %318) %361 = fcmp ole float %360, -0.000000e+00 %.temp36.0 = select i1 %361, float %313, float %temp36.0 %362 = call float @llvm.fabs.f32(float %318) %363 = fcmp ole float %362, -0.000000e+00 %temp20.1 = select i1 %363, float 0.000000e+00, float %.248 %364 = fmul float %295, %272 %365 = fmul float %296, %271 %366 = fadd float %364, %365 %367 = fmul float %297, %270 %368 = fadd float %366, %367 %369 = fmul float %299, %269 %370 = fadd float %368, %369 %371 = fadd float %temp36.2, -5.000000e-01 %372 = fadd float %.temp36.0, -5.000000e-01 %373 = call float @llvm.fabs.f32(float %371) %374 = call float @llvm.fabs.f32(float %372) %375 = fsub float %373, %49 %376 = fsub float %374, %49 %377 = fmul float %375, %50 %378 = fmul float %376, %50 %379 = call float @llvm.AMDIL.clamp.(float %377, float 0.000000e+00, float 1.000000e+00) %380 = call float @llvm.AMDIL.clamp.(float %378, float 0.000000e+00, float 1.000000e+00) %381 = fsub float 1.000000e+00, %379 %382 = fsub float 1.000000e+00, %380 %383 = fmul float %382, %381 %384 = call float @llvm.AMDIL.clamp.(float %temp36.2, float 0.000000e+00, float 1.000000e+00) %385 = call float @llvm.AMDIL.clamp.(float %.temp36.0, float 0.000000e+00, float 1.000000e+00) %386 = fadd float %temp20.1, -1.000000e+00 %387 = fadd float %temp20.1, -2.000000e+00 %388 = call float @llvm.fabs.f32(float %temp20.1) %389 = fcmp ole float %388, -0.000000e+00 %.249 = select i1 %389, float %266, float 0.000000e+00 %390 = call float @llvm.fabs.f32(float %temp20.1) %391 = fcmp ole float %390, -0.000000e+00 %temp64.1 = select i1 %391, float %265, float 0.000000e+00 %392 = call float @llvm.fabs.f32(float %temp20.1) %393 = fcmp ole float %392, -0.000000e+00 %.250 = select i1 %393, float %268, float 0.000000e+00 %394 = call float @llvm.fabs.f32(float %temp20.1) %395 = fcmp ole float %394, -0.000000e+00 %temp64.3 = select i1 %395, float %267, float 0.000000e+00 %396 = call float @llvm.fabs.f32(float %386) %397 = fcmp ole float %396, -0.000000e+00 %..249 = select i1 %397, float %79, float %.249 %398 = call float @llvm.fabs.f32(float %386) %399 = fcmp ole float %398, -0.000000e+00 %temp56.1 = select i1 %399, float %80, float %temp64.1 %400 = call float @llvm.fabs.f32(float %386) %401 = fcmp ole float %400, -0.000000e+00 %..250 = select i1 %401, float %77, float %.250 %402 = call float @llvm.fabs.f32(float %386) %403 = fcmp ole float %402, -0.000000e+00 %temp56.3 = select i1 %403, float %78, float %temp64.3 %404 = call float @llvm.fabs.f32(float %387) %405 = fcmp ole float %404, -0.000000e+00 %...249 = select i1 %405, float %83, float %..249 %406 = call float @llvm.fabs.f32(float %387) %407 = fcmp ole float %406, -0.000000e+00 %temp56.5 = select i1 %407, float %84, float %temp56.1 %408 = call float @llvm.fabs.f32(float %387) %409 = fcmp ole float %408, -0.000000e+00 %...250 = select i1 %409, float %81, float %..250 %410 = call float @llvm.fabs.f32(float %387) %411 = fcmp ole float %410, -0.000000e+00 %temp56.7 = select i1 %411, float %82, float %temp56.3 %412 = fmul float %384, %...249 %413 = fadd float %412, %...250 %414 = fmul float %385, %temp56.5 %415 = fadd float %414, %temp56.7 %416 = fadd float %413, 0x3F40000000000000 %417 = fadd float %415, 0x3F40000000000000 %418 = fadd float %370, 0.000000e+00 %419 = bitcast float %418 to i32 %420 = bitcast float %416 to i32 %421 = bitcast float %417 to i32 %422 = insertelement <4 x i32> undef, i32 %419, i32 0 %423 = insertelement <4 x i32> %422, i32 %420, i32 1 %424 = insertelement <4 x i32> %423, i32 %421, i32 2 %425 = insertelement <4 x i32> %424, i32 0, i32 3 %426 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %425, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %427 = extractelement <4 x float> %426, i32 0 %428 = fadd float %413, 0xBF40000000000000 %429 = fadd float %415, 0x3F40000000000000 %430 = fadd float %370, 0.000000e+00 %431 = fadd float %413, 0x3F40000000000000 %432 = fadd float %415, 0xBF40000000000000 %433 = fadd float %370, 0.000000e+00 %434 = fadd float %413, 0xBF40000000000000 %435 = fadd float %415, 0xBF40000000000000 %436 = fadd float %370, 0.000000e+00 %437 = bitcast float %430 to i32 %438 = bitcast float %428 to i32 %439 = bitcast float %429 to i32 %440 = insertelement <4 x i32> undef, i32 %437, i32 0 %441 = insertelement <4 x i32> %440, i32 %438, i32 1 %442 = insertelement <4 x i32> %441, i32 %439, i32 2 %443 = insertelement <4 x i32> %442, i32 0, i32 3 %444 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %443, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %445 = extractelement <4 x float> %444, i32 0 %446 = bitcast float %433 to i32 %447 = bitcast float %431 to i32 %448 = bitcast float %432 to i32 %449 = insertelement <4 x i32> undef, i32 %446, i32 0 %450 = insertelement <4 x i32> %449, i32 %447, i32 1 %451 = insertelement <4 x i32> %450, i32 %448, i32 2 %452 = insertelement <4 x i32> %451, i32 0, i32 3 %453 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %452, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %454 = extractelement <4 x float> %453, i32 0 %455 = bitcast float %436 to i32 %456 = bitcast float %434 to i32 %457 = bitcast float %435 to i32 %458 = insertelement <4 x i32> undef, i32 %455, i32 0 %459 = insertelement <4 x i32> %458, i32 %456, i32 1 %460 = insertelement <4 x i32> %459, i32 %457, i32 2 %461 = insertelement <4 x i32> %460, i32 0, i32 3 %462 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %461, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %463 = extractelement <4 x float> %462, i32 0 %464 = fmul float %427, 6.250000e-02 %465 = fmul float %445, 6.250000e-02 %466 = fadd float %464, %465 %467 = fmul float %454, 6.250000e-02 %468 = fadd float %466, %467 %469 = fmul float %463, 6.250000e-02 %470 = fadd float %468, %469 %471 = fadd float %413, 0x3F40000000000000 %472 = fadd float %415, 0.000000e+00 %473 = fadd float %370, 0.000000e+00 %474 = bitcast float %473 to i32 %475 = bitcast float %471 to i32 %476 = bitcast float %472 to i32 %477 = insertelement <4 x i32> undef, i32 %474, i32 0 %478 = insertelement <4 x i32> %477, i32 %475, i32 1 %479 = insertelement <4 x i32> %478, i32 %476, i32 2 %480 = insertelement <4 x i32> %479, i32 0, i32 3 %481 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %480, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %482 = extractelement <4 x float> %481, i32 0 %483 = fadd float %413, 0xBF40000000000000 %484 = fadd float %415, 0.000000e+00 %485 = fadd float %370, 0.000000e+00 %486 = bitcast float %485 to i32 %487 = bitcast float %483 to i32 %488 = bitcast float %484 to i32 %489 = insertelement <4 x i32> undef, i32 %486, i32 0 %490 = insertelement <4 x i32> %489, i32 %487, i32 1 %491 = insertelement <4 x i32> %490, i32 %488, i32 2 %492 = insertelement <4 x i32> %491, i32 0, i32 3 %493 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %492, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %494 = extractelement <4 x float> %493, i32 0 %495 = fadd float %413, 0.000000e+00 %496 = fadd float %415, 0xBF40000000000000 %497 = fadd float %370, 0.000000e+00 %498 = bitcast float %497 to i32 %499 = bitcast float %495 to i32 %500 = bitcast float %496 to i32 %501 = insertelement <4 x i32> undef, i32 %498, i32 0 %502 = insertelement <4 x i32> %501, i32 %499, i32 1 %503 = insertelement <4 x i32> %502, i32 %500, i32 2 %504 = insertelement <4 x i32> %503, i32 0, i32 3 %505 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %504, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %506 = extractelement <4 x float> %505, i32 0 %507 = fadd float %413, 0.000000e+00 %508 = fadd float %415, 0x3F40000000000000 %509 = fadd float %370, 0.000000e+00 %510 = bitcast float %509 to i32 %511 = bitcast float %507 to i32 %512 = bitcast float %508 to i32 %513 = insertelement <4 x i32> undef, i32 %510, i32 0 %514 = insertelement <4 x i32> %513, i32 %511, i32 1 %515 = insertelement <4 x i32> %514, i32 %512, i32 2 %516 = insertelement <4 x i32> %515, i32 0, i32 3 %517 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %516, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %518 = extractelement <4 x float> %517, i32 0 %519 = fmul float %482, 1.250000e-01 %520 = fmul float %494, 1.250000e-01 %521 = fadd float %519, %520 %522 = fmul float %506, 1.250000e-01 %523 = fadd float %521, %522 %524 = fmul float %518, 1.250000e-01 %525 = fadd float %523, %524 %526 = bitcast float %370 to i32 %527 = bitcast float %413 to i32 %528 = bitcast float %415 to i32 %529 = insertelement <4 x i32> undef, i32 %526, i32 0 %530 = insertelement <4 x i32> %529, i32 %527, i32 1 %531 = insertelement <4 x i32> %530, i32 %528, i32 2 %532 = insertelement <4 x i32> %531, i32 0, i32 3 %533 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %532, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %534 = extractelement <4 x float> %533, i32 0 %535 = extractelement <4 x float> %533, i32 3 %536 = fadd float %525, %470 %537 = fmul float %534, 2.500000e-01 %538 = fadd float %537, %536 %539 = fcmp olt float %383, 1.000000e+00 br i1 %539, label %IF135, label %ENDIF134 ENDIF: ; preds = %main_body, %ENDIF134 %temp23.0 = phi float [ %temp23.1, %ENDIF134 ], [ %195, %main_body ] %temp44.0 = phi float [ %942, %ENDIF134 ], [ %234, %main_body ] %temp45.0 = phi float [ %946, %ENDIF134 ], [ %235, %main_body ] %temp46.0 = phi float [ %950, %ENDIF134 ], [ %236, %main_body ] %540 = fmul float %258, %139 %541 = fmul float %259, %140 %542 = fadd float %541, %540 %543 = fmul float %260, %141 %544 = fadd float %542, %543 %545 = fmul float %258, %145 %546 = fmul float %259, %146 %547 = fadd float %546, %545 %548 = fmul float %260, %147 %549 = fadd float %547, %548 %550 = fmul float %258, %151 %551 = fmul float %259, %152 %552 = fadd float %551, %550 %553 = fmul float %260, %153 %554 = fadd float %552, %553 %555 = fadd float %temp44.0, %46 %556 = fadd float %temp45.0, %47 %557 = fadd float %temp46.0, %48 %558 = fmul float %544, %166 %559 = fmul float %549, %167 %560 = fadd float %559, %558 %561 = fmul float %554, %168 %562 = fadd float %560, %561 %563 = fadd float %562, %562 %564 = fmul float %544, %544 %565 = fmul float %549, %549 %566 = fadd float %565, %564 %567 = fmul float %554, %554 %568 = fadd float %566, %567 %569 = fmul float %166, %568 %570 = fmul float %167, %568 %571 = fmul float %168, %568 %572 = fmul float %563, %544 %573 = fsub float %572, %569 %574 = fmul float %563, %549 %575 = fsub float %574, %570 %576 = fmul float %563, %554 %577 = fsub float %576, %571 %578 = fmul float %166, %166 %579 = fmul float %167, %167 %580 = fadd float %579, %578 %581 = fmul float %168, %168 %582 = fadd float %580, %581 %583 = call float @llvm.AMDGPU.rsq.clamped.f32(float %582) %584 = fmul float %583, %166 %585 = fmul float %583, %167 %586 = fmul float %583, %168 %587 = fmul float %544, %584 %588 = fmul float %549, %585 %589 = fadd float %588, %587 %590 = fmul float %554, %586 %591 = fadd float %589, %590 %592 = fsub float 1.000000e+00, %591 %593 = call float @llvm.maxnum.f32(float %592, float 0.000000e+00) %594 = fmul float %593, %593 %595 = fmul float %594, %594 %596 = fmul float %595, %30 %597 = fadd float %596, %31 %598 = insertelement <4 x float> undef, float %573, i32 0 %599 = insertelement <4 x float> %598, float %575, i32 1 %600 = insertelement <4 x float> %599, float %577, i32 2 %601 = insertelement <4 x float> %600, float %temp23.0, i32 3 %602 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %601) %603 = extractelement <4 x float> %602, i32 0 %604 = extractelement <4 x float> %602, i32 1 %605 = extractelement <4 x float> %602, i32 2 %606 = extractelement <4 x float> %602, i32 3 %607 = call float @llvm.fabs.f32(float %605) %608 = fdiv float 1.000000e+00, %607 %609 = fmul float %603, %608 %610 = fadd float %609, 1.500000e+00 %611 = fmul float %604, %608 %612 = fadd float %611, 1.500000e+00 %613 = bitcast float %612 to i32 %614 = bitcast float %610 to i32 %615 = bitcast float %606 to i32 %616 = insertelement <4 x i32> undef, i32 %613, i32 0 %617 = insertelement <4 x i32> %616, i32 %614, i32 1 %618 = insertelement <4 x i32> %617, i32 %615, i32 2 %619 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %618, <8 x i32> %102, <4 x i32> %104, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %620 = extractelement <4 x float> %619, i32 0 %621 = extractelement <4 x float> %619, i32 1 %622 = extractelement <4 x float> %619, i32 2 %623 = fmul float %620, %45 %624 = fmul float %621, %45 %625 = fmul float %622, %45 %626 = fmul float %186, %623 %627 = fmul float %186, %624 %628 = fmul float %186, %625 %629 = fmul float %626, %25 %630 = fmul float %627, %26 %631 = fmul float %628, %27 %632 = fmul float %629, %629 %633 = fsub float %632, %629 %634 = fmul float %630, %630 %635 = fsub float %634, %630 %636 = fmul float %631, %631 %637 = fsub float %636, %631 %638 = fmul float %28, %633 %639 = fadd float %638, %629 %640 = fmul float %28, %635 %641 = fadd float %640, %630 %642 = fmul float %28, %637 %643 = fadd float %642, %631 %644 = fmul float %639, 0x3FD322D0E0000000 %645 = fmul float %641, 0x3FE2C8B440000000 %646 = fadd float %645, %644 %647 = fmul float %643, 0x3FBD2F1AA0000000 %648 = fadd float %646, %647 %649 = fsub float 1.000000e+00, %29 %650 = fmul float %639, %29 %651 = fmul float %648, %649 %652 = fadd float %650, %651 %653 = fsub float 1.000000e+00, %29 %654 = fmul float %641, %29 %655 = fmul float %648, %653 %656 = fadd float %654, %655 %657 = fsub float 1.000000e+00, %29 %658 = fmul float %643, %29 %659 = fmul float %648, %657 %660 = fadd float %658, %659 %661 = fmul float %597, %652 %662 = fmul float %597, %656 %663 = fmul float %597, %660 %664 = fmul float %212, %555 %665 = fadd float %664, %661 %666 = fmul float %213, %556 %667 = fadd float %666, %662 %668 = fmul float %214, %557 %669 = fadd float %668, %663 %670 = fdiv float 1.000000e+00, %583 %671 = fmul float %670, %37 %672 = fadd float %671, %35 %673 = call float @llvm.AMDIL.clamp.(float %672, float 0.000000e+00, float 1.000000e+00) %674 = call float @llvm.minnum.f32(float %673, float %36) %675 = fmul float %665, %44 %676 = fmul float %667, %44 %677 = fmul float %669, %44 %678 = fmul float %674, %674 %679 = fmul float %44, %665 %680 = fsub float %41, %679 %681 = fmul float %44, %667 %682 = fsub float %42, %681 %683 = fmul float %44, %669 %684 = fsub float %43, %683 %685 = fmul float %678, %680 %686 = fadd float %685, %675 %687 = fmul float %678, %682 %688 = fadd float %687, %676 %689 = fmul float %678, %684 %690 = fadd float %689, %677 %691 = call i32 @llvm.SI.packf16(float %686, float %688) %692 = bitcast i32 %691 to float %693 = call i32 @llvm.SI.packf16(float %690, float %215) %694 = bitcast i32 %693 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %692, float %694, float %692, float %694) ret void IF135: ; preds = %IF %695 = fadd float %temp20.1, 0.000000e+00 %696 = fadd float %temp20.1, -1.000000e+00 %697 = fadd float %temp20.1, -2.000000e+00 %698 = call float @llvm.fabs.f32(float %695) %699 = fcmp ole float %698, -0.000000e+00 %.251 = select i1 %699, float %53, float 0.000000e+00 %700 = call float @llvm.fabs.f32(float %695) %701 = fcmp ole float %700, -0.000000e+00 %temp64.6 = select i1 %701, float %54, float 0.000000e+00 %702 = call float @llvm.fabs.f32(float %695) %703 = fcmp ole float %702, -0.000000e+00 %.252 = select i1 %703, float %55, float 0.000000e+00 %704 = call float @llvm.fabs.f32(float %695) %705 = fcmp ole float %704, -0.000000e+00 %temp64.8 = select i1 %705, float %56, float 0.000000e+00 %706 = call float @llvm.fabs.f32(float %695) %707 = fcmp ole float %706, -0.000000e+00 %.253 = select i1 %707, float %57, float 0.000000e+00 %708 = call float @llvm.fabs.f32(float %695) %709 = fcmp ole float %708, -0.000000e+00 %temp64.10 = select i1 %709, float %58, float 0.000000e+00 %710 = call float @llvm.fabs.f32(float %695) %711 = fcmp ole float %710, -0.000000e+00 %.254 = select i1 %711, float %59, float 0.000000e+00 %712 = call float @llvm.fabs.f32(float %695) %713 = fcmp ole float %712, -0.000000e+00 %temp64.12 = select i1 %713, float %60, float 0.000000e+00 %714 = call float @llvm.fabs.f32(float %696) %715 = fcmp ole float %714, -0.000000e+00 %..251 = select i1 %715, float %61, float %.251 %716 = call float @llvm.fabs.f32(float %696) %717 = fcmp ole float %716, -0.000000e+00 %temp64.14 = select i1 %717, float %62, float %temp64.6 %718 = call float @llvm.fabs.f32(float %696) %719 = fcmp ole float %718, -0.000000e+00 %..252 = select i1 %719, float %63, float %.252 %720 = call float @llvm.fabs.f32(float %696) %721 = fcmp ole float %720, -0.000000e+00 %temp64.16 = select i1 %721, float %64, float %temp64.8 %722 = call float @llvm.fabs.f32(float %696) %723 = fcmp ole float %722, -0.000000e+00 %..253 = select i1 %723, float %65, float %.253 %724 = call float @llvm.fabs.f32(float %696) %725 = fcmp ole float %724, -0.000000e+00 %temp64.18 = select i1 %725, float %66, float %temp64.10 %726 = call float @llvm.fabs.f32(float %696) %727 = fcmp ole float %726, -0.000000e+00 %..254 = select i1 %727, float %67, float %.254 %728 = call float @llvm.fabs.f32(float %696) %729 = fcmp ole float %728, -0.000000e+00 %temp64.20 = select i1 %729, float %68, float %temp64.12 %730 = call float @llvm.fabs.f32(float %697) %731 = fcmp ole float %730, -0.000000e+00 %...251 = select i1 %731, float %69, float %..251 %732 = call float @llvm.fabs.f32(float %697) %733 = fcmp ole float %732, -0.000000e+00 %temp64.22 = select i1 %733, float %70, float %temp64.14 %734 = call float @llvm.fabs.f32(float %697) %735 = fcmp ole float %734, -0.000000e+00 %...252 = select i1 %735, float %71, float %..252 %736 = call float @llvm.fabs.f32(float %697) %737 = fcmp ole float %736, -0.000000e+00 %temp64.24 = select i1 %737, float %72, float %temp64.16 %738 = call float @llvm.fabs.f32(float %697) %739 = fcmp ole float %738, -0.000000e+00 %...253 = select i1 %739, float %73, float %..253 %740 = call float @llvm.fabs.f32(float %697) %741 = fcmp ole float %740, -0.000000e+00 %temp64.26 = select i1 %741, float %74, float %temp64.18 %742 = call float @llvm.fabs.f32(float %697) %743 = fcmp ole float %742, -0.000000e+00 %...254 = select i1 %743, float %75, float %..254 %744 = call float @llvm.fabs.f32(float %697) %745 = fcmp ole float %744, -0.000000e+00 %temp64.28 = select i1 %745, float %76, float %temp64.20 %746 = fmul float %295, %...251 %747 = fmul float %296, %temp64.22 %748 = fadd float %746, %747 %749 = fmul float %297, %...252 %750 = fadd float %748, %749 %751 = fmul float %299, %temp64.24 %752 = fadd float %750, %751 %753 = call float @llvm.AMDIL.clamp.(float %752, float 0.000000e+00, float 1.000000e+00) %754 = fmul float %295, %...253 %755 = fmul float %296, %temp64.26 %756 = fadd float %754, %755 %757 = fmul float %297, %...254 %758 = fadd float %756, %757 %759 = fmul float %299, %temp64.28 %760 = fadd float %758, %759 %761 = call float @llvm.AMDIL.clamp.(float %760, float 0.000000e+00, float 1.000000e+00) %762 = call float @llvm.fabs.f32(float %695) %763 = fcmp ole float %762, -0.000000e+00 %.255 = select i1 %763, float %79, float 0.000000e+00 %764 = call float @llvm.fabs.f32(float %695) %765 = fcmp ole float %764, -0.000000e+00 %temp68.0 = select i1 %765, float %80, float 0.000000e+00 %766 = call float @llvm.fabs.f32(float %695) %767 = fcmp ole float %766, -0.000000e+00 %.256 = select i1 %767, float %77, float 0.000000e+00 %768 = call float @llvm.fabs.f32(float %695) %769 = fcmp ole float %768, -0.000000e+00 %temp68.2 = select i1 %769, float %78, float 0.000000e+00 %770 = call float @llvm.fabs.f32(float %696) %771 = fcmp ole float %770, -0.000000e+00 %..255 = select i1 %771, float %83, float %.255 %772 = call float @llvm.fabs.f32(float %696) %773 = fcmp ole float %772, -0.000000e+00 %temp64.30 = select i1 %773, float %84, float %temp68.0 %774 = call float @llvm.fabs.f32(float %696) %775 = fcmp ole float %774, -0.000000e+00 %..256 = select i1 %775, float %81, float %.256 %776 = call float @llvm.fabs.f32(float %696) %777 = fcmp ole float %776, -0.000000e+00 %temp64.32 = select i1 %777, float %82, float %temp68.2 %778 = call float @llvm.fabs.f32(float %697) %779 = fcmp ole float %778, -0.000000e+00 %...255 = select i1 %779, float %87, float %..255 %780 = call float @llvm.fabs.f32(float %697) %781 = fcmp ole float %780, -0.000000e+00 %temp64.34 = select i1 %781, float %88, float %temp64.30 %782 = call float @llvm.fabs.f32(float %697) %783 = fcmp ole float %782, -0.000000e+00 %...256 = select i1 %783, float %85, float %..256 %784 = call float @llvm.fabs.f32(float %697) %785 = fcmp ole float %784, -0.000000e+00 %temp64.36 = select i1 %785, float %86, float %temp64.32 %786 = fmul float %753, %...255 %787 = fadd float %786, %...256 %788 = fmul float %761, %temp64.34 %789 = fadd float %788, %temp64.36 %790 = fadd float %787, 0x3F40000000000000 %791 = fadd float %789, 0x3F40000000000000 %792 = fadd float %370, 0.000000e+00 %793 = bitcast float %792 to i32 %794 = bitcast float %790 to i32 %795 = bitcast float %791 to i32 %796 = insertelement <4 x i32> undef, i32 %793, i32 0 %797 = insertelement <4 x i32> %796, i32 %794, i32 1 %798 = insertelement <4 x i32> %797, i32 %795, i32 2 %799 = insertelement <4 x i32> %798, i32 0, i32 3 %800 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %799, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %801 = extractelement <4 x float> %800, i32 0 %802 = fadd float %787, 0xBF40000000000000 %803 = fadd float %789, 0x3F40000000000000 %804 = fadd float %370, 0.000000e+00 %805 = fadd float %787, 0x3F40000000000000 %806 = fadd float %789, 0xBF40000000000000 %807 = fadd float %370, 0.000000e+00 %808 = fadd float %787, 0xBF40000000000000 %809 = fadd float %789, 0xBF40000000000000 %810 = fadd float %370, 0.000000e+00 %811 = bitcast float %804 to i32 %812 = bitcast float %802 to i32 %813 = bitcast float %803 to i32 %814 = insertelement <4 x i32> undef, i32 %811, i32 0 %815 = insertelement <4 x i32> %814, i32 %812, i32 1 %816 = insertelement <4 x i32> %815, i32 %813, i32 2 %817 = insertelement <4 x i32> %816, i32 0, i32 3 %818 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %817, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %819 = extractelement <4 x float> %818, i32 0 %820 = bitcast float %807 to i32 %821 = bitcast float %805 to i32 %822 = bitcast float %806 to i32 %823 = insertelement <4 x i32> undef, i32 %820, i32 0 %824 = insertelement <4 x i32> %823, i32 %821, i32 1 %825 = insertelement <4 x i32> %824, i32 %822, i32 2 %826 = insertelement <4 x i32> %825, i32 0, i32 3 %827 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %826, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %828 = extractelement <4 x float> %827, i32 0 %829 = bitcast float %810 to i32 %830 = bitcast float %808 to i32 %831 = bitcast float %809 to i32 %832 = insertelement <4 x i32> undef, i32 %829, i32 0 %833 = insertelement <4 x i32> %832, i32 %830, i32 1 %834 = insertelement <4 x i32> %833, i32 %831, i32 2 %835 = insertelement <4 x i32> %834, i32 0, i32 3 %836 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %835, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %837 = extractelement <4 x float> %836, i32 0 %838 = fmul float %801, 6.250000e-02 %839 = fmul float %819, 6.250000e-02 %840 = fadd float %838, %839 %841 = fmul float %828, 6.250000e-02 %842 = fadd float %840, %841 %843 = fmul float %837, 6.250000e-02 %844 = fadd float %842, %843 %845 = fadd float %787, 0x3F40000000000000 %846 = fadd float %789, 0.000000e+00 %847 = fadd float %370, 0.000000e+00 %848 = bitcast float %847 to i32 %849 = bitcast float %845 to i32 %850 = bitcast float %846 to i32 %851 = insertelement <4 x i32> undef, i32 %848, i32 0 %852 = insertelement <4 x i32> %851, i32 %849, i32 1 %853 = insertelement <4 x i32> %852, i32 %850, i32 2 %854 = insertelement <4 x i32> %853, i32 0, i32 3 %855 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %854, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %856 = extractelement <4 x float> %855, i32 0 %857 = fadd float %787, 0xBF40000000000000 %858 = fadd float %789, 0.000000e+00 %859 = fadd float %370, 0.000000e+00 %860 = bitcast float %859 to i32 %861 = bitcast float %857 to i32 %862 = bitcast float %858 to i32 %863 = insertelement <4 x i32> undef, i32 %860, i32 0 %864 = insertelement <4 x i32> %863, i32 %861, i32 1 %865 = insertelement <4 x i32> %864, i32 %862, i32 2 %866 = insertelement <4 x i32> %865, i32 0, i32 3 %867 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %866, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %868 = extractelement <4 x float> %867, i32 0 %869 = fadd float %787, 0.000000e+00 %870 = fadd float %789, 0xBF40000000000000 %871 = fadd float %370, 0.000000e+00 %872 = bitcast float %871 to i32 %873 = bitcast float %869 to i32 %874 = bitcast float %870 to i32 %875 = insertelement <4 x i32> undef, i32 %872, i32 0 %876 = insertelement <4 x i32> %875, i32 %873, i32 1 %877 = insertelement <4 x i32> %876, i32 %874, i32 2 %878 = insertelement <4 x i32> %877, i32 0, i32 3 %879 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %878, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %880 = extractelement <4 x float> %879, i32 0 %881 = fadd float %787, 0.000000e+00 %882 = fadd float %789, 0x3F40000000000000 %883 = fadd float %370, 0.000000e+00 %884 = bitcast float %883 to i32 %885 = bitcast float %881 to i32 %886 = bitcast float %882 to i32 %887 = insertelement <4 x i32> undef, i32 %884, i32 0 %888 = insertelement <4 x i32> %887, i32 %885, i32 1 %889 = insertelement <4 x i32> %888, i32 %886, i32 2 %890 = insertelement <4 x i32> %889, i32 0, i32 3 %891 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %890, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %892 = extractelement <4 x float> %891, i32 0 %893 = fmul float %856, 1.250000e-01 %894 = fmul float %868, 1.250000e-01 %895 = fadd float %893, %894 %896 = fmul float %880, 1.250000e-01 %897 = fadd float %895, %896 %898 = fmul float %892, 1.250000e-01 %899 = fadd float %897, %898 %900 = bitcast float %370 to i32 %901 = bitcast float %787 to i32 %902 = bitcast float %789 to i32 %903 = insertelement <4 x i32> undef, i32 %900, i32 0 %904 = insertelement <4 x i32> %903, i32 %901, i32 1 %905 = insertelement <4 x i32> %904, i32 %902, i32 2 %906 = insertelement <4 x i32> %905, i32 0, i32 3 %907 = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> %906, <8 x i32> %110, <4 x i32> %112, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %908 = extractelement <4 x float> %907, i32 0 %909 = fadd float %899, %844 %910 = fmul float %908, 2.500000e-01 %911 = fadd float %910, %909 %912 = fcmp oge float %697, 0.000000e+00 %.257 = select i1 %912, float 1.000000e+00, float %911 %913 = fsub float 1.000000e+00, %383 %914 = fmul float %538, %383 %915 = fmul float %.257, %913 %916 = fadd float %914, %915 br label %ENDIF134 ENDIF134: ; preds = %IF, %IF135 %temp16.0 = phi float [ %916, %IF135 ], [ %538, %IF ] %temp23.1 = phi float [ 0.000000e+00, %IF135 ], [ %535, %IF ] %917 = fsub float %133, %89 %918 = fsub float %134, %90 %919 = fsub float %135, %91 %920 = fmul float %917, %917 %921 = fmul float %918, %918 %922 = fadd float %921, %920 %923 = fmul float %919, %919 %924 = fadd float %922, %923 %925 = fmul float %924, %52 %926 = fadd float %925, %51 %927 = call float @llvm.AMDIL.clamp.(float %926, float 0.000000e+00, float 1.000000e+00) %928 = fsub float 1.000000e+00, %927 %929 = fmul float %temp16.0, %928 %930 = fadd float %927, %929 %931 = fsub float 1.000000e+00, %930 %932 = fmul float %931, %294 %933 = fsub float 1.000000e+00, %932 %934 = fmul float %933, %236 %935 = fmul float %933, %235 %936 = fmul float %933, %234 %937 = fmul float %933, 5.000000e-01 %938 = fadd float %937, 5.000000e-01 %939 = fsub float 1.000000e+00, %938 %940 = fmul float %936, %938 %941 = fmul float %934, %939 %942 = fadd float %940, %941 %943 = fsub float 1.000000e+00, %938 %944 = fmul float %935, %938 %945 = fmul float %935, %943 %946 = fadd float %944, %945 %947 = fsub float 1.000000e+00, %938 %948 = fmul float %934, %938 %949 = fmul float %936, %947 %950 = fadd float %948, %949 br label %ENDIF } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = !{!"const", null, i32 1} ERROR: ld.so: object '/home/ernst/.local/share/Steam/ubuntu12_64/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded (wrong ELF class: ELFCLASS64): ignored. assert_20151120170023_1.dmp[3408]: Uploading dump (out-of-process) /tmp/dumps/assert_20151120170023_1.dmp /home/Gemensamt/Spel/Steam/steamapps/common/Counter-Strike Global Offensive/csgo.sh: rad 57: 3278 Segmenteringsfel ${DEBUGGER} "${GAMEROOT}"/${GAMEEXE} "$@" Game removed: AppID 730 "Counter-Strike: Global Offensive", ProcID 3278 assert_20151120170023_1.dmp[3408]: Finished uploading minidump (out-of-process): success = yes assert_20151120170023_1.dmp[3408]: response: CrashID=bp-9b6351c2-e4f0-4abc-894b-b9f1d2151120 assert_20151120170023_1.dmp[3408]: file ''/tmp/dumps/assert_20151120170023_1.dmp'', upload yes: ''CrashID=bp-9b6351c2-e4f0-4abc-894b-b9f1d2151120'' pid 3408 != 3407, skipping destruction (fork without exec?) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378) Installing breakpad exception handler for appid(steam)/version(1447125378)