VM fault report. Driver vendor: X.Org Device vendor: AMD Device name: AMD BONAIRE (DRM 2.43.0, LLVM 3.8.0) Failing VM page: 0x00095080 Buffer list (in units of pages = 4kB):  Size VM start page VM end page Usage 16 0x0000000000871 0x0000000000881 BORDER_COLORS 1 0x0000000000881 0x0000000000882 USER_SHADER 1 -- hole -- 1 0x0000000000883 0x0000000000884 CONST_BUFFER 192 -- hole -- 64 0x0000000000944 0x0000000000984 SAMPLER_TEXTURE 136 -- hole -- 1 0x0000000000a0c 0x0000000000a0d VERTEX_BUFFER 8 -- hole -- 1 0x0000000000a15 0x0000000000a16 VERTEX_BUFFER 74 -- hole -- 64 0x0000000000a60 0x0000000000aa0 INDEX_BUFFER 68 -- hole -- 1 0x0000000000ae4 0x0000000000ae5 VERTEX_BUFFER 15 -- hole -- 1 0x0000000000af4 0x0000000000af5 SAMPLER_TEXTURE 5 -- hole -- 1 0x0000000000afa 0x0000000000afb SAMPLER_TEXTURE 1 0x0000000000afb 0x0000000000afc SAMPLER_TEXTURE 7 -- hole -- 1 0x0000000000b03 0x0000000000b04 INDEX_BUFFER 16004 -- hole -- 256 0x0000000004988 0x0000000004a88 CONST_BUFFER, DESCRIPTORS 200 -- hole -- 18 0x0000000004b50 0x0000000004b62 HTILE 363 -- hole -- 1 0x0000000004ccd 0x0000000004cce CONST_BUFFER 1105 -- hole -- 1 0x000000000511f 0x0000000005120 USER_SHADER 31 -- hole -- 1 0x000000000513f 0x0000000005140 USER_SHADER 72 -- hole -- 1 0x0000000005188 0x0000000005189 USER_SHADER 1 0x0000000005189 0x000000000518a USER_SHADER 1 0x000000000518a 0x000000000518b USER_SHADER 1 -- hole -- 1 0x000000000518c 0x000000000518d USER_SHADER 1 0x000000000518d 0x000000000518e USER_SHADER 1 0x000000000518e 0x000000000518f USER_SHADER 1 0x000000000518f 0x0000000005190 USER_SHADER 100 -- hole -- 120 0x00000000051f4 0x000000000526c SAMPLER_TEXTURE 115 -- hole -- 1 0x00000000052df 0x00000000052e0 IB2 287 -- hole -- 1 0x00000000053ff 0x0000000005400 USER_SHADER 12 -- hole -- 4 0x000000000540c 0x0000000005410 SAMPLER_TEXTURE 281 -- hole -- 256 0x0000000005529 0x0000000005629 VERTEX_BUFFER 256 0x0000000005629 0x0000000005729 INDEX_BUFFER 746 -- hole -- 1 0x0000000005a13 0x0000000005a14 USER_SHADER 73 -- hole -- 1 0x0000000005a5d 0x0000000005a5e CONST_BUFFER 299 -- hole -- 1 0x0000000005b89 0x0000000005b8a SAMPLER_TEXTURE 6 -- hole -- 1024 0x0000000005b90 0x0000000005f90 SAMPLER_TEXTURE 13312 -- hole -- 1080 0x0000000009390 0x00000000097c8 SAMPLER_TEXTURE, DEPTH_BUFFER 2304 -- hole -- 512 0x000000000a0c8 0x000000000a2c8 SAMPLER_TEXTURE, COLOR_BUFFER 512 0x000000000a2c8 0x000000000a4c8 SAMPLER_TEXTURE, COLOR_BUFFER 512 0x000000000a4c8 0x000000000a6c8 SAMPLER_TEXTURE, COLOR_BUFFER 512 0x000000000a6c8 0x000000000a8c8 SAMPLER_TEXTURE, COLOR_BUFFER 512 0x000000000a8c8 0x000000000aac8 SAMPLER_TEXTURE, COLOR_BUFFER 512 0x000000000aac8 0x000000000acc8 SAMPLER_TEXTURE, COLOR_BUFFER 1712 -- hole -- 748 0x000000000b378 0x000000000b664 SAMPLER_TEXTURE 748 0x000000000b664 0x000000000b950 SAMPLER_TEXTURE 748 -- hole -- 748 0x000000000bc3c 0x000000000bf28 SAMPLER_TEXTURE, COLOR_BUFFER 2248 -- hole -- 748 0x000000000c7f0 0x000000000cadc SAMPLER_TEXTURE 640 -- hole -- 480 0x000000000cd5c 0x000000000cf3c RINGS_STREAMOUT 384 0x000000000cf3c 0x000000000d0bc RINGS_STREAMOUT 2 0x000000000d0bc 0x000000000d0be CP_DMA, CMASK 1 -- hole -- 1 0x000000000d0bf 0x000000000d0c0 USER_SHADER 5496 -- hole -- 1496 0x000000000e638 0x000000000ec10 SAMPLER_TEXTURE 481 -- hole -- 2 0x000000000edf1 0x000000000edf3 CMASK 677 -- hole -- 1496 0x000000000f098 0x000000000f670 SAMPLER_TEXTURE, COLOR_BUFFER 1496 -- hole -- 1496 0x000000000fc48 0x0000000010220 SAMPLER_TEXTURE, COLOR_BUFFER 2136 -- hole -- 2 0x0000000010a78 0x0000000010a7a SAMPLER_TEXTURE 334 -- hole -- 2 0x0000000010bc8 0x0000000010bca SAMPLER_TEXTURE 14 -- hole -- 2 0x0000000010bd8 0x0000000010bda SAMPLER_TEXTURE 598 -- hole -- 3 0x0000000010e30 0x0000000010e33 SAMPLER_TEXTURE 6218 -- hole -- 1 0x000000001267d 0x000000001267e INDEX_BUFFER 1 0x000000001267e 0x000000001267f VERTEX_BUFFER 1 0x000000001267f 0x0000000012680 VERTEX_BUFFER 296 -- hole -- 2 0x00000000127a8 0x00000000127aa SAMPLER_TEXTURE 910 -- hole -- 1 0x0000000012b38 0x0000000012b39 CONST_BUFFER 13210 -- hole -- 5 0x0000000015ed3 0x0000000015ed8 VERTEX_BUFFER 2 -- hole -- 6 0x0000000015eda 0x0000000015ee0 VERTEX_BUFFER 3 -- hole -- 3 0x0000000015ee3 0x0000000015ee6 INDEX_BUFFER 1 0x0000000015ee6 0x0000000015ee7 SAMPLER_TEXTURE 1 0x0000000015ee7 0x0000000015ee8 CONST_BUFFER 36096 -- hole -- 128 0x000000001ebe8 0x000000001ec68 SAMPLER_TEXTURE 310 -- hole -- 1 0x000000001ed9e 0x000000001ed9f USER_SHADER 1 0x000000001ed9f 0x000000001eda0 USER_SHADER 636 -- hole -- 1 0x000000001f01c 0x000000001f01d USER_SHADER 2 0x000000001f01d 0x000000001f01f USER_SHADER 1 0x000000001f01f 0x000000001f020 CONST_BUFFER 46 -- hole -- 1 0x000000001f04e 0x000000001f04f USER_SHADER 1 0x000000001f04f 0x000000001f050 USER_SHADER 4 -- hole -- 1 0x000000001f054 0x000000001f055 USER_SHADER 1 0x000000001f055 0x000000001f056 USER_SHADER 1 0x000000001f056 0x000000001f057 USER_SHADER 8 -- hole -- 1 0x000000001f05f 0x000000001f060 USER_SHADER 1552 -- hole -- 2 0x000000001f670 0x000000001f672 SAMPLER_TEXTURE 6 -- hole -- 2 0x000000001f678 0x000000001f67a SAMPLER_TEXTURE 1 0x000000001f67a 0x000000001f67b CONST_BUFFER 799 -- hole -- 86 0x000000001f99a 0x000000001f9f0 VERTEX_BUFFER 90 -- hole -- 1 0x000000001fa4a 0x000000001fa4b CONST_BUFFER 2628 -- hole -- 1 0x000000002048f 0x0000000020490 CONST_BUFFER 1892 -- hole -- 6 0x0000000020bf4 0x0000000020bfa SAMPLER_TEXTURE 233 -- hole -- 84 0x0000000020ce3 0x0000000020d37 INDEX_BUFFER 143 0x0000000020d37 0x0000000020dc6 VERTEX_BUFFER 8246 -- hole -- 1 0x0000000022dfc 0x0000000022dfd CONST_BUFFER 14 -- hole -- 1 0x0000000022e0b 0x0000000022e0c CONST_BUFFER 1 0x0000000022e0c 0x0000000022e0d CONST_BUFFER 1 0x0000000022e0d 0x0000000022e0e CONST_BUFFER 5 -- hole -- 1 0x0000000022e13 0x0000000022e14 CONST_BUFFER 1 -- hole -- 1 0x0000000022e15 0x0000000022e16 CONST_BUFFER 1 -- hole -- 1 0x0000000022e17 0x0000000022e18 CONST_BUFFER 3021 -- hole -- 1 0x00000000239e5 0x00000000239e6 CONST_BUFFER 17382 -- hole -- 16 0x0000000027dcc 0x0000000027ddc SAMPLER_TEXTURE 251 -- hole -- 1 0x0000000027ed7 0x0000000027ed8 CONST_BUFFER 1 -- hole -- 1 0x0000000027ed9 0x0000000027eda CONST_BUFFER 4 -- hole -- 1 0x0000000027ede 0x0000000027edf SAMPLER_TEXTURE 131 -- hole -- 1 0x0000000027f62 0x0000000027f63 CONST_BUFFER 18 -- hole -- 1 0x0000000027f75 0x0000000027f76 CONST_BUFFER 366 -- hole -- 2 0x00000000280e4 0x00000000280e6 SAMPLER_TEXTURE 19189 -- hole -- 1 0x000000002cbdb 0x000000002cbdc CONST_BUFFER 359 -- hole -- 1 0x000000002cd43 0x000000002cd44 CONST_BUFFER 1708 -- hole -- 344 0x000000002d3f0 0x000000002d548 SAMPLER_TEXTURE 344 0x000000002d548 0x000000002d6a0 SAMPLER_TEXTURE 4776 -- hole -- 1 0x000000002e948 0x000000002e949 CONST_BUFFER 7 -- hole -- 4096 0x000000002e950 0x000000002f950 SAMPLER_TEXTURE 2048 -- hole -- 4096 0x0000000030150 0x0000000031150 SAMPLER_TEXTURE 2048 0x0000000031150 0x0000000031950 SAMPLER_TEXTURE 1024 0x0000000031950 0x0000000031d50 SAMPLER_TEXTURE 32184 -- hole -- 6 0x0000000039b08 0x0000000039b0e SAMPLER_TEXTURE 21546 -- hole -- 2 0x000000003ef38 0x000000003ef3a SAMPLER_TEXTURE 2 -- hole -- 6 0x000000003ef3c 0x000000003ef42 SAMPLER_TEXTURE 4 -- hole -- 1 0x000000003ef46 0x000000003ef47 CONST_BUFFER 1 0x000000003ef47 0x000000003ef48 INDEX_BUFFER 1 0x000000003ef48 0x000000003ef49 VERTEX_BUFFER 1 0x000000003ef49 0x000000003ef4a VERTEX_BUFFER 1 -- hole -- 1 0x000000003ef4b 0x000000003ef4c CONST_BUFFER 1 0x000000003ef4c 0x000000003ef4d INDEX_BUFFER 1 0x000000003ef4d 0x000000003ef4e VERTEX_BUFFER 1 0x000000003ef4e 0x000000003ef4f VERTEX_BUFFER 6 -- hole -- 1 0x000000003ef55 0x000000003ef56 CONST_BUFFER 1 -- hole -- 1 0x000000003ef57 0x000000003ef58 CONST_BUFFER 2452 -- hole -- 6 0x000000003f8ec 0x000000003f8f2 SAMPLER_TEXTURE 8634 -- hole -- 1 0x0000000041aac 0x0000000041aad CONST_BUFFER 2 0x0000000041aad 0x0000000041aaf USER_SHADER 5 0x0000000041aaf 0x0000000041ab4 USER_SHADER 1 0x0000000041ab4 0x0000000041ab5 CONST_BUFFER 1 0x0000000041ab5 0x0000000041ab6 CONST_BUFFER 1 0x0000000041ab6 0x0000000041ab7 CONST_BUFFER 29 0x0000000041ab7 0x0000000041ad4 VERTEX_BUFFER 1 0x0000000041ad4 0x0000000041ad5 CONST_BUFFER 2 0x0000000041ad5 0x0000000041ad7 USER_SHADER 4 0x0000000041ad7 0x0000000041adb USER_SHADER 2 0x0000000041adb 0x0000000041add USER_SHADER 1 0x0000000041add 0x0000000041ade USER_SHADER 1 0x0000000041ade 0x0000000041adf USER_SHADER 1 0x0000000041adf 0x0000000041ae0 USER_SHADER 1 0x0000000041ae0 0x0000000041ae1 USER_SHADER 1 0x0000000041ae1 0x0000000041ae2 USER_SHADER 12 -- hole -- 1 0x0000000041aee 0x0000000041aef TRACE 62 -- hole -- 1 0x0000000041b2d 0x0000000041b2e CONST_BUFFER 13990 -- hole -- 3168 0x00000000451d4 0x0000000045e34 SCRATCH_BUFFER 748 0x0000000045e34 0x0000000046120 COLOR_BUFFER 1315 -- hole -- 1 0x0000000046643 0x0000000046644 CONST_BUFFER 233 -- hole -- 1 0x000000004672d 0x000000004672e CONST_BUFFER 349 -- hole -- 256 0x000000004688b 0x000000004698b CONST_BUFFER, DESCRIPTORS, VERTEX_BUFFER 43 -- hole -- 1 0x00000000469b6 0x00000000469b7 CONST_BUFFER 197 -- hole -- 16 0x0000000046a7c 0x0000000046a8c VERTEX_BUFFER 8320 -- hole -- 342 0x0000000048b0c 0x0000000048c62 SAMPLER_TEXTURE 256 0x0000000048c62 0x0000000048d62 DESCRIPTORS 11710 -- hole -- 7 0x000000004bb20 0x000000004bb27 SAMPLER_TEXTURE 2276 -- hole -- 3 0x000000004c40b 0x000000004c40e USER_SHADER 173 -- hole -- 3 0x000000004c4bb 0x000000004c4be USER_SHADER 173 -- hole -- 3 0x000000004c56b 0x000000004c56e USER_SHADER 173 -- hole -- 3 0x000000004c61b 0x000000004c61e USER_SHADER 1721 -- hole -- 16 0x000000004ccd7 0x000000004cce7 VERTEX_BUFFER 26415 -- hole -- 2 0x0000000053416 0x0000000053418 USER_SHADER 38 -- hole -- 1 0x000000005343e 0x000000005343f USER_SHADER 1 0x000000005343f 0x0000000053440 USER_SHADER 38 -- hole -- 2 0x0000000053466 0x0000000053468 USER_SHADER 38 -- hole -- 1 0x000000005348e 0x000000005348f USER_SHADER 1 0x000000005348f 0x0000000053490 USER_SHADER 38 -- hole -- 1 0x00000000534b6 0x00000000534b7 USER_SHADER 1 0x00000000534b7 0x00000000534b8 USER_SHADER 118 -- hole -- 1 0x000000005352e 0x000000005352f CONST_BUFFER 1 0x000000005352f 0x0000000053530 CONST_BUFFER 38 -- hole -- 1 0x0000000053556 0x0000000053557 CONST_BUFFER 79 -- hole -- 1 0x00000000535a6 0x00000000535a7 CONST_BUFFER 360 -- hole -- 1 0x000000005370f 0x0000000053710 SAMPLER_BUFFER 942 -- hole -- 2 0x0000000053abe 0x0000000053ac0 SAMPLER_BUFFER 12 -- hole -- 1 0x0000000053acc 0x0000000053acd SAMPLER_BUFFER 633 -- hole -- 1 0x0000000053d46 0x0000000053d47 CONST_BUFFER 142 -- hole -- 2 0x0000000053dd5 0x0000000053dd7 USER_SHADER 1 0x0000000053dd7 0x0000000053dd8 USER_SHADER 2 0x0000000053dd8 0x0000000053dda USER_SHADER 1 0x0000000053dda 0x0000000053ddb USER_SHADER 3 0x0000000053ddb 0x0000000053dde USER_SHADER 1 -- hole -- 1 0x0000000053ddf 0x0000000053de0 USER_SHADER 6 -- hole -- 1 0x0000000053de6 0x0000000053de7 CONST_BUFFER 129 -- hole -- 1 0x0000000053e68 0x0000000053e69 CONST_BUFFER 1 0x0000000053e69 0x0000000053e6a CONST_BUFFER 1 0x0000000053e6a 0x0000000053e6b CONST_BUFFER 1 0x0000000053e6b 0x0000000053e6c CONST_BUFFER 1 0x0000000053e6c 0x0000000053e6d CONST_BUFFER 1 0x0000000053e6d 0x0000000053e6e CONST_BUFFER 1 0x0000000053e6e 0x0000000053e6f CONST_BUFFER 1 0x0000000053e6f 0x0000000053e70 CONST_BUFFER 2 -- hole -- 1 0x0000000053e72 0x0000000053e73 CONST_BUFFER 220 -- hole -- 1 0x0000000053f4f 0x0000000053f50 SAMPLER_BUFFER Note: The holes represent memory not used by the IB. Other buffers can still be allocated there. ------------------ IB2: Init config begin ------------------ CONTEXT_CONTROL: 0x80000000 0x80000000 SET_CONTEXT_REG: VGT_HOS_MAX_TESS_LEVEL <- 64.0f (0x42800000) VGT_HOS_MIN_TESS_LEVEL <- 0 SET_CONTEXT_REG: VGT_GS_PER_ES <- GS_PER_ES = 128 (0x80) VGT_ES_PER_GS <- ES_PER_GS = 64 (0x40) VGT_GS_PER_VS <- GS_PER_VS = 2 SET_CONTEXT_REG: VGT_PRIMITIVEID_RESET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_DRAW_OPAQUE_OFFSET <- 0 SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_REUSE_OFF <- REUSE_OFF = 0 VGT_VTX_CNT_EN <- VTX_CNT_EN = 0 SET_CONTEXT_REG: PA_SC_CENTROID_PRIORITY_0 <- DISTANCE_0 = 0 DISTANCE_1 = 1 DISTANCE_2 = 2 DISTANCE_3 = 3 DISTANCE_4 = 4 DISTANCE_5 = 5 DISTANCE_6 = 6 DISTANCE_7 = 7 PA_SC_CENTROID_PRIORITY_1 <- DISTANCE_8 = 8 DISTANCE_9 = 9 DISTANCE_10 = 10 (0xa) DISTANCE_11 = 11 (0xb) DISTANCE_12 = 12 (0xc) DISTANCE_13 = 13 (0xd) DISTANCE_14 = 14 (0xe) DISTANCE_15 = 15 (0xf) SET_CONTEXT_REG: PA_SU_PRIM_FILTER_CNTL <- TRIANGLE_FILTER_DISABLE = 0 LINE_FILTER_DISABLE = 0 POINT_FILTER_DISABLE = 0 RECTANGLE_FILTER_DISABLE = 0 TRIANGLE_EXPAND_ENA = 0 LINE_EXPAND_ENA = 0 POINT_EXPAND_ENA = 0 RECTANGLE_EXPAND_ENA = 0 PRIM_EXPAND_CONSTANT = 0 XMAX_RIGHT_EXCLUSION = 0 YMAX_BOTTOM_EXCLUSION = 0 SET_CONTEXT_REG: PA_SC_VPORT_ZMIN_0 <- 0 PA_SC_VPORT_ZMAX_0 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_1 <- 0 PA_SC_VPORT_ZMAX_1 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_2 <- 0 PA_SC_VPORT_ZMAX_2 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_3 <- 0 PA_SC_VPORT_ZMAX_3 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_4 <- 0 PA_SC_VPORT_ZMAX_4 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_5 <- 0 PA_SC_VPORT_ZMAX_5 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_6 <- 0 PA_SC_VPORT_ZMAX_6 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_7 <- 0 PA_SC_VPORT_ZMAX_7 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_8 <- 0 PA_SC_VPORT_ZMAX_8 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_9 <- 0 PA_SC_VPORT_ZMAX_9 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_10 <- 0 PA_SC_VPORT_ZMAX_10 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_11 <- 0 PA_SC_VPORT_ZMAX_11 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_12 <- 0 PA_SC_VPORT_ZMAX_12 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_13 <- 0 PA_SC_VPORT_ZMAX_13 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_14 <- 0 PA_SC_VPORT_ZMAX_14 <- 1.0f (0x3f800000) PA_SC_VPORT_ZMIN_15 <- 0 PA_SC_VPORT_ZMAX_15 <- 1.0f (0x3f800000) PA_SC_RASTER_CONFIG <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2 RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0 RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1 RB_XSEL = 0 RB_YSEL = 0 PKR_MAP = RASTER_CONFIG_PKR_MAP_0 PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0 PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0 PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0 SC_MAP = RASTER_CONFIG_SC_MAP_0 SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE SE_MAP = RASTER_CONFIG_SE_MAP_2 SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE PA_SC_RASTER_CONFIG_1 <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 SET_CONTEXT_REG: PA_SC_GENERIC_SCISSOR_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_GENERIC_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_SCREEN_SCISSOR_TL <- TL_X = 0 TL_Y = 0 PA_SC_SCREEN_SCISSOR_BR <- BR_X = 16384 (0x4000) BR_Y = 16384 (0x4000) SET_CONTEXT_REG: PA_SC_CLIPRECT_RULE <- CLIP_RULE = 0xffff SET_CONTEXT_REG: PA_SC_EDGERULE <- ER_TRI = 10 (0xa) ER_POINT = 10 (0xa) ER_RECT = 10 (0xa) ER_LINE_LR = 42 (0x2a) ER_LINE_RL = 42 (0x2a) ER_LINE_TB = 10 (0xa) ER_LINE_BT = 10 (0xa) PA_SU_HARDWARE_SCREEN_OFFSET <- HW_SCREEN_OFFSET_X = 0 HW_SCREEN_OFFSET_Y = 0 SET_CONTEXT_REG: PA_CL_NANINF_CNTL <- VTE_XY_INF_DISCARD = 0 VTE_Z_INF_DISCARD = 0 VTE_W_INF_DISCARD = 0 VTE_0XNANINF_IS_0 = 0 VTE_XY_NAN_RETAIN = 0 VTE_Z_NAN_RETAIN = 0 VTE_W_NAN_RETAIN = 0 VTE_W_RECIP_NAN_IS_0 = 0 VS_XY_NAN_TO_INF = 0 VS_XY_INF_RETAIN = 0 VS_Z_NAN_TO_INF = 0 VS_Z_INF_RETAIN = 0 VS_W_NAN_TO_INF = 0 VS_W_INF_RETAIN = 0 VS_CLIP_DIST_INF_DISCARD = 0 VTE_NO_OUTPUT_NEG_0 = 0 SET_CONTEXT_REG: PA_CL_GB_VERT_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_VERT_DISC_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_CLIP_ADJ <- 1.0f (0x3f800000) PA_CL_GB_HORZ_DISC_ADJ <- 1.0f (0x3f800000) SET_CONTEXT_REG: DB_SRESULTS_COMPARE_STATE0 <- COMPAREFUNC0 = REF_NEVER COMPAREVALUE0 = 0 COMPAREMASK0 = 0 ENABLE0 = 0 DB_SRESULTS_COMPARE_STATE1 <- COMPAREFUNC1 = REF_NEVER COMPAREVALUE1 = 0 COMPAREMASK1 = 0 ENABLE1 = 0 DB_PRELOAD_CONTROL <- START_X = 0 START_Y = 0 MAX_X = 0 MAX_Y = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE <- FORCE_HIZ_ENABLE = FORCE_OFF FORCE_HIS_ENABLE0 = FORCE_DISABLE FORCE_HIS_ENABLE1 = FORCE_DISABLE FORCE_SHADER_Z_ORDER = 0 FAST_Z_DISABLE = 0 FAST_STENCIL_DISABLE = 0 NOOP_CULL_DISABLE = 0 FORCE_COLOR_KILL = 0 FORCE_Z_READ = 0 FORCE_STENCIL_READ = 0 FORCE_FULL_Z_RANGE = FORCE_OFF FORCE_QC_SMASK_CONFLICT = 0 DISABLE_VIEWPORT_CLAMP = 0 IGNORE_SC_ZRANGE = 0 DISABLE_FULLY_COVERED = 0 FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF MAX_TILES_IN_DTT = 0 DISABLE_TILE_RATE_TILES = 0 FORCE_Z_DIRTY = 0 FORCE_STENCIL_DIRTY = 0 FORCE_Z_VALID = 0 FORCE_STENCIL_VALID = 0 PRESERVE_COMPRESSION = 0 SET_CONTEXT_REG: VGT_MAX_VTX_INDX <- 0xffffffff VGT_MIN_VTX_INDX <- 0 VGT_INDX_OFFSET <- 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_LS <- CU_EN = 0xfffc WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_HS <- WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_ES <- CU_EN = 0xfffe WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_GS <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 GROUP_FIFO_DEPTH = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_VS <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 SPI_SHADER_LATE_ALLOC_VS <- LIMIT = 0 SET_SH_REG: SPI_SHADER_PGM_RSRC3_PS <- CU_EN = 0xffff WAVE_LIMIT = 0 LOCK_LOW_THRESHOLD = 0 SET_CONTEXT_REG: TA_BC_BASE_ADDR <- 0x00008710 TA_BC_BASE_ADDR_HI <- ADDRESS = 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = VGT_FLUSH EVENT_INDEX <- 0 INV_L2 <- 0 ------------------- IB2: Init config end ------------------- ------------------ IB2: Init GS rings begin ------------------ SET_UCONFIG_REG: VGT_ESGS_RING_SIZE <- 7680 (0x00001e00) VGT_GSVS_RING_SIZE <- 6144 (0x00001800) ------------------- IB2: Init GS rings end ------------------- ------------------ IB begin ------------------ WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000001 NOP: Trace point ID: 1 This trace point was reached by the CP. INDIRECT_BUFFER_CIK: 0x052df000 0x00000000 0x00000088 SET_UCONFIG_REG: VGT_ESGS_RING_SIZE <- 7680 (0x00001e00) VGT_GSVS_RING_SIZE <- 6144 (0x00001800) EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 1 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 1 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: VGT_STRMOUT_BUFFER_CONFIG <- STREAM_0_BUFFER_EN = 0 STREAM_1_BUFFER_EN = 0 STREAM_2_BUFFER_EN = 0 STREAM_3_BUFFER_EN = 0 SET_CONTEXT_REG: VGT_STRMOUT_CONFIG <- STREAMOUT_0_EN = 0 STREAMOUT_1_EN = 0 STREAMOUT_2_EN = 0 STREAMOUT_3_EN = 0 RAST_STREAM = 0 RAST_STREAM_MASK = 0 USE_RAST_STREAM_MASK = 0 SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000a6c80 CB_COLOR0_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR0_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000a6c80 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x000a6c80 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_BASE <- 0x000a4c80 CB_COLOR1_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR1_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR1_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR1_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR1_CMASK <- 0x000a4c80 CB_COLOR1_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR1_FMASK <- 0x000a4c80 CB_COLOR1_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_CLEAR_WORD0 <- 0 CB_COLOR1_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR2_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR3_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR4_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR5_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR6_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: CB_COLOR7_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_Z_INFO <- FORMAT = Z_INVALID NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 0 READ_SIZE = 0 TILE_SURFACE_ENABLE = 0 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 0 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 64 (0x040) BR_Y = 64 (0x040) SET_CONTEXT_REG: PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 <- S8_X = 0 S8_Y = 0 S9_X = 0 S9_Y = 0 S10_X = 0 S10_Y = 0 S11_X = 0 S11_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 <- S12_X = 0 S12_Y = 0 S13_X = 0 S13_Y = 0 S14_X = 0 S14_Y = 0 S15_X = 0 S15_Y = 0 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 <- S0_X = 14 (0xe) S0_Y = 11 (0xb) S1_X = 3 S1_Y = 12 (0xc) S2_X = 15 (0xf) S2_Y = 5 S3_X = 10 (0xa) S3_Y = 14 (0xe) PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 <- S4_X = 6 S4_Y = 0 S5_X = 0 S5_Y = 0 S6_X = 11 (0xb) S6_Y = 3 S7_X = 4 S7_Y = 4 SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 1 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: PA_SC_LINE_CNTL <- EXPAND_LINE_WIDTH = 0 LAST_PIXEL = 1 PERPENDICULAR_ENDCAP_ENA = 0 DX10_DIAMOND_TEST_ENA = 0 PA_SC_AA_CONFIG <- MSAA_NUM_SAMPLES = 0 AA_MASK_CENTROID_DTMN = 0 MAX_SAMPLE_DIST = 0 MSAA_EXPOSED_SAMPLES = 0 DETAIL_TO_EXPOSED_MODE = 0 SET_CONTEXT_REG: DB_EQAA <- MAX_ANCHOR_SAMPLES = 0 PS_ITER_SAMPLES = 0 MASK_EXPORT_NUM_SAMPLES = 0 ALPHA_TO_MASK_NUM_SAMPLES = 0 HIGH_QUALITY_INTERSECTIONS = 1 INCOHERENT_EQAA_READS = 0 INTERPOLATE_COMP_Z = 0 INTERPOLATE_SRC_Z = 0 STATIC_ANCHOR_ASSOCIATIONS = 1 ALPHA_TO_MASK_EQAA_DISABLE = 0 OVERRASTERIZATION_AMOUNT = 0 ENABLE_POSTZ_OVERRASTERIZATION = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_1 <- WALK_SIZE = 0 WALK_ALIGNMENT = 0 WALK_ALIGN8_PRIM_FITS_ST = 0 WALK_FENCE_ENABLE = 0 WALK_FENCE_SIZE = 0 SUPERTILE_WALK_ORDER_ENABLE = 0 TILE_WALK_ORDER_ENABLE = 0 TILE_COVER_DISABLE = 0 TILE_COVER_NO_SCISSOR = 0 ZMM_LINE_EXTENT = 0 ZMM_LINE_OFFSET = 0 ZMM_RECT_EXTENT = 0 KILL_PIX_POST_HI_Z = 0 KILL_PIX_POST_DETAIL_MASK = 0 PS_ITER_SAMPLE = 0 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0 MULTI_GPU_SUPERTILE_ENABLE = 0 GPU_ID_OVERRIDE_ENABLE = 0 GPU_ID_OVERRIDE = 0 MULTI_GPU_PRIM_DISCARD_ENABLE = 0 FORCE_EOV_CNTDWN_ENABLE = 1 FORCE_EOV_REZ_ENABLE = 1 OUT_OF_ORDER_PRIMITIVE_ENABLE = 0 OUT_OF_ORDER_WATER_MARK = 0 SET_CONTEXT_REG: PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0xffff AA_MASK_X1Y0 = 0xffff PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0xffff AA_MASK_X1Y1 = 0xffff SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 7 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: CB_BLEND_RED <- 0 CB_BLEND_GREEN <- 0 CB_BLEND_BLUE <- 0 CB_BLEND_ALPHA <- 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 1 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 1 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_CONTEXT_REG: PA_CL_UCP_0_X <- 0 PA_CL_UCP_0_Y <- 0 PA_CL_UCP_0_Z <- 0 PA_CL_UCP_0_W <- 0 PA_CL_UCP_1_X <- 0 PA_CL_UCP_1_Y <- 0 PA_CL_UCP_1_Z <- 0 PA_CL_UCP_1_W <- 0 PA_CL_UCP_2_X <- 0 PA_CL_UCP_2_Y <- 0 PA_CL_UCP_2_Z <- 0 PA_CL_UCP_2_W <- 0 PA_CL_UCP_3_X <- 0 PA_CL_UCP_3_Y <- 0 PA_CL_UCP_3_Z <- 0 PA_CL_UCP_3_W <- 0 PA_CL_UCP_4_X <- 0 PA_CL_UCP_4_Y <- 0 PA_CL_UCP_4_Z <- 0 PA_CL_UCP_4_W <- 0 PA_CL_UCP_5_X <- 0 PA_CL_UCP_5_Y <- 0 PA_CL_UCP_5_Z <- 0 PA_CL_UCP_5_W <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18594.0f (0x46914400) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18582.5f (0x46912d00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_0 <- 18582.5f (0x46912d00) SPI_SHADER_USER_DATA_ES_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_0 <- 18582.5f (0x46912d00) SPI_SHADER_USER_DATA_ES_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_2 <- 18594.0f (0x46914400) SPI_SHADER_USER_DATA_ES_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_6 <- 0x48cac200 SPI_SHADER_USER_DATA_ES_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_4 <- 0x48cac700 SPI_SHADER_USER_DATA_ES_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_0 <- 0x04988d00 SPI_SHADER_USER_DATA_PS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18595.0f (0x46914600) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18587.0f (0x46913600) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18589.5f (0x46913b00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_0 <- 18591.5f (0x46913f00) SPI_SHADER_USER_DATA_GS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18596.0f (0x46914800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_6 <- 0x04989800 SPI_SHADER_USER_DATA_GS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_4 <- 0x04989d00 SPI_SHADER_USER_DATA_GS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_0 <- 0x0498a100 SPI_SHADER_USER_DATA_HS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_2 <- 0x049b0300 SPI_SHADER_USER_DATA_HS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_6 <- 0x0498a200 SPI_SHADER_USER_DATA_HS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_HS_4 <- 0x0498a700 SPI_SHADER_USER_DATA_HS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_8 <- 18597.0f (0x46914a00) SPI_SHADER_USER_DATA_ES_9 <- 0 SET_CONTEXT_REG: PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 64 (0x040) BR_Y = 64 (0x040) SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE <- 0 PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 0 STENCILMASK = 0 STENCILWRITEMASK = 0 STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0 STENCILMASK_BF = 0 STENCILWRITEMASK_BF = 0 STENCILOPVAL_BF = 1 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_ESGS_RING_ITEMSIZE <- ITEMSIZE = 20 (0x014) SET_SH_REG: SPI_SHADER_PGM_LO_ES <- 0x001f05f0 SPI_SHADER_PGM_HI_ES <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_ES <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_ES <- SCRATCH_EN = 0 USER_SGPR = 12 (0xc) TRAP_PRESENT = 0 OC_LDS_EN = 0 EXCP_EN = 0 LDS_SIZE = 0 SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_SCENARIO_G RESERVED_0 = 0 CUT_MODE = GS_CUT_128 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 1 GS_WRITE_OPTIMIZE = 1 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_GSVS_RING_OFFSET_1 <- OFFSET = 48 (0x030) VGT_GSVS_RING_OFFSET_2 <- OFFSET = 48 (0x030) VGT_GSVS_RING_OFFSET_3 <- OFFSET = 48 (0x030) SET_CONTEXT_REG: VGT_GSVS_RING_ITEMSIZE <- ITEMSIZE = 48 (0x030) SET_CONTEXT_REG: VGT_GS_MAX_VERT_OUT <- MAX_VERT_OUT = 3 SET_CONTEXT_REG: VGT_GS_VERT_ITEMSIZE <- ITEMSIZE = 16 (0x010) VGT_GS_VERT_ITEMSIZE_1 <- ITEMSIZE = 0 VGT_GS_VERT_ITEMSIZE_2 <- ITEMSIZE = 0 VGT_GS_VERT_ITEMSIZE_3 <- ITEMSIZE = 0 SET_CONTEXT_REG: VGT_GS_INSTANCE_CNT <- ENABLE = 1 CNT = 1 SET_SH_REG: SPI_SHADER_PGM_LO_GS <- 0x001f0540 SPI_SHADER_PGM_HI_GS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_GS <- VGPRS = 7 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_GS <- SCRATCH_EN = 0 USER_SGPR = 8 TRAP_PRESENT = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 SET_CONTEXT_REG: VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF HS_EN = 0 ES_EN = ES_STAGE_REAL GS_EN = 1 VS_EN = VS_STAGE_COPY_SHADER DYNAMIC_HS = 0 DISPATCH_DRAW_EN = 0 DIS_DEALLOC_ACCUM_0 = 0 DIS_DEALLOC_ACCUM_1 = 0 VS_WAVE_ID_EN = 0 SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 2 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_4COMP POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x001f0550 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 3 SGPRS = 0 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 0 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 4 TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 2 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 15 (0xf) OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x001f0560 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 3 SGPRS = 5 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 SET_CONTEXT_REG: SPI_TMPRING_SIZE <- WAVES = 384 (0x180) WAVESIZE = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRISTRIP IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 63 (0x003f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 SET_CONTEXT_REG: VGT_GS_OUT_PRIM_TYPE <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP OUTPRIM_TYPE_1 = 0 OUTPRIM_TYPE_2 = 0 OUTPRIM_TYPE_3 = 0 UNIQUE_TYPE_PER_STREAM = 0 SET_CONTEXT_REG: VGT_MULTI_PRIM_IB_RESET_EN <- RESET_EN = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 64 (0x00000040) SET_SH_REG: SPI_SHADER_USER_DATA_ES_10 <- 0 SPI_SHADER_USER_DATA_ES_11 <- 0 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 4 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000002 NOP: Trace point ID: 2 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000a2c80 CB_COLOR0_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR0_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000a2c80 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x000a2c80 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_BASE <- 0x000a0c80 CB_COLOR1_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR1_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR1_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR1_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR1_CMASK <- 0x000a0c80 CB_COLOR1_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR1_FMASK <- 0x000a0c80 CB_COLOR1_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_CLEAR_WORD0 <- 0 CB_COLOR1_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 64 (0x040) BR_Y = 64 (0x040) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 15 (0xf) TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 1 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 1 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18599.0f (0x46914e00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_2 <- 18599.0f (0x46914e00) SPI_SHADER_USER_DATA_ES_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18600.0f (0x46915000) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18601.0f (0x46915200) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18603.5f (0x46915700) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18604.5f (0x46915900) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_8 <- 18605.5f (0x46915b00) SPI_SHADER_USER_DATA_ES_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE_1 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_1 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_1 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_1 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_1 <- 0 PA_CL_VPORT_ZOFFSET_1 <- 0 PA_CL_VPORT_XSCALE_2 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_2 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_2 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_2 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_2 <- 0 PA_CL_VPORT_ZOFFSET_2 <- 0 PA_CL_VPORT_XSCALE_3 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_3 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_3 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_3 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_3 <- 0 PA_CL_VPORT_ZOFFSET_3 <- 0 PA_CL_VPORT_XSCALE_4 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_4 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_4 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_4 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_4 <- 0 PA_CL_VPORT_ZOFFSET_4 <- 0 PA_CL_VPORT_XSCALE_5 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_5 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_5 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_5 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_5 <- 0 PA_CL_VPORT_ZOFFSET_5 <- 0 PA_CL_VPORT_XSCALE_6 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_6 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_6 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_6 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_6 <- 0 PA_CL_VPORT_ZOFFSET_6 <- 0 PA_CL_VPORT_XSCALE_7 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_7 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_7 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_7 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_7 <- 0 PA_CL_VPORT_ZOFFSET_7 <- 0 PA_CL_VPORT_XSCALE_8 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_8 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_8 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_8 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_8 <- 0 PA_CL_VPORT_ZOFFSET_8 <- 0 PA_CL_VPORT_XSCALE_9 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_9 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_9 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_9 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_9 <- 0 PA_CL_VPORT_ZOFFSET_9 <- 0 PA_CL_VPORT_XSCALE_10 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_10 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_10 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_10 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_10 <- 0 PA_CL_VPORT_ZOFFSET_10 <- 0 PA_CL_VPORT_XSCALE_11 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_11 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_11 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_11 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_11 <- 0 PA_CL_VPORT_ZOFFSET_11 <- 0 PA_CL_VPORT_XSCALE_12 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_12 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_12 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_12 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_12 <- 0 PA_CL_VPORT_ZOFFSET_12 <- 0 PA_CL_VPORT_XSCALE_13 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_13 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_13 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_13 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_13 <- 0 PA_CL_VPORT_ZOFFSET_13 <- 0 PA_CL_VPORT_XSCALE_14 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_14 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_14 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_14 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_14 <- 0 PA_CL_VPORT_ZOFFSET_14 <- 0 PA_CL_VPORT_XSCALE_15 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_15 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_15 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_15 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_15 <- 0 PA_CL_VPORT_ZOFFSET_15 <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: VGT_ESGS_RING_ITEMSIZE <- ITEMSIZE = 20 (0x014) SET_SH_REG: SPI_SHADER_PGM_LO_ES <- 0x00051880 SPI_SHADER_PGM_HI_ES <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_ES <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_ES <- SCRATCH_EN = 0 USER_SGPR = 12 (0xc) TRAP_PRESENT = 0 OC_LDS_EN = 0 EXCP_EN = 0 LDS_SIZE = 0 SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_SCENARIO_G RESERVED_0 = 0 CUT_MODE = GS_CUT_128 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 1 GS_WRITE_OPTIMIZE = 1 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_GSVS_RING_OFFSET_1 <- OFFSET = 48 (0x030) VGT_GSVS_RING_OFFSET_2 <- OFFSET = 48 (0x030) VGT_GSVS_RING_OFFSET_3 <- OFFSET = 48 (0x030) SET_CONTEXT_REG: VGT_GSVS_RING_ITEMSIZE <- ITEMSIZE = 48 (0x030) SET_CONTEXT_REG: VGT_GS_MAX_VERT_OUT <- MAX_VERT_OUT = 3 SET_CONTEXT_REG: VGT_GS_VERT_ITEMSIZE <- ITEMSIZE = 16 (0x010) VGT_GS_VERT_ITEMSIZE_1 <- ITEMSIZE = 0 VGT_GS_VERT_ITEMSIZE_2 <- ITEMSIZE = 0 VGT_GS_VERT_ITEMSIZE_3 <- ITEMSIZE = 0 SET_CONTEXT_REG: VGT_GS_INSTANCE_CNT <- ENABLE = 1 CNT = 1 SET_SH_REG: SPI_SHADER_PGM_LO_GS <- 0x00051890 SPI_SHADER_PGM_HI_GS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_GS <- VGPRS = 7 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_GS <- SCRATCH_EN = 0 USER_SGPR = 8 TRAP_PRESENT = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 2 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_4COMP POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x000518a0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 3 SGPRS = 0 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 0 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 4 TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 2 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 15 (0xf) OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00008810 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 16 (0x10) SGPRS = 3 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 64 (0x00000040) DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 4 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000003 NOP: Trace point ID: 3 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000aac80 CB_COLOR0_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR0_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000aac80 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x000aac80 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_BASE <- 0x000a8c80 CB_COLOR1_PITCH <- TILE_MAX = 7 FMASK_TILE_MAX = 7 CB_COLOR1_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_VIEW <- SLICE_START = 0 SLICE_MAX = 63 (0x3f) CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR1_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR1_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR1_CMASK <- 0x000a8c80 CB_COLOR1_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR1_FMASK <- 0x000a8c80 CB_COLOR1_FMASK_SLICE <- TILE_MAX = 63 (0x0003f) CB_COLOR1_CLEAR_WORD0 <- 0 CB_COLOR1_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 64 (0x040) BR_Y = 64 (0x040) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 15 (0xf) TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18607.5f (0x46915f00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_ES_2 <- 18607.5f (0x46915f00) SPI_SHADER_USER_DATA_ES_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18608.5f (0x46916100) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18609.5f (0x46916300) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18612.0f (0x46916800) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18613.0f (0x46916a00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE_1 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_1 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_1 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_1 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_1 <- 0 PA_CL_VPORT_ZOFFSET_1 <- 0 PA_CL_VPORT_XSCALE_2 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_2 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_2 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_2 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_2 <- 0 PA_CL_VPORT_ZOFFSET_2 <- 0 PA_CL_VPORT_XSCALE_3 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_3 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_3 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_3 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_3 <- 0 PA_CL_VPORT_ZOFFSET_3 <- 0 PA_CL_VPORT_XSCALE_4 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_4 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_4 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_4 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_4 <- 0 PA_CL_VPORT_ZOFFSET_4 <- 0 PA_CL_VPORT_XSCALE_5 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_5 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_5 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_5 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_5 <- 0 PA_CL_VPORT_ZOFFSET_5 <- 0 PA_CL_VPORT_XSCALE_6 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_6 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_6 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_6 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_6 <- 0 PA_CL_VPORT_ZOFFSET_6 <- 0 PA_CL_VPORT_XSCALE_7 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_7 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_7 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_7 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_7 <- 0 PA_CL_VPORT_ZOFFSET_7 <- 0 PA_CL_VPORT_XSCALE_8 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_8 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_8 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_8 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_8 <- 0 PA_CL_VPORT_ZOFFSET_8 <- 0 PA_CL_VPORT_XSCALE_9 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_9 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_9 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_9 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_9 <- 0 PA_CL_VPORT_ZOFFSET_9 <- 0 PA_CL_VPORT_XSCALE_10 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_10 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_10 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_10 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_10 <- 0 PA_CL_VPORT_ZOFFSET_10 <- 0 PA_CL_VPORT_XSCALE_11 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_11 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_11 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_11 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_11 <- 0 PA_CL_VPORT_ZOFFSET_11 <- 0 PA_CL_VPORT_XSCALE_12 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_12 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_12 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_12 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_12 <- 0 PA_CL_VPORT_ZOFFSET_12 <- 0 PA_CL_VPORT_XSCALE_13 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_13 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_13 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_13 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_13 <- 0 PA_CL_VPORT_ZOFFSET_13 <- 0 PA_CL_VPORT_XSCALE_14 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_14 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_14 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_14 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_14 <- 0 PA_CL_VPORT_ZOFFSET_14 <- 0 PA_CL_VPORT_XSCALE_15 <- 32.0f (0x42000000) PA_CL_VPORT_XOFFSET_15 <- 32.0f (0x42000000) PA_CL_VPORT_YSCALE_15 <- 32.0f (0x42000000) PA_CL_VPORT_YOFFSET_15 <- 32.0f (0x42000000) PA_CL_VPORT_ZSCALE_15 <- 0 PA_CL_VPORT_ZOFFSET_15 <- 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 64 (0x00000040) DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 4 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000004 NOP: Trace point ID: 4 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 7 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18582.5f (0x46912d00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18615.0f (0x46916e00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 0x48cac200 SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 0x48cac700 SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18616.0f (0x46917000) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18617.0f (0x46917200) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18619.5f (0x46917700) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18620.5f (0x46917900) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18621.5f (0x46917b00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ONE ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: VGT_SHADER_STAGES_EN <- LS_EN = LS_STAGE_OFF HS_EN = 0 ES_EN = ES_STAGE_OFF GS_EN = 0 VS_EN = VS_STAGE_REAL DYNAMIC_HS = 0 DISPATCH_DRAW_EN = 0 DIS_DEALLOC_ACCUM_0 = 0 DIS_DEALLOC_ACCUM_1 = 0 VS_WAVE_ID_EN = 0 SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x000518d0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x000518e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 10 (0xa) PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 SET_SH_REG: SPI_SHADER_USER_DATA_VS_10 <- 0 SPI_SHADER_USER_DATA_VS_11 <- 0 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 9 VGT_DMA_BASE <- 0x00b03000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000005 NOP: Trace point ID: 5 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) DMA_DATA: DMA_DATA_WORD0 <- CP_SYNC = 1 SRC_SEL = DATA DSL_SEL = DST_ADDR ENGINE = ME SRC_ADDR_LO <- 0 SRC_ADDR_HI <- 0 DST_ADDR_LO <- 0x0d0bc000 DST_ADDR_HI <- 0 COMMAND <- BYTE_COUNT = 8192 (0x02000) DISABLE_WR_CONFIRM = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 1 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18625.0f (0x46918200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18624.0f (0x46918000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18625.5f (0x46918300) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18626.5f (0x46918500) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18629.0f (0x46918a00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18630.0f (0x46918c00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18631.0f (0x46918e00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000006 NOP: Trace point ID: 6 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_Z_INFO <- FORMAT = Z_INVALID NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 0 READ_SIZE = 0 TILE_SURFACE_ENABLE = 0 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 0 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0xffff AA_MASK_X1Y0 = 0xffff PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0xffff AA_MASK_X1Y1 = 0xffff SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18632.0f (0x46919000) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18632.5f (0x46919100) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_ELIMINATE_FAST_CLEAR ROP3 = X_0XCC SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x000518c0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000007 NOP: Trace point ID: 7 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18633.0f (0x46919200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18633.5f (0x46919300) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x000d0bf0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x000518f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 7 SGPRS = 7 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 3 VGT_DMA_BASE <- 0x00b0300c VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000008 NOP: Trace point ID: 8 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_Z_INFO <- FORMAT = Z_INVALID NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 0 READ_SIZE = 0 TILE_SURFACE_ENABLE = 0 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_INVALID TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 0 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: PA_SC_AA_MASK_X0Y0_X1Y0 <- AA_MASK_X0Y0 = 0xffff AA_MASK_X1Y0 = 0xffff PA_SC_AA_MASK_X0Y1_X1Y1 <- AA_MASK_X0Y1 = 0xffff AA_MASK_X1Y1 = 0xffff SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18636.5f (0x46919900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18635.5f (0x46919700) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18637.0f (0x46919a00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18638.0f (0x46919c00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18640.5f (0x4691a100) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18641.5f (0x4691a300) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18642.5f (0x4691a500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_ELIMINATE_FAST_CLEAR ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x000518c0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000009 NOP: Trace point ID: 9 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18643.0f (0x4691a600) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18643.5f (0x4691a700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ONE ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x001f04e0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x001f04f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 7 SGPRS = 5 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 9 VGT_DMA_BASE <- 0x00b03000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000a NOP: Trace point ID: 10 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18646.5f (0x4691ad00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18645.5f (0x4691ab00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18647.0f (0x4691ae00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18648.0f (0x4691b000) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18650.5f (0x4691b500) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18651.5f (0x4691b700) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18652.5f (0x4691b900) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000b NOP: Trace point ID: 11 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 7 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18653.0f (0x4691ba00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18653.5f (0x4691bb00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ONE ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 1 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x001f01c0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 2 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x001f01d0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 21 (0x15) SGPRS = 6 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x0005e280 VGT_DMA_BASE <- 0x0566cb00 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000c NOP: Trace point ID: 12 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000bc3c0 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000bc3c0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x000bc3c0 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18655.0f (0x4691be00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18656.0f (0x4691c000) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18657.0f (0x4691c200) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18659.5f (0x4691c700) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18660.5f (0x4691c900) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18661.5f (0x4691cb00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE_1 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_1 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_1 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_1 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_1 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_1 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_2 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_2 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_2 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_2 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_2 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_2 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_3 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_3 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_3 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_3 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_3 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_3 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_4 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_4 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_4 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_4 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_4 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_4 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_5 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_5 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_5 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_5 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_5 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_5 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_6 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_6 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_6 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_6 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_6 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_6 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_7 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_7 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_7 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_7 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_7 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_7 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_8 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_8 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_8 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_8 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_8 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_8 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_9 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_9 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_9 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_9 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_9 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_9 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_10 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_10 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_10 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_10 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_10 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_10 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_11 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_11 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_11 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_11 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_11 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_11 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_12 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_12 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_12 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_12 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_12 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_12 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_13 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_13 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_13 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_13 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_13 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_13 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_14 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_14 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_14 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_14 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_14 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_14 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_15 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_15 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_15 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_15 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_15 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_15 <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x001ed9e0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 1 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x001ed9f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 3 VGT_DMA_BASE <- 0x00b0300c VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000d NOP: Trace point ID: 13 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18665.0f (0x4691d200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18664.0f (0x4691d000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18665.5f (0x4691d300) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18668.0f (0x4691d800) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18669.0f (0x4691da00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18670.0f (0x4691dc00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18672.5f (0x4691e100) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18673.5f (0x4691e300) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18674.5f (0x4691e500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000e NOP: Trace point ID: 14 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18675.0f (0x4691e600) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18675.5f (0x4691e700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_5 <- OFFSET = 5 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 1 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 5 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041aad0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 27 (0x1b) SGPRS = 9 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 6 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041aaf0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 41 (0x29) SGPRS = 12 (0xc) PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 1 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 1 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00029fac VGT_DMA_BASE <- 0x20ce3000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 0x00029fac VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000000f NOP: Trace point ID: 15 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000bc3c0 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000bc3c0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x000bc3c0 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18677.0f (0x4691ea00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18678.0f (0x4691ec00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18679.0f (0x4691ee00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18681.5f (0x4691f300) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18682.5f (0x4691f500) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18683.5f (0x4691f700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE_1 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_1 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_1 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_1 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_1 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_1 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_2 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_2 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_2 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_2 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_2 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_2 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_3 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_3 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_3 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_3 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_3 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_3 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_4 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_4 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_4 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_4 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_4 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_4 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_5 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_5 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_5 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_5 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_5 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_5 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_6 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_6 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_6 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_6 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_6 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_6 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_7 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_7 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_7 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_7 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_7 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_7 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_8 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_8 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_8 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_8 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_8 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_8 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_9 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_9 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_9 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_9 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_9 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_9 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_10 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_10 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_10 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_10 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_10 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_10 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_11 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_11 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_11 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_11 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_11 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_11 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_12 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_12 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_12 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_12 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_12 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_12 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_13 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_13 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_13 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_13 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_13 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_13 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_14 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_14 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_14 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_14 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_14 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_14 <- 0.5f (0x3f000000) PA_CL_VPORT_XSCALE_15 <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET_15 <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE_15 <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET_15 <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE_15 <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET_15 <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x001ed9e0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 1 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x001ed9f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 3 VGT_DMA_BASE <- 0x00b0300c VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000010 NOP: Trace point ID: 16 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18687.0f (0x4691fe00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18686.0f (0x4691fc00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18687.5f (0x4691ff00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18688.5f (0x46920100) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18689.5f (0x46920300) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18692.0f (0x46920800) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18693.0f (0x46920a00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18694.0f (0x46920c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000011 NOP: Trace point ID: 17 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000fc480 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000edf10 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000fc480 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18694.5f (0x46920d00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18695.0f (0x46920e00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_5 <- OFFSET = 5 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 5 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041ad50 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 27 (0x1b) SGPRS = 9 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 6 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041ad70 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 41 (0x29) SGPRS = 12 (0xc) PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 1 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 1 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00029fac VGT_DMA_BASE <- 0x20ce3000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 0x00029fac VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000012 NOP: Trace point ID: 18 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) DMA_DATA: DMA_DATA_WORD0 <- CP_SYNC = 1 SRC_SEL = DATA DSL_SEL = DST_ADDR ENGINE = ME SRC_ADDR_LO <- 0 SRC_ADDR_HI <- 0 DST_ADDR_LO <- 0x0d0bc000 DST_ADDR_HI <- 0 COMMAND <- BYTE_COUNT = 8192 (0x02000) DISABLE_WR_CONFIRM = 0 SRC_SWAP = NONE DST_SWAP = NONE SAS = MEMORY DAS = MEMORY SAIC = INCREMENT DAIC = INCREMENT RAW_WAIT = 1 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18700.0f (0x46921800) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18699.0f (0x46921600) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18700.5f (0x46921900) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18701.5f (0x46921b00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18702.5f (0x46921d00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18705.0f (0x46922200) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18706.0f (0x46922400) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18707.0f (0x46922600) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000013 NOP: Trace point ID: 19 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18707.5f (0x46922700) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18708.0f (0x46922800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c61b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00534b60 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 27 (0x0000001b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000014 NOP: Trace point ID: 20 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18711.5f (0x46922f00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18710.5f (0x46922d00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18712.0f (0x46923000) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18713.0f (0x46923200) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18714.0f (0x46923400) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18715.0f (0x46923600) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18716.0f (0x46923800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000015 NOP: Trace point ID: 21 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18716.5f (0x46923900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18717.0f (0x46923a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c56b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00534b70 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 27 (0x0000001b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000016 NOP: Trace point ID: 22 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18720.5f (0x46924100) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18719.5f (0x46923f00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18721.0f (0x46924200) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18722.0f (0x46924400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18723.0f (0x46924600) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18724.0f (0x46924800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18725.0f (0x46924a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000017 NOP: Trace point ID: 23 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18725.5f (0x46924b00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18726.0f (0x46924c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c61b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00534b60 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 27 (0x0000001b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000018 NOP: Trace point ID: 24 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18729.5f (0x46925300) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18728.5f (0x46925100) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18730.0f (0x46925400) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18731.0f (0x46925600) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18732.0f (0x46925800) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18733.0f (0x46925a00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18734.0f (0x46925c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000019 NOP: Trace point ID: 25 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18734.5f (0x46925d00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18735.0f (0x46925e00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c56b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00534b70 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 27 (0x0000001b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001a NOP: Trace point ID: 26 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18738.5f (0x46926500) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18737.5f (0x46926300) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18739.0f (0x46926600) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18740.0f (0x46926800) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18741.0f (0x46926a00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18743.5f (0x46926f00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18744.5f (0x46927100) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18745.5f (0x46927300) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001b NOP: Trace point ID: 27 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18746.0f (0x46927400) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18746.5f (0x46927500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c4bb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001c NOP: Trace point ID: 28 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18750.0f (0x46927c00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18749.0f (0x46927a00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18750.5f (0x46927d00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18751.5f (0x46927f00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18752.5f (0x46928100) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001d NOP: Trace point ID: 29 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18753.0f (0x46928200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18753.5f (0x46928300) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c4bb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 11 (0x0000000b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001e NOP: Trace point ID: 30 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18757.0f (0x46928a00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18756.0f (0x46928800) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18757.5f (0x46928b00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18758.5f (0x46928d00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18759.5f (0x46928f00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000001f NOP: Trace point ID: 31 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18760.0f (0x46929000) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18760.5f (0x46929100) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c4bb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 9 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000020 NOP: Trace point ID: 32 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18764.0f (0x46929800) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18763.0f (0x46929600) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18764.5f (0x46929900) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18765.5f (0x46929b00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18766.5f (0x46929d00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000021 NOP: Trace point ID: 33 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18767.0f (0x46929e00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18767.5f (0x46929f00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c4bb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 11 (0x0000000b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000022 NOP: Trace point ID: 34 This trace point was reached by the CP. SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18769.5f (0x4692a300) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18770.5f (0x4692a500) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18773.0f (0x4692aa00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18774.0f (0x4692ac00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18775.0f (0x4692ae00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18777.5f (0x4692b300) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18778.5f (0x4692b500) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18779.5f (0x4692b700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 1 STENCILMASK = 255 (0xff) STENCILWRITEMASK = 255 (0xff) STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 1 STENCILMASK_BF = 255 (0xff) STENCILWRITEMASK_BF = 255 (0xff) STENCILOPVAL_BF = 1 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 1 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_ALWAYS STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_REPLACE_TEST STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c40b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 9 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 6 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 96 (0x00000060) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000023 NOP: Trace point ID: 35 This trace point was reached by the CP. SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18781.5f (0x4692bb00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18782.5f (0x4692bd00) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18785.0f (0x4692c200) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18786.0f (0x4692c400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18787.0f (0x4692c600) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18788.0f (0x4692c800) SPI_SHADER_USER_DATA_GS_3 <- 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 96 (0x00000060) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000024 NOP: Trace point ID: 36 This trace point was reached by the CP. SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18790.5f (0x4692cd00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18791.5f (0x4692cf00) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18794.0f (0x4692d400) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18795.0f (0x4692d600) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18796.0f (0x4692d800) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18797.0f (0x4692da00) SPI_SHADER_USER_DATA_GS_3 <- 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 27 (0x0000001b) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 96 (0x00000060) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000025 NOP: Trace point ID: 37 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18801.0f (0x4692e200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18800.0f (0x4692e000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18801.5f (0x4692e300) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18804.0f (0x4692e800) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18805.0f (0x4692ea00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18806.0f (0x4692ec00) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18808.5f (0x4692f100) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18809.5f (0x4692f300) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18810.5f (0x4692f500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 0 STENCILMASK = 0 STENCILWRITEMASK = 0 STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0 STENCILMASK_BF = 0 STENCILWRITEMASK_BF = 0 STENCILOPVAL_BF = 1 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000026 NOP: Trace point ID: 38 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18811.0f (0x4692f600) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18811.5f (0x4692f700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534660 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000027 NOP: Trace point ID: 39 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18815.0f (0x4692fe00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18814.0f (0x4692fc00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18815.5f (0x4692ff00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18816.5f (0x46930100) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18817.5f (0x46930300) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000028 NOP: Trace point ID: 40 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18818.0f (0x46930400) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18818.5f (0x46930500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534660 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000029 NOP: Trace point ID: 41 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18822.0f (0x46930c00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18821.0f (0x46930a00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18822.5f (0x46930d00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18823.5f (0x46930f00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18824.5f (0x46931100) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18825.5f (0x46931300) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18826.5f (0x46931500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002a NOP: Trace point ID: 42 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18827.0f (0x46931600) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18827.5f (0x46931700) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534160 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 2 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002b NOP: Trace point ID: 43 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18831.0f (0x46931e00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18830.0f (0x46931c00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18831.5f (0x46931f00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18832.5f (0x46932100) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18833.5f (0x46932300) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002c NOP: Trace point ID: 44 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18834.0f (0x46932400) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18834.5f (0x46932500) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534160 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002d NOP: Trace point ID: 45 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18838.0f (0x46932c00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18837.0f (0x46932a00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18838.5f (0x46932d00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18839.5f (0x46932f00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18840.5f (0x46933100) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18843.0f (0x46933600) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18844.0f (0x46933800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18845.0f (0x46933a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002e NOP: Trace point ID: 46 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18845.5f (0x46933b00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18846.0f (0x46933c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0053dd50 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0053dd70 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 2 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000002f NOP: Trace point ID: 47 This trace point was reached by the CP. SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18848.0f (0x46934000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18849.0f (0x46934200) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18850.0f (0x46934400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18851.0f (0x46934600) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18853.5f (0x46934b00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18854.5f (0x46934d00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18855.5f (0x46934f00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0053dd80 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0053dda0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 6 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 4194 (0x00001062) VGT_DMA_BASE <- 0x15ee3000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 4194 (0x00001062) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000030 NOP: Trace point ID: 48 This trace point was reached by the CP. SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18857.5f (0x46935300) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18858.5f (0x46935500) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18861.0f (0x46935a00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18862.0f (0x46935c00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18863.0f (0x46935e00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18864.0f (0x46936000) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18865.0f (0x46936200) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 1 STENCILMASK = 255 (0xff) STENCILWRITEMASK = 255 (0xff) STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 1 STENCILMASK_BF = 255 (0xff) STENCILWRITEMASK_BF = 255 (0xff) STENCILOPVAL_BF = 1 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 1 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_ALWAYS STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_REPLACE_TEST STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x004c40b0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 26 (0x1a) SGPRS = 9 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005348f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 2 SGPRS = 2 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 100 (0x00000064) DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 96 (0x00000060) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000031 NOP: Trace point ID: 49 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18868.5f (0x46936900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18867.5f (0x46936700) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_6 <- 18869.0f (0x46936a00) SPI_SHADER_USER_DATA_VS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18871.5f (0x46936f00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18872.5f (0x46937100) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18873.5f (0x46937300) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18876.0f (0x46937800) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18877.0f (0x46937a00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18878.0f (0x46937c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: DB_STENCILREFMASK <- STENCILTESTVAL = 0 STENCILMASK = 0 STENCILWRITEMASK = 0 STENCILOPVAL = 1 DB_STENCILREFMASK_BF <- STENCILTESTVAL_BF = 0 STENCILMASK_BF = 0 STENCILWRITEMASK_BF = 0 STENCILOPVAL_BF = 1 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000032 NOP: Trace point ID: 50 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18878.5f (0x46937d00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18879.0f (0x46937e00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534660 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 7 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000033 NOP: Trace point ID: 51 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18882.5f (0x46938500) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18881.5f (0x46938300) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18883.0f (0x46938600) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18884.0f (0x46938800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18885.0f (0x46938a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000034 NOP: Trace point ID: 52 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18885.5f (0x46938b00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18886.0f (0x46938c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534660 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000035 NOP: Trace point ID: 53 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18889.5f (0x46939300) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18888.5f (0x46939100) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18890.0f (0x46939400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18891.0f (0x46939600) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18892.0f (0x46939800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000036 NOP: Trace point ID: 54 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18892.5f (0x46939900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18893.0f (0x46939a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534660 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343e0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 5 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000037 NOP: Trace point ID: 55 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18896.5f (0x4693a100) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18895.5f (0x46939f00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18897.0f (0x4693a200) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18898.0f (0x4693a400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18899.0f (0x4693a600) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18900.0f (0x4693a800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18901.0f (0x4693aa00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000038 NOP: Trace point ID: 56 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18901.5f (0x4693ab00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18902.0f (0x4693ac00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534160 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000039 NOP: Trace point ID: 57 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18905.5f (0x4693b300) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18904.5f (0x4693b100) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18906.0f (0x4693b400) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18907.0f (0x4693b600) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18908.0f (0x4693b800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003a NOP: Trace point ID: 58 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18908.5f (0x4693b900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18909.0f (0x4693ba00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534160 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 7 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003b NOP: Trace point ID: 59 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18912.5f (0x4693c100) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18911.5f (0x4693bf00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18913.0f (0x4693c200) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18914.0f (0x4693c400) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18915.0f (0x4693c600) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003c NOP: Trace point ID: 60 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18915.5f (0x4693c700) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18916.0f (0x4693c800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x00534160 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 24 (0x18) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x005343f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 4 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 2 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 432 (0x000001b0) VGT_DMA_BASE <- 0x1267d000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 432 (0x000001b0) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003d NOP: Trace point ID: 61 This trace point was reached by the CP. SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18918.0f (0x4693cc00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18919.0f (0x4693ce00) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18920.0f (0x4693d000) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18921.0f (0x4693d200) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18923.5f (0x4693d700) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18924.5f (0x4693d900) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18925.5f (0x4693db00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 3 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0053ddb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 25 (0x19) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 3 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 4 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0053ddf0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 11 (0xb) SGPRS = 12 (0xc) PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 1 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 3 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00018000 VGT_DMA_BASE <- 0x00a60000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 6 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003e NOP: Trace point ID: 62 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18929.0f (0x4693e200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18928.0f (0x4693e000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_4 <- 18929.5f (0x4693e300) SPI_SHADER_USER_DATA_VS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18930.5f (0x4693e500) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18931.5f (0x4693e700) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18934.0f (0x4693ec00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18935.0f (0x4693ee00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18936.0f (0x4693f000) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000003f NOP: Trace point ID: 63 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18936.5f (0x4693f100) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18937.0f (0x4693f200) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 2 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041adb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 23 (0x17) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 3 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041add0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 6 SGPRS = 6 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 252 (0x000000fc) VGT_DMA_BASE <- 0x3ef4c000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 252 (0x000000fc) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000040 NOP: Trace point ID: 64 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18940.5f (0x4693f900) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18939.5f (0x4693f700) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18941.0f (0x4693fa00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18942.0f (0x4693fc00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18943.0f (0x4693fe00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000041 NOP: Trace point ID: 65 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x000f0980 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x000d0bc0 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 59 (0x03b) CB_COLOR0_FMASK <- 0x000f0980 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0x3c000000 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_16_16_16_16 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_FLOAT COMP_SWAP = SWAP_STD FAST_CLEAR = 1 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18943.5f (0x4693ff00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18944.0f (0x46940000) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_SRC_ALPHA COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA SEPARATE_ALPHA_BLEND = 1 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 2 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041adb0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 23 (0x17) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 3 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041add0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 6 SGPRS = 6 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 528 (0x00000210) VGT_DMA_BASE <- 0x3ef47000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 528 (0x00000210) VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000042 NOP: Trace point ID: 66 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18945.5f (0x46940300) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18946.0f (0x46940400) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18947.0f (0x46940600) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 1076 (0x434) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000043 NOP: Trace point ID: 67 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x0045e340 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x0045e340 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x0045e340 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18947.5f (0x46940700) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18948.0f (0x46940800) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 540.0f (0x44070000) PA_CL_VPORT_XOFFSET <- 540.0f (0x44070000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 1 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x000513f0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 1 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x000511f0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRIFAN IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 4 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000044 NOP: Trace point ID: 68 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18951.0f (0x46940e00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18950.0f (0x46940c00) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18951.5f (0x46940f00) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18952.5f (0x46941100) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18955.0f (0x46941600) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18956.0f (0x46941800) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18957.0f (0x46941a00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_SC_VPORT_SCISSOR_0_TL <- TL_X = 0 TL_Y = 0 WINDOW_OFFSET_DISABLE = 1 PA_SC_VPORT_SCISSOR_0_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000045 NOP: Trace point ID: 69 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x0045e340 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x0045e340 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x0045e340 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 1 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18957.5f (0x46941b00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18958.0f (0x46941c00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 1 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041ade0 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 9 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041adf0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 15 (0xf) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 1 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00029fac VGT_DMA_BASE <- 0x20ce3000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 0x00029fac VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000046 NOP: Trace point ID: 70 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18961.0f (0x46942200) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18960.0f (0x46942000) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18961.5f (0x46942300) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18962.5f (0x46942500) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18965.0f (0x46942a00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18966.0f (0x46942c00) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18967.0f (0x46942e00) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000047 NOP: Trace point ID: 71 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_BASE <- 0x0045e340 CB_COLOR0_PITCH <- TILE_MAX = 135 (0x87) FMASK_TILE_MAX = 135 (0x87) CB_COLOR0_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_VIEW <- SLICE_START = 0 SLICE_MAX = 0 CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 CB_COLOR0_ATTRIB <- TILE_MODE_INDEX = 14 (0xe) FMASK_TILE_MODE_INDEX = 14 (0xe) FMASK_BANK_HEIGHT = 0 NUM_SAMPLES = 0 NUM_FRAGMENTS = 0 FORCE_DST_ALPHA_1 = 0 CB_COLOR0_DCC_CONTROL <- OVERWRITE_COMBINER_DISABLE = 0 KEY_CLEAR_ENABLE = 0 MAX_UNCOMPRESSED_BLOCK_SIZE = 0 MIN_COMPRESSED_BLOCK_SIZE = 0 MAX_COMPRESSED_BLOCK_SIZE = 0 COLOR_TRANSFORM = 0 INDEPENDENT_64B_BLOCKS = 0 LOSSY_RGB_PRECISION = 0 LOSSY_ALPHA_PRECISION = 0 CB_COLOR0_CMASK <- 0x0045e340 CB_COLOR0_CMASK_SLICE <- TILE_MAX = 0 CB_COLOR0_FMASK <- 0x0045e340 CB_COLOR0_FMASK_SLICE <- TILE_MAX = 11967 (0x02ebf) CB_COLOR0_CLEAR_WORD0 <- 0 CB_COLOR0_CLEAR_WORD1 <- 0 SET_CONTEXT_REG: CB_COLOR1_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_8_8_8_8 LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_ALT FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 1 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 0 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 1 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 15 (0xf) TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18967.5f (0x46942f00) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18968.0f (0x46943000) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 538.0f (0x44068000) PA_CL_VPORT_XOFFSET <- 538.0f (0x44068000) PA_CL_VPORT_YSCALE <- 336.0f (0x43a80000) PA_CL_VPORT_YOFFSET <- 336.0f (0x43a80000) PA_CL_VPORT_ZSCALE <- 0.5f (0x3f000000) PA_CL_VPORT_ZOFFSET <- 0.5f (0x3f000000) SET_CONTEXT_REG: SPI_PS_INPUT_CNTL_0 <- OFFSET = 0 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_1 <- OFFSET = 1 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_2 <- OFFSET = 2 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_3 <- OFFSET = 3 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SPI_PS_INPUT_CNTL_4 <- OFFSET = 4 DEFAULT_VAL = X_0_0F FLAT_SHADE = 0 CYL_WRAP = 0 PT_SPRITE_TEX = 0 DUP = 0 FP16_INTERP_MODE = 0 USE_DEFAULT_ATTR1 = 0 DEFAULT_VAL_ATTR1 = 0 PT_SPRITE_TEX_ATTR1 = 0 ATTR0_VALID = 0 ATTR1_VALID = 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 0 PERSP_CENTER_ENA = 1 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ONE COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ONE ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 1 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_NORMAL ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 1 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 8 WIDTH = 8 PA_SU_POINT_MINMAX <- MIN_SIZE = 8 MAX_SIZE = 8 PA_SU_LINE_CNTL <- WIDTH = 8 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 1 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 1 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_GEQUAL BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 4 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0041ae00 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 9 SGPRS = 4 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 5 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 15 (0xf) OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x0041ae10 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 15 (0xf) SGPRS = 8 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 1 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_TRILIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 INDEX_TYPE: VGT_DMA_INDEX_TYPE <- INDEX_TYPE = VGT_INDEX_16 SWAP_MODE = VGT_DMA_SWAP_NONE BUF_TYPE = VGT_DMA_BUF_MEM RDREQ_POLICY = VGT_POLICY_LRU RDREQ_POLICY_VI = 0 ATC = 0 NOT_EOP = 0 REQ_PATH = 0 MTYPE = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_2: VGT_DMA_MAX_SIZE <- 0x00029fac VGT_DMA_BASE <- 0x20ce3000 VGT_DMA_BASE_HI <- BASE_ADDR = 0 VGT_NUM_INDICES <- 0x00029fac VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_DMA MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000048 NOP: Trace point ID: 72 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) SET_CONTEXT_REG: CB_COLOR0_INFO <- ENDIAN = ENDIAN_NONE FORMAT = COLOR_INVALID LINEAR_GENERAL = 0 NUMBER_TYPE = NUMBER_UNORM COMP_SWAP = SWAP_STD FAST_CLEAR = 0 COMPRESSION = 0 BLEND_CLAMP = 0 BLEND_BYPASS = 0 SIMPLE_FLOAT = 0 ROUND_MODE = 0 CMASK_IS_LINEAR = 0 BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO FMASK_COMPRESSION_DISABLE = 0 FMASK_COMPRESS_1FRAG_ONLY = 0 DCC_ENABLE = 0 CMASK_ADDR_TYPE = 0 SET_CONTEXT_REG: DB_DEPTH_VIEW <- SLICE_START = 0 SLICE_MAX = 0 Z_READ_ONLY = 0 STENCIL_READ_ONLY = 0 SET_CONTEXT_REG: DB_HTILE_DATA_BASE <- 0x0004b500 SET_CONTEXT_REG: DB_DEPTH_INFO <- ADDR5_SWIZZLE_MASK = 1 ARRAY_MODE = ARRAY_2D_TILED_THIN1 PIPE_CONFIG = X_ADDR_SURF_P4_16X16 BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1 BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4 MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4 NUM_BANKS = ADDR_SURF_16_BANK DB_Z_INFO <- FORMAT = Z_24 NUM_SAMPLES = 0 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 DECOMPRESS_ON_N_ZPLANES = 0 ALLOW_EXPCLEAR = 1 READ_SIZE = 0 TILE_SURFACE_ENABLE = 1 CLEAR_DISALLOWED = 0 ZRANGE_PRECISION = 0 DB_STENCIL_INFO <- FORMAT = STENCIL_8 TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B TILE_MODE_INDEX = 0 ALLOW_EXPCLEAR = 1 TILE_STENCIL_DISABLE = 0 CLEAR_DISALLOWED = 0 DB_Z_READ_BASE <- 0x00093900 DB_STENCIL_READ_BASE <- 0x00096f00 DB_Z_WRITE_BASE <- 0x00093900 DB_STENCIL_WRITE_BASE <- 0x00096f00 DB_DEPTH_SIZE <- PITCH_TILE_MAX = 143 (0x8f) HEIGHT_TILE_MAX = 95 (0x5f) DB_DEPTH_SLICE <- SLICE_TILE_MAX = 13823 (0x035ff) SET_CONTEXT_REG: DB_STENCIL_CLEAR <- CLEAR = 0 DB_DEPTH_CLEAR <- 0 SET_CONTEXT_REG: DB_HTILE_SURFACE <- LINEAR = 0 FULL_CACHE = 1 HTILE_USES_PRELOAD_WIN = 0 PRELOAD = 0 PREFETCH_WIDTH = 0 PREFETCH_HEIGHT = 0 DST_OUTSIDE_ZERO_TO_ONE = 0 TC_COMPATIBLE = 0 SET_CONTEXT_REG: PA_SU_POLY_OFFSET_DB_FMT_CNTL <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8) POLY_OFFSET_DB_IS_FLOAT_FMT = 0 SET_CONTEXT_REG: PA_SC_WINDOW_SCISSOR_BR <- BR_X = 1080 (0x438) BR_Y = 672 (0x2a0) SET_CONTEXT_REG: DB_RENDER_CONTROL <- DEPTH_CLEAR_ENABLE = 0 STENCIL_CLEAR_ENABLE = 0 DEPTH_COPY = 0 STENCIL_COPY = 0 RESUMMARIZE_ENABLE = 0 STENCIL_COMPRESS_DISABLE = 0 DEPTH_COMPRESS_DISABLE = 1 COPY_CENTROID = 0 COPY_SAMPLE = 0 DECOMPRESS_ENABLE = 0 DB_COUNT_CONTROL <- ZPASS_INCREMENT_DISABLE = 0 PERFECT_ZPASS_COUNTS = 0 SAMPLE_RATE = 0 ZPASS_ENABLE = 0 ZFAIL_ENABLE = 0 SFAIL_ENABLE = 0 DBFAIL_ENABLE = 0 SLICE_EVEN_ENABLE = 0 SLICE_ODD_ENABLE = 0 SET_CONTEXT_REG: DB_RENDER_OVERRIDE2 <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0 DISABLE_COLOR_ON_VALIDATION = 0 DECOMPRESS_Z_ON_FLUSH = 0 DISABLE_REG_SNOOP = 0 DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0 SEPARATE_HIZS_FUNC_ENABLE = 0 HIZ_ZFUNC = 0 HIS_SFUNC_FF = 0 HIS_SFUNC_BF = 0 PRESERVE_ZRANGE = 0 PRESERVE_SRESULTS = 0 DISABLE_FAST_PASS = 0 SET_CONTEXT_REG: DB_SHADER_CONTROL <- Z_EXPORT_ENABLE = 0 STENCIL_TEST_VAL_EXPORT_ENABLE = 0 STENCIL_OP_VAL_EXPORT_ENABLE = 0 Z_ORDER = EARLY_Z_THEN_LATE_Z KILL_ENABLE = 0 COVERAGE_TO_MASK_ENABLE = 0 MASK_EXPORT_ENABLE = 0 EXEC_ON_HIER_FAIL = 0 EXEC_ON_NOOP = 0 ALPHA_TO_MASK_DISABLE = 0 DEPTH_BEFORE_SHADER = 0 CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z DUAL_QUAD_DISABLE = 0 SET_CONTEXT_REG: CB_TARGET_MASK <- TARGET0_ENABLE = 0 TARGET1_ENABLE = 0 TARGET2_ENABLE = 0 TARGET3_ENABLE = 0 TARGET4_ENABLE = 0 TARGET5_ENABLE = 0 TARGET6_ENABLE = 0 TARGET7_ENABLE = 0 SET_CONTEXT_REG: PA_CL_VS_OUT_CNTL <- CLIP_DIST_ENA_0 = 0 CLIP_DIST_ENA_1 = 0 CLIP_DIST_ENA_2 = 0 CLIP_DIST_ENA_3 = 0 CLIP_DIST_ENA_4 = 0 CLIP_DIST_ENA_5 = 0 CLIP_DIST_ENA_6 = 0 CLIP_DIST_ENA_7 = 0 CULL_DIST_ENA_0 = 0 CULL_DIST_ENA_1 = 0 CULL_DIST_ENA_2 = 0 CULL_DIST_ENA_3 = 0 CULL_DIST_ENA_4 = 0 CULL_DIST_ENA_5 = 0 CULL_DIST_ENA_6 = 0 CULL_DIST_ENA_7 = 0 USE_VTX_POINT_SIZE = 0 USE_VTX_EDGE_FLAG = 0 USE_VTX_RENDER_TARGET_INDX = 0 USE_VTX_VIEWPORT_INDX = 0 USE_VTX_KILL_FLAG = 0 VS_OUT_MISC_VEC_ENA = 0 VS_OUT_CCDIST0_VEC_ENA = 0 VS_OUT_CCDIST1_VEC_ENA = 0 VS_OUT_MISC_SIDE_BUS_ENA = 1 USE_VTX_GS_CUT_FLAG = 0 USE_VTX_LINE_WIDTH = 0 SET_CONTEXT_REG: PA_CL_CLIP_CNTL <- UCP_ENA_0 = 0 UCP_ENA_1 = 0 UCP_ENA_2 = 0 UCP_ENA_3 = 0 UCP_ENA_4 = 0 UCP_ENA_5 = 0 PS_UCP_Y_SCALE_NEG = 0 PS_UCP_MODE = 3 CLIP_DISABLE = 0 UCP_CULL_ONLY_ENA = 0 BOUNDARY_EDGE_FLAG_ENA = 0 DX_CLIP_SPACE_DEF = 0 DIS_CLIP_ERR_DETECT = 0 VTX_KILL_OR = 0 DX_RASTERIZATION_KILL = 0 DX_LINEAR_ATTR_CLIP_ENA = 1 VTE_VPORT_PROVOKE_DISABLE = 0 ZCLIP_NEAR_DISABLE = 0 ZCLIP_FAR_DISABLE = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_0 <- 18971.0f (0x46943600) SPI_SHADER_USER_DATA_VS_1 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_2 <- 18970.0f (0x46943400) SPI_SHADER_USER_DATA_VS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_2 <- 18971.5f (0x46943700) SPI_SHADER_USER_DATA_PS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_6 <- 18972.5f (0x46943900) SPI_SHADER_USER_DATA_PS_7 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_PS_4 <- 18975.0f (0x46943e00) SPI_SHADER_USER_DATA_PS_5 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_GS_2 <- 18976.0f (0x46944000) SPI_SHADER_USER_DATA_GS_3 <- 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_8 <- 18977.0f (0x46944200) SPI_SHADER_USER_DATA_VS_9 <- 0 SET_CONTEXT_REG: PA_CL_VPORT_XSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_XOFFSET <- 0 PA_CL_VPORT_YSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_YOFFSET <- 0 PA_CL_VPORT_ZSCALE <- 1.0f (0x3f800000) PA_CL_VPORT_ZOFFSET <- 0 SET_CONTEXT_REG: SPI_PS_INPUT_ENA <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SPI_PS_INPUT_ADDR <- PERSP_SAMPLE_ENA = 1 PERSP_CENTER_ENA = 0 PERSP_CENTROID_ENA = 0 PERSP_PULL_MODEL_ENA = 0 LINEAR_SAMPLE_ENA = 0 LINEAR_CENTER_ENA = 0 LINEAR_CENTROID_ENA = 0 LINE_STIPPLE_TEX_ENA = 0 POS_X_FLOAT_ENA = 0 POS_Y_FLOAT_ENA = 0 POS_Z_FLOAT_ENA = 0 POS_W_FLOAT_ENA = 0 FRONT_FACE_ENA = 0 ANCILLARY_ENA = 0 SAMPLE_COVERAGE_ENA = 0 POS_FIXED_PT_ENA = 0 SET_CONTEXT_REG: DB_ALPHA_TO_MASK <- ALPHA_TO_MASK_ENABLE = 0 ALPHA_TO_MASK_OFFSET0 = 2 ALPHA_TO_MASK_OFFSET1 = 2 ALPHA_TO_MASK_OFFSET2 = 2 ALPHA_TO_MASK_OFFSET3 = 2 OFFSET_ROUND = 0 SET_CONTEXT_REG: CB_BLEND0_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND1_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND2_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND3_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND4_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND5_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND6_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 CB_BLEND7_CONTROL <- COLOR_SRCBLEND = BLEND_ZERO COLOR_COMB_FCN = COMB_DST_PLUS_SRC COLOR_DESTBLEND = BLEND_ZERO ALPHA_SRCBLEND = BLEND_ZERO ALPHA_COMB_FCN = COMB_DST_PLUS_SRC ALPHA_DESTBLEND = BLEND_ZERO SEPARATE_ALPHA_BLEND = 0 ENABLE = 0 DISABLE_ROP3 = 0 SET_CONTEXT_REG: CB_COLOR_CONTROL <- DISABLE_DUAL_QUAD = 0 DEGAMMA_ENABLE = 0 MODE = CB_DISABLE ROP3 = X_0XCC SET_CONTEXT_REG: SPI_INTERP_CONTROL_0 <- FLAT_SHADE_ENA = 1 PNT_SPRITE_ENA = 1 PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0 PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1 PNT_SPRITE_TOP_1 = 0 SET_CONTEXT_REG: PA_SU_POINT_SIZE <- HEIGHT = 0 WIDTH = 0 PA_SU_POINT_MINMAX <- MIN_SIZE = 0 MAX_SIZE = 0 PA_SU_LINE_CNTL <- WIDTH = 0 SET_CONTEXT_REG: PA_SC_MODE_CNTL_0 <- MSAA_ENABLE = 0 VPORT_SCISSOR_ENABLE = 0 LINE_STIPPLE_ENABLE = 0 SEND_UNLIT_STILES_TO_PKR = 0 SET_CONTEXT_REG: PA_SU_VTX_CNTL <- PIX_CENTER = 1 ROUND_MODE = X_TRUNCATE QUANT_MODE = X_16_8_FIXED_POINT_1_256TH SET_CONTEXT_REG: PA_SU_POLY_OFFSET_CLAMP <- 0 SET_CONTEXT_REG: PA_SU_SC_MODE_CNTL <- CULL_FRONT = 0 CULL_BACK = 0 FACE = 1 POLY_MODE = X_DISABLE_POLY_MODE POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES POLY_OFFSET_FRONT_ENABLE = 0 POLY_OFFSET_BACK_ENABLE = 0 POLY_OFFSET_PARA_ENABLE = 0 VTX_WINDOW_OFFSET_ENABLE = 0 PROVOKING_VTX_LAST = 1 PERSP_CORR_DIS = 0 MULTI_PRIM_IB_ENA = 0 SET_SH_REG: SPI_SHADER_USER_DATA_VS_12 <- 0 SET_CONTEXT_REG: DB_DEPTH_CONTROL <- STENCIL_ENABLE = 0 Z_ENABLE = 0 Z_WRITE_ENABLE = 0 DEPTH_BOUNDS_ENABLE = 0 ZFUNC = FRAG_NEVER BACKFACE_ENABLE = 0 STENCILFUNC = REF_NEVER STENCILFUNC_BF = REF_NEVER ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0 DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0 SET_CONTEXT_REG: DB_STENCIL_CONTROL <- STENCILFAIL = STENCIL_KEEP STENCILZPASS = STENCIL_KEEP STENCILZFAIL = STENCIL_KEEP STENCILFAIL_BF = STENCIL_KEEP STENCILZPASS_BF = STENCIL_KEEP STENCILZFAIL_BF = STENCIL_KEEP SET_CONTEXT_REG: VGT_GS_MODE <- MODE = GS_OFF RESERVED_0 = 0 CUT_MODE = GS_CUT_1024 RESERVED_1 = 0 GS_C_PACK_EN = 0 RESERVED_2 = 0 ES_PASSTHRU = 0 COMPUTE_MODE = 0 FAST_COMPUTE_MODE = 0 ELEMENT_INFO_EN = 0 PARTIAL_THD_AT_EOI = 0 SUPPRESS_CUTS = 0 ES_WRITE_OPTIMIZE = 0 GS_WRITE_OPTIMIZE = 0 ONCHIP = X_0_OFFCHIP_GS SET_CONTEXT_REG: VGT_PRIMITIVEID_EN <- PRIMITIVEID_EN = 0 DISABLE_RESET_ON_EOI = 0 SET_CONTEXT_REG: SPI_VS_OUT_CONFIG <- VS_EXPORT_COUNT = 0 VS_HALF_PACK = 0 VS_EXPORTS_FOG = 0 VS_OUT_FOG_VEC_ADDR = 0 SET_CONTEXT_REG: SPI_SHADER_POS_FORMAT <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP POS1_EXPORT_FORMAT = SPI_SHADER_NONE POS2_EXPORT_FORMAT = SPI_SHADER_NONE POS3_EXPORT_FORMAT = SPI_SHADER_NONE SET_SH_REG: SPI_SHADER_PGM_LO_VS <- 0x0005a130 SPI_SHADER_PGM_HI_VS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_VS <- VGPRS = 2 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 VGPR_COMP_CNT = 0 CU_GROUP_ENABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_VS <- SCRATCH_EN = 0 USER_SGPR = 13 (0xd) TRAP_PRESENT = 0 OC_LDS_EN = 0 SO_BASE0_EN = 0 SO_BASE1_EN = 0 SO_BASE2_EN = 0 SO_BASE3_EN = 0 SO_EN = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DISPATCH_DRAW_EN = 0 SET_CONTEXT_REG: PA_CL_VTE_CNTL <- VPORT_X_SCALE_ENA = 1 VPORT_X_OFFSET_ENA = 1 VPORT_Y_SCALE_ENA = 1 VPORT_Y_OFFSET_ENA = 1 VPORT_Z_SCALE_ENA = 1 VPORT_Z_OFFSET_ENA = 1 VTX_XY_FMT = 0 VTX_Z_FMT = 0 VTX_W0_FMT = 1 SET_CONTEXT_REG: SPI_BARYC_CNTL <- PERSP_CENTER_CNTL = 0 PERSP_CENTROID_CNTL = 0 LINEAR_CENTER_CNTL = 0 LINEAR_CENTROID_CNTL = 0 POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT POS_FLOAT_ULC = 0 FRONT_FACE_ALL_BITS = 0 SET_CONTEXT_REG: SPI_PS_IN_CONTROL <- NUM_INTERP = 0 PARAM_GEN = 0 FOG_ADDR = 0 BC_OPTIMIZE_DISABLE = 0 PASS_FOG_THROUGH_PS = 0 SET_CONTEXT_REG: SPI_SHADER_Z_FORMAT <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO SPI_SHADER_COL_FORMAT <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO COL1_EXPORT_FORMAT = SPI_SHADER_ZERO COL2_EXPORT_FORMAT = SPI_SHADER_ZERO COL3_EXPORT_FORMAT = SPI_SHADER_ZERO COL4_EXPORT_FORMAT = SPI_SHADER_ZERO COL5_EXPORT_FORMAT = SPI_SHADER_ZERO COL6_EXPORT_FORMAT = SPI_SHADER_ZERO COL7_EXPORT_FORMAT = SPI_SHADER_ZERO SET_CONTEXT_REG: CB_SHADER_MASK <- OUTPUT0_ENABLE = 0 OUTPUT1_ENABLE = 0 OUTPUT2_ENABLE = 0 OUTPUT3_ENABLE = 0 OUTPUT4_ENABLE = 0 OUTPUT5_ENABLE = 0 OUTPUT6_ENABLE = 0 OUTPUT7_ENABLE = 0 SET_SH_REG: SPI_SHADER_PGM_LO_PS <- 0x00053ff0 SPI_SHADER_PGM_HI_PS <- MEM_BASE = 0 SPI_SHADER_PGM_RSRC1_PS <- VGPRS = 0 SGPRS = 1 PRIORITY = 0 FLOAT_MODE = 0 PRIV = 0 DX10_CLAMP = 1 DEBUG_MODE = 0 IEEE_MODE = 0 CU_GROUP_DISABLE = 0 CACHE_CTL = 0 CDBG_USER = 0 SPI_SHADER_PGM_RSRC2_PS <- SCRATCH_EN = 0 USER_SGPR = 10 (0xa) TRAP_PRESENT = 0 WAVE_CNT_EN = 0 EXTRA_LDS_SIZE = 0 EXCP_EN = 0 EXCP_EN_CIK = 0 DRAW_PREAMBLE: VGT_PRIMITIVE_TYPE <- PRIM_TYPE = DI_PT_RECTLIST IA_MULTI_VGT_PARAM <- PRIMGROUP_SIZE = 127 (0x007f) PARTIAL_VS_WAVE_ON = 0 SWITCH_ON_EOP = 0 PARTIAL_ES_WAVE_ON = 0 SWITCH_ON_EOI = 0 WD_SWITCH_ON_EOP = 1 MAX_PRIMGRP_IN_WAVE = 0 VGT_LS_HS_CONFIG <- NUM_PATCHES = 0 HS_NUM_INPUT_CP = 0 HS_NUM_OUTPUT_CP = 0 NUM_INSTANCES: VGT_NUM_INSTANCES <- 1 DRAW_INDEX_AUTO: VGT_NUM_INDICES <- 3 VGT_DRAW_INITIATOR <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX MAJOR_MODE = DI_MAJOR_MODE_0 NOT_EOP = 0 USE_OPAQUE = 0 WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x00000049 NOP: Trace point ID: 73 This trace point was reached by the CP. EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_CB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = FLUSH_AND_INV_DB_META EVENT_INDEX <- 0 INV_L2 <- 0 EVENT_WRITE: VGT_EVENT_INITIATOR <- EVENT_TYPE = PS_PARTIAL_FLUSH EVENT_INDEX <- 4 INV_L2 <- 0 ACQUIRE_MEM: CP_COHER_CNTL <- DEST_BASE_0_ENA = 0 DEST_BASE_1_ENA = 0 TC_SD_ACTION_ENA = 0 TC_NC_ACTION_ENA = 0 CB0_DEST_BASE_ENA = 1 CB1_DEST_BASE_ENA = 1 CB2_DEST_BASE_ENA = 1 CB3_DEST_BASE_ENA = 1 CB4_DEST_BASE_ENA = 1 CB5_DEST_BASE_ENA = 1 CB6_DEST_BASE_ENA = 1 CB7_DEST_BASE_ENA = 1 DB_DEST_BASE_ENA = 1 TCL1_VOL_ACTION_ENA = 0 TC_VOL_ACTION_ENA = 0 TC_WB_ACTION_ENA = 0 DEST_BASE_2_ENA = 0 DEST_BASE_3_ENA = 0 TCL1_ACTION_ENA = 1 TC_ACTION_ENA = 1 CB_ACTION_ENA = 1 DB_ACTION_ENA = 1 SH_KCACHE_ACTION_ENA = 0 SH_KCACHE_VOL_ACTION_ENA = 0 SH_ICACHE_ACTION_ENA = 0 SH_KCACHE_WB_ACTION_ENA = 0 SH_SD_ACTION_ENA = 0 CP_COHER_SIZE <- 0xffffffff CP_COHER_SIZE_HI <- COHER_SIZE_HI_256B = 255 (0xff) CP_COHER_BASE <- 0 CP_COHER_BASE_HI <- COHER_BASE_HI_256B = 0 POLL_INTERVAL <- 10 (0x000a) WRITE_DATA: CONTROL <- ENGINE_SEL = ME WR_CONFIRM = 1 WR_ONE_ADDR = 0 DST_SEL = MEMORY_SYNC DST_ADDR_LO <- 0x41aee000 DST_ADDR_HI <- 0 0x0000004a NOP: Trace point ID: 74 !!!!! This is the last trace point that was reached by the CP !!!!! ------------------- IB end -------------------