From 186837318a2b63531dfe625850feda2caf9cf22c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Thu, 7 Jan 2016 17:27:38 +0900 Subject: [PATCH] drm/radeon: Always use indirect access for CRTC(2)_GEN_CNTL registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- drivers/gpu/drm/radeon/r100.c | 32 +++++++++++----------- drivers/gpu/drm/radeon/radeon_bios.c | 22 ++++++++-------- drivers/gpu/drm/radeon/radeon_device.c | 4 +-- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 35 ++++++++++++++----------- drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 26 +++++++++--------- 5 files changed, 61 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 238b13f..711256d 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -116,10 +116,10 @@ void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) return; if (crtc == 0) { - if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) + if (!(RREG32_IDX(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) return; } else { - if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) + if (!(RREG32_IDX(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) return; } @@ -452,13 +452,13 @@ void r100_pm_prepare(struct radeon_device *rdev) radeon_crtc = to_radeon_crtc(crtc); if (radeon_crtc->enabled) { if (radeon_crtc->crtc_id) { - tmp = RREG32(RADEON_CRTC2_GEN_CNTL); + tmp = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); tmp |= RADEON_CRTC2_DISP_REQ_EN_B; - WREG32(RADEON_CRTC2_GEN_CNTL, tmp); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, tmp); } else { - tmp = RREG32(RADEON_CRTC_GEN_CNTL); + tmp = RREG32_IDX(RADEON_CRTC_GEN_CNTL); tmp |= RADEON_CRTC_DISP_REQ_EN_B; - WREG32(RADEON_CRTC_GEN_CNTL, tmp); + WREG32_IDX(RADEON_CRTC_GEN_CNTL, tmp); } } } @@ -483,13 +483,13 @@ void r100_pm_finish(struct radeon_device *rdev) radeon_crtc = to_radeon_crtc(crtc); if (radeon_crtc->enabled) { if (radeon_crtc->crtc_id) { - tmp = RREG32(RADEON_CRTC2_GEN_CNTL); + tmp = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; - WREG32(RADEON_CRTC2_GEN_CNTL, tmp); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, tmp); } else { - tmp = RREG32(RADEON_CRTC_GEN_CNTL); + tmp = RREG32_IDX(RADEON_CRTC_GEN_CNTL); tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; - WREG32(RADEON_CRTC_GEN_CNTL, tmp); + WREG32_IDX(RADEON_CRTC_GEN_CNTL, tmp); } } } @@ -2850,7 +2850,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev) { if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { (void)RREG32(RADEON_CLOCK_CNTL_DATA); - (void)RREG32(RADEON_CRTC_GEN_CNTL); + (void)RREG32_IDX(RADEON_CRTC_GEN_CNTL); } } @@ -3758,10 +3758,10 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) /* Save few CRTC registers */ save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); - save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); + save->CRTC_GEN_CNTL = RREG32_IDX(R_000050_CRTC_GEN_CNTL); save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { - save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); + save->CRTC2_GEN_CNTL = RREG32_IDX(R_0003F8_CRTC2_GEN_CNTL); save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); } @@ -3771,7 +3771,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | S_000054_CRTC_DISPLAY_DIS(1)); - WREG32(R_000050_CRTC_GEN_CNTL, + WREG32_IDX(R_000050_CRTC_GEN_CNTL, (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | S_000050_CRTC_DISP_REQ_EN_B(1)); WREG32(R_000420_OV0_SCALE_CNTL, @@ -3780,7 +3780,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) if (!(rdev->flags & RADEON_SINGLE_CRTC)) { WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | S_000360_CUR2_LOCK(1)); - WREG32(R_0003F8_CRTC2_GEN_CNTL, + WREG32_IDX(R_0003F8_CRTC2_GEN_CNTL, (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | S_0003F8_CRTC2_DISPLAY_DIS(1) | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); @@ -3799,7 +3799,7 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) /* Restore CRTC registers */ WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); - WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); + WREG32_IDX(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); } diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index 21b6732..f45e2b0 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c @@ -511,7 +511,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) bus_cntl = RREG32(RV370_BUS_CNTL); else bus_cntl = RREG32(RADEON_BUS_CNTL); - crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC_GEN_CNTL); crtc2_gen_cntl = 0; crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); fp2_gen_cntl = 0; @@ -521,7 +521,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) } if (!(rdev->flags & RADEON_SINGLE_CRTC)) { - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); } WREG32(RADEON_SEPROM_CNTL1, @@ -538,14 +538,14 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); /* Turn off mem requests and CRTC for both controllers */ - WREG32(RADEON_CRTC_GEN_CNTL, - ((crtc_gen_cntl & ~RADEON_CRTC_EN) | - (RADEON_CRTC_DISP_REQ_EN_B | - RADEON_CRTC_EXT_DISP_EN))); + WREG32_IDX(RADEON_CRTC_GEN_CNTL, + ((crtc_gen_cntl & ~RADEON_CRTC_EN) | + (RADEON_CRTC_DISP_REQ_EN_B | + RADEON_CRTC_EXT_DISP_EN))); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { - WREG32(RADEON_CRTC2_GEN_CNTL, - ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | - RADEON_CRTC2_DISP_REQ_EN_B)); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, + ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | + RADEON_CRTC2_DISP_REQ_EN_B)); } /* Turn off CRTC */ WREG32(RADEON_CRTC_EXT_CNTL, @@ -566,9 +566,9 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev) WREG32(RV370_BUS_CNTL, bus_cntl); else WREG32(RADEON_BUS_CNTL, bus_cntl); - WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); + WREG32_IDX(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); } WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c566993..ec5b071 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -673,8 +673,8 @@ bool radeon_card_posted(struct radeon_device *rdev) return true; } } else { - reg = RREG32(RADEON_CRTC_GEN_CNTL) | - RREG32(RADEON_CRTC2_GEN_CNTL); + reg = RREG32_IDX(RADEON_CRTC_GEN_CNTL) | + RREG32_IDX(RADEON_CRTC2_GEN_CNTL); if (reg & RADEON_CRTC_EN) { return true; } diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 4259e27..a95eb99 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -296,6 +296,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; uint32_t crtc_ext_cntl = 0; + uint32_t crtc_gen_cntl; uint32_t mask; if (radeon_crtc->crtc_id) @@ -323,11 +324,12 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) radeon_crtc->enabled = true; /* adjust pm to dpms changes BEFORE enabling crtcs */ radeon_pm_compute_clocks(rdev); - if (radeon_crtc->crtc_id) - WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); - else { - WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | - RADEON_CRTC_DISP_REQ_EN_B)); + if (radeon_crtc->crtc_id) { + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL) & ~mask; + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl | RADEON_CRTC2_EN); + } else { + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC_GEN_CNTL) & ~RADEON_CRTC_DISP_REQ_EN_B; + WREG32_IDX(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl | RADEON_CRTC_EN); WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); } drm_vblank_on(dev, radeon_crtc->crtc_id); @@ -337,11 +339,12 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: drm_vblank_off(dev, radeon_crtc->crtc_id); - if (radeon_crtc->crtc_id) - WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); - else { - WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | - RADEON_CRTC_DISP_REQ_EN_B)); + if (radeon_crtc->crtc_id) { + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL) & ~RADEON_CRTC2_EN; + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl | mask); + } else { + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC_GEN_CNTL) & ~RADEON_CRTC_EN; + WREG32_IDX(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl | RADEON_CRTC_DISP_REQ_EN_B); WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); } radeon_crtc->enabled = false; @@ -535,11 +538,11 @@ retry: else gen_cntl_reg = RADEON_CRTC_GEN_CNTL; - gen_cntl_val = RREG32(gen_cntl_reg); + gen_cntl_val = RREG32_IDX(gen_cntl_reg); gen_cntl_val &= ~(0xf << 8); gen_cntl_val |= (format << 8); gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; - WREG32(gen_cntl_reg, gen_cntl_val); + WREG32_IDX(gen_cntl_reg, gen_cntl_val); crtc_offset = (u32)base; @@ -652,7 +655,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod uint32_t disp2_merge_cntl; /* if TV DAC is enabled for another crtc and keep it enabled */ - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL) & 0x00718080; crtc2_gen_cntl |= ((format << 8) | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS @@ -676,7 +679,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); @@ -685,7 +688,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod uint32_t crtc_ext_cntl; uint32_t disp_merge_cntl; - crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; + crtc_gen_cntl = RREG32_IDX(RADEON_CRTC_GEN_CNTL) & 0x00718000; crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN | (format << 8) | RADEON_CRTC_DISP_REQ_EN_B @@ -713,7 +716,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); - WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); + WREG32_IDX(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); } diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 30de433..1d8b1c6 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -1046,7 +1046,7 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (is_tv) tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); else - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); } @@ -1108,7 +1108,7 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); /* handled in radeon_crtc_dpms() */ else if (!(rdev->flags & RADEON_SINGLE_CRTC)) - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); } @@ -1308,7 +1308,7 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, /* save regs needed */ gpiopad_a = RREG32(RADEON_GPIOPAD_A); dac_cntl2 = RREG32(RADEON_DAC_CNTL2); - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); @@ -1317,8 +1317,8 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); - WREG32(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, + RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; @@ -1360,7 +1360,7 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32(RADEON_DAC_CNTL2, dac_cntl2); WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); @@ -1448,7 +1448,7 @@ static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, gpio_monid = RREG32(RADEON_GPIO_MONID); fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); @@ -1473,8 +1473,8 @@ static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | RADEON_DISP_TRANS_MATRIX_GRAPHICS)); - WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | - RADEON_CRTC2_DISP_REQ_EN_B)); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | + RADEON_CRTC2_DISP_REQ_EN_B)); WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); @@ -1513,7 +1513,7 @@ static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32(RADEON_GPIO_MONID, gpio_monid); @@ -1584,7 +1584,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder } else { disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); } - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + crtc2_gen_cntl = RREG32_IDX(RADEON_CRTC2_GEN_CNTL); } tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); @@ -1601,7 +1601,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; tmp |= RADEON_CRTC2_CRT2_ON | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); - WREG32(RADEON_CRTC2_GEN_CNTL, tmp); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, tmp); if (ASIC_IS_R300(rdev)) { WREG32_P(RADEON_GPIOPAD_A, 1, ~1); @@ -1657,7 +1657,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder if (rdev->flags & RADEON_SINGLE_CRTC) { WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); } else { - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32_IDX(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); if (ASIC_IS_R300(rdev)) { WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); -- 2.6.2