commit 01c99f94a5bc52f3a031ad194bf453a105835d37
Author: Imre Deak <imre.deak@intel.com>
Date:   Tue Nov 25 17:36:21 2014 +0800

    x86/bxt/tsc: HACK: hard code system bus frequency to 100MHz
    
    Add Broxton CPU, model IDs. Since reading the freuquency ID MSR register
    causes a general protection fault on my A1, hard-code the system bus
    (SA) frequency to 100MHz, which seems to be fixed for Broxton. Also mark
    TSC as a "reliable" clock source, so it's selected as the system clock
    source.
    
    Signed-off-by: Imre Deak <imre.deak@intel.com>

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 92ae6ac..1008689 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -56,6 +56,8 @@ static struct freq_desc freq_desc_tables[] = {
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+	/* BXT */
+	{ 6, 0x5c, 1, { /* no freq ID on this platform */ } },
 };
 
 static int match_cpu(u8 family, u8 model)
@@ -102,10 +104,21 @@ unsigned long try_msr_calibrate_tsc(void)
 	if (!ratio)
 		goto fail;
 
-	/* Get FSB FREQ ID */
-	rdmsr(MSR_FSB_FREQ, lo, hi);
-	freq_id = lo & 0x7;
-	freq = id_to_freq(cpu_index, freq_id);
+	/*
+	 * On BXT A1 reading the MSR_FSB_FREQ causes a general protection
+	 * fault. Hard-code the frequency 100Mhz which is the SA clock
+	 * frequency.
+	 */
+	if (boot_cpu_data.x86 == 0x6 && boot_cpu_data.x86_model == 0x5c) {
+		freq_id = 0;
+		freq = 100000;
+		set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
+	} else {
+		/* Get FSB FREQ ID */
+		rdmsr(MSR_FSB_FREQ, lo, hi);
+		freq_id = lo & 0x7;
+		freq = id_to_freq(cpu_index, freq_id);
+	}
 	pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
 				freq_id, freq);
 	if (!freq)