From 6095f67ece6ace8f2f9025cc5f96216a8aed1588 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 25 Jan 2016 17:53:23 -0800 Subject: [PATCH] i965/skl: Address DS errata The docs say we need to have the start GRF be 6 in the conditions listed. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_fs.cpp | 8 ++++++++ src/mesa/drivers/dri/i965/gen8_ds_state.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index cbeab6f..9ddba9a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -5250,6 +5250,14 @@ fs_visitor::run_tes() /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */ payload.num_regs = 5; + /* From 3DSTATE_DS definition: + * "When SIMD8_SINGLE_OR_DUAL_PATCH dispatch mode is selected, SW shall + * program this field to a value of 6 or greater to accommodate either + * the DUAL_PATCH or SIMD8_SINGLE_PATCH payloads." + */ + if (devinfo->gen >= 9) + payload.num_regs = 6; + if (shader_time_index >= 0) emit_shader_time_begin(); diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c index 9f2db33..16f77c2 100644 --- a/src/mesa/drivers/dri/i965/gen8_ds_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c @@ -39,6 +39,9 @@ gen8_upload_ds_state(struct brw_context *brw) const struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base; const struct brw_stage_prog_data *prog_data = &vue_prog_data->base; + /* Gen9 constrains the first GRF used in certain evaluation modes. */ + assert(brw->gen < 9 || !active || prog_data->dispatch_grf_start_reg >= 6); + if (active) { BEGIN_BATCH(brw->gen >= 9 ? 11 : 9); OUT_BATCH(_3DSTATE_DS << 16 | (9 - 2)); -- 2.7.0